8000 unsufficient parse for large scale verilog design · Issue #118 · PyHDI/Pyverilog · GitHub

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unsufficient parse for large scale verilog design #118

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ZhaoYunfei123 opened this issue Mar 14, 2023 · 0 comments

ZhaoYunfei123 commented

I'm tring to use pyverilog to parse one large scale design, but the ast.show() can't display all module's AST. How can I get all module's AST ?

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