RISCVNexus
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picorv32
picorv32 PublicForked from YosysHQ/picorv32
PicoRV32 - A Size-Optimized RISC-V CPU
Verilog 1
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ibex
ibex PublicForked from lowRISC/ibex
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
SystemVerilog 1
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Repositories
- ibex Public Forked from lowRISC/ibex
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
RISCVNexus/ibex’s past year of commit activity - scr1 Public Forked from syntacore/scr1
SCR1 is a high-quality open-source RISC-V MCU core in Verilog
RISCVNexus/scr1’s past year of commit activity - RISC-V-Single-Cycle-CPU Public Forked from T-K-233/RISC-V-Single-Cycle-CPU
RISC-V 32bit single-cycle CPUs written in Logisim, Verilog, and Chisel
RISCVNexus/RISC-V-Single-Cycle-CPU’s past year of commit activity
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