8000 `fsm.delayed_enter` incompatible with vcd dump · Issue #305 · m-labs/migen · GitHub
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enurseitov opened this issue Apr 15, 2025 · 1 comment
Open

fsm.delayed_enter incompatible with vcd dump #305

enurseitov opened this issue Apr 15, 2025 · 1 comment

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@enurseitov
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enurseitov commented Apr 15, 2025 •
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when trying to simulate an FSM containing delayed_enter with vcd_name provided, saving of VCD fails because of 'AnonymousState' object has no attribute 'encode' and object of type 'AnonymousState' has no len().

Example:

from migen import *
from migen.fhdl import verilog

class ToggleFSM(Module):
    def __init__(self):

        self.test_out = Signal()         

        self.submodules.fsm = fsm = FSM(reset_state="STATE_A")
        
        fsm.act("STATE_A",
            NextState("STATE_B")
        )

        fsm.act("STATE_B",
            self.test_out.eq(1),
        )        

        fsm.delayed_enter("STATE_B", "STATE_A", 3)

if __name__ == "__main__":
    dut = ToggleFSM()
    
    def testbench():
        for i in range(10):
            state = yield dut.fsm.state
            test_out = yield dut.test_out
            print(f"Cycle {i}: State = {state}, test_out = {test_out}")
            yield
            
    # print(verilog.convert(dut, ios={dut.test_out}))
    run_simulation(dut, testbench(), vcd_name="toggle_fsm.vcd")
    # run_simulation(dut, testbench())

This fails with:

Traceback (most recent call last):
  File "prjdir/.venv/lib64/python3.13/site-packages/migen/sim/core.py", line 414, in run_simulation
    s.run()
    ~~~~~^^
  File "prjdir/.venv/lib64/python3.13/site-packages/migen/sim/core.py", line 406, in run
    self._commit_and_comb_propagate()
    ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^^
  File "prjdir/.venv/lib64/python3.13/site-packages/migen/sim/core.py", line 338, in _commit_and_comb_propagate
    self.vcd.set(signal, self.evaluator.signal_values[signal])
    ~~~~~~~~~~~~^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
  File "prjdir/.venv/lib64/python3.13/site-packages/migen/sim/vcd.py", line 66, in set
    self._write_value(self.buffer_file, signal, value)
    ~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
  File "prjdir/.venv/lib64/python3.13/site-packages/migen/sim/vcd.py", line 60, in _write_value
    self._write_enum_value(self.buffer_file, signal, value)
    ~~~~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
  File "prjdir/.venv/lib64/python3.13/site-packages/migen/sim/vcd.py", line 53, in _write_enum_value
    for c in signal._enumeration[value].encode():
             ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
AttributeError: 'AnonymousState' object has no attribute 'encode'

During handling of the above exception, another exception occurred:

Traceback (most recent call last):
  File "prjdir/test.py", line 36, in <module>
    run_simulation(dut, testbench(), vcd_name="toggle_fsm.vcd")
    ~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
  File "prjdir/.venv/lib64/python3.13/site-packages/migen/sim/core.py", line 413, in run_simulation
    with Simulator(*args, **kwargs) as s:
         ~~~~~~~~~^^^^^^^^^^^^^^^^^
  File "prjdir/.venv/lib64/python3.13/site-packages/migen/sim/core.py", line 323, in __exit__
    self.close()
    ~~~~~~~~~~^^
  File "prjdir/.venv/lib64/python3.13/site-packages/migen/sim/core.py", line 326, in close
    self.vcd.close()
    ~~~~~~~~~~~~~~^^
  File "prjdir/.venv/lib64/python3.13/site-packages/migen/sim/vcd.py", line 82, in close
    size = max([len(v) for v in signal._enumeration.values()])*8
                ~~~^^^
TypeError: object of type 'AnonymousState' has no len()
@enurseitov
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Seem to be related to #267

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