8000 Invalid verilog representation · Issue #308 · m-labs/migen · GitHub
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Invalid verilog representation #308

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ollie-etl opened this issue May 6, 2025 · 0 comments
Open

Invalid verilog representation #308

ollie-etl opened this issue May 6, 2025 · 0 comments

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@ollie-etl
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I've been looking at a litex JESD204b core, and trying to simulate the resultant code in xsim.

https://github.com/enjoy-digital/litejesd204b/blob/68c63709648e4b533a0f8154a79e06e98ac4fd4d/litejesd204b/link.py#L298-L311

It appears that migen is generating verilog of the following form for this constant

reg [31:0] a = 32'0;

// ...
always@(*) begin
   a <= 32'b0
  a[7:0]  <= 8'd8
end

This is invalid, as always @(*) is not evaluated at time zero (unlike vhdl), and there are no inputs in the list to cause an event. This means the content of the always block never executes.

The question is, is this expected behaviour, with a known workaround, or a bug in the backend of migen?
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