8000 Example of using SoC host program and SoC on FPGA failed · Issue #1 · aignacio/riscv_verilator_model · GitHub
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Example of using SoC host program and SoC on FPGA failed #1
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@zmh403

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@zmh403

Hi, when I ran the flow I got the error message in both case.
I have checked the software requirements and version, then I used "$make check" to ensure that I don't miss any requirements.
Here are my running environment and the version of tools which installed through apt-get.
OS: Ubuntu 18.04
Verilator 3.916 2017-11-25 rev verilator_3_914-65-g0478dbd
g++ (Ubuntu 8.4.0-1ubuntu1~18.04) 8.4.0

(1). $ make EN_VCD=1 all WAVEFORM_VCD=output_verilator/dumpfile.vcd
/usr/share/verilator/include/verilated.cpp:1725:6: error: no declaration matches ‘void VerilatedAssertOneThread::fatal_different()’
void VerilatedAssertOneThread::fatal_different() VL_MT_SAFE {

(2). $ make fpga FPGA_BOARD=artix_a35
Building output_temp/vector.o
riscv32-unknown-elf-gcc -march=rv32im -mabi=ilp32 -Wall -Wno-unused -ffreestanding -O0 -g --specs=nano.specs -Wall -Wno-main -save-temps=obj -DVERILATOR=0 -I../common/API/inc -I../common/base -c init/vector.S -o output_temp/vector.o
riscv32-unknown-elf-gcc: error: nano.specs: No such file or directory

The riscv32-unknown-elf-gcc is the riscv toolchain I installed from the link

How cloud I pass the both flow??
, Thank you.

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