8000 axi_logic_analyzer: Optimize the input data path · analogdevicesinc/hdl@47fa86c · GitHub
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AndreiGrozavAndreiGrozav
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axi_logic_analyzer: Optimize the input data path
The input data path has a delay section that compensates for the ADC path delay. By using a Dynamic Shift Registers coding style we can improve/change the resource utilization on m2k: Before After Resources LUT 10097 10048 48 (0.28%) LUTRAM 516 540 -24 (-0.4%) FF 15285 14803 482 (1.37%)
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‎library/axi_logic_analyzer/axi_logic_analyzer.v

Lines changed: 26 additions & 89 deletions
Original file line numberDiff line numberDiff line change
@@ -125,42 +125,11 @@ module axi_logic_analyzer (
125125
reg [ 1:0] high_level_trigger = 1'd0;
126126
reg [ 1:0] low_level_trigger = 1'd0;
127127

128-
reg [15:0] adc_data_mn = 'd0;
129-
reg [31:0] trigger_holdoff_counter = 32'd0;
130-
reg [ 4:0] adc_data_delay = 5'd0;
131-
132-
reg [15:0] data_m_0;
133-
reg [15:0] data_m_1;
134-
reg [15:0] data_m_2;
135-
reg [15:0] data_m_3;
136-
reg [15:0] data_m_4;
137-
reg [15:0] data_m_5;
138-
reg [15:0] data_m_6;
139-
reg [15:0] data_m_7;
140-
reg [15:0] data_m_8;
141-
reg [15:0] data_m_9;
142-
reg [15:0] data_m_10;
143-
reg [15:0] data_m_11;
144-
reg [15:0] data_m_12;
145-
reg [15:0] data_m_13;
146-
reg [15:0] data_m_14;
147-
reg [15:0] data_m_15;
148-
reg [15:0] data_m_16;
149-
reg [15:0] data_m_17;
150-
reg [15:0] data_m_18;
151-
reg [15:0] data_m_19;
152-
reg [15:0] data_m_20;
153-
reg [15:0] data_m_21;
154-
reg [15:0] data_m_22;
155-
reg [15:0] data_m_23;
156-
reg [15:0] data_m_24;
157-
reg [15:0] data_m_25;
158-
reg [15:0] data_m_26;
159-
reg [15:0] data_m_27;
160-
reg [15:0] data_m_28;
161-
reg [15:0] data_m_29;
162-
reg [15:0] data_m_30;
163-
reg [15:0] data_m_31;
128+
reg [31:0] trigger_holdoff_counter = 32'd0;
129+
reg [ 4:0] adc_data_delay = 5'd0;
130+
131+
reg [16:0] data_fixed_delay [0:15];
132+
reg [15:0] data_dynamic_delay [0:15];
164133

165134
// internal signals
166135

@@ -218,6 +187,7 @@ module axi_logic_analyzer (
218187
wire [ 4:0] up_data_delay;
219188
wire master_delay_ctrl;
220189
wire [ 9:0] data_delay_control;
190+
wire [15:0] adc_data_mn;
221191

222192
genvar i;
223193

@@ -294,43 +264,29 @@ module axi_logic_analyzer (
294264
// - synchronization
295265
// - compensate for m2k adc path delay
296266

297-
always @(posedge clk_out) begin
298-
data_m_0 <= data_i;
299-
data_m_1 <= data_m_0;
300-
data_m_2 <= data_m_1;
301-
data_m_3 <= data_m_2;
302-
data_m_4 <= data_m_3;
303-
data_m_5 <= data_m_4;
304-
data_m_6 <= data_m_5;
305-
data_m_7 <= data_m_6;
306-
data_m_8 <= data_m_7;
307-
data_m_9 <= data_m_8;
308-
data_m_10 <= data_m_9;
309-
data_m_11 <= data_m_10;
310-
data_m_12 <= data_m_11;
311-
data_m_13 <= data_m_12;
312-
data_m_14 <= data_m_13;
313-
data_m_15 <= data_m_14;
314-
data_m_16 <= data_m_15;
315-
if (sample_valid_la == 1'b1) begin
316-
data_m_17 <= data_m_16;
317-
data_m_18 <= data_m_17;
318-
data_m_19 <= data_m_18;
319-
data_m_20 <= data_m_19;
320-
data_m_21 <= data_m_20;
321-
data_m_22 <= data_m_21;
322-
data_m_23 <= data_m_22;
323-
data_m_24 <= data_m_23;
324-
data_m_25 <= data_m_24;
325-
data_m_26 <= data_m_25;
326-
data_m_27 <= data_m_26;
327-
data_m_28 <= data_m_27;
328-
data_m_29 <= data_m_28;
329-
data_m_30 <= data_m_29;
330-
data_m_31 <= data_m_30;
267+
// 17 clock cycles delay
268+
generate
269+
for (i = 0 ; i < 16; i = i + 1) begin
270+
always @(posedge clk_out) begin
271+
if (reset == 1'b1) begin
272+
data_fixed_delay[i] <= 'd0;
273+
end else begin
274+
data_fixed_delay[i] <= {data_fixed_delay[i][15:0], data_i[i]};
275+
end
331276
end
332277
end
333278

279+
// dynamic sample delay (1 to 16)
280+
for (i = 0 ; i < 16; i = i + 1) begin
281+
always @(posedge clk_out) begin
282+
if (sample_valid_la == 1'b1) begin
283+
data_dynamic_delay[i] <= {data_dynamic_delay[i][14:0], data_fixed_delay[i][16]};
284+
end
285+
end
286+
assign adc_data_mn[i] = data_dynamic_delay[i][in_data_delay[3:0]];
287+
end
288+
endgenerate
289+
334290
// adc path 'rate delay' given by axi_adc_decimate
335291
always @(po B421 sedge clk_out) begin
336292
case (external_rate)
@@ -350,25 +306,6 @@ module axi_logic_analyzer (
350306

351307
always @(posedge clk_out) begin
352308
if (sample_valid_la == 1'b1) begin
353-
case (in_data_delay)
354-
5'd0: adc_data_mn <= data_m_16;
355-
5'd1: adc_data_mn <= data_m_17;
356-
5'd2: adc_data_mn <= data_m_18;
357-
5'd3: adc_data_mn <= data_m_19;
358-
5'd4: adc_data_mn <= data_m_20;
359-
5'd5: adc_data_mn <= data_m_21;
360-
5'd6: adc_data_mn <= data_m_22;
361-
5'd7: adc_data_mn <= data_m_23;
362-
5'd8: adc_data_mn <= data_m_24;
363-
5'd9: adc_data_mn <= data_m_25;
364-
5'd10: adc_data_mn <= data_m_26;
365-
5'd11: adc_data_mn <= data_m_27;
366-
5'd12: adc_data_mn <= data_m_28;
367-
5'd13: adc_data_mn <= data_m_29;
368-
5'd14: adc_data_mn <= data_m_30;
369-
5'd15: adc_data_mn <= data_m_31;
370-
default: adc_data_mn <= data_m_16;
371-
endcase
372309
adc_data <= adc_data_mn;
373310
end
374311
end

‎library/axi_logic_analyzer/axi_logic_analyzer_constr.xdc

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1,12 +1,10 @@
11
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *up_triggered_d*}]
22
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *up_triggered_reset_d*}]
3-
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *data_m*}]
4-
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *up_sync_ack_m*}]
3+
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *data_fixed_delay*}]
54

65
set_false_path -to [get_pins BUFGMUX_CTRL_inst/S*]
76

87
set_false_path -to [get_cells -hier -filter {name =~ *up_triggered_d1* && IS_SEQUENTIAL}]
98
set_false_path -to [get_cells -hier -filter {name =~ *up_triggered_reset_d1* && IS_SEQUENTIAL}]
10-
set_false_path -to [get_cells -hier -filter {name =~ *data_m* && IS_SEQUENTIAL}]
11-
set_false_path -to [get_cells -hier -filter {name =~ *up_sync_ack_m* && IS_SEQUENTIAL}]
9+
set_false_path -to [get_cells -hier -filter {name =~ *data_fixed_delay* && IS_SEQUENTIAL}]
1210

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