8000 axi_dac_interpolate: Add last sample support · analogdevicesinc/hdl@4f4a420 · GitHub
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AndreiGrozavAndreiGrozav
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axi_dac_interpolate: Add last sample support
This feature will allow the user to hold(indefinitely) the last sample, from an ongoing DMA transfer, simple or cyclic(stooped by user or trigger). This commit also adds as functionality option: -synchronized stop between the two channels(DMAs) -stop by trigger
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3 files changed

+66
-5
lines changed

3 files changed

+66
-5
lines changed

‎library/axi_dac_interpolate/axi_dac_interpolate.v

Lines changed: 26 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -56,6 +56,9 @@ module axi_dac_interpolate #(
5656
input dac_enable_b,
5757
output [15:0] dac_int_data_a,
5858
output [15:0] dac_int_data_b,
59+
output dac_valid_out_a,
60+
output dac_valid_out_b,
61+
output hold_last_sample,
5962
output underflow,
6063

6164
input [ 1:0] trigger_i,
@@ -130,6 +133,8 @@ module axi_dac_interpolate #(
130133
wire [15:0] dac_correction_coefficient_b;
131134
wire [19:0] trigger_config;
132135

136+
wire en_start_trigger;
137+
wire en_stop_trigger;
133138
wire [ 1:0] en_trigger_pins;
134139
wire en_trigger_adc;
135140
wire en_trigger_la;
@@ -141,11 +146,15 @@ module axi_dac_interpolate #(
141146
wire [ 1:0] fall_edge;
142147

143148
wire trigger_active;
149+
wire trigger;
144150
wire ext_trigger;
145151

146152
wire underflow_a;
147153
wire underflow_b;
148154

155+
wire [ 1:0] lsample_hold_config;
156+
wire sync_stop_channels;
157+
149158
// signal name changes
150159

151160
assign up_clk = s_axi_aclk;
@@ -159,9 +168,11 @@ module axi_dac_interpolate #(
159168
assign rise_edge = trigger_config[7:6];
160169
assign fall_edge = trigger_config[9:8];
161170

162-
assign en_trigger_pins = trigger_config[17:16];
163-
assign en_trigger_adc = trigger_config[18];
164-
assign en_trigger_la = trigger_config[19];
171+
assign en_start_trigger = trigger_config[14];
172+
assign en_stop_trigger = trigger_config[15];
173+
assign en_trigger_pins = trigger_config[17:16];
174+
assign en_trigger_adc = trigger_config[18];
175+
assign en_trigger_la = trigger_config[19];
165176

166177
assign trigger_active = |trigger_config[19:16];
167178
assign trigger = (ext_trigger & en_trigger_pins) |
@@ -195,6 +206,9 @@ module axi_dac_interpolate #(
195206
low_level_trigger <= ~trigger_i_m3 & low_level;
196207
end
197208

209+
assign hold_last_sample = lsample_hold_config[0];
210+
assign sync_stop_channels = lsample_hold_config[1];
211+
198212
assign underflow = underflow_a | underflow_b;
199213

200214
axi_dac_interpolate_filter #(
@@ -205,6 +219,8 @@ module axi_dac_interpolate #(
205219

206220
.dac_data (dac_data_a),
207221
.dac_valid (dac_valid_a),
222+
.dac_valid_out (dac_valid_out_a),
223+
.sync_stop_channels (sync_stop_channels),
208224

209225
.dac_enable (dac_enable_a),
210226
.dac_int_data (dac_int_data_a),
@@ -217,6 +233,8 @@ module axi_dac_interpolate #(
217233
.start_sync_channels (start_sync_channels),
218234
.trigger (trigger),
219235
.trigger_active (trigger_active),
236+
.en_start_trigger (en_start_trigger),
237+
.en_stop_trigger (en_stop_trigger),
220238
.dma_valid (dma_valid_a),
221239
.dma_valid_adjacent (dma_valid_b),
222240
.dac_correction_enable(dac_correction_enable_a),
@@ -231,6 +249,8 @@ module axi_dac_interpolate #(
231249

232250
.dac_data (dac_data_b),
233251
.dac_valid (dac_valid_b),
252+
.dac_valid_out (dac_valid_out_b),
253+
.sync_stop_channels (sync_stop_channels),
234254
.underflow (underflow_b),
235255

236256
.dac_enable (dac_enable_b),
@@ -243,6 +263,8 @@ module axi_dac_interpolate #(
243263
.start_sync_channels (start_sync_channels),
244264
.trigger (trigger),
245265
.trigger_active (trigger_active),
266+
.en_start_trigger (en_start_trigger),
267+
.en_stop_trigger (en_stop_trigger),
246268
.dma_valid (dma_valid_b),
247269
.dma_valid_adjacent (dma_valid_a),
248270
.dac_correction_enable(dac_correction_enable_b),
@@ -265,6 +287,7 @@ module axi_dac_interpolate #(
265287
.dac_correction_coefficient_a(dac_correction_coefficient_a),
266288
.dac_correction_coefficient_b(dac_correction_coefficient_b),
267289
.trigger_config (trigger_config),
290+
.lsample_hold_config (lsample_hold_config),
268291

269292
.up_rstn (up_rstn),
270293
.up_clk (up_clk),

‎library/axi_dac_interpolate/axi_dac_interpolate_filter.v

Lines changed: 30 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -49,6 +49,8 @@ module axi_dac_interpolate_filter #(
4949
input dac_enable,
5050
output reg [15:0] dac_int_data,
5151
output dma_ready,
52+
output dac_valid_out,
53+
input sync_stop_channels,
5254
output underflow,
5355

5456
input [ 2:0] filter_mask,
@@ -59,6 +61,8 @@ module axi_dac_interpolate_filter #(
5961
input start_sync_channels,
6062
input trigger,
6163
input trigger_active,
64+
input en_start_trigger,
65+
input en_stop_trigger,
6266
input dma_valid,
6367
input dma_valid_adjacent
6468
);
@@ -78,6 +82,8 @@ module axi_dac_interpolate_filter #(
7882

7983
reg filter_enable = 1'b0;
8084
reg transfer = 1'b0;
85+
reg [15:0] dma_valid_m = 16'd0;
86+
reg stop_transfer = 1'd0;
8187

8288
wire dac_valid_corrected;
8389
wire [15:0] dac_data_corrected;
@@ -87,6 +93,9 @@ module axi_dac_interpolate_filter #(
8793
wire dac_cic_valid;
8894
wire [109:0] dac_cic_data;
8995

96+
wire dma_valid_ch_sync;
97+
wire dma_valid_ch;
98+
9099
ad_iqcor #(.Q_OR_I_N (0),
91100
.DISABLE(CORRECTION_DISABLE),
92101
.SCALE_ONLY(1))
@@ -119,6 +128,21 @@ module axi_dac_interpolate_filter #(
119128
.filter_out (dac_cic_data),
120129
.ce_out (dac_cic_valid));
121130

131+
assign dma_valid_ch_sync = sync_stop_channels ?
132+
dma_valid & dma_valid_adjacent & !dma_transfer_suspend :
133+
dma_valid & !dma_transfer_suspend;
134+
135+
assign dma_valid_ch = dma_valid_ch_sync & !stop_transfer;
136+
always @(posedge dac_clk) begin
137+
if (dac_rst == 1'b1) begin
138+
dma_valid_m <= 'd0;
139+
end else begin
140+
dma_valid_m <= {dma_valid_m[14:0], dma_valid_ch};
141+
end
142+
end
143+
144+
assign dac_valid_out = dma_valid_m[4'h5];
145+
122146
always @(posedge dac_clk) begin
123147
filter_mask_d1 <= filter_mask;
124148
if (filter_mask_d1 != filter_mask) begin
@@ -151,7 +175,7 @@ module axi_dac_interpolate_filter #(
151175

152176
always @(posedge dac_clk) begin
153177
if (dma_transfer_suspend == 1'b0) begin
154-
transfer <= trigger ? 1'b1 : transfer | !trigger_active;
178+
transfer <= trigger ? 1'b1 : transfer | !(trigger_active & en_start_trigger);
155179
end else begin
156180
transfer <= 1'b0;
157181
end
@@ -162,6 +186,11 @@ module axi_dac_interpolate_filter #(
162186
end
163187
end
164188

189+
always @(posedge dac_clk) begin
190+
stop_transfer <= !en_stop_trigger | dma_transfer_suspend ? 1'b0 :
191+
stop_transfer | (trigger_active & trigger & transfer);
192+
end
193+
165194
assign dma_ready = transmit_ready ? dac_int_ready : 1'b0;
166195
assign underflow = dac_enable & dma_ready & ~dma_valid;
167196

‎library/axi_dac_interpolate/axi_dac_interpolate_reg.v

Lines changed: 10 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -50,6 +50,7 @@ module axi_dac_interpolate_reg(
5050
output [15:0] dac_correction_coefficient_a,
5151
output [15:0] dac_correction_coefficient_b,
5252
output [19:0] trigger_config,
53+
output [ 1:0] lsample_hold_config,
5354
// bus interface
5455

5556
input up_rstn,
@@ -77,6 +78,7 @@ module axi_dac_interpolate_reg(
7778
reg [15:0] up_correction_coefficient_a = 16'h0;
7879
reg [15:0] up_correction_coefficient_b = 16'h0;
7980
reg [19:0] up_trigger_config = 20'h0;
81+
reg [ 1:0] up_lsample_hold_config = 2'h0;
8082

8183
wire [ 1:0] flags;
8284

@@ -96,6 +98,7 @@ module axi_dac_interpolate_reg(
9698
up_correction_coefficient_a <= 'd0;
9799
up_correction_coefficient_b <= 'd0;
98100
up_trigger_config <= 'd0;
101+
up_lsample_hold_config <= 'h0;
99102
end else begin
100103
up_wack <= up_wreq;
101104
if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h1)) begin
@@ -128,6 +131,9 @@ module axi_dac_interpolate_reg(
128131
if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h18)) begin
129132
up_trigger_config <= up_wdata[19:0];
130133
end
134+
if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h19)) begin
135+
up_lsample_hold_config <= up_wdata[1:0];
136+
end
131137
end
132138
end
133139

@@ -152,6 +158,7 @@ module axi_dac_interpolate_reg(
152158
5'h16: up_rdata <= {16'h0,up_correction_coefficient_a};
153159
5'h17: up_rdata <= {16'h0,up_correction_coefficient_b};
154160
5'h18: up_rdata <= {12'h0,up_trigger_config};
161+
5'h19: up_rdata <= {30'h0,up_lsample_hold_config};
155162
default: up_rdata <= 0;
156163
endcase
157164
end else begin
@@ -160,14 +167,15 @@ module axi_dac_interpolate_reg(
160167
end
161168
end
162169

163-
up_xfer_cntrl #(.DATA_WIDTH(126)) i_xfer_cntrl (
170+
up_xfer_cntrl #(.DATA_WIDTH(128)) i_xfer_cntrl (
164171
.up_rstn (up_rstn),
165172
.up_clk (up_clk),
166173
.up_data_cntrl ({ up_config[1], // 1
167174
up_config[0], // 1
168175
up_correction_coefficient_b,// 16
169176
up_correction_coefficient_a,// 16
170177
up_trigger_config, // 20
178+
up_lsample_hold_config, // 2
171179
up_flags, // 2
172180
up_interpolation_ratio_b, // 32
173181
up_interpolation_ratio_a, // 32
@@ -182,6 +190,7 @@ module axi_dac_interpolate_reg(
182190
dac_correction_coefficient_b, // 16
183191
dac_correction_coefficient_a, // 16
184192
trigger_config, // 20
193+
lsample_hold_config, // 2
185194
flags, // 2
186195
dac_interpolation_ratio_b, // 32
187196
dac_interpolation_ratio_a, // 32

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