8000 axi_dmac: Allow wider FIFO/AXI Stream interface · analogdevicesinc/hdl@5dd9fd4 · GitHub
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ronagylronagyl
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axi_dmac: Allow wider FIFO/AXI Stream interface
On large projects with multiple channels the databus on the FIFO/AXI stream interface can get wider that 1024 bits. This commit allows a wider range for all the interfaces, in 8000 case for the memory mapped interfaces where the range is 32-1024 the user selects a bus width out of range that will be handled by the IPI.
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‎library/axi_dmac/axi_dmac_ip.tcl

Lines changed: 2 additions & 1 deletion
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@@ -258,7 +258,7 @@ set_property -dict [list \
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foreach dir {"SRC" "DEST"} {
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set_property -dict [list \
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"value_validation_type" "list" \
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"value_validation_list" "16 32 64 128 256 512 1024" \
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"value_validation_list" "16 32 64 128 256 512 1024 2048" \
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] \
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[ipx::get_user_parameters DMA_DATA_WIDTH_${dir} -of_objects $cc]
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@@ -308,6 +308,7 @@ foreach {dir group} [list "SRC" $src_group "DEST" $dest_group] {
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ipgui::move_param -component $cc -order 2 $p -parent $group
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set_property -dict [list \
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"display_name" "Bus Width" \
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"tooltip" "Bus Width: For Memory-Mapped interface the valid range is 32-1024 bits" \
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] $p
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set p [ipgui::get_guiparamspec -name "AXI_SLICE_${dir}" -component $cc]

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