8000 axi_logic_analyzer: Improve external trigger · analogdevicesinc/hdl@6af5d3c · GitHub
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AndreiGrozavAndreiGrozav
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axi_logic_analyzer: Improve external trigger
Fix external trigger for low sampling rates. Because the external trigger can be a short pulse at high decimation rates there is a high chance that the pulse will be missed.
1 parent 5dc2ab9 commit 6af5d3c

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2 files changed

+83
-30
lines changed

2 files changed

+83
-30
lines changed

‎library/axi_logic_analyzer/axi_logic_analyzer.v

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -256,6 +256,9 @@ module axi_logic_analyzer #(
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257257
assign adc_valid = sample_valid_la;
258258

259+
always @(posedge clk_out) begin
260+
trigger_m1 <= trigger_i;
261+
end
259262
// downsampler logic analyzer
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261264
always @(posedge clk_out) begin

‎library/axi_logic_analyzer/axi_logic_analyzer_trigger.v

Lines changed: 80 additions & 30 deletions
Original file line numberDiff line numberDiff line change
@@ -56,16 +56,32 @@ module axi_logic_analyzer_trigger (
5656
output reg trigger_out,
5757
output reg trigger_out_adc);
5858

59-
reg [ 17:0] data_m1 = 'd0;
60-
reg [ 17:0] low_level = 'd0;
61-
reg [ 17:0] high_level = 'd0;
62-
reg [ 17:0] edge_detect = 'd0;
63-
reg [ 17:0] rise_edge = 'd0;
64-
reg [ 17:0] fall_edge = 'd0;
65-
66-
reg trigger_active;
67-
reg trigger_active_mux;
68-
reg trigger_active_d1;
59+
reg [ 1:0] ext_t_m = 'd0;
60+
reg [ 1:0] ext_t_low_level_hold = 'd0;
61+
reg [ 1:0] ext_t_high_level_hold = 'd0;
62+
reg [ 1:0] ext_t_edge_detect_hold = 'd0;
63+
reg [ 1:0] ext_t_rise_edge_hold = 'd0;
64+
reg [ 1:0] ext_t_fall_edge_hold = 'd0;
65+
reg ext_t_low_level_ack = 'd0;
66+
reg ext_t_high_level_ack = 'd0;
67+
reg ext_t_edge_detect_ack = 'd0;
68+
reg ext_t_rise_edge_ack = 'd0;
69+
reg ext_t_fall_edge_ack = 'd0;
70+
reg [ 15:0] data_m1 = 'd0;
71+
reg [ 15:0] low_level = 'd0;
72+
reg [ 15:0] high_level = 'd0;
73+
reg [ 15:0] edge_detect = 'd0;
74+
reg [ 15:0] rise_edge = 'd0;
75+
reg [ 15:0] fall_edge = 'd0;
76+
reg [ 15:0] low_level_m = 'd0;
77+
reg [ 15:0] high_level_m = 'd0;
78+
reg [ 15:0] edge_detect_m = 'd0;
79+
reg [ 15:0] rise_edge_m = 'd0;
80+
reg [ 15:0] fall_edge_m = 'd0;
81+
82+
reg trigger_active;
83+
reg trigger_active_mux;
84+
reg trigger_active_d1;
6985

7086
always @(posedge clk) begin
7187
if (data_valid == 1'b1) begin
@@ -80,19 +96,19 @@ module axi_logic_analyzer_trigger (
8096
// 0 OR
8197
// 1 AND
8298

83-
always @(posedge clk) begin
99+
always @(*) begin
84100
if (data_valid == 1'b1) begin
85101
case (trigger_logic[0])
86-
0: trigger_active <= |((edge_detect & edge_detect_enable) |
87-
(rise_edge & rise_edge_enable) |
88-
(fall_edge & fall_edge_enable) |
89-
(low_level & low_level_enable) |
90-
(high_level & high_level_enable));
91-
1: trigger_active <= &((edge_detect | ~edge_detect_enable) &
92-
(rise_edge | ~rise_edge_enable) &
93-
(fall_edge | ~fall_edge_enable) &
94-
(low_level | ~low_level_enable) &
95-
(high_level | ~high_level_enable));
102+
0: trigger_active = |(({ext_t_edge_detect_hold, edge_detect_m} & edge_detect_enable) |
103+
({ext_t_rise_edge_hold, rise_edge_m} & rise_edge_enable) |
104+
({ext_t_fall_edge_hold, fall_edge_m} & fall_edge_enable) |
105+
({ext_t_low_level_hold, low_level_m} & low_level_enable) |
106+
({ext_t_high_level_hold , high_level_m} & high_level_enable));
107+
1: trigger_active = &(({ext_t_edge_detect_hold, edge_detect_m} | ~edge_detect_enable) &
108+
({ext_t_rise_edge_hold, rise_edge_m} | ~rise_edge_enable) &
109+
({ext_t_fall_edge_hold, fall_edge_m} | ~fall_edge_enable) &
110+
({ext_t_low_level_hold, low_level_m} | ~low_level_enable) &
111+
({ext_t_high_level_hold , high_level_m} | ~high_level_enable));
96112
default: trigger_active = 1'b1;
97113
endcase
98114
end
@@ -109,9 +125,6 @@ module axi_logic_analyzer_trigger (
109125
endcase
110126
end
111127

112-
113-
// internal signals
114-
115128
always @(posedge clk) begin
116129
if (reset == 1'b1) begin
117130
data_m1 <= 'd0;
@@ -122,16 +135,53 @@ module axi_logic_analyzer_trigger (
122135
high_level <= 'd0;
123136
end else begin
124137
if (data_valid == 1'b1) begin
125-
data_m1 <= {trigger_i, data} ;
126-
edge_detect <= data_m1 ^ {trigger_i, data};
127-
rise_edge <= (data_m1 ^ {trigger_i, data} ) & {trigger_i, data};
128-
fall_edge <= (data_m1 ^ {trigger_i, data}) & ~{trigger_i, data};
129-
low_level <= ~{trigger_i, data};
130-
high_level <= {trigger_i, data};
138+
data_m1 <= data;
139+
edge_detect <= data_m1 ^ data;
140+
rise_edge <= (data_m1 ^ data) & data;
141+
fall_edge <= (data_m1 ^ data) & ~data;
142+
low_level <= ~data;
143+
high_level <= data;
144+
145+
edge_detect_m <= edge_detect;
146+
rise_edge_m <= rise_edge;
147+
fall_edge_m <= fall_edge;
148+
low_level_m <= low_level;
149+
high_level_m <= high_level;
131150
end
132151
end
133152
end
134153

154+
// external trigger detect
155+
156+
always @(posedge clk) begin
157+
if (reset == 1'b1) begin
158+
ext_t_m <= 'd0;
159+
ext_t_edge_detect_hold <= 'd0;
160+
ext_t_rise_edge_hold <= 'd0;
161+
ext_t_fall_edge_hold <= 'd0;
162+
ext_t_low_level_hold <= 'd0;
163+
ext_t_high_level_hold <= 'd0;
164+
end else begin
165+
ext_t_m <= trigger_i;
166+
167+
ext_t_edge_detect_hold <= ext_t_edge_detect_ack ? 2'b0 :
168+
(ext_t_m ^ trigger_i) | ext_t_edge_detect_hold;
169+
ext_t_rise_edge_hold <= ext_t_rise_edge_ack ? 2'b0 :
170+
((ext_t_m ^ trigger_i) & trigger_i) | ext_t_rise_edge_hold;
171+
ext_t_fall_edge_hold <= ext_t_fall_edge_ack ? 2'b0 :
172+
((ext_t_m ^ trigger_i) & ~trigger_i) | ext_t_fall_edge_hold;
173+
ext_t_low_level_hold <= ext_t_low_level_ack ? 2'b0 :
174+
(~trigger_i) | ext_t_low_level_hold;
175+
ext_t_high_level_hold <= ext_t_high_level_ack ? 2'b0 :
176+
(trigger_i) | ext_t_high_level_hold;
177+
178+
ext_t_edge_detect_ack <= data_valid & ( |ext_t_edge_detect_hold);
179+
ext_t_rise_edge_ack <= data_valid & ( |ext_t_rise_edge_hold);
180+
ext_t_fall_edge_ack <= data_valid & ( |ext_t_fall_edge_hold);
181+
ext_t_low_level_ack <= data_valid & ( |ext_t_low_level_hold);
182+
ext_t_high_level_ack <= data_valid & ( |ext_t_high_level_hold);
183+
end
184+
end
135185

136186
endmodule
137187

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