analogdevicesinc
diff --git a/‎library/axi_logic_analyzer/axi_logic_analyzer.v
Lines changed: 2 additions & 3 deletions
< 8000 div data-testid="addition diffstat" class="DiffSquares-module__diffSquare--h5kjy DiffSquares-module__addition--jeNtt"> b/‎library/axi_logic_analyzer/axi_logic_analyzer.v
Lines changed: 2 additions & 3 deletions
< 8000 div data-testid="addition diffstat" class="DiffSquares-module__diffSquare--h5kjy DiffSquares-module__addition--jeNtt">
diff --git a/‎library/axi_logic_analyzer/axi_logic_analyzer_trigger.v
Lines changed: 1 addition & 1 deletion b/‎library/axi_logic_analyzer/axi_logic_analyzer_trigger.v
Lines changed: 1 addition & 1 deletion
@@ -52,7 +52,7 @@ module axi_logic_analyzer #(
   input       [ 1:0]    trigger_i,
 
   output                adc_valid,
-  output      [15:0]    adc_data,
+  output reg  [15:0]    adc_data,
 
   input       [15:0]    dac_data,
   input                 dac_valid,
@@ -161,8 +161,6 @@ module axi_logic_analyzer #(
   assign trigger_out = trigger_delay == 32'h0 ? trigger_out_s | streaming_on : trigger_out_delayed | streaming_on;
   assign trigger_out_delayed = delay_counter == 32'h0 ? 1 : 0;
 
-  assign adc_data = adc_data_mn;
-
  always @(posedge clk_out) begin
     if (trigger_delay == 0) begin
       if (streaming == 1'b1 && sample_valid_la == 1'b1 && trigger_out_s == 1'b1) begin
@@ -250,6 +248,7 @@ module axi_logic_analyzer #(
     always @(posedge clk_out) begin
       if (sample_valid_la == 1'b1) begin
         adc_data_mn <= data_m[ADC_PATH_DELAY-2];
+        adc_data <= adc_data_mn;
       end
     end
   endgenerate
 
@@ -96,7 +96,7 @@ module axi_logic_analyzer_trigger (
   // 0 OR
   // 1 AND
 
-  always @(*) begin
+  always @(posedge clk) begin
     if (data_valid == 1'b1) begin
       case (trigger_logic[0])
         0: trigger_active = |(({ext_t_edge_detect_hold, edge_detect_m} & edge_detect_enable) |