analogdevicesinc
diff --git a/‎library/axi_adc_trigger/axi_adc_trigger.v
Lines changed: 4 additions & 2 deletions b/‎library/axi_adc_trigger/axi_adc_trigger.v
Lines changed: 4 additions & 2 deletions
diff --git a/‎library/axi_adc_trigger/axi_adc_trigger_reg.v
Lines changed: 10 additions & 1 deletion b/‎library/axi_adc_trigger/axi_adc_trigger_reg.v
Lines changed: 10 additions & 1 deletion
@@ -129,6 +129,7 @@ module axi_adc_trigger #(
   wire         [31:0]   trigger_delay;
 
   wire         [31:0]   trigger_holdoff;
+  wire         [31:0]   trigger_out_hold_pins;
 
   wire signed  [DW:0]   data_a_cmp;
   wire signed  [DW:0]   data_b_cmp;
@@ -260,15 +261,15 @@ module axi_adc_trigger #(
     if (trig_o_hold_cnt_0 != 17'd0) begin
       trig_o_hold_cnt_0 <= trig_o_hold_cnt_0 - 17'd1;
     end else if (trig_o_hold_0 != trigger_o_m[0]) begin
-      trig_o_hold_cnt_0 <= OUT_PIN_HOLD_N;
+      trig_o_hold_cnt_0 <= trigger_out_hold_pins;
       trig_o_hold_0 <= trigger_o_m[0];
     end
 
     // trigger_o[1] hold start
     if (trig_o_hold_cnt_1 != 17'd0) begin
       trig_o_hold_cnt_1 <= trig_o_hold_cnt_1 - 17'd1;
     end else if (trig_o_hold_1 != trigger_o_m[1]) begin
-      trig_o_hold_cnt_1 <= OUT_PIN_HOLD_N;
+      trig_o_hold_cnt_1 <= trigger_out_hold_pins;
       trig_o_hold_1 <= trigger_o_m[1];
     end
 
@@ -591,6 +592,7 @@ module axi_adc_trigger #(
   .trigger_out_control(trigger_out_control),
   .trigger_delay(trigger_delay),
   .trigger_holdoff (trigger_holdoff),
+  .trigger_out_hold_pins (trigger_out_hold_pins),
 
   .fifo_depth(fifo_depth),
 
 
@@ -63,6 +63,7 @@ module axi_adc_trigger_reg (
   output      [31:0]  fifo_depth,
   output      [31:0]  trigger_delay,
   output      [31:0]  trigger_holdoff,
+  output      [31:0]  trigger_out_hold_pins,
 
   output              streaming,
 
@@ -102,6 +103,7 @@ module axi_adc_trigger_reg (
   reg     [31:0]  up_fifo_depth = 32'h0;
   reg     [31:0]  up_trigger_delay = 32'h0;
   reg     [31:0]  up_trigger_holdoff = 32'h0;
+  reg     [31:0]  up_trigger_out_hold_pins = 32'h0;
   reg             up_triggered = 1'h0;
   reg             up_streaming = 1'h0;
 
@@ -132,6 +134,7 @@ module axi_adc_trigger_reg (
       up_triggered <= 1'd0;
       up_streaming <= 1'd0;
       up_trigger_holdoff <= 32'h0;
+      up_trigger_out_hold_pins <= 32'h0;
     end else begin
       up_wack <= up_wreq;
       if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h1)) begin
@@ -190,6 +193,9 @@ module axi_adc_trigger_reg (
       if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h12)) begin
         up_trigger_holdoff <= up_wdata[31:0];
       end
+      if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h13)) begin
+        up_trigger_out_hold_pins <= up_wdata[31:0];
+      end
     end
   end
 
@@ -222,6 +228,7 @@ module axi_adc_trigger_reg (
           5'h10: up_rdata <= up_trigger_delay;
           5'h11: up_rdata <= {31'h0,up_streaming};
           5'h12: up_rdata <= up_trigger_holdoff;
+          5'h13: up_rdata <= up_trigger_out_hold_pins;
           default: up_rdata <= 0;
         endcase
       end else begin
@@ -230,7 +237,7 @@ module axi_adc_trigger_reg (
     end
   end
 
-   up_xfer_cntrl #(.DATA_WIDTH(242)) i_xfer_cntrl (
+   up_xfer_cntrl #(.DATA_WIDTH(274)) i_xfer_cntrl (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_data_cntrl ({ up_streaming,           // 1
@@ -248,6 +255,7 @@ module axi_adc_trigger_reg (
                       up_trigger_out_control, // 17
                       up_fifo_depth,          // 32
                       up_trigger_holdoff,     // 32
+                      up_trigger_out_hold_pins,// 32
                       up_trigger_delay}),     // 32
 
@@ -268,6 +276,7 @@ module axi_adc_trigger_reg (
                       trigger_out_control,// 17
                       fifo_depth,         // 32
                       trigger_holdoff,    // 32
+                      trigger_out_hold_pins,// 32
                       trigger_delay}));   // 32
 
 endmodule