8000 axi_dmac: Add interface description register · analogdevicesinc/hdl@d2b1164 · GitHub
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axi_dmac: Add interface description register
Adds information on: - Log 2 of interface data widths in bits - Interface type (0 - Axi MemoryMap, 1 - AXI Stream, 2 - FIFO ) . Lets the driver discover interface widths and interface type settings, this will deprecate the corresponding device tree properties. This is useful in case of parametrized projects where the width of the datapath is changing. This change will allow the use of a generic device tree node. Updated version to 4.3.a
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‎library/axi_dmac/axi_dmac.v

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@@ -397,6 +397,8 @@ axi_dmac_regmap #(
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.BYTES_PER_BEAT_WIDTH_DEST(BYTES_PER_BEAT_WIDTH_DEST),
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.BYTES_PER_BEAT_WIDTH_SRC(BYTES_PER_BEAT_WIDTH_SRC),
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.BYTES_PER_BURST_WIDTH(BYTES_PER_BURST_WIDTH),
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.DMA_TYPE_DEST(DMA_TYPE_DEST),
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.DMA_TYPE_SRC(DMA_TYPE_SRC),
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.DMA_AXI_ADDR_WIDTH(DMA_AXI_ADDR_WIDTH),
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.DMA_LENGTH_WIDTH(DMA_LENGTH_WIDTH),
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.DMA_LENGTH_ALIGN(DMA_LENGTH_ALIGN),

‎library/axi_dmac/axi_dmac_regmap.v

Lines changed: 6 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -41,6 +41,8 @@ module axi_dmac_regmap #(
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parameter BYTES_PER_BEAT_WIDTH_DEST = 1,
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parameter BYTES_PER_BEAT_WIDTH_SRC = 1,
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parameter BYTES_PER_BURST_WIDTH = 7,
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parameter DMA_TYPE_DEST = 0,
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parameter DMA_TYPE_SRC = 2,
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parameter DMA_AXI_ADDR_WIDTH = 32,
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parameter DMA_LENGTH_WIDTH = 24,
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parameter DMA_LENGTH_ALIGN = 3,
@@ -112,7 +114,7 @@ module axi_dmac_regmap #(
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input [31:0] dbg_ids1
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);
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localparam PCORE_VERSION = 'h00040262;
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localparam PCORE_VERSION = 'h00040361;
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// Register interface signals
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reg [31:0] up_rdata = 32'h00;
@@ -199,6 +201,9 @@ always @(posedge s_axi_aclk) begin
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9'h001: up_rdata <= ID;
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9'h002: up_rdata <= up_scratch;
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9'h003: up_rdata <= 32'h444d4143; // "DMAC"
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9'h004: up_rdata <= {16'b0,
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2'b0,DMA_TYPE_SRC[1:0],BYTES_PER_BEAT_WIDTH_SRC[3:0],
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2'b0,DMA_TYPE_DEST[1:0],BYTES_PER_BEAT_WIDTH_DEST[3:0]};
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9'h020: up_rdata <= up_irq_mask;
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9'h021: up_rdata <= up_irq_pending;
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9'h022: up_rdata <= up_irq_source;

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