8000 m2k: Pattern Generator add instrument triggering · analogdevicesinc/hdl@ef5f29e · GitHub
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AndreiGrozavAndreiGrozav
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m2k: Pattern Generator add instrument triggering
The Pattern generator is part of the axi_logic_analyzer core. The trigger signal can be internal (Oscilloscope or Logic Analyzer) or external(TI or TO pins).
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-7
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2 files changed

+88
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‎library/axi_logic_analyzer/axi_logic_analyzer.v

Lines changed: 78 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -112,6 +112,20 @@ module axi_logic_analyzer #(
112112

113113
reg streaming_on;
114114

115+
reg [ 1:0] trigger_i_m1 = 2'd0;
116+
reg [ 1:0] trigger_i_m2 = 2'd0;
117+
reg [ 1:0] trigger_i_m3 = 2'd0;
118+
reg trigger_adc_m1 = 1'd0;
119+
reg trigger_adc_m2 = 1'd0;
120+
reg trigger_la_m2 = 1'd0;
121+
reg pg_trigered = 1'd0;
122+
123+
reg [ 1:0] any_edge_trigger = 1'd0;
124+
reg [ 1:0] rise_edge_trigger = 1'd0;
125+
reg [ 1:0] fall_edge_trigger = 1'd0;
126+
reg [ 1:0] high_level_trigger = 1'd0;
127+
reg [ 1:0] low_level_trigger = 1'd0;
128+
115129
reg [15:0] adc_data_mn = 'd0;
116130
reg [31:0] trigger_holdoff_counter = 32'd0;
117131

@@ -150,6 +164,18 @@ module axi_logic_analyzer #(
150164
wire [31:0] trigger_delay;
151165
wire trigger_out_delayed;
152166

167+
wire [19:0] pg_trigger_config;
168+
169+
wire [ 1:0] pg_en_trigger_pins;
170+
wire pg_en_trigger_adc;
171+
wire pg_en_trigger_la;
172+
173+
wire [ 1:0] pg_low_level;
174+
wire [ 1:0] pg_high_level;
175+
wire [ 1:0] pg_any_edge;
176+
wire [ 1:0] pg_rise_edge;
177+
wire [ 1:0] pg_fall_edge;
178+
153179
wire [31:0] trigger_holdoff;
154180
wire trigger_out_holdoff;
155181

@@ -280,6 +306,47 @@ module axi_logic_analyzer #(
280306
end
281307
end
282308

309+
// pattern generator instrument triggering
310+
311+
assign pg_any_edge = pg_trigger_config[1:0];
312+
assign pg_rise_edge = pg_trigger_config[3:2];
313+
assign pg_fall_edge = pg_trigger_config[5:4];
314+
assign pg_low_level = pg_trigger_config[7:6];
315+
assign pg_high_level = pg_trigger_config[9:8];
316+
317+
assign pg_en_trigger_pins = pg_trigger_config[17:16];
318+
assign pg_en_trigger_adc = pg_trigger_config[18];
319+
assign pg_en_trigger_la = pg_trigger_config[19];
320+
321+
assign trigger_active = |pg_trigger_config[19:16];
322+
assign trigger = (ext_trigger & pg_en_trigger_pins) |
323+
(trigger_adc_m2 & pg_en_trigger_adc) |
324+
(trigger_out_s & pg_en_trigger_la);
325+
326+
assign ext_trigger = |(any_edge_trigger |
327+
rise_edge_trigger |
328+
fall_edge_trigger |
329+
high_level_trigger |
330+
low_level_trigger);
331+
332+
// sync
333+
always @(posedge clk) begin
334+
trigger_i_m1 <= trigger_i;
335+
trigger_i_m2 <= trigger_i_m1;
336+
trigger_i_m3 <= trigger_i_m2;
337+
338+
trigger_adc_m1 <= trigger_in;
339+
trigger_adc_m2 <= trigger_adc_m1;
340+
end
341+
342+
always @(posedge clk) begin
343+
any_edge_trigger <= (trigger_i_m3 ^ trigger_i_m2) & pg_any_edge;
344+
rise_edge_trigger <= (~trigger_i_m3 & trigger_i_m2) & pg_rise_edge;
345+
fall_edge_trigger <= (trigger_i_m3 & ~trigger_i_m2) & pg_fall_edge;
346+
high_level_trigger <= trigger_i_m3 & pg_high_level;
347+
low_level_trigger <= ~trigger_i_m3 & pg_low_level;
348+
end
349+
283350
// upsampler pattern generator
284351

285352
always @(posedge clk_out) begin
@@ -288,12 +355,16 @@ module axi_logic_analyzer #(
288355
dac_read <= 1'b0;
289356
end else begin
290357
dac_read <= 1'b0;
291-
if (upsampler_counter_pg < divider_counter_pg) begin
292-
upsampler_counter_pg <= upsampler_counter_pg + 1;
293-
end else begin
294-
upsampler_counter_pg <= 32'h0;
295-
dac_read <= 1'b1;
296-
end
358+
pg_trigered <= trigger_active ? (trigger | pg_trigered) : 1'b0;
359+
if (trigger_active & !pg_trigered) begin
360+
upsampler_counter_pg <= 32'h0;
361+
dac_read <= 1'b0;
362+
end else if (upsampler_counter_pg < divider_counter_pg) begin
363+
upsampler_counter_pg <= upsampler_counter_pg + 1;
364+
end else begin
365+
upsampler_counter_pg <= 32'h0;
366+
dac_read <= 1'b1;
367+
end
297368
end
298369
end
299370

@@ -377,6 +448,7 @@ module axi_logic_analyzer #(
377448
.od_pp_n (od_pp_n),
378449

379450
.triggered (up_triggered),
451+
.pg_trigger_config (pg_trigger_config),
380452

381453
.streaming(streaming),
382454

‎library/axi_logic_analyzer/axi_logic_analyzer_reg.v

Lines changed: 10 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -59,6 +59,7 @@ module axi_logic_analyzer_reg (
5959
output [15:0] od_pp_n,
6060

6161
output [31:0] trigger_holdoff,
62+
output [19:0] pg_trigger_config,
6263

6364
input triggered,
6465

@@ -98,6 +99,7 @@ module axi_logic_analyzer_reg (
9899
reg [15:0] up_overwrite_data = 0;
99100
reg [15:0] up_od_pp_n = 0;
100101
reg [31:0] up_trigger_holdoff = 32'h0;
102+
reg [19:0] up_pg_trigger_config = 20'h0;
101103
reg up_triggered = 0;
102104
reg up_streaming = 0;
103105

@@ -125,6 +127,7 @@ module axi_logic_analyzer_reg (
125127
up_triggered <= 1'd0;
126128
up_streaming <= 1'd0;
127129
up_trigger_holdoff <= 32'h0;
130+
up_pg_trigger_config <= 20'd0;
128131
end else begin
129132
up_wack <= up_wreq;
130133
if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h1)) begin
@@ -186,6 +189,9 @@ module axi_logic_analyzer_reg (
186189
if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h14)) begin
187190
up_trigger_holdoff <= up_wdata[31:0];
188191
end
192+
if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h15)) begin
193+
up_pg_trigger_config <= up_wdata[19:0];
194+
end
189195
end
190196
end
191197

@@ -220,6 +226,7 @@ module axi_logic_analyzer_reg (
220226
5'h12: up_rdata <= {31'h0,up_triggered};
221227
5'h13: up_rdata <= {31'h0,up_streaming};
222228
5'h14: up_rdata <= up_trigger_holdoff;
229+
5'h15: up_rdata <= {12'h0,up_pg_trigger_config};
223230
default: up_rdata <= 0;
224231
endcase
225232
end else begin
@@ -230,7 +237,7 @@ module axi_logic_analyzer_reg (
230237

231238
ad_rst i_core_rst_reg (.rst_async(~up_rstn), .clk(clk), .rstn(), .rst(reset));
232239

233-
up_xfer_cntrl #(.DATA_WIDTH(323)) i_xfer_cntrl (
240+
up_xfer_cntrl #(.DATA_WIDTH(343)) i_xfer_cntrl (
234241
.up_rstn (up_rstn),
235242
.up_clk (up_clk),
236243
.up_data_cntrl ({ up_streaming, // 1
@@ -248,6 +255,7 @@ module axi_logic_analyzer_reg (
248255
up_rise_edge_enable, // 18
249256
up_edge_detect_enable, // 18
250257
up_io_selection, // 16
258+
up_pg_trigger_config, // 20
251259
up_divider_counter_pg, // 32
252260
up_divider_counter_la}), // 32
253261

@@ -269,6 +277,7 @@ module axi_logic_analyzer_reg (
269277
rise_edge_enable, // 18
270278
edge_detect_enable, // 18
271279
io_selection, // 16
280+
pg_trigger_config, // 20
272281
divider_counter_pg, // 32
273282
divider_counter_la})); // 32
274283

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