8000 library/axi_dmac: Rename 2d_transfer to dmac_2d_transfer · analogdevicesinc/hdl@fe713a5 · GitHub
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IuliaCMoldovanIuliaCMoldovan
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library/axi_dmac: Rename 2d_transfer to dmac_2d_transfer
Update the file according to HDL guideline. Replace all occurrences of 2d_transfer with dmac_2d_transfer. Update axi_dmac/Makefile.
1 parent d9ec446 commit fe713a5

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8 files changed

+100
-96
lines changed

8 files changed

+100
-96
lines changed

‎library/axi_dmac/Makefile

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -8,7 +8,6 @@ LIBRARY_NAME := axi_dmac
88

99
GENERIC_DEPS += ../common/ad_mem_asym.v
1010
GENERIC_DEPS += ../common/up_axi.v
11-
GENERIC_DEPS += 2d_transfer.v
1211
GENERIC_DEPS += address_generator.v
1312
GENERIC_DEPS += axi_dmac.v
1413
GENERIC_DEPS += axi_dmac_burst_memory.v
@@ -24,6 +23,7 @@ GENERIC_DEPS += data_mover.v
2423
GENERIC_DEPS += dest_axi_mm.v
2524
GENERIC_DEPS += dest_axi_stream.v
2625
GENERIC_DEPS += dest_fifo_inf.v
26+
GENERIC_DEPS += dmac_2d_transfer.v
2727
GENERIC_DEPS += inc_id.vh
2828
GENERIC_DEPS += request_arb.v
2929
GENERIC_DEPS += request_generator.v

‎library/axi_dmac/axi_dmac_hw.tcl

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -37,7 +37,7 @@ ad_ip_files axi_dmac [list \
3737
request_generator.v \
3838
response_handler.v \
3939
axi_register_slice.v \
40-
2d_transfer.v \
40+
dmac_2d_transfer.v \
4141
dest_axi_mm.v \
4242
dest_axi_stream.v \
4343
dest_fifo_inf.v \

‎library/axi_dmac/axi_dmac_ip.tcl

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -25,7 +25,7 @@ adi_ip_files axi_dmac [list \
2525
"request_generator.v" \
2626
"response_handler.v" \
2727
"axi_register_slice.v" \
28-
"2d_transfer.v" \
28+
"dmac_2d_transfer.v" \
2929
"dest_axi_mm.v" \
3030
"dest_axi_stream.v" \
3131
"dest_fifo_inf.v" \

‎library/axi_dmac/2d_transfer.v renamed to ‎library/axi_dmac/dmac_2d_transfer.v

Lines changed: 93 additions & 89 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
// ***************************************************************************
22
// ***************************************************************************
3-
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
3+
// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved.
44
//
55
// In this HDL repository, there are many different and unique modules, consisting
66
// of various HDL (Verilog or VHDL) components. The individual modules are
@@ -41,7 +41,7 @@ module dmac_2d_transfer #(
4141
parameter DMA_LENGTH_WIDTH = 24,
4242
parameter BYTES_PER_BURST_WIDTH = 7,
4343
parameter BYTES_PER_BEAT_WIDTH_SRC = 3,
44-
parameter BYTES_PER_BEAT_WIDTH_DEST = 3)(
44+
parameter BYTES_PER_BEAT_WIDTH_DEST = 3) (
4545

4646
input req_aclk,
4747
input req_aresetn,
@@ -78,116 +78,120 @@ module dmac_2d_transfer #(
7878
input [BYTES_PER_BURST_WIDTH-1:0] out_measured_burst_length,
7979
input out_response_partial,
8080
input out_response_valid,
81-
output reg out_response_ready = 1'b1
81+
output reg out_response_ready = 1'b1);
8282

83-
);
83+
// internal registers
8484

85-
reg [DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_DEST] dest_address = 'h00;
86-
reg [DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_SRC] src_address = 'h00;
87-
reg [DMA_LENGTH_WIDTH-1:0] x_length = 'h00;
88-
reg [DMA_LENGTH_WIDTH-1:0] y_length = 'h00;
89-
reg [DMA_LENGTH_WIDTH-1:0] dest_stride = 'h0;
90-
reg [DMA_LENGTH_WIDTH-1:0] src_stride = 'h00;
85+
reg [DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_DEST] dest_address = 'h00;
86+
reg [DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_SRC] src_address = 'h00;
87+
reg [DMA_LENGTH_WIDTH-1:0] x_length = 'h00;
88+
reg [DMA_LENGTH_WIDTH-1:0] y_length = 'h00;
89+
reg [DMA_LENGTH_WIDTH-1:0] dest_stride = 'h0;
90+
reg [DMA_LENGTH_WIDTH-1:0] src_stride = 'h00;
9191

92-
reg gen_last = 'h0;
92+
reg gen_last = 'h0;
9393

94-
reg [1:0] req_id = 'h00;
95-
reg [1:0] eot_id = 'h00;
96-
reg [3:0] last_req = 'h00;
94+
reg [1:0] req_id = 'h00;
95+
reg [1:0] eot_id = 'h00;
96+
reg [3:0] last_req = 'h00;
9797

98-
wire out_last;
98+
// internal signals
9999

100-
assign out_req_dest_address = dest_address;
101-
assign out_req_src_address = src_address;
102-
assign out_req_length = x_length;
103-
assign out_last = y_length == 'h00;
100+
wire out_last;
104101

105-
always @(posedge req_aclk) begin
106-
if (req_aresetn == 1'b0) begin
107-
req_id <= 2'b0;
108-
eot_id <= 2'b0;
109-
req_eot <= 1'b0;
110-
end else begin
111-
if (out_req_valid == 1'b1 && out_req_ready == 1'b1) begin
112-
req_id <= req_id + 1'b1;
113-
end
102+
// signal name changes
114103

115-
if (out_eot == 1'b1 && out_response_valid == 1'b1 && out_response_ready == 1'b1) begin
116-
eot_id <= eot_id + 1'b1;
117-
req_eot <= last_req[eot_id];
118-
end else begin
104+
assign out_req_dest_address = dest_address;
105+
assign out_req_src_address = src_address;
106+
assign out_req_length = x_length;
107+
assign out_last = y_length == 'h00;
108+
109+
always @(posedge req_aclk) begin
110+
if (req_aresetn == 1'b0) begin
111+
req_id <= 2'b0;
112+
eot_id <= 2'b0;
119113
req_eot <= 1'b0;
114+
end else begin
115+
if (out_req_valid == 1'b1 && out_req_ready == 1'b1) begin
116+
req_id <= req_id + 1'b1;
117+
end
118+
119+
if (out_eot == 1'b1 && out_response_valid == 1'b1 && out_response_ready == 1'b1) begin
120+
eot_id <= eot_id + 1'b1;
121+
req_eot <= last_req[eot_id];
122+
end else begin
123+
req_eot <= 1'b0;
124+
end
120125
end
121126
end
122-
end
123127

124-
always @(posedge req_aclk) begin
125-
if (out_req_valid == 1'b1 && out_req_ready == 1'b1) begin
126-
last_req[req_id] <= out_last;
128+
always @(posedge req_aclk) begin
129+
if (out_req_valid == 1'b1 && out_req_ready == 1'b1) begin
130+
last_req[req_id] <= out_last;
131+
end
127132
end
128-
end
129133

130-
always @(posedge req_aclk) begin
131-
if (out_response_valid == 1'b1 && out_response_ready == 1'b1) begin
132-
req_measured_burst_length <= out_measured_burst_length;
133-
req_response_partial <= out_response_partial;
134+
always @(posedge req_aclk) begin
135+
if (out_response_valid == 1'b1 && out_response_ready == 1'b1) begin
136+
req_measured_burst_length <= out_measured_burst_length;
137+
req_response_partial <= out_response_partial;
138+
end
134139
end
135-
end
136140

137-
always @(posedge req_aclk) begin
138-
if (out_response_valid == 1'b1 && out_response_ready == 1'b1) begin
139-
req_response_valid <= 1'b1;
140-
end else if (req_response_ready == 1'b1) begin
141-
req_response_valid <= 1'b0;
142-
end
143-
end
144-
145-
always @(posedge req_aclk) begin
146-
if (req_aresetn == 1'b0) begin
147-
out_response_ready <= 1'b1;
148-
end else if (out_response_ready == 1'b1) begin
149-
out_response_ready <= ~out_response_valid;
150-
end else if (req_response_ready == 1'b1) begin
151-
out_response_ready <= 1'b1;
141+
always @(posedge req_aclk) begin
142+
if (out_response_valid == 1'b1 && out_response_ready == 1'b1) begin
143+
req_response_valid <= 1'b1;
144+
end else if (req_response_ready == 1'b1) begin
145+
req_response_valid <= 1'b0;
146+
end
152147
end
153-
end
154-
155-
always @(posedge req_aclk) begin
156-
if (req_ready == 1'b1 && req_valid == 1'b1) begin
157-
dest_address <= req_dest_address;
158-
src_address <= req_src_address;
159-
x_length <= req_x_length;
160-
y_length <= req_y_length;
161-
dest_stride <= req_dest_stride;
162-
src_stride <= req_src_stride;
163-
out_req_sync_transfer_start <= req_sync_transfer_start;
164-
gen_last <= req_last;
165-
end else if (out_abort_req == 1'b1) begin
166-
y_length <= 0;
167-
end else if (out_req_valid == 1'b1 && out_req_ready == 1'b1) begin
168-
dest_address <= dest_address + dest_stride[DMA_LENGTH_WIDTH-1:BYTES_PER_BEAT_WIDTH_DEST];
169-
src_address <= src_address + src_stride[DMA_LENGTH_WIDTH-1:BYTES_PER_BEAT_WIDTH_SRC];
170-
y_length <= y_length - 1'b1;
171-
out_req_sync_transfer_start <= 1'b0;
148+
149+
always @(posedge req_aclk) begin
150+
if (req_aresetn == 1'b0) begin
151+
out_response_ready <= 1'b1;
152+
end else if (out_response_ready == 1'b1) begin
153+
out_response_ready <= ~out_response_valid;
154+
end else if (req_response_ready == 1'b1) begin
155+
out_response_ready <= 1'b1;
156+
end
172157
end
173-
end
174158

175-
always @(posedge req_aclk) begin
176-
if (req_aresetn == 1'b0) begin
177-
req_ready <= 1'b1;
178-
out_req_valid <= 1'b0;
179-
end else begin
159+
always @(posedge req_aclk) begin
180160
if (req_ready == 1'b1 && req_valid == 1'b1) begin
181-
req_ready <= 1'b0;
182-
out_req_valid <= 1'b1;
183-
end else if (out_req_valid == 1'b1 && out_req_ready == 1'b1 &&
184-
out_last == 1'b1) begin
185-
out_req_valid <= 1'b0;
161+
dest_address <= req_dest_address;
162+
src_address <= req_src_address;
163+
x_length <= req_x_length;
164+
y_length <= req_y_length;
165+
dest_stride <= req_dest_stride;
166+
src_stride <= req_src_stride;
167+
out_req_sync_transfer_start <= req_sync_transfer_start;
168+
gen_last <= req_last;
169+
end else if (out_abort_req == 1'b1) begin
170+
y_length <= 0;
171+
end else if (out_req_valid == 1'b1 && out_req_ready == 1'b1) begin
172+
dest_address <= dest_address + dest_stride[DMA_LENGTH_WIDTH-1:BYTES_PER_BEAT_WIDTH_DEST];
173+
src_address <= src_address + src_stride[DMA_LENGTH_WIDTH-1:BYTES_PER_BEAT_WIDTH_SRC];
174+
y_length <= y_length - 1'b1;
175+
out_req_sync_transfer_start <= 1'b0;
176+
end
177+
end
178+
179+
always @(posedge req_aclk) begin
180+
if (req_aresetn == 1'b0) begin
186181
req_ready <= 1'b1;
182+
out_req_valid <= 1'b0;
183+
end else begin
184+
if (req_ready == 1'b1 && req_valid == 1'b1) begin
185+
req_ready <= 1'b0;
186+
out_req_valid <= 1'b1;
187+
end else if (out_req_valid == 1'b1 && out_req_ready == 1'b1 &&
188+
out_last == 1'b1) begin
189+
out_req_valid <= 1'b0;
190+
req_ready <= 1'b1;
191+
end
187192
end
188193
end
189-
end
190194

191-
assign out_req_last = out_last & gen_last;
195+
assign out_req_last = out_last & gen_last;
192196

193197
endmodule

‎library/axi_dmac/tb/dma_read_shutdown_tb

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3,7 +3,7 @@
33
SOURCE="$0.v"
44
SOURCE+=" axi_read_slave.v axi_slave.v"
55
SOURCE+=" ../axi_dmac_transfer.v ../request_arb.v ../request_generator.v ../splitter.v"
6-
SOURCE+=" ../2d_transfer.v"
6+
SOURCE+=" ../dmac_2d_transfer.v"
77
SOURCE+=" ../axi_dmac_resize_src.v ../axi_dmac_resize_dest.v"
88
SOURCE+=" ../axi_dmac_burst_memory.v"
99
SOURCE+=" ../axi_dmac_reset_manager.v ../axi_register_slice.v"

‎library/axi_dmac/tb/dma_read_tb

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,7 @@
22

33
SOURCE="dma_read_tb.v"
44
SOURCE+=" axi_read_slave.v axi_slave.v"
5-
SOURCE+=" ../axi_dmac_transfer.v ../2d_transfer.v ../request_arb.v ../request_generator.v ../splitter.v"
5+
SOURCE+=" ../axi_dmac_transfer.v ../dmac_2d_transfer.v ../request_arb.v ../request_generator.v ../splitter.v"
66
SOURCE+=" ../axi_dmac_resize_src.v ../axi_dmac_resize_dest.v"
77
SOURCE+=" ../axi_dmac_burst_memory.v"
88
SOURCE+=" ../axi_dmac_reset_manager.v ../axi_register_slice.v"

‎library/axi_dmac/tb/dma_write_shutdown_tb

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3,7 +3,7 @@
33
SOURCE="$0.v"
44
SOURCE+=" axi_write_slave.v axi_slave.v"
55
SOURCE+=" ../axi_dmac_transfer.v ../request_arb.v ../request_generator.v ../splitter.v"
6-
SOURCE+=" ../2d_transfer.v"
6+
SOURCE+=" ../dmac_2d_transfer.v"
77
SOURCE+=" ../axi_dmac_resize_src.v ../axi_dmac_resize_dest.v"
88
SOURCE+=" ../axi_dmac_burst_memory.v"
99
SOURCE+=" ../axi_dmac_reset_manager.v ../data_mover.v ../axi_register_slice.v"

‎library/axi_dmac/tb/dma_write_tb

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,7 @@
22

33
SOURCE="dma_write_tb.v"
44
SOURCE+=" axi_write_slave.v axi_slave.v"
5-
SOURCE+=" ../axi_dmac_transfer.v ../2d_transfer.v ../request_arb.v ../request_generator.v ../splitter.v"
5+
SOURCE+=" ../axi_dmac_transfer.v ../dmac_2d_transfer.v ../request_arb.v ../request_generator.v ../splitter.v"
66
SOURCE+=" ../axi_dmac_resize_src.v ../axi_dmac_resize_dest.v"
77
SOURCE+=" ../axi_dmac_burst_memory.v"
88
SOURCE+=" ../axi_dmac_reset_manager.v ../data_mover.v ../axi_register_slice.v"

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