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Description
The AD9208 driver in drivers/iio/adc/ad9208.c incorrectly assumes the minimum valid clock frequency is 625 MHz, which is valid for the AD9208-1300 variant but too high for the AD9208-625.
When using an AD9208-625 chip with a valid lower sampling clock (e.g., 250–500 MHz), the driver fails during probe with messages like:
Root Cause
These lines in the driver enforce a 625 MHz minimum:
phy->ad9208.input_clk_min_hz = 625000000ULL;
phy->ad9208.adc_clk_min_hz = 625000000ULL;
Proposed Fix
Lower both thresholds to support the -625 variant, which operates down to 250 MSPS. Recommend changing to:
phy->ad9208.input_clk_min_hz = 240000000ULL;
phy->ad9208.adc_clk_min_hz = 240000000ULL;
Optionally, the driver could query the part ID during probe to distinguish between AD9208-625 and AD9208-1300 and set limits accordingly.
Tested Platform
Board: ZCU102
Chip: AD9208-625
Kernel: 6.1.0-xilinx-v2023.1 (Raspbian)Metadata
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