Description
Type of issue: Bug Report
Please provide the steps to reproduce the problem:
Consider these tests: dtzSiFive@d8a3f12 .
Steps to reproduce are to checkout that branch / apply that commit and run the tests.
What is the current behavior?
The tests fail due to generating invalid FIRRTL because BoringUtils appends connect statements to the end where not all declarations are visible.
Example FIRRTL for the layer test example:
FIRRTL version 4.0.0
circuit Top :
layer TestLayer, bind : @[src/test/scala/chiselTests/BoringUtilsTapSpec.scala 167:36]
module
5DE2
Bar : @[src/test/scala/chiselTests/BoringUtilsTapSpec.scala 168:11]
output out : UInt<1> @[src/test/scala/chiselTests/BoringUtilsTapSpec.scala 169:19]
input out_bore : UInt<1> @[src/test/scala/chiselTests/BoringUtilsTapSpec.scala 170:36]
connect out, out_bore @[src/test/scala/chiselTests/BoringUtilsTapSpec.scala 170:11]
module Foo : @[src/test/scala/chiselTests/BoringUtilsTapSpec.scala 172:11]
input out_bore : UInt<1> @[src/test/scala/chiselTests/BoringUtilsTapSpec.scala 170:36]
layerblock TestLayer : @[src/test/scala/chiselTests/BoringUtilsTapSpec.scala 173:30]
inst bar of Bar @[src/test/scala/chiselTests/BoringUtilsTapSpec.scala 174:25]
connect bar.out_bore, out_bore @[src/test/scala/chiselTests/BoringUtilsTapSpec.scala 170:36]
public module Top : @[src/test/scala/chiselTests/BoringUtilsTapSpec.scala 177:11]
wire parentWire : UInt<1> @[src/test/scala/chiselTests/BoringUtilsTapSpec.scala 178:28]
inst foo of Foo @[src/test/scala/chiselTests/BoringUtilsTapSpec.scala 179:23]
connect foo.out_bore, parentWire @[src/test/scala/chiselTests/BoringUtilsTapSpec.scala 170:36]
connect bar.out_bore, out_bore is invalid, bar is only visible within the layer.
What is the expected behavior?
Boring produces diagnostic instead of illegal FIRRTL (as reasonable), and for probes this should work.
Other Information
Encountered this migrating to boring probes, specifically involving a layer.
What is the use case for changing the behavior?