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I have created a new simulator that uses svsim to output a vcd file with the verilator backend. I used the EphemeralSimulator as starting point.
Now I would like to use the "-g" option for the simulation, however I haven't find any way to do that. It seems it is not possible at the moment. I have seen that the annotations passed to chiselStage.execute are fixed.
chisel/src/main/scala/chisel3/simulator/package.scala
Lines 93 to 110 in 9f34eb5
It would be nice to have something that allows to select optimization options or directly passing firtooloptions like here. Either as a field of workspace or of the simulator or as an argument here.
def elaborateGeneratedModule[T <: RawModule](
generateModule: () => T
)(firtoolArgs: Seq[String] = Seq()): ElaboratedModule[T] = {
// Use CIRCT to generate SystemVerilog sources, and potentially additional artifacts
var someDut: Option[T] = None
val firtoolOptions = firtoolArgs.map(circt.stage.FirtoolOption)
val outputAnnotations = (new circt.stage.ChiselStage).execute(
Array("--target", "systemverilog", "--split-verilog"),
Seq(
chisel3.stage.ChiselGeneratorAnnotation { () =>
val dut = generateModule()
someDut = Some(dut)
dut
},
circt.stage.FirtoolOption("-disable-annotation-unknown"),
firrtl.options.TargetDirAnnotation(workspace.supportArtifactsPath),
) ++
firtoolOptions,
)
// ....
}Metadata
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