Lower function invocations to Verilog module instantiations #646

joachimschmidt557 · 2022-06-27T13:18:36Z

joachimschmidt557
Jun 27, 2022

Hi! I was wondering whether it would be possible to lower DSLX function invocations to module instantiations in the codegen pass. A small example:

fn foo(a: u32, b:u32) -> u32 {
  a + b
}

fn test(a: u32, b:u32) -> u32 {
  foo(a, b)
}

Converted to XLS IR, this produces

package test

fn __test__foo(a: bits[32], b: bits[32]) -> bits[32] {
  ret add.3: bits[32] = add(a, b, id=3, pos=0,1,4)
}

fn __test__test(a: bits[32], b: bits[32]) -> bits[32] {
  ret invoke.6: bits[32] = invoke(a, b, to_apply=__test__foo, id=6, pos=0,5,5)
}

Currently, when the invoke IR instruction is encountered by codegen_main, an error message is emitted. Would it be possible to convert that invoke instruction into a Verilog module instantiation and thus "preserve the function/module hierarchy"? Like this:

module __test__foo(
  input wire [31:0] a,
  input wire [31:0] b,
  output wire [31:0] out
);
  assign out = a + b;
endmodule

module __test__test(
  input wire [31:0] a,
  input wire [31:0] b,
  output wire [31:0] out
);
  foo foo_0(a, b, out);
endmodule

meheff · 2022-06-28T00:30:36Z

meheff
Jun 28, 2022
Maintainer

This wouldn't be too hard to implement. We already have the IR nodes and construct for module instantiation (they are not used at the moment). Codegen would have to walk the call graph and emit all the dependent modules first. To prevent inlining of the call sites, one could disable inlining entirely or add an attribute at the on functions DSLX level (and reflected in the IR) which disables inlining.

Currently we don't do any global (cross-function) optimizations so not inlining functions could potentially have some qor ramifications.

3 replies

joachimschmidt557 Jul 6, 2022
Author

Hi! Thanks for the pointers on how the implementation could look like. I implemented lowering function invocations to module instantiations in a local checkout (only for combinational modules so far, as I'm mostly interested in those). I modified GenerateCombinationalModule to walk the call graph in post-order (similar to the inlining pass). Furthermore, I introduced a new codegen pass InvocationToInstantiation which converts every invoke node in the block to an instantiation together with the InstantiationInput and InstantiationOutput nodes.

Let me know if you would be interested in upstreaming the implementation, otherwise, I'll just maintain it in a fork 👍

proppy Aug 19, 2024
Maintainer

otherwise, I'll just maintain it in a fork

@joachimschmidt557 is it this fork main...joachimschmidt557:xls:spfe-framework ?

joachimschmidt557 Aug 23, 2024
Author

Yes, I have based the changes on a previous version of XLS. Since then, multiple changes to the base files have happened, so that the changes can't be merged at the moment. I might rebase it if there is interest...

proppy · 2024-08-19T06:27:24Z

8000

proppy
Aug 19, 2024
Maintainer

@meheff @grebe should we transform this in an enhancement proposal?

0 replies

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Lower function invocations to Verilog module instantiations #646

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joachimschmidt557 Jun 27, 2022

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meheff Jun 28, 2022 Maintainer

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meheff
Jun 28, 2022
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joachimschmidt557 Jul 6, 2022
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proppy Aug 19, 2024
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joachimschmidt557 Aug 23, 2024
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proppy
Aug 19, 2024
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