8000 Commits · lu-ping/firrtl · GitHub

More Web Proxy on the site http://driver.im/

Commits

Commits on Dec 24, 2017

Spec erroneously says mod instead of rem.

grebe
authored and
edwardcwang
committed

Commits on Dec 23, 2017

API change: out-of-bounds vec accesses now invalid, not first element (#685)

azidar
authored and
jackkoenig
committed

Commits on Dec 21, 2017

Verify shl/shr amount is > 0 (#710)

ucbjrl
authored and
jackkoenig
committed

Commits on Dec 19, 2017

Create ISSUE_TEMPLATE.md (#699)

azidar
authored and
jackkoenig
committed

Commits on Dec 18, 2017

Bump sbt (#703)
jackkoenig
authored

Commits on Dec 16, 2017

getBuildDir now builds full path
azidar
committed

Commits on Dec 13, 2017

Merge pull request #684 from freechipsproject/remove-wires
jackkoenig
authored

Commits on Dec 12, 2017

Commits on Nov 29, 2017

Add alternative graph IR (#671)

dt27182
authored and
jackkoenig
committed
Have DedupModules report renaming

jackkoenig
authored and
azidar
committed
Refactor RenameMap to rename Components if their Module is renamed

jackkoenig
authored and
azidar
committed

Commits on Nov 17, 2017

Move digraph exceptions out of digraph class (#688)
albert-magyar
authored

Commits on Nov 16, 2017

Make Yosys equivalence check more robust (#686)
jackkoenig
authored

Commits on Nov 10, 2017

Make digraph methods deterministic (#653)

albert-magyar
authored and
jackkoenig
committed

Commits on Nov 8, 2017

Add InfoSpec for checking Info propagation

jackkoenig
authored and
azidar
committed
Add FirrtlCheckers and scalatest helpers for testing

jackkoenig
authored and
azidar
committed
Emit source locators as comments in emitted Verilog

jackkoenig
authored and
azidar
committed

Commits on Oct 31, 2017

Fix bug emitting and reparsing ExtModule String parameters (#675)
jackkoenig
authored

Commits on Oct 4, 2017

Merge pull request #670 from freechipsproject/add-formal-check
jackkoenig
authored

Commits on Oct 2, 2017

Add script for formally comparing emitted Verilog
jackkoenig
committed

Commits on Oct 1, 2017

Commits on Sep 30, 2017

Update README.md to link tech report (#550)

azidar
authored and
jackkoenig
committed
Fixed zero width cat but (#651)

azidar
authored and
jackkoenig
committed

Commits on Sep 29, 2017

StringLit.verilogEscape should support all printable ASCII chars (#668)
jackkoenig
authored

0