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Yosys supports several non-standard features of the BLIF specification that bring it more up to speed with a modern netlist format. Some other FPGA consumers of the BLIF format use this already.
For example the .cname feature could be used to give meaningful names for instances, e.g. an SRAM or IP block, that will be manually placed or at least you would like diagnostics and reporting for
Attributes on cells via the .attr feature could potentially be exposed via the Python API enabling e.g. querying cells with an attribute set to handle them specially.
Is there interest in this being added to Coriolis, or do you prefer to stick to the strict BLIF specification?
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