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Properties and sequences currently form an expression tree that is emitted wholly inline in the output Verilog. It would be beneficial to have a declaration op for properties and sequences that allows for an expression to be given a name. Emission would then move the expression into a property foo; ... endproperty or sequence bar; ... endsequence declaration and refer to them by the name foo or bar. The name on the declaration should be optional, such that ExportVerilog can pick a unique one if necessary. PrepareForEmission should then do a prepass over the IR and find properties and sequences that are used multiple times (or a sufficient number of times), and move those behind a declaration.
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