Description
When core execute JAL instruction, return address should be written to ra register. But in single step execution, the ra register is not updated.
Here is an example waveform.
code is: 730000ef jal ra,102073c
-
the core is free run.
You can see the return address 0x1020010 is written to ra register. -
the core is in single step.
Return address 0x1020010 is not written to ra register. We debug this issue and found that core deassert we_a_i in DBG_SIGNAL state. And ctrl_fsm_ns enter DBG_SIGNAL state before ra register update.
I tried to fix this issue by add & id_ready_i when ctrl_fsm_ns try to enter DBG_SIGNAL.
jump_set_i: begin
pc_mux_o = PC_JUMP;
pc_set_o = 1'b1;
perf_jump_o = 1'b1;
dbg_trap_o = dbg_settings_i[DBG_SETS_SSTE];
if (dbg_req_i & id_ready_i)
ctrl_fsm_ns = DBG_SIGNAL;
The return address can be written to ra due to this change. But I'm not sure this is a good workaround.