From cb56b56efaa8c4ad563790ac78765109515c4c24 Mon Sep 17 00:00:00 2001 From: xctan Date: Sun, 24 Dec 2023 19:33:15 +0800 Subject: [PATCH 1/3] [DYNAREC_RV64] Fixed SHLD for GI --- src/dynarec/rv64/dynarec_rv64_emit_shift.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/dynarec/rv64/dynarec_rv64_emit_shift.c b/src/dynarec/rv64/dynarec_rv64_emit_shift.c index 2460bd722b..ddbb2bc017 100644 --- a/src/dynarec/rv64/dynarec_rv64_emit_shift.c +++ b/src/dynarec/rv64/dynarec_rv64_emit_shift.c @@ -562,6 +562,7 @@ void emit_shrd32c(dynarec_rv64_t* dyn, int ninst, rex_t rex, int s1, int s2, uin } void emit_shld32c(dynarec_rv64_t* dyn, int ninst, rex_t rex, int s1, int s2, uint32_t c, int s3, int s4, int s5) { + c&=(rex.w?0x3f:0x1f); CLEAR_FLAGS(); IFX(X_PEND) { if (c) { From 152b4a5600e9783bec546372268a464ea163048a Mon Sep 17 00:00:00 2001 From: xctan Date: Sun, 24 Dec 2023 19:51:29 +0800 Subject: [PATCH 2/3] [DYNAREC_RV64] Fixed SHRD for GI --- src/dynarec/rv64/dynarec_rv64_emit_shift.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/dynarec/rv64/dynarec_rv64_emit_shift.c b/src/dynarec/rv64/dynarec_rv64_emit_shift.c index ddbb2bc017..0fdc10e310 100644 --- a/src/dynarec/rv64/dynarec_rv64_emit_shift.c +++ b/src/dynarec/rv64/dynarec_rv64_emit_shift.c @@ -497,6 +497,7 @@ void emit_ror32c(dynarec_rv64_t* dyn, int ninst, rex_t rex, int s1, uint32_t c, // emit SHRD32 instruction, from s1, fill s2 , constant c, store result in s1 using s3 and s4 as scratch void emit_shrd32c(dynarec_rv64_t* dyn, int ninst, rex_t rex, int s1, int s2, uint32_t c, int s3, int s4) { + c&=(rex.w?0x3f:0x1f); CLEAR_FLAGS(); IFX(X_PEND) { From 59492b7a3aa3375df666e5a5bea86473c33d0dce Mon Sep 17 00:00:00 2001 From: xctan Date: Sun, 24 Dec 2023 20:08:38 +0800 Subject: [PATCH 3/3] [DYNAREC_RV64] Fixed shamt mask of 16-bit shifts --- src/dynarec/rv64/dynarec_rv64_66.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/src/dynarec/rv64/dynarec_rv64_66.c b/src/dynarec/rv64/dynarec_rv64_66.c index d4e196c636..4f58ff9836 100644 --- a/src/dynarec/rv64/dynarec_rv64_66.c +++ b/src/dynarec/rv64/dynarec_rv64_66.c @@ -887,13 +887,13 @@ uintptr_t dynarec64_66(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t ip, int ni SETFLAGS(X_ALL, SF_PENDING); GETEW(x1, 1); u8 = F8; - UFLAG_IF {MOV32w(x2, (u8&0x1f));} + UFLAG_IF {MOV32w(x2, (u8&15));} UFLAG_OP12(ed, x2) if(MODREG) { - SLLI(ed, ed, 48+(u8&0x1f)); + SLLI(ed, ed, 48+(u8&15)); SRLI(ed, ed, 48); } else { - SLLI(ed, ed, u8&0x1f); + SLLI(ed, ed, u8&15); } EWBACK; UFLAG_RES(ed); @@ -905,9 +905,9 @@ uintptr_t dynarec64_66(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t ip, int ni SETFLAGS(X_ALL, SF_PENDING); GETEW(x1, 1); u8 = F8; - UFLAG_IF {MOV32w(x2, (u8&0x1f));} + UFLAG_IF {MOV32w(x2, (u8&15));} UFLAG_OP12(ed, x2) - SRLI(ed, ed, u8&0x1f); + SRLI(ed, ed, u8&15); EWBACK; UFLAG_RES(ed); UFLAG_DF(x3, d_shr16); @@ -918,9 +918,9 @@ uintptr_t dynarec64_66(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t ip, int ni UFLAG_IF {MESSAGE(LOG_DUMP, "Need Optimization for flags\n");} GETSEW(x1, 1); u8 = F8; - UFLAG_IF {MOV32w(x2, (u8&0x1f));} + UFLAG_IF {MOV32w(x2, (u8&15));} UFLAG_OP12(ed, x2) - SRAI(ed, ed, u8&0x1f); + SRAI(ed, ed, u8&15); if(MODREG) { ZEXTH(ed, ed); }