8000 Decode for sm4 and aes32 instructions, rs1==rd · Issue #65 · riscv/riscv-crypto · GitHub
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Decode for sm4 and aes32 instructions, rs1==rd #65
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Decode for sm4 and aes32 instructions, rs1==rd#65
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encodingSomething about an instruction's encoding.questionFurther information is requestedspecificationImprovements or additions to the specification
@JamesKenneyImperas

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@JamesKenneyImperas
JamesKenneyImperas
opened on Dec 4, 2020

Hi Ben,

I notice that these instructions are specified to require rs1==rd, with the intention that the number of encoding points is reduced.

I wonder whether it would be better just to require the rs1 field to be a specified constant (probably 0) instead? This would free up the same number of encoding points in a more useful manner.

James.

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