From 64ef6a8a237d438ecfb3c92d92be0fba84af4e3a Mon Sep 17 00:00:00 2001 From: Luca Boccassi Date: Tue, 13 Mar 2018 00:27:55 +0000 Subject: [PATCH 001/503] Change format to non-native, set myself as maintainer --- debian/changelog | 6 ++++++ debian/control | 6 +++--- debian/source/format | 2 +- 3 files changed, 10 insertions(+), 4 deletions(-) diff --git a/debian/changelog b/debian/changelog index ac18fd872..d55b32837 100644 --- a/debian/changelog +++ b/debian/changelog @@ -1,3 +1,9 @@ +stlink (1.5.0-1) UNRELEASED; urgency=medium + + * Upload to unstable. (Closes: #869421) + + -- Luca Boccassi Tue, 13 Mar 2018 00:26:52 +0000 + stlink (1.5.0) unstable; urgency=medium [ Jerry Jacobs ] diff --git a/debian/control b/debian/control index e33fc757c..db6f9e7e0 100644 --- a/debian/control +++ b/debian/control @@ -1,12 +1,12 @@ Source: stlink Priority: optional -Maintainer: Andrew 'Necromant' Andrianov +Maintainer: Luca Boccassi Build-Depends: debhelper (>= 9), cmake, libusb-1.0-0-dev, libgtk-3-dev Standards-Version: 4.1.3 Section: electronics Homepage: https://github.com/texane/stlink -Vcs-Git: https://github.com/texane/stlink.git -Vcs-Browser: https://github.com/texane/stlink +Vcs-Git: https://github.com/bluca/stlink.git +Vcs-Browser: https://github.com/bluca/stlink Package: libstlink-dev Section: libdevel diff --git a/debian/source/format b/debian/source/format index 89ae9db8f..163aaf8d8 100644 --- a/debian/source/format +++ b/debian/source/format @@ -1 +1 @@ -3.0 (native) +3.0 (quilt) From 848839034573498ed80e3290e119e1fcaa031dcc Mon Sep 17 00:00:00 2001 From: Luca Boccassi Date: Fri, 16 Mar 2018 16:13:53 +0000 Subject: [PATCH 002/503] Repack tarball to remove debian/ and stlinkv1_macosx_driver/ --- debian/changelog | 2 +- debian/copyright | 5 +++++ debian/watch | 2 +- 3 files changed, 7 insertions(+), 2 deletions(-) diff --git a/debian/changelog b/debian/changelog index d55b32837..3439e586c 100644 --- a/debian/changelog +++ b/debian/changelog @@ -1,4 +1,4 @@ -stlink (1.5.0-1) UNRELEASED; urgency=medium +stlink (1.5.0+ds-1) UNRELEASED; urgency=medium * Upload to unstable. (Closes: #869421) diff --git a/debian/copyright b/debian/copyright index 941a4a011..d56807ca5 100644 --- a/debian/copyright +++ b/debian/copyright @@ -2,6 +2,11 @@ Format: https://www.debian.org/doc/packaging-manuals/copyright-format/1.0/ Upstream-Name: stlink Upstream-Contact: Andrew 'Necromant' Andrianov Source: https://github.com/texane/stlink +Comment: Upstream tarball has been repackaged to remove binary OSX kernel + drivers that are of unknown license and of no use to Debian. + Upstream's debian directory is also removed. +Files-Excluded: stlinkv1_macosx_driver + debian Files: * Copyright: 2011-2018 agpanarin diff --git a/debian/watch b/debian/watch index cc653ca9f..921dc8f0d 100644 --- a/debian/watch +++ b/debian/watch @@ -1,3 +1,3 @@ version=3 -opts=filenamemangle=s/.+\/v?(\d\S+)\.tar\.gz/-$1\.tar\.gz/ \ +opts=dversionmangle=s/\+ds$//,repacksuffix=+ds,filenamemangle=s/.+\/v?(\d\S+)\.tar\.gz/-$1\.tar\.gz/ \ https://github.com/texane/stlink/tags .*/v?(\d\S+)\.tar\.gz From abdf4ce070b01586d82740922e86a16bb0206ba5 Mon Sep 17 00:00:00 2001 From: Luca Boccassi Date: Fri, 16 Mar 2018 16:20:26 +0000 Subject: [PATCH 003/503] Remove breaks and replaces, not applicable to Debian --- debian/control | 4 ---- 1 file changed, 4 deletions(-) diff --git a/debian/control b/debian/control index db6f9e7e0..3427359c6 100644 --- a/debian/control +++ b/debian/control @@ -22,8 +22,6 @@ Package: libstlink1 Section: libs Architecture: any Depends: ${shlibs:Depends}, ${misc:Depends} -Breaks: libstlink -Replaces: libstlink Description: OpenSource ST-Link tools replacement. Flashing tools for STMicroelectronics STM32VL and STM32L. The transport layers STLINKv1 and STLINKv2 are supported. @@ -33,8 +31,6 @@ Description: OpenSource ST-Link tools replacement. Package: stlink-tools Architecture: any Depends: libstlink1 (= ${binary:Version}), ${shlibs:Depends}, ${misc:Depends} -Breaks: libstlink -Replaces: libstlink Description: OpenSource ST-Link tools replacement. Flashing tools for STMicroelectronics STM32VL and STM32L. The transport layers STLINKv1 and STLINKv2 are supported. From ef9d527eb74231d1818ade3495f003b85bec5325 Mon Sep 17 00:00:00 2001 From: Luca Boccassi Date: Fri, 16 Mar 2018 16:56:19 +0000 Subject: [PATCH 004/503] Update changelog for 1.5.0+ds-1 release --- debian/changelog | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/debian/changelog b/debian/changelog index 3439e586c..798093c9e 100644 --- a/debian/changelog +++ b/debian/changelog @@ -1,8 +1,8 @@ -stlink (1.5.0+ds-1) UNRELEASED; urgency=medium +stlink (1.5.0+ds-1) unstable; urgency=medium * Upload to unstable. (Closes: #869421) - -- Luca Boccassi Tue, 13 Mar 2018 00:26:52 +0000 + -- Luca Boccassi Fri, 16 Mar 2018 16:56:17 +0000 stlink (1.5.0) unstable; urgency=medium From 66e5e3ac806c7c54ba2b7f9ecb24c037c95c98be Mon Sep 17 00:00:00 2001 From: Luca Boccassi Date: Fri, 28 Sep 2018 10:27:24 +0100 Subject: [PATCH 005/503] Mark packages as linux-any, other systems not supported. --- debian/control | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/debian/control b/debian/control index 3427359c6..da8f69203 100644 --- a/debian/control +++ b/debian/control @@ -10,7 +10,7 @@ Vcs-Browser: https://github.com/bluca/stlink Package: libstlink-dev Section: libdevel -Architecture: any +Architecture: linux-any Depends: libstlink1 (= ${binary:Version}), ${misc:Depends} Description: OpenSource ST-Link tools replacement. Flashing tools for STMicroelectronics STM32VL and STM32L. The transport layers @@ -20,7 +20,7 @@ Description: OpenSource ST-Link tools replacement. Package: libstlink1 Section: libs -Architecture: any +Architecture: linux-any Depends: ${shlibs:Depends}, ${misc:Depends} Description: OpenSource ST-Link tools replacement. Flashing tools for STMicroelectronics STM32VL and STM32L. The transport layers @@ -29,7 +29,7 @@ Description: OpenSource ST-Link tools replacement. This package contains the shared library for stlink. Package: stlink-tools -Architecture: any +Architecture: linux-any Depends: libstlink1 (= ${binary:Version}), ${shlibs:Depends}, ${misc:Depends} Description: OpenSource ST-Link tools replacement. Flashing tools for STMicroelectronics STM32VL and STM32L. The transport layers @@ -39,7 +39,7 @@ Description: OpenSource ST-Link tools replacement. udev rules. Package: stlink-gui -Architecture: any +Architecture: linux-any Depends: libstlink1 (= ${binary:Version}), stlink-tools (= ${binary:Version}), ${shlibs:Depends}, ${misc:Depends} Description: OpenSource ST-Link tools replacement. From acd192fea0e440ee91a643321417a7665ad7f248 Mon Sep 17 00:00:00 2001 From: Luca Boccassi Date: Fri, 28 Sep 2018 10:26:46 +0100 Subject: [PATCH 006/503] Update changelog for 1.5.1+ds-1 release --- debian/changelog | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/debian/changelog b/debian/changelog index 798093c9e..b0c877388 100644 --- a/debian/changelog +++ b/debian/changelog @@ -1,3 +1,11 @@ +stlink (1.5.1+ds-1) unstable; urgency=medium + + * Merge tag 'v1.5.1' into debian. See upstream changelog for info: + https://github.com/texane/stlink/releases/tag/v1.5.1 + * Mark packages as linux-any, other systems not supported. + + -- Luca Boccassi Fri, 28 Sep 2018 10:26:39 +0100 + stlink (1.5.0+ds-1) unstable; urgency=medium * Upload to unstable. (Closes: #869421) From 8a07f1276901e71a1df7ad0e664f80e73290048d Mon Sep 17 00:00:00 2001 From: Luca Boccassi Date: Fri, 28 Sep 2018 18:48:04 +0100 Subject: [PATCH 007/503] Mark library packages as Multi-Arch: same. --- debian/control | 2 ++ 1 file changed, 2 insertions(+) diff --git a/debian/control b/debian/control index da8f69203..1499dcf1a 100644 --- a/debian/control +++ b/debian/control @@ -11,6 +11,7 @@ Vcs-Browser: https://github.com/bluca/stlink Package: libstlink-dev Section: libdevel Architecture: linux-any +Multi-Arch: same Depends: libstlink1 (= ${binary:Version}), ${misc:Depends} Description: OpenSource ST-Link tools replacement. Flashing tools for STMicroelectronics STM32VL and STM32L. The transport layers @@ -21,6 +22,7 @@ Description: OpenSource ST-Link tools replacement. Package: libstlink1 Section: libs Architecture: linux-any +Multi-Arch: same Depends: ${shlibs:Depends}, ${misc:Depends} Description: OpenSource ST-Link tools replacement. Flashing tools for STMicroelectronics STM32VL and STM32L. The transport layers From bc01701a8d58a68fe78f6823813293fb3192d46a Mon Sep 17 00:00:00 2001 From: Luca Boccassi Date: Sun, 29 Sep 2019 12:42:14 +0100 Subject: [PATCH 008/503] Apply cross.patch to fix cross-compiling the GUI. Thanks Helmut for the patch! (Closes: #941320) Gbp-Dch: full --- debian/patches/cross.patch | 15 +++++++++++++++ debian/patches/series | 1 + 2 files changed, 16 insertions(+) create mode 100644 debian/patches/cross.patch create mode 100644 debian/patches/series diff --git a/debian/patches/cross.patch b/debian/patches/cross.patch new file mode 100644 index 000000000..92084238b --- /dev/null +++ b/debian/patches/cross.patch @@ -0,0 +1,15 @@ +Author: Helmut Grohne +Description: do not stop the GUI from being cross-compiled +Bug-Debian: 941320 +Forwarded: yes +--- a/CMakeLists.txt ++++ b/CMakeLists.txt +@@ -39,7 +39,7 @@ + # Dependencies + ### + find_package(LibUSB REQUIRED) +-if (NOT APPLE AND NOT WIN32 AND NOT CMAKE_CROSSCOMPILING) ++if (NOT APPLE AND NOT WIN32) + find_package(PkgConfig) + pkg_check_modules(gtk gtk+-3.0) + endif () diff --git a/debian/patches/series b/debian/patches/series new file mode 100644 index 000000000..def274a02 --- /dev/null +++ b/debian/patches/series @@ -0,0 +1 @@ +cross.patch From ecfb5becd0e091000ea8dc6058a214305b1b319b Mon Sep 17 00:00:00 2001 From: Luca Boccassi Date: Sun, 29 Sep 2019 12:44:22 +0100 Subject: [PATCH 009/503] Vcs-Git: add -b debian --- debian/control | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/debian/control b/debian/control index 1499dcf1a..5994ea084 100644 --- a/debian/control +++ b/debian/control @@ -5,7 +5,7 @@ Build-Depends: debhelper (>= 9), cmake, libusb-1.0-0-dev, libgtk-3-dev Standards-Version: 4.1.3 Section: electronics Homepage: https://github.com/texane/stlink -Vcs-Git: https://github.com/bluca/stlink.git +Vcs-Git: https://github.com/bluca/stlink.git -b debian Vcs-Browser: https://github.com/bluca/stlink Package: libstlink-dev From 52189af7a2274b7a57b4ae36454df62bf9e06b5d Mon Sep 17 00:00:00 2001 From: Luca Boccassi Date: Sun, 29 Sep 2019 12:45:57 +0100 Subject: [PATCH 010/503] Set Rules-Requires-Root: no --- debian/control | 1 + 1 file changed, 1 insertion(+) diff --git a/debian/control b/debian/control index 5994ea084..e38a046fd 100644 --- a/debian/control +++ b/debian/control @@ -3,6 +3,7 @@ Priority: optional Maintainer: Luca Boccassi Build-Depends: debhelper (>= 9), cmake, libusb-1.0-0-dev, libgtk-3-dev Standards-Version: 4.1.3 +Rules-Requires-Root: no Section: electronics Homepage: https://github.com/texane/stlink Vcs-Git: https://github.com/bluca/stlink.git -b debian From 4f29ef92bf5095f3152564319a2be4bda1d1d7df Mon Sep 17 00:00:00 2001 From: Luca Boccassi Date: Sun, 29 Sep 2019 12:48:53 +0100 Subject: [PATCH 011/503] Bump Standards-Version to 4.4.0 --- debian/control | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/debian/control b/debian/control index e38a046fd..c541d5bef 100644 --- a/debian/control +++ b/debian/control @@ -2,7 +2,7 @@ Source: stlink Priority: optional Maintainer: Luca Boccassi Build-Depends: debhelper (>= 9), cmake, libusb-1.0-0-dev, libgtk-3-dev -Standards-Version: 4.1.3 +Standards-Version: 4.4.0 Rules-Requires-Root: no Section: electronics Homepage: https://github.com/texane/stlink From 0b629606aaa7608656487eccf7dd55c647743e4e Mon Sep 17 00:00:00 2001 From: Luca Boccassi Date: Sun, 29 Sep 2019 12:51:05 +0100 Subject: [PATCH 012/503] Update changelog for 1.5.1+ds-2 release --- debian/changelog | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/debian/changelog b/debian/changelog index b0c877388..5d132ca55 100644 --- a/debian/changelog +++ b/debian/changelog @@ -1,3 +1,14 @@ +stlink (1.5.1+ds-2) unstable; urgency=medium + + * Mark library packages as Multi-Arch: same. + * Apply cross.patch to fix cross-compiling the GUI. Thanks Helmut for + the patch! (Closes: #941320) + * Vcs-Git: add -b debian + * Set Rules-Requires-Root: no + * Bump Standards-Version to 4.4.0 + + -- Luca Boccassi Sun, 29 Sep 2019 12:50:58 +0100 + stlink (1.5.1+ds-1) unstable; urgency=medium * Merge tag 'v1.5.1' into debian. See upstream changelog for info: From 14c2cbe0c6e15429fb8f02919c94ed976fbf371e Mon Sep 17 00:00:00 2001 From: Luca Boccassi Date: Tue, 25 Feb 2020 22:08:24 +0000 Subject: [PATCH 013/503] Bump Standards-Version to 4.5.0, no changes. --- debian/control | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/debian/control b/debian/control index c541d5bef..4382cdcd5 100644 --- a/debian/control +++ b/debian/control @@ -2,7 +2,7 @@ Source: stlink Priority: optional Maintainer: Luca Boccassi Build-Depends: debhelper (>= 9), cmake, libusb-1.0-0-dev, libgtk-3-dev -Standards-Version: 4.4.0 +Standards-Version: 4.5.0 Rules-Requires-Root: no Section: electronics Homepage: https://github.com/texane/stlink From d3021e569f2a151ba415d75a8984db17307b1170 Mon Sep 17 00:00:00 2001 From: Luca Boccassi Date: Tue, 25 Feb 2020 22:10:41 +0000 Subject: [PATCH 014/503] Add d/s/options to ignore repacked files Gbp-Dch: ignore --- debian/source/options | 1 + 1 file changed, 1 insertion(+) create mode 100644 debian/source/options diff --git a/debian/source/options b/debian/source/options new file mode 100644 index 000000000..7022977a9 --- /dev/null +++ b/debian/source/options @@ -0,0 +1 @@ +extend-diff-ignore=stlinkv1_macosx_driver From 00441133fa59e09ac8da87d25ee2bdabb2c6e720 Mon Sep 17 00:00:00 2001 From: Luca Boccassi Date: Tue, 25 Feb 2020 22:13:51 +0000 Subject: [PATCH 015/503] Update libstlink1 symbols file for 1.6.0. --- debian/libstlink1.symbols | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/debian/libstlink1.symbols b/debian/libstlink1.symbols index 51fa9bdb1..4518989a1 100644 --- a/debian/libstlink1.symbols +++ b/debian/libstlink1.symbols @@ -78,6 +78,8 @@ libstlink.so.1 libstlink1 #MINVER# stlink_force_debug@Base 1.5.0 stlink_fread@Base 1.5.0 stlink_fwrite_flash@Base 1.5.0 + stlink_fwrite_option_bytes@Base 1.6.0 + stlink_fwrite_option_bytes_32bit@Base 1.6.0 stlink_fwrite_sram@Base 1.5.0 stlink_get_erased_pattern@Base 1.5.0 stlink_is_core_halted@Base 1.5.0 @@ -95,6 +97,8 @@ libstlink.so.1 libstlink1 #MINVER# stlink_read_all_unsupported_regs@Base 1.5.0 stlink_read_debug32@Base 1.5.0 stlink_read_mem32@Base 1.5.0 + stlink_read_option_bytes_f2@Base 1.6.0 + stlink_read_option_bytes_f4@Base 1.6.0 stlink_read_reg@Base 1.5.0 stlink_read_unsupported_reg@Base 1.5.0 stlink_reset@Base 1.5.0 @@ -115,6 +119,7 @@ libstlink.so.1 libstlink1 #MINVER# stlink_write_flash@Base 1.5.0 stlink_write_mem32@Base 1.5.0 stlink_write_mem8@Base 1.5.0 + stlink_write_option_bytes@Base 1.6.0 stlink_write_reg@Base 1.5.0 stlink_write_unsupported_reg@Base 1.5.0 stm32l1_write_half_pages@Base 1.5.0 From f92878df5e2761cf38fc4719b18e288a0a1fa61e Mon Sep 17 00:00:00 2001 From: Luca Boccassi Date: Tue, 25 Feb 2020 22:08:48 +0000 Subject: [PATCH 016/503] Update changelog for 1.6.0+ds-1 release --- debian/changelog | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/debian/changelog b/debian/changelog index 5d132ca55..0ad68fed3 100644 --- a/debian/changelog +++ b/debian/changelog @@ -1,3 +1,11 @@ +stlink (1.6.0+ds-1) unstable; urgency=medium + + * Merge tag 'v1.6.0' into debian + * Bump Standards-Version to 4.5.0, no changes. + * Update libstlink1 symbols file for 1.6.0. + + -- Luca Boccassi Tue, 25 Feb 2020 22:08:33 +0000 + stlink (1.5.1+ds-2) unstable; urgency=medium * Mark library packages as Multi-Arch: same. From 4337408e0413e61b74be90fe46f9b0336acc7215 Mon Sep 17 00:00:00 2001 From: rutgerhendriks <3134550+rutgerhendriks@users.noreply.github.com> Date: Wed, 27 May 2020 15:59:44 +0200 Subject: [PATCH 017/503] Create ccpp.yml --- .github/workflows/ccpp.yml | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) create mode 100644 .github/workflows/ccpp.yml diff --git a/.github/workflows/ccpp.yml b/.github/workflows/ccpp.yml new file mode 100644 index 000000000..23aa0bfc5 --- /dev/null +++ b/.github/workflows/ccpp.yml @@ -0,0 +1,17 @@ +name: C/C++ CI + +on: + push: + branches: [ master ] + pull_request: + branches: [ master ] + +jobs: + build: + + runs-on: ubuntu-latest + + steps: + - uses: actions/checkout@v2 + - name: make + run: make From 2016590502558caa98c21abad2ce83c5f4804a98 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?S=C3=B6ren=20Tempel?= Date: Mon, 1 Jun 2020 00:20:26 +0200 Subject: [PATCH 018/503] doc/man: Fix installation directory On Unix-like operating systems man pages are commonly installed to `/usr/share/man` not `/usr/share/stlink/man`. --- doc/man/CMakeLists.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/doc/man/CMakeLists.txt b/doc/man/CMakeLists.txt index 23da9e150..9b3c50764 100644 --- a/doc/man/CMakeLists.txt +++ b/doc/man/CMakeLists.txt @@ -30,7 +30,7 @@ foreach (manpage ${MANPAGES}) endif () if (f AND NOT WIN32) - install(FILES ${f} DESTINATION ${CMAKE_INSTALL_DATAROOTDIR}/${PROJECT_NAME}/man/man1) + install(FILES ${f} DESTINATION ${CMAKE_INSTALL_DATAROOTDIR}/man/man1) unset(f) endif () endforeach () From e95b5ffcfe38c917a1f421c2257e58a3d9b2e8cc Mon Sep 17 00:00:00 2001 From: Vasiliy Glazov Date: Mon, 1 Jun 2020 08:44:11 +0300 Subject: [PATCH 019/503] Fix installation path for desktop-file and icons. This change fixes installation path for desktop-file and icons. They should be installed directly to ``` /usr/share/applications/ /usr/share/icons/hicolor/scalable/apps/ ``` --- src/stlink-gui/CMakeLists.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/stlink-gui/CMakeLists.txt b/src/stlink-gui/CMakeLists.txt index 8c36e5a1f..cc68509fe 100644 --- a/src/stlink-gui/CMakeLists.txt +++ b/src/stlink-gui/CMakeLists.txt @@ -13,11 +13,11 @@ if (NOT WIN32) # Install desktop application entry install(FILES stlink-gui.desktop - DESTINATION ${CMAKE_INSTALL_DATAROOTDIR}/${PROJECT_NAME}/applications) + DESTINATION ${CMAKE_INSTALL_DATAROOTDIR}/applications) # Install icons install(FILES icons/stlink-gui.svg - DESTINATION ${CMAKE_INSTALL_DATAROOTDIR}/${PROJECT_NAME}/icons/hicolor/scalable/apps) + DESTINATION ${CMAKE_INSTALL_DATAROOTDIR}/icons/hicolor/scalable/apps) set(GUI_SOURCES gui.c gui.h) From c774dca67676dbf06784ca088a6ff369ef4fe9ce Mon Sep 17 00:00:00 2001 From: Oleksiy Slyshyk Date: Tue, 2 Jun 2020 17:46:05 +0300 Subject: [PATCH 020/503] link ssp as static only for WIN32 --- CMakeLists.txt | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index 86282775e..ae7ddf971 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -71,7 +71,11 @@ include(CheckLibraryExists) CHECK_LIBRARY_EXISTS(ssp __stack_chk_fail "" _stack_chk_fail_exists) if (_stack_chk_fail_exists) - set(SSP_LIB -static ssp) + if(WIN32) + set(SSP_LIB -static ssp) + else() + set(SSP_LIB -static ssp) + endif() else () set(SSP_LIB "") endif () From b1af21d396e5888a4df802d9364f172cd9260846 Mon Sep 17 00:00:00 2001 From: Oleksiy Slyshyk Date: Tue, 2 Jun 2020 17:55:34 +0300 Subject: [PATCH 021/503] link ssp as static only for WIN32 --- CMakeLists.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index ae7ddf971..51d09412d 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -74,7 +74,7 @@ if (_stack_chk_fail_exists) if(WIN32) set(SSP_LIB -static ssp) else() - set(SSP_LIB -static ssp) + set(SSP_LIB ssp) endif() else () set(SSP_LIB "") From ade735dd671ea30ebbef36aaa17b51c6294425cf Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Wed, 3 Jun 2020 20:02:09 +0200 Subject: [PATCH 022/503] Moved unused pkg-config settings to /doc/dev (Closes #971) --- .gitignore | 2 +- CMakeLists.txt | 7 -- doc/compiling.md | 2 - doc/{ => dev}/app-example/CMakeLists.txt | 0 doc/{ => dev}/app-example/README.md | 0 doc/{ => dev}/app-example/main.c | 0 doc/{ => dev}/developer.txt | 115 ++++++++++-------- .../dev/pkg-config}/CMakeLists.txt | 0 .../dev/pkg-config}/pkgconfig.pc.cmake | 0 9 files changed, 67 insertions(+), 59 deletions(-) rename doc/{ => dev}/app-example/CMakeLists.txt (100%) rename doc/{ => dev}/app-example/README.md (100%) rename doc/{ => dev}/app-example/main.c (100%) rename doc/{ => dev}/developer.txt (93%) rename {cmake/pkgconfig => doc/dev/pkg-config}/CMakeLists.txt (100%) rename {cmake/pkgconfig => doc/dev/pkg-config}/pkgconfig.pc.cmake (100%) diff --git a/.gitignore b/.gitignore index 09b9b33de..229242a53 100644 --- a/.gitignore +++ b/.gitignore @@ -1,5 +1,5 @@ build build-mingw +.project obj-* *.user* -.project diff --git a/CMakeLists.txt b/CMakeLists.txt index 51d09412d..0538f3b14 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -47,13 +47,6 @@ endif () find_package(libusb REQUIRED) -## Package configuration (pkg-config) on unix-based systems -if (NOT WIN32 AND NOT CMAKE_CROSSCOMPILING) - #add_subdirectory(cmake/pkgconfig) - find_package(PkgConfig) - pkg_check_modules(GTK3 gtk+-3.0) -endif () - ## Check for system-specific additional header files and libraries include(CheckIncludeFile) diff --git a/doc/compiling.md b/doc/compiling.md index 428d9cc3c..c278c9ca8 100644 --- a/doc/compiling.md +++ b/doc/compiling.md @@ -88,7 +88,6 @@ Install the following packages from your package repository: * `build-essential` (on Debian based distros (Debian, Ubuntu)) * `cmake` (3.4.2 or later, use the latest version available from the repository) * `rpm` (on Debian based distros (Debian, Ubuntu), needed for package build with `make package`) -* `pkg-config` * `libusb-1.0` * `libusb-1.0-0-dev` (development headers for building) * `libgtk-3-dev` (_optional_, needed for `stlink-gui`) @@ -194,7 +193,6 @@ Then install the following dependencies from the package repository: * `git` * `gcc` or `llvm` (for clang) (C-compiler) * `cmake` -* `pkg-config` * `libusb` * `gtk+3` or `gtk3` (_optional_, needed for `stlink-gui`) diff --git a/doc/app-example/CMakeLists.txt b/doc/dev/app-example/CMakeLists.txt similarity index 100% rename from doc/app-example/CMakeLists.txt rename to doc/dev/app-example/CMakeLists.txt diff --git a/doc/app-example/README.md b/doc/dev/app-example/README.md similarity index 100% rename from doc/app-example/README.md rename to doc/dev/app-example/README.md diff --git a/doc/app-example/main.c b/doc/dev/app-example/main.c similarity index 100% rename from doc/app-example/main.c rename to doc/dev/app-example/main.c diff --git a/doc/developer.txt b/doc/dev/developer.txt similarity index 93% rename from doc/developer.txt rename to doc/dev/developer.txt index 2d05b9312..4032eca3e 100644 --- a/doc/developer.txt +++ b/doc/dev/developer.txt @@ -1,4 +1,21 @@ - +=== Compilation with pkg-config === + +In order to use pkg-config for development purposes, add the following lines to the toplevel CMakeLists.txt file: + +### +# Additional build tasks +### + +## Package configuration (pkg-config) on unix-based systems +if (NOT WIN32 AND NOT CMAKE_CROSSCOMPILING) + add_subdirectory(doc/dev/pkg-config) # Option A: external tool pkg-config + find_package(PkgConfig) # Option B: internal cmake module for pkg-config integration + pkg_check_modules(GTK3 gtk+-3.0) +endif () + +ToDo: Check for compatibility issues between options A and B. + + === Target Identification === The following information is available about the target: @@ -42,7 +59,7 @@ Include stlink/backend.h int (*current_mode) (stlink_t * stl); int (*force_debug) (stlink_t *sl); int32_t (*target_voltage) (stlink_t *sl); - int (*set_swdclk) (stlink_t * stl, uint16_t divisor); + int (*set_swdclk) (stlink_t * stl, uint16_t divisor); } stlink_backend_t; Descriptions below describe the actions of the usb.h backend: @@ -55,7 +72,7 @@ int (*exit_debug_mode) (stlink_t * sl); int (*enter_swd_mode) (stlink_t * sl); _stlink_usb_enter_swd_mode: Send STLINK_DEBUG_ENTER+STLINK_DEBUG_ENTER_SWD returns -1 or 0 - + int (*enter_jtag_mode) (stlink_t * stl); int (*exit_dfu_mode) (stlink_t * stl); @@ -65,19 +82,19 @@ int (*exit_dfu_mode) (stlink_t * stl); int (*core_id) (stlink_t * stl); _stlink_usb_core_id: Assign the result from STLINK_DEBUG_READCOREID to stl->core_id returns -1 or 0 - + int (*reset) (stlink_t * stl); _stlink_usb_reset: Send STLINK_DEBUG_RESETSYS and reset via AIRCR - AIRCR is part of the CMSIS System Control Block (SCB), which is located in + AIRCR is part of the CMSIS System Control Block (SCB), which is located in the System Control Space at 0xE000ED0C returns -1 or 0 ? - + int (*jtag_reset) (stlink_t * stl, int value); _stlink_usb_jtag_reset: Send STLINK_JTAG_DRIVE_NRST. "value" is sent as argument for STLINK_JTAG_DRIVE_NRST and probably contains the status of the NRST line (0: low, 1: high). Also the value 2 is used in the software. returns -1 or 0 - + int (*run) (stlink_t * stl); _stlink_usb_run: Send STLINK_DEBUG_RUNCORE returns -1 or 0 @@ -85,12 +102,12 @@ int (*run) (stlink_t * stl); int (*status) (stlink_t * stl); _stlink_usb_status: Assign the result from STLINK_DEBUG_GETSTATUS to stl->q_len returns -1 or 0 - + int (*version) (stlink_t *sl); _stlink_usb_version: Read version with STLINK_GET_VERSION. Result is stored in sl->q_buf (6 bytes????) returns -1 or 0 - + int (*read_debug32) (stlink_t *sl, uint32_t addr, uint32_t *data); _stlink_usb_read_debug32: Send STLINK_JTAG_READDEBUG_32BIT to read 32 bits from "addr". The result data is stored at "*data". @@ -99,10 +116,10 @@ int (*read_debug32) (stlink_t *sl, uint32_t addr, uint32_t *data); int (*read_mem32) (stlink_t *sl, uint32_t addr, uint16_t len); _stlink_usb_read_mem32: Use STLINK_DEBUG_READMEM_32BIT to read "len" bytes from "addr" - Result is returned in sl->q_buf, sl->q_len returns the size of the data (should be + Result is returned in sl->q_buf, sl->q_len returns the size of the data (should be equal to "len"???). returns -1 or 0 - + int (*write_debug32) (stlink_t *sl, uint32_t addr, uint32_t data); _stlink_usb_write_debug32: Use STLINK_JTAG_WRITEDEBUG_32BIT to store "data" at "addr" @@ -124,13 +141,13 @@ int (*read_all_regs) (stlink_t *sl, struct stlink_reg * regp); _stlink_usb_read_all_regs: Send STLINK_DEBUG_READALLREGS to read all register values and store them into *regp; returns -1 or 0 - + int (*read_reg) (stlink_t *sl, int r_idx, struct stlink_reg * regp); _stlink_usb_read_reg: Send STLINK_DEBUG_READREG to read specific register "r_idx". - The result is then stored in *regp in the correct register. + The result is then stored in *regp in the correct register. Example if "r_idx" is 18, then the result is stored in regp->process_sp returns -1 or 0 - + int (*read_all_unsupported_regs) (stlink_t *sl, struct stlink_reg *regp); _stlink_usb_read_all_unsupported_regs: Calls "_stlink_usb_read_unsupported_reg" (see below) to read all registers. @@ -142,7 +159,7 @@ int (*read_unsupported_reg) (stlink_t *sl, int r_idx, struct stlink_reg *regp); Also will fill regp->s (???) for some specific "r_idx" values. WARNING: Some r_idx values may lead to a out of array bound problem in C. returns -1 or 0 - + int (*write_unsupported_reg) (stlink_t *sl, uint32_t value, int idx, struct stlink_reg *regp); _stlink_usb_write_unsupported_reg: Updates one of the following registers: @@ -154,14 +171,14 @@ int (*write_unsupported_reg) (stlink_t *sl, uint32_t value, int idx, struct stli returns -1 or 0 int (*write_reg) (stlink_t *sl, uint32_t reg, int idx); - _stlink_usb_write_reg: Use STLINK_DEBUG_WRITEREG to update register "idx" + _stlink_usb_write_reg: Use STLINK_DEBUG_WRITEREG to update register "idx" with value "reg". returns -1 or 0 - + int (*step) (stlink_t * stl); _stlink_usb_step: Send STLINK_DEBUG_STEPCORE returns -1 or 0 - + int (*current_mode) (stlink_t * stl); _stlink_usb_current_mode: Send STLINK_GET_CURRENT_MODE and return the current mode. @@ -174,15 +191,15 @@ int (*current_mode) (stlink_t * stl); int (*force_debug) (stlink_t *sl); _stlink_usb_force_debug: Sends STLINK_DEBUG_FORCEDEBUG. No other side effects returns -1 or 0 - + int32_t (*target_voltage) (stlink_t *sl); _stlink_usb_target_voltage: Send STLINK_GET_TARGET_VOLTAGE returns -1 or the target voltage. (??? dimension is not clear...) -int (*set_swdclk) (stlink_t * stl, uint16_t divisor); +int (*set_swdclk) (stlink_t * stl, uint16_t divisor); _stlink_usb_set_swdclk: Send STLINK_DEBUG_APIV2_SWD_SET_FREQ and "divisor" value returns -1 or 0 - + === Other Functions === @@ -193,17 +210,17 @@ Include: stlink.h Prototype: void stlink_close(stlink_t *sl); Include: inc/stlink.h Definition: src/common.c -Description: +Description: Calls the backend "close" procedure and frees 'sl' Backend: "close" Arguments: sl: Pointer to the stlink data structure, returned by stlink_v1_open() or stlink_open_usb() Return: - - + Include: inc/stlink.h Prototype: int stlink_core_id(stlink_t *sl); Definition: src/common.c -Description: +Description: Calls the backend "core_id", calls stlink_print_data() on higher verbose levels. Assigns the core id returned by STLINK_DEBUGREADCOREID to sl->core_id Only some specific core ids are used: See include/stm32.h @@ -216,8 +233,8 @@ Return: -1 for error. 0 for success. Include: inc/stlink.h Prototype: int stlink_reset(stlink_t *sl); Definition: src/common.c -Description: - Just calls the backend "reset" procedure (reset via STLINK_DEBUG_RESETSYS +Description: + Just calls the backend "reset" procedure (reset via STLINK_DEBUG_RESETSYS and reset via AIRCR register at 0xE000ED0C) Backend: "reset" Arguments: @@ -227,29 +244,29 @@ Return: -1 for error. 0 for success. Include: inc/stlink.h Prototype: int stlink_jtag_reset(stlink_t *sl, int value); Definition: src/common.c -Description: - Just calls the backend "jtag_reset" procedure +Description: + Just calls the backend "jtag_reset" procedure Backend: "jtag_reset" Arguments: sl: Pointer to the stlink data structure, returned by stlink_v1_open() or stlink_open_usb() value: 0: drive low, 1: drive high, 2: ???? Return: -1 for error. 0 for success. - - + + Include: inc/stlink.h Prototype: int stlink_run(stlink_t *sl); Definition: src/common.c -Description: +Description: Just calls the backend "run" procedure. Backend: "run" Arguments: sl: Pointer to the stlink data structure, returned by stlink_v1_open() or stlink_open_usb() Return: -1 for error. 0 for success. - + Include: inc/stlink.h Prototype: int stlink_status(stlink_t *sl); Definition: src/common.c -Description: +Description: Calls the backend "status" procedure and the procedure "stlink_core_stat()" to store the status in "sl->core_stat". Possible value for "sl->core_stat" are: STLINK_CORE_RUNNING @@ -259,12 +276,12 @@ Backend: "status" Arguments: sl: Pointer to the stlink data structure, returned by stlink_v1_open() or stlink_open_usb() Return: -1 for error. 0 for success. - + Include: inc/stlink.h Prototype: int stlink_version(stlink_t *sl); Definition: src/common.c -Description: +Description: Calls the backend "version" procedure, parses the result and puts the result into sl->version This version probably refers to the version of the adapter. Backend: "version" @@ -272,9 +289,9 @@ Arguments: sl: Pointer to the stlink data structure, returned by stlink_v1_open() or stlink_open_usb() Return: -1 for error. 0 for success. - + int stlink_read_debug32(stlink_t *sl, uint32_t addr, uint32_t *data); - int stlink_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len); + int stlink_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len); int stlink_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data); int stlink_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len); int stlink_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len); @@ -305,9 +322,9 @@ Return: -1 for error. 0 for success. Include: inc/stlink.h Prototype: int stlink_chip_id(stlink_t *sl, uint32_t *chip_id); Definition: src/common.c -Description: +Description: Tries to read out the chip id via memory read from the device. - Note: sl->chip_id is NOT updated by this procedure. Instead this happens in stlink_load_device_params(): + Note: sl->chip_id is NOT updated by this procedure. Instead this happens in stlink_load_device_params(): Do not call this function, but instead call stlink_load_device_params() Backend: - Arguments: @@ -319,7 +336,7 @@ Return: -1 for error. 0 for success. Include: inc/stlink.h Prototype: int stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid); Definition: src/common.c -Description: +Description: Reads the CPU id from STLINK_REG_CM3_CPUID (0xE000ED00, first value of the SCB, system control block) and splits this into cpuid->implementer_id @@ -333,19 +350,19 @@ Arguments: cpuid: Pointer. Result is stored via this pointer. Return: -1 for error. 0 for success. - - + + int stlink_erase_flash_page(stlink_t* sl, stm32_addr_t flashaddr); uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr); uint16_t read_uint16(const unsigned char *c, const int pt); void stlink_core_stat(stlink_t *sl); - + Include: inc/stlink.h Prototype: void stlink_print_data(stlink_t *sl); Definition: src/common.c -Description: +Description: If debug logging is enabled: Print the HEX content of the q_buf array. q_buf will contain the result of the last "backend" command. Backend: - @@ -362,21 +379,21 @@ Return: - int write_buffer_to_sram(stlink_t *sl, flash_loader_t* fl, const uint8_t* buf, size_t size); int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size); int stlink_fread(stlink_t* sl, const char* path, bool is_ihex, stm32_addr_t addr, size_t size); - - + + Include: inc/stlink.h Prototype: int stlink_load_device_params(stlink_t *sl); Definition: src/common.c -Description: +Description: This is one of the most important procedures. It will get all the device info and store the results in the "sl" structure. Many other procedures will depend on this information. - The identification is based on the stlink_chip_id() result and the flash_size register value + The identification is based on the stlink_chip_id() result and the flash_size register value Backend: - Arguments: sl: Pointer to the stlink data structure, returned by stlink_v1_open() or stlink_open_usb() Return: -1 for error. 0 for success. - + int stlink_read_option_bytes_f2(stlink_t *sl, uint32_t* option_byte); int stlink_read_option_bytes_f4(stlink_t *sl, uint32_t* option_byte); diff --git a/cmake/pkgconfig/CMakeLists.txt b/doc/dev/pkg-config/CMakeLists.txt similarity index 100% rename from cmake/pkgconfig/CMakeLists.txt rename to doc/dev/pkg-config/CMakeLists.txt diff --git a/cmake/pkgconfig/pkgconfig.pc.cmake b/doc/dev/pkg-config/pkgconfig.pc.cmake similarity index 100% rename from cmake/pkgconfig/pkgconfig.pc.cmake rename to doc/dev/pkg-config/pkgconfig.pc.cmake From 8f42f5443852bfb062fdb858a157d88a800470a9 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Thu, 4 Jun 2020 12:50:02 +0200 Subject: [PATCH 023/503] Deleted duplicated issue template --- ...ort--only-valid-if-template-is-reused--.md | 38 ------------------- 1 file changed, 38 deletions(-) delete mode 100644 .github/ISSUE_TEMPLATE/bug-report--only-valid-if-template-is-reused--.md diff --git a/.github/ISSUE_TEMPLATE/bug-report--only-valid-if-template-is-reused--.md b/.github/ISSUE_TEMPLATE/bug-report--only-valid-if-template-is-reused--.md deleted file mode 100644 index 255596955..000000000 --- a/.github/ISSUE_TEMPLATE/bug-report--only-valid-if-template-is-reused--.md +++ /dev/null @@ -1,38 +0,0 @@ ---- -name: Bug Report (only valid if template is reused!) -about: 'Please read #906 before submitting a ticket.' -title: "[STM32 device name]: [Title]" -labels: '' -assignees: '' - ---- - -Thank you for giving feedback to the stlink project. - -In order to allow developers and other contributors to isolate and target your respective issue, please take some time to fill out each of the following items appropriate to your specific problem: - -- Programmer/board type: [enter here] (e.g Stlink /v1, /v2, /v2-clone, /v2-1) -- Programmer firmware version: [enter here] (e.g STSW-LINK007 2.27.15) -- Operating system and version: [enter here] (e.g Linux, Mac OS X, Windows) -- **Stlink tools version** and/or git commit hash: [enter here] (e.g v1.1.0/git-c722056) -- Stlink commandline tool name: [enter here] (e.g `st-info`, `st-flash`, `st-util`) -- Target chip (and board if applicable): [enter here] (e.g STM32F402VG) - -Futher we kindly ask you to describe the detected problem as detailed as possible and to add debug output if available, by using the following template: - -Commandline-Output: - -``` -OUTPUT/ERROR of the commandline tool(s) -``` - -Expected/description: - -`short description of the expected value` - - -**NOTICE: This bug report may be closed without further notice, if not enough information is provided!** - -Thank you for your support. - -The stlink project maintainers From 05f79e1cdf72a3a6ebdeac229842e39577e6700b Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Thu, 4 Jun 2020 21:33:34 +0200 Subject: [PATCH 024/503] [regression] Fixed GTK3 detection --- CMakeLists.txt | 2 +- doc/dev/developer.txt | 7 +------ src/stlink-gui/CMakeLists.txt | 7 ++++--- 3 files changed, 6 insertions(+), 10 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index 0538f3b14..4055110ad 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -140,7 +140,7 @@ endif () set(STLINK_LIBRARY_PATH ${CMAKE_INSTALL_LIBDIR} CACHE PATH "Main library install directory") # Set the environment variable LD_LIBRARY_PATH to point to /usr/local/lib (per default). -execute_process (COMMAND bash -c "export LD_LIBRARY_PATH="${CMAKE_INSTALL_LIBDIR}" ") +execute_process (COMMAND bash -c "export LD_LIBRARY_PATH=${CMAKE_INSTALL_LIBDIR}") ### diff --git a/doc/dev/developer.txt b/doc/dev/developer.txt index 4032eca3e..32afd4352 100644 --- a/doc/dev/developer.txt +++ b/doc/dev/developer.txt @@ -8,14 +8,9 @@ In order to use pkg-config for development purposes, add the following lines to ## Package configuration (pkg-config) on unix-based systems if (NOT WIN32 AND NOT CMAKE_CROSSCOMPILING) - add_subdirectory(doc/dev/pkg-config) # Option A: external tool pkg-config - find_package(PkgConfig) # Option B: internal cmake module for pkg-config integration - pkg_check_modules(GTK3 gtk+-3.0) + add_subdirectory(doc/dev/pkg-config) # external tool pkg-config endif () -ToDo: Check for compatibility issues between options A and B. - - === Target Identification === The following information is available about the target: diff --git a/src/stlink-gui/CMakeLists.txt b/src/stlink-gui/CMakeLists.txt index cc68509fe..89e5403d8 100644 --- a/src/stlink-gui/CMakeLists.txt +++ b/src/stlink-gui/CMakeLists.txt @@ -2,7 +2,10 @@ # Build GUI ### -if (NOT WIN32) +if (NOT WIN32 AND NOT CMAKE_CROSSCOMPILING) + find_package(PkgConfig) + pkg_check_modules(GTK3 gtk+-3.0) + ## GUI-Building requires the presence of a GTK3 toolset if (NOT GTK3_FOUND) message(STATUS "GTK3 not found!") @@ -35,7 +38,5 @@ if (NOT WIN32) COMPILE_DEFINITIONS STLINK_UI_DIR="${CMAKE_INSTALL_PREFIX}/bin") target_link_libraries(stlink-gui ${STLINK_LIB_SHARED} ${SSP_LIB} ${GTK3_LDFLAGS}) install(TARGETS stlink-gui DESTINATION ${CMAKE_INSTALL_BINDIR}) - - endif () endif () From c7041cc2be2582caca522c18babeb40aadcc246f Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Thu, 4 Jun 2020 21:53:17 +0200 Subject: [PATCH 025/503] Reorganised project source directories (Closes #976) --- CMakeLists.txt | 62 +++-- doc/dev/developer.txt | 4 +- inc/CMakeLists.txt | 9 + {include => inc}/stlink.h | 0 {include => inc}/stm32.h | 0 {include/stlink => inc}/version.h.in | 0 include/CMakeLists.txt | 9 - {include/stlink => src}/backend.h | 0 {include/stlink => src}/commands.h | 0 src/common.c | 6 +- src/{ => mmap}/mmap.c | 0 src/{ => mmap}/mmap.h | 0 {include/stlink => src}/reg.h | 0 src/{tools => st-flash}/flash.c | 2 +- .../stlink/tools => src/st-flash}/flash.h | 0 src/{tools => st-flash}/flash_opts.c | 2 +- src/{tools => st-info}/info.c | 0 src/st-util/semihosting.c | 59 ++--- src/stlink-gui/CMakeLists.txt | 7 +- src/{ => stlink-lib}/chipid.c | 2 +- {include/stlink => src/stlink-lib}/chipid.h | 0 src/{ => stlink-lib}/flash_loader.c | 243 +++++++++--------- .../stlink => src/stlink-lib}/flash_loader.h | 0 src/{ => stlink-lib}/logging.c | 0 src/{ => stlink-lib}/logging.h | 0 src/{ => stlink-lib}/md5.c | 0 src/{ => stlink-lib}/md5.h | 0 src/{ => stlink-lib}/sg.c | 1 + src/{ => stlink-lib}/sg.h | 2 +- src/{ => stlink-lib}/usb.c | 3 +- src/{ => stlink-lib}/usb.h | 2 +- tests/CMakeLists.txt | 2 +- 32 files changed, 193 insertions(+), 222 deletions(-) create mode 100644 inc/CMakeLists.txt rename {include => inc}/stlink.h (100%) rename {include => inc}/stm32.h (100%) rename {include/stlink => inc}/version.h.in (100%) delete mode 100644 include/CMakeLists.txt rename {include/stlink => src}/backend.h (100%) rename {include/stlink => src}/commands.h (100%) rename src/{ => mmap}/mmap.c (100%) rename src/{ => mmap}/mmap.h (100%) rename {include/stlink => src}/reg.h (100%) rename src/{tools => st-flash}/flash.c (99%) rename {include/stlink/tools => src/st-flash}/flash.h (100%) rename src/{tools => st-flash}/flash_opts.c (99%) rename src/{tools => st-info}/info.c (100%) rename src/{ => stlink-lib}/chipid.c (99%) rename {include/stlink => src/stlink-lib}/chipid.h (100%) rename src/{ => stlink-lib}/flash_loader.c (71%) rename {include/stlink => src/stlink-lib}/flash_loader.h (100%) rename src/{ => stlink-lib}/logging.c (100%) rename src/{ => stlink-lib}/logging.h (100%) rename src/{ => stlink-lib}/md5.c (100%) rename src/{ => stlink-lib}/md5.h (100%) rename src/{ => stlink-lib}/sg.c (99%) rename src/{ => stlink-lib}/sg.h (98%) rename src/{ => stlink-lib}/usb.c (99%) rename src/{ => stlink-lib}/usb.h (98%) diff --git a/CMakeLists.txt b/CMakeLists.txt index 0538f3b14..854ce9ed5 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -81,43 +81,41 @@ endif () ## Define include directories to avoid absolute paths for header defines include_directories(${LIBUSB_INCLUDE_DIR}) -# ==== -include_directories(${PROJECT_SOURCE_DIR}/include) ### TODO: Clean this up... -include_directories(${PROJECT_BINARY_DIR}/include/stlink) -include_directories(${PROJECT_SOURCE_DIR}/include/stlink) -include_directories(${PROJECT_SOURCE_DIR}/include/stlink/tools) -# ==== +include_directories(${PROJECT_SOURCE_DIR}/inc) # contains top-level header files +include_directories(${PROJECT_BINARY_DIR}/inc) # contains version.h include_directories(src) -include_directories(src/tools) ### TODO: Clean this up... +include_directories(src/mmap) +include_directories(src/st-flash) +include_directories(src/stlink-lib) set(STLINK_HEADERS - include/stlink.h - include/stlink/backend.h - include/stlink/chipid.h - include/stlink/commands.h - include/stlink/flash_loader.h - include/stlink/reg.h - src/logging.h - src/md5.h - src/sg.h - src/usb.h + inc/stlink.h + src/backend.h + src/commands.h + src/reg.h + src/stlink-lib/chipid.h + src/stlink-lib/flash_loader.h + src/stlink-lib/logging.h + src/stlink-lib/md5.h + src/stlink-lib/sg.h + src/stlink-lib/usb.h ) set(STLINK_SOURCE src/common.c - src/chipid.c - src/flash_loader.c - src/logging.c - src/md5.c - src/sg.c - src/usb.c + src/stlink-lib/chipid.c + src/stlink-lib/flash_loader.c + src/stlink-lib/logging.c + src/stlink-lib/md5.c + src/stlink-lib/sg.c + src/stlink-lib/usb.c ) if (WIN32 OR MINGW OR MSYS) include_directories(src/mingw) - set(STLINK_SOURCE "${STLINK_SOURCE};src/mmap.c;src/mingw/mingw.c") - set(STLINK_HEADERS "${STLINK_HEADERS};src/mmap.h;src/mingw/mingw.h") + set(STLINK_SOURCE "${STLINK_SOURCE};src/mmap/mmap.c;src/mingw/mingw.c") + set(STLINK_HEADERS "${STLINK_HEADERS};src/mmap/mmap.h;src/mingw/mingw.h") endif () if (MSVC) @@ -140,7 +138,7 @@ endif () set(STLINK_LIBRARY_PATH ${CMAKE_INSTALL_LIBDIR} CACHE PATH "Main library install directory") # Set the environment variable LD_LIBRARY_PATH to point to /usr/local/lib (per default). -execute_process (COMMAND bash -c "export LD_LIBRARY_PATH="${CMAKE_INSTALL_LIBDIR}" ") +execute_process (COMMAND bash -c "export LD_LIBRARY_PATH=${CMAKE_INSTALL_LIBDIR}") ### @@ -221,6 +219,8 @@ install(TARGETS ${STLINK_LIB_STATIC} ARCHIVE DESTINATION ${STLINK_LIBRARY_PATH}) # Build toolset executables ### +set(ST-FLASH_SOURCES src/st-flash/flash.c src/st-flash/flash_opts.c) +set(ST-INFO_SOURCES src/st-info/info.c) set(ST-UTIL_SOURCES src/st-util/gdb-remote.c src/st-util/gdb-server.c src/st-util/semihosting.c) if (MSVC) @@ -228,8 +228,8 @@ if (MSVC) set(ST-UTIL_SOURCES "${ST-UTIL_SOURCES};src/getopt/getopt.c") endif () -add_executable(st-flash src/tools/flash.c src/tools/flash_opts.c) -add_executable(st-info src/tools/info.c) +add_executable(st-flash ${ST-FLASH_SOURCES}) +add_executable(st-info ${ST-INFO_SOURCES}) add_executable(st-util ${ST-UTIL_SOURCES}) if (WIN32 OR APPLE) @@ -267,11 +267,7 @@ endif () # Additional build tasks ### -# ==== -add_subdirectory(include) # contains subordinate CMakeLists for version config and old header includes - ### TODO: Clean this up ... -# ==== - +add_subdirectory(inc) # contains subordinate CMakeLists for version config add_subdirectory(src/stlink-gui) # contains subordinate CMakeLists to build GUI add_subdirectory(tests) # contains subordinate CMakeLists to build test executables add_subdirectory(cmake/packaging) # contains subordinate CMakeLists to build packages diff --git a/doc/dev/developer.txt b/doc/dev/developer.txt index 4032eca3e..077234e54 100644 --- a/doc/dev/developer.txt +++ b/doc/dev/developer.txt @@ -8,9 +8,7 @@ In order to use pkg-config for development purposes, add the following lines to ## Package configuration (pkg-config) on unix-based systems if (NOT WIN32 AND NOT CMAKE_CROSSCOMPILING) - add_subdirectory(doc/dev/pkg-config) # Option A: external tool pkg-config - find_package(PkgConfig) # Option B: internal cmake module for pkg-config integration - pkg_check_modules(GTK3 gtk+-3.0) + add_subdirectory(doc/dev/pkg-config) # external tool pkg-config endif () ToDo: Check for compatibility issues between options A and B. diff --git a/inc/CMakeLists.txt b/inc/CMakeLists.txt new file mode 100644 index 000000000..66af7e33f --- /dev/null +++ b/inc/CMakeLists.txt @@ -0,0 +1,9 @@ +configure_file( + "${PROJECT_SOURCE_DIR}/inc/version.h.in" + "${CMAKE_BINARY_DIR}/inc/version.h" + ) + +file(GLOB STLINK_HEADERS "src/st-link-lib/*.h" "${CMAKE_BINARY_DIR}/inc/version.h") +install(FILES ${STLINK_HEADERS} DESTINATION ${STLINK_INCLUDE_PATH}) +install(FILES ${CMAKE_SOURCE_DIR}/inc/stlink.h DESTINATION ${STLINK_INCLUDE_PATH}) +install(FILES ${CMAKE_SOURCE_DIR}/inc/stm32.h DESTINATION ${STLINK_INCLUDE_PATH}) diff --git a/include/stlink.h b/inc/stlink.h similarity index 100% rename from include/stlink.h rename to inc/stlink.h diff --git a/include/stm32.h b/inc/stm32.h similarity index 100% rename from include/stm32.h rename to inc/stm32.h diff --git a/include/stlink/version.h.in b/inc/version.h.in similarity index 100% rename from include/stlink/version.h.in rename to inc/version.h.in diff --git a/include/CMakeLists.txt b/include/CMakeLists.txt deleted file mode 100644 index 6cf397659..000000000 --- a/include/CMakeLists.txt +++ /dev/null @@ -1,9 +0,0 @@ -configure_file( - "${PROJECT_SOURCE_DIR}/include/stlink/version.h.in" - "${CMAKE_BINARY_DIR}/include/stlink/version.h" - ) - -file(GLOB STLINK_HEADERS "stlink/*.h" "${CMAKE_BINARY_DIR}/include/stlink/*.h") -install(FILES ${CMAKE_SOURCE_DIR}/include/stlink.h DESTINATION ${STLINK_INCLUDE_PATH}) -install(FILES ${CMAKE_SOURCE_DIR}/include/stm32.h DESTINATION ${STLINK_INCLUDE_PATH}) -install(FILES ${STLINK_HEADERS} DESTINATION ${STLINK_INCLUDE_PATH}/stlink) diff --git a/include/stlink/backend.h b/src/backend.h similarity index 100% rename from include/stlink/backend.h rename to src/backend.h diff --git a/include/stlink/commands.h b/src/commands.h similarity index 100% rename from include/stlink/commands.h rename to src/commands.h diff --git a/src/common.c b/src/common.c index e8f7cebc6..fb669e255 100644 --- a/src/common.c +++ b/src/common.c @@ -12,9 +12,9 @@ #include #include -#include "mmap.h" -#include "logging.h" -#include "md5.h" +#include +#include +#include #ifndef O_BINARY #define O_BINARY 0 diff --git a/src/mmap.c b/src/mmap/mmap.c similarity index 100% rename from src/mmap.c rename to src/mmap/mmap.c diff --git a/src/mmap.h b/src/mmap/mmap.h similarity index 100% rename from src/mmap.h rename to src/mmap/mmap.h diff --git a/include/stlink/reg.h b/src/reg.h similarity index 100% rename from include/stlink/reg.h rename to src/reg.h diff --git a/src/tools/flash.c b/src/st-flash/flash.c similarity index 99% rename from src/tools/flash.c rename to src/st-flash/flash.c index 3a83daf8a..fc62bcf15 100644 --- a/src/tools/flash.c +++ b/src/st-flash/flash.c @@ -9,7 +9,7 @@ #include #include -#include +#include "flash.h" static stlink_t *connected_stlink = NULL; diff --git a/include/stlink/tools/flash.h b/src/st-flash/flash.h similarity index 100% rename from include/stlink/tools/flash.h rename to src/st-flash/flash.h diff --git a/src/tools/flash_opts.c b/src/st-flash/flash_opts.c similarity index 99% rename from src/tools/flash_opts.c rename to src/st-flash/flash_opts.c index c8d7841de..9d8d3225b 100644 --- a/src/tools/flash_opts.c +++ b/src/st-flash/flash_opts.c @@ -2,7 +2,7 @@ #include #include -#include +#include "flash.h" static bool starts_with(const char * str, const char * prefix) { size_t n = strlen(prefix); diff --git a/src/tools/info.c b/src/st-info/info.c similarity index 100% rename from src/tools/info.c rename to src/st-info/info.c diff --git a/src/st-util/semihosting.c b/src/st-util/semihosting.c index fed66ab60..cb03868cd 100644 --- a/src/st-util/semihosting.c +++ b/src/st-util/semihosting.c @@ -9,70 +9,52 @@ #include #include "semihosting.h" -static int mem_read_u8(stlink_t *sl, uint32_t addr, uint8_t *data) -{ +static int mem_read_u8(stlink_t *sl, uint32_t addr, uint8_t *data) { int offset = addr % 4; int len = 4; - if (sl == NULL || data == NULL) { - return -1; - } + if (sl == NULL || data == NULL) return -1; /* Read address and length must be aligned */ - if (stlink_read_mem32(sl, addr - offset, len) != 0) { - return -1; - } + if (stlink_read_mem32(sl, addr - offset, len) != 0) return -1; *data = sl->q_buf[offset]; return 0; } #ifdef UNUSED -static int mem_read_u16(stlink_t *sl, uint32_t addr, uint16_t *data) -{ +static int mem_read_u16(stlink_t *sl, uint32_t addr, uint16_t *data) { int offset = addr % 4; int len = (offset > 2 ? 8 : 4); - if (sl == NULL || data == NULL) { - return -1; - } + if (sl == NULL || data == NULL) return -1; /* Read address and length must be aligned */ - if (stlink_read_mem32(sl, addr - offset, len) != 0) { - return -1; - } + if (stlink_read_mem32(sl, addr - offset, len) != 0) return -1; memcpy(data, &sl->q_buf[offset], sizeof(*data)); return 0; } -static int mem_read_u32(stlink_t *sl, uint32_t addr, uint32_t *data) -{ +static int mem_read_u32(stlink_t *sl, uint32_t addr, uint32_t *data) { int offset = addr % 4; int len = (offset > 0 ? 8 : 4); - if (sl == NULL || data == NULL) { - return -1; - } + if (sl == NULL || data == NULL) return -1; /* Read address and length must be aligned */ - if (stlink_read_mem32(sl, addr - offset, len) != 0) { - return -1; - } + if (stlink_read_mem32(sl, addr - offset, len) != 0) return -1; memcpy(data, &sl->q_buf[offset], sizeof(*data)); return 0; } #endif -static int mem_read(stlink_t *sl, uint32_t addr, void *data, uint16_t len) -{ +static int mem_read(stlink_t *sl, uint32_t addr, void *data, uint16_t len) { int offset = addr % 4; int read_len = len + offset; - if (sl == NULL || data == NULL) { - return -1; - } + if (sl == NULL || data == NULL) return -1; /* Align read size */ if ((read_len % 4) != 0) { @@ -80,16 +62,13 @@ static int mem_read(stlink_t *sl, uint32_t addr, void *data, uint16_t len) } /* Address and length must be aligned */ - if (stlink_read_mem32(sl, addr - offset, read_len) != 0) { - return -1; - } + if (stlink_read_mem32(sl, addr - offset, read_len) != 0) return -1; memcpy(data, &sl->q_buf[offset], len); return 0; } -static int mem_write(stlink_t *sl, uint32_t addr, void *data, uint16_t len) -{ +static int mem_write(stlink_t *sl, uint32_t addr, void *data, uint16_t len) { // Note: this function can write more than it is asked to! // If addr is not an even 32 bit boundary, or len is not a multiple of 4. // @@ -106,9 +85,7 @@ static int mem_write(stlink_t *sl, uint32_t addr, void *data, uint16_t len) int offset = addr % 4; int write_len = len + offset; - if (sl == NULL || data == NULL) { - return -1; - } + if (sl == NULL || data == NULL) return -1; /* Align read size */ if ((write_len % 4) != 0) { @@ -118,9 +95,7 @@ static int mem_write(stlink_t *sl, uint32_t addr, void *data, uint16_t len) memcpy(&sl->q_buf[offset], data, len); /* Address and length must be aligned */ - if (stlink_write_mem32(sl, addr - offset, write_len) != 0) { - return -1; - } + if (stlink_write_mem32(sl, addr - offset, write_len) != 0) return -1; return 0; } @@ -162,9 +137,7 @@ static int saved_errno = 0; int do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { - if (sl == NULL || ret == NULL) { - return -1; - } + if (sl == NULL || ret == NULL) return -1; DLOG("Do semihosting R0=0x%08x R1=0x%08x\n", r0, r1); diff --git a/src/stlink-gui/CMakeLists.txt b/src/stlink-gui/CMakeLists.txt index cc68509fe..89e5403d8 100644 --- a/src/stlink-gui/CMakeLists.txt +++ b/src/stlink-gui/CMakeLists.txt @@ -2,7 +2,10 @@ # Build GUI ### -if (NOT WIN32) +if (NOT WIN32 AND NOT CMAKE_CROSSCOMPILING) + find_package(PkgConfig) + pkg_check_modules(GTK3 gtk+-3.0) + ## GUI-Building requires the presence of a GTK3 toolset if (NOT GTK3_FOUND) message(STATUS "GTK3 not found!") @@ -35,7 +38,5 @@ if (NOT WIN32) COMPILE_DEFINITIONS STLINK_UI_DIR="${CMAKE_INSTALL_PREFIX}/bin") target_link_libraries(stlink-gui ${STLINK_LIB_SHARED} ${SSP_LIB} ${GTK3_LDFLAGS}) install(TARGETS stlink-gui DESTINATION ${CMAKE_INSTALL_BINDIR}) - - endif () endif () diff --git a/src/chipid.c b/src/stlink-lib/chipid.c similarity index 99% rename from src/chipid.c rename to src/stlink-lib/chipid.c index fcc1c55eb..e6a82a2a9 100644 --- a/src/chipid.c +++ b/src/stlink-lib/chipid.c @@ -1,5 +1,5 @@ #include -#include +#include "chipid.h" static const struct stlink_chipid_params devices[] = { { diff --git a/include/stlink/chipid.h b/src/stlink-lib/chipid.h similarity index 100% rename from include/stlink/chipid.h rename to src/stlink-lib/chipid.h diff --git a/src/flash_loader.c b/src/stlink-lib/flash_loader.c similarity index 71% rename from src/flash_loader.c rename to src/stlink-lib/flash_loader.c index a2c5879ce..b97a6edaa 100644 --- a/src/flash_loader.c +++ b/src/stlink-lib/flash_loader.c @@ -3,6 +3,7 @@ #include #include +#include "flash_loader.h" #define FLASH_REGS_BANK2_OFS 0x40 #define FLASH_BANK2_START_ADDR 0x08080000 @@ -11,164 +12,164 @@ /* flashloaders/stm32f0.s -- compiled with thumb2 */ static const uint8_t loader_code_stm32vl[] = { - 0x16, 0x4f, 0x3c, 0x68, - 0x16, 0x4f, 0x3e, 0x68, - 0x36, 0x19, 0x16, 0x4f, - 0x3d, 0x68, 0x2d, 0x19, - 0x4f, 0xf0, 0x01, 0x07, - 0x33, 0x68, 0x3b, 0x43, - 0x33, 0x60, 0x03, 0x88, - 0x0b, 0x80, 0x4f, 0xf0, - 0x02, 0x07, 0xc0, 0x19, - 0xc9, 0x19, 0x4f, 0xf0, - 0x01, 0x07, 0x2b, 0x68, - 0x3b, 0x42, 0xfa, 0xd0, - 0x4f, 0xf0, 0x04, 0x07, - 0x3b, 0x42, 0x04, 0xd1, - 0x4f, 0xf0, 0x01, 0x07, - 0xd2, 0x1b, 0x00, 0x2a, - 0xe6, 0xd1, 0x4f, 0xf0, - 0x01, 0x07, 0x33, 0x68, - 0xbb, 0x43, 0x33, 0x60, - 0x00, 0xbe, 0x00, 0xbf, - 0x00, 0x20, 0x02, 0x40, - 0x10, 0x00, 0x00, 0x00, - 0x0c, 0x00, 0x00, 0x00, - 0x50, 0x00, 0x00, 0x20, - 0x54, 0x00, 0x00, 0x20, + 0x16, 0x4f, 0x3c, 0x68, + 0x16, 0x4f, 0x3e, 0x68, + 0x36, 0x19, 0x16, 0x4f, + 0x3d, 0x68, 0x2d, 0x19, + 0x4f, 0xf0, 0x01, 0x07, + 0x33, 0x68, 0x3b, 0x43, + 0x33, 0x60, 0x03, 0x88, + 0x0b, 0x80, 0x4f, 0xf0, + 0x02, 0x07, 0xc0, 0x19, + 0xc9, 0x19, 0x4f, 0xf0, + 0x01, 0x07, 0x2b, 0x68, + 0x3b, 0x42, 0xfa, 0xd0, + 0x4f, 0xf0, 0x04, 0x07, + 0x3b, 0x42, 0x04, 0xd1, + 0x4f, 0xf0, 0x01, 0x07, + 0xd2, 0x1b, 0x00, 0x2a, + 0xe6, 0xd1, 0x4f, 0xf0, + 0x01, 0x07, 0x33, 0x68, + 0xbb, 0x43, 0x33, 0x60, + 0x00, 0xbe, 0x00, 0xbf, + 0x00, 0x20, 0x02, 0x40, + 0x10, 0x00, 0x00, 0x00, + 0x0c, 0x00, 0x00, 0x00, + 0x50, 0x00, 0x00, 0x20, + 0x54, 0x00, 0x00, 0x20, 0x58, 0x00, 0x00, 0x20 }; /* flashloaders/stm32f0.s -- thumb1 only, same sequence as for STM32VL, bank ignored */ static const uint8_t loader_code_stm32f0[] = { - 0xc0, 0x46, 0xc0, 0x46, - 0x13, 0x4f, 0x3c, 0x68, - 0x13, 0x4f, 0x3e, 0x68, - 0x36, 0x19, 0x13, 0x4f, - 0x3d, 0x68, 0x2d, 0x19, - 0x12, 0x4f, 0x33, 0x68, - 0x3b, 0x43, 0x33, 0x60, - 0x03, 0x88, 0x0b, 0x80, - 0x10, 0x4f, 0xc0, 0x19, - 0xc9, 0x19, 0x0e, 0x4f, - 0x2b, 0x68, 0x3b, 0x42, - 0xfb, 0xd0, 0x0e, 0x4f, - 0x3b, 0x42, 0x03, 0xd1, - 0x0a, 0x4f, 0xd2, 0x1b, - 0x00, 0x2a, 0xeb, 0xd1, - 0x08, 0x4f, 0x33, 0x68, - 0xbb, 0x43, 0x33, 0x60, - 0x00, 0xbe, 0xc0, 0x46, - 0x00, 0x20, 0x02, 0x40, - 0x10, 0x00, 0x00, 0x00, - 0x0c, 0x00, 0x00, 0x00, - 0x48, 0x00, 0x00, 0x20, - 0x4c, 0x00, 0x00, 0x20, - 0x50, 0x00, 0x00, 0x20, - 0x01, 0x00, 0x00, 0x00, - 0x02, 0x00, 0x00, 0x00, + 0xc0, 0x46, 0xc0, 0x46, + 0x13, 0x4f, 0x3c, 0x68, + 0x13, 0x4f, 0x3e, 0x68, + 0x36, 0x19, 0x13, 0x4f, + 0x3d, 0x68, 0x2d, 0x19, + 0x12, 0x4f, 0x33, 0x68, + 0x3b, 0x43, 0x33, 0x60, + 0x03, 0x88, 0x0b, 0x80, + 0x10, 0x4f, 0xc0, 0x19, + 0xc9, 0x19, 0x0e, 0x4f, + 0x2b, 0x68, 0x3b, 0x42, + 0xfb, 0xd0, 0x0e, 0x4f, + 0x3b, 0x42, 0x03, 0xd1, + 0x0a, 0x4f, 0xd2, 0x1b, + 0x00, 0x2a, 0xeb, 0xd1, + 0x08, 0x4f, 0x33, 0x68, + 0xbb, 0x43, 0x33, 0x60, + 0x00, 0xbe, 0xc0, 0x46, + 0x00, 0x20, 0x02, 0x40, + 0x10, 0x00, 0x00, 0x00, + 0x0c, 0x00, 0x00, 0x00, + 0x48, 0x00, 0x00, 0x20, + 0x4c, 0x00, 0x00, 0x20, + 0x50, 0x00, 0x00, 0x20, + 0x01, 0x00, 0x00, 0x00, + 0x02, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00 }; static const uint8_t loader_code_stm32l[] = { // flashloaders/stm32lx.s - 0x03, 0x68, 0x0b, 0x60, - 0x4f, 0xf0, 0x04, 0x07, - 0x38, 0x44, 0x39, 0x44, - 0x4f, 0xf0, 0x01, 0x07, - 0xd2, 0x1b, 0x00, 0x2a, + 0x03, 0x68, 0x0b, 0x60, + 0x4f, 0xf0, 0x04, 0x07, + 0x38, 0x44, 0x39, 0x44, + 0x4f, 0xf0, 0x01, 0x07, + 0xd2, 0x1b, 0x00, 0x2a, 0xf4, 0xd1, 0x00, 0xbe, }; static const uint8_t loader_code_stm32f4[] = { // flashloaders/stm32f4.s - 0xdf, 0xf8, 0x28, 0xc0, - 0xdf, 0xf8, 0x28, 0xa0, - 0xe2, 0x44, 0x03, 0x68, - 0x0b, 0x60, 0x00, 0xf1, - 0x04, 0x00, 0x01, 0xf1, - 0x04, 0x01, 0xba, 0xf8, - 0x00, 0x30, 0x13, 0xf0, - 0x01, 0x0f, 0xfa, 0xd0, - 0xa2, 0xf1, 0x01, 0x02, - 0x00, 0x2a, 0xf0, 0xd1, - 0x00, 0xbe, 0x00, 0xbf, - 0x00, 0x3c, 0x02, 0x40, + 0xdf, 0xf8, 0x28, 0xc0, + 0xdf, 0xf8, 0x28, 0xa0, + 0xe2, 0x44, 0x03, 0x68, + 0x0b, 0x60, 0x00, 0xf1, + 0x04, 0x00, 0x01, 0xf1, + 0x04, 0x01, 0xba, 0xf8, + 0x00, 0x30, 0x13, 0xf0, + 0x01, 0x0f, 0xfa, 0xd0, + 0xa2, 0xf1, 0x01, 0x02, + 0x00, 0x2a, 0xf0, 0xd1, + 0x00, 0xbe, 0x00, 0xbf, + 0x00, 0x3c, 0x02, 0x40, 0x0e, 0x00, 0x00, 0x00 }; static const uint8_t loader_code_stm32f4_lv[] = { // flashloaders/stm32f4lv.s - 0xdf, 0xf8, 0x2c, 0xc0, - 0xdf, 0xf8, 0x2c, 0xa0, - 0xe2, 0x44, 0x4f, 0xea, - 0x82, 0x02, 0x03, 0x78, - 0x0b, 0x70, 0x00, 0xf1, - 0x01, 0x00, 0x01, 0xf1, - 0x01, 0x01, 0xba, 0xf8, - 0x00, 0x30, 0x13, 0xf0, - 0x01, 0x0f, 0xfa, 0xd0, - 0xa2, 0xf1, 0x01, 0x02, - 0x00, 0x2a, 0xf0, 0xd1, - 0x00, 0xbe, 0x00, 0xbf, - 0x00, 0x3c, 0x02, 0x40, + 0xdf, 0xf8, 0x2c, 0xc0, + 0xdf, 0xf8, 0x2c, 0xa0, + 0xe2, 0x44, 0x4f, 0xea, + 0x82, 0x02, 0x03, 0x78, + 0x0b, 0x70, 0x00, 0xf1, + 0x01, 0x00, 0x01, 0xf1, + 0x01, 0x01, 0xba, 0xf8, + 0x00, 0x30, 0x13, 0xf0, + 0x01, 0x0f, 0xfa, 0xd0, + 0xa2, 0xf1, 0x01, 0x02, + 0x00, 0x2a, 0xf0, 0xd1, + 0x00, 0xbe, 0x00, 0xbf, + 0x00, 0x3c, 0x02, 0x40, 0x0e, 0x00, 0x00, 0x00 }; static const uint8_t loader_code_stm32l4[] = { // flashloaders/stm32l4.s - 0xdf, 0xf8, 0x2c, 0xc0, - 0xdf, 0xf8, 0x2c, 0xa0, - 0xe2, 0x44, 0x03, 0x68, - 0x44, 0x68, 0x0b, 0x60, - 0x4c, 0x60, 0x00, 0xf1, - 0x08, 0x00, 0x01, 0xf1, - 0x08, 0x01, 0xba, 0xf8, - 0x00, 0x30, 0x13, 0xf0, - 0x01, 0x0f, 0xfa, 0xd0, - 0xa2, 0xf1, 0x01, 0x02, - 0x00, 0x2a, 0xee, 0xd1, - 0x00, 0xbe, 0x00, 0xbf, - 0x00, 0x20, 0x02, 0x40, + 0xdf, 0xf8, 0x2c, 0xc0, + 0xdf, 0xf8, 0x2c, 0xa0, + 0xe2, 0x44, 0x03, 0x68, + 0x44, 0x68, 0x0b, 0x60, + 0x4c, 0x60, 0x00, 0xf1, + 0x08, 0x00, 0x01, 0xf1, + 0x08, 0x01, 0xba, 0xf8, + 0x00, 0x30, 0x13, 0xf0, + 0x01, 0x0f, 0xfa, 0xd0, + 0xa2, 0xf1, 0x01, 0x02, + 0x00, 0x2a, 0xee, 0xd1, + 0x00, 0xbe, 0x00, 0xbf, + 0x00, 0x20, 0x02, 0x40, 0x12, 0x00, 0x00, 0x00 }; static const uint8_t loader_code_stm32f7[] = { // flashloaders/stm32f7.s - 0xdf, 0xf8, 0x2c, 0xc0, - 0xdf, 0xf8, 0x2c, 0xa0, - 0xe2, 0x44, 0x03, 0x68, - 0x0b, 0x60, 0x00, 0xf1, - 0x04, 0x00, 0x01, 0xf1, - 0x04, 0x01, 0xbf, 0xf3, - 0x4f, 0x8f, 0xba, 0xf8, - 0x00, 0x30, 0x13, 0xf0, - 0x01, 0x0f, 0xfa, 0xd0, - 0xa2, 0xf1, 0x01, 0x02, - 0x00, 0x2a, 0xee, 0xd1, - 0x00, 0xbe, 0x00, 0xbf, - 0x00, 0x3c, 0x02, 0x40, + 0xdf, 0xf8, 0x2c, 0xc0, + 0xdf, 0xf8, 0x2c, 0xa0, + 0xe2, 0x44, 0x03, 0x68, + 0x0b, 0x60, 0x00, 0xf1, + 0x04, 0x00, 0x01, 0xf1, + 0x04, 0x01, 0xbf, 0xf3, + 0x4f, 0x8f, 0xba, 0xf8, + 0x00, 0x30, 0x13, 0xf0, + 0x01, 0x0f, 0xfa, 0xd0, + 0xa2, 0xf1, 0x01, 0x02, + 0x00, 0x2a, 0xee, 0xd1, + 0x00, 0xbe, 0x00, 0xbf, + 0x00, 0x3c, 0x02, 0x40, 0x0e, 0x00, 0x00, 0x00 }; static const uint8_t loader_code_stm32f7_lv[] = { // flashloaders/stm32f7lv.s - 0xdf, 0xf8, 0x30, 0xc0, - 0xdf, 0xf8, 0x30, 0xa0, - 0xe2, 0x44, 0x4f, 0xea, - 0x82, 0x02, 0x03, 0x78, - 0x0b, 0x70, 0x00, 0xf1, - 0x01, 0x00, 0x01, 0xf1, - 0x01, 0x01, 0xbf, 0xf3, - 0x4f, 0x8f, 0xba, 0xf8, - 0x00, 0x30, 0x13, 0xf0, - 0x01, 0x0f, 0xfa, 0xd0, - 0xa2, 0xf1, 0x01, 0x02, - 0x00, 0x2a, 0xee, 0xd1, - 0x00, 0xbe, 0x00, 0xbf, - 0x00, 0x3c, 0x02, 0x40, + 0xdf, 0xf8, 0x30, 0xc0, + 0xdf, 0xf8, 0x30, 0xa0, + 0xe2, 0x44, 0x4f, 0xea, + 0x82, 0x02, 0x03, 0x78, + 0x0b, 0x70, 0x00, 0xf1, + 0x01, 0x00, 0x01, 0xf1, + 0x01, 0x01, 0xbf, 0xf3, + 0x4f, 0x8f, 0xba, 0xf8, + 0x00, 0x30, 0x13, 0xf0, + 0x01, 0x0f, 0xfa, 0xd0, + 0xa2, 0xf1, 0x01, 0x02, + 0x00, 0x2a, 0xee, 0xd1, + 0x00, 0xbe, 0x00, 0xbf, + 0x00, 0x3c, 0x02, 0x40, 0x0e, 0x00, 0x00, 0x00 }; diff --git a/include/stlink/flash_loader.h b/src/stlink-lib/flash_loader.h similarity index 100% rename from include/stlink/flash_loader.h rename to src/stlink-lib/flash_loader.h diff --git a/src/logging.c b/src/stlink-lib/logging.c similarity index 100% rename from src/logging.c rename to src/stlink-lib/logging.c diff --git a/src/logging.h b/src/stlink-lib/logging.h similarity index 100% rename from src/logging.h rename to src/stlink-lib/logging.h diff --git a/src/md5.c b/src/stlink-lib/md5.c similarity index 100% rename from src/md5.c rename to src/stlink-lib/md5.c diff --git a/src/md5.h b/src/stlink-lib/md5.h similarity index 100% rename from src/md5.h rename to src/stlink-lib/md5.h diff --git a/src/sg.c b/src/stlink-lib/sg.c similarity index 99% rename from src/sg.c rename to src/stlink-lib/sg.c index 798cda9ab..7fae19976 100644 --- a/src/sg.c +++ b/src/stlink-lib/sg.c @@ -84,6 +84,7 @@ #include #include "logging.h" +#include "sg.h" #define STLINK_OK 0x80 #define STLINK_FALSE 0x81 diff --git a/src/sg.h b/src/stlink-lib/sg.h similarity index 98% rename from src/sg.h rename to src/stlink-lib/sg.h index 3a8a7a239..811b339c7 100644 --- a/src/sg.h +++ b/src/stlink-lib/sg.h @@ -8,8 +8,8 @@ #ifndef STLINK_SG_H #define STLINK_SG_H -#include "libusb_settings.h" #include +#include #ifdef __cplusplus extern "C" { diff --git a/src/usb.c b/src/stlink-lib/usb.c similarity index 99% rename from src/usb.c rename to src/stlink-lib/usb.c index a711749da..b76639731 100644 --- a/src/usb.c +++ b/src/stlink-lib/usb.c @@ -14,6 +14,7 @@ #include #endif #include +#include "usb.h" enum SCSI_Generic_Direction {SG_DXFER_TO_DEV=0, SG_DXFER_FROM_DEV=0x80}; @@ -1147,7 +1148,7 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, int reset, char serial[STL if (reset == 2) { stlink_jtag_reset(sl,0); - if (stlink_current_mode(sl) != STLINK_DEV_DEBUG_MODE) stlink_enter_swd_mode(sl); + if (stlink_current_mode(sl) != STLINK_DEV_DEBUG_MODE) stlink_enter_swd_mode(sl); stlink_force_debug(sl); stlink_jtag_reset(sl,1); usleep(10000); diff --git a/src/usb.h b/src/stlink-lib/usb.h similarity index 98% rename from src/usb.h rename to src/stlink-lib/usb.h index 5c1f5b7ca..3581eabf1 100644 --- a/src/usb.h +++ b/src/stlink-lib/usb.h @@ -11,7 +11,7 @@ #include #include -#include "libusb_settings.h" +#include #include "logging.h" #ifdef __cplusplus diff --git a/tests/CMakeLists.txt b/tests/CMakeLists.txt index 6e60fdd5a..a3011fc7e 100644 --- a/tests/CMakeLists.txt +++ b/tests/CMakeLists.txt @@ -11,6 +11,6 @@ foreach (test ${TESTEXEC}) add_test(test-${test} ${CMAKE_BINARY_DIR}/bin/test-${test}) endforeach () -add_executable(test-flash flash.c "${CMAKE_SOURCE_DIR}/src/tools/flash_opts.c") +add_executable(test-flash flash.c "${CMAKE_SOURCE_DIR}/src/st-flash/flash_opts.c") target_link_libraries(test-flash ${STLINK_LIB_SHARED} ${SSP_LIB}) add_test(test-flash ${CMAKE_BINARY_DIR}/bin/test-flash) From e895a7c85e8150bf6874f7831d3bee247418091b Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Fri, 5 Jun 2020 16:41:47 +0200 Subject: [PATCH 026/503] [refactoring] Build settings for win32 - Grouped source files for win32 - Whitespace & code style cleanup --- CMakeLists.txt | 62 ++++--- src/common.c | 100 ++++++------ src/mmap/mmap.h | 31 ---- src/st-util/gdb-remote.c | 4 +- src/st-util/gdb-server.c | 2 +- src/stlink-lib/usb.c | 5 +- src/{ => win32}/getopt/LICENSE.txt | 0 src/{ => win32}/getopt/README.md | 0 src/{ => win32}/getopt/getopt.c | 0 src/{ => win32}/getopt/getopt.h | 0 src/{mmap => win32}/mmap.c | 1 - src/win32/mmap.h | 29 ++++ src/win32/{ => unistd}/unistd.h | 0 src/{mingw/mingw.c => win32/win32_socket.c} | 171 +++++++++----------- src/{mingw/mingw.h => win32/win32_socket.h} | 20 +-- 15 files changed, 206 insertions(+), 219 deletions(-) delete mode 100644 src/mmap/mmap.h rename src/{ => win32}/getopt/LICENSE.txt (100%) rename src/{ => win32}/getopt/README.md (100%) rename src/{ => win32}/getopt/getopt.c (100%) rename src/{ => win32}/getopt/getopt.h (100%) rename src/{mmap => win32}/mmap.c (99%) create mode 100644 src/win32/mmap.h rename src/win32/{ => unistd}/unistd.h (100%) rename src/{mingw/mingw.c => win32/win32_socket.c} (59%) rename src/{mingw/mingw.h => win32/win32_socket.h} (81%) diff --git a/CMakeLists.txt b/CMakeLists.txt index 854ce9ed5..c1ced137d 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -48,29 +48,34 @@ endif () find_package(libusb REQUIRED) ## Check for system-specific additional header files and libraries + include(CheckIncludeFile) +include(CheckLibraryExists) + +CHECK_LIBRARY_EXISTS(ssp __stack_chk_fail "" _stack_chk_fail_exists) +if (_stack_chk_fail_exists) + if (WIN32) + set(SSP_LIB -static ssp) + else () + set(SSP_LIB ssp) + endif () +else () + set(SSP_LIB "") +endif () CHECK_INCLUDE_FILE(sys/mman.h STLINK_HAVE_SYS_MMAN_H) if (STLINK_HAVE_SYS_MMAN_H) add_definitions(-DSTLINK_HAVE_SYS_MMAN_H) -endif () +endif() CHECK_INCLUDE_FILE(unistd.h STLINK_HAVE_UNISTD_H) if (STLINK_HAVE_UNISTD_H) add_definitions(-DSTLINK_HAVE_UNISTD_H) endif () -include(CheckLibraryExists) - -CHECK_LIBRARY_EXISTS(ssp __stack_chk_fail "" _stack_chk_fail_exists) -if (_stack_chk_fail_exists) - if(WIN32) - set(SSP_LIB -static ssp) - else() - set(SSP_LIB ssp) - endif() -else () - set(SSP_LIB "") +if (MSVC) + # Use string.h rather than strings.h and disable annoying warnings + add_definitions(-DHAVE_STRING_H -D_CRT_SECURE_NO_WARNINGS -D_CRT_NONSTDC_NO_WARNINGS /wd4710) endif () @@ -85,10 +90,14 @@ include_directories(${PROJECT_SOURCE_DIR}/inc) # contains top-level header files include_directories(${PROJECT_BINARY_DIR}/inc) # contains version.h include_directories(src) -include_directories(src/mmap) include_directories(src/st-flash) include_directories(src/stlink-lib) +if (MSVC) + include_directories(src/win32) + include_directories(src/win32/unistd) +endif () + set(STLINK_HEADERS inc/stlink.h src/backend.h @@ -112,17 +121,21 @@ set(STLINK_SOURCE src/stlink-lib/usb.c ) -if (WIN32 OR MINGW OR MSYS) - include_directories(src/mingw) - set(STLINK_SOURCE "${STLINK_SOURCE};src/mmap/mmap.c;src/mingw/mingw.c") - set(STLINK_HEADERS "${STLINK_HEADERS};src/mmap/mmap.h;src/mingw/mingw.h") -endif () - -if (MSVC) +if (WIN32) include_directories(src/win32) - include_directories(src/getopt) - # Use string.h rather than strings.h and disable annoying warnings - add_definitions(-DHAVE_STRING_H -D_CRT_SECURE_NO_WARNINGS -D_CRT_NONSTDC_NO_WARNINGS /wd4710) + set(STLINK_SOURCE "${STLINK_SOURCE};src/win32/win32_socket.c") + set(STLINK_HEADERS "${STLINK_HEADERS};src/win32/win32_socket.h") + + if (MSVC) + include_directories(src/win32/unistd) + set(STLINK_HEADERS "${STLINK_HEADERS};src/win32/unistd/unistd.h") + endif () + + if (NOT STLINK_HAVE_SYS_MMAN_H) + include_directories(src/win32/mmap) + set(STLINK_SOURCE "${STLINK_SOURCE};src/win32/mmap.c") + set(STLINK_HEADERS "${STLINK_HEADERS};src/win32/mmap.h") + endif() endif () ## Include test execution for test-targets for target Debug @@ -225,7 +238,8 @@ set(ST-UTIL_SOURCES src/st-util/gdb-remote.c src/st-util/gdb-server.c src/st-uti if (MSVC) # Add getopt to sources - set(ST-UTIL_SOURCES "${ST-UTIL_SOURCES};src/getopt/getopt.c") + include_directories(src/win32/getopt) + set(ST-UTIL_SOURCES "${ST-UTIL_SOURCES};src/win32/getopt/getopt.c") endif () add_executable(st-flash ${ST-FLASH_SOURCES}) diff --git a/src/common.c b/src/common.c index fb669e255..c9a54cf9f 100644 --- a/src/common.c +++ b/src/common.c @@ -12,10 +12,15 @@ #include #include -#include #include #include +#ifdef STLINK_HAVE_SYS_MMAN_H +#include +#else +#include +#endif + #ifndef O_BINARY #define O_BINARY 0 #endif @@ -193,24 +198,26 @@ #define STM32L4_FLASH_CR (FLASH_REGS_ADDR + 0x14) #define STM32L4_FLASH_OPTR (FLASH_REGS_ADDR + 0x20) -#define STM32L4_FLASH_SR_BSY 16 -#define STM32L4_FLASH_SR_ERRMASK 0x3f8 /* SR [9:3] */ - -#define STM32L4_FLASH_CR_LOCK 31 /* Lock control register */ -#define STM32L4_FLASH_CR_OPTLOCK 30 /* Lock option bytes */ -#define STM32L4_FLASH_CR_PG 0 /* Program */ -#define STM32L4_FLASH_CR_PER 1 /* Page erase */ -#define STM32L4_FLASH_CR_MER1 2 /* Bank 1 erase */ -#define STM32L4_FLASH_CR_MER2 15 /* Bank 2 erase */ -#define STM32L4_FLASH_CR_STRT 16 /* Start command */ -#define STM32L4_FLASH_CR_OPTSTRT 17 /* Start writing option bytes */ -#define STM32L4_FLASH_CR_BKER 11 /* Bank select for page erase */ -#define STM32L4_FLASH_CR_PNB 3 /* Page number (8 bits) */ -#define STM32L4_FLASH_CR_OBL_LAUNCH 27 /* Option bytes reload */ +#define STM32L4_FLASH_SR_BSY 16 +#define STM32L4_FLASH_SR_ERRMASK 0x3f8 /* SR [9:3] */ + +#define STM32L4_FLASH_CR_LOCK 31 /* Lock control register */ +#define STM32L4_FLASH_CR_OPTLOCK 30 /* Lock option bytes */ +#define STM32L4_FLASH_CR_PG 0 /* Program */ +#define STM32L4_FLASH_CR_PER 1 /* Page erase */ +#define STM32L4_FLASH_CR_MER1 2 /* Bank 1 erase */ +#define STM32L4_FLASH_CR_MER2 15 /* Bank 2 erase */ +#define STM32L4_FLASH_CR_STRT 16 /* Start command */ +#define STM32L4_FLASH_CR_OPTSTRT 17 /* Start writing option bytes */ +#define STM32L4_FLASH_CR_BKER 11 /* Bank select for page erase */ +#define STM32L4_FLASH_CR_PNB 3 /* Page number (8 bits) */ +#define STM32L4_FLASH_CR_OBL_LAUNCH 27 /* Option bytes reload */ // Bits requesting flash operations (useful when we want to clear them) -#define STM32L4_FLASH_CR_OPBITS \ - (uint32_t)((1lu<flash_type == STLINK_FLASH_TYPE_F4) { cr_reg = FLASH_F4_CR; - x |= 1 << FLASH_CR_PG; + x |= (1 << FLASH_CR_PG); } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { cr_reg = STM32L4_FLASH_CR; x &= ~STM32L4_FLASH_CR_OPBITS; - x |= 1 << STM32L4_FLASH_CR_PG; + x |= (1 << STM32L4_FLASH_CR_PG); } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || sl->flash_type == STLINK_FLASH_TYPE_G4) { cr_reg = STM32Gx_FLASH_CR; @@ -662,7 +668,7 @@ static void set_flash_cr_pg(stlink_t *sl) { x |= (1 << FLASH_CR_PG); } else { cr_reg = FLASH_CR; - x = 1 << FLASH_CR_PG; + x = (1 << FLASH_CR_PG); } stlink_write_debug32(sl, cr_reg, x); @@ -704,7 +710,7 @@ static void set_flash_cr_per(stlink_t *sl) { } static void set_flash_cr2_per(stlink_t *sl) { - const uint32_t n = 1 << FLASH_CR_PER; + const uint32_t n = (1 << FLASH_CR_PER); stlink_write_debug32(sl, FLASH_CR2, n); } @@ -728,12 +734,12 @@ static void set_flash_cr_mer(stlink_t *sl, bool v) { if (sl->flash_type == STLINK_FLASH_TYPE_F4) { cr_reg = FLASH_F4_CR; - cr_mer = 1 << FLASH_CR_MER; - cr_pg = 1 << FLASH_CR_PG; + cr_mer = (1 << FLASH_CR_MER); + cr_pg = (1 << FLASH_CR_PG); } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { cr_reg = STM32L4_FLASH_CR; cr_mer = (1 << STM32L4_FLASH_CR_MER1) | (1 << STM32L4_FLASH_CR_MER2); - cr_pg = 1 << STM32L4_FLASH_CR_PG; + cr_pg = (1 << STM32L4_FLASH_CR_PG); } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || sl->flash_type == STLINK_FLASH_TYPE_G4) { cr_reg = STM32Gx_FLASH_CR; @@ -748,8 +754,8 @@ static void set_flash_cr_mer(stlink_t *sl, bool v) { cr_pg = (1 << FLASH_CR_PG); } else { cr_reg = FLASH_CR; - cr_mer = 1 << FLASH_CR_MER; - cr_pg = 1 << FLASH_CR_PG; + cr_mer = (1 << FLASH_CR_MER); + cr_pg = (1 << FLASH_CR_PG); } stlink_read_debug32(sl, cr_reg, &val); @@ -767,8 +773,8 @@ static void set_flash_cr_mer(stlink_t *sl, bool v) { } static void set_flash_cr2_mer(stlink_t *sl, bool v) { - const uint32_t cr_pg = 1 << FLASH_CR_PER; - const uint32_t cr_mer = 1 << FLASH_CR_MER; + const uint32_t cr_pg = (1 << FLASH_CR_PER); + const uint32_t cr_mer = (1 << FLASH_CR_MER); uint32_t val; stlink_read_debug32(sl, FLASH_CR2, &val); @@ -785,13 +791,13 @@ static void __attribute__((unused)) clear_flash_cr_mer(stlink_t *sl) { if (sl->flash_type == STLINK_FLASH_TYPE_F4) { cr_reg = FLASH_F4_CR; - cr_mer = 1 << FLASH_CR_MER; + cr_mer = (1 << FLASH_CR_MER); } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { cr_reg = STM32L4_FLASH_CR; cr_mer = (1 << STM32L4_FLASH_CR_MER1) | (1 << STM32L4_FLASH_CR_MER2); } else { cr_reg = FLASH_CR; - cr_mer = 1 << FLASH_CR_MER; + cr_mer = (1 << FLASH_CR_MER); } stlink_read_debug32(sl, cr_reg, &val); @@ -804,20 +810,20 @@ static void set_flash_cr_strt(stlink_t *sl) { if (sl->flash_type == STLINK_FLASH_TYPE_F4) { cr_reg = FLASH_F4_CR; - cr_strt = 1 << FLASH_F4_CR_STRT; + cr_strt = (1 << FLASH_F4_CR_STRT); } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { cr_reg = STM32L4_FLASH_CR; - cr_strt = 1 << STM32L4_FLASH_CR_STRT; + cr_strt = (1 << STM32L4_FLASH_CR_STRT); } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || sl->flash_type == STLINK_FLASH_TYPE_G4) { cr_reg = STM32Gx_FLASH_CR; - cr_strt = 1 << STM32Gx_FLASH_CR_STRT; + cr_strt = (1 << STM32Gx_FLASH_CR_STRT); } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { cr_reg = STM32WB_FLASH_CR; - cr_strt = 1 << STM32WB_FLASH_CR_STRT; + cr_strt = (1 << STM32WB_FLASH_CR_STRT); } else { cr_reg = FLASH_CR; - cr_strt = 1 << FLASH_CR_STRT; + cr_strt = (1 << FLASH_CR_STRT); } stlink_read_debug32(sl, cr_reg, &val); @@ -2377,8 +2383,7 @@ int stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, } -int stm32l1_write_half_pages(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t len, uint32_t pagesize) -{ +int stm32l1_write_half_pages(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t len, uint32_t pagesize) { unsigned int count; unsigned int num_half_pages = len / pagesize; uint32_t val; @@ -2742,7 +2747,8 @@ int stlink_parse_ihex(const char* path, uint8_t erased_pattern, uint8_t * * mem, uint32_t end = 0; bool eof_found = false; - for (int scan = 0; (res == 0) && (scan < 2); ++scan) { // parse file two times - first to find memory range, second - to fill it + for (int scan = 0; (res == 0) && (scan < 2); ++scan) { + // parse file two times - first to find memory range, second - to fill it if (scan == 1) { if (!eof_found) { ELOG("No EoF recond\n"); @@ -3015,8 +3021,7 @@ static int stlink_write_option_bytes_gx(stlink_t *sl, uint8_t* base, stm32_addr_ * @param base option bytes to write * @return 0 on success, -ve on failure. */ -static int stlink_write_option_bytes_l0(stlink_t *sl, uint8_t* base, stm32_addr_t addr, uint32_t len) -{ +static int stlink_write_option_bytes_l0(stlink_t *sl, uint8_t* base, stm32_addr_t addr, uint32_t len) { uint32_t flash_base = get_stm32l0_flash_base(sl); uint32_t val; uint32_t data; @@ -3162,8 +3167,7 @@ int stlink_read_option_bytes_generic(stlink_t *sl, uint32_t* option_byte) { * @param option_byte option value * @return 0 on success, -ve on failure. */ -int stlink_read_option_bytes32(stlink_t *sl, uint32_t* option_byte) -{ +int stlink_read_option_bytes32(stlink_t *sl, uint32_t* option_byte) { if (sl->option_base == 0) { ELOG("Option bytes read is currently not supported for connected chip\n"); return -1; @@ -3190,8 +3194,7 @@ int stlink_read_option_bytes32(stlink_t *sl, uint32_t* option_byte) * @param option_byte value to write * @return 0 on success, -ve on failure. */ -int stlink_write_option_bytes32(stlink_t *sl, uint32_t option_byte) -{ +int stlink_write_option_bytes32(stlink_t *sl, uint32_t option_byte) { WLOG("About to write option byte %#10x to target.\n", option_byte); return stlink_write_option_bytes(sl, sl->option_base, (uint8_t *) &option_byte, 4); } @@ -3203,8 +3206,7 @@ int stlink_write_option_bytes32(stlink_t *sl, uint32_t option_byte) * @param base option bytes to write * @return 0 on success, -ve on failure. */ -int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t len) -{ +int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t len) { int ret = -1; if (sl->option_base == 0) { diff --git a/src/mmap/mmap.h b/src/mmap/mmap.h deleted file mode 100644 index ab94fb7d4..000000000 --- a/src/mmap/mmap.h +++ /dev/null @@ -1,31 +0,0 @@ -#ifndef STLINK_MMAP_H -#define STLINK_MMAP_H - -#ifdef STLINK_HAVE_SYS_MMAN_H -#include -#else - -#define PROT_READ (1<<0) -#define PROT_WRITE (1<<1) - -#define MAP_SHARED (1<<0) -#define MAP_PRIVATE (1<<1) - -#define MAP_ANONYMOUS (1<<5) - -#define MAP_FAILED ((void *)-1) - -#ifdef __cplusplus -extern "C" { -#endif - - void *mmap(void *addr, size_t len, int prot, int flags, int fd, long long offset); - int munmap(void *addr, size_t len); - -#ifdef __cplusplus -} -#endif - -#endif /* HAVE_SYS_MMAN_H */ - -#endif /* STLINK_MMAP_H */ diff --git a/src/st-util/gdb-remote.c b/src/st-util/gdb-remote.c index 24636e8c9..d5ea0b1c6 100644 --- a/src/st-util/gdb-remote.c +++ b/src/st-util/gdb-remote.c @@ -9,8 +9,8 @@ #include #include -#if defined(__MINGW32__) || defined(_MSC_VER) -#include +#if defined(_WIN32) +#include #else #include #include diff --git a/src/st-util/gdb-server.c b/src/st-util/gdb-server.c index a7107ff88..b851409e0 100644 --- a/src/st-util/gdb-server.c +++ b/src/st-util/gdb-server.c @@ -16,7 +16,7 @@ #endif #if defined(_WIN32) -#include +#include #else #include #include diff --git a/src/stlink-lib/usb.c b/src/stlink-lib/usb.c index b76639731..ec126cc7e 100644 --- a/src/stlink-lib/usb.c +++ b/src/stlink-lib/usb.c @@ -10,9 +10,10 @@ #include #include -#if defined(__MINGW32__) || defined(_MSC_VER) -#include +#if defined(_WIN32) +#include #endif + #include #include "usb.h" diff --git a/src/getopt/LICENSE.txt b/src/win32/getopt/LICENSE.txt similarity index 100% rename from src/getopt/LICENSE.txt rename to src/win32/getopt/LICENSE.txt diff --git a/src/getopt/README.md b/src/win32/getopt/README.md similarity index 100% rename from src/getopt/README.md rename to src/win32/getopt/README.md diff --git a/src/getopt/getopt.c b/src/win32/getopt/getopt.c similarity index 100% rename from src/getopt/getopt.c rename to src/win32/getopt/getopt.c diff --git a/src/getopt/getopt.h b/src/win32/getopt/getopt.h similarity index 100% rename from src/getopt/getopt.h rename to src/win32/getopt/getopt.h diff --git a/src/mmap/mmap.c b/src/win32/mmap.c similarity index 99% rename from src/mmap/mmap.c rename to src/win32/mmap.c index b76e4ad64..60bb440e9 100644 --- a/src/mmap/mmap.c +++ b/src/win32/mmap.c @@ -20,7 +20,6 @@ void *mmap (void *addr, size_t len, int prot, int flags, int fd, long long offs return MAP_FAILED; } - count = read(fd, buf, len); if (count != (ssize_t)len) { diff --git a/src/win32/mmap.h b/src/win32/mmap.h new file mode 100644 index 000000000..1f2e756cb --- /dev/null +++ b/src/win32/mmap.h @@ -0,0 +1,29 @@ +#ifndef STLINK_MMAP_H +#define STLINK_MMAP_H + +#ifdef STLINK_HAVE_SYS_MMAN_H +#include +#else + +#define PROT_READ (1 << 0) +#define PROT_WRITE (1 << 1) + +#define MAP_SHARED (1 << 0) +#define MAP_PRIVATE (1 << 1) +#define MAP_ANONYMOUS (1 << 5) +#define MAP_FAILED ((void *)-1) + +#ifdef __cplusplus +extern "C" { +#endif + +void *mmap(void *addr, size_t len, int prot, int flags, int fd, long long offset); +int munmap(void *addr, size_t len); + +#ifdef __cplusplus +} +#endif + +#endif /* HAVE_SYS_MMAN_H */ + +#endif /* STLINK_MMAP_H */ diff --git a/src/win32/unistd.h b/src/win32/unistd/unistd.h similarity index 100% rename from src/win32/unistd.h rename to src/win32/unistd/unistd.h diff --git a/src/mingw/mingw.c b/src/win32/win32_socket.c similarity index 59% rename from src/mingw/mingw.c rename to src/win32/win32_socket.c index 646fca238..3a3abae16 100644 --- a/src/mingw/mingw.c +++ b/src/win32/win32_socket.c @@ -1,6 +1,6 @@ -#if defined(__MINGW32__) || defined(_MSC_VER) +#if defined(_WIN32) -#include "mingw.h" +#include "win32_socket.h" #undef socket #undef connect @@ -11,23 +11,23 @@ #include #include -int win32_poll(struct pollfd *fds, unsigned int nfds, int timo) -{ +int win32_poll(struct pollfd *fds, unsigned int nfds, int timo) { struct timeval timeout, *toptr; fd_set ifds, ofds, efds, *ip, *op; unsigned int i; int rc; - /* Set up the file-descriptor sets in ifds, ofds and efds. */ #ifdef _MSC_VER #pragma warning(disable: 4548) #endif + + /* Set up the file-descriptor sets in ifds, ofds and efds. */ FD_ZERO(&ifds); FD_ZERO(&ofds); FD_ZERO(&efds); for (i = 0, op = ip = 0; i < nfds; ++i) { fds[i].revents = 0; - if (fds[i].events & (POLLIN|POLLPRI)) { + if (fds[i].events & (POLLIN | POLLPRI)) { ip = &ifds; FD_SET(fds[i].fd, ip); } @@ -36,7 +36,8 @@ int win32_poll(struct pollfd *fds, unsigned int nfds, int timo) FD_SET(fds[i].fd, op); } FD_SET(fds[i].fd, &efds); - } + } + #ifdef _MSC_VER #pragma warning(default: 4548) #endif @@ -54,13 +55,14 @@ int win32_poll(struct pollfd *fds, unsigned int nfds, int timo) printf("Entering select() sec=%ld usec=%ld ip=%lx op=%lx\n", (long)timeout.tv_sec, (long)timeout.tv_usec, (long)ip, (long)op); #endif + rc = select(0, ip, op, &efds, toptr); + #ifdef DEBUG_POLL printf("Exiting select rc=%d\n", rc); #endif - if (rc <= 0) - return rc; + if (rc <= 0) return rc; if (rc > 0) { for ( i = 0; i < nfds; ++i) { @@ -72,19 +74,20 @@ int win32_poll(struct pollfd *fds, unsigned int nfds, int timo) if (FD_ISSET(fd, &efds)) /* Some error was detected ... should be some way to know. */ fds[i].revents |= POLLHUP; + #ifdef DEBUG_POLL - printf("%d %d %d revent = %x\n", - FD_ISSET(fd, &ifds), FD_ISSET(fd, &ofds), FD_ISSET(fd, &efds), - fds[i].revents - ); + printf("%d %d %d revent = %x\n", + FD_ISSET(fd, &ifds), FD_ISSET(fd, &ofds), FD_ISSET(fd, &efds), + fds[i].revents + ); #endif + } } return rc; } -static void -set_connect_errno(int winsock_err) -{ + +static void set_connect_errno(int winsock_err) { switch(winsock_err) { case WSAEINVAL: case WSAEALREADY: @@ -97,9 +100,7 @@ set_connect_errno(int winsock_err) } } -static void -set_socket_errno(int winsock_err) -{ +static void set_socket_errno(int winsock_err) { switch(winsock_err) { case WSAEWOULDBLOCK: errno = EAGAIN; @@ -109,44 +110,36 @@ set_socket_errno(int winsock_err) break; } } + /* - * A wrapper around the socket() function. The purpose of this wrapper - * is to ensure that the global errno symbol is set if an error occurs, + * A wrapper around the socket() function. + * The purpose of this wrapper is to ensure that the global errno symbol is set if an error occurs, * even if we are using winsock. */ -SOCKET -win32_socket(int domain, int type, int protocol) -{ +SOCKET win32_socket(int domain, int type, int protocol) { SOCKET fd = socket(domain, type, protocol); - if (fd == INVALID_SOCKET) { - set_socket_errno(WSAGetLastError()); - } + if (fd == INVALID_SOCKET) set_socket_errno(WSAGetLastError()); return fd; } + /* - * A wrapper around the connect() function. The purpose of this wrapper - * is to ensure that the global errno symbol is set if an error occurs, + * A wrapper around the connect() function. + * The purpose of this wrapper is to ensure that the global errno symbol is set if an error occurs, * even if we are using winsock. */ -int -win32_connect(SOCKET fd, struct sockaddr *addr, socklen_t addr_len) -{ +int win32_connect(SOCKET fd, struct sockaddr *addr, socklen_t addr_len) { int rc = connect(fd, addr, addr_len); assert(rc == 0 || rc == SOCKET_ERROR); - if (rc == SOCKET_ERROR) { - set_connect_errno(WSAGetLastError()); - } + if (rc == SOCKET_ERROR) set_connect_errno(WSAGetLastError()); return rc; } /* - * A wrapper around the accept() function. The purpose of this wrapper - * is to ensure that the global errno symbol is set if an error occurs, + * A wrapper around the accept() function. + * The purpose of this wrapper is to ensure that the global errno symbol is set if an error occurs, * even if we are using winsock. */ -SOCKET -win32_accept(SOCKET fd, struct sockaddr *addr, socklen_t *addr_len) -{ +SOCKET win32_accept(SOCKET fd, struct sockaddr *addr, socklen_t *addr_len) { SOCKET newfd = accept(fd, addr, addr_len); if (newfd == INVALID_SOCKET) { set_socket_errno(WSAGetLastError()); @@ -156,62 +149,45 @@ win32_accept(SOCKET fd, struct sockaddr *addr, socklen_t *addr_len) } /* - * A wrapper around the shutdown() function. The purpose of this wrapper - * is to ensure that the global errno symbol is set if an error occurs, + * A wrapper around the shutdown() function. + * The purpose of this wrapper is to ensure that the global errno symbol is set if an error occurs, * even if we are using winsock. */ -int -win32_shutdown(SOCKET fd, int mode) -{ +int win32_shutdown(SOCKET fd, int mode) { int rc = shutdown(fd, mode); assert(rc == 0 || rc == SOCKET_ERROR); - if (rc == SOCKET_ERROR) { - set_socket_errno(WSAGetLastError()); - } + if (rc == SOCKET_ERROR) set_socket_errno(WSAGetLastError()); return rc; } -int win32_close_socket(SOCKET fd) -{ +int win32_close_socket(SOCKET fd) { int rc = closesocket(fd); - if (rc == SOCKET_ERROR) { - set_socket_errno(WSAGetLastError()); - } + if (rc == SOCKET_ERROR) set_socket_errno(WSAGetLastError()); return rc; } -ssize_t win32_write_socket(SOCKET fd, void *buf, int n) -{ +ssize_t win32_write_socket(SOCKET fd, void *buf, int n) { int rc = send(fd, buf, n, 0); - if (rc == SOCKET_ERROR) { - set_socket_errno(WSAGetLastError()); - } + if (rc == SOCKET_ERROR) set_socket_errno(WSAGetLastError()); return rc; } -ssize_t win32_read_socket(SOCKET fd, void *buf, int n) -{ +ssize_t win32_read_socket(SOCKET fd, void *buf, int n) { int rc = recv(fd, buf, n, 0); - if (rc == SOCKET_ERROR) { - set_socket_errno(WSAGetLastError()); - } + if (rc == SOCKET_ERROR) set_socket_errno(WSAGetLastError()); return rc; } -char * win32_strtok_r(char *s, const char *delim, char **lasts) -{ +char * win32_strtok_r(char *s, const char *delim, char **lasts) { register char *spanp; register int c, sc; char *tok; - if (s == NULL && (s = *lasts) == NULL) - return (NULL); + if (s == NULL && (s = *lasts) == NULL) return (NULL); - /* - * Skip (span) leading delimiters (s += strspn(s, delim), sort of). - */ + // Skip (span) leading delimiters (s += strspn(s, delim), sort of). cont: c = *s++; for (spanp = (char *)delim; (sc = *spanp++) != 0;) { @@ -219,7 +195,7 @@ char * win32_strtok_r(char *s, const char *delim, char **lasts) goto cont; } - if (c == 0) { /* no non-delimiter characters */ + if (c == 0) { // no non-delimiter characters *lasts = NULL; return (NULL); } @@ -234,10 +210,11 @@ char * win32_strtok_r(char *s, const char *delim, char **lasts) spanp = (char *)delim; do { if ((sc = *spanp++) == c) { - if (c == 0) + if (c == 0) { s = NULL; - else + } else { s[-1] = 0; + } *lasts = s; return (tok); } @@ -246,24 +223,23 @@ char * win32_strtok_r(char *s, const char *delim, char **lasts) /* NOTREACHED */ } -char *win32_strsep (char **stringp, const char *delim) -{ +char *win32_strsep (char **stringp, const char *delim) { register char *s; register const char *spanp; register int c, sc; char *tok; - if ((s = *stringp) == NULL) - return (NULL); + if ((s = *stringp) == NULL) return (NULL); for (tok = s;;) { c = *s++; spanp = delim; do { if ((sc = *spanp++) == c) { - if (c == 0) + if (c == 0) { s = NULL; - else + } else { s[-1] = 0; + } *stringp = s; return (tok); } @@ -273,24 +249,23 @@ char *win32_strsep (char **stringp, const char *delim) } #ifndef STLINK_HAVE_UNISTD_H -int usleep(unsigned int waitTime) -{ - if (waitTime >= 1000) - { - // Don't do long busy-waits. - // However much it seems like the QPC code would be more accurate, - // you can and probably will lose your time slice at any point during the wait, - // so we might as well voluntarily give up the CPU with a WaitForSingleObject. - HANDLE timer; - LARGE_INTEGER dueTime; - dueTime.QuadPart = -10 * (LONGLONG)waitTime; - - timer = CreateWaitableTimer(NULL, TRUE, NULL); - SetWaitableTimer(timer, &dueTime, 0, NULL, NULL, 0); - WaitForSingleObject(timer, INFINITE); - CloseHandle(timer); +int usleep(unsigned int waitTime) { + if (waitTime >= 1000) { + /* Don't do long busy-waits. + * However much it seems like the QPC code would be more accurate, + * you can and probably will lose your time slice at any point during the wait, + * so we might as well voluntarily give up the CPU with a WaitForSingleObject. + */ + HANDLE timer; + LARGE_INTEGER dueTime; + dueTime.QuadPart = -10 * (LONGLONG)waitTime; + timer = CreateWaitableTimer(NULL, TRUE, NULL); + SetWaitableTimer(timer, &dueTime, 0, NULL, NULL, 0); + WaitForSingleObject(timer, INFINITE); + CloseHandle(timer); + return 0; - } + } LARGE_INTEGER perf_cnt, start, now; QueryPerformanceFrequency(&perf_cnt); @@ -304,6 +279,4 @@ int usleep(unsigned int waitTime) } #endif -#endif - - +#endif // defined(_WIN32) diff --git a/src/mingw/mingw.h b/src/win32/win32_socket.h similarity index 81% rename from src/mingw/mingw.h rename to src/win32/win32_socket.h index 8f5b992fe..0d26a80e3 100644 --- a/src/mingw/mingw.h +++ b/src/win32/win32_socket.h @@ -9,19 +9,20 @@ #include #include + #if defined(_MSC_VER) #pragma comment(lib, "ws2_32.lib") #endif + #include #if defined(_MSC_VER) #pragma warning(pop) #endif -/* winsock doesn't feature poll(), so there is a version implemented - * in terms of select() in mingw.c. The following definitions - * are copied from linux man pages. A poll() macro is defined to - * call the version in mingw.c. +/* winsock doesn't feature poll(), so there is a version implemented in terms of select() in mingw.c. + * The following definitions are copied from linux man pages. + * A poll() macro is defined to call the version in mingw.c. */ #if !defined(_WIN32_WINNT) || (_WIN32_WINNT < 0x0600) @@ -39,11 +40,10 @@ struct pollfd { #endif #define poll(x, y, z) win32_poll(x, y, z) -/* These wrappers do nothing special except set the global errno variable if - * an error occurs (winsock doesn't do this by default). They set errno - * to unix-like values (i.e. WSAEWOULDBLOCK is mapped to EAGAIN), so code - * outside of this file "shouldn't" have to worry about winsock specific error - * handling. +/* These wrappers do nothing special except set the global errno variable if an error occurs + * (winsock doesn't do this by default). + * They set errno to unix-like values (i.e. WSAEWOULDBLOCK is mapped to EAGAIN), + * so code outside of this file "shouldn't" have to worry about winsock specific error handling. */ #define socket(x, y, z) win32_socket(x, y, z) #define connect(x, y, z) win32_connect(x, y, z) @@ -71,4 +71,4 @@ char *win32_strsep(char **stringp, const char *delim); ssize_t win32_read_socket(SOCKET fd, void *buf, int n); ssize_t win32_write_socket(SOCKET fd, void *buf, int n); -#endif //defined(__MINGW32__) || defined(_MSC_VER) +#endif // defined(__MINGW32__) || defined(_MSC_VER) From 97974649c38533a2a7a2e72bb356fe20e8b232ce Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sat, 6 Jun 2020 00:13:15 +0200 Subject: [PATCH 027/503] Whitespace & code style cleanup --- CMakeLists.txt | 7 +- src/st-util/gdb-remote.c | 35 +-- src/st-util/gdb-server.c | 518 +++++++++++++++----------------------- src/stlink-lib/usb.c | 2 + src/win32/unistd/unistd.h | 12 +- src/win32/win32_socket.c | 4 +- src/win32/win32_socket.h | 4 +- 7 files changed, 227 insertions(+), 355 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index c1ced137d..8428e7565 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -9,6 +9,7 @@ set(CMAKE_ARCHIVE_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}/lib) set(CMAKE_LIBRARY_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}/lib) set(CMAKE_RUNTIME_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}/bin) + ### # General project settings ### @@ -93,11 +94,6 @@ include_directories(src) include_directories(src/st-flash) include_directories(src/stlink-lib) -if (MSVC) - include_directories(src/win32) - include_directories(src/win32/unistd) -endif () - set(STLINK_HEADERS inc/stlink.h src/backend.h @@ -127,6 +123,7 @@ if (WIN32) set(STLINK_HEADERS "${STLINK_HEADERS};src/win32/win32_socket.h") if (MSVC) + # Add drop-in replacement for unistd.h to sources include_directories(src/win32/unistd) set(STLINK_HEADERS "${STLINK_HEADERS};src/win32/unistd/unistd.h") endif () diff --git a/src/st-util/gdb-remote.c b/src/st-util/gdb-remote.c index d5ea0b1c6..04729cc75 100644 --- a/src/st-util/gdb-remote.c +++ b/src/st-util/gdb-remote.c @@ -1,7 +1,6 @@ /* * Copyright (C) 2011 Peter Zotov - * Use of this source code is governed by a BSD-style - * license that can be found in the LICENSE file. + * Use of this source code is governed by a BSD-style license that can be found in the LICENSE file. */ #include @@ -23,7 +22,7 @@ static const char hex[] = "0123456789abcdef"; int gdb_send_packet(int fd, char* data) { unsigned int data_length = (unsigned int) strlen(data); int length = data_length + 4; - char* packet = malloc(length); /* '$' data (hex) '#' cksum (hex) */ + char* packet = malloc(length); // '$' data (hex) '#' cksum (hex) memset(packet, 0, length); @@ -67,8 +66,7 @@ int gdb_recv_packet(int fd, char** buffer) { char* packet_buffer = malloc(packet_size); unsigned state; - if (packet_buffer == NULL) - return -2; + if (packet_buffer == NULL) return -2; start: state = 0; @@ -90,11 +88,7 @@ int gdb_recv_packet(int fd, char** buffer) { switch(state) { case 0: - if (c != '$') { - // ignore - } else { - state = 1; - } + if (c != '$') { /* ignore */ } else { state = 1; } break; case 1: @@ -107,9 +101,9 @@ int gdb_recv_packet(int fd, char** buffer) { if (packet_idx == packet_size) { packet_size += ALLOC_STEP; void* p = realloc(packet_buffer, packet_size); - if (p != NULL) + if (p != NULL) { packet_buffer = p; - else { + } else { free(packet_buffer); return -2; } @@ -136,7 +130,6 @@ int gdb_recv_packet(int fd, char** buffer) { free(packet_buffer); return -2; } - goto start; } else { char ack = '+'; @@ -152,9 +145,11 @@ int gdb_recv_packet(int fd, char** buffer) { return packet_idx; } -// Here we skip any characters which are not \x03, GDB interrupt. -// As we use the mode with ACK, in a (very unlikely) situation of a packet -// lost because of this skipping, it will be resent anyway. +/* + * Here we skip any characters which are not \x03, GDB interrupt. + * As we use the mode with ACK, in a (very unlikely) situation of a packet lost + * because of this skipping, it will be resent anyway. + */ int gdb_check_for_interrupt(int fd) { struct pollfd pfd; pfd.fd = fd; @@ -162,12 +157,8 @@ int gdb_check_for_interrupt(int fd) { if (poll(&pfd, 1, 0) != 0) { char c; - - if (read(fd, &c, 1) != 1) - return -2; - - if (c == '\x03') // ^C - return 1; + if (read(fd, &c, 1) != 1) return -2; + if (c == '\x03') return 1; // ^C } return 0; diff --git a/src/st-util/gdb-server.c b/src/st-util/gdb-server.c index b851409e0..119d0ff9a 100644 --- a/src/st-util/gdb-server.c +++ b/src/st-util/gdb-server.c @@ -1,8 +1,8 @@ /* * Copyright (C) 2011 Peter Zotov - * Use of this source code is governed by a BSD-style - * license that can be found in the LICENSE file. + * Use of this source code is governed by a BSD-style license that can be found in the LICENSE file. */ + #include #include #include @@ -10,6 +10,7 @@ #include #include #include + #if defined(_MSC_VER) #include #define __attribute__(x) @@ -32,11 +33,11 @@ #define FLASH_BASE 0x08000000 -/* Semihosting doesn't have a short option, we define a value to identify it */ +// Semihosting doesn't have a short option, we define a value to identify it #define SEMIHOSTING_OPTION 128 #define SERIAL_OPTION 127 -//Allways update the FLASH_PAGE before each use, by calling stlink_calculate_pagesize +// always update the FLASH_PAGE before each use, by calling stlink_calculate_pagesize #define FLASH_PAGE (sl->flash_pgsz) static stlink_t *connected_stlink = NULL; @@ -71,7 +72,7 @@ char* make_memory_map(stlink_t *sl); static void init_cache (stlink_t *sl); static void cleanup(int signum) { - (void)signum; + (void)signum; if (connected_stlink) { /* Switch back to mass storage mode before closing. */ @@ -86,10 +87,10 @@ static void cleanup(int signum) { static stlink_t* do_connect(st_state_t *st) { stlink_t *sl = NULL; - if (serial_specified) { - sl = stlink_open_usb(st->logging_level, st->reset, serialnumber, 0); - } else { - sl = stlink_open_usb(st->logging_level, st->reset, NULL, 0); + if (serial_specified) { + sl = stlink_open_usb(st->logging_level, st->reset, serialnumber, 0); + } else { + sl = stlink_open_usb(st->logging_level, st->reset, NULL, 0); } return sl; } @@ -201,18 +202,16 @@ int main(int argc, char** argv) { st_state_t state; memset(&state, 0, sizeof(state)); - // set defaults... + // set defaults ... state.logging_level = DEFAULT_LOGGING_LEVEL; state.listen_port = DEFAULT_GDB_LISTEN_PORT; - state.reset = 1; /* By default, reset board */ + state.reset = 1; // by default, reset board parse_options(argc, argv, &state); printf("st-util\n"); sl = do_connect(&state); - if (sl == NULL) { - return 1; - } + if (sl == NULL) return 1; if (sl->chip_id == STLINK_CHIPID_UNKNOWN) { ELOG("Unsupported Target (Chip ID is %#010x, Core ID is %#010x).\n", sl->chip_id, sl->core_id); @@ -224,42 +223,32 @@ int main(int argc, char** argv) { signal(SIGTERM, &cleanup); signal(SIGSEGV, &cleanup); - if (state.reset) { - stlink_reset(sl); - } + if (state.reset) stlink_reset(sl); DLOG("Chip ID is %#010x, Core ID is %#08x.\n", sl->chip_id, sl->core_id); sl->verbose=0; current_memory_map = make_memory_map(sl); -#if defined(__MINGW32__) || defined(_MSC_VER) - WSADATA wsadata; - if (WSAStartup(MAKEWORD(2,2),&wsadata) !=0){ - goto winsock_error; - } +#if defined(_WIN32) + WSADATA wsadata; + if (WSAStartup(MAKEWORD(2,2),&wsadata) !=0) goto winsock_error; #endif init_cache(sl); do { - if (serve(sl, &state)) { - usleep (1 * 1000); // don't go bezurk if serve returns with error - } - - /* in case serve() changed the connection */ - sl = connected_stlink; - - /* Continue */ - stlink_run(sl); + if (serve(sl, &state)) { usleep (1 * 1000); } // don't go beserk if serve returns with error + sl = connected_stlink; // in case serve() changed the connection + stlink_run(sl); // continue } while (state.persistent); -#if defined(__MINGW32__) || defined(_MSC_VER) +#if defined(_WIN32) winsock_error: WSACleanup(); #endif - /* Switch back to mass storage mode before closing. */ + // switch back to mass storage mode before closing stlink_exit_debug_mode(sl); stlink_close(sl); @@ -507,7 +496,7 @@ static const char* const memory_map_template_F4_DE = ""; char* make_memory_map(stlink_t *sl) { - /* This will be freed in serve() */ + // this will be freed in serve() const size_t sz = 4096; char* map = malloc(sz); map[0] = '\0'; @@ -545,7 +534,6 @@ char* make_memory_map(stlink_t *sl) { return map; } - /* * DWT_COMP0 0xE0001020 * DWT_MASK0 0xE0001024 @@ -589,8 +577,8 @@ static void init_data_watchpoints(stlink_t *sl) { } } -static int add_data_watchpoint(stlink_t *sl, enum watchfun wf, - stm32_addr_t addr, unsigned int len) { +static int add_data_watchpoint( + stlink_t *sl, enum watchfun wf, stm32_addr_t addr, unsigned int len) { int i = 0; uint32_t mask, dummy; @@ -635,8 +623,7 @@ static int add_data_watchpoint(stlink_t *sl, enum watchfun wf, return -1; } -static int delete_data_watchpoint(stlink_t *sl, stm32_addr_t addr) -{ +static int delete_data_watchpoint(stlink_t *sl, stm32_addr_t addr) { int i; for (i = 0 ; i < DATA_WATCH_NUM; i++) { @@ -657,9 +644,9 @@ static int delete_data_watchpoint(stlink_t *sl, stm32_addr_t addr) static int code_break_num; static int code_lit_num; -#define CODE_BREAK_NUM_MAX 15 -#define CODE_BREAK_LOW 0x01 -#define CODE_BREAK_HIGH 0x02 +#define CODE_BREAK_NUM_MAX 15 +#define CODE_BREAK_LOW 0x01 +#define CODE_BREAK_HIGH 0x02 struct code_hw_breakpoint { stm32_addr_t addr; @@ -687,9 +674,7 @@ static void init_code_breakpoints(stlink_t *sl) { static int has_breakpoint(stm32_addr_t addr) { for (int i = 0; i < code_break_num; i++) { - if (code_breaks[i].addr == addr) { - return 1; - } + if (code_breaks[i].addr == addr) return 1; } return 0; } @@ -704,52 +689,43 @@ static int update_code_breakpoint(stlink_t *sl, stm32_addr_t addr, int set) { return -1; } - if (sl->core_id==STM32F7_CORE_ID) { - fpb_addr = addr; - } else { - fpb_addr = addr & ~0x3; - } + if (sl->core_id==STM32F7_CORE_ID) { + fpb_addr = addr; + } else { + fpb_addr = addr & ~0x3; + } int id = -1; for (int i = 0; i < code_break_num; i++) { - if (fpb_addr == code_breaks[i].addr || - (set && code_breaks[i].type == 0)) { + if (fpb_addr == code_breaks[i].addr || (set && code_breaks[i].type == 0)) { id = i; break; } } if (id == -1) { - if (set) return -1; // Free slot not found - else return 0; // Breakpoint is already removed + if (set) { return -1; } // free slot not found + else { return 0; } // breakpoint is already removed } struct code_hw_breakpoint* bp = &code_breaks[id]; bp->addr = fpb_addr; - if (sl->core_id==STM32F7_CORE_ID) { - if (set) bp->type = type; - else bp->type = 0; - - mask = (bp->addr) | 1; - } else { - if (set) bp->type |= type; - else bp->type &= ~type; - - mask = (bp->addr) | 1 | (bp->type << 30); - } + if (sl->core_id==STM32F7_CORE_ID) { + if (set) { bp->type = type; } else { bp->type = 0; } + mask = (bp->addr) | 1; + } else { + if (set) { bp->type |= type; } else { bp->type &= ~type; } + mask = (bp->addr) | 1 | (bp->type << 30); + } if (bp->type == 0) { DLOG("clearing hw break %d\n", id); - stlink_write_debug32(sl, 0xe0002008 + id * 4, 0); } else { - DLOG("setting hw break %d at %08x (%d)\n", - id, bp->addr, bp->type); - DLOG("reg %08x \n", - mask); - + DLOG("setting hw break %d at %08x (%d)\n", id, bp->addr, bp->type); + DLOG("reg %08x \n", mask); stlink_write_debug32(sl, 0xe0002008 + id * 4, mask); } @@ -782,7 +758,6 @@ static int flash_add_block(stm32_addr_t addr, unsigned length, stlink_t *sl) { struct flash_block* new = malloc(sizeof(struct flash_block)); new->next = flash_root; - new->addr = addr; new->length = length; new->data = calloc(length, 1); @@ -824,8 +799,7 @@ static int flash_populate(stm32_addr_t addr, uint8_t* data, unsigned length) { } if (fit_length != length) { - WLOG("data block %08x -> %04x truncated to %04x\n", - addr, length, fit_length); + WLOG("data block %08x -> %04x truncated to %04x\n", addr, length, fit_length); WLOG("(this is not an error, just a GDB glitch)\n"); } @@ -835,7 +809,7 @@ static int flash_populate(stm32_addr_t addr, uint8_t* data, unsigned length) { static int flash_go(stlink_t *sl) { int error = -1; - // Some kinds of clock settings do not allow writing to flash. + // some kinds of clock settings do not allow writing to flash. stlink_reset(sl); stlink_force_debug(sl); @@ -845,14 +819,13 @@ static int flash_go(stlink_t *sl) { for (stm32_addr_t page = fb->addr; page < fb->addr + fb->length; page += (uint32_t)FLASH_PAGE) { unsigned length = fb->length - (page - fb->addr); - //Update FLASH_PAGE + // update FLASH_PAGE stlink_calculate_pagesize(sl, page); DLOG("flash_do: page %08x\n", page); unsigned len = (length > FLASH_PAGE) ? (unsigned int) FLASH_PAGE : length; int ret = stlink_write_flash(sl, page, fb->data + (page - fb->addr), len, 0); - if (ret < 0) - goto error; + if (ret < 0) goto error; } } @@ -882,98 +855,86 @@ static int flash_go(stlink_t *sl) { #define DCCSW 0xE000EF6C #define ICIALLU 0xE000EF50 -struct cache_level_desc -{ - unsigned int nsets; - unsigned int nways; - unsigned int log2_nways; - unsigned int width; +struct cache_level_desc { + unsigned int nsets; + unsigned int nways; + unsigned int log2_nways; + unsigned int width; }; -struct cache_desc_t -{ - /* Minimal line size in bytes. */ - unsigned int dminline; - unsigned int iminline; +struct cache_desc_t { + // Minimal line size in bytes + unsigned int dminline; + unsigned int iminline; - /* Last level of unification (uniprocessor). */ - unsigned int louu; + // Last level of unification (uniprocessor) + unsigned int louu; - struct cache_level_desc icache[7]; - struct cache_level_desc dcache[7]; + struct cache_level_desc icache[7]; + struct cache_level_desc dcache[7]; }; static struct cache_desc_t cache_desc; -/* Return the smallest R so that V <= (1 << R). Not performance critical. */ -static unsigned ceil_log2(unsigned v) -{ - unsigned res; - for (res = 0; (1U << res) < v; res++) - ; - return res; +// return the smallest R so that V <= (1 << R); not performance critical +static unsigned ceil_log2(unsigned v) { + unsigned res; + for (res = 0; (1U << res) < v; res++) ; + return res; } -static void read_cache_level_desc(stlink_t *sl, struct cache_level_desc *desc) -{ - unsigned int ccsidr; - unsigned int log2_nsets; - - stlink_read_debug32(sl, CCSIDR, &ccsidr); - desc->nsets = ((ccsidr >> 13) & 0x3fff) + 1; - desc->nways = ((ccsidr >> 3) & 0x1ff) + 1; - desc->log2_nways = ceil_log2 (desc->nways); - log2_nsets = ceil_log2 (desc->nsets); - desc->width = 4 + (ccsidr & 7) + log2_nsets; - ILOG("%08x LineSize: %u, ways: %u, sets: %u (width: %u)\n", - ccsidr, 4 << (ccsidr & 7), desc->nways, desc->nsets, desc->width); +static void read_cache_level_desc(stlink_t *sl, struct cache_level_desc *desc) { + unsigned int ccsidr; + unsigned int log2_nsets; + + stlink_read_debug32(sl, CCSIDR, &ccsidr); + desc->nsets = ((ccsidr >> 13) & 0x3fff) + 1; + desc->nways = ((ccsidr >> 3) & 0x1ff) + 1; + desc->log2_nways = ceil_log2 (desc->nways); + log2_nsets = ceil_log2 (desc->nsets); + desc->width = 4 + (ccsidr & 7) + log2_nsets; + ILOG("%08x LineSize: %u, ways: %u, sets: %u (width: %u)\n", + ccsidr, 4 << (ccsidr & 7), desc->nways, desc->nsets, desc->width); } static void init_cache (stlink_t *sl) { - unsigned int clidr; - unsigned int ccr; - unsigned int ctr; - int i; - - /* Assume only F7 has a cache. */ - if (sl->core_id!=STM32F7_CORE_ID) - return; - - stlink_read_debug32(sl, CLIDR, &clidr); - stlink_read_debug32(sl, CCR, &ccr); - stlink_read_debug32(sl, CTR, &ctr); - cache_desc.dminline = 4 << ((ctr >> 16) & 0x0f); - cache_desc.iminline = 4 << (ctr & 0x0f); - cache_desc.louu = (clidr >> 27) & 7; - - ILOG("Chip clidr: %08x, I-Cache: %s, D-Cache: %s\n", - clidr, ccr & CCR_IC ? "on" : "off", ccr & CCR_DC ? "on" : "off"); - ILOG(" cache: LoUU: %u, LoC: %u, LoUIS: %u\n", - (clidr >> 27) & 7, (clidr >> 24) & 7, (clidr >> 21) & 7); - ILOG(" cache: ctr: %08x, DminLine: %u bytes, IminLine: %u bytes\n", ctr, - cache_desc.dminline, cache_desc.iminline); - for (i = 0; i < 7; i++) - { - unsigned int ct = (clidr >> (3 * i)) & 0x07; - - cache_desc.dcache[i].width = 0; - cache_desc.icache[i].width = 0; - - if (ct == 2 || ct == 3 || ct == 4) - { - /* Data. */ - stlink_write_debug32(sl, CSSELR, i << 1); - ILOG("D-Cache L%d: ", i); - read_cache_level_desc(sl, &cache_desc.dcache[i]); - } - - if (ct == 1 || ct == 3) - { - /* Instruction. */ - stlink_write_debug32(sl, CSSELR, (i << 1) | 1); - ILOG("I-Cache L%d: ", i); - read_cache_level_desc(sl, &cache_desc.icache[i]); - } + unsigned int clidr; + unsigned int ccr; + unsigned int ctr; + int i; + + // Assume only F7 has a cache + if (sl->core_id!=STM32F7_CORE_ID) return; + + stlink_read_debug32(sl, CLIDR, &clidr); + stlink_read_debug32(sl, CCR, &ccr); + stlink_read_debug32(sl, CTR, &ctr); + cache_desc.dminline = 4 << ((ctr >> 16) & 0x0f); + cache_desc.iminline = 4 << (ctr & 0x0f); + cache_desc.louu = (clidr >> 27) & 7; + + ILOG("Chip clidr: %08x, I-Cache: %s, D-Cache: %s\n", + clidr, ccr & CCR_IC ? "on" : "off", ccr & CCR_DC ? "on" : "off"); + ILOG(" cache: LoUU: %u, LoC: %u, LoUIS: %u\n", + (clidr >> 27) & 7, (clidr >> 24) & 7, (clidr >> 21) & 7); + ILOG(" cache: ctr: %08x, DminLine: %u bytes, IminLine: %u bytes\n", ctr, + cache_desc.dminline, cache_desc.iminline); + for (i = 0; i < 7; i++) { + unsigned int ct = (clidr >> (3 * i)) & 0x07; + cache_desc.dcache[i].width = 0; + cache_desc.icache[i].width = 0; + + if (ct == 2 || ct == 3 || ct == 4) { // Data + stlink_write_debug32(sl, CSSELR, i << 1); + ILOG("D-Cache L%d: ", i); + read_cache_level_desc(sl, &cache_desc.dcache[i]); + } + + if (ct == 1 || ct == 3) { // Instruction + stlink_write_debug32(sl, CSSELR, (i << 1) | 1); + ILOG("I-Cache L%d: ", i); + read_cache_level_desc(sl, &cache_desc.icache[i]); + } } } @@ -987,54 +948,43 @@ static void cache_flush(stlink_t *sl, unsigned ccr) { unsigned max_addr = 1 << desc->width; unsigned way_sh = 32 - desc->log2_nways; - /* D-cache clean by set-ways. */ + // D-cache clean by set-ways. for (addr = (level << 1); addr < max_addr; addr += cache_desc.dminline) { unsigned int way; - for (way = 0; way < desc->nways; way++) - stlink_write_debug32(sl, DCCSW, addr | (way << way_sh)); - } + stlink_write_debug32(sl, DCCSW, addr | (way << way_sh)); + } } - /* Invalidate all I-cache to oPU. */ - if (ccr & CCR_IC) - stlink_write_debug32(sl, ICIALLU, 0); + // invalidate all I-cache to oPU + if (ccr & CCR_IC) stlink_write_debug32(sl, ICIALLU, 0); } static int cache_modified; -static void cache_change(stm32_addr_t start, unsigned count) -{ - if (count == 0) - return; - (void)start; - cache_modified = 1; +static void cache_change(stm32_addr_t start, unsigned count) { + if (count == 0) return; + (void)start; + cache_modified = 1; } -static void cache_sync(stlink_t *sl) -{ - unsigned ccr; +static void cache_sync(stlink_t *sl) { + unsigned ccr; - if (sl->core_id!=STM32F7_CORE_ID) - return; - if (!cache_modified) - return; - cache_modified = 0; + if (sl->core_id!=STM32F7_CORE_ID) return; + if (!cache_modified) return; + cache_modified = 0; - stlink_read_debug32(sl, CCR, &ccr); - if (ccr & (CCR_IC | CCR_DC)) - cache_flush(sl, ccr); + stlink_read_debug32(sl, CCR, &ccr); + if (ccr & (CCR_IC | CCR_DC)) cache_flush(sl, ccr); } -static size_t unhexify(const char *in, char *out, size_t out_count) -{ +static size_t unhexify(const char *in, char *out, size_t out_count) { size_t i; unsigned int c; for (i = 0; i < out_count; i++) { - if (sscanf(in + (2 * i), "%02x", &c) != 1) { - return i; - } + if (sscanf(in + (2 * i), "%02x", &c) != 1) return i; out[i] = (char)c; } @@ -1082,24 +1032,21 @@ int serve(stlink_t *sl, st_state_t *st) { close_socket(sock); stlink_force_debug(sl); - if (st->reset) { - stlink_reset(sl); - } + if (st->reset) stlink_reset(sl); init_code_breakpoints(sl); init_data_watchpoints(sl); ILOG("GDB connected.\n"); /* - * To allow resetting the chip from GDB it is required to - * emulate attaching and detaching to target. + * To allow resetting the chip from GDB it is required to emulate attaching + * and detaching to target. */ unsigned int attached = 1; - /* - * If a critical error is detected, break from the loop - */ + // if a critical error is detected, break from the loop int critical_error = 0; int ret; + while (1) { ret = 0; char* packet; @@ -1137,12 +1084,11 @@ int serve(stlink_t *sl, st_state_t *st) { DLOG("query: %s;%s\n", queryName, params); if (!strcmp(queryName, "Supported")) { - if (sl->chip_id==STLINK_CHIPID_STM32_F4 - || sl->chip_id==STLINK_CHIPID_STM32_F4_HD - || sl->core_id==STM32F7_CORE_ID) { - reply = strdup("PacketSize=3fff;qXfer:memory-map:read+;qXfer:features:read+"); - } - else { + if (sl->chip_id==STLINK_CHIPID_STM32_F4 || + sl->chip_id==STLINK_CHIPID_STM32_F4_HD || + sl->core_id==STM32F7_CORE_ID) { + reply = strdup("PacketSize=3fff;qXfer:memory-map:read+;qXfer:features:read+"); + } else { reply = strdup("PacketSize=3fff;qXfer:memory-map:read+"); } } else if (!strcmp(queryName, "Xfer")) { @@ -1174,7 +1120,6 @@ int serve(stlink_t *sl, st_state_t *st) { unsigned data_length = (unsigned int) strlen(data); if (addr + length > data_length) length = data_length - addr; - if (length == 0) { reply = strdup("l"); } else { @@ -1208,52 +1153,48 @@ int serve(stlink_t *sl, st_state_t *st) { DLOG("unhexified Rcmd: '%s'\n", cmd); - if (!strncmp(cmd, "resume", 6)) {// resume + if (!strncmp(cmd, "resume", 6)) { // resume DLOG("Rcmd: resume\n"); cache_sync(sl); ret = stlink_run(sl); if (ret) { DLOG("Rcmd: resume failed\n"); reply = strdup("E00"); - } else { reply = strdup("OK"); } - } else if (!strncmp(cmd, "halt", 4)) { //halt + } else if (!strncmp(cmd, "halt", 4)) { // halt ret = stlink_force_debug(sl); if (ret) { DLOG("Rcmd: halt failed\n"); reply = strdup("E00"); - } else { reply = strdup("OK"); DLOG("Rcmd: halt\n"); } - } else if (!strncmp(cmd, "jtag_reset", 10)) { //jtag_reset + } else if (!strncmp(cmd, "jtag_reset", 10)) { // jtag_reset reply = strdup("OK"); ret = stlink_jtag_reset(sl, 0); if (ret) { DLOG("Rcmd: jtag_reset failed with jtag_reset\n"); reply = strdup("E00"); - } ret = stlink_jtag_reset(sl, 1); if (ret) { DLOG("Rcmd: jtag_reset failed with jtag_reset\n"); reply = strdup("E00"); - } ret = stlink_force_debug(sl); if (ret) { DLOG("Rcmd: jtag_reset failed with force_debug\n"); reply = strdup("E00"); - } + if (strcmp(reply, "E00")) { // no errors have been found DLOG("Rcmd: jtag_reset\n"); @@ -1284,19 +1225,13 @@ int serve(stlink_t *sl, st_state_t *st) { DLOG("Rcmd: got semihosting cmd '%s'", cmd); char *arg = cmd + 12; - /* Skip whitespaces */ - while (isspace(*arg)) { - arg++; - } + // Skip whitespaces + while (isspace(*arg)) { arg++; } - if (!strncmp(arg, "enable", 6) - || !strncmp(arg, "1", 1)) - { + if (!strncmp(arg, "enable", 6) || !strncmp(arg, "1", 1)) { semihosting = true; reply = strdup("OK"); - } else if (!strncmp(arg, "disable", 7) - || !strncmp(arg, "0", 1)) - { + } else if (!strncmp(arg, "disable", 7) || !strncmp(arg, "0", 1)) { semihosting = false; reply = strdup("OK"); } else { @@ -1350,8 +1285,7 @@ int serve(stlink_t *sl, st_state_t *st) { unsigned addr = (unsigned int) strtoul(__s_addr, NULL, 16); unsigned data_length = status - (unsigned int) (data - packet); - // Length of decoded data cannot be more than - // encoded, as escapes are removed. + // Length of decoded data cannot be more than encoded, as escapes are removed. // Additional byte is reserved for alignment fix. uint8_t *decoded = calloc(data_length + 1, 1); unsigned dec_index = 0; @@ -1364,9 +1298,8 @@ int serve(stlink_t *sl, st_state_t *st) { } } - // Fix alignment - if (dec_index % 2 != 0) - dec_index++; + // fix alignment + if (dec_index % 2 != 0) dec_index++; DLOG("binary packet %d -> %d\n", data_length, dec_index); @@ -1385,7 +1318,6 @@ int serve(stlink_t *sl, st_state_t *st) { } } else if (!strcmp(cmdName, "Kill")) { attached = 0; - reply = strdup("OK"); } @@ -1398,9 +1330,7 @@ int serve(stlink_t *sl, st_state_t *st) { case 'c': cache_sync(sl); ret = stlink_run(sl); - if (ret) { - DLOG("Semihost: run failed\n"); - } + if (ret) DLOG("Semihost: run failed\n"); while (1) { status = gdb_check_for_interrupt(client); @@ -1416,9 +1346,7 @@ int serve(stlink_t *sl, st_state_t *st) { } ret = stlink_status(sl); - if (ret) { - DLOG("Semihost: status failed\n"); - } + if (ret) DLOG("Semihost: status failed\n"); if(sl->core_stat == TARGET_HALTED) { struct stlink_reg reg; stm32_addr_t pc; @@ -1426,30 +1354,23 @@ int serve(stlink_t *sl, st_state_t *st) { int offset = 0; uint16_t insn; - if (!semihosting) { - break; - } + if (!semihosting) break; ret = stlink_read_all_regs (sl, ®); - if (ret) { - DLOG("Semihost: read_all_regs failed\n"); - } + if (ret) DLOG("Semihost: read_all_regs failed\n"); - /* Read PC */ + // Read PC pc = reg.r[15]; - /* Compute aligned value */ + // Compute aligned value offset = pc % 4; addr = pc - offset; - /* Read instructions (address and length must be - * aligned). - */ + // Read instructions (address and length must be aligned). ret = stlink_read_mem32(sl, addr, (offset > 2 ? 8 : 4)); if (ret != 0) { - DLOG("Semihost: cannot read instructions at: " - "0x%08x\n", addr); + DLOG("Semihost: cannot read instructions at: 0x%08x\n", addr); break; } @@ -1458,28 +1379,20 @@ int serve(stlink_t *sl, st_state_t *st) { if (insn == 0xBEAB && !has_breakpoint(addr)) { ret = do_semihosting (sl, reg.r[0], reg.r[1], ®.r[0]); - if (ret) { - DLOG("Semihost: do_semihosting failed\n"); - } + if (ret) DLOG("Semihost: do_semihosting failed\n"); - /* Write return value */ + // Write return value ret = stlink_write_reg(sl, reg.r[0], 0); - if (ret) { - DLOG("Semihost: write_reg failed for return value\n"); - } + if (ret) DLOG("Semihost: write_reg failed for return value\n"); - /* Jump over the break instruction */ + // Jump over the break instruction ret = stlink_write_reg(sl, reg.r[15] + 2, 15); - if (ret) { - DLOG("Semihost: write_reg failed for jumping over break\n"); - } + if (ret) DLOG("Semihost: write_reg failed for jumping over break\n"); - /* continue execution */ + // Continue execution cache_sync(sl); ret = stlink_run(sl); - if (ret) { - DLOG("Semihost: continue execution failed with stlink_run\n"); - } + if (ret) DLOG("Semihost: continue execution failed with stlink_run\n"); } else { break; } @@ -1492,10 +1405,10 @@ int serve(stlink_t *sl, st_state_t *st) { break; case 's': - cache_sync(sl); + cache_sync(sl); ret = stlink_step(sl); if (ret) { - // have problem sending step packet + // ... having a problem sending step packet ELOG("Step: cannot send step request\n"); reply = strdup("E00"); critical_error = 1; // absolutely critical @@ -1509,21 +1422,18 @@ int serve(stlink_t *sl, st_state_t *st) { if (attached) { reply = strdup("S05"); // TRAP } else { - /* Stub shall reply OK if not attached. */ + // Stub shall reply OK if not attached. reply = strdup("OK"); } break; case 'g': ret = stlink_read_all_regs(sl, ®p); - if (ret) { - DLOG("g packet: read_all_regs failed\n"); - } + if (ret) DLOG("g packet: read_all_regs failed\n"); reply = calloc(8 * 16 + 1, 1); for (int i = 0; i < 16; i++) sprintf(&reply[i * 8], "%08x", (uint32_t)htonl(regp.r[i])); - break; case 'p': { @@ -1564,12 +1474,10 @@ int serve(stlink_t *sl, st_state_t *st) { ret = 1; reply = strdup("E00"); } - if (ret) { - DLOG("p packet: stlink_read_unsupported_reg failed with id %u\n", id); - } + if (ret) DLOG("p packet: stlink_read_unsupported_reg failed with id %u\n", id); if (reply == NULL) { - // if reply is set to "E00", skip + // If reply is set to "E00", skip reply = calloc(8 + 1, 1); sprintf(reply, "%08x", myreg); } @@ -1609,13 +1517,8 @@ int serve(stlink_t *sl, st_state_t *st) { ret = 1; reply = strdup("E00"); } - if (ret) { - DLOG("P packet: stlink_write_unsupported_reg failed with reg %u\n", reg); - } - if (reply == NULL) { - // note that NULL may not be zero - reply = strdup("OK"); - } + if (ret) DLOG("P packet: stlink_write_unsupported_reg failed with reg %u\n", reg); + if (reply == NULL) reply = strdup("OK"); // note that NULL may not be zero break; } @@ -1626,9 +1529,7 @@ int serve(stlink_t *sl, st_state_t *st) { strncpy(str, &packet[1 + i * 8], 8); uint32_t reg = (uint32_t) strtoul(str, NULL, 16); ret = stlink_write_reg(sl, ntohl(reg), i); - if (ret) { - DLOG("G packet: stlink_write_reg failed"); - } + if (ret) DLOG("G packet: stlink_write_reg failed"); } reply = strdup("OK"); @@ -1643,17 +1544,12 @@ int serve(stlink_t *sl, st_state_t *st) { unsigned adj_start = start % 4; unsigned count_rnd = (count + adj_start + 4 - 1) / 4 * 4; - if (count_rnd > sl->flash_pgsz) - count_rnd = (unsigned int) sl->flash_pgsz; - if (count_rnd > 0x1800) - count_rnd = 0x1800; - if (count_rnd < count) - count = count_rnd; - - if (stlink_read_mem32(sl, start - adj_start, count_rnd) != 0) { - /* read failed somehow, don't return stale buffer */ - count = 0; - } + if (count_rnd > sl->flash_pgsz) count_rnd = (unsigned int) sl->flash_pgsz; + if (count_rnd > 0x1800) count_rnd = 0x1800; + if (count_rnd < count) count = count_rnd; + + if (stlink_read_mem32(sl, start - adj_start, count_rnd) != 0) count = 0; + // read failed somehow, don't return stale buffer reply = calloc(count * 2 + 1, 1); for (unsigned int i = 0; i < count; i++) { @@ -1785,15 +1681,9 @@ int serve(stlink_t *sl, st_state_t *st) { } case '!': { - /* - * Enter extended mode which allows restarting. - * We do support that always. - */ - - /* - * Also, set to persistent mode - * to allow GDB disconnect. - */ + // Enter extended mode which allows restarting. We do support that always. + + // Also, set to persistent mode to allow GDB disconnect. st->persistent = 1; reply = strdup("OK"); @@ -1802,9 +1692,7 @@ int serve(stlink_t *sl, st_state_t *st) { } case 'R': { - - /* Reset the core. */ - + // Reset the core. ret = stlink_reset(sl); if (ret) { DLOG("R packet : stlink_reset failed\n"); @@ -1819,35 +1707,25 @@ int serve(stlink_t *sl, st_state_t *st) { break; } case 'k': - /* Kill request - reset the connection itself */ + // Kill request - reset the connection itself ret = stlink_run(sl); - if (ret) { - DLOG("Kill: stlink_run failed\n"); - } - + if (ret) DLOG("Kill: stlink_run failed\n"); ret = stlink_exit_debug_mode(sl); - if (ret) { - DLOG("Kill: stlink_exit_debug_mode failed\n"); - } + if (ret) DLOG("Kill: stlink_exit_debug_mode failed\n"); stlink_close(sl); sl = do_connect(st); - if (sl == NULL || sl->chip_id == STLINK_CHIPID_UNKNOWN) - cleanup(0); + if (sl == NULL || sl->chip_id == STLINK_CHIPID_UNKNOWN) cleanup(0); connected_stlink = sl; - if (st->reset) { - stlink_reset(sl); - } + if (st->reset) stlink_reset(sl); ret = stlink_force_debug(sl); - if (ret) { - DLOG("Kill: stlink_force_debug failed\n"); - } + if (ret) DLOG("Kill: stlink_force_debug failed\n"); init_cache(sl); init_code_breakpoints(sl); init_data_watchpoints(sl); - reply = NULL; /* no response */ + reply = NULL; // no response break; diff --git a/src/stlink-lib/usb.c b/src/stlink-lib/usb.c index ec126cc7e..c22f2fe5e 100644 --- a/src/stlink-lib/usb.c +++ b/src/stlink-lib/usb.c @@ -3,9 +3,11 @@ #include #include #include + #if !defined(_MSC_VER) #include #endif + #include #include #include diff --git a/src/win32/unistd/unistd.h b/src/win32/unistd/unistd.h index 5b2798b41..0cdb9af7b 100644 --- a/src/win32/unistd/unistd.h +++ b/src/win32/unistd/unistd.h @@ -3,19 +3,23 @@ /* * This file intended to serve as a drop-in replacement for unistd.h on Windows - * Please add functionality as neeeded. + * Please add functionality as needed. */ #include #include + #if defined(_MSC_VER) #pragma warning(push) #pragma warning(disable: 4820) #endif + #include + #if defined(_MSC_VER) #pragma warning(pop) #endif + #include // getopt at: https://gist.github.com/ashelly/7776712 #include // for getpid() and the exec..() family #include // for _getcwd() and _chdir() @@ -23,7 +27,7 @@ #define srandom srand #define random rand -/* Values for the second argument to access. These may be OR'd together. */ +/* values for the second argument to access. These may be OR'd together. */ #define R_OK 4 // Test for read permission #define W_OK 2 // Test for write permission // #define X_OK 1 // execute permission - unsupported in windows @@ -48,7 +52,7 @@ #define STDIN_FILENO 0 #define STDOUT_FILENO 1 #define STDERR_FILENO 2 -/* should be in some equivalent to */ +// should be in some equivalent to typedef __int8 int8_t; typedef __int16 int16_t; typedef __int32 int32_t; @@ -62,4 +66,4 @@ typedef unsigned __int64 uint64_t; int usleep(unsigned int waitTime); #endif -#endif /* unistd.h */ +#endif // _UNISTD_H diff --git a/src/win32/win32_socket.c b/src/win32/win32_socket.c index 3a3abae16..18f2351f8 100644 --- a/src/win32/win32_socket.c +++ b/src/win32/win32_socket.c @@ -220,7 +220,7 @@ char * win32_strtok_r(char *s, const char *delim, char **lasts) { } } while (sc != 0); } - /* NOTREACHED */ + // NOT REACHED } char *win32_strsep (char **stringp, const char *delim) { @@ -245,7 +245,7 @@ char *win32_strsep (char **stringp, const char *delim) { } } while (sc != 0); } - /* NOTREACHED */ + // NOT REACHED } #ifndef STLINK_HAVE_UNISTD_H diff --git a/src/win32/win32_socket.h b/src/win32/win32_socket.h index 0d26a80e3..d2a3ac38c 100644 --- a/src/win32/win32_socket.h +++ b/src/win32/win32_socket.h @@ -1,4 +1,4 @@ -#if defined(__MINGW32__) || defined(_MSC_VER) +#if defined(_WIN32) #define _USE_W32_SOCKETS 1 @@ -71,4 +71,4 @@ char *win32_strsep(char **stringp, const char *delim); ssize_t win32_read_socket(SOCKET fd, void *buf, int n); ssize_t win32_write_socket(SOCKET fd, void *buf, int n); -#endif // defined(__MINGW32__) || defined(_MSC_VER) +#endif // defined(_WIN32) From 03a358bd078f8d0c965b26ba2ae3098894a2179a Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sat, 6 Jun 2020 01:00:17 +0200 Subject: [PATCH 028/503] Added check for cflag -std=gnu18 --- cmake/modules/c_flags.cmake | 1 + 1 file changed, 1 insertion(+) diff --git a/cmake/modules/c_flags.cmake b/cmake/modules/c_flags.cmake index 520182e37..8291ea0ee 100644 --- a/cmake/modules/c_flags.cmake +++ b/cmake/modules/c_flags.cmake @@ -18,6 +18,7 @@ function(add_cflag_if_supported flag) endfunction() add_cflag_if_supported("-std=gnu11") +add_cflag_if_supported("-std=gnu18") add_cflag_if_supported("-Wall") add_cflag_if_supported("-Wextra") add_cflag_if_supported("-Wshadow") From 77df52ff61fdfe2c8675b504e523535bf972da61 Mon Sep 17 00:00:00 2001 From: Luca Boccassi Date: Sat, 6 Jun 2020 12:34:32 +0100 Subject: [PATCH 029/503] Update Files-Excluded in d/copyright for new layout --- debian/copyright | 4 +--- debian/source/options | 2 +- 2 files changed, 2 insertions(+), 4 deletions(-) diff --git a/debian/copyright b/debian/copyright index d56807ca5..cf13a5b4f 100644 --- a/debian/copyright +++ b/debian/copyright @@ -4,9 +4,7 @@ Upstream-Contact: Andrew 'Necromant' Andrianov Source: https://github.com/texane/stlink Comment: Upstream tarball has been repackaged to remove binary OSX kernel drivers that are of unknown license and of no use to Debian. - Upstream's debian directory is also removed. -Files-Excluded: stlinkv1_macosx_driver - debian +Files-Excluded: stlinkv1_macos_driver Files: * Copyright: 2011-2018 agpanarin diff --git a/debian/source/options b/debian/source/options index 7022977a9..506210d2c 100644 --- a/debian/source/options +++ b/debian/source/options @@ -1 +1 @@ -extend-diff-ignore=stlinkv1_macosx_driver +extend-diff-ignore=stlinkv1_macos_driver From 3775e7504eeecbae40813993dc181ae1605a5235 Mon Sep 17 00:00:00 2001 From: Luca Boccassi Date: Sat, 6 Jun 2020 12:36:32 +0100 Subject: [PATCH 030/503] Fix d/watch intermediary file name --- debian/watch | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/debian/watch b/debian/watch index 921dc8f0d..45fece19b 100644 --- a/debian/watch +++ b/debian/watch @@ -1,3 +1,3 @@ version=3 -opts=dversionmangle=s/\+ds$//,repacksuffix=+ds,filenamemangle=s/.+\/v?(\d\S+)\.tar\.gz/-$1\.tar\.gz/ \ +opts=dversionmangle=s/\+ds$//,repacksuffix=+ds,filenamemangle=s/.+\/v?(\d\S+)\.tar\.gz/stlink-$1\.tar\.gz/ \ https://github.com/texane/stlink/tags .*/v?(\d\S+)\.tar\.gz From b4ddd0d38dfabb88298179fcaf6f5fefa274e35d Mon Sep 17 00:00:00 2001 From: Luca Boccassi Date: Sat, 6 Jun 2020 12:44:55 +0100 Subject: [PATCH 031/503] Drop cross.patch, merged upstream in v1.6.1 --- debian/patches/cross.patch | 15 --------------- debian/patches/series | 1 - 2 files changed, 16 deletions(-) delete mode 100644 debian/patches/cross.patch delete mode 100644 debian/patches/series diff --git a/debian/patches/cross.patch b/debian/patches/cross.patch deleted file mode 100644 index 92084238b..000000000 --- a/debian/patches/cross.patch +++ /dev/null @@ -1,15 +0,0 @@ -Author: Helmut Grohne -Description: do not stop the GUI from being cross-compiled -Bug-Debian: 941320 -Forwarded: yes ---- a/CMakeLists.txt -+++ b/CMakeLists.txt -@@ -39,7 +39,7 @@ - # Dependencies - ### - find_package(LibUSB REQUIRED) --if (NOT APPLE AND NOT WIN32 AND NOT CMAKE_CROSSCOMPILING) -+if (NOT APPLE AND NOT WIN32) - find_package(PkgConfig) - pkg_check_modules(gtk gtk+-3.0) - endif () diff --git a/debian/patches/series b/debian/patches/series deleted file mode 100644 index def274a02..000000000 --- a/debian/patches/series +++ /dev/null @@ -1 +0,0 @@ -cross.patch From fbaf536f940a5f93debc72ba69429dae4bba9252 Mon Sep 17 00:00:00 2001 From: Luca Boccassi Date: Sat, 6 Jun 2020 14:30:41 +0100 Subject: [PATCH 032/503] Bump Build-Depends to cmake >= 3.4.2 --- debian/control | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/debian/control b/debian/control index 4382cdcd5..0e81de671 100644 --- a/debian/control +++ b/debian/control @@ -1,7 +1,7 @@ Source: stlink Priority: optional Maintainer: Luca Boccassi -Build-Depends: debhelper (>= 9), cmake, libusb-1.0-0-dev, libgtk-3-dev +Build-Depends: debhelper (>= 9), cmake (>= 3.4.2), libusb-1.0-0-dev, libgtk-3-dev Standards-Version: 4.5.0 Rules-Requires-Root: no Section: electronics From 1ea5b4d8ff9bae9fc4d921563f800129e66ae164 Mon Sep 17 00:00:00 2001 From: Luca Boccassi Date: Sat, 6 Jun 2020 14:30:56 +0100 Subject: [PATCH 033/503] Add new symbols from upstream version 1.6.1 --- debian/libstlink1.symbols | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/debian/libstlink1.symbols b/debian/libstlink1.symbols index 4518989a1..159f27d0f 100644 --- a/debian/libstlink1.symbols +++ b/debian/libstlink1.symbols @@ -1,4 +1,8 @@ libstlink.so.1 libstlink1 #MINVER# + Md5Calculate@Base 1.6.1 + Md5Finalise@Base 1.6.1 + Md5Initialise@Base 1.6.1 + Md5Update@Base 1.6.1 _parse_version@Base 1.5.0 _stlink_sg_close@Base 1.5.0 _stlink_sg_core_id@Base 1.5.0 @@ -29,6 +33,7 @@ libstlink.so.1 libstlink1 #MINVER# _stlink_usb_exit_debug_mode@Base 1.5.0 _stlink_usb_exit_dfu_mode@Base 1.5.0 _stlink_usb_force_debug@Base 1.5.0 + _stlink_usb_get_rw_status@Base 1.6.1 _stlink_usb_jtag_reset@Base 1.5.0 _stlink_usb_read_all_regs@Base 1.5.0 _stlink_usb_read_all_unsupported_regs@Base 1.5.0 @@ -40,6 +45,7 @@ libstlink.so.1 libstlink1 #MINVER# _stlink_usb_run@Base 1.5.0 _stlink_usb_set_swdclk@Base 1.5.0 _stlink_usb_status@Base 1.5.0 + _stlink_usb_status_v2@Base 1.6.1 _stlink_usb_step@Base 1.5.0 _stlink_usb_target_voltage@Base 1.5.0 _stlink_usb_version@Base 1.5.0 @@ -79,7 +85,7 @@ libstlink.so.1 libstlink1 #MINVER# stlink_fread@Base 1.5.0 stlink_fwrite_flash@Base 1.5.0 stlink_fwrite_option_bytes@Base 1.6.0 - stlink_fwrite_option_bytes_32bit@Base 1.6.0 +#MISSING: 1.6.1# stlink_fwrite_option_bytes_32bit@Base 1.6.0 stlink_fwrite_sram@Base 1.5.0 stlink_get_erased_pattern@Base 1.5.0 stlink_is_core_halted@Base 1.5.0 @@ -97,8 +103,11 @@ libstlink.so.1 libstlink1 #MINVER# stlink_read_all_unsupported_regs@Base 1.5.0 stlink_read_debug32@Base 1.5.0 stlink_read_mem32@Base 1.5.0 + stlink_read_option_bytes32@Base 1.6.1 + stlink_read_option_bytes_Gx@Base 1.6.1 stlink_read_option_bytes_f2@Base 1.6.0 stlink_read_option_bytes_f4@Base 1.6.0 + stlink_read_option_bytes_generic@Base 1.6.1 stlink_read_reg@Base 1.5.0 stlink_read_unsupported_reg@Base 1.5.0 stlink_reset@Base 1.5.0 @@ -119,11 +128,13 @@ libstlink.so.1 libstlink1 #MINVER# stlink_write_flash@Base 1.5.0 stlink_write_mem32@Base 1.5.0 stlink_write_mem8@Base 1.5.0 + stlink_write_option_bytes32@Base 1.6.1 stlink_write_option_bytes@Base 1.6.0 stlink_write_reg@Base 1.5.0 stlink_write_unsupported_reg@Base 1.5.0 stm32l1_write_half_pages@Base 1.5.0 ugly_init@Base 1.5.0 + ugly_libusb_log_level@Base 1.6.1 ugly_log@Base 1.5.0 write_buffer_to_sram@Base 1.5.0 write_uint16@Base 1.5.0 From c74c942a37913f70fa96a3e10dc6527b026c8fe7 Mon Sep 17 00:00:00 2001 From: Luca Boccassi Date: Sat, 6 Jun 2020 14:31:24 +0100 Subject: [PATCH 034/503] Adjust install files, some files moved --- debian/stlink-gui.install | 8 ++++---- debian/stlink-tools.manpages | 4 +++- 2 files changed, 7 insertions(+), 5 deletions(-) diff --git a/debian/stlink-gui.install b/debian/stlink-gui.install index b419ac054..5620a25e5 100644 --- a/debian/stlink-gui.install +++ b/debian/stlink-gui.install @@ -1,4 +1,4 @@ -/usr/bin/stlink-gui* -/usr/share/stlink/stlink-gui.ui -/usr/share/applications/stlink-gui.desktop -/usr/share/icons/hicolor/scalable/apps/stlink-gui.svg +/usr/bin/stlink-gui +/usr/bin/stlink-gui.ui /usr/share/stlink/ +/usr/share/stlink/applications/stlink-gui.desktop /usr/share/applications/ +/usr/share/stlink/icons/hicolor/scalable/apps/stlink-gui.svg /usr/share/icons/hicolor/scalable/apps/stlink-gui.svg diff --git a/debian/stlink-tools.manpages b/debian/stlink-tools.manpages index 6a461c09e..049509abe 100644 --- a/debian/stlink-tools.manpages +++ b/debian/stlink-tools.manpages @@ -1 +1,3 @@ -doc/man/st-*.1 +usr/share/stlink/man/man1/st-flash.1 +usr/share/stlink/man/man1/st-info.1 +usr/share/stlink/man/man1/st-util.1 From f5095079717ebe4168ac26ea0b4a65c0b1f4ec1f Mon Sep 17 00:00:00 2001 From: Luca Boccassi Date: Sat, 6 Jun 2020 14:31:41 +0100 Subject: [PATCH 035/503] Remove unused variable from d/rules --- debian/rules | 1 - 1 file changed, 1 deletion(-) diff --git a/debian/rules b/debian/rules index e228a7087..99ee08aa7 100755 --- a/debian/rules +++ b/debian/rules @@ -15,5 +15,4 @@ export DEB_BUILD_MAINT_OPTIONS = hardening=+all override_dh_auto_configure: dh_auto_configure -- \ - -DLIB_INSTALL_DIR=/usr/lib/$(DEB_HOST_MULTIARCH) \ -DSTLINK_UDEV_RULES_DIR='/lib/udev/rules.d' From 0052b907a9c216b816c79abc33b8ffb8fd29ec4f Mon Sep 17 00:00:00 2001 From: Luca Boccassi Date: Sat, 6 Jun 2020 14:32:03 +0100 Subject: [PATCH 036/503] Generate pkgconfig file from d/rules, upstream doesn't do it --- debian/rules | 5 +++++ debian/stlink.pc.in | 10 ++++++++++ 2 files changed, 15 insertions(+) create mode 100644 debian/stlink.pc.in diff --git a/debian/rules b/debian/rules index 99ee08aa7..512bd533f 100755 --- a/debian/rules +++ b/debian/rules @@ -16,3 +16,8 @@ export DEB_BUILD_MAINT_OPTIONS = hardening=+all override_dh_auto_configure: dh_auto_configure -- \ -DSTLINK_UDEV_RULES_DIR='/lib/udev/rules.d' + +override_dh_auto_install: + dh_auto_install + mkdir -p $(CURDIR)/debian/tmp/usr/lib/$(DEB_HOST_MULTIARCH)/pkgconfig + sed -e "s/@VERSION@/$(DEB_VERSION_UPSTREAM)/" -e "s/@DEB_HOST_MULTIARCH@/$(DEB_HOST_MULTIARCH)/" $(CURDIR)/debian/stlink.pc.in > $(CURDIR)/debian/tmp/usr/lib/$(DEB_HOST_MULTIARCH)/pkgconfig/stlink.pc diff --git a/debian/stlink.pc.in b/debian/stlink.pc.in new file mode 100644 index 000000000..7fde2d968 --- /dev/null +++ b/debian/stlink.pc.in @@ -0,0 +1,10 @@ +prefix=/usr +includedir=${prefix}/include/stlink +libdir=${prefix}/lib/@DEB_HOST_MULTIARCH@ + +Name: stlink +Description: Open source version of the STMicroelectronics Stlink Tools +Version: @VERSION@ +Requires: libusb-1.0 +Libs: -L${libdir} -lstlink +Cflags: -I${includedir} From b85c7fb41e9b5a8c5dcde7f6f241d101537e161f Mon Sep 17 00:00:00 2001 From: Luca Boccassi Date: Sat, 6 Jun 2020 14:33:19 +0100 Subject: [PATCH 037/503] Switch to debhelper-compat 12 --- debian/compat | 1 - debian/control | 2 +- 2 files changed, 1 insertion(+), 2 deletions(-) delete mode 100644 debian/compat diff --git a/debian/compat b/debian/compat deleted file mode 100644 index ec635144f..000000000 --- a/debian/compat +++ /dev/null @@ -1 +0,0 @@ -9 diff --git a/debian/control b/debian/control index 0e81de671..7172583e9 100644 --- a/debian/control +++ b/debian/control @@ -1,7 +1,7 @@ Source: stlink Priority: optional Maintainer: Luca Boccassi -Build-Depends: debhelper (>= 9), cmake (>= 3.4.2), libusb-1.0-0-dev, libgtk-3-dev +Build-Depends: debhelper-compat (= 12), cmake (>= 3.4.2), libusb-1.0-0-dev, libgtk-3-dev Standards-Version: 4.5.0 Rules-Requires-Root: no Section: electronics From 7056afe415028d6786075d12325e3b835e5d0f02 Mon Sep 17 00:00:00 2001 From: Luca Boccassi Date: Sat, 6 Jun 2020 14:45:15 +0100 Subject: [PATCH 038/503] Update changelog for 1.6.1+ds-1 release --- debian/changelog | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/debian/changelog b/debian/changelog index 0ad68fed3..26f17b1fb 100644 --- a/debian/changelog +++ b/debian/changelog @@ -1,3 +1,18 @@ +stlink (1.6.1+ds-1) unstable; urgency=medium + + * Merge tag 'v1.6.1' into debian + * Update Files-Excluded in d/copyright for new layout + * Fix d/watch intermediary file name + * Drop cross.patch, merged upstream in v1.6.1 + * Bump Build-Depends to cmake >= 3.4.2 + * Add new symbols from upstream version 1.6.1 + * Adjust install files, some files moved + * Remove unused variable from d/rules + * Generate pkgconfig file from d/rules, upstream doesn't do it + * Switch to debhelper-compat 12 + + -- Luca Boccassi Sat, 06 Jun 2020 14:44:54 +0100 + stlink (1.6.0+ds-1) unstable; urgency=medium * Merge tag 'v1.6.0' into debian From c1918c0ff636494546bddbc5cc3793fc287c6594 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Fri, 12 Jun 2020 22:28:16 +0200 Subject: [PATCH 039/503] Aligned coding style - Added config for uncrustify style settings - Applied changes to source files - Moved some header files --- CMakeLists.txt | 7 +- config/code_style.cfg | 3090 ++++++++++++++++++++++++ flashloaders/linker.ld | 6 +- {src => inc}/backend.h | 4 +- inc/stlink.h | 57 +- inc/stm32.h | 10 +- inc/version.h.in | 2 +- src/common.c | 1970 +++++++-------- src/reg.h | 20 - src/st-flash/flash.c | 153 +- src/st-flash/flash.h | 11 +- src/st-flash/flash_opts.c | 342 +-- src/st-info/info.c | 103 +- src/st-util/gdb-remote.c | 55 +- src/st-util/gdb-remote.h | 2 +- src/st-util/gdb-server.c | 1664 +++++++------ src/st-util/gdb-server.h | 2 +- src/st-util/semihosting.c | 230 +- src/st-util/semihosting.h | 4 +- src/stlink-gui/gui.c | 1089 +++++---- src/stlink-gui/gui.h | 39 +- src/stlink-lib/chipid.c | 1259 +++++----- src/stlink-lib/chipid.h | 134 +- src/{ => stlink-lib}/commands.h | 2 +- src/stlink-lib/flash_loader.c | 497 ++-- src/stlink-lib/flash_loader.h | 8 +- src/{ => stlink-lib}/libusb_settings.h | 36 +- src/stlink-lib/logging.c | 36 +- src/stlink-lib/logging.h | 17 +- src/stlink-lib/md5.c | 259 +- src/stlink-lib/md5.h | 127 +- src/stlink-lib/reg.h | 20 + src/stlink-lib/sg.c | 401 +-- src/stlink-lib/sg.h | 45 +- src/stlink-lib/usb.c | 603 +++-- src/stlink-lib/usb.h | 66 +- src/win32/getopt/README.md | 7 +- src/win32/getopt/getopt.c | 341 ++- src/win32/getopt/getopt.h | 15 +- src/win32/mmap.c | 18 +- src/win32/unistd/unistd.h | 27 +- src/win32/win32_socket.c | 144 +- src/win32/win32_socket.h | 4 +- tests/flash.c | 237 +- tests/sg.c | 58 +- tests/usb.c | 42 +- 46 files changed, 8306 insertions(+), 4957 deletions(-) create mode 100644 config/code_style.cfg rename {src => inc}/backend.h (94%) delete mode 100644 src/reg.h rename src/{ => stlink-lib}/commands.h (97%) rename src/{ => stlink-lib}/libusb_settings.h (53%) create mode 100644 src/stlink-lib/reg.h diff --git a/CMakeLists.txt b/CMakeLists.txt index 8428e7565..52f6867f4 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -95,10 +95,11 @@ include_directories(src/st-flash) include_directories(src/stlink-lib) set(STLINK_HEADERS + inc/backend.h + src/stlink-lib/commands.h + src/stlink-lib/libusb_settings.h + src/stlink-lib/reg.h inc/stlink.h - src/backend.h - src/commands.h - src/reg.h src/stlink-lib/chipid.h src/stlink-lib/flash_loader.h src/stlink-lib/logging.h diff --git a/config/code_style.cfg b/config/code_style.cfg new file mode 100644 index 000000000..c6ced268c --- /dev/null +++ b/config/code_style.cfg @@ -0,0 +1,3090 @@ +# Uncrustify-0.71.0 + +# +# General options +# + +# The type of line endings. +# +# Default: auto +newlines = auto # lf/crlf/cr/auto + +# The original size of tabs in the input. +# +# Default: 8 +input_tab_size = 4 # unsigned number + +# The size of tabs in the output (only used if align_with_tabs=true). +# +# Default: 8 +output_tab_size = 4 # unsigned number + +# The ASCII value of the string escape char, usually 92 (\) or (Pawn) 94 (^). +# +# Default: 92 +string_escape_char = 92 # unsigned number + +# Alternate string escape char (usually only used for Pawn). +# Only works right before the quote char. +string_escape_char2 = 0 # unsigned number + +# Replace tab characters found in string literals with the escape sequence \t +# instead. +string_replace_tab_chars = false # true/false + +# Allow interpreting '>=' and '>>=' as part of a template in code like +# 'void f(list>=val);'. If true, 'assert(x<0 && y>=3)' will be broken. +# Improvements to template detection may make this option obsolete. +tok_split_gte = false # true/false + +# Disable formatting of NL_CONT ('\\n') ended lines (e.g. multiline macros) +#disable_processing_nl_cont = false # true/false ### not 0.69 + +# Specify the marker used in comments to disable processing of part of the +# file. +# The comment should be used alone in one line. +# +# Default: *INDENT-OFF* +disable_processing_cmt = " *INDENT-OFF*" # string + +# Specify the marker used in comments to (re)enable processing in a file. +# The comment should be used alone in one line. +# +# Default: *INDENT-ON* +enable_processing_cmt = " *INDENT-ON*" # string + +# Enable parsing of digraphs. +enable_digraphs = false # true/false + +# Add or remove the UTF-8 BOM (recommend 'remove'). +utf8_bom = ignore # ignore/add/remove/force + +# If the file contains bytes with values between 128 and 255, but is not +# UTF-8, then output as UTF-8. +utf8_byte = false # true/false + +# Force the output encoding to UTF-8. +utf8_force = true # true/false + +# Add or remove space between 'do' and '{'. +#sp_do_brace_open = add # ignore/add/remove/force ### not 0.69 + +# Add or remove space between '}' and 'while'. +#sp_brace_close_while = add # ignore/add/remove/force ### not 0.69 + +# Add or remove space between 'while' and '('. +#sp_while_paren_open = add # ignore/add/remove/force ### not 0.69 + +# +# Spacing options +# + +# Add or remove space around non-assignment symbolic operators ('+', '/', '%', +# '<<', and so forth). +sp_arith = add # ignore/add/remove/force + +# Add or remove space around arithmetic operators '+' and '-'. +# +# Overrides sp_arith. +sp_arith_additive = add # ignore/add/remove/force + +# Add or remove space around assignment operator '=', '+=', etc. +sp_assign = add # ignore/add/remove/force + +# Add or remove space around '=' in C++11 lambda capture specifications. +# +# Overrides sp_assign. +sp_cpp_lambda_assign = add # ignore/add/remove/force + +# Add or remove space after the capture specification of a C++11 lambda when +# an argument list is present, as in '[] (int x){ ... }'. +#sp_cpp_lambda_square_paren = add # ignore/add/remove/force ### not 0.69 + +# Add or remove space after the capture specification of a C++11 lambda with +# no argument list is present, as in '[] { ... }'. +#sp_cpp_lambda_square_brace = add # ignore/add/remove/force ### not 0.69 + +# Add or remove space after the argument list of a C++11 lambda, as in +# '[](int x) { ... }'. +#sp_cpp_lambda_paren_brace = add # ignore/add/remove/force ### not 0.69 + +# Add or remove space between a lambda body and its call operator of an +# immediately invoked lambda, as in '[]( ... ){ ... } ( ... )'. +#sp_cpp_lambda_fparen = add # ignore/add/remove/force ### not 0.69 + +# Add or remove space around assignment operator '=' in a prototype. +# +# If set to ignore, use sp_assign. +sp_assign_default = add # ignore/add/remove/force + +# Add or remove space before assignment operator '=', '+=', etc. +# +# Overrides sp_assign. +sp_before_assign = add # ignore/add/remove/force + +# Add or remove space after assignment operator '=', '+=', etc. +# +# Overrides sp_assign. +sp_after_assign = add # ignore/add/remove/force + +# Add or remove space in 'NS_ENUM ('. +sp_enum_paren = add # ignore/add/remove/force + +# Add or remove space around assignment '=' in enum. +sp_enum_assign = add # ignore/add/remove/force + +# Add or remove space before assignment '=' in enum. +# +# Overrides sp_enum_assign. +sp_enum_before_assign = add # ignore/add/remove/force + +# Add or remove space after assignment '=' in enum. +# +# Overrides sp_enum_assign. +sp_enum_after_assign = add # ignore/add/remove/force + +# Add or remove space around assignment ':' in enum. +sp_enum_colon = add # ignore/add/remove/force + +# Add or remove space around preprocessor '##' concatenation operator. +# +# Default: add +sp_pp_concat = add # ignore/add/remove/force + +# Add or remove space after preprocessor '#' stringify operator. +# Also affects the '#@' charizing operator. +sp_pp_stringify = ignore # ignore/add/remove/force + +# Add or remove space before preprocessor '#' stringify operator +# as in '#define x(y) L#y'. +sp_before_pp_stringify = ignore # ignore/add/remove/force + +# Add or remove space around boolean operators '&&' and '||'. +sp_bool = add # ignore/add/remove/force + +# Add or remove space around compare operator '<', '>', '==', etc. +sp_compare = add # ignore/add/remove/force + +# Add or remove space inside '(' and ')'. +sp_inside_paren = remove # ignore/add/remove/force + +# Add or remove space between nested parentheses, i.e. '((' vs. ') )'. +sp_paren_paren = remove # ignore/add/remove/force + +# Add or remove space between back-to-back parentheses, i.e. ')(' vs. ') ('. +sp_cparen_oparen = add # ignore/add/remove/force + +# Whether to balance spaces inside nested parentheses. +sp_balance_nested_parens = false # true/false + +# Add or remove space between ')' and '{'. +sp_paren_brace = add # ignore/add/remove/force + +# Add or remove space between nested braces, i.e. '{{' vs '{ {'. +sp_brace_brace = remove # ignore/add/remove/force + +# Add or remove space before pointer star '*'. +sp_before_ptr_star = ignore # ignore/add/remove/force + +# Add or remove space before pointer star '*' that isn't followed by a +# variable name. If set to ignore, sp_before_ptr_star is used instead. +sp_before_unnamed_ptr_star = ignore # ignore/add/remove/force + +# Add or remove space between pointer stars '*'. +sp_between_ptr_star = ignore # ignore/add/remove/force + +# Add or remove space after pointer star '*', if followed by a word. +# +# Overrides sp_type_func. +sp_after_ptr_star = ignore # ignore/add/remove/force + +# Add or remove space after pointer caret '^', if followed by a word. +sp_after_ptr_block_caret = ignore # ignore/add/remove/force + +# Add or remove space after pointer star '*', if followed by a qualifier. +sp_after_ptr_star_qualifier = ignore # ignore/add/remove/force + +# Add or remove space after a pointer star '*', if followed by a function +# prototype or function definition. +# +# Overrides sp_after_ptr_star and sp_type_func. +sp_after_ptr_star_func = ignore # ignore/add/remove/force + +# Add or remove space after a pointer star '*', if followed by an open +# parenthesis, as in 'void* (*)(). +sp_ptr_star_paren = ignore # ignore/add/remove/force + +# Add or remove space before a pointer star '*', if followed by a function +# prototype or function definition. +sp_before_ptr_star_func = ignore # ignore/add/remove/force + +# Add or remove space before a reference sign '&'. +sp_before_byref = ignore # ignore/add/remove/force + +# Add or remove space before a reference sign '&' that isn't followed by a +# variable name. If set to ignore, sp_before_byref is used instead. +sp_before_unnamed_byref = ignore # ignore/add/remove/force + +# Add or remove space after reference sign '&', if followed by a word. +# +# Overrides sp_type_func. +sp_after_byref = ignore # ignore/add/remove/force + +# Add or remove space after a reference sign '&', if followed by a function +# prototype or function definition. +# +# Overrides sp_after_byref and sp_type_func. +sp_after_byref_func = ignore # ignore/add/remove/force + +# Add or remove space before a reference sign '&', if followed by a function +# prototype or function definition. +sp_before_byref_func = ignore # ignore/add/remove/force + +# Add or remove space between type and word. +# +# Default: force +sp_after_type = force # ignore/add/remove/force + +# Add or remove space between 'decltype(...)' and word. +sp_after_decltype = ignore # ignore/add/remove/force + +# (D) Add or remove space before the parenthesis in the D constructs +# 'template Foo(' and 'class Foo('. +sp_before_template_paren = ignore # ignore/add/remove/force + +# Add or remove space between 'template' and '<'. +# If set to ignore, sp_before_angle is used. +sp_template_angle = ignore # ignore/add/remove/force + +# Add or remove space before '<'. +sp_before_angle = ignore # ignore/add/remove/force + +# Add or remove space inside '<' and '>'. +sp_inside_angle = ignore # ignore/add/remove/force + +# Add or remove space inside '<>'. +sp_inside_angle_empty = add # ignore/add/remove/force + +# Add or remove space between '>' and ':'. +sp_angle_colon = ignore # ignore/add/remove/force + +# Add or remove space after '>'. +sp_after_angle = ignore # ignore/add/remove/force + +# Add or remove space between '>' and '(' as found in 'new List(foo);'. +sp_angle_paren = remove # ignore/add/remove/force + +# Add or remove space between '>' and '()' as found in 'new List();'. +sp_angle_paren_empty = remove # ignore/add/remove/force + +# Add or remove space between '>' and a word as in 'List m;' or +# 'template static ...'. +sp_angle_word = add # ignore/add/remove/force + +# Add or remove space between '>' and '>' in '>>' (template stuff). +# +# Default: add +sp_angle_shift = add # ignore/add/remove/force + +# (C++11) Permit removal of the space between '>>' in 'foo >'. Note +# that sp_angle_shift cannot remove the space without this option. +sp_permit_cpp11_shift = false # true/false + +# Add or remove space before '(' of control statements ('if', 'for', 'switch', +# 'while', etc.). +sp_before_sparen = add # ignore/add/remove/force + +# Add or remove space inside '(' and ')' of control statements. +sp_inside_sparen = ignore # ignore/add/remove/force + +# Add or remove space after '(' of control statements. +# +# Overrides sp_inside_sparen. +sp_inside_sparen_open = ignore # ignore/add/remove/force + +# Add or remove space before ')' of control statements. +# +# Overrides sp_inside_sparen. +sp_inside_sparen_close = ignore # ignore/add/remove/force + +# Add or remove space after ')' of control statements. +sp_after_sparen = ignore # ignore/add/remove/force + +# Add or remove space between ')' and '{' of of control statements. +sp_sparen_brace = add # ignore/add/remove/force + +# (D) Add or remove space between 'invariant' and '('. +sp_invariant_paren = ignore # ignore/add/remove/force + +# (D) Add or remove space after the ')' in 'invariant (C) c'. +sp_after_invariant_paren = ignore # ignore/add/remove/force + +# Add or remove space before empty statement ';' on 'if', 'for' and 'while'. +sp_special_semi = add # ignore/add/remove/force + +# Add or remove space before ';'. +# +# Default: remove +sp_before_semi = remove # ignore/add/remove/force + +# Add or remove space before ';' in non-empty 'for' statements. +sp_before_semi_for = remove # ignore/add/remove/force + +# Add or remove space before a semicolon of an empty part of a for statement. +sp_before_semi_for_empty = add # ignore/add/remove/force + +# Add or remove space after ';', except when followed by a comment. +# +# Default: add +sp_after_semi = add # ignore/add/remove/force + +# Add or remove space after ';' in non-empty 'for' statements. +# +# Default: force +sp_after_semi_for = force # ignore/add/remove/force + +# Add or remove space after the final semicolon of an empty part of a for +# statement, as in 'for ( ; ; )'. +sp_after_semi_for_empty = ignore # ignore/add/remove/force + +# Add or remove space before '[' (except '[]'). +sp_before_square = ignore # ignore/add/remove/force + +# Add or remove space before '[' for a variable definition. +# +# Default: remove +#sp_before_vardef_square = remove # ignore/add/remove/force ### not 0.69 + +# Add or remove space before '[' for asm block. +#sp_before_square_asm_block = ignore # ignore/add/remove/force ### not 0.69 + +# Add or remove space before '[]'. +sp_before_squares = ignore # ignore/add/remove/force + +# Add or remove space before C++17 structured bindings. +sp_cpp_before_struct_binding = ignore # ignore/add/remove/force + +# Add or remove space inside a non-empty '[' and ']'. +sp_inside_square = ignore # ignore/add/remove/force + +# (OC) Add or remove space inside a non-empty Objective-C boxed array '@[' and +# ']'. If set to ignore, sp_inside_square is used. +sp_inside_square_oc_array = ignore # ignore/add/remove/force + +# Add or remove space after ',', i.e. 'a,b' vs. 'a, b'. +sp_after_comma = add # ignore/add/remove/force + +# Add or remove space before ','. +# +# Default: remove +sp_before_comma = remove # ignore/add/remove/force + +# (C#) Add or remove space between ',' and ']' in multidimensional array type +# like 'int[,,]'. +sp_after_mdatype_commas = ignore # ignore/add/remove/force + +# (C#) Add or remove space between '[' and ',' in multidimensional array type +# like 'int[,,]'. +sp_before_mdatype_commas = ignore # ignore/add/remove/force + +# (C#) Add or remove space between ',' in multidimensional array type +# like 'int[,,]'. +sp_between_mdatype_commas = ignore # ignore/add/remove/force + +# Add or remove space between an open parenthesis and comma, +# i.e. '(,' vs. '( ,'. +# +# Default: force +sp_paren_comma = force # ignore/add/remove/force + +# Add or remove space before the variadic '...' when preceded by a +# non-punctuator. +sp_before_ellipsis = ignore # ignore/add/remove/force + +# Add or remove space between a type and '...'. +sp_type_ellipsis = ignore # ignore/add/remove/force + +# (D) Add or remove space between a type and '?'. +sp_type_question = ignore # ignore/add/remove/force + +# Add or remove space between ')' and '...'. +sp_paren_ellipsis = ignore # ignore/add/remove/force + +# Add or remove space between ')' and a qualifier such as 'const'. +sp_paren_qualifier = ignore # ignore/add/remove/force + +# Add or remove space between ')' and 'noexcept'. +sp_paren_noexcept = ignore # ignore/add/remove/force + +# Add or remove space after class ':'. +sp_after_class_colon = ignore # ignore/add/remove/force + +# Add or remove space before class ':'. +sp_before_class_colon = ignore # ignore/add/remove/force + +# Add or remove space after class constructor ':'. +sp_after_constr_colon = ignore # ignore/add/remove/force + +# Add or remove space before class constructor ':'. +sp_before_constr_colon = ignore # ignore/add/remove/force + +# Add or remove space before case ':'. +# +# Default: remove +sp_before_case_colon = remove # ignore/add/remove/force + +# Add or remove space between 'operator' and operator sign. +sp_after_operator = ignore # ignore/add/remove/force + +# Add or remove space between the operator symbol and the open parenthesis, as +# in 'operator ++('. +sp_after_operator_sym = ignore # ignore/add/remove/force + +# Overrides sp_after_operator_sym when the operator has no arguments, as in +# 'operator *()'. +sp_after_operator_sym_empty = ignore # ignore/add/remove/force + +# Add or remove space after C/D cast, i.e. 'cast(int)a' vs. 'cast(int) a' or +# '(int)a' vs. '(int) a'. +sp_after_cast = remove # ignore/add/remove/force + +# Add or remove spaces inside cast parentheses. +sp_inside_paren_cast = ignore # ignore/add/remove/force + +# Add or remove space between the type and open parenthesis in a C++ cast, +# i.e. 'int(exp)' vs. 'int (exp)'. +sp_cpp_cast_paren = remove # ignore/add/remove/force + +# Add or remove space between 'sizeof' and '('. +sp_sizeof_paren = remove # ignore/add/remove/force + +# Add or remove space between 'sizeof' and '...'. +sp_sizeof_ellipsis = add # ignore/add/remove/force + +# Add or remove space between 'sizeof...' and '('. +sp_sizeof_ellipsis_paren = add # ignore/add/remove/force + +# Add or remove space between 'decltype' and '('. +sp_decltype_paren = ignore # ignore/add/remove/force + +# (Pawn) Add or remove space after the tag keyword. +sp_after_tag = ignore # ignore/add/remove/force + +# Add or remove space inside enum '{' and '}'. +sp_inside_braces_enum = ignore # ignore/add/remove/force + +# Add or remove space inside struct/union '{' and '}'. +sp_inside_braces_struct = ignore # ignore/add/remove/force + +# (OC) Add or remove space inside Objective-C boxed dictionary '{' and '}' +sp_inside_braces_oc_dict = ignore # ignore/add/remove/force + +# Add or remove space after open brace in an unnamed temporary +# direct-list-initialization. +sp_after_type_brace_init_lst_open = ignore # ignore/add/remove/force + +# Add or remove space before close brace in an unnamed temporary +# direct-list-initialization. +sp_before_type_brace_init_lst_close = ignore # ignore/add/remove/force + +# Add or remove space inside an unnamed temporary direct-list-initialization. +sp_inside_type_brace_init_lst = ignore # ignore/add/remove/force + +# Add or remove space inside '{' and '}'. +sp_inside_braces = ignore # ignore/add/remove/force + +# Add or remove space inside '{}'. +sp_inside_braces_empty = ignore # ignore/add/remove/force + +# Add or remove space around trailing return operator '->'. +#sp_trailing_return = ignore # ignore/add/remove/force ### not 0.69 + +# Add or remove space between return type and function name. A minimum of 1 +# is forced except for pointer return types. +sp_type_func = ignore # ignore/add/remove/force + +# Add or remove space between type and open brace of an unnamed temporary +# direct-list-initialization. +sp_type_brace_init_lst = ignore # ignore/add/remove/force + +# Add or remove space between function name and '(' on function declaration. +sp_func_proto_paren = remove # ignore/add/remove/force + +# Add or remove space between function name and '()' on function declaration +# without parameters. +sp_func_proto_paren_empty = remove # ignore/add/remove/force + +# Add or remove space between function name and '(' with a typedef specifier. +#sp_func_type_paren = ignore # ignore/add/remove/force ### not 0.69 + +# Add or remove space between alias name and '(' of a non-pointer function type typedef. +sp_func_def_paren = ignore # ignore/add/remove/force + +# Add or remove space between function name and '()' on function definition +# without parameters. +sp_func_def_paren_empty = remove # ignore/add/remove/force + +# Add or remove space inside empty function '()'. +# Overrides sp_after_angle unless use_sp_after_angle_always is set to true. +sp_inside_fparens = ignore # ignore/add/remove/force + +# Add or remove space inside function '(' and ')'. +sp_inside_fparen = ignore # ignore/add/remove/force + +# Add or remove space inside the first parentheses in a function type, as in +# 'void (*x)(...)'. +sp_inside_tparen = ignore # ignore/add/remove/force + +# Add or remove space between the ')' and '(' in a function type, as in +# 'void (*x)(...)'. +sp_after_tparen_close = ignore # ignore/add/remove/force + +# Add or remove space between ']' and '(' when part of a function call. +sp_square_fparen = add # ignore/add/remove/force + +# Add or remove space between ')' and '{' of function. +sp_fparen_brace = add # ignore/add/remove/force + +# Add or remove space between ')' and '{' of s function call in object +# initialization. +# +# Overrides sp_fparen_brace. +sp_fparen_brace_initializer = ignore # ignore/add/remove/force + +# (Java) Add or remove space between ')' and '{{' of double brace initializer. +sp_fparen_dbrace = ignore # ignore/add/remove/force + +# Add or remove space between function name and '(' on function calls. +sp_func_call_paren = ignore # ignore/add/remove/force + +# Add or remove space between function name and '()' on function calls without +# parameters. If set to ignore (the default), sp_func_call_paren is used. +sp_func_call_paren_empty = ignore # ignore/add/remove/force + +# Add or remove space between the user function name and '(' on function +# calls. You need to set a keyword to be a user function in the config file, +# like: +# set func_call_user tr _ i18n +sp_func_call_user_paren = ignore # ignore/add/remove/force + +# Add or remove space inside user function '(' and ')'. +sp_func_call_user_inside_fparen = ignore # ignore/add/remove/force + +# Add or remove space between nested parentheses with user functions, +# i.e. '((' vs. '( ('. +sp_func_call_user_paren_paren = ignore # ignore/add/remove/force + +# Add or remove space between a constructor/destructor and the open +# parenthesis. +sp_func_class_paren = ignore # ignore/add/remove/force + +# Add or remove space between a constructor without parameters or destructor +# and '()'. +sp_func_class_paren_empty = ignore # ignore/add/remove/force + +# Add or remove space between 'return' and '('. +sp_return_paren = ignore # ignore/add/remove/force + +# Add or remove space between 'return' and '{'. +sp_return_brace = ignore # ignore/add/remove/force + +# Add or remove space between '__attribute__' and '('. +sp_attribute_paren = ignore # ignore/add/remove/force + +# Add or remove space between 'defined' and '(' in '#if defined (FOO)'. +sp_defined_paren = ignore # ignore/add/remove/force + +# Add or remove space between 'throw' and '(' in 'throw (something)'. +sp_throw_paren = ignore # ignore/add/remove/force + +# Add or remove space between 'throw' and anything other than '(' as in +# '@throw [...];'. +sp_after_throw = ignore # ignore/add/remove/force + +# Add or remove space between 'catch' and '(' in 'catch (something) { }'. +# If set to ignore, sp_before_sparen is used. +sp_catch_paren = ignore # ignore/add/remove/force + +# (OC) Add or remove space between '@catch' and '(' +# in '@catch (something) { }'. If set to ignore, sp_catch_paren is used. +sp_oc_catch_paren = ignore # ignore/add/remove/force + +# (OC) Add or remove space before Objective-C protocol list +# as in '@protocol Protocol' or '@interface MyClass : NSObject'. +#sp_before_oc_proto_list = ignore # ignore/add/remove/force ### not 0.69 + +# (OC) Add or remove space between class name and '(' +# in '@interface className(categoryName):BaseClass' +sp_oc_classname_paren = ignore # ignore/add/remove/force + +# (D) Add or remove space between 'version' and '(' +# in 'version (something) { }'. If set to ignore, sp_before_sparen is used. +sp_version_paren = ignore # ignore/add/remove/force + +# (D) Add or remove space between 'scope' and '(' +# in 'scope (something) { }'. If set to ignore, sp_before_sparen is used. +sp_scope_paren = ignore # ignore/add/remove/force + +# Add or remove space between 'super' and '(' in 'super (something)'. +# +# Default: remove +sp_super_paren = remove # ignore/add/remove/force + +# Add or remove space between 'this' and '(' in 'this (something)'. +# +# Default: remove +sp_this_paren = remove # ignore/add/remove/force + +# Add or remove space between a macro name and its definition. +sp_macro = ignore # ignore/add/remove/force + +# Add or remove space between a macro function ')' and its definition. +sp_macro_func = ignore # ignore/add/remove/force + +# Add or remove space between 'else' and '{' if on the same line. +sp_else_brace = add # ignore/add/remove/force + +# Add or remove space between '}' and 'else' if on the same line. +sp_brace_else = add # ignore/add/remove/force + +# Add or remove space between '}' and the name of a typedef on the same line. +sp_brace_typedef = add # ignore/add/remove/force + +# Add or remove space before the '{' of a 'catch' statement, if the '{' and +# 'catch' are on the same line, as in 'catch (decl) {'. +sp_catch_brace = add # ignore/add/remove/force + +# (OC) Add or remove space before the '{' of a '@catch' statement, if the '{' +# and '@catch' are on the same line, as in '@catch (decl) {'. +# If set to ignore, sp_catch_brace is used. +sp_oc_catch_brace = ignore # ignore/add/remove/force + +# Add or remove space between '}' and 'catch' if on the same line. +sp_brace_catch = add # ignore/add/remove/force + +# (OC) Add or remove space between '}' and '@catch' if on the same line. +# If set to ignore, sp_brace_catch is used. +sp_oc_brace_catch = ignore # ignore/add/remove/force + +# Add or remove space between 'finally' and '{' if on the same line. +sp_finally_brace = add # ignore/add/remove/force + +# Add or remove space between '}' and 'finally' if on the same line. +sp_brace_finally = add # ignore/add/remove/force + +# Add or remove space between 'try' and '{' if on the same line. +sp_try_brace = add # ignore/add/remove/force + +# Add or remove space between get/set and '{' if on the same line. +sp_getset_brace = add # ignore/add/remove/force + +# Add or remove space between a variable and '{' for C++ uniform +# initialization. +#sp_word_brace_init_lst = add # ignore/add/remove/force ### not 0.69 + +# Add or remove space between a variable and '{' for a namespace. +# +# Default: add +sp_word_brace_ns = add # ignore/add/remove/force + +# Add or remove space before the '::' operator. +sp_before_dc = ignore # ignore/add/remove/force + +# Add or remove space after the '::' operator. +sp_after_dc = ignore # ignore/add/remove/force + +# (D) Add or remove around the D named array initializer ':' operator. +sp_d_array_colon = ignore # ignore/add/remove/force + +# Add or remove space after the '!' (not) unary operator. +# +# Default: remove +sp_not = remove # ignore/add/remove/force + +# Add or remove space after the '~' (invert) unary operator. +# +# Default: remove +sp_inv = remove # ignore/add/remove/force + +# Add or remove space after the '&' (address-of) unary operator. This does not +# affect the spacing after a '&' that is part of a type. +# +# Default: remove +sp_addr = remove # ignore/add/remove/force + +# Add or remove space around the '.' or '->' operators. +# +# Default: remove +sp_member = remove # ignore/add/remove/force + +# Add or remove space after the '*' (dereference) unary operator. This does +# not affect the spacing after a '*' that is part of a type. +# +# Default: remove +sp_deref = remove # ignore/add/remove/force + +# Add or remove space after '+' or '-', as in 'x = -5' or 'y = +7'. +# +# Default: remove +sp_sign = remove # ignore/add/remove/force + +# Add or remove space between '++' and '--' the word to which it is being +# applied, as in '(--x)' or 'y++;'. +# +# Default: remove +sp_incdec = remove # ignore/add/remove/force + +# Add or remove space before a backslash-newline at the end of a line. +# +# Default: add +sp_before_nl_cont = add # ignore/add/remove/force + +# (OC) Add or remove space after the scope '+' or '-', as in '-(void) foo;' +# or '+(int) bar;'. +sp_after_oc_scope = ignore # ignore/add/remove/force + +# (OC) Add or remove space after the colon in message specs, +# i.e. '-(int) f:(int) x;' vs. '-(int) f: (int) x;'. +sp_after_oc_colon = ignore # ignore/add/remove/force + +# (OC) Add or remove space before the colon in message specs, +# i.e. '-(int) f: (int) x;' vs. '-(int) f : (int) x;'. +sp_before_oc_colon = ignore # ignore/add/remove/force + +# (OC) Add or remove space after the colon in immutable dictionary expression +# 'NSDictionary *test = @{@"foo" :@"bar"};'. +sp_after_oc_dict_colon = ignore # ignore/add/remove/force + +# (OC) Add or remove space before the colon in immutable dictionary expression +# 'NSDictionary *test = @{@"foo" :@"bar"};'. +sp_before_oc_dict_colon = ignore # ignore/add/remove/force + +# (OC) Add or remove space after the colon in message specs, +# i.e. '[object setValue:1];' vs. '[object setValue: 1];'. +sp_after_send_oc_colon = ignore # ignore/add/remove/force + +# (OC) Add or remove space before the colon in message specs, +# i.e. '[object setValue:1];' vs. '[object setValue :1];'. +sp_before_send_oc_colon = ignore # ignore/add/remove/force + +# (OC) Add or remove space after the (type) in message specs, +# i.e. '-(int)f: (int) x;' vs. '-(int)f: (int)x;'. +sp_after_oc_type = ignore # ignore/add/remove/force + +# (OC) Add or remove space after the first (type) in message specs, +# i.e. '-(int) f:(int)x;' vs. '-(int)f:(int)x;'. +sp_after_oc_return_type = ignore # ignore/add/remove/force + +# (OC) Add or remove space between '@selector' and '(', +# i.e. '@selector(msgName)' vs. '@selector (msgName)'. +# Also applies to '@protocol()' constructs. +sp_after_oc_at_sel = ignore # ignore/add/remove/force + +# (OC) Add or remove space between '@selector(x)' and the following word, +# i.e. '@selector(foo) a:' vs. '@selector(foo)a:'. +sp_after_oc_at_sel_parens = ignore # ignore/add/remove/force + +# (OC) Add or remove space inside '@selector' parentheses, +# i.e. '@selector(foo)' vs. '@selector( foo )'. +# Also applies to '@protocol()' constructs. +sp_inside_oc_at_sel_parens = ignore # ignore/add/remove/force + +# (OC) Add or remove space before a block pointer caret, +# i.e. '^int (int arg){...}' vs. ' ^int (int arg){...}'. +sp_before_oc_block_caret = ignore # ignore/add/remove/force + +# (OC) Add or remove space after a block pointer caret, +# i.e. '^int (int arg){...}' vs. '^ int (int arg){...}'. +sp_after_oc_block_caret = ignore # ignore/add/remove/force + +# (OC) Add or remove space between the receiver and selector in a message, +# as in '[receiver selector ...]'. +sp_after_oc_msg_receiver = ignore # ignore/add/remove/force + +# (OC) Add or remove space after '@property'. +sp_after_oc_property = ignore # ignore/add/remove/force + +# (OC) Add or remove space between '@synchronized' and the open parenthesis, +# i.e. '@synchronized(foo)' vs. '@synchronized (foo)'. +sp_after_oc_synchronized = ignore # ignore/add/remove/force + +# Add or remove space around the ':' in 'b ? t : f'. +sp_cond_colon = add # ignore/add/remove/force + +# Add or remove space before the ':' in 'b ? t : f'. +# +# Overrides sp_cond_colon. +sp_cond_colon_before = ignore # ignore/add/remove/force + +# Add or remove space after the ':' in 'b ? t : f'. +# +# Overrides sp_cond_colon. +sp_cond_colon_after = ignore # ignore/add/remove/force + +# Add or remove space around the '?' in 'b ? t : f'. +sp_cond_question = add # ignore/add/remove/force + +# Add or remove space before the '?' in 'b ? t : f'. +# +# Overrides sp_cond_question. +sp_cond_question_before = ignore # ignore/add/remove/force + +# Add or remove space after the '?' in 'b ? t : f'. +# +# Overrides sp_cond_question. +sp_cond_question_after = ignore # ignore/add/remove/force + +# In the abbreviated ternary form '(a ?: b)', add or remove space between '?' +# and ':'. +# +# Overrides all other sp_cond_* options. +sp_cond_ternary_short = ignore # ignore/add/remove/force + +# Fix the spacing between 'case' and the label. Only 'ignore' and 'force' make +# sense here. +sp_case_label = ignore # ignore/add/remove/force + +# (D) Add or remove space around the D '..' operator. +sp_range = ignore # ignore/add/remove/force + +# Add or remove space after ':' in a Java/C++11 range-based 'for', +# as in 'for (Type var : expr)'. +sp_after_for_colon = ignore # ignore/add/remove/force + +# Add or remove space before ':' in a Java/C++11 range-based 'for', +# as in 'for (Type var : expr)'. +sp_before_for_colon = ignore # ignore/add/remove/force + +# (D) Add or remove space between 'extern' and '(' as in 'extern (C)'. +sp_extern_paren = ignore # ignore/add/remove/force + +# Add or remove space after the opening of a C++ comment, +# i.e. '// A' vs. '//A'. +sp_cmt_cpp_start = add # ignore/add/remove/force + +# If true, space is added with sp_cmt_cpp_start will be added after doxygen +# sequences like '///', '///<', '//!' and '//!<'. +sp_cmt_cpp_doxygen = false # true/false + +# If true, space is added with sp_cmt_cpp_start will be added after Qt +# translator or meta-data comments like '//:', '//=', and '//~'. +sp_cmt_cpp_qttr = false # true/false + +# Add or remove space between #else or #endif and a trailing comment. +sp_endif_cmt = add # ignore/add/remove/force + +# Add or remove space after 'new', 'delete' and 'delete[]'. +sp_after_new = ignore # ignore/add/remove/force + +# Add or remove space between 'new' and '(' in 'new()'. +sp_between_new_paren = ignore # ignore/add/remove/force + +# Add or remove space between ')' and type in 'new(foo) BAR'. +sp_after_newop_paren = ignore # ignore/add/remove/force + +# Add or remove space inside parenthesis of the new operator +# as in 'new(foo) BAR'. +sp_inside_newop_paren = ignore # ignore/add/remove/force + +# Add or remove space after the open parenthesis of the new operator, +# as in 'new(foo) BAR'. +# +# Overrides sp_inside_newop_paren. +sp_inside_newop_paren_open = ignore # ignore/add/remove/force + +# Add or remove space before the close parenthesis of the new operator, +# as in 'new(foo) BAR'. +# +# Overrides sp_inside_newop_paren. +sp_inside_newop_paren_close = ignore # ignore/add/remove/force + +# Add or remove space before a trailing or embedded comment. +sp_before_tr_emb_cmt = ignore # ignore/add/remove/force + +# Number of spaces before a trailing or embedded comment. +sp_num_before_tr_emb_cmt = 0 # unsigned number + +# (Java) Add or remove space between an annotation and the open parenthesis. +sp_annotation_paren = ignore # ignore/add/remove/force + +# If true, vbrace tokens are dropped to the previous token and skipped. +sp_skip_vbrace_tokens = false # true/false + +# Add or remove space after 'noexcept'. +sp_after_noexcept = ignore # ignore/add/remove/force + +# Add or remove space after '_'. +sp_vala_after_translation = ignore # ignore/add/remove/force + +# If true, a is inserted after #define. +force_tab_after_define = false # true/false + +# +# Indenting options +# + +# The number of columns to indent per level. Usually 2, 3, 4, or 8. +# +# Default: 8 +indent_columns = 4 # unsigned number + +# The continuation indent. If non-zero, this overrides the indent of '(', '[' +# and '=' continuation indents. Negative values are OK; negative value is +# absolute and not increased for each '(' or '[' level. +# +# For FreeBSD, this is set to 4. +indent_continue = 0 # number + +# The continuation indent, only for class header line(s). If non-zero, this +# overrides the indent of 'class' continuation indents. +indent_continue_class_head = 0 # unsigned number + +# Whether to indent empty lines (i.e. lines which contain only spaces before +# the newline character). +indent_single_newlines = false # true/false + +# The continuation indent for func_*_param if they are true. If non-zero, this +# overrides the indent. +indent_param = 0 # unsigned number + +# How to use tabs when indenting code. +# +# 0: Spaces only +# 1: Indent with tabs to brace level, align with spaces (default) +# 2: Indent and align with tabs, using spaces when not on a tabstop +# +# Default: 1 +indent_with_tabs = 0 # unsigned number + +# Whether to indent comments that are not at a brace level with tabs on a +# tabstop. Requires indent_with_tabs=2. If false, will use spaces. +indent_cmt_with_tabs = false # true/false + +# Whether to indent strings broken by '\' so that they line up. +indent_align_string = false # true/false + +# The number of spaces to indent multi-line XML strings. +# Requires indent_align_string=true. +indent_xml_string = 0 # unsigned number + +# Spaces to indent '{' from level. +indent_brace = 0 # unsigned number + +# Whether braces are indented to the body level. +indent_braces = false # true/false + +# Whether to disable indenting function braces if indent_braces=true. +indent_braces_no_func = false # true/false + +# Whether to disable indenting class braces if indent_braces=true. +indent_braces_no_class = false # true/false + +# Whether to disable indenting struct braces if indent_braces=true. +indent_braces_no_struct = false # true/false + +# Whether to indent based on the size of the brace parent, +# i.e. 'if' => 3 spaces, 'for' => 4 spaces, etc. +indent_brace_parent = false # true/false + +# Whether to indent based on the open parenthesis instead of the open brace +# in '({\n'. +indent_paren_open_brace = false # true/false + +# (C#) Whether to indent the brace of a C# delegate by another level. +indent_cs_delegate_brace = false # true/false + +# (C#) Whether to indent a C# delegate (to handle delegates with no brace) by +# another level. +indent_cs_delegate_body = false # true/false + +# Whether to indent the body of a 'namespace'. +indent_namespace = false # true/false + +# Whether to indent only the first namespace, and not any nested namespaces. +# Requires indent_namespace=true. +indent_namespace_single_indent = false # true/false + +# The number of spaces to indent a namespace block. +# If set to zero, use the value indent_columns +indent_namespace_level = 0 # unsigned number + +# If the body of the namespace is longer than this number, it won't be +# indented. Requires indent_namespace=true. 0 means no limit. +indent_namespace_limit = 0 # unsigned number + +# Whether the 'extern "C"' body is indented. +indent_extern = false # true/false + +# Whether the 'class' body is indented. +indent_class = false # true/false + +# Whether to indent the stuff after a leading base class colon. +indent_class_colon = false # true/false + +# Whether to indent based on a class colon instead of the stuff after the +# colon. Requires indent_class_colon=true. +indent_class_on_colon = false # true/false + +# Whether to indent the stuff after a leading class initializer colon. +indent_constr_colon = false # true/false + +# Virtual indent from the ':' for member initializers. +# +# Default: 2 +indent_ctor_init_leading = 2 # unsigned number + +# Additional indent for constructor initializer list. +# Negative values decrease indent down to the first column. +indent_ctor_init = 0 # number + +# Whether to indent 'if' following 'else' as a new block under the 'else'. +# If false, 'else\nif' is treated as 'else if' for indenting purposes. +indent_else_if = false # true/false + +# Amount to indent variable declarations after a open brace. +# +# <0: Relative +# >=0: Absolute +indent_var_def_blk = 0 # number + +# Whether to indent continued variable declarations instead of aligning. +indent_var_def_cont = false # true/false + +# Whether to indent continued shift expressions ('<<' and '>>') instead of +# aligning. Set align_left_shift=false when enabling this. +indent_shift = false # true/false + +# Whether to force indentation of function definitions to start in column 1. +indent_func_def_force_col1 = false # true/false + +# Whether to indent continued function call parameters one indent level, +# rather than aligning parameters under the open parenthesis. +indent_func_call_param = false # true/false + +# Whether to indent continued function definition parameters one indent level, +# rather than aligning parameters under the open parenthesis. +indent_func_def_param = false # true/false + +# for function definitions, only if indent_func_def_param is false +# Allows to align params when appropriate and indent them when not +# behave as if it was true if paren position is more than this value +# if paren position is more than the option value +#indent_func_def_param_paren_pos_threshold = 0 # unsigned number ### not 0.69 + +# Whether to indent continued function call prototype one indent level, +# rather than aligning parameters under the open parenthesis. +indent_func_proto_param = false # true/false + +# Whether to indent continued function call declaration one indent level, +# rather than aligning parameters under the open parenthesis. +indent_func_class_param = false # true/false + +# Whether to indent continued class variable constructors one indent level, +# rather than aligning parameters under the open parenthesis. +indent_func_ctor_var_param = false # true/false + +# Whether to indent continued template parameter list one indent level, +# rather than aligning parameters under the open parenthesis. +indent_template_param = false # true/false + +# Double the indent for indent_func_xxx_param options. +# Use both values of the options indent_columns and indent_param. +indent_func_param_double = false # true/false + +# Indentation column for standalone 'const' qualifier on a function +# prototype. +indent_func_const = 0 # unsigned number + +# Indentation column for standalone 'throw' qualifier on a function +# prototype. +indent_func_throw = 0 # unsigned number + +# How to indent within a macro followed by a brace on the same line +# This allows reducing the indent in macros that have (for example) +# `do { ... } while (0)` blocks bracketing them. +# +# true: add an indent for the brace on the same line as the macro +# false: do not add an indent for the brace on the same line as the macro +# +# Default: true +#indent_macro_brace = true # true/false ### not 0.69 + +# The number of spaces to indent a continued '->' or '.'. +# Usually set to 0, 1, or indent_columns. +indent_member = 0 # unsigned number + +# Whether lines broken at '.' or '->' should be indented by a single indent. +# The indent_member option will not be effective if this is set to true. +indent_member_single = false # true/false + +# Spaces to indent single line ('//') comments on lines before code. +indent_sing_line_comments = 0 # unsigned number + +# When opening a paren for a control statement (if, for, while, etc), increase +# the indent level by this value. Negative values decrease the indent level. +#indent_sparen_extra = 0 # number ### not 0.69 + +# Whether to indent trailing single line ('//') comments relative to the code +# instead of trying to keep the same absolute column. +indent_relative_single_line_comments = false # true/false + +# Spaces to indent 'case' from 'switch'. Usually 0 or indent_columns. +indent_switch_case = 0 # unsigned number + +# indent 'break' with 'case' from 'switch'. +#indent_switch_break_with_case = false # true/false ### not 0.69 + +# Whether to indent preprocessor statements inside of switch statements. +# +# Default: true +indent_switch_pp = true # true/false + +# Spaces to shift the 'case' line, without affecting any other lines. +# Usually 0. +indent_case_shift = 0 # unsigned number + +# Spaces to indent '{' from 'case'. By default, the brace will appear under +# the 'c' in case. Usually set to 0 or indent_columns. Negative values are OK. +indent_case_brace = 0 # number + +# Whether to indent comments found in first column. +indent_col1_comment = false # true/false + +# Whether to indent multi string literal in first column. +indent_col1_multi_string_literal = false # true/false + +# How to indent goto labels. +# +# >0: Absolute column where 1 is the leftmost column +# <=0: Subtract from brace indent +# +# Default: 1 +indent_label = 1 # number + +# How to indent access specifiers that are followed by a +# colon. +# +# >0: Absolute column where 1 is the leftmost column +# <=0: Subtract from brace indent +# +# Default: 1 +indent_access_spec = 1 # number + +# Whether to indent the code after an access specifier by one level. +# If true, this option forces 'indent_access_spec=0'. +indent_access_spec_body = false # true/false + +# If an open parenthesis is followed by a newline, whether to indent the next +# line so that it lines up after the open parenthesis (not recommended). +indent_paren_nl = false # true/false + +# How to indent a close parenthesis after a newline. +# +# 0: Indent to body level (default) +# 1: Align under the open parenthesis +# 2: Indent to the brace level +indent_paren_close = 0 # unsigned number + +# Whether to indent the open parenthesis of a function definition, +# if the parenthesis is on its own line. +indent_paren_after_func_def = false # true/false + +# Whether to indent the open parenthesis of a function declaration, +# if the parenthesis is on its own line. +indent_paren_after_func_decl = false # true/false + +# Whether to indent the open parenthesis of a function call, +# if the parenthesis is on its own line. +indent_paren_after_func_call = false # true/false + +# Whether to indent a comma when inside a parenthesis. +# If true, aligns under the open parenthesis. +indent_comma_paren = false # true/false + +# Whether to indent a Boolean operator when inside a parenthesis. +# If true, aligns under the open parenthesis. +indent_bool_paren = false # true/false + +# Whether to indent a semicolon when inside a for parenthesis. +# If true, aligns under the open for parenthesis. +indent_semicolon_for_paren = false # true/false + +# Whether to align the first expression to following ones +# if indent_bool_paren=true. +indent_first_bool_expr = false # true/false + +# Whether to align the first expression to following ones +# if indent_semicolon_for_paren=true. +indent_first_for_expr = false # true/false + +# If an open square is followed by a newline, whether to indent the next line +# so that it lines up after the open square (not recommended). +indent_square_nl = false # true/false + +# (ESQL/C) Whether to preserve the relative indent of 'EXEC SQL' bodies. +indent_preserve_sql = false # true/false + +# Whether to align continued statements at the '='. If false or if the '=' is +# followed by a newline, the next line is indent one tab. +# +# Default: true +indent_align_assign = true # true/false + +# If true, the indentation of the chunks after a '=' sequence will be set at +# LHS token indentation column before '='. +#indent_off_after_assign = false # true/false ### not 0.69 + +# Whether to align continued statements at the '('. If false or the '(' is +# followed by a newline, the next line indent is one tab. +# +# Default: true +indent_align_paren = true # true/false + +# (OC) Whether to indent Objective-C code inside message selectors. +#indent_oc_inside_msg_sel = false # true/false ### not 0.69 + +# (OC) Whether to indent Objective-C blocks at brace level instead of usual +# rules. +indent_oc_block = false # true/false + +# (OC) Indent for Objective-C blocks in a message relative to the parameter +# name. +# +# =0: Use indent_oc_block rules +# >0: Use specified number of spaces to indent +indent_oc_block_msg = 0 # unsigned number + +# (OC) Minimum indent for subsequent parameters +indent_oc_msg_colon = 0 # unsigned number + +# (OC) Whether to prioritize aligning with initial colon (and stripping spaces +# from lines, if necessary). +# +# Default: true +indent_oc_msg_prioritize_first_colon = true # true/false + +# (OC) Whether to indent blocks the way that Xcode does by default +# (from the keyword if the parameter is on its own line; otherwise, from the +# previous indentation level). Requires indent_oc_block_msg=true. +indent_oc_block_msg_xcode_style = false # true/false + +# (OC) Whether to indent blocks from where the brace is, relative to a +# message keyword. Requires indent_oc_block_msg=true. +indent_oc_block_msg_from_keyword = false # true/false + +# (OC) Whether to indent blocks from where the brace is, relative to a message +# colon. Requires indent_oc_block_msg=true. +indent_oc_block_msg_from_colon = false # true/false + +# (OC) Whether to indent blocks from where the block caret is. +# Requires indent_oc_block_msg=true. +indent_oc_block_msg_from_caret = false # true/false + +# (OC) Whether to indent blocks from where the brace caret is. +# Requires indent_oc_block_msg=true. +indent_oc_block_msg_from_brace = false # true/false + +# When indenting after virtual brace open and newline add further spaces to +# reach this minimum indent. +indent_min_vbrace_open = 0 # unsigned number + +# Whether to add further spaces after regular indent to reach next tabstop +# when identing after virtual brace open and newline. +indent_vbrace_open_on_tabstop = false # true/false + +# How to indent after a brace followed by another token (not a newline). +# true: indent all contained lines to match the token +# false: indent all contained lines to match the brace +# +# Default: true +indent_token_after_brace = true # true/false + +# Whether to indent the body of a C++11 lambda. +indent_cpp_lambda_body = false # true/false + +# How to indent compound literals that are being returned. +# true: add both the indent from return & the compound literal open brace (ie: +# 2 indent levels) +# false: only indent 1 level, don't add the indent for the open brace, only add +# the indent for the return. +# +# Default: true +#indent_compound_literal_return = true # true/false ### not 0.69 + +# (C#) Whether to indent a 'using' block if no braces are used. +# +# Default: true +indent_using_block = true # true/false + +# How to indent the continuation of ternary operator. +# +# 0: Off (default) +# 1: When the `if_false` is a continuation, indent it under `if_false` +# 2: When the `:` is a continuation, indent it under `?` +indent_ternary_operator = 0 # unsigned number + +# Whether to indent the statments inside ternary operator. +#indent_inside_ternary_operator = false # true/false ### not 0.69 + +# If true, the indentation of the chunks after a `return` sequence will be set at return indentation column. +#indent_off_after_return = false # true/false ### not 0.69 + +# If true, the indentation of the chunks after a `return new` sequence will be set at return indentation column. +indent_off_after_return_new = false # true/false + +# If true, the tokens after return are indented with regular single indentation. By default (false) the indentation is after the return token. +indent_single_after_return = false # true/false + +# Whether to ignore indent and alignment for 'asm' blocks (i.e. assume they +# have their own indentation). +indent_ignore_asm_block = false # true/false + +# +# Newline adding and removing options +# + +# Whether to collapse empty blocks between '{' and '}'. +nl_collapse_empty_body = false # true/false + +# Don't split one-line braced assignments, as in 'foo_t f = { 1, 2 };'. +nl_assign_leave_one_liners = false # true/false + +# Don't split one-line braced statements inside a 'class xx { }' body. +nl_class_leave_one_liners = false # true/false + +# Don't split one-line enums, as in 'enum foo { BAR = 15 };' +nl_enum_leave_one_liners = false # true/false + +# Don't split one-line get or set functions. +nl_getset_leave_one_liners = false # true/false + +# (C#) Don't split one-line property get or set functions. +nl_cs_property_leave_one_liners = false # true/false + +# Don't split one-line function definitions, as in 'int foo() { return 0; }'. +# might modify nl_func_type_name +nl_func_leave_one_liners = false # true/false + +# Don't split one-line C++11 lambdas, as in '[]() { return 0; }'. +nl_cpp_lambda_leave_one_liners = false # true/false + +# Don't split one-line if/else statements, as in 'if(...) b++;'. +nl_if_leave_one_liners = false # true/false + +# Don't split one-line while statements, as in 'while(...) b++;'. +nl_while_leave_one_liners = false # true/false + +# Don't split one-line for statements, as in 'for(...) b++;'. +nl_for_leave_one_liners = false # true/false + +# (OC) Don't split one-line Objective-C messages. +nl_oc_msg_leave_one_liner = false # true/false + +# (OC) Add or remove newline between method declaration and '{'. +nl_oc_mdef_brace = ignore # ignore/add/remove/force + +# (OC) Add or remove newline between Objective-C block signature and '{'. +nl_oc_block_brace = ignore # ignore/add/remove/force + +# (OC) Add or remove blank line before '@interface' statement. +#nl_oc_before_interface = ignore # ignore/add/remove/force ### not 0.69 + +# (OC) Add or remove blank line before '@implementation' statement. +#nl_oc_before_implementation = ignore # ignore/add/remove/force ### not 0.69 + +# (OC) Add or remove blank line before '@end' statement. +#nl_oc_before_end = ignore # ignore/add/remove/force ### not 0.69 + +# (OC) Add or remove newline between '@interface' and '{'. +nl_oc_interface_brace = ignore # ignore/add/remove/force + +# (OC) Add or remove newline between '@implementation' and '{'. +nl_oc_implementation_brace = ignore # ignore/add/remove/force + +# Add or remove newlines at the start of the file. +nl_start_of_file = remove # ignore/add/remove/force + +# The minimum number of newlines at the start of the file (only used if +# nl_start_of_file is 'add' or 'force'). +nl_start_of_file_min = 0 # unsigned number + +# Add or remove newline at the end of the file. +nl_end_of_file = ignore # ignore/add/remove/force + +# The minimum number of newlines at the end of the file (only used if +# nl_end_of_file is 'add' or 'force'). +nl_end_of_file_min = 0 # unsigned number + +# Add or remove newline between '=' and '{'. +nl_assign_brace = ignore # ignore/add/remove/force + +# (D) Add or remove newline between '=' and '['. +nl_assign_square = ignore # ignore/add/remove/force + +# Add or remove newline between '[]' and '{'. +nl_tsquare_brace = ignore # ignore/add/remove/force + +# (D) Add or remove newline after '= ['. Will also affect the newline before +# the ']'. +nl_after_square_assign = ignore # ignore/add/remove/force + +# Add or remove newline between a function call's ')' and '{', as in +# 'list_for_each(item, &list) { }'. +nl_fcall_brace = ignore # ignore/add/remove/force + +# Add or remove newline between 'enum' and '{'. +nl_enum_brace = remove # ignore/add/remove/force + +# Add or remove newline between 'enum' and 'class'. +nl_enum_class = ignore # ignore/add/remove/force + +# Add or remove newline between 'enum class' and the identifier. +nl_enum_class_identifier = ignore # ignore/add/remove/force + +# Add or remove newline between 'enum class' type and ':'. +nl_enum_identifier_colon = ignore # ignore/add/remove/force + +# Add or remove newline between 'enum class identifier :' and type. +nl_enum_colon_type = ignore # ignore/add/remove/force + +# Add or remove newline between 'struct and '{'. +nl_struct_brace = remove # ignore/add/remove/force + +# Add or remove newline between 'union' and '{'. +nl_union_brace = remove # ignore/add/remove/force + +# Add or remove newline between 'if' and '{'. +nl_if_brace = remove # ignore/add/remove/force + +# Add or remove newline between '}' and 'else'. +nl_brace_else = remove # ignore/add/remove/force + +# Add or remove newline between 'else if' and '{'. If set to ignore, +# nl_if_brace is used instead. +nl_elseif_brace = remove # ignore/add/remove/force + +# Add or remove newline between 'else' and '{'. +nl_else_brace = remove # ignore/add/remove/force + +# Add or remove newline between 'else' and 'if'. +nl_else_if = remove # ignore/add/remove/force + +# Add or remove newline before '{' opening brace +#nl_before_opening_brace_func_class_def = remove # ignore/add/remove/force ### not 0.69 + +# Add or remove newline before 'if'/'else if' closing parenthesis. +nl_before_if_closing_paren = remove # ignore/add/remove/force + +# Add or remove newline between '}' and 'finally'. +nl_brace_finally = remove # ignore/add/remove/force + +# Add or remove newline between 'finally' and '{'. +nl_finally_brace = remove # ignore/add/remove/force + +# Add or remove newline between 'try' and '{'. +nl_try_brace = remove # ignore/add/remove/force + +# Add or remove newline between get/set and '{'. +nl_getset_brace = remove # ignore/add/remove/force + +# Add or remove newline between 'for' and '{'. +nl_for_brace = remove # ignore/add/remove/force + +# Add or remove newline before the '{' of a 'catch' statement, as in +# 'catch (decl) {'. +nl_catch_brace = remove # ignore/add/remove/force + +# (OC) Add or remove newline before the '{' of a '@catch' statement, as in +# '@catch (decl) {'. If set to ignore, nl_catch_brace is used. +nl_oc_catch_brace = ignore # ignore/add/remove/force + +# Add or remove newline between '}' and 'catch'. +nl_brace_catch = remove # ignore/add/remove/force + +# (OC) Add or remove newline between '}' and '@catch'. If set to ignore, +# nl_brace_catch is used. +nl_oc_brace_catch = ignore # ignore/add/remove/force + +# Add or remove newline between '}' and ']'. +nl_brace_square = ignore # ignore/add/remove/force + +# Add or remove newline between '}' and ')' in a function invocation. +nl_brace_fparen = ignore # ignore/add/remove/force + +# Add or remove newline between 'while' and '{'. +nl_while_brace = remove # ignore/add/remove/force + +# (D) Add or remove newline between 'scope (x)' and '{'. +nl_scope_brace = ignore # ignore/add/remove/force + +# (D) Add or remove newline between 'unittest' and '{'. +nl_unittest_brace = ignore # ignore/add/remove/force + +# (D) Add or remove newline between 'version (x)' and '{'. +nl_version_brace = ignore # ignore/add/remove/force + +# (C#) Add or remove newline between 'using' and '{'. +nl_using_brace = ignore # ignore/add/remove/force + +# Add or remove newline between two open or close braces. Due to general +# newline/brace handling, REMOVE may not work. +nl_brace_brace = add # ignore/add/remove/force + +# Add or remove newline between 'do' and '{'. +nl_do_brace = remove # ignore/add/remove/force + +# Add or remove newline between '}' and 'while' of 'do' statement. +nl_brace_while = remove # ignore/add/remove/force + +# Add or remove newline between 'switch' and '{'. +nl_switch_brace = remove # ignore/add/remove/force + +# Add or remove newline between 'synchronized' and '{'. +nl_synchronized_brace = remove # ignore/add/remove/force + +# Add a newline between ')' and '{' if the ')' is on a different line than the +# if/for/etc. +# +# Overrides nl_for_brace, nl_if_brace, nl_switch_brace, nl_while_switch and +# nl_catch_brace. +nl_multi_line_cond = false # true/false + +# Add a newline after '(' if an if/for/while/switch condition spans multiple +# lines +#nl_multi_line_sparen_open = ignore # ignore/add/remove/force ### not 0.69 + +# Add a newline before ')' if an if/for/while/switch condition spans multiple +# lines. Overrides nl_before_if_closing_paren if both are specified. +#nl_multi_line_sparen_close = ignore # ignore/add/remove/force ### not 0.69 + +# Force a newline in a define after the macro name for multi-line defines. +nl_multi_line_define = false # true/false + +# Whether to add a newline before 'case', and a blank line before a 'case' +# statement that follows a ';' or '}'. +nl_before_case = false # true/false + +# Whether to add a newline after a 'case' statement. +nl_after_case = false # true/false + +# Add or remove newline between a case ':' and '{'. +# +# Overrides nl_after_case. +nl_case_colon_brace = ignore # ignore/add/remove/force + +# Add or remove newline between ')' and 'throw'. +nl_before_throw = ignore # ignore/add/remove/force + +# Add or remove newline between 'namespace' and '{'. +nl_namespace_brace = ignore # ignore/add/remove/force + +# Add or remove newline after 'template<...>' of a template class. +nl_template_class = ignore # ignore/add/remove/force + +# Add or remove newline after 'template<...>' of a template class declaration. +# +# Overrides nl_template_class. +#nl_template_class_decl = ignore # ignore/add/remove/force ### not 0.69 + +# Add or remove newline after 'template<>' of a specialized class declaration. +# +# Overrides nl_template_class_decl. +#nl_template_class_decl_special = ignore # ignore/add/remove/force ### not 0.69 + +# Add or remove newline after 'template<...>' of a template class definition. +# +# Overrides nl_template_class. +#nl_template_class_def = ignore # ignore/add/remove/force ### not 0.69 + +# Add or remove newline after 'template<>' of a specialized class definition. +# +# Overrides nl_template_class_def. +#nl_template_class_def_special = ignore # ignore/add/remove/force ### not 0.69 + +# Add or remove newline after 'template<...>' of a template function. +#nl_template_func = ignore # ignore/add/remove/force ### not 0.69 + +# Add or remove newline after 'template<...>' of a template function +# declaration. +# +# Overrides nl_template_func. +#nl_template_func_decl = ignore # ignore/add/remove/force ### not 0.69 + +# Add or remove newline after 'template<>' of a specialized function +# declaration. +# +# Overrides nl_template_func_decl. +#nl_template_func_decl_special = ignore # ignore/add/remove/force ### not 0.69 + +# Add or remove newline after 'template<...>' of a template function +# definition. +# +# Overrides nl_template_func. +#nl_template_func_def = ignore # ignore/add/remove/force ### not 0.69 + +# Add or remove newline after 'template<>' of a specialized function +# definition. +# +# Overrides nl_template_func_def. +#nl_template_func_def_special = ignore # ignore/add/remove/force ### not 0.69 + +# Add or remove newline after 'template<...>' of a template variable. +#nl_template_var = ignore # ignore/add/remove/force ### not 0.69 + +# Add or remove newline between 'template<...>' and 'using' of a templated +# type alias. +#nl_template_using = ignore # ignore/add/remove/force ### not 0.69 + +# Add or remove newline between 'class' and '{'. +nl_class_brace = ignore # ignore/add/remove/force + +# Add or remove newline before or after (depending on pos_class_comma, +# may not be IGNORE) each',' in the base class list. +nl_class_init_args = ignore # ignore/add/remove/force + +# Add or remove newline after each ',' in the constructor member +# initialization. Related to nl_constr_colon, pos_constr_colon and +# pos_constr_comma. +nl_constr_init_args = ignore # ignore/add/remove/force + +# Add or remove newline before first element, after comma, and after last +# element, in 'enum'. +nl_enum_own_lines = ignore # ignore/add/remove/force + +# Add or remove newline between return type and function name in a function +# definition. +# might be modified by nl_func_leave_one_liners +nl_func_type_name = ignore # ignore/add/remove/force + +# Add or remove newline between return type and function name inside a class +# definition. If set to ignore, nl_func_type_name or nl_func_proto_type_name +# is used instead. +nl_func_type_name_class = ignore # ignore/add/remove/force + +# Add or remove newline between class specification and '::' +# in 'void A::f() { }'. Only appears in separate member implementation (does +# not appear with in-line implementation). +nl_func_class_scope = ignore # ignore/add/remove/force + +# Add or remove newline between function scope and name, as in +# 'void A :: f() { }'. +nl_func_scope_name = ignore # ignore/add/remove/force + +# Add or remove newline between return type and function name in a prototype. +nl_func_proto_type_name = ignore # ignore/add/remove/force + +# Add or remove newline between a function name and the opening '(' in the +# declaration. +nl_func_paren = remove # ignore/add/remove/force + +# Overrides nl_func_paren for functions with no parameters. +nl_func_paren_empty = ignore # ignore/add/remove/force + +# Add or remove newline between a function name and the opening '(' in the +# definition. +nl_func_def_paren = remove # ignore/add/remove/force + +# Overrides nl_func_def_paren for functions with no parameters. +nl_func_def_paren_empty = ignore # ignore/add/remove/force + +# Add or remove newline between a function name and the opening '(' in the +# call. +nl_func_call_paren = ignore # ignore/add/remove/force + +# Overrides nl_func_call_paren for functions with no parameters. +nl_func_call_paren_empty = ignore # ignore/add/remove/force + +# Add or remove newline after '(' in a function declaration. +nl_func_decl_start = remove # ignore/add/remove/force + +# Add or remove newline after '(' in a function definition. +nl_func_def_start = remove # ignore/add/remove/force + +# Overrides nl_func_decl_start when there is only one parameter. +nl_func_decl_start_single = ignore # ignore/add/remove/force + +# Overrides nl_func_def_start when there is only one parameter. +nl_func_def_start_single = ignore # ignore/add/remove/force + +# Whether to add a newline after '(' in a function declaration if '(' and ')' +# are in different lines. If false, nl_func_decl_start is used instead. +nl_func_decl_start_multi_line = false # true/false + +# Whether to add a newline after '(' in a function definition if '(' and ')' +# are in different lines. If false, nl_func_def_start is used instead. +nl_func_def_start_multi_line = false # true/false + +# Add or remove newline after each ',' in a function declaration. +nl_func_decl_args = ignore # ignore/add/remove/force + +# Add or remove newline after each ',' in a function definition. +nl_func_def_args = ignore # ignore/add/remove/force + +# Add or remove newline after each ',' in a function call. +#nl_func_call_args = ignore # ignore/add/remove/force ### not 0.69 + +# Whether to add a newline after each ',' in a function declaration if '(' +# and ')' are in different lines. If false, nl_func_decl_args is used instead. +nl_func_decl_args_multi_line = false # true/false + +# Whether to add a newline after each ',' in a function definition if '(' +# and ')' are in different lines. If false, nl_func_def_args is used instead. +nl_func_def_args_multi_line = false # true/false + +# Add or remove newline before the ')' in a function declaration. +nl_func_decl_end = remove # ignore/add/remove/force + +# Add or remove newline before the ')' in a function definition. +nl_func_def_end = remove # ignore/add/remove/force + +# Overrides nl_func_decl_end when there is only one parameter. +nl_func_decl_end_single = ignore # ignore/add/remove/force + +# Overrides nl_func_def_end when there is only one parameter. +nl_func_def_end_single = ignore # ignore/add/remove/force + +# Whether to add a newline before ')' in a function declaration if '(' and ')' +# are in different lines. If false, nl_func_decl_end is used instead. +nl_func_decl_end_multi_line = false # true/false + +# Whether to add a newline before ')' in a function definition if '(' and ')' +# are in different lines. If false, nl_func_def_end is used instead. +nl_func_def_end_multi_line = false # true/false + +# Add or remove newline between '()' in a function declaration. +nl_func_decl_empty = remove # ignore/add/remove/force + +# Add or remove newline between '()' in a function definition. +nl_func_def_empty = remove # ignore/add/remove/force + +# Add or remove newline between '()' in a function call. +nl_func_call_empty = remove # ignore/add/remove/force + +# Whether to add a newline after '(' in a function call, +# has preference over nl_func_call_start_multi_line. +nl_func_call_start = ignore # ignore/add/remove/force + +# Whether to add a newline before ')' in a function call. +#nl_func_call_end = ignore # ignore/add/remove/force ### not 0.69 + +# Whether to add a newline after '(' in a function call if '(' and ')' are in +# different lines. +nl_func_call_start_multi_line = false # true/false + +# Whether to add a newline after each ',' in a function call if '(' and ')' +# are in different lines. +nl_func_call_args_multi_line = false # true/false + +# Whether to add a newline before ')' in a function call if '(' and ')' are in +# different lines. +nl_func_call_end_multi_line = false # true/false + +# Whether to respect nl_func_call_XXX option incase of closure args. +#nl_func_call_args_multi_line_ignore_closures = false # true/false ### not 0.69 + +# Whether to add a newline after '<' of a template parameter list. +#nl_template_start = false # true/false ### not 0.69 + +# Whether to add a newline after each ',' in a template parameter list. +#nl_template_args = false # true/false ### not 0.69 + +# Whether to add a newline before '>' of a template parameter list. +#nl_template_end = false # true/false ### not 0.69 + +# (OC) Whether to put each Objective-C message parameter on a separate line. +# See nl_oc_msg_leave_one_liner. +nl_oc_msg_args = false # true/false + +# Add or remove newline between function signature and '{'. +nl_fdef_brace = ignore # ignore/add/remove/force + +# Add or remove newline between function signature and '{', +# if signature ends with ')'. Overrides nl_fdef_brace. +nl_fdef_brace_cond = ignore # ignore/add/remove/force + +# Add or remove newline between C++11 lambda signature and '{'. +nl_cpp_ldef_brace = ignore # ignore/add/remove/force + +# Add or remove newline between 'return' and the return expression. +nl_return_expr = ignore # ignore/add/remove/force + +# Whether to add a newline after semicolons, except in 'for' statements. +nl_after_semicolon = false # true/false + +# (Java) Add or remove newline between the ')' and '{{' of the double brace +# initializer. +nl_paren_dbrace_open = ignore # ignore/add/remove/force + +# Whether to add a newline after the type in an unnamed temporary +# direct-list-initialization. +nl_type_brace_init_lst = ignore # ignore/add/remove/force + +# Whether to add a newline after the open brace in an unnamed temporary +# direct-list-initialization. +nl_type_brace_init_lst_open = ignore # ignore/add/remove/force + +# Whether to add a newline before the close brace in an unnamed temporary +# direct-list-initialization. +nl_type_brace_init_lst_close = ignore # ignore/add/remove/force + +# Whether to add a newline after '{'. This also adds a newline before the +# matching '}'. +nl_after_brace_open = false # true/false + +# Whether to add a newline between the open brace and a trailing single-line +# comment. Requires nl_after_brace_open=true. +nl_after_brace_open_cmt = false # true/false + +# Whether to add a newline after a virtual brace open with a non-empty body. +# These occur in un-braced if/while/do/for statement bodies. +nl_after_vbrace_open = false # true/false + +# Whether to add a newline after a virtual brace open with an empty body. +# These occur in un-braced if/while/do/for statement bodies. +nl_after_vbrace_open_empty = false # true/false + +# Whether to add a newline after '}'. Does not apply if followed by a +# necessary ';'. +nl_after_brace_close = false # true/false + +# Whether to add a newline after a virtual brace close, +# as in 'if (foo) a++; return;'. +nl_after_vbrace_close = false # true/false + +# Add or remove newline between the close brace and identifier, +# as in 'struct { int a; } b;'. Affects enumerations, unions and +# structures. If set to ignore, uses nl_after_brace_close. +nl_brace_struct_var = ignore # ignore/add/remove/force + +# Whether to alter newlines in '#define' macros. +nl_define_macro = false # true/false + +# Whether to alter newlines between consecutive parenthesis closes. The number +# of closing parentheses in a line will depend on respective open parenthesis +# lines. +nl_squeeze_paren_close = false # true/false + +# Whether to remove blanks after '#ifxx' and '#elxx', or before '#elxx' and +# '#endif'. Does not affect top-level #ifdefs. +nl_squeeze_ifdef = false # true/false + +# Makes the nl_squeeze_ifdef option affect the top-level #ifdefs as well. +nl_squeeze_ifdef_top_level = false # true/false + +# Add or remove blank line before 'if'. +nl_before_if = add # ignore/add/remove/force + +# Add or remove blank line after 'if' statement. Add/Force work only if the +# next token is not a closing brace. +nl_after_if = add # ignore/add/remove/force + +# Add or remove blank line before 'for'. +nl_before_for = add # ignore/add/remove/force + +# Add or remove blank line after 'for' statement. +nl_after_for = add # ignore/add/remove/force + +# Add or remove blank line before 'while'. +nl_before_while = add # ignore/add/remove/force + +# Add or remove blank line after 'while' statement. +nl_after_while = add # ignore/add/remove/force + +# Add or remove blank line before 'switch'. +nl_before_switch = add # ignore/add/remove/force + +# Add or remove blank line after 'switch' statement. +nl_after_switch = add # ignore/add/remove/force + +# Add or remove blank line before 'synchronized'. +nl_before_synchronized = add # ignore/add/remove/force + +# Add or remove blank line after 'synchronized' statement. +nl_after_synchronized = add # ignore/add/remove/force + +# Add or remove blank line before 'do'. +nl_before_do = add # ignore/add/remove/force + +# Add or remove blank line after 'do/while' statement. +nl_after_do = add # ignore/add/remove/force + +# Whether to put a blank line before 'return' statements, unless after an open +# brace. +nl_before_return = false # true/false + +# Whether to put a blank line after 'return' statements, unless followed by a +# close brace. +nl_after_return = false # true/false + +# Whether to put a blank line before a member '.' or '->' operators. +#nl_before_member = ignore # ignore/add/remove/force ### not 0.69 + +# (Java) Whether to put a blank line after a member '.' or '->' operators. +#nl_after_member = ignore # ignore/add/remove/force ### not 0.69 + +# Whether to double-space commented-entries in 'struct'/'union'/'enum'. +nl_ds_struct_enum_cmt = false # true/false + +# Whether to force a newline before '}' of a 'struct'/'union'/'enum'. +# (Lower priority than eat_blanks_before_close_brace.) +nl_ds_struct_enum_close_brace = false # true/false + +# Add or remove newline before or after (depending on pos_class_colon) a class +# colon, as in 'class Foo : public Bar'. +nl_class_colon = ignore # ignore/add/remove/force + +# Add or remove newline around a class constructor colon. The exact position +# depends on nl_constr_init_args, pos_constr_colon and pos_constr_comma. +nl_constr_colon = ignore # ignore/add/remove/force + +# Whether to collapse a two-line namespace, like 'namespace foo\n{ decl; }' +# into a single line. If true, prevents other brace newline rules from turning +# such code into four lines. +nl_namespace_two_to_one_liner = false # true/false + +# Whether to remove a newline in simple unbraced if statements, turning them +# into one-liners, as in 'if(b)\n i++;' => 'if(b) i++;'. +nl_create_if_one_liner = false # true/false + +# Whether to remove a newline in simple unbraced for statements, turning them +# into one-liners, as in 'for (...)\n stmt;' => 'for (...) stmt;'. +nl_create_for_one_liner = false # true/false + +# Whether to remove a newline in simple unbraced while statements, turning +# them into one-liners, as in 'while (expr)\n stmt;' => 'while (expr) stmt;'. +nl_create_while_one_liner = false # true/false + +# Whether to collapse a function definition whose body (not counting braces) +# is only one line so that the entire definition (prototype, braces, body) is +# a single line. +nl_create_func_def_one_liner = false # true/false + +# Whether to collapse a function definition whose body (not counting braces) +# is only one line so that the entire definition (prototype, braces, body) is +# a single line. +#nl_create_list_one_liner = false # true/false ### not 0.69 + +# Whether to split one-line simple unbraced if statements into two lines by +# adding a newline, as in 'if(b) i++;'. +nl_split_if_one_liner = false # true/false + +# Whether to split one-line simple unbraced for statements into two lines by +# adding a newline, as in 'for (...) stmt;'. +nl_split_for_one_liner = false # true/false + +# Whether to split one-line simple unbraced while statements into two lines by +# adding a newline, as in 'while (expr) stmt;'. +nl_split_while_one_liner = false # true/false + +# +# Blank line options +# + +# The maximum number of consecutive newlines (3 = 2 blank lines). +nl_max = 0 # unsigned number + +# The maximum number of consecutive newlines in a function. +nl_max_blank_in_func = 0 # unsigned number + +# The number of newlines before a function prototype. +nl_before_func_body_proto = 0 # unsigned number + +# The number of newlines before a multi-line function definition. +nl_before_func_body_def = 0 # unsigned number + +# The number of newlines before a class constructor/destructor prototype. +nl_before_func_class_proto = 0 # unsigned number + +# The number of newlines before a class constructor/destructor definition. +nl_before_func_class_def = 0 # unsigned number + +# The number of newlines after a function prototype. +nl_after_func_proto = 0 # unsigned number + +# The number of newlines after a function prototype, if not followed by +# another function prototype. +nl_after_func_proto_group = 0 # unsigned number + +# The number of newlines after a class constructor/destructor prototype. +nl_after_func_class_proto = 0 # unsigned number + +# The number of newlines after a class constructor/destructor prototype, +# if not followed by another constructor/destructor prototype. +nl_after_func_class_proto_group = 0 # unsigned number + +# Whether one-line method definitions inside a class body should be treated +# as if they were prototypes for the purposes of adding newlines. +# +# Requires nl_class_leave_one_liners=true. Overrides nl_before_func_body_def +# and nl_before_func_class_def for one-liners. +nl_class_leave_one_liner_groups = false # true/false + +# The number of newlines after '}' of a multi-line function body. +nl_after_func_body = 0 # unsigned number + +# The number of newlines after '}' of a multi-line function body in a class +# declaration. Also affects class constructors/destructors. +# +# Overrides nl_after_func_body. +nl_after_func_body_class = 0 # unsigned number + +# The number of newlines after '}' of a single line function body. Also +# affects class constructors/destructors. +# +# Overrides nl_after_func_body and nl_after_func_body_class. +nl_after_func_body_one_liner = 0 # unsigned number + +# The number of blank lines after a block of variable definitions at the top +# of a function body. +# +# 0: No change (default). +nl_func_var_def_blk = 0 # unsigned number + +# The number of newlines before a block of typedefs. If nl_after_access_spec +# is non-zero, that option takes precedence. +# +# 0: No change (default). +nl_typedef_blk_start = 0 # unsigned number + +# The number of newlines after a block of typedefs. +# +# 0: No change (default). +nl_typedef_blk_end = 0 # unsigned number + +# The maximum number of consecutive newlines within a block of typedefs. +# +# 0: No change (default). +nl_typedef_blk_in = 0 # unsigned number + +# The number of newlines before a block of variable definitions not at the top +# of a function body. If nl_after_access_spec is non-zero, that option takes +# precedence. +# +# 0: No change (default). +nl_var_def_blk_start = 0 # unsigned number + +# The number of newlines after a block of variable definitions not at the top +# of a function body. +# +# 0: No change (default). +nl_var_def_blk_end = 0 # unsigned number + +# The maximum number of consecutive newlines within a block of variable +# definitions. +# +# 0: No change (default). +nl_var_def_blk_in = 0 # unsigned number + +# The minimum number of newlines before a multi-line comment. +# Doesn't apply if after a brace open or another multi-line comment. +nl_before_block_comment = 0 # unsigned number + +# The minimum number of newlines before a single-line C comment. +# Doesn't apply if after a brace open or other single-line C comments. +nl_before_c_comment = 0 # unsigned number + +# The minimum number of newlines before a CPP comment. +# Doesn't apply if after a brace open or other CPP comments. +nl_before_cpp_comment = 0 # unsigned number + +# Whether to force a newline after a multi-line comment. +nl_after_multiline_comment = false # true/false + +# Whether to force a newline after a label's colon. +nl_after_label_colon = false # true/false + +# The number of newlines after '}' or ';' of a struct/enum/union definition. +nl_after_struct = 0 # unsigned number + +# The number of newlines before a class definition. +nl_before_class = 0 # unsigned number + +# The number of newlines after '}' or ';' of a class definition. +nl_after_class = 0 # unsigned number + +# The number of newlines before a namespace. +#nl_before_namespace = 0 # unsigned number ### not 0.69 + +# The number of newlines after '{' of a namespace. This also adds newlines +# before the matching '}'. +# +# 0: Apply eat_blanks_after_open_brace or eat_blanks_before_close_brace if +# applicable, otherwise no change. +# +# Overrides eat_blanks_after_open_brace and eat_blanks_before_close_brace. +nl_inside_namespace = 0 # unsigned number + +# The number of newlines after '}' of a namespace. +#nl_after_namespace = 0 # unsigned number ### not 0.69 + +# The number of newlines before an access specifier label. This also includes +# the Qt-specific 'signals:' and 'slots:'. Will not change the newline count +# if after a brace open. +# +# 0: No change (default). +nl_before_access_spec = 0 # unsigned number + +# The number of newlines after an access specifier label. This also includes +# the Qt-specific 'signals:' and 'slots:'. Will not change the newline count +# if after a brace open. +# +# 0: No change (default). +# +# Overrides nl_typedef_blk_start and nl_var_def_blk_start. +nl_after_access_spec = 0 # unsigned number + +# The number of newlines between a function definition and the function +# comment, as in '// comment\n void foo() {...}'. +# +# 0: No change (default). +nl_comment_func_def = 0 # unsigned number + +# The number of newlines after a try-catch-finally block that isn't followed +# by a brace close. +# +# 0: No change (default). +nl_after_try_catch_finally = 0 # unsigned number + +# (C#) The number of newlines before and after a property, indexer or event +# declaration. +# +# 0: No change (default). +nl_around_cs_property = 0 # unsigned number + +# (C#) The number of newlines between the get/set/add/remove handlers. +# +# 0: No change (default). +nl_between_get_set = 0 # unsigned number + +# (C#) Add or remove newline between property and the '{'. +nl_property_brace = ignore # ignore/add/remove/force + +# Whether to remove blank lines after '{'. +eat_blanks_after_open_brace = false # true/false + +# Whether to remove blank lines before '}'. +eat_blanks_before_close_brace = false # true/false + +# How aggressively to remove extra newlines not in preprocessor. +# +# 0: No change (default) +# 1: Remove most newlines not handled by other config +# 2: Remove all newlines and reformat completely by config +nl_remove_extra_newlines = 0 # unsigned number + +# (Java) Add or remove newline after an annotation statement. Only affects +# annotations that are after a newline. +nl_after_annotation = ignore # ignore/add/remove/force + +# (Java) Add or remove newline between two annotations. +nl_between_annotation = ignore # ignore/add/remove/force + +# The number of newlines before a whole-file #ifdef. +# +# 0: No change (default). +#nl_before_whole_file_ifdef = 0 # unsigned number ### not 0.69 + +# The number of newlines after a whole-file #ifdef. +# +# 0: No change (default). +#nl_after_whole_file_ifdef = 0 # unsigned number ### not 0.69 + +# The number of newlines before a whole-file #endif. +# +# 0: No change (default). +#nl_before_whole_file_endif = 0 # unsigned number ### not 0.69 + +# The number of newlines after a whole-file #endif. +# +# 0: No change (default). +#nl_after_whole_file_endif = 0 # unsigned number ### not 0.69 + +# +# Positioning options +# + +# The position of arithmetic operators in wrapped expressions. +pos_arith = ignore # ignore/break/force/lead/trail/join/lead_break/lead_force/trail_break/trail_force + +# The position of assignment in wrapped expressions. Do not affect '=' +# followed by '{'. +pos_assign = ignore # ignore/break/force/lead/trail/join/lead_break/lead_force/trail_break/trail_force + +# The position of Boolean operators in wrapped expressions. +pos_bool = ignore # ignore/break/force/lead/trail/join/lead_break/lead_force/trail_break/trail_force + +# The position of comparison operators in wrapped expressions. +pos_compare = ignore # ignore/break/force/lead/trail/join/lead_break/lead_force/trail_break/trail_force + +# The position of conditional operators, as in the '?' and ':' of +# 'expr ? stmt : stmt', in wrapped expressions. +pos_conditional = ignore # ignore/break/force/lead/trail/join/lead_break/lead_force/trail_break/trail_force + +# The position of the comma in wrapped expressions. +pos_comma = ignore # ignore/break/force/lead/trail/join/lead_break/lead_force/trail_break/trail_force + +# The position of the comma in enum entries. +pos_enum_comma = ignore # ignore/break/force/lead/trail/join/lead_break/lead_force/trail_break/trail_force + +# The position of the comma in the base class list if there is more than one +# line. Affects nl_class_init_args. +pos_class_comma = ignore # ignore/break/force/lead/trail/join/lead_break/lead_force/trail_break/trail_force + +# The position of the comma in the constructor initialization list. +# Related to nl_constr_colon, nl_constr_init_args and pos_constr_colon. +pos_constr_comma = ignore # ignore/break/force/lead/trail/join/lead_break/lead_force/trail_break/trail_force + +# The position of trailing/leading class colon, between class and base class +# list. Affects nl_class_colon. +pos_class_colon = ignore # ignore/break/force/lead/trail/join/lead_break/lead_force/trail_break/trail_force + +# The position of colons between constructor and member initialization. +# Related to nl_constr_colon, nl_constr_init_args and pos_constr_comma. +pos_constr_colon = ignore # ignore/break/force/lead/trail/join/lead_break/lead_force/trail_break/trail_force + +# +# Line splitting options +# + +# Try to limit code width to N columns. +code_width = 0 # unsigned number + +# Whether to fully split long 'for' statements at semi-colons. +ls_for_split_full = false # true/false + +# Whether to fully split long function prototypes/calls at commas. +# The option ls_code_width has priority over the option ls_func_split_full. +ls_func_split_full = false # true/false + +# Whether to split lines as close to code_width as possible and ignore some +# groupings. +# The option ls_code_width has priority over the option ls_func_split_full. +ls_code_width = false # true/false + +# +# Code alignment options (not left column spaces/tabs) +# + +# Whether to keep non-indenting tabs. +align_keep_tabs = false # true/false + +# Whether to use tabs for aligning. +align_with_tabs = false # true/false + +# Whether to bump out to the next tab when aligning. +align_on_tabstop = false # true/false + +# Whether to right-align numbers. +align_number_right = false # true/false + +# Whether to keep whitespace not required for alignment. +align_keep_extra_space = false # true/false + +# Whether to align variable definitions in prototypes and functions. +align_func_params = false # true/false + +# The span for aligning parameter definitions in function on parameter name. +# +# 0: Don't align (default). +align_func_params_span = 0 # unsigned number + +# The threshold for aligning function parameter definitions. +# Use a negative number for absolute thresholds. +# +# 0: No limit (default). +align_func_params_thresh = 0 # number + +# The gap for aligning function parameter definitions. +align_func_params_gap = 0 # unsigned number + +# The span for aligning constructor value. +# +# 0: Don't align (default). +align_constr_value_span = 0 # unsigned number + +# The threshold for aligning constructor value. +# Use a negative number for absolute thresholds. +# +# 0: No limit (default). +align_constr_value_thresh = 0 # number + +# The gap for aligning constructor value. +align_constr_value_gap = 0 # unsigned number + +# Whether to align parameters in single-line functions that have the same +# name. The function names must already be aligned with each other. +align_same_func_call_params = false # true/false + +# The span for aligning function-call parameters for single line functions. +# +# 0: Don't align (default). +align_same_func_call_params_span = 0 # unsigned number + +# The threshold for aligning function-call parameters for single line +# functions. +# Use a negative number for absolute thresholds. +# +# 0: No limit (default). +align_same_func_call_params_thresh = 0 # number + +# The span for aligning variable definitions. +# +# 0: Don't align (default). +align_var_def_span = 0 # unsigned number + +# How to consider (or treat) the '*' in the alignment of variable definitions. +# +# 0: Part of the type 'void * foo;' (default) +# 1: Part of the variable 'void *foo;' +# 2: Dangling 'void *foo;' +# Dangling: the '*' will not be taken into account when aligning. +align_var_def_star_style = 0 # unsigned number + +# How to consider (or treat) the '&' in the alignment of variable definitions. +# +# 0: Part of the type 'long & foo;' (default) +# 1: Part of the variable 'long &foo;' +# 2: Dangling 'long &foo;' +# Dangling: the '&' will not be taken into account when aligning. +align_var_def_amp_style = 0 # unsigned number + +# The threshold for aligning variable definitions. +# Use a negative number for absolute thresholds. +# +# 0: No limit (default). +align_var_def_thresh = 0 # number + +# The gap for aligning variable definitions. +align_var_def_gap = 0 # unsigned number + +# Whether to align the colon in struct bit fields. +align_var_def_colon = false # true/false + +# The gap for aligning the colon in struct bit fields. +align_var_def_colon_gap = 0 # unsigned number + +# Whether to align any attribute after the variable name. +align_var_def_attribute = false # true/false + +# Whether to align inline struct/enum/union variable definitions. +align_var_def_inline = false # true/false + +# The span for aligning on '=' in assignments. +# +# 0: Don't align (default). +align_assign_span = 0 # unsigned number + +# The span for aligning on '=' in function prototype modifier. +# +# 0: Don't align (default). +align_assign_func_proto_span = 0 # unsigned number + +# The threshold for aligning on '=' in assignments. +# Use a negative number for absolute thresholds. +# +# 0: No limit (default). +align_assign_thresh = 0 # number + +# How to apply align_assign_span to function declaration "assignments", i.e. +# 'virtual void foo() = 0' or '~foo() = {default|delete}'. +# +# 0: Align with other assignments (default) +# 1: Align with each other, ignoring regular assignments +# 2: Don't align +align_assign_decl_func = 0 # unsigned number + +# The span for aligning on '=' in enums. +# +# 0: Don't align (default). +align_enum_equ_span = 0 # unsigned number + +# The threshold for aligning on '=' in enums. +# Use a negative number for absolute thresholds. +# +# 0: no limit (default). +align_enum_equ_thresh = 0 # number + +# The span for aligning class member definitions. +# +# 0: Don't align (default). +align_var_class_span = 0 # unsigned number + +# The threshold for aligning class member definitions. +# Use a negative number for absolute thresholds. +# +# 0: No limit (default). +align_var_class_thresh = 0 # number + +# The gap for aligning class member definitions. +align_var_class_gap = 0 # unsigned number + +# The span for aligning struct/union member definitions. +# +# 0: Don't align (default). +align_var_struct_span = 0 # unsigned number + +# The threshold for aligning struct/union member definitions. +# Use a negative number for absolute thresholds. +# +# 0: No limit (default). +align_var_struct_thresh = 0 # number + +# The gap for aligning struct/union member definitions. +align_var_struct_gap = 0 # unsigned number + +# The span for aligning struct initializer values. +# +# 0: Don't align (default). +align_struct_init_span = 0 # unsigned number + +# The span for aligning single-line typedefs. +# +# 0: Don't align (default). +align_typedef_span = 0 # unsigned number + +# The minimum space between the type and the synonym of a typedef. +align_typedef_gap = 0 # unsigned number + +# How to align typedef'd functions with other typedefs. +# +# 0: Don't mix them at all (default) +# 1: Align the open parenthesis with the types +# 2: Align the function type name with the other type names +align_typedef_func = 0 # unsigned number + +# How to consider (or treat) the '*' in the alignment of typedefs. +# +# 0: Part of the typedef type, 'typedef int * pint;' (default) +# 1: Part of type name: 'typedef int *pint;' +# 2: Dangling: 'typedef int *pint;' +# Dangling: the '*' will not be taken into account when aligning. +align_typedef_star_style = 0 # unsigned number + +# How to consider (or treat) the '&' in the alignment of typedefs. +# +# 0: Part of the typedef type, 'typedef int & intref;' (default) +# 1: Part of type name: 'typedef int &intref;' +# 2: Dangling: 'typedef int &intref;' +# Dangling: the '&' will not be taken into account when aligning. +align_typedef_amp_style = 0 # unsigned number + +# The span for aligning comments that end lines. +# +# 0: Don't align (default). +align_right_cmt_span = 0 # unsigned number + +# Minimum number of columns between preceding text and a trailing comment in +# order for the comment to qualify for being aligned. Must be non-zero to have +# an effect. +align_right_cmt_gap = 0 # unsigned number + +# If aligning comments, whether to mix with comments after '}' and #endif with +# less than three spaces before the comment. +align_right_cmt_mix = false # true/false + +# Whether to only align trailing comments that are at the same brace level. +align_right_cmt_same_level = false # true/false + +# Minimum column at which to align trailing comments. Comments which are +# aligned beyond this column, but which can be aligned in a lesser column, +# may be "pulled in". +# +# 0: Ignore (default). +align_right_cmt_at_col = 0 # unsigned number + +# The span for aligning function prototypes. +# +# 0: Don't align (default). +align_func_proto_span = 0 # unsigned number + +# The threshold for aligning function prototypes. +# Use a negative number for absolute thresholds. +# +# 0: No limit (default). +align_func_proto_thresh = 0 # number + +# Minimum gap between the return type and the function name. +align_func_proto_gap = 0 # unsigned number + +# Whether to align function prototypes on the 'operator' keyword instead of +# what follows. +align_on_operator = false # true/false + +# Whether to mix aligning prototype and variable declarations. If true, +# align_var_def_XXX options are used instead of align_func_proto_XXX options. +align_mix_var_proto = false # true/false + +# Whether to align single-line functions with function prototypes. +# Uses align_func_proto_span. +align_single_line_func = false # true/false + +# Whether to align the open brace of single-line functions. +# Requires align_single_line_func=true. Uses align_func_proto_span. +align_single_line_brace = false # true/false + +# Gap for align_single_line_brace. +align_single_line_brace_gap = 0 # unsigned number + +# (OC) The span for aligning Objective-C message specifications. +# +# 0: Don't align (default). +align_oc_msg_spec_span = 0 # unsigned number + +# Whether to align macros wrapped with a backslash and a newline. This will +# not work right if the macro contains a multi-line comment. +align_nl_cont = false # true/false + +# Whether to align macro functions and variables together. +align_pp_define_together = false # true/false + +# The span for aligning on '#define' bodies. +# +# =0: Don't align (default) +# >0: Number of lines (including comments) between blocks +align_pp_define_span = 0 # unsigned number + +# The minimum space between label and value of a preprocessor define. +align_pp_define_gap = 0 # unsigned number + +# Whether to align lines that start with '<<' with previous '<<'. +# +# Default: true +align_left_shift = true # true/false + +# Whether to align text after 'asm volatile ()' colons. +align_asm_colon = false # true/false + +# (OC) Span for aligning parameters in an Objective-C message call +# on the ':'. +# +# 0: Don't align. +align_oc_msg_colon_span = 0 # unsigned number + +# (OC) Whether to always align with the first parameter, even if it is too +# short. +align_oc_msg_colon_first = false # true/false + +# (OC) Whether to align parameters in an Objective-C '+' or '-' declaration +# on the ':'. +align_oc_decl_colon = false # true/false + +# (OC) Whether to not align parameters in an Objectve-C message call if first +# colon is not on next line of the message call (the same way Xcode does +# aligment) +#align_oc_msg_colon_xcode_like = false # true/false ### not 0.69 + +# +# Comment modification options +# + +# Try to wrap comments at N columns. +cmt_width = 0 # unsigned number + +# How to reflow comments. +# +# 0: No reflowing (apart from the line wrapping due to cmt_width) (default) +# 1: No touching at all +# 2: Full reflow +cmt_reflow_mode = 0 # unsigned number + +# Whether to convert all tabs to spaces in comments. If false, tabs in +# comments are left alone, unless used for indenting. +cmt_convert_tab_to_spaces = false # true/false + +# Whether to apply changes to multi-line comments, including cmt_width, +# keyword substitution and leading chars. +# +# Default: true +cmt_indent_multi = true # true/false + +# Whether to group c-comments that look like they are in a block. +cmt_c_group = false # true/false + +# Whether to put an empty '/*' on the first line of the combined c-comment. +cmt_c_nl_start = false # true/false + +# Whether to add a newline before the closing '*/' of the combined c-comment. +cmt_c_nl_end = false # true/false + +# Whether to change cpp-comments into c-comments. +cmt_cpp_to_c = false # true/false + +# Whether to group cpp-comments that look like they are in a block. Only +# meaningful if cmt_cpp_to_c=true. +cmt_cpp_group = false # true/false + +# Whether to put an empty '/*' on the first line of the combined cpp-comment +# when converting to a c-comment. +# +# Requires cmt_cpp_to_c=true and cmt_cpp_group=true. +cmt_cpp_nl_start = false # true/false + +# Whether to add a newline before the closing '*/' of the combined cpp-comment +# when converting to a c-comment. +# +# Requires cmt_cpp_to_c=true and cmt_cpp_group=true. +cmt_cpp_nl_end = false # true/false + +# Whether to put a star on subsequent comment lines. +cmt_star_cont = false # true/false + +# The number of spaces to insert at the start of subsequent comment lines. +cmt_sp_before_star_cont = 0 # unsigned number + +# The number of spaces to insert after the star on subsequent comment lines. +cmt_sp_after_star_cont = 0 # unsigned number + +# For multi-line comments with a '*' lead, remove leading spaces if the first +# and last lines of the comment are the same length. +# +# Default: true +cmt_multi_check_last = true # true/false + +# For multi-line comments with a '*' lead, remove leading spaces if the first +# and last lines of the comment are the same length AND if the length is +# bigger as the first_len minimum. +# +# Default: 4 +cmt_multi_first_len_minimum = 4 # unsigned number + +# Path to a file that contains text to insert at the beginning of a file if +# the file doesn't start with a C/C++ comment. If the inserted text contains +# '$(filename)', that will be replaced with the current file's name. +cmt_insert_file_header = "" # string + +# Path to a file that contains text to insert at the end of a file if the +# file doesn't end with a C/C++ comment. If the inserted text contains +# '$(filename)', that will be replaced with the current file's name. +cmt_insert_file_footer = "" # string + +# Path to a file that contains text to insert before a function definition if +# the function isn't preceded by a C/C++ comment. If the inserted text +# contains '$(function)', '$(javaparam)' or '$(fclass)', these will be +# replaced with, respectively, the name of the function, the javadoc '@param' +# and '@return' stuff, or the name of the class to which the member function +# belongs. +cmt_insert_func_header = "" # string + +# Path to a file that contains text to insert before a class if the class +# isn't preceded by a C/C++ comment. If the inserted text contains '$(class)', +# that will be replaced with the class name. +cmt_insert_class_header = "" # string + +# Path to a file that contains text to insert before an Objective-C message +# specification, if the method isn't preceded by a C/C++ comment. If the +# inserted text contains '$(message)' or '$(javaparam)', these will be +# replaced with, respectively, the name of the function, or the javadoc +# '@param' and '@return' stuff. +cmt_insert_oc_msg_header = "" # string + +# Whether a comment should be inserted if a preprocessor is encountered when +# stepping backwards from a function name. +# +# Applies to cmt_insert_oc_msg_header, cmt_insert_func_header and +# cmt_insert_class_header. +cmt_insert_before_preproc = false # true/false + +# Whether a comment should be inserted if a function is declared inline to a +# class definition. +# +# Applies to cmt_insert_func_header. +# +# Default: true +cmt_insert_before_inlines = true # true/false + +# Whether a comment should be inserted if the function is a class constructor +# or destructor. +# +# Applies to cmt_insert_func_header. +cmt_insert_before_ctor_dtor = false # true/false + +# +# Code modifying options (non-whitespace) +# + +# Add or remove braces on a single-line 'do' statement. +mod_full_brace_do = remove # ignore/add/remove/force + +# Add or remove braces on a single-line 'for' statement. +mod_full_brace_for = remove # ignore/add/remove/force + +# (Pawn) Add or remove braces on a single-line function definition. +mod_full_brace_function = ignore # ignore/add/remove/force + +# Add or remove braces on a single-line 'if' statement. Braces will not be +# removed if the braced statement contains an 'else'. +mod_full_brace_if = add # ignore/add/remove/force + +# Whether to enforce that all blocks of an 'if'/'else if'/'else' chain either +# have, or do not have, braces. If true, braces will be added if any block +# needs braces, and will only be removed if they can be removed from all +# blocks. +# +# Overrides mod_full_brace_if. +mod_full_brace_if_chain = false # true/false + +# Whether to add braces to all blocks of an 'if'/'else if'/'else' chain. +# If true, mod_full_brace_if_chain will only remove braces from an 'if' that +# does not have an 'else if' or 'else'. +mod_full_brace_if_chain_only = true # true/false + +# Add or remove braces on single-line 'while' statement. +mod_full_brace_while = remove # ignore/add/remove/force + +# Add or remove braces on single-line 'using ()' statement. +mod_full_brace_using = remove # ignore/add/remove/force + +# Don't remove braces around statements that span N newlines +mod_full_brace_nl = 0 # unsigned number + +# Whether to prevent removal of braces from 'if'/'for'/'while'/etc. blocks +# which span multiple lines. +# +# Affects: +# mod_full_brace_for +# mod_full_brace_if +# mod_full_brace_if_chain +# mod_full_brace_if_chain_only +# mod_full_brace_while +# mod_full_brace_using +# +# Does not affect: +# mod_full_brace_do +# mod_full_brace_function +mod_full_brace_nl_block_rem_mlcond = false # true/false + +# Add or remove unnecessary parenthesis on 'return' statement. +mod_paren_on_return = add # ignore/add/remove/force + +# (Pawn) Whether to change optional semicolons to real semicolons. +mod_pawn_semicolon = false # true/false + +# Whether to fully parenthesize Boolean expressions in 'while' and 'if' +# statement, as in 'if (a && b > c)' => 'if (a && (b > c))'. +mod_full_paren_if_bool = false # true/false + +# Whether to remove superfluous semicolons. +mod_remove_extra_semicolon = false # true/false + +# If a function body exceeds the specified number of newlines and doesn't have +# a comment after the close brace, a comment will be added. +mod_add_long_function_closebrace_comment = 0 # unsigned number + +# If a namespace body exceeds the specified number of newlines and doesn't +# have a comment after the close brace, a comment will be added. +mod_add_long_namespace_closebrace_comment = 0 # unsigned number + +# If a class body exceeds the specified number of newlines and doesn't have a +# comment after the close brace, a comment will be added. +mod_add_long_class_closebrace_comment = 0 # unsigned number + +# If a switch body exceeds the specified number of newlines and doesn't have a +# comment after the close brace, a comment will be added. +mod_add_long_switch_closebrace_comment = 0 # unsigned number + +# If an #ifdef body exceeds the specified number of newlines and doesn't have +# a comment after the #endif, a comment will be added. +mod_add_long_ifdef_endif_comment = 0 # unsigned number + +# If an #ifdef or #else body exceeds the specified number of newlines and +# doesn't have a comment after the #else, a comment will be added. +mod_add_long_ifdef_else_comment = 0 # unsigned number + +# Whether to take care of the case by the mod_sort_xx options. +#mod_sort_case_sensitive = false # true/false ### not 0.69 + +# Whether to sort consecutive single-line 'import' statements. +mod_sort_import = false # true/false + +# (C#) Whether to sort consecutive single-line 'using' statements. +mod_sort_using = false # true/false + +# Whether to sort consecutive single-line '#include' statements (C/C++) and +# '#import' statements (Objective-C). Be aware that this has the potential to +# break your code if your includes/imports have ordering dependencies. +mod_sort_include = false # true/false + +# Whether to prioritize '#include' and '#import' statements that contain +# filename without extension when sorting is enabled. +#mod_sort_incl_import_prioritize_filename = false # true/false ### not 0.69 + +# Whether to prioritize '#include' and '#import' statements that does not +# contain extensions when sorting is enabled. +#mod_sort_incl_import_prioritize_extensionless = false # true/false ### not 0.69 + +# Whether to prioritize '#include' and '#import' statements that contain +# angle over quotes when sorting is enabled. +#mod_sort_incl_import_prioritize_angle_over_quotes = false # true/false ### not 0.69 + +# Whether to ignore file extension in '#include' and '#import' statements +# for sorting comparison. +#mod_sort_incl_import_ignore_extension = false # true/false ### not 0.69 + +# Whether to group '#include' and '#import' statements when sorting is enabled. +#mod_sort_incl_import_grouping_enabled = false # true/false ### not 0.69 + +# Whether to move a 'break' that appears after a fully braced 'case' before +# the close brace, as in 'case X: { ... } break;' => 'case X: { ... break; }'. +mod_move_case_break = false # true/false + +# Add or remove braces around a fully braced case statement. Will only remove +# braces if there are no variable declarations in the block. +mod_case_brace = ignore # ignore/add/remove/force + +# Whether to remove a void 'return;' that appears as the last statement in a +# function. +mod_remove_empty_return = false # true/false + +# Add or remove the comma after the last value of an enumeration. +mod_enum_last_comma = ignore # ignore/add/remove/force + +# (OC) Whether to organize the properties. If true, properties will be +# rearranged according to the mod_sort_oc_property_*_weight factors. +mod_sort_oc_properties = false # true/false + +# (OC) Weight of a class property modifier. +mod_sort_oc_property_class_weight = 0 # number + +# (OC) Weight of 'atomic' and 'nonatomic'. +mod_sort_oc_property_thread_safe_weight = 0 # number + +# (OC) Weight of 'readwrite' when organizing properties. +mod_sort_oc_property_readwrite_weight = 0 # number + +# (OC) Weight of a reference type specifier ('retain', 'copy', 'assign', +# 'weak', 'strong') when organizing properties. +mod_sort_oc_property_reference_weight = 0 # number + +# (OC) Weight of getter type ('getter=') when organizing properties. +mod_sort_oc_property_getter_weight = 0 # number + +# (OC) Weight of setter type ('setter=') when organizing properties. +mod_sort_oc_property_setter_weight = 0 # number + +# (OC) Weight of nullability type ('nullable', 'nonnull', 'null_unspecified', +# 'null_resettable') when organizing properties. +mod_sort_oc_property_nullability_weight = 0 # number + +# +# Preprocessor options +# + +# Add or remove indentation of preprocessor directives inside #if blocks +# at brace level 0 (file-level). +pp_indent = ignore # ignore/add/remove/force + +# Whether to indent #if/#else/#endif at the brace level. If false, these are +# indented from column 1. +pp_indent_at_level = false # true/false + +# Specifies the number of columns to indent preprocessors per level +# at brace level 0 (file-level). If pp_indent_at_level=false, also specifies +# the number of columns to indent preprocessors per level +# at brace level > 0 (function-level). +# +# Default: 1 +pp_indent_count = 1 # unsigned number + +# Add or remove space after # based on pp_level of #if blocks. +pp_space = ignore # ignore/add/remove/force + +# Sets the number of spaces per level added with pp_space. +pp_space_count = 0 # unsigned number + +# The indent for '#region' and '#endregion' in C# and '#pragma region' in +# C/C++. Negative values decrease indent down to the first column. +pp_indent_region = 0 # number + +# Whether to indent the code between #region and #endregion. +pp_region_indent_code = false # true/false + +# If pp_indent_at_level=true, sets the indent for #if, #else and #endif when +# not at file-level. Negative values decrease indent down to the first column. +# +# =0: Indent preprocessors using output_tab_size +# >0: Column at which all preprocessors will be indented +pp_indent_if = 0 # number + +# Whether to indent the code between #if, #else and #endif. +pp_if_indent_code = false # true/false + +# Whether to indent '#define' at the brace level. If false, these are +# indented from column 1. +pp_define_at_level = false # true/false + +# Whether to ignore the '#define' body while formatting. +pp_ignore_define_body = false # true/false + +# Whether to indent case statements between #if, #else, and #endif. +# Only applies to the indent of the preprocesser that the case statements +# directly inside of. +# +# Default: true +pp_indent_case = true # true/false + +# Whether to indent whole function definitions between #if, #else, and #endif. +# Only applies to the indent of the preprocesser that the function definition +# is directly inside of. +# +# Default: true +pp_indent_func_def = true # true/false + +# Whether to indent extern C blocks between #if, #else, and #endif. +# Only applies to the indent of the preprocesser that the extern block is +# directly inside of. +# +# Default: true +pp_indent_extern = true # true/false + +# Whether to indent braces directly inside #if, #else, and #endif. +# Only applies to the indent of the preprocesser that the braces are directly +# inside of. +# +# Default: true +pp_indent_brace = true # true/false + +# +# Sort includes options +# + +# The regex for include category with priority 0. +include_category_0 = "" # string + +# The regex for include category with priority 1. +include_category_1 = "" # string + +# The regex for include category with priority 2. +include_category_2 = "" # string + +# +# Use or Do not Use options +# + +# true: indent_func_call_param will be used (default) +# false: indent_func_call_param will NOT be used +# +# Default: true +use_indent_func_call_param = true # true/false + +# The value of the indentation for a continuation line is calculated +# differently if the statement is: +# - a declaration: your case with QString fileName ... +# - an assignment: your case with pSettings = new QSettings( ... +# +# At the second case the indentation value might be used twice: +# - at the assignment +# - at the function call (if present) +# +# To prevent the double use of the indentation value, use this option with the +# value 'true'. +# +# true: indent_continue will be used only once +# false: indent_continue will be used every time (default) +use_indent_continue_only_once = false # true/false + +# The value might be used twice: +# - at the assignment +# - at the opening brace +# +# To prevent the double use of the indentation value, use this option with the +# value 'true'. +# +# true: indentation will be used only once +# false: indentation will be used every time (default) +indent_cpp_lambda_only_once = false # true/false + +# Whether sp_after_angle takes precedence over sp_inside_fparen. This was the +# historic behavior, but is probably not the desired behavior, so this is off +# by default. +#use_sp_after_angle_always = false # true/false ### not 0.69 + +# Whether to apply special formatting for Qt SIGNAL/SLOT macros. Essentially, +# this tries to format these so that they match Qt's normalized form (i.e. the +# result of QMetaObject::normalizedSignature), which can slightly improve the +# performance of the QObject::connect call, rather than how they would +# otherwise be formatted. +# +# See options_for_QT.cpp for details. +# +# Default: true +use_options_overriding_for_qt_macros = true # true/false + +# If true: the form feed character is removed from the list +# of whitespace characters. +# See https://en.cppreference.com/w/cpp/string/byte/isspace +#use_form_feed_no_more_as_whitespace_character = false # true/false ### not 0.69 + +# +# Warn levels - 1: error, 2: warning (default), 3: note +# + +# (C#) Warning is given if doing tab-to-\t replacement and we have found one +# in a C# verbatim string literal. +# +# Default: 2 +warn_level_tabs_found_in_verbatim_string_literals = 2 # unsigned number + +# Limit the number of loops. +# Used by uncrustify.cpp to exit from infinite loop. +# 0: no limit. +#debug_max_number_of_loops = 0 # number ### not 0.69 + +# Set the number of the line to protocol; +# Used in the function prot_the_line if the 2. parameter is zero. +# 0: nothing protocol. +#debug_line_number_to_protocol = 0 # number ### not 0.69 + +# Meaning of the settings: +# Ignore - do not do any changes +# Add - makes sure there is 1 or more space/brace/newline/etc +# Force - makes sure there is exactly 1 space/brace/newline/etc, +# behaves like Add in some contexts +# Remove - removes space/brace/newline/etc +# +# +# - Token(s) can be treated as specific type(s) with the 'set' option: +# `set tokenType tokenString [tokenString...]` +# +# Example: +# `set BOOL __AND__ __OR__` +# +# tokenTypes are defined in src/token_enum.h, use them without the +# 'CT_' prefix: 'CT_BOOL' => 'BOOL' +# +# +# - Token(s) can be treated as type(s) with the 'type' option. +# `type tokenString [tokenString...]` +# +# Example: +# `type int c_uint_8 Rectangle` +# +# This can also be achieved with `set TYPE int c_uint_8 Rectangle` +# +# +# To embed whitespace in tokenStrings use the '\' escape character, or quote +# the tokenStrings. These quotes are supported: "'` +# +# +# - Support for the auto detection of languages through the file ending can be +# added using the 'file_ext' command. +# `file_ext langType langString [langString..]` +# +# Example: +# `file_ext CPP .ch .cxx .cpp.in` +# +# langTypes are defined in uncrusify_types.h in the lang_flag_e enum, use +# them without the 'LANG_' prefix: 'LANG_CPP' => 'CPP' +# +# +# - Custom macro-based indentation can be set up using 'macro-open', +# 'macro-else' and 'macro-close'. +# `(macro-open | macro-else | macro-close) tokenString` +# +# Example: +# `macro-open BEGIN_TEMPLATE_MESSAGE_MAP` +# `macro-open BEGIN_MESSAGE_MAP` +# `macro-close END_MESSAGE_MAP` +# +# +# option(s) with 'not default' value: 0 +# diff --git a/flashloaders/linker.ld b/flashloaders/linker.ld index 4d06433ea..7267fe10f 100644 --- a/flashloaders/linker.ld +++ b/flashloaders/linker.ld @@ -1,9 +1,9 @@ -/*. Entry Point *./ +/* Entry Point */ ENTRY( copy ) -/*. Specify the memory areas .*/ +/* Specify the memory areas */ MEMORY { RAM ( xrw) : ORIGIN = 0x20000000 , LENGTH = 64K -} \ No newline at end of file +} diff --git a/src/backend.h b/inc/backend.h similarity index 94% rename from src/backend.h rename to inc/backend.h index 42d12d4ac..f852da05d 100644 --- a/src/backend.h +++ b/inc/backend.h @@ -28,7 +28,7 @@ int (*current_mode) (stlink_t * stl); int (*force_debug) (stlink_t *sl); int32_t (*target_voltage) (stlink_t *sl); - int (*set_swdclk) (stlink_t * stl, uint16_t divisor); + int (*set_swdclk) (stlink_t * stl, uint16_t divisor); } stlink_backend_t; -#endif /* STLINK_BACKEND_H_ */ +#endif // STLINK_BACKEND_H_ diff --git a/inc/stlink.h b/inc/stlink.h index c87c6b173..140d68866 100644 --- a/inc/stlink.h +++ b/inc/stlink.h @@ -18,11 +18,11 @@ extern "C" { #endif -#define STLINK_ARRAY_SIZE(x) (sizeof(x)/sizeof(x[0])) +#define STLINK_ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0])) /* Max data transfer size */ // 6kB = max mem32_read block, 8kB sram -//#define Q_BUF_LEN 96 +// #define Q_BUF_LEN 96 #define Q_BUF_LEN (1024 * 100) // STLINK_DEBUG_RESETSYS, etc: @@ -103,16 +103,16 @@ enum target_state { #define S_RESET_ST (1 << 25) /* Map the relevant features, quirks and workaround for specific firmware version of stlink */ -#define STLINK_F_HAS_TRACE (1<<0) -#define STLINK_F_HAS_SWD_SET_FREQ (1<<1) -#define STLINK_F_HAS_JTAG_SET_FREQ (1<<2) -#define STLINK_F_HAS_MEM_16BIT (1<<3) -#define STLINK_F_HAS_GETLASTRWSTATUS2 (1<<4) -#define STLINK_F_HAS_DAP_REG (1<<5) -#define STLINK_F_QUIRK_JTAG_DP_READ (1<<6) -#define STLINK_F_HAS_AP_INIT (1<<7) -#define STLINK_F_HAS_DPBANKSEL (1<<8) -#define STLINK_F_HAS_RW8_512BYTES (1<<9) +#define STLINK_F_HAS_TRACE (1 << 0) +#define STLINK_F_HAS_SWD_SET_FREQ (1 << 1) +#define STLINK_F_HAS_JTAG_SET_FREQ (1 << 2) +#define STLINK_F_HAS_MEM_16BIT (1 << 3) +#define STLINK_F_HAS_GETLASTRWSTATUS2 (1 << 4) +#define STLINK_F_HAS_DAP_REG (1 << 5) +#define STLINK_F_QUIRK_JTAG_DP_READ (1 << 6) +#define STLINK_F_HAS_AP_INIT (1 << 7) +#define STLINK_F_HAS_DPBANKSEL (1 << 8) +#define STLINK_F_HAS_RW8_512BYTES (1 << 9) #define C_BUF_LEN 32 @@ -146,8 +146,8 @@ struct stlink_reg { typedef uint32_t stm32_addr_t; typedef struct flash_loader { -stm32_addr_t loader_addr; // loader sram addr -stm32_addr_t buf_addr; // buffer sram address + stm32_addr_t loader_addr; // loader sram addr + stm32_addr_t buf_addr; // buffer sram address } flash_loader_t; typedef struct _cortex_m3_cpuid_ { @@ -183,16 +183,16 @@ enum transport_type { }; typedef struct _stlink stlink_t; - + #include struct _stlink { struct _stlink_backend *backend; void *backend_data; - // Room for the command header + // room for the command header unsigned char c_buf[C_BUF_LEN]; - // Data transferred from or to device + // data transferred from or to device unsigned char q_buf[Q_BUF_LEN]; int q_len; @@ -205,28 +205,29 @@ struct _stlink { char serial[STLINK_SERIAL_MAX_SIZE]; int serial_size; - int freq; // set by stlink_open_usb(), values: STLINK_SWDCLK_xxx_DIVISOR + int freq; // set by stlink_open_usb(), values: STLINK_SWDCLK_xxx_DIVISOR enum stlink_flash_type flash_type; // stlink_chipid_params.flash_type, set by stlink_load_device_params(), values: STLINK_FLASH_TYPE_xxx bool has_dual_bank; - stm32_addr_t flash_base; // STM32_FLASH_BASE, set by stlink_load_device_params() - size_t flash_size; // calculated by stlink_load_device_params() - size_t flash_pgsz; // stlink_chipid_params.flash_pagesize, set by stlink_load_device_params() + stm32_addr_t flash_base; // STM32_FLASH_BASE, set by stlink_load_device_params() + size_t flash_size; // calculated by stlink_load_device_params() + size_t flash_pgsz; // stlink_chipid_params.flash_pagesize, set by stlink_load_device_params() /* sram settings */ - stm32_addr_t sram_base; // STM32_SRAM_BASE, set by stlink_load_device_params() - size_t sram_size; // stlink_chipid_params.sram_size, set by stlink_load_device_params() + stm32_addr_t sram_base; // STM32_SRAM_BASE, set by stlink_load_device_params() + size_t sram_size; // stlink_chipid_params.sram_size, set by stlink_load_device_params() - /* option settings */ + /* option settings */ stm32_addr_t option_base; size_t option_size; // bootloader - // sys_base and sys_size are not used by the tools, but are only there to download the bootloader code (see tests/sg.c) - stm32_addr_t sys_base; // stlink_chipid_params.bootrom_base, set by stlink_load_device_params() - size_t sys_size; // stlink_chipid_params.bootrom_size, set by stlink_load_device_params() + // sys_base and sys_size are not used by the tools, but are only there to download the bootloader code + // (see tests/sg.c) + stm32_addr_t sys_base; // stlink_chipid_params.bootrom_base, set by stlink_load_device_params() + size_t sys_size; // stlink_chipid_params.bootrom_size, set by stlink_load_device_params() struct stlink_version_ version; }; @@ -306,4 +307,4 @@ int stlink_fwrite_option_bytes(stlink_t *sl, const char* path, stm32_addr_t addr } #endif -#endif /* STLINK_H */ +#endif // STLINK_H diff --git a/inc/stm32.h b/inc/stm32.h index c71718653..36c14ee23 100644 --- a/inc/stm32.h +++ b/inc/stm32.h @@ -1,17 +1,17 @@ /* - * File: stm32.h + * File: stm32.h * - * STM32 specific defines + * STM32-specific defines */ #ifndef STM32_H #define STM32_H -// cortex core ids +/* Cortex core ids */ #define STM32VL_CORE_ID 0x1ba01477 #define STM32F7_CORE_ID 0x5ba02477 -// Constant STM32 memory map figures +/* Constant STM32 memory map figures */ #define STM32_FLASH_BASE ((uint32_t)0x08000000) #define STM32_SRAM_BASE ((uint32_t)0x20000000) #define STM32_G0_OPTION_BYTES_BASE ((uint32_t)0x1FFF7800) @@ -21,4 +21,4 @@ #define STM32_L4_OPTION_BYTES_BASE ((uint32_t)0x1FFF7800) #define STM32_L1_OPTION_BYTES_BASE ((uint32_t)0x1FF80000) -#endif /* STM32_H */ +#endif // STM32_H diff --git a/inc/version.h.in b/inc/version.h.in index 4ce2a5cac..66159e0e5 100644 --- a/inc/version.h.in +++ b/inc/version.h.in @@ -6,4 +6,4 @@ #define STLINK_VERSION_MINOR @PROJECT_VERSION_MINOR@ #define STLINK_VERSION_PATCH @PROJECT_VERSION_PATCH@ -#endif /* STLINK_VERSION_ */ +#endif // STLINK_VERSION_H_ diff --git a/src/common.c b/src/common.c index c9a54cf9f..361a24dbf 100644 --- a/src/common.c +++ b/src/common.c @@ -191,7 +191,7 @@ // WB Flash status register. #define STM32WB_FLASH_SR_BSY (16) /* FLASH_SR Busy */ -//32L4 register base is at FLASH_REGS_ADDR (0x40022000) +// 32L4 register base is at FLASH_REGS_ADDR (0x40022000) #define STM32L4_FLASH_KEYR (FLASH_REGS_ADDR + 0x08) #define STM32L4_FLASH_OPTKEYR (FLASH_REGS_ADDR + 0x0C) #define STM32L4_FLASH_SR (FLASH_REGS_ADDR + 0x10) @@ -214,16 +214,16 @@ #define STM32L4_FLASH_CR_OBL_LAUNCH 27 /* Option bytes reload */ // Bits requesting flash operations (useful when we want to clear them) #define STM32L4_FLASH_CR_OPBITS \ - (uint32_t)((1lu< le (don't swap) - buf[0] = ((unsigned char*) &ui)[0]; - buf[1] = ((unsigned char*) &ui)[1]; - buf[2] = ((unsigned char*) &ui)[2]; - buf[3] = ((unsigned char*) &ui)[3]; + buf[0] = ((unsigned char*)&ui)[0]; + buf[1] = ((unsigned char*)&ui)[1]; + buf[2] = ((unsigned char*)&ui)[2]; + buf[3] = ((unsigned char*)&ui)[3]; } else { - buf[0] = ((unsigned char*) &ui)[3]; - buf[1] = ((unsigned char*) &ui)[2]; - buf[2] = ((unsigned char*) &ui)[1]; - buf[3] = ((unsigned char*) &ui)[0]; + buf[0] = ((unsigned char*)&ui)[3]; + buf[1] = ((unsigned char*)&ui)[2]; + buf[2] = ((unsigned char*)&ui)[1]; + buf[3] = ((unsigned char*)&ui)[0]; } } void write_uint16(unsigned char* buf, uint16_t ui) { if (!is_bigendian()) { // le -> le (don't swap) - buf[0] = ((unsigned char*) &ui)[0]; - buf[1] = ((unsigned char*) &ui)[1]; + buf[0] = ((unsigned char*)&ui)[0]; + buf[1] = ((unsigned char*)&ui)[1]; } else { - buf[0] = ((unsigned char*) &ui)[1]; - buf[1] = ((unsigned char*) &ui)[0]; + buf[0] = ((unsigned char*)&ui)[1]; + buf[1] = ((unsigned char*)&ui)[0]; } } uint32_t read_uint32(const unsigned char *c, const int pt) { uint32_t ui; - char *p = (char *) &ui; + char *p = (char *)&ui; if (!is_bigendian()) { // le -> le (don't swap) p[0] = c[pt + 0]; @@ -317,49 +317,51 @@ uint32_t read_uint32(const unsigned char *c, const int pt) { p[2] = c[pt + 1]; p[3] = c[pt + 0]; } - return ui; + + return(ui); } static uint32_t get_stm32l0_flash_base(stlink_t *sl) { switch (sl->chip_id) { - case STLINK_CHIPID_STM32_L1_CAT2: - case STLINK_CHIPID_STM32_L1_MEDIUM: - case STLINK_CHIPID_STM32_L1_MEDIUM_PLUS: - case STLINK_CHIPID_STM32_L1_HIGH: - return STM32L1_FLASH_REGS_ADDR; - default: - return STM32L0_FLASH_REGS_ADDR; + case STLINK_CHIPID_STM32_L1_CAT2: + case STLINK_CHIPID_STM32_L1_MEDIUM: + case STLINK_CHIPID_STM32_L1_MEDIUM_PLUS: + case STLINK_CHIPID_STM32_L1_HIGH: + return(STM32L1_FLASH_REGS_ADDR); + default: + return(STM32L0_FLASH_REGS_ADDR); } } static uint32_t __attribute__((unused)) read_flash_rdp(stlink_t *sl) { uint32_t rdp; stlink_read_debug32(sl, FLASH_WRPR, &rdp); - return rdp & 0xff; + return(rdp & 0xff); } static inline uint32_t read_flash_cr(stlink_t *sl) { uint32_t reg, res; - if (sl->flash_type == STLINK_FLASH_TYPE_F4) + if (sl->flash_type == STLINK_FLASH_TYPE_F4) { reg = FLASH_F4_CR; - else if (sl->flash_type == STLINK_FLASH_TYPE_L4) + } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { reg = STM32L4_FLASH_CR; - else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) + } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || + sl->flash_type == STLINK_FLASH_TYPE_G4) { reg = STM32Gx_FLASH_CR; - else if (sl->flash_type == STLINK_FLASH_TYPE_WB) + } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { reg = STM32WB_FLASH_CR; - else + } else { reg = FLASH_CR; + } stlink_read_debug32(sl, reg, &res); #if DEBUG_FLASH fprintf(stdout, "CR:0x%x\n", res); #endif - return res; + return(res); } static inline uint32_t read_flash_cr2(stlink_t *sl) { @@ -368,7 +370,7 @@ static inline uint32_t read_flash_cr2(stlink_t *sl) { #if DEBUG_FLASH fprintf(stdout, "CR2:0x%x\n", res); #endif - return res; + return(res); } static inline unsigned int is_flash_locked(stlink_t *sl) { @@ -378,7 +380,7 @@ static inline unsigned int is_flash_locked(stlink_t *sl) { uint32_t n; if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || - (sl->flash_type == STLINK_FLASH_TYPE_F1_XL)) { + (sl->flash_type == STLINK_FLASH_TYPE_F1_XL)) { cr_reg = FLASH_CR; cr_lock_shift = FLASH_CR_LOCK; } else if (sl->flash_type == STLINK_FLASH_TYPE_F4) { @@ -399,25 +401,24 @@ static inline unsigned int is_flash_locked(stlink_t *sl) { cr_lock_shift = STM32WB_FLASH_CR_LOCK; } else { ELOG("unsupported flash method, abort\n"); - return -1; + return(-1); } stlink_read_debug32(sl, cr_reg, &n); - return n & (1u << cr_lock_shift); + return(n & (1u << cr_lock_shift)); } static void unlock_flash(stlink_t *sl) { uint32_t key_reg; uint32_t flash_key1 = FLASH_KEY1; uint32_t flash_key2 = FLASH_KEY2; - /* the unlock sequence consists of 2 write cycles where - 2 key values are written to the FLASH_KEYR register. - an invalid sequence results in a definitive lock of - the FPEC block until next reset. - */ + /* The unlock sequence consists of 2 write cycles where 2 key values are written + * to the FLASH_KEYR register. + * An invalid sequence results in a definitive lock of the FPEC block until next reset. + */ if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || - (sl->flash_type == STLINK_FLASH_TYPE_F1_XL)) { + (sl->flash_type == STLINK_FLASH_TYPE_F1_XL)) { key_reg = FLASH_KEYR; } else if (sl->flash_type == STLINK_FLASH_TYPE_F4) { key_reg = FLASH_F4_KEYR; @@ -428,7 +429,7 @@ static void unlock_flash(stlink_t *sl) { } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { key_reg = STM32L4_FLASH_KEYR; } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { + sl->flash_type == STLINK_FLASH_TYPE_G4) { key_reg = STM32Gx_FLASH_KEYR; } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { key_reg = STM32WB_FLASH_KEYR; @@ -450,20 +451,22 @@ static void unlock_flash(stlink_t *sl) { static int unlock_flash_if(stlink_t *sl) { if (is_flash_locked(sl)) { unlock_flash(sl); + if (is_flash_locked(sl)) { WLOG("Failed to unlock flash!\n"); - return -1; + return(-1); } } + DLOG("Successfully unlocked flash\n"); - return 0; + return(0); } static void lock_flash(stlink_t *sl) { uint32_t cr_lock_shift, cr_reg, n; if (sl->flash_type == STLINK_FLASH_TYPE_F0 || - sl->flash_type == STLINK_FLASH_TYPE_F1_XL) { + sl->flash_type == STLINK_FLASH_TYPE_F1_XL) { cr_reg = FLASH_CR; cr_lock_shift = FLASH_CR_LOCK; } else if (sl->flash_type == STLINK_FLASH_TYPE_F4) { @@ -503,43 +506,45 @@ static bool is_flash_option_locked(stlink_t *sl) { uint32_t n; switch (sl->flash_type) { - case STLINK_FLASH_TYPE_F0: - case STLINK_FLASH_TYPE_F1_XL: - optcr_reg = FLASH_CR; - optlock_shift = FLASH_CR_OPTWRE; - active_bit_level = 0; /* bit is "option write enable", not lock */ - break; - case STLINK_FLASH_TYPE_F4: - optcr_reg = FLASH_F4_OPTCR; - optlock_shift = FLASH_F4_OPTCR_LOCK; - break; - case STLINK_FLASH_TYPE_L0: - optcr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF; - optlock_shift = STM32L0_FLASH_OPTLOCK; - break; - case STLINK_FLASH_TYPE_L4: - optcr_reg = STM32L4_FLASH_CR; - optlock_shift = STM32L4_FLASH_CR_OPTLOCK; - break; - case STLINK_FLASH_TYPE_G0: - case STLINK_FLASH_TYPE_G4: - optcr_reg = STM32Gx_FLASH_CR; - optlock_shift = STM32Gx_FLASH_CR_OPTLOCK; - break; - case STLINK_FLASH_TYPE_WB: - optcr_reg = STM32WB_FLASH_CR; - optlock_shift = STM32WB_FLASH_CR_OPTLOCK; - break; - default: - ELOG("unsupported flash method, abort\n"); - return -1; + case STLINK_FLASH_TYPE_F0: + case STLINK_FLASH_TYPE_F1_XL: + optcr_reg = FLASH_CR; + optlock_shift = FLASH_CR_OPTWRE; + active_bit_level = 0; // bit is "option write enable", not lock + break; + case STLINK_FLASH_TYPE_F4: + optcr_reg = FLASH_F4_OPTCR; + optlock_shift = FLASH_F4_OPTCR_LOCK; + break; + case STLINK_FLASH_TYPE_L0: + optcr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF; + optlock_shift = STM32L0_FLASH_OPTLOCK; + break; + case STLINK_FLASH_TYPE_L4: + optcr_reg = STM32L4_FLASH_CR; + optlock_shift = STM32L4_FLASH_CR_OPTLOCK; + break; + case STLINK_FLASH_TYPE_G0: + case STLINK_FLASH_TYPE_G4: + optcr_reg = STM32Gx_FLASH_CR; + optlock_shift = STM32Gx_FLASH_CR_OPTLOCK; + break; + case STLINK_FLASH_TYPE_WB: + optcr_reg = STM32WB_FLASH_CR; + optlock_shift = STM32WB_FLASH_CR_OPTLOCK; + break; + default: + ELOG("unsupported flash method, abort\n"); + return(-1); } stlink_read_debug32(sl, optcr_reg, &n); - if (active_bit_level == 0) - return !(n & (1u << optlock_shift)); - return n & (1u << optlock_shift); + if (active_bit_level == 0) { + return(!(n & (1u << optlock_shift))); + } + + return(n & (1u << optlock_shift)); } @@ -548,46 +553,48 @@ static int lock_flash_option(stlink_t *sl) { int active_bit_level = 1; switch (sl->flash_type) { - case STLINK_FLASH_TYPE_F0: - case STLINK_FLASH_TYPE_F1_XL: - optcr_reg = FLASH_CR; - optlock_shift = FLASH_CR_OPTWRE; - active_bit_level = 0; - break; - case STLINK_FLASH_TYPE_F4: - optcr_reg = FLASH_F4_OPTCR; - optlock_shift = FLASH_F4_OPTCR_LOCK; - break; - case STLINK_FLASH_TYPE_L0: - optcr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF; - optlock_shift = STM32L0_FLASH_OPTLOCK; - break; - case STLINK_FLASH_TYPE_L4: - optcr_reg = STM32L4_FLASH_CR; - optlock_shift = STM32L4_FLASH_CR_OPTLOCK; - break; - case STLINK_FLASH_TYPE_G0: - case STLINK_FLASH_TYPE_G4: - optcr_reg = STM32Gx_FLASH_CR; - optlock_shift = STM32Gx_FLASH_CR_OPTLOCK; - break; - case STLINK_FLASH_TYPE_WB: - optcr_reg = STM32WB_FLASH_CR; - optlock_shift = STM32WB_FLASH_CR_OPTLOCK; - break; - default: - ELOG("unsupported flash method, abort\n"); - return -1; + case STLINK_FLASH_TYPE_F0: + case STLINK_FLASH_TYPE_F1_XL: + optcr_reg = FLASH_CR; + optlock_shift = FLASH_CR_OPTWRE; + active_bit_level = 0; + break; + case STLINK_FLASH_TYPE_F4: + optcr_reg = FLASH_F4_OPTCR; + optlock_shift = FLASH_F4_OPTCR_LOCK; + break; + case STLINK_FLASH_TYPE_L0: + optcr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF; + optlock_shift = STM32L0_FLASH_OPTLOCK; + break; + case STLINK_FLASH_TYPE_L4: + optcr_reg = STM32L4_FLASH_CR; + optlock_shift = STM32L4_FLASH_CR_OPTLOCK; + break; + case STLINK_FLASH_TYPE_G0: + case STLINK_FLASH_TYPE_G4: + optcr_reg = STM32Gx_FLASH_CR; + optlock_shift = STM32Gx_FLASH_CR_OPTLOCK; + break; + case STLINK_FLASH_TYPE_WB: + optcr_reg = STM32WB_FLASH_CR; + optlock_shift = STM32WB_FLASH_CR_OPTLOCK; + break; + default: + ELOG("unsupported flash method, abort\n"); + return(-1); } stlink_read_debug32(sl, optcr_reg, &n); - if (active_bit_level == 0) + + if (active_bit_level == 0) { n &= ~(1u << optlock_shift); - else + } else { n |= (1u << optlock_shift); - stlink_write_debug32(sl, optcr_reg, n); + } - return 0; + stlink_write_debug32(sl, optcr_reg, n); + return(0); } static int unlock_flash_option(stlink_t *sl) { @@ -596,55 +603,56 @@ static int unlock_flash_option(stlink_t *sl) { uint32_t optkey2 = FLASH_OPTKEY2; switch (sl->flash_type) { - case STLINK_FLASH_TYPE_F0: - case STLINK_FLASH_TYPE_F1_XL: - optkey_reg = FLASH_OPTKEYR; - optkey1 = FLASH_F0_OPTKEY1; - optkey2 = FLASH_F0_OPTKEY2; - break; - case STLINK_FLASH_TYPE_F4: - optkey_reg = FLASH_F4_OPT_KEYR; - break; - case STLINK_FLASH_TYPE_L0: - optkey_reg = get_stm32l0_flash_base(sl) + FLASH_OPTKEYR_OFF; - optkey1 = FLASH_L0_OPTKEY1; - optkey2 = FLASH_L0_OPTKEY2; - break; - case STLINK_FLASH_TYPE_L4: - optkey_reg = STM32L4_FLASH_OPTKEYR; - break; - case STLINK_FLASH_TYPE_G0: - case STLINK_FLASH_TYPE_G4: - optkey_reg = STM32Gx_FLASH_OPTKEYR; - break; - case STLINK_FLASH_TYPE_WB: - optkey_reg = STM32WB_FLASH_OPT_KEYR; - break; + case STLINK_FLASH_TYPE_F0: + case STLINK_FLASH_TYPE_F1_XL: + optkey_reg = FLASH_OPTKEYR; + optkey1 = FLASH_F0_OPTKEY1; + optkey2 = FLASH_F0_OPTKEY2; + break; + case STLINK_FLASH_TYPE_F4: + optkey_reg = FLASH_F4_OPT_KEYR; + break; + case STLINK_FLASH_TYPE_L0: + optkey_reg = get_stm32l0_flash_base(sl) + FLASH_OPTKEYR_OFF; + optkey1 = FLASH_L0_OPTKEY1; + optkey2 = FLASH_L0_OPTKEY2; + break; + case STLINK_FLASH_TYPE_L4: + optkey_reg = STM32L4_FLASH_OPTKEYR; + break; + case STLINK_FLASH_TYPE_G0: + case STLINK_FLASH_TYPE_G4: + optkey_reg = STM32Gx_FLASH_OPTKEYR; + break; + case STLINK_FLASH_TYPE_WB: + optkey_reg = STM32WB_FLASH_OPT_KEYR; + break; - default: - ELOG("unsupported flash method, abort\n"); - return -1; + default: + ELOG("unsupported flash method, abort\n"); + return(-1); } stlink_write_debug32(sl, optkey_reg, optkey1); stlink_write_debug32(sl, optkey_reg, optkey2); - - return 0; + return(0); } static int unlock_flash_option_if(stlink_t *sl) { if (is_flash_option_locked(sl)) { if (unlock_flash_option(sl)) { ELOG("Could not unlock flash option!\n"); - return -1; + return(-1); } + if (is_flash_option_locked(sl)) { ELOG("Failed to unlock flash option!\n"); - return -1; + return(-1); } } + DLOG("Successfully unlocked flash option\n"); - return 0; + return(0); } static void set_flash_cr_pg(stlink_t *sl) { @@ -677,17 +685,18 @@ static void set_flash_cr_pg(stlink_t *sl) { static void clear_flash_cr_pg(stlink_t *sl) { uint32_t cr_reg, n; - if (sl->flash_type == STLINK_FLASH_TYPE_F4) + if (sl->flash_type == STLINK_FLASH_TYPE_F4) { cr_reg = FLASH_F4_CR; - else if (sl->flash_type == STLINK_FLASH_TYPE_L4) + } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { cr_reg = STM32L4_FLASH_CR; - else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) + } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || + sl->flash_type == STLINK_FLASH_TYPE_G4) { cr_reg = STM32Gx_FLASH_CR; - else if (sl->flash_type == STLINK_FLASH_TYPE_WB) + } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { cr_reg = STM32WB_FLASH_CR; - else + } else { cr_reg = FLASH_CR; + } n = read_flash_cr(sl) & ~(1 << FLASH_CR_PG); stlink_write_debug32(sl, cr_reg, n); @@ -697,12 +706,13 @@ static void set_flash_cr_per(stlink_t *sl) { uint32_t cr_reg, val; if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) + sl->flash_type == STLINK_FLASH_TYPE_G4) { cr_reg = STM32Gx_FLASH_CR; - else if (sl->flash_type == STLINK_FLASH_TYPE_WB) + } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { cr_reg = STM32WB_FLASH_CR; - else + } else { cr_reg = FLASH_CR; + } stlink_read_debug32(sl, cr_reg, &val); val |= (1 << FLASH_CR_PER); @@ -718,12 +728,13 @@ static void clear_flash_cr_per(stlink_t *sl) { uint32_t cr_reg; if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) + sl->flash_type == STLINK_FLASH_TYPE_G4) { cr_reg = STM32Gx_FLASH_CR; - else if (sl->flash_type == STLINK_FLASH_TYPE_WB) + } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { cr_reg = STM32WB_FLASH_CR; - else + } else { cr_reg = FLASH_CR; + } const uint32_t n = read_flash_cr(sl) & ~(1 << FLASH_CR_PER); stlink_write_debug32(sl, cr_reg, n); @@ -744,9 +755,11 @@ static void set_flash_cr_mer(stlink_t *sl, bool v) { sl->flash_type == STLINK_FLASH_TYPE_G4) { cr_reg = STM32Gx_FLASH_CR; cr_mer = (1 << STM32Gx_FLASH_CR_MER1); + if (sl->has_dual_bank) { cr_mer |= (1 << STM32Gx_FLASH_CR_MER2); } + cr_pg = (1 << FLASH_CR_PG); } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { cr_reg = STM32WB_FLASH_CR; @@ -759,16 +772,19 @@ static void set_flash_cr_mer(stlink_t *sl, bool v) { } stlink_read_debug32(sl, cr_reg, &val); + if (val & cr_pg) { - /* STM32F030 will drop MER bit if PG was set */ + // STM32F030 will drop MER bit if PG was set val &= ~cr_pg; stlink_write_debug32(sl, cr_reg, val); } - if (v) + if (v) { val |= cr_mer; - else + } else { val &= ~cr_mer; + } + stlink_write_debug32(sl, cr_reg, val); } @@ -779,10 +795,13 @@ static void set_flash_cr2_mer(stlink_t *sl, bool v) { stlink_read_debug32(sl, FLASH_CR2, &val); val &= ~cr_pg; - if (v) + + if (v) { val |= cr_mer; - else + } else { val &= ~cr_mer; + } + stlink_write_debug32(sl, FLASH_CR2, val); } @@ -842,7 +861,8 @@ static void set_flash_cr2_strt(stlink_t *sl) { static inline uint32_t read_flash_sr(stlink_t *sl) { uint32_t res, sr_reg; - if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || (sl->flash_type == STLINK_FLASH_TYPE_F1_XL)) { + if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || + (sl->flash_type == STLINK_FLASH_TYPE_F1_XL)) { sr_reg = FLASH_SR; } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { sr_reg = get_stm32l0_flash_base(sl) + FLASH_SR_OFF; @@ -851,44 +871,45 @@ static inline uint32_t read_flash_sr(stlink_t *sl) { } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { sr_reg = STM32L4_FLASH_SR; } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { + sl->flash_type == STLINK_FLASH_TYPE_G4) { sr_reg = STM32Gx_FLASH_SR; } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { sr_reg = STM32WB_FLASH_SR; } else { ELOG("unsupported flash method, abort"); - return -1; + return(-1); } stlink_read_debug32(sl, sr_reg, &res); - - return res; + return(res); } static inline uint32_t read_flash_sr2(stlink_t *sl) { uint32_t res; stlink_read_debug32(sl, FLASH_SR2, &res); - return res; + return(res); } static inline unsigned int is_flash_busy(stlink_t *sl) { uint32_t sr_busy_shift; unsigned int res; - if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || (sl->flash_type == STLINK_FLASH_TYPE_F0) || (sl->flash_type == STLINK_FLASH_TYPE_L0)) { + if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || + (sl->flash_type == STLINK_FLASH_TYPE_F0) || + (sl->flash_type == STLINK_FLASH_TYPE_L0)) { sr_busy_shift = FLASH_SR_BSY; } else if (sl->flash_type == STLINK_FLASH_TYPE_F4) { sr_busy_shift = FLASH_F4_SR_BSY; } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { sr_busy_shift = STM32L4_FLASH_SR_BSY; } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { + sl->flash_type == STLINK_FLASH_TYPE_G4) { sr_busy_shift = STM32Gx_FLASH_SR_BSY; } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { sr_busy_shift = STM32WB_FLASH_SR_BSY; } else { ELOG("unsupported flash method, abort"); - return -1; + return(-1); } res = read_flash_sr(sl) & (1 << sr_busy_shift); @@ -897,11 +918,11 @@ static inline unsigned int is_flash_busy(stlink_t *sl) { res |= read_flash_sr2(sl) & (1 << sr_busy_shift); } - return res; + return(res); } static void wait_flash_busy(stlink_t *sl) { - /* todo: add some delays here */ + // TODO: add some delays here while (is_flash_busy(sl)) ; } @@ -910,44 +931,48 @@ static void wait_flash_busy_progress(stlink_t *sl) { int i = 0; fprintf(stdout, "Mass erasing"); fflush(stdout); + while (is_flash_busy(sl)) { usleep(10000); i++; + if (i % 100 == 0) { fprintf(stdout, "."); fflush(stdout); } } + fprintf(stdout, "\n"); } static int check_flash_error(stlink_t *sl) { uint32_t res = 0; + switch (sl->flash_type) { - case STLINK_FLASH_TYPE_F0: - res = read_flash_sr(sl) & FLASH_SR_ERROR_MASK; - break; - case STLINK_FLASH_TYPE_G0: - case STLINK_FLASH_TYPE_G4: - res = read_flash_sr(sl) & STM32Gx_FLASH_SR_ERROR_MASK; - break; - case STLINK_FLASH_TYPE_L0: - res = read_flash_sr(sl) & STM32L0_FLASH_SR_ERROR_MASK; - default: - break; + case STLINK_FLASH_TYPE_F0: + res = read_flash_sr(sl) & FLASH_SR_ERROR_MASK; + break; + case STLINK_FLASH_TYPE_G0: + case STLINK_FLASH_TYPE_G4: + res = read_flash_sr(sl) & STM32Gx_FLASH_SR_ERROR_MASK; + break; + case STLINK_FLASH_TYPE_L0: + res = read_flash_sr(sl) & STM32L0_FLASH_SR_ERROR_MASK; + default: + break; } if (res) { ELOG("Flash programming error : %#010x\n", res); - return -1; + return(-1); } - return 0; + return(0); } static inline unsigned int is_flash_eop(stlink_t *sl) { - return read_flash_sr(sl) & (1 << FLASH_SR_EOP); + return(read_flash_sr(sl) & (1 << FLASH_SR_EOP)); } static void __attribute__((unused)) clear_flash_sr_eop(stlink_t *sl) { @@ -956,7 +981,7 @@ static void __attribute__((unused)) clear_flash_sr_eop(stlink_t *sl) { } static void __attribute__((unused)) wait_flash_eop(stlink_t *sl) { - /* todo: add some delays here */ + // TODO: add some delays here while (is_flash_eop(sl) == 0) ; } @@ -992,12 +1017,12 @@ static inline void write_flash_cr_snb(stlink_t *sl, uint32_t n) { } static inline void write_flash_cr_bker_pnb(stlink_t *sl, uint32_t n) { - stlink_write_debug32(sl, STM32L4_FLASH_SR, 0xFFFFFFFF & ~(1<backend->close(sl); free(sl); } @@ -1021,26 +1049,28 @@ int stlink_exit_debug_mode(stlink_t *sl) { DLOG("*** stlink_exit_debug_mode ***\n"); ret = stlink_write_debug32(sl, STLINK_REG_DHCSR, STLINK_REG_DHCSR_DBGKEY); - if (ret == -1) - return ret; - return sl->backend->exit_debug_mode(sl); + if (ret == -1) { + return(ret); + } + + return(sl->backend->exit_debug_mode(sl)); } int stlink_enter_swd_mode(stlink_t *sl) { DLOG("*** stlink_enter_swd_mode ***\n"); - return sl->backend->enter_swd_mode(sl); + return(sl->backend->enter_swd_mode(sl)); } // Force the core into the debug mode -> halted state. int stlink_force_debug(stlink_t *sl) { DLOG("*** stlink_force_debug_mode ***\n"); - return sl->backend->force_debug(sl); + return(sl->backend->force_debug(sl)); } int stlink_exit_dfu_mode(stlink_t *sl) { DLOG("*** stlink_exit_dfu_mode ***\n"); - return sl->backend->exit_dfu_mode(sl); + return(sl->backend->exit_dfu_mode(sl)); } int stlink_core_id(stlink_t *sl) { @@ -1048,14 +1078,18 @@ int stlink_core_id(stlink_t *sl) { DLOG("*** stlink_core_id ***\n"); ret = sl->backend->core_id(sl); + if (ret == -1) { ELOG("Failed to read core_id\n"); - return ret; + return(ret); } - if (sl->verbose > 2) + + if (sl->verbose > 2) { stlink_print_data(sl); + } + DLOG("core_id = 0x%08x\n", sl->core_id); - return ret; + return(ret); } // stlink_chip_id() is called by stlink_load_device_params() @@ -1064,13 +1098,17 @@ int stlink_chip_id(stlink_t *sl, uint32_t *chip_id) { int ret; ret = stlink_read_debug32(sl, 0xE0042000, chip_id); - if (ret == -1) - return ret; - if (*chip_id == 0) - ret = stlink_read_debug32(sl, 0x40015800, chip_id); //Try Corex M0 DBGMCU_IDCODE register address + if (ret == -1) { + return(ret); + } + + if (*chip_id == 0) { + // Try Corex M0 DBGMCU_IDCODE register address + ret = stlink_read_debug32(sl, 0x40015800, chip_id); + } - return ret; + return(ret); } /** @@ -1086,23 +1124,24 @@ int stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid) { cpuid->variant = 0; cpuid->part = 0; cpuid->revision = 0; - return -1; + return(-1); } + cpuid->implementer_id = (raw >> 24) & 0x7f; cpuid->variant = (raw >> 20) & 0xf; cpuid->part = (raw >> 4) & 0xfff; cpuid->revision = raw & 0xf; - return 0; + return(0); } /** - * reads and decodes the flash parameters, as dynamically as possible + * Reads and decodes the flash parameters, as dynamically as possible * @param sl * @return 0 for success, or -1 for unsupported core type. */ int stlink_load_device_params(stlink_t *sl) { - // This seems to normally work so is unnecessary info for a normal - // user. Demoted to debug. -- REW + // This seems to normally work so is unnecessary info for a normal user. + // Demoted to debug. -- REW DLOG("Loading device parameters....\n"); const struct stlink_chipid_params *params = NULL; stlink_core_id(sl); @@ -1111,43 +1150,50 @@ int stlink_load_device_params(stlink_t *sl) { stlink_chip_id(sl, &chip_id); sl->chip_id = chip_id & 0xfff; - /* Fix chip_id for F4 rev A errata , Read CPU ID, as CoreID is the same for F2/F4*/ + + // Fix chip_id for F4 rev A errata , Read CPU ID, as CoreID is the same for F2/F4 if (sl->chip_id == 0x411) { uint32_t cpuid; stlink_read_debug32(sl, 0xE000ED00, &cpuid); - if ((cpuid & 0xfff0) == 0xc240) + + if ((cpuid & 0xfff0) == 0xc240) { sl->chip_id = 0x413; + } } params = stlink_chipid_get_params(sl->chip_id); + if (params == NULL) { WLOG("unknown chip id! %#x\n", chip_id); - return -1; + return(-1); } if (params->flash_type == STLINK_FLASH_TYPE_UNKNOWN) { WLOG("Invalid flash type, please check device declaration\n"); sl->flash_size = 0; - return 0; + return(0); } // These are fixed... sl->flash_base = STM32_FLASH_BASE; sl->sram_base = STM32_SRAM_BASE; - stlink_read_debug32(sl,(params->flash_size_reg) & ~3, &flash_size); - if (params->flash_size_reg & 2) - flash_size = flash_size >>16; + stlink_read_debug32(sl, (params->flash_size_reg) & ~3, &flash_size); + + if (params->flash_size_reg & 2) { + flash_size = flash_size >> 16; + } + flash_size = flash_size & 0xffff; if ((sl->chip_id == STLINK_CHIPID_STM32_L1_MEDIUM || sl->chip_id == STLINK_CHIPID_STM32_F1_VL_MEDIUM_LOW || - sl->chip_id == STLINK_CHIPID_STM32_L1_MEDIUM_PLUS) && ( flash_size == 0 )) { - sl->flash_size = 128 * 1024; + sl->chip_id == STLINK_CHIPID_STM32_L1_MEDIUM_PLUS) && (flash_size == 0)) { + sl->flash_size = 128 * 1024; } else if (sl->chip_id == STLINK_CHIPID_STM32_L1_CAT2) { sl->flash_size = (flash_size & 0xff) * 1024; } else if ((sl->chip_id & 0xFFF) == STLINK_CHIPID_STM32_L1_HIGH) { // 0 is 384k and 1 is 256k - if ( flash_size == 0){ + if (flash_size == 0) { sl->flash_size = 384 * 1024; } else { sl->flash_size = 256 * 1024; @@ -1165,54 +1211,53 @@ int stlink_load_device_params(stlink_t *sl) { sl->option_base = params->option_base; sl->option_size = params->option_size; - //medium and low devices have the same chipid. ram size depends on flash size. - //STM32F100xx datasheet Doc ID 16455 Table 2 - if (sl->chip_id == STLINK_CHIPID_STM32_F1_VL_MEDIUM_LOW && sl->flash_size < 64 * 1024){ + // medium and low devices have the same chipid. ram size depends on flash size. + // STM32F100xx datasheet Doc ID 16455 Table 2 + if (sl->chip_id == STLINK_CHIPID_STM32_F1_VL_MEDIUM_LOW && sl->flash_size < 64 * 1024) { sl->sram_size = 0x1000; } if (sl->chip_id == STLINK_CHIPID_STM32_G4_CAT3) { uint32_t flash_optr; stlink_read_debug32(sl, STM32Gx_FLASH_OPTR, &flash_optr); - if (!(flash_optr & (1 << STM32G4_FLASH_OPTR_DBANK))) { - sl->flash_pgsz <<= 1; - } + + if (!(flash_optr & (1 << STM32G4_FLASH_OPTR_DBANK))) { sl->flash_pgsz <<= 1; } } #if 0 // Old code -- REW ILOG("Device connected is: %s, id %#x\n", params->description, chip_id); - // TODO make note of variable page size here..... + // TODO: make note of variable page size here..... ILOG("SRAM size: %#x bytes (%d KiB), Flash: %#x bytes (%d KiB) in pages of %u bytes\n", - sl->sram_size, sl->sram_size / 1024, sl->flash_size, sl->flash_size / 1024, - (unsigned int)sl->flash_pgsz); + sl->sram_size, sl->sram_size / 1024, sl->flash_size, sl->flash_size / 1024, + (unsigned int)sl->flash_pgsz); #else ILOG("%s: %zd KiB SRAM, %zd KiB flash in at least %zd %s pages.\n", - params->description, sl->sram_size / 1024, sl->flash_size / 1024, - (sl->flash_pgsz < 1024)? sl->flash_pgsz : sl->flash_pgsz/1024, - (sl->flash_pgsz < 1024)? "byte" : "KiB"); + params->description, sl->sram_size / 1024, sl->flash_size / 1024, + (sl->flash_pgsz < 1024) ? sl->flash_pgsz : sl->flash_pgsz / 1024, + (sl->flash_pgsz < 1024) ? "byte" : "KiB"); #endif - return 0; + return(0); } int stlink_reset(stlink_t *sl) { DLOG("*** stlink_reset ***\n"); - return sl->backend->reset(sl); + return(sl->backend->reset(sl)); } int stlink_jtag_reset(stlink_t *sl, int value) { DLOG("*** stlink_jtag_reset ***\n"); - return sl->backend->jtag_reset(sl, value); + return(sl->backend->jtag_reset(sl, value)); } int stlink_run(stlink_t *sl) { DLOG("*** stlink_run ***\n"); - return sl->backend->run(sl); + return(sl->backend->run(sl)); } int stlink_set_swdclk(stlink_t *sl, uint16_t divisor) { DLOG("*** set_swdclk ***\n"); - return sl->backend->set_swdclk(sl, divisor); + return(sl->backend->set_swdclk(sl, divisor)); } int stlink_status(stlink_t *sl) { @@ -1221,8 +1266,7 @@ int stlink_status(stlink_t *sl) { DLOG("*** stlink_status ***\n"); ret = sl->backend->status(sl); stlink_core_stat(sl); - - return ret; + return(ret); } /** @@ -1232,13 +1276,14 @@ int stlink_status(stlink_t *sl) { */ void _parse_version(stlink_t *sl, stlink_version_t *slv) { sl->version.flags = 0; + if (sl->version.stlink_v < 3) { - uint32_t b0 = sl->q_buf[0]; //lsb + uint32_t b0 = sl->q_buf[0]; // lsb uint32_t b1 = sl->q_buf[1]; uint32_t b2 = sl->q_buf[2]; uint32_t b3 = sl->q_buf[3]; uint32_t b4 = sl->q_buf[4]; - uint32_t b5 = sl->q_buf[5]; //msb + uint32_t b5 = sl->q_buf[5]; // msb // b0 b1 || b2 b3 | b4 b5 // 4b | 6b | 6b || 2B | 2B @@ -1249,14 +1294,17 @@ void _parse_version(stlink_t *sl, stlink_version_t *slv) { slv->swim_v = b1 & 0x3f; slv->st_vid = (b3 << 8) | b2; slv->stlink_pid = (b5 << 8) | b4; - /* ST-LINK/V1 from J11 switch to api-v2 (and support SWD) */ - if (slv->stlink_v == 1) - slv->jtag_api = slv->jtag_v > 11? STLINK_JTAG_API_V2 : STLINK_JTAG_API_V1; - else { + + // ST-LINK/V1 from J11 switch to api-v2 (and support SWD) + if (slv->stlink_v == 1) { + slv->jtag_api = slv->jtag_v > 11 ? STLINK_JTAG_API_V2 : STLINK_JTAG_API_V1; + } else { slv->jtag_api = STLINK_JTAG_API_V2; - /* preferred API to get last R/W status from J15 */ - if (sl->version.jtag_v >= 15) + + // preferred API to get last R/W status from J15 + if (sl->version.jtag_v >= 15) { sl->version.flags |= STLINK_F_HAS_GETLASTRWSTATUS2; + } } } else { // V3 uses different version format, for reference see OpenOCD source @@ -1271,13 +1319,16 @@ void _parse_version(stlink_t *sl, stlink_version_t *slv) { /* preferred API to get last R/W status */ sl->version.flags |= STLINK_F_HAS_GETLASTRWSTATUS2; } + return; } int stlink_version(stlink_t *sl) { DLOG("*** looking up stlink version\n"); - if (sl->backend->version(sl)) - return -1; + + if (sl->backend->version(sl)) { + return(-1); + } _parse_version(sl, &sl->version); @@ -1286,21 +1337,25 @@ int stlink_version(stlink_t *sl) { DLOG("stlink version = 0x%x\n", sl->version.stlink_v); DLOG("jtag version = 0x%x\n", sl->version.jtag_v); DLOG("swim version = 0x%x\n", sl->version.swim_v); + if (sl->version.jtag_v == 0) { DLOG(" notice: the firmware doesn't support a jtag/swd interface\n"); } + if (sl->version.swim_v == 0) { DLOG(" notice: the firmware doesn't support a swim interface\n"); } - return 0; + return(0); } int stlink_target_voltage(stlink_t *sl) { int voltage = -1; DLOG("*** reading target voltage\n"); + if (sl->backend->target_voltage != NULL) { voltage = sl->backend->target_voltage(sl); + if (voltage != -1) { DLOG("target voltage = %ldmV\n", voltage); } else { @@ -1309,66 +1364,76 @@ int stlink_target_voltage(stlink_t *sl) { } else { DLOG("reading voltage not supported by backend\n"); } - return voltage; + + return(voltage); } int stlink_read_debug32(stlink_t *sl, uint32_t addr, uint32_t *data) { int ret; ret = sl->backend->read_debug32(sl, addr, data); - if (!ret) + + if (!ret) { DLOG("*** stlink_read_debug32 %x is %#x\n", *data, addr); + } - return ret; + return(ret); } int stlink_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data) { DLOG("*** stlink_write_debug32 %x to %#x\n", data, addr); - return sl->backend->write_debug32(sl, addr, data); + return(sl->backend->write_debug32(sl, addr, data)); } int stlink_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { DLOG("*** stlink_write_mem32 %u bytes to %#x\n", len, addr); + if (len % 4 != 0) { - fprintf(stderr, "Error: Data length doesn't have a 32 bit alignment: +%d byte.\n", len % 4); + fprintf(stderr, "Error: Data length doesn't have a 32 bit alignment: +%d byte.\n", + len % 4); abort(); } - return sl->backend->write_mem32(sl, addr, len); + + return(sl->backend->write_mem32(sl, addr, len)); } int stlink_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { DLOG("*** stlink_read_mem32 ***\n"); + if (len % 4 != 0) { // !!! never ever: fw gives just wrong values fprintf(stderr, "Error: Data length doesn't have a 32 bit alignment: +%d byte.\n", len % 4); abort(); } - return sl->backend->read_mem32(sl, addr, len); + + return(sl->backend->read_mem32(sl, addr, len)); } int stlink_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len) { DLOG("*** stlink_write_mem8 ***\n"); - if (len > 0x40){ // !!! never ever: Writing more then 0x40 bytes gives unexpected behaviour + + if (len > 0x40) { // !!! never ever: Writing more then 0x40 bytes gives unexpected behaviour fprintf(stderr, "Error: Data length > 64: +%d byte.\n", len); abort(); } - return sl->backend->write_mem8(sl, addr, len); + + return(sl->backend->write_mem8(sl, addr, len)); } int stlink_read_all_regs(stlink_t *sl, struct stlink_reg *regp) { DLOG("*** stlink_read_all_regs ***\n"); - return sl->backend->read_all_regs(sl, regp); + return(sl->backend->read_all_regs(sl, regp)); } int stlink_read_all_unsupported_regs(stlink_t *sl, struct stlink_reg *regp) { DLOG("*** stlink_read_all_unsupported_regs ***\n"); - return sl->backend->read_all_unsupported_regs(sl, regp); + return(sl->backend->read_all_unsupported_regs(sl, regp)); } int stlink_write_reg(stlink_t *sl, uint32_t reg, int idx) { DLOG("*** stlink_write_reg\n"); - return sl->backend->write_reg(sl, reg, idx); + return(sl->backend->write_reg(sl, reg, idx)); } int stlink_read_reg(stlink_t *sl, int r_idx, struct stlink_reg *regp) { @@ -1377,10 +1442,10 @@ int stlink_read_reg(stlink_t *sl, int r_idx, struct stlink_reg *regp) { if (r_idx > 20 || r_idx < 0) { fprintf(stderr, "Error: register index must be in [0..20]\n"); - return -1; + return(-1); } - return sl->backend->read_reg(sl, r_idx, regp); + return(sl->backend->read_reg(sl, r_idx, regp)); } int stlink_read_unsupported_reg(stlink_t *sl, int r_idx, struct stlink_reg *regp) { @@ -1390,18 +1455,18 @@ int stlink_read_unsupported_reg(stlink_t *sl, int r_idx, struct stlink_reg *regp DLOG(" (%d) ***\n", r_idx); /* Convert to values used by STLINK_REG_DCRSR */ - if (r_idx >= 0x1C && r_idx <= 0x1F) { /* primask, basepri, faultmask, or control */ + if (r_idx >= 0x1C && r_idx <= 0x1F) { // primask, basepri, faultmask, or control r_convert = 0x14; - } else if (r_idx == 0x40) { /* FPSCR */ + } else if (r_idx == 0x40) { // FPSCR r_convert = 0x21; } else if (r_idx >= 0x20 && r_idx < 0x40) { r_convert = 0x40 + (r_idx - 0x20); } else { fprintf(stderr, "Error: register address must be in [0x1C..0x40]\n"); - return -1; + return(-1); } - return sl->backend->read_unsupported_reg(sl, r_convert, regp); + return(sl->backend->read_unsupported_reg(sl, r_convert, regp)); } int stlink_write_unsupported_reg(stlink_t *sl, uint32_t val, int r_idx, struct stlink_reg *regp) { @@ -1412,45 +1477,46 @@ int stlink_write_unsupported_reg(stlink_t *sl, uint32_t val, int r_idx, struct s /* Convert to values used by STLINK_REG_DCRSR */ if (r_idx >= 0x1C && r_idx <= 0x1F) { /* primask, basepri, faultmask, or control */ - r_convert = r_idx; /* The backend function handles this */ - } else if (r_idx == 0x40) { /* FPSCR */ + r_convert = r_idx; // the backend function handles this + } else if (r_idx == 0x40) { // FPSCR r_convert = 0x21; } else if (r_idx >= 0x20 && r_idx < 0x40) { r_convert = 0x40 + (r_idx - 0x20); } else { fprintf(stderr, "Error: register address must be in [0x1C..0x40]\n"); - return -1; + return(-1); } - return sl->backend->write_unsupported_reg(sl, val, r_convert, regp); + return(sl->backend->write_unsupported_reg(sl, val, r_convert, regp)); } -bool stlink_is_core_halted(stlink_t *sl) -{ +bool stlink_is_core_halted(stlink_t *sl) { stlink_status(sl); - return sl->core_stat == TARGET_HALTED; + return(sl->core_stat == TARGET_HALTED); } int stlink_step(stlink_t *sl) { DLOG("*** stlink_step ***\n"); - return sl->backend->step(sl); + return(sl->backend->step(sl)); } int stlink_current_mode(stlink_t *sl) { int mode = sl->backend->current_mode(sl); + switch (mode) { case STLINK_DEV_DFU_MODE: DLOG("stlink current mode: dfu\n"); - return mode; + return(mode); case STLINK_DEV_DEBUG_MODE: DLOG("stlink current mode: debug (jtag or swd)\n"); - return mode; + return(mode); case STLINK_DEV_MASS_MODE: DLOG("stlink current mode: mass\n"); - return mode; + return(mode); } + DLOG("stlink mode: unknown!\n"); - return STLINK_DEV_UNKNOWN_MODE; + return(STLINK_DEV_UNKNOWN_MODE); } @@ -1463,12 +1529,12 @@ int stlink_current_mode(stlink_t *sl) { unsigned int is_bigendian(void) { static volatile const unsigned int i = 1; - return *(volatile const char*) &i == 0; + return(*(volatile const char*)&i == 0); } uint16_t read_uint16(const unsigned char *c, const int pt) { uint32_t ui; - char *p = (char *) &ui; + char *p = (char *)&ui; if (!is_bigendian()) { // le -> le (don't swap) p[0] = c[pt + 0]; @@ -1477,18 +1543,17 @@ uint16_t read_uint16(const unsigned char *c, const int pt) { p[0] = c[pt + 1]; p[1] = c[pt + 0]; } - return ui; + + return(ui); } // same as above with entrypoint. void stlink_run_at(stlink_t *sl, stm32_addr_t addr) { stlink_write_reg(sl, addr, 15); /* pc register */ - stlink_run(sl); - while (stlink_is_core_halted(sl)) - usleep(3000000); + while (stlink_is_core_halted(sl)) { usleep(3000000); } } @@ -1514,27 +1579,26 @@ void stlink_core_stat(stlink_t *sl) { } void stlink_print_data(stlink_t * sl) { - if (sl->q_len <= 0 || sl->verbose < UDEBUG) - return; - if (sl->verbose > 2) - DLOG("data_len = %d 0x%x\n", sl->q_len, sl->q_len); + if (sl->q_len <= 0 || sl->verbose < UDEBUG) { return; } + + if (sl->verbose > 2) { DLOG("data_len = %d 0x%x\n", sl->q_len, sl->q_len); } for (int i = 0; i < sl->q_len; i++) { if (i % 16 == 0) { - /* - if (sl->q_data_dir == Q_DATA_OUT) - fprintf(stdout, "\n<- 0x%08x ", sl->q_addr + i); - else - fprintf(stdout, "\n-> 0x%08x ", sl->q_addr + i); - */ + // if (sl->q_data_dir == Q_DATA_OUT) { + // fprintf(stdout, "\n<- 0x%08x ", sl->q_addr + i); + // } else { + // fprintf(stdout, "\n-> 0x%08x ", sl->q_addr + i); + // } } - DLOG(" %02x", (unsigned int) sl->q_buf[i]); + + DLOG(" %02x", (unsigned int)sl->q_buf[i]); } + DLOG("\n\n"); } -/* memory mapped file */ - +/* Memory mapped file */ typedef struct mapped_file { uint8_t* base; size_t len; @@ -1547,86 +1611,85 @@ static int map_file(mapped_file_t* mf, const char* path) { struct stat st; const int fd = open(path, O_RDONLY | O_BINARY); + if (fd == -1) { fprintf(stderr, "open(%s) == -1\n", path); - return -1; + return(-1); } if (fstat(fd, &st) == -1) { fprintf(stderr, "fstat(%s) == -1\n", path); goto on_error; } + if (sizeof(st.st_size) != sizeof(size_t)) { - /* On 32 bit systems, check if there is an overflow */ + // on 32 bit systems, check if there is an overflow if (st.st_size > (off_t)UINT32_MAX) { fprintf(stderr, "mmap() size_t overflow for file %s\n", path); goto on_error; } } - mf->base = (uint8_t*) mmap(NULL, (size_t)(st.st_size), PROT_READ, MAP_SHARED, fd, 0); + + mf->base = (uint8_t*)mmap(NULL, (size_t)(st.st_size), PROT_READ, MAP_SHARED, fd, 0); + if (mf->base == MAP_FAILED) { fprintf(stderr, "mmap() == MAP_FAILED for file %s\n", path); goto on_error; } mf->len = st.st_size; - - /* success */ - error = 0; + error = 0; // success on_error: close(fd); - - return error; + return(error); } static void unmap_file(mapped_file_t * mf) { - munmap((void*) mf->base, mf->len); - mf->base = (unsigned char*) MAP_FAILED; + munmap((void*)mf->base, mf->len); + mf->base = (unsigned char*)MAP_FAILED; mf->len = 0; } -/* Limit the block size to compare to 0x1800 - Anything larger will stall the STLINK2 - Maybe STLINK V1 needs smaller value!*/ +/* Limit the block size to compare to 0x1800 as anything larger will stall the STLINK2 + * Maybe STLINK V1 needs smaller value! + */ static int check_file(stlink_t* sl, mapped_file_t* mf, stm32_addr_t addr) { size_t off; size_t n_cmp = sl->flash_pgsz; - if ( n_cmp > 0x1800) - n_cmp = 0x1800; + + if ( n_cmp > 0x1800) { n_cmp = 0x1800; } for (off = 0; off < mf->len; off += n_cmp) { size_t aligned_size; - /* adjust last page size */ - size_t cmp_size = n_cmp; - if ((off + n_cmp) > mf->len) - cmp_size = mf->len - off; + size_t cmp_size = n_cmp; // adjust last page size + + if ((off + n_cmp) > mf->len) { cmp_size = mf->len - off; } aligned_size = cmp_size; - if (aligned_size & (4 - 1)) - aligned_size = (cmp_size + 4) & ~(4 - 1); - stlink_read_mem32(sl, addr + (uint32_t) off, aligned_size); + if (aligned_size & (4 - 1)) { aligned_size = (cmp_size + 4) & ~(4 - 1); } + + stlink_read_mem32(sl, addr + (uint32_t)off, aligned_size); - if (memcmp(sl->q_buf, mf->base + off, cmp_size)) - return -1; + if (memcmp(sl->q_buf, mf->base + off, cmp_size)) { return(-1); } } - return 0; + return(0); } static void md5_calculate(mapped_file_t *mf) { - /* calculate md5 checksum of given binary file */ - Md5Context md5Context; - MD5_HASH md5Hash; + // calculate md5 checksum of given binary file + Md5Context md5Context; + MD5_HASH md5Hash; Md5Initialise(&md5Context); Md5Update(&md5Context, mf->base, (uint32_t)mf->len); Md5Finalise(&md5Context, &md5Hash); printf("md5 checksum: "); - for (int i = 0; i < (int) sizeof(md5Hash); i++) { - printf("%x", md5Hash.bytes[i]); - } + + for (int i = 0; i < (int)sizeof(md5Hash); i++) { printf("%x", md5Hash.bytes[i]); } + printf(", "); } @@ -1634,31 +1697,31 @@ static void stlink_checksum(mapped_file_t *mp) { /* checksum that backward compatible with official ST tools */ uint32_t sum = 0; uint8_t *mp_byte = (uint8_t *)mp->base; - for (size_t i = 0; i < mp->len; ++i) { - sum += mp_byte[i]; - } + + for (size_t i = 0; i < mp->len; ++i) { sum += mp_byte[i]; } + printf("stlink checksum: 0x%08x\n", sum); } static void stlink_fwrite_finalize(stlink_t *sl, stm32_addr_t addr) { unsigned int val; - /* set stack*/ + // set stack stlink_read_debug32(sl, addr, &val); stlink_write_reg(sl, val, 13); - /* Set PC to the reset routine*/ + // set PC to the reset routine stlink_read_debug32(sl, addr + 4, &val); stlink_write_reg(sl, val, 15); stlink_run(sl); } int stlink_mwrite_sram(stlink_t * sl, uint8_t* data, uint32_t length, stm32_addr_t addr) { - /* write the file in sram at addr */ + // write the file in sram at addr int error = -1; size_t off; size_t len; - /* check addr range is inside the sram */ + // check addr range is inside the sram if (addr < sl->sram_base) { fprintf(stderr, "addr too low\n"); goto on_error; @@ -1669,47 +1732,42 @@ int stlink_mwrite_sram(stlink_t * sl, uint8_t* data, uint32_t length, stm32_addr fprintf(stderr, "addr too high\n"); goto on_error; } else if (addr & 3) { - /* todo */ fprintf(stderr, "unaligned addr\n"); goto on_error; } len = length; - if (len & 3) { - len -= len & 3; - } + if (len & 3) { len -= len & 3; } - /* do the copy by 1k blocks */ + // do the copy by 1kB blocks for (off = 0; off < len; off += 1024) { size_t size = 1024; - if ((off + size) > len) - size = len - off; + + if ((off + size) > len) { size = len - off; } memcpy(sl->q_buf, data + off, size); - /* round size if needed */ - if (size & 3) - size += 2; + if (size & 3) { size += 2; } // round size if needed - stlink_write_mem32(sl, addr + (uint32_t) off, size); + stlink_write_mem32(sl, addr + (uint32_t)off, size); } if (length > len) { memcpy(sl->q_buf, data + len, length - len); - stlink_write_mem8(sl, addr + (uint32_t) len, length - len); + stlink_write_mem8(sl, addr + (uint32_t)len, length - len); } - /* success */ - error = 0; + + error = 0; // success stlink_fwrite_finalize(sl, addr); on_error: - return error; + return(error); } int stlink_fwrite_sram(stlink_t * sl, const char* path, stm32_addr_t addr) { - /* write the file in sram at addr */ + // write the file in sram at addr int error = -1; size_t off; @@ -1718,13 +1776,14 @@ int stlink_fwrite_sram(stlink_t * sl, const char* path, stm32_addr_t addr) { if (map_file(&mf, path) == -1) { fprintf(stderr, "map_file() == -1\n"); - return -1; + return(-1); } + printf("file %s ", path); md5_calculate(&mf); stlink_checksum(&mf); - /* check addr range is inside the sram */ + // check if addr range is inside the SRAM if (addr < sl->sram_base) { fprintf(stderr, "addr too low\n"); goto on_error; @@ -1735,88 +1794,80 @@ int stlink_fwrite_sram(stlink_t * sl, const char* path, stm32_addr_t addr) { fprintf(stderr, "addr too high\n"); goto on_error; } else if (addr & 3) { - /* todo */ fprintf(stderr, "unaligned addr\n"); goto on_error; } len = mf.len; - if (len & 3) { - len -= len & 3; - } + if (len & 3) { len -= len & 3; } - /* do the copy by 1k blocks */ + // do the copy by 1kB blocks for (off = 0; off < len; off += 1024) { size_t size = 1024; - if ((off + size) > len) - size = len - off; + + if ((off + size) > len) { size = len - off; } memcpy(sl->q_buf, mf.base + off, size); - /* round size if needed */ - if (size & 3) - size += 2; + if (size & 3) { size += 2; } // round size if needed - stlink_write_mem32(sl, addr + (uint32_t) off, size); + stlink_write_mem32(sl, addr + (uint32_t)off, size); } if (mf.len > len) { memcpy(sl->q_buf, mf.base + len, mf.len - len); - stlink_write_mem8(sl, addr + (uint32_t) len, mf.len - len); + stlink_write_mem8(sl, addr + (uint32_t)len, mf.len - len); } - /* check the file ha been written */ + // check the file has been written if (check_file(sl, &mf, addr) == -1) { fprintf(stderr, "check_file() == -1\n"); goto on_error; } - /* success */ - error = 0; + error = 0; // success stlink_fwrite_finalize(sl, addr); on_error: unmap_file(&mf); - return error; + return(error); } typedef bool (*save_block_fn)(void* arg, uint8_t* block, ssize_t len); -static int stlink_read(stlink_t* sl, stm32_addr_t addr, size_t size, save_block_fn fn, void* fn_arg) { +static int stlink_read( + stlink_t* sl, stm32_addr_t addr, size_t size, save_block_fn fn, void* fn_arg) { int error = -1; - if (size <1) - size = sl->flash_size; + if (size < 1) { size = sl->flash_size; } - if (size > sl->flash_size) + if (size > sl->flash_size) { size = sl->flash_size; + } + + size_t cmp_size = (sl->flash_pgsz > 0x1800) ? 0x1800 : sl->flash_pgsz; - size_t cmp_size = (sl->flash_pgsz > 0x1800)? 0x1800:sl->flash_pgsz; for (size_t off = 0; off < size; off += cmp_size) { size_t aligned_size; - /* adjust last page size */ - if ((off + cmp_size) > size) - cmp_size = size - off; + // adjust last page size + if ((off + cmp_size) > size) { cmp_size = size - off; } aligned_size = cmp_size; - if (aligned_size & (4 - 1)) - aligned_size = (cmp_size + 4) & ~(4 - 1); - stlink_read_mem32(sl, addr + (uint32_t) off, aligned_size); + if (aligned_size & (4 - 1)) { aligned_size = (cmp_size + 4) & ~(4 - 1); } - if (!fn(fn_arg, sl->q_buf, aligned_size)) { - goto on_error; - } + stlink_read_mem32(sl, addr + (uint32_t)off, aligned_size); + + if (!fn(fn_arg, sl->q_buf, aligned_size)) { goto on_error; } } - /* success */ - error = 0; + error = 0; // success on_error: - return error; + return(error); } struct stlink_fread_worker_arg { @@ -1825,12 +1876,12 @@ struct stlink_fread_worker_arg { static bool stlink_fread_worker(void* arg, uint8_t* block, ssize_t len) { struct stlink_fread_worker_arg* the_arg = (struct stlink_fread_worker_arg*)arg; + if (write(the_arg->fd, block, len) != len) { fprintf(stderr, "write() != aligned_size\n"); - return false; - } - else { - return true; + return(false); + } else { + return(true); } } @@ -1845,45 +1896,56 @@ struct stlink_fread_ihex_worker_arg { static bool stlink_fread_ihex_newsegment(struct stlink_fread_ihex_worker_arg* the_arg) { uint32_t addr = the_arg->addr; uint8_t sum = 2 + 4 + (uint8_t)((addr & 0xFF000000) >> 24) + (uint8_t)((addr & 0x00FF0000) >> 16); - if (17 != fprintf(the_arg->file, ":02000004%04X%02X\r\n", (addr & 0xFFFF0000) >> 16, (uint8_t)(0x100 - sum))) - return false; - the_arg->lba = (addr & 0xFFFF0000); + if (17 != fprintf(the_arg->file, ":02000004%04X%02X\r\n", (addr & 0xFFFF0000) >> 16, + (uint8_t)(0x100 - sum))) { + return(false); + } - return true; + the_arg->lba = (addr & 0xFFFF0000); + return(true); } static bool stlink_fread_ihex_writeline(struct stlink_fread_ihex_worker_arg* the_arg) { uint8_t count = the_arg->buf_pos; - if (count == 0) return true; + + if (count == 0) { return(true); } uint32_t addr = the_arg->addr; if (the_arg->lba != (addr & 0xFFFF0000)) { // segment changed - if (!stlink_fread_ihex_newsegment(the_arg)) return false; + if (!stlink_fread_ihex_newsegment(the_arg)) { + return(false); + } } uint8_t sum = count + (uint8_t)((addr & 0x0000FF00) >> 8) + (uint8_t)(addr & 0x000000FF); - if (9 != fprintf(the_arg->file, ":%02X%04X00", count, (addr & 0x0000FFFF))) - return false; + + if (9 != fprintf(the_arg->file, ":%02X%04X00", count, (addr & 0x0000FFFF))) { + return(false); + } for (uint8_t i = 0; i < count; ++i) { uint8_t b = the_arg->buf[i]; sum += b; - if (2 != fprintf(the_arg->file, "%02X", b)) - return false; + + if (2 != fprintf(the_arg->file, "%02X", b)) { + return(false); + } } - if (4 != fprintf(the_arg->file, "%02X\r\n", (uint8_t)(0x100 - sum))) - return false; + if (4 != fprintf(the_arg->file, "%02X\r\n", (uint8_t)(0x100 - sum))) { + return(false); + } the_arg->addr += count; the_arg->buf_pos = 0; - return true; + return(true); } -static bool stlink_fread_ihex_init(struct stlink_fread_ihex_worker_arg* the_arg, int fd, stm32_addr_t addr) { +static bool stlink_fread_ihex_init( + struct stlink_fread_ihex_worker_arg* the_arg, int fd, stm32_addr_t addr) { the_arg->file = fdopen(fd, "w"); the_arg->addr = addr; the_arg->lba = 0; @@ -1897,109 +1959,127 @@ static bool stlink_fread_ihex_worker(void* arg, uint8_t* block, ssize_t len) { for (ssize_t i = 0; i < len; ++i) { if (the_arg->buf_pos == sizeof(the_arg->buf)) { // line is full - if (!stlink_fread_ihex_writeline(the_arg)) return false; + if (!stlink_fread_ihex_writeline(the_arg)) { return(false); } } the_arg->buf[the_arg->buf_pos++] = block[i]; } - return true; + return(true); } static bool stlink_fread_ihex_finalize(struct stlink_fread_ihex_worker_arg* the_arg) { - if (!stlink_fread_ihex_writeline(the_arg)) return false; + if (!stlink_fread_ihex_writeline(the_arg)) { return(false); } - // FIXME do we need the Start Linear Address? + // FIXME: do we need the Start Linear Address? - if (13 != fprintf(the_arg->file, ":00000001FF\r\n")) // EoF - return false; + if (13 != fprintf(the_arg->file, ":00000001FF\r\n")) { // EoF + return(false); + } return (0 == fclose(the_arg->file)); } int stlink_fread(stlink_t* sl, const char* path, bool is_ihex, stm32_addr_t addr, size_t size) { - /* read size bytes from addr to file */ + // read size bytes from addr to file int error; - int fd = open(path, O_RDWR | O_TRUNC | O_CREAT | O_BINARY, 00700); + if (fd == -1) { fprintf(stderr, "open(%s) == -1\n", path); - return -1; + return(-1); } if (is_ihex) { struct stlink_fread_ihex_worker_arg arg; + if (stlink_fread_ihex_init(&arg, fd, addr)) { error = stlink_read(sl, addr, size, &stlink_fread_ihex_worker, &arg); - if (!stlink_fread_ihex_finalize(&arg)) - error = -1; - } - else { + + if (!stlink_fread_ihex_finalize(&arg)) { error = -1; } + } else { error = -1; } - } - else { + } else { struct stlink_fread_worker_arg arg = { fd }; error = stlink_read(sl, addr, size, &stlink_fread_worker, &arg); } close(fd); - - return error; + return(error); } int write_buffer_to_sram(stlink_t *sl, flash_loader_t* fl, const uint8_t* buf, size_t size) { - /* write the buffer right after the loader */ + // write the buffer right after the loader size_t chunk = size & ~0x3; size_t rem = size & 0x3; + if (chunk) { memcpy(sl->q_buf, buf, chunk); stlink_write_mem32(sl, fl->buf_addr, chunk); } + if (rem) { - memcpy(sl->q_buf, buf+chunk, rem); - stlink_write_mem8(sl, (fl->buf_addr) + (uint32_t) chunk, rem); + memcpy(sl->q_buf, buf + chunk, rem); + stlink_write_mem8(sl, (fl->buf_addr) + (uint32_t)chunk, rem); } - return 0; + + return(0); } -uint32_t calculate_F4_sectornum(uint32_t flashaddr){ +uint32_t calculate_F4_sectornum(uint32_t flashaddr) { uint32_t offset = 0; - flashaddr &= ~STM32_FLASH_BASE; //Page now holding the actual flash address + flashaddr &= ~STM32_FLASH_BASE; // page now holding the actual flash address + if (flashaddr >= 0x100000) { offset = 12; flashaddr -= 0x100000; } - if (flashaddr<0x4000) return (offset + 0); - else if (flashaddr<0x8000) return(offset + 1); - else if (flashaddr<0xc000) return(offset + 2); - else if (flashaddr<0x10000) return(offset + 3); - else if (flashaddr<0x20000) return(offset + 4); - else return offset + (flashaddr/0x20000) +4; + + if (flashaddr < 0x4000) { + return (offset + 0); + } else if (flashaddr < 0x8000) { + return(offset + 1); + } else if (flashaddr < 0xc000) { + return(offset + 2); + } else if (flashaddr < 0x10000) { + return(offset + 3); + } else if (flashaddr < 0x20000) { + return(offset + 4); + } else { + return(offset + (flashaddr / 0x20000) + 4); + } } -uint32_t calculate_F7_sectornum(uint32_t flashaddr){ - flashaddr &= ~STM32_FLASH_BASE; //Page now holding the actual flash address - if (flashaddr<0x20000) return(flashaddr/0x8000); - else if (flashaddr<0x40000) return(4); - else return(flashaddr/0x40000) +4; +uint32_t calculate_F7_sectornum(uint32_t flashaddr) { + flashaddr &= ~STM32_FLASH_BASE; // Page now holding the actual flash address + + if (flashaddr < 0x20000) { + return(flashaddr / 0x8000); + } else if (flashaddr < 0x40000) { + return(4); + } else { + return((flashaddr / 0x40000) + 4); + } } -// Returns BKER:PNB for the given page address +// returns BKER:PNB for the given page address uint32_t calculate_L4_page(stlink_t *sl, uint32_t flashaddr) { uint32_t bker = 0; uint32_t flashopt; stlink_read_debug32(sl, STM32L4_FLASH_OPTR, &flashopt); flashaddr -= STM32_FLASH_BASE; + if (sl->chip_id == STLINK_CHIPID_STM32_L4 || sl->chip_id == STLINK_CHIPID_STM32_L496X || sl->chip_id == STLINK_CHIPID_STM32_L4RX) { - // This chip use dual banked flash + // this chip use dual banked flash if (flashopt & (uint32_t)(1lu << STM32L4_FLASH_OPTR_DUALBANK)) { - uint32_t banksize = (uint32_t) sl->flash_size / 2; + uint32_t banksize = (uint32_t)sl->flash_size / 2; + if (flashaddr >= banksize) { flashaddr -= banksize; bker = 0x100; @@ -2007,38 +2087,47 @@ uint32_t calculate_L4_page(stlink_t *sl, uint32_t flashaddr) { } } - // For 1MB chips without the dual-bank option set, the page address will - // overflow into the BKER bit, which gives us the correct bank:page value. - return bker | flashaddr/(uint32_t)sl->flash_pgsz; + // For 1MB chips without the dual-bank option set, the page address will overflow + // into the BKER bit, which gives us the correct bank:page value. + return(bker | flashaddr / (uint32_t)sl->flash_pgsz); } -uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr){ +uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr) { if ((sl->chip_id == STLINK_CHIPID_STM32_F2) || (sl->chip_id == STLINK_CHIPID_STM32_F4) || (sl->chip_id == STLINK_CHIPID_STM32_F4_DE) || - (sl->chip_id == STLINK_CHIPID_STM32_F4_LP) || - (sl->chip_id == STLINK_CHIPID_STM32_F4_HD) || - (sl->chip_id == STLINK_CHIPID_STM32_F411RE) || - (sl->chip_id == STLINK_CHIPID_STM32_F446) || - (sl->chip_id == STLINK_CHIPID_STM32_F4_DSI) || - (sl->chip_id == STLINK_CHIPID_STM32_F72XXX) || - (sl->chip_id == STLINK_CHIPID_STM32_F412)) { - uint32_t sector=calculate_F4_sectornum(flashaddr); - if (sector>= 12) { - sector -= 12; + (sl->chip_id == STLINK_CHIPID_STM32_F4_LP) || + (sl->chip_id == STLINK_CHIPID_STM32_F4_HD) || + (sl->chip_id == STLINK_CHIPID_STM32_F411RE) || + (sl->chip_id == STLINK_CHIPID_STM32_F446) || + (sl->chip_id == STLINK_CHIPID_STM32_F4_DSI) || + (sl->chip_id == STLINK_CHIPID_STM32_F72XXX) || + (sl->chip_id == STLINK_CHIPID_STM32_F412)) { + uint32_t sector = calculate_F4_sectornum(flashaddr); + + if (sector >= 12) { sector -= 12; } + + if (sector < 4) { + sl->flash_pgsz = 0x4000; + } else if (sector < 5) { + sl->flash_pgsz = 0x10000; + } else { + sl->flash_pgsz = 0x20000; + } + } else if (sl->chip_id == STLINK_CHIPID_STM32_F7 || + sl->chip_id == STLINK_CHIPID_STM32_F7XXXX) { + uint32_t sector = calculate_F7_sectornum(flashaddr); + + if (sector < 4) { + sl->flash_pgsz = 0x8000; + } else if (sector < 5) { + sl->flash_pgsz = 0x20000; + } else { + sl->flash_pgsz = 0x40000; } - if (sector<4) sl->flash_pgsz=0x4000; - else if (sector<5) sl->flash_pgsz=0x10000; - else sl->flash_pgsz=0x20000; - } - else if (sl->chip_id == STLINK_CHIPID_STM32_F7 || - sl->chip_id == STLINK_CHIPID_STM32_F7XXXX) { - uint32_t sector=calculate_F7_sectornum(flashaddr); - if (sector<4) sl->flash_pgsz=0x8000; - else if (sector<5) sl->flash_pgsz=0x20000; - else sl->flash_pgsz=0x40000; } - return (uint32_t) sl->flash_pgsz; + + return((uint32_t)sl->flash_pgsz); } /** @@ -2047,17 +2136,16 @@ uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr){ * @param flashaddr an address in the flash page to erase * @return 0 on success -ve on failure */ -int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) -{ +int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { if (sl->flash_type == STLINK_FLASH_TYPE_F4 || sl->flash_type == STLINK_FLASH_TYPE_L4) { - /* wait for ongoing op to finish */ + // wait for ongoing op to finish wait_flash_busy(sl); - /* unlock if locked */ + // unlock if locked unlock_flash_if(sl); - /* select the page to erase */ + // select the page to erase if ((sl->chip_id == STLINK_CHIPID_STM32_L4) || (sl->chip_id == STLINK_CHIPID_STM32_L43X) || (sl->chip_id == STLINK_CHIPID_STM32_L46X) || @@ -2066,38 +2154,35 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) // calculate the actual bank+page from the address uint32_t page = calculate_L4_page(sl, flashaddr); - fprintf(stderr, "EraseFlash - Page:0x%x Size:0x%x ", page, stlink_calculate_pagesize(sl, flashaddr)); + fprintf(stderr, "EraseFlash - Page:0x%x Size:0x%x ", + page, stlink_calculate_pagesize(sl, flashaddr)); write_flash_cr_bker_pnb(sl, page); } else if (sl->chip_id == STLINK_CHIPID_STM32_F7 || sl->chip_id == STLINK_CHIPID_STM32_F7XXXX) { // calculate the actual page from the address - uint32_t sector=calculate_F7_sectornum(flashaddr); - - fprintf(stderr, "EraseFlash - Sector:0x%x Size:0x%x ", sector, stlink_calculate_pagesize(sl, flashaddr)); + uint32_t sector = calculate_F7_sectornum(flashaddr); + fprintf(stderr, "EraseFlash - Sector:0x%x Size:0x%x ", + sector, stlink_calculate_pagesize(sl, flashaddr)); write_flash_cr_snb(sl, sector); } else { // calculate the actual page from the address - uint32_t sector=calculate_F4_sectornum(flashaddr); + uint32_t sector = calculate_F4_sectornum(flashaddr); - fprintf(stderr, "EraseFlash - Sector:0x%x Size:0x%x ", sector, stlink_calculate_pagesize(sl, flashaddr)); + fprintf(stderr, "EraseFlash - Sector:0x%x Size:0x%x ", + sector, stlink_calculate_pagesize(sl, flashaddr)); - //the SNB values for flash sectors in the second bank do not directly follow the values for the first bank on 2mb devices... - if (sector >= 12) sector += 4; + // the SNB values for flash sectors in the second bank do not directly + // follow the values for the first bank on 2mb devices... + if (sector >= 12) { sector += 4; } write_flash_cr_snb(sl, sector); } - /* start erase operation */ - set_flash_cr_strt(sl); - - /* wait for completion */ - wait_flash_busy(sl); - - /* relock the flash */ - //todo: fails to program if this is in - lock_flash(sl); + set_flash_cr_strt(sl); // start erase operation + wait_flash_busy(sl); // wait for completion + lock_flash(sl); // TODO: fails to program if this is in #if DEBUG_FLASH fprintf(stdout, "Erase Final CR:0x%x\n", read_flash_cr(sl)); #endif @@ -2105,6 +2190,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) uint32_t val; uint32_t flash_regs_base; + if (sl->chip_id == STLINK_CHIPID_STM32_L0 || sl->chip_id == STLINK_CHIPID_STM32_L0_CAT5 || sl->chip_id == STLINK_CHIPID_STM32_L0_CAT2 || @@ -2114,61 +2200,61 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) flash_regs_base = STM32L_FLASH_REGS_ADDR; } - /* check if the locks are set */ + // check if the locks are set stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); - if ((val & (1<<0))||(val & (1<<1))) { - /* disable pecr protection */ + + if ((val & (1 << 0)) || (val & (1 << 1))) { + // disable pecr protection stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, FLASH_L0_PEKEY1); stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, FLASH_L0_PEKEY2); - /* check pecr.pelock is cleared */ + // check pecr.pelock is cleared stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); + if (val & (1 << 0)) { WLOG("pecr.pelock not clear (%#x)\n", val); - return -1; + return(-1); } - /* unlock program memory */ + // unlock program memory stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, FLASH_L0_PRGKEY1); stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, FLASH_L0_PRGKEY2); - /* check pecr.prglock is cleared */ + // check pecr.prglock is cleared stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); + if (val & (1 << 1)) { WLOG("pecr.prglock not clear (%#x)\n", val); - return -1; + return(-1); } } - /* set pecr.{erase,prog} */ + // set pecr.{erase,prog} val |= (1 << 9) | (1 << 3); stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); -#if 0 /* fix_to_be_confirmed */ - - /* wait for sr.busy to be cleared - * MP: Test shows that busy bit is not set here. Perhaps, PM0062 is - * wrong and we do not need to wait here for clearing the busy bit. - * TEXANE: ok, if experience says so and it works for you, we comment - * it. If someone has a problem, please drop an email. +#if 0 + /* Wait for sr.busy to be cleared + * MP: Test shows that busy bit is not set here. Perhaps, PM0062 is wrong + * and we do not need to wait here for clearing the busy bit. */ do { stlink_read_debug32(sl, STM32L_FLASH_SR, &val) } while ((val & (1 << 0)) != 0); +#endif -#endif /* fix_to_be_confirmed */ - - /* write 0 to the first word of the page to be erased */ + // write 0 to the first word of the page to be erased stlink_write_debug32(sl, flashaddr, 0); - /* MP: It is better to wait for clearing the busy bit after issuing - page erase command, even though PM0062 recommends to wait before it. - Test shows that a few iterations is performed in the following loop - before busy bit is cleared.*/ - do { + /* MP: It is better to wait for clearing the busy bit after issuing page + * erase command, even though PM0062 recommends to wait before it. + * Test shows that a few iterations is performed in the following loop + * before busy bit is cleared. + */ + do stlink_read_debug32(sl, flash_regs_base + FLASH_SR_OFF, &val); - } while ((val & (1 << 0)) != 0); + while ((val & (1 << 0)) != 0); - /* reset lock bits */ + // reset lock bits stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); val |= (1 << 0) | (1 << 1) | (1 << 2); stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); @@ -2176,14 +2262,11 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) sl->flash_type == STLINK_FLASH_TYPE_G0 || sl->flash_type == STLINK_FLASH_TYPE_G4) { uint32_t val; - // Wait for any ongoing Flash operation to finish. - wait_flash_busy(sl); - // Unlock Flash if necessary. + wait_flash_busy(sl); // wait for any ongoing Flash operation to finish unlock_flash_if(sl); - // Set the 'enable Flash erase' bit. - set_flash_cr_per(sl); + set_flash_cr_per(sl); // set the 'enable Flash erase' bit - // Set the page to erase. + // set the page to erase if (sl->flash_type == STLINK_FLASH_TYPE_WB) { uint32_t flash_page = ((flashaddr - STM32_FLASH_BASE) / (uint32_t)(sl->flash_pgsz)); stlink_read_debug32(sl, STM32WB_FLASH_CR, &val); @@ -2198,154 +2281,107 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) stlink_read_debug32(sl, STM32Gx_FLASH_CR, &val); // sec 3.7.5 - PNB[5:0] is offset by 3. PER is 0x2. val &= ~(0x3F << 3); - val |= ((flash_page & 0x3F) << 3) | ( 1 << FLASH_CR_PER ); + val |= ((flash_page & 0x3F) << 3) | (1 << FLASH_CR_PER); stlink_write_debug32(sl, STM32Gx_FLASH_CR, val); } else if (sl->flash_type == STLINK_FLASH_TYPE_G4) { uint32_t flash_page = ((flashaddr - STM32_FLASH_BASE) / (uint32_t)(sl->flash_pgsz)); stlink_read_debug32(sl, STM32Gx_FLASH_CR, &val); // sec 3.7.5 - PNB[6:0] is offset by 3. PER is 0x2. val &= ~(0x7F << 3); - val |= ((flash_page & 0x7F) << 3) | ( 1 << FLASH_CR_PER ); + val |= ((flash_page & 0x7F) << 3) | (1 << FLASH_CR_PER); stlink_write_debug32(sl, STM32Gx_FLASH_CR, val); } - // Set the 'start operation' bit. - set_flash_cr_strt(sl); - // Wait for the 'busy' bit to clear. - wait_flash_busy(sl); - // Clear the 'enable page erase' bit. - clear_flash_cr_per(sl); - // Re-lock the flash. + set_flash_cr_strt(sl); // set the 'start operation' bit + wait_flash_busy(sl); // wait for the 'busy' bit to clear + clear_flash_cr_per(sl); // clear the 'enable page erase' bit lock_flash(sl); } else if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || - ((sl->flash_type == STLINK_FLASH_TYPE_F1_XL) && (flashaddr < FLASH_BANK2_START_ADDR))) { - /* wait for ongoing op to finish */ + ((sl->flash_type == STLINK_FLASH_TYPE_F1_XL) && (flashaddr < FLASH_BANK2_START_ADDR))) { wait_flash_busy(sl); - - /* unlock if locked */ unlock_flash_if(sl); - - /* clear the pg bit */ - clear_flash_cr_pg(sl); - - /* set the page erase bit */ - set_flash_cr_per(sl); - - /* select the page to erase */ - write_flash_ar(sl, flashaddr); - - /* start erase operation, reset by hw with bsy bit */ - set_flash_cr_strt(sl); - - /* wait for completion */ + clear_flash_cr_pg(sl); // clear the pg bit + set_flash_cr_per(sl); // set the page erase bit + write_flash_ar(sl, flashaddr); // select the page to erase + set_flash_cr_strt(sl); // start erase operation, reset by hw with busy bit wait_flash_busy(sl); - - /* relock the flash */ lock_flash(sl); } else if ((sl->flash_type == STLINK_FLASH_TYPE_F1_XL) && (flashaddr >= FLASH_BANK2_START_ADDR)) { - /* wait for ongoing op to finish */ wait_flash_busy(sl); - - /* unlock if locked */ unlock_flash_if(sl); - - /* set the page erase bit */ - set_flash_cr2_per(sl); - - /* select the page to erase */ - write_flash_ar2(sl, flashaddr); - - /* start erase operation, reset by hw with bsy bit */ - set_flash_cr2_strt(sl); - - /* wait for completion */ + set_flash_cr2_per(sl); // set the page erase bit + write_flash_ar2(sl, flashaddr); // select the page to erase + set_flash_cr2_strt(sl); // start erase operation, reset by hw with busy bit wait_flash_busy(sl); - - /* relock the flash */ lock_flash(sl); } else { WLOG("unknown coreid %x, page erase failed\n", sl->core_id); - return -1; + return(-1); } - /* todo: verify the erased page */ - - return 0; + // TODO: verify the erased page + return(0); } int stlink_erase_flash_mass(stlink_t *sl) { - /* TODO: User MER bit to mass-erase G0, G4, WB series. */ + // TODO: User MER bit to mass-erase G0, G4, WB series. if (sl->flash_type == STLINK_FLASH_TYPE_L0 || sl->flash_type == STLINK_FLASH_TYPE_WB) { - /* erase each page */ - int i = 0, num_pages = (int)(sl->flash_size/sl->flash_pgsz); + // erase each page + int i = 0, num_pages = (int)(sl->flash_size / sl->flash_pgsz); + for (i = 0; i < num_pages; i++) { - /* addr must be an addr inside the page */ - stm32_addr_t addr = (stm32_addr_t) sl->flash_base + i * (stm32_addr_t) sl->flash_pgsz; + // addr must be an addr inside the page + stm32_addr_t addr = (stm32_addr_t)sl->flash_base + i * (stm32_addr_t)sl->flash_pgsz; + if (stlink_erase_flash_page(sl, addr) == -1) { WLOG("Failed to erase_flash_page(%#zx) == -1\n", addr); - return -1; + return(-1); } - fprintf(stdout,"-> Flash page at %5d/%5d erased\n", i, num_pages); + + fprintf(stdout, "-> Flash page at %5d/%5d erased\n", i, num_pages); fflush(stdout); } + fprintf(stdout, "\n"); } else { - /* wait for ongoing op to finish */ wait_flash_busy(sl); - - /* unlock if locked */ unlock_flash_if(sl); - - /* set the mass erase bit */ - set_flash_cr_mer(sl,1); - - /* start erase operation, reset by hw with bsy bit */ - set_flash_cr_strt(sl); + set_flash_cr_mer(sl, 1); // set the mass erase bit + set_flash_cr_strt(sl); // start erase operation, reset by hw with busy bit if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL) { - /* set the mass erase bit in bank 2 */ - set_flash_cr2_mer(sl,1); - - /* start erase operation in bank 2 */ - set_flash_cr2_strt(sl); + set_flash_cr2_mer(sl, 1); // set the mass erase bit in bank 2 + set_flash_cr2_strt(sl); // start erase operation in bank 2 } - /* wait for completion */ wait_flash_busy_progress(sl); - check_flash_error(sl); - - /* relock the flash */ lock_flash(sl); - /* reset the mass erase bit */ - set_flash_cr_mer(sl,0); + set_flash_cr_mer(sl, 0); // reset the mass erase bit if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL) { - /* reset the mass erase bit in bank 2 */ - set_flash_cr2_mer(sl,0); + set_flash_cr2_mer(sl, 0); // reset the mass erase bit in bank 2 } - /* todo: verify the erased memory */ + // TODO: verify the erased memory } - return 0; + + return(0); } int stlink_fcheck_flash(stlink_t *sl, const char* path, stm32_addr_t addr) { - /* check the contents of path are at addr */ + // check the contents of path are at addr int res; mapped_file_t mf = MAPPED_FILE_INITIALIZER; - if (map_file(&mf, path) == -1) - return -1; + if (map_file(&mf, path) == -1) { return(-1); } res = check_file(sl, &mf, addr); - unmap_file(&mf); - - return res; + return(res); } /** @@ -2358,32 +2394,34 @@ int stlink_fcheck_flash(stlink_t *sl, const char* path, stm32_addr_t addr) { */ int stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, unsigned length) { size_t off; - size_t cmp_size = (sl->flash_pgsz > 0x1800)? 0x1800:sl->flash_pgsz; + size_t cmp_size = (sl->flash_pgsz > 0x1800) ? 0x1800 : sl->flash_pgsz; ILOG("Starting verification of write complete\n"); + for (off = 0; off < length; off += cmp_size) { size_t aligned_size; - /* adjust last page size */ - if ((off + cmp_size) > length) - cmp_size = length - off; + // adjust last page size + if ((off + cmp_size) > length) { cmp_size = length - off; } aligned_size = cmp_size; - if (aligned_size & (4 - 1)) - aligned_size = (cmp_size + 4) & ~(4 - 1); - stlink_read_mem32(sl, address + (uint32_t) off, aligned_size); + if (aligned_size & (4 - 1)) { aligned_size = (cmp_size + 4) & ~(4 - 1); } + + stlink_read_mem32(sl, address + (uint32_t)off, aligned_size); if (memcmp(sl->q_buf, data + off, cmp_size)) { ELOG("Verification of flash failed at offset: %u\n", (unsigned int)off); - return -1; + return(-1); } } + ILOG("Flash written and verified! jolly good!\n"); - return 0; + return(0); } -int stm32l1_write_half_pages(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t len, uint32_t pagesize) { +int stm32l1_write_half_pages( + stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t len, uint32_t pagesize) { unsigned int count; unsigned int num_half_pages = len / pagesize; uint32_t val; @@ -2400,215 +2438,223 @@ int stm32l1_write_half_pages(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uin } ILOG("Starting Half page flash write for STM32L core id\n"); - /* flash loader initialization */ + + /* Flash loader initialisation */ if (stlink_flash_loader_init(sl, &fl) == -1) { WLOG("stlink_flash_loader_init() == -1\n"); - return -1; + return(-1); } - /* Unlock already done */ + + // unlock already done stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); val |= (1 << FLASH_L1_FPRG); stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); val |= (1 << FLASH_L1_PROG); stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); + do { stlink_read_debug32(sl, flash_regs_base + FLASH_SR_OFF, &val); } while ((val & (1 << 0)) != 0); - for (count = 0; count < num_half_pages; count ++) { - if (stlink_flash_loader_run(sl, &fl, addr + count * pagesize, base + count * pagesize, pagesize) == -1) { + for (count = 0; count < num_half_pages; count++) { + if (stlink_flash_loader_run( + sl, &fl, addr + count * pagesize, base + count * pagesize, pagesize) == -1) { WLOG("l1_stlink_flash_loader_run(%#zx) failed! == -1\n", addr + count * pagesize); stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); - val &= ~((1 << FLASH_L1_FPRG) |(1 << FLASH_L1_PROG)); + val &= ~((1 << FLASH_L1_FPRG) | (1 << FLASH_L1_PROG)); stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); - return -1; + return(-1); } - /* wait for sr.busy to be cleared */ + + // wait for sr.busy to be cleared if (sl->verbose >= 1) { - /* show progress. writing procedure is slow - and previous errors are misleading */ + // show progress; writing procedure is slow and previous errors are misleading fprintf(stdout, "\r%3u/%u halfpages written", count + 1, num_half_pages); fflush(stdout); } + do { stlink_read_debug32(sl, flash_regs_base + FLASH_SR_OFF, &val); } while ((val & (1 << 0)) != 0); } + stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); val &= ~(1 << FLASH_L1_PROG); stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); val &= ~(1 << FLASH_L1_FPRG); stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); - - return 0; + return(0); } -int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t len, uint8_t eraseonly) { +int stlink_write_flash( + stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t len, uint8_t eraseonly) { size_t off; flash_loader_t fl; - ILOG("Attempting to write %d (%#x) bytes to stm32 address: %u (%#x)\n", - len, len, addr, addr); - /* check addr range is inside the flash */ + ILOG("Attempting to write %d (%#x) bytes to stm32 address: %u (%#x)\n", len, len, addr, addr); + // check addr range is inside the flash stlink_calculate_pagesize(sl, addr); + if (addr < sl->flash_base) { ELOG("addr too low %#x < %#x\n", addr, sl->flash_base); - return -1; + return(-1); } else if ((addr + len) < addr) { ELOG("addr overruns\n"); - return -1; + return(-1); } else if ((addr + len) > (sl->flash_base + sl->flash_size)) { ELOG("addr too high\n"); - return -1; + return(-1); } else if (addr & 1) { ELOG("unaligned addr 0x%x\n", addr); - return -1; + return(-1); } else if (len & 1) { WLOG("unaligned len 0x%x -- padding with zero\n", len); len += 1; } else if (addr & (sl->flash_pgsz - 1)) { - ELOG("addr not a multiple of current pagesize (%zd bytes), not supported, check page start address and compare with flash module organisation in related ST reference manual of your device.\n", sl->flash_pgsz); - return -1; + ELOG("addr not a multiple of current pagesize (%zd bytes), not supported, " + "check page start address and compare with flash module organisation " + "in related ST reference manual of your device.\n", sl->flash_pgsz); + return(-1); } - // Make sure we've loaded the context with the chip details + // make sure we've loaded the context with the chip details stlink_core_id(sl); - /* erase each page */ + + // Erase each page int page_count = 0; - for (off = 0; off < len; off += stlink_calculate_pagesize(sl, addr + (uint32_t) off)) { + + for (off = 0; off < len; off += stlink_calculate_pagesize(sl, addr + (uint32_t)off)) { // addr must be an addr inside the page - if (stlink_erase_flash_page(sl, addr + (uint32_t) off) == -1) { + if (stlink_erase_flash_page(sl, addr + (uint32_t)off) == -1) { ELOG("Failed to erase_flash_page(%#zx) == -1\n", addr + off); - return -1; + return(-1); } - ILOG("Flash page at addr: 0x%08lx erased\n", - (unsigned long)(addr + off)); + + ILOG("Flash page at addr: 0x%08lx erased\n", (unsigned long)(addr + off)); page_count++; } + ILOG("Finished erasing %d pages of %d (%#x) bytes\n", - page_count, sl->flash_pgsz, sl->flash_pgsz); + page_count, sl->flash_pgsz, sl->flash_pgsz); - if (eraseonly) - return 0; + if (eraseonly) { return(0); } if ((sl->flash_type == STLINK_FLASH_TYPE_F4) || (sl->flash_type == STLINK_FLASH_TYPE_L4)) { - /* todo: check write operation */ + // TODO: check write operation ILOG("Starting Flash write for F2/F4/L4\n"); - /* flash loader initialization */ + + // Flash loader initialisation if (stlink_flash_loader_init(sl, &fl) == -1) { ELOG("stlink_flash_loader_init() == -1\n"); - return -1; + return(-1); } - /* First unlock the cr */ - unlock_flash_if(sl); + unlock_flash_if(sl); // first unlock the cr - /* TODO: Check that Voltage range is 2.7 - 3.6 V */ + // TODO: Check that Voltage range is 2.7 - 3.6 V if ((sl->chip_id != STLINK_CHIPID_STM32_L4) && (sl->chip_id != STLINK_CHIPID_STM32_L43X) && (sl->chip_id != STLINK_CHIPID_STM32_L46X) && (sl->chip_id != STLINK_CHIPID_STM32_L496X) && (sl->chip_id != STLINK_CHIPID_STM32_L4RX)) { - if ( sl->version.stlink_v == 1){ - printf("STLINK V1 cannot read voltage, defaulting to 32-bit writes on F4 devices\n"); + if ( sl->version.stlink_v == 1) { + printf("STLINK V1 cannot read voltage, defaulting to 32-bit " + "writes on F4 devices\n"); write_flash_cr_psiz(sl, 2); - } - else { - /* set parallelisim to 32 bit*/ + } else { + // set parallelism to 32 bit int voltage = stlink_target_voltage(sl); + if (voltage == -1) { printf("Failed to read Target voltage\n"); - return voltage; + return(voltage); } else if (voltage > 2700) { printf("enabling 32-bit flash writes\n"); write_flash_cr_psiz(sl, 2); } else { - printf("Target voltage (%d mV) too low for 32-bit flash, using 8-bit flash writes\n", voltage); + printf("Target voltage (%d mV) too low for 32-bit flash, " + "using 8-bit flash writes\n", voltage); write_flash_cr_psiz(sl, 0); } } } else { - /* L4 does not have a byte-write mode */ + // L4 does not have a byte-write mode int voltage = stlink_target_voltage(sl); + if (voltage == -1) { printf("Failed to read Target voltage\n"); - return voltage; + return(voltage); } else if (voltage < 1710) { printf("Target voltage (%d mV) too low for flash writes!\n", voltage); - return -1; + return(-1); } } - /* set programming mode */ + // set programming mode set_flash_cr_pg(sl); size_t buf_size = (sl->sram_size > 0x8000) ? 0x8000 : 0x4000; + for (off = 0; off < len;) { size_t size = len - off > buf_size ? buf_size : len - off; - printf("size: %u\n", (unsigned int)size); - if (stlink_flash_loader_run(sl, &fl, addr + (uint32_t) off, base + off, size) == -1) { + if (stlink_flash_loader_run(sl, &fl, addr + (uint32_t)off, base + off, size) == -1) { ELOG("stlink_flash_loader_run(%#zx) failed! == -1\n", addr + off); - return -1; + return(-1); } off += size; } - /* Relock flash */ clear_flash_cr_pg(sl); lock_flash(sl); - } //STM32F4END - else if (sl->flash_type == STLINK_FLASH_TYPE_WB || - sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { + // STM32F4END + } else if (sl->flash_type == STLINK_FLASH_TYPE_WB || + sl->flash_type == STLINK_FLASH_TYPE_G0 || + sl->flash_type == STLINK_FLASH_TYPE_G4) { fprintf(stdout, "Writing\r\n"); fflush(stdout); - // Wait for any ongoing operations to finish. wait_flash_busy(sl); - // Unlock flash if necessary. - unlock_flash_if(sl); - // Set PG 'allow programming' bit. - set_flash_cr_pg(sl); - // Write all words. + unlock_flash_if(sl); // unlock flash if necessary + set_flash_cr_pg(sl); // set PG 'allow programming' bit + // write all words. off = 0; - fprintf(stdout, "Starting %3u page write\r\n", (unsigned int)(len/sl->flash_pgsz)); + fprintf(stdout, "Starting %3u page write\r\n", (unsigned int)(len / sl->flash_pgsz)); fflush(stdout); + for ( ; off < len; off += sizeof(uint32_t)) { uint32_t data; - if (off > 254) - fprintf(stdout, "\r"); - if ((off % sl->flash_pgsz) > (sl->flash_pgsz -5)) { + if (off > 254) { fprintf(stdout, "\r"); } + + if ((off % sl->flash_pgsz) > (sl->flash_pgsz - 5)) { fprintf(stdout, "\r%3u/%3u pages written", - (unsigned int)(off/sl->flash_pgsz), - (unsigned int)(len/sl->flash_pgsz)); + (unsigned int)(off / sl->flash_pgsz), + (unsigned int)(len / sl->flash_pgsz)); fflush(stdout); } - write_uint32((unsigned char*) &data, *(uint32_t*) (base + off)); - stlink_write_debug32(sl, addr + (uint32_t) off, data); - // Wait for 'busy' bit in FLASH_SR to clear. - wait_flash_busy(sl); + + write_uint32((unsigned char*)&data, *(uint32_t*)(base + off)); + stlink_write_debug32(sl, addr + (uint32_t)off, data); + wait_flash_busy(sl); // wait for 'busy' bit in FLASH_SR to clear } - // (Flash writes happen 2 words at a time.) + + // flash writes happen as 2 words at a time if ((off / sizeof(uint32_t)) % 2 != 0) { - // Write a single word of zeros. - stlink_write_debug32(sl, addr + (uint32_t) off, 0); - // Wait for 'busy' bit in FLASH_SR to clear. - wait_flash_busy(sl); + stlink_write_debug32(sl, addr + (uint32_t)off, 0); // write a single word of zeros + wait_flash_busy(sl); // wait for 'busy' bit in FLASH_SR to clear } - // Reset PG bit. - clear_flash_cr_pg(sl); - // Re-lock flash. + + clear_flash_cr_pg(sl); // reset PG bit. lock_flash(sl); - } - else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { - /* use fast word write. todo: half page. */ + } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { + // use fast word write + // TODO: half page uint32_t val; uint32_t flash_regs_base; uint32_t pagesize; @@ -2624,123 +2670,144 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t pagesize = L1_WRITE_BLOCK_SIZE; } - /* todo: check write operation */ + // TODO: check write operation - /* disable pecr protection */ + // disable pecr protection stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, FLASH_L0_PEKEY1); stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, FLASH_L0_PEKEY2); - /* check pecr.pelock is cleared */ + // check pecr.pelock is cleared stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); + if (val & (1 << 0)) { fprintf(stderr, "pecr.pelock not clear\n"); - return -1; + return(-1); } - /* unlock program memory */ + // unlock program memory stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, FLASH_L0_PRGKEY1); stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, FLASH_L0_PRGKEY2); - /* check pecr.prglock is cleared */ + // check pecr.prglock is cleared stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); + if (val & (1 << 1)) { fprintf(stderr, "pecr.prglock not clear\n"); - return -1; + return(-1); } + off = 0; + if (len > pagesize) { if (stm32l1_write_half_pages(sl, addr, base, len, pagesize) == -1) { - /* This may happen on a blank device! */ + // this may happen on a blank device! WLOG("\nwrite_half_pages failed == -1\n"); } else { - off = (len / pagesize)*pagesize; + off = (len / pagesize) * pagesize; } } - /* write remainingword in program memory */ + // write remaining word in program memory for ( ; off < len; off += sizeof(uint32_t)) { uint32_t data; - if (off > 254) - fprintf(stdout, "\r"); - if ((off % sl->flash_pgsz) > (sl->flash_pgsz -5)) { + if (off > 254) { fprintf(stdout, "\r"); } + + if ((off % sl->flash_pgsz) > (sl->flash_pgsz - 5)) { fprintf(stdout, "\r%3u/%3u pages written", - (unsigned int)(off/sl->flash_pgsz), - (unsigned int)(len/sl->flash_pgsz)); + (unsigned int)(off / sl->flash_pgsz), + (unsigned int)(len / sl->flash_pgsz)); fflush(stdout); } - write_uint32((unsigned char*) &data, *(uint32_t*) (base + off)); - stlink_write_debug32(sl, addr + (uint32_t) off, data); + write_uint32((unsigned char*)&data, *(uint32_t*)(base + off)); + stlink_write_debug32(sl, addr + (uint32_t)off, data); - /* wait for sr.busy to be cleared */ + // wait for sr.busy to be cleared do { stlink_read_debug32(sl, flash_regs_base + FLASH_SR_OFF, &val); } while ((val & (1 << 0)) != 0); - /* todo: check redo write operation */ - + // TODO: check redo write operation } + fprintf(stdout, "\n"); - /* reset lock bits */ + // reset lock bits stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); val |= (1 << 0) | (1 << 1) | (1 << 2); stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); - } else if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || (sl->flash_type == STLINK_FLASH_TYPE_F1_XL)) { + } else if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || + (sl->flash_type == STLINK_FLASH_TYPE_F1_XL)) { ILOG("Starting Flash write for VL/F0/F3/F1_XL core id\n"); - /* flash loader initialization */ + + // flash loader initialisation if (stlink_flash_loader_init(sl, &fl) == -1) { ELOG("stlink_flash_loader_init() == -1\n"); - return -1; + return(-1); } int write_block_count = 0; + for (off = 0; off < len; off += sl->flash_pgsz) { - /* adjust last write size */ + // adjust last write size size_t size = sl->flash_pgsz; - if ((off + sl->flash_pgsz) > len) size = len - off; - /* unlock and set programming mode */ + if ((off + sl->flash_pgsz) > len) { size = len - off; } + + // unlock and set programming mode unlock_flash_if(sl); - if (sl->flash_type != STLINK_FLASH_TYPE_F1_XL) { - set_flash_cr_pg(sl); - } + + if (sl->flash_type != STLINK_FLASH_TYPE_F1_XL) { set_flash_cr_pg(sl); } + DLOG("Finished unlocking flash, running loader!\n"); - if (stlink_flash_loader_run(sl, &fl, addr + (uint32_t) off, base + off, size) == -1) { + + if (stlink_flash_loader_run(sl, &fl, addr + (uint32_t)off, base + off, size) == -1) { ELOG("stlink_flash_loader_run(%#zx) failed! == -1\n", addr + off); - return -1; + return(-1); } + lock_flash(sl); + if (sl->verbose >= 1) { - /* show progress. writing procedure is slow - and previous errors are misleading */ - fprintf(stdout, "\r%3u/%lu pages written", ++write_block_count, (unsigned long)((len+sl->flash_pgsz-1)/sl->flash_pgsz)); + // show progress; writing procedure is slow and previous errors are misleading + fprintf(stdout, "\r%3u/%lu pages written", ++write_block_count, + (unsigned long)((len + sl->flash_pgsz - 1) / sl->flash_pgsz)); fflush(stdout); } } + fprintf(stdout, "\n"); } else { ELOG("unknown coreid, not sure how to write: %x\n", sl->core_id); - return -1; + return(-1); } - return stlink_verify_write_flash(sl, addr, base, len); + return(stlink_verify_write_flash(sl, addr, base, len)); } -// note: length not checked +// TODO: length not checked static uint8_t stlink_parse_hex(const char* hex) { uint8_t d[2]; + for (int i = 0; i < 2; ++i) { char c = *(hex + i); - if (c >= '0' && c <= '9') d[i] = c - '0'; - else if (c >= 'A' && c <= 'F') d[i] = c - 'A' + 10; - else if (c >= 'a' && c <= 'f') d[i] = c - 'a' + 10; - else return 0; // error + + if (c >= '0' && c <= '9') { + d[i] = c - '0'; + } else if (c >= 'A' && c <= 'F') { + d[i] = c - 'A' + 10; + } else if (c >= 'a' && c <= 'f') { + d[i] = c - 'a' + 10; + } else { + return(0); // error + } } - return (d[0] << 4) | (d[1]); + + return((d[0] << 4) | (d[1])); } -int stlink_parse_ihex(const char* path, uint8_t erased_pattern, uint8_t * * mem, size_t * size, uint32_t * begin) { +int stlink_parse_ihex(const char* path, uint8_t erased_pattern, uint8_t * * mem, size_t * size, + uint32_t * begin) { int res = 0; *begin = UINT32_MAX; uint8_t* data = NULL; @@ -2764,6 +2831,7 @@ int stlink_parse_ihex(const char* path, uint8_t erased_pattern, uint8_t * * mem, *size = (end - *begin) + 1; data = calloc(*size, 1); // use calloc to get NULL if out of memory + if (!data) { ELOG("Cannot allocate %d bytes\n", *size); res = -1; @@ -2774,6 +2842,7 @@ int stlink_parse_ihex(const char* path, uint8_t erased_pattern, uint8_t * * mem, } FILE* file = fopen(path, "r"); + if (!file) { ELOG("Cannot open file\n"); res = -1; @@ -2781,10 +2850,11 @@ int stlink_parse_ihex(const char* path, uint8_t erased_pattern, uint8_t * * mem, } uint32_t lba = 0; + char line[1 + 5 * 2 + 255 * 2 + 2]; - char line[1 + 5*2 + 255*2 + 2]; while (fgets(line, sizeof(line), file)) { - if (line[0] == '\n' || line[0] == '\r') continue; // skip empty lines + if (line[0] == '\n' || line[0] == '\r') { continue; } // skip empty lines + if (line[0] != ':') { // no marker - wrong file format ELOG("Wrong file format - no marker\n"); res = -1; @@ -2792,18 +2862,19 @@ int stlink_parse_ihex(const char* path, uint8_t erased_pattern, uint8_t * * mem, } size_t l = strlen(line); - while (l > 0 && (line[l-1] == '\n' || line[l-1] == '\r')) --l; // trim EoL - if ((l < 11) || (l == (sizeof(line)-1))) { // line too short or long - wrong file format + + while (l > 0 && (line[l - 1] == '\n' || line[l - 1] == '\r')) { --l; } // trim EoL + + if ((l < 11) || (l == (sizeof(line) - 1))) { // line too short or long - wrong file format ELOG("Wrong file format - wrong line length\n"); res = -1; break; } - // check sum - uint8_t chksum = 0; - for (size_t i = 1; i < l; i += 2) { - chksum += stlink_parse_hex(line + i); - } + uint8_t chksum = 0; // check sum + + for (size_t i = 1; i < l; i += 2) { chksum += stlink_parse_hex(line + i); } + if (chksum != 0) { ELOG("Wrong file format - checksum mismatch\n"); res = -1; @@ -2811,64 +2882,61 @@ int stlink_parse_ihex(const char* path, uint8_t erased_pattern, uint8_t * * mem, } uint8_t reclen = stlink_parse_hex(line + 1); - if (((uint32_t)reclen + 5)*2 + 1 != l) { + + if (((uint32_t)reclen + 5) * 2 + 1 != l) { ELOG("Wrong file format - record length mismatch\n"); res = -1; break; } - uint16_t offset = ((uint16_t)stlink_parse_hex(line + 3) << 8) | ((uint16_t)stlink_parse_hex(line + 5)); - uint8_t rectype = stlink_parse_hex(line + 7); - - switch(rectype) { - case 0: // data - if (scan == 0) { - uint32_t b = lba + offset; - uint32_t e = b + reclen - 1; - if (b < *begin) *begin = b; - if (e > end) end = e; - } - else { - for (uint8_t i = 0; i < reclen; ++i) { - uint8_t b = stlink_parse_hex(line + 9 + i*2); - uint32_t addr = lba + offset + i; - if (addr >= *begin && addr <= end) { - data[addr - *begin] = b; - } - } - } - break; + uint16_t offset = ((uint16_t)stlink_parse_hex(line + 3) << 8) | + ((uint16_t)stlink_parse_hex(line + 5)); + uint8_t rectype = stlink_parse_hex(line + 7); - case 1: // EoF - eof_found = true; - break; + switch (rectype) { + case 0: /* Data */ + if (scan == 0) { + uint32_t b = lba + offset; + uint32_t e = b + reclen - 1; - case 2: // Extended Segment Address, unexpected - res = -1; - break; + if (b < *begin) { *begin = b; } - case 3: // Start Segment Address, unexpected - res = -1; - break; + if (e > end) { end = e; } + } else { + for (uint8_t i = 0; i < reclen; ++i) { + uint8_t b = stlink_parse_hex(line + 9 + i * 2); + uint32_t addr = lba + offset + i; - case 4: // Extended Linear Address - if (reclen == 2) { - lba = ((uint32_t)stlink_parse_hex(line + 9) << 24) | ((uint32_t)stlink_parse_hex(line + 11) << 16); - } - else { - ELOG("Wrong file format - wrong LBA length\n"); - res = -1; + if (addr >= *begin && addr <= end) { data[addr - *begin] = b; } } - break; - - case 5: // Start Linear Address - expected, but ignore - break; - - default: - ELOG("Wrong file format - unexpected record type %d\n", rectype); + } + break; + case 1: /* EoF */ + eof_found = true; + break; + case 2: /* Extended Segment Address, unexpected */ + res = -1; + break; + case 3: /* Start Segment Address, unexpected */ + res = -1; + break; + case 4: /* Extended Linear Address */ + if (reclen == 2) { + lba = ((uint32_t)stlink_parse_hex(line + 9) << 24) | + ((uint32_t)stlink_parse_hex(line + 11) << 16); + } else { + ELOG("Wrong file format - wrong LBA length\n"); res = -1; + } + break; + case 5: /* Start Linear Address - expected, but ignore */ + break; + default: + ELOG("Wrong file format - unexpected record type %d\n", rectype); + res = -1; } - if (res != 0) break; + + if (res != 0) { break; } } fclose(file); @@ -2876,55 +2944,56 @@ int stlink_parse_ihex(const char* path, uint8_t erased_pattern, uint8_t * * mem, if (res == 0) { *mem = data; - } - else { + } else { free(data); } - return res; + return(res); } uint8_t stlink_get_erased_pattern(stlink_t *sl) { - if (sl->flash_type == STLINK_FLASH_TYPE_L0) - return 0x00; - else - return 0xff; + if (sl->flash_type == STLINK_FLASH_TYPE_L0) { + return(0x00); + } else { + return(0xff); + } } int stlink_mwrite_flash(stlink_t *sl, uint8_t* data, uint32_t length, stm32_addr_t addr) { - /* write the block in flash at addr */ + /* Write the block in flash at addr */ int err; unsigned int num_empty, idx; uint8_t erased_pattern = stlink_get_erased_pattern(sl); /* - * This optimization may cause unexpected garbage data remaining - * Turned off by default + * This optimisation may cause unexpected garbage data remaining. + * Therfore it is turned off by default. */ if (sl->opt) { idx = (unsigned int)length; - for (num_empty = 0; num_empty != length; ++num_empty) { - if (data[--idx] != erased_pattern) { - break; - } - } - /* Round down to words */ - num_empty -= (num_empty & 3); + + for (num_empty = 0; num_empty != length; ++num_empty) + if (data[--idx] != erased_pattern) { break; } + + num_empty -= (num_empty & 3); // Round down to words + if (num_empty != 0) { ILOG("Ignoring %d bytes of 0x%02x at end of file\n", num_empty, erased_pattern); } } else { num_empty = 0; } + /* - * TODO: investigate: - * a kind of weird behaviour here: - * if the file is identified to be all-empty and four-bytes aligned, - * still flash the whole file even if ignoring message is printed + * TODO: investigate a kind of weird behaviour here: + * If the file is identified to be all-empty and four-bytes aligned, + * still flash the whole file even if ignoring message is printed. */ - err = stlink_write_flash(sl, addr, data, (num_empty == length) ? (uint32_t) length : (uint32_t) length - num_empty, num_empty == length); + err = stlink_write_flash(sl, addr, data, + (num_empty == length) ? (uint32_t)length : (uint32_t)length - num_empty, + num_empty == length); stlink_fwrite_finalize(sl, addr); - return err; + return(err); } /** @@ -2935,7 +3004,7 @@ int stlink_mwrite_flash(stlink_t *sl, uint8_t* data, uint32_t length, stm32_addr * @return 0 on success, -ve on failure. */ int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr) { - /* write the file in flash at addr */ + /* Write the file in flash at addr */ int err; unsigned int num_empty, idx; uint8_t erased_pattern = stlink_get_erased_pattern(sl); @@ -2943,7 +3012,7 @@ int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr) { if (map_file(&mf, path) == -1) { ELOG("map_file() == -1\n"); - return -1; + return(-1); } printf("file %s ", path); @@ -2951,30 +3020,32 @@ int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr) { stlink_checksum(&mf); if (sl->opt) { - idx = (unsigned int) mf.len; + idx = (unsigned int)mf.len; + for (num_empty = 0; num_empty != mf.len; ++num_empty) { - if (mf.base[--idx] != erased_pattern) { - break; - } + if (mf.base[--idx] != erased_pattern) { break; } } - /* Round down to words */ - num_empty -= (num_empty & 3); + + num_empty -= (num_empty & 3); // round down to words + if (num_empty != 0) { ILOG("Ignoring %d bytes of 0x%02x at end of file\n", num_empty, erased_pattern); } } else { num_empty = 0; } + /* - * TODO: investigate: - * a kind of weird behaviour here: - * if the file is identified to be all-empty and four-bytes aligned, - * still flash the whole file even if ignoring message is printed + * TODO: investigate a kind of weird behaviour here: + * If the file is identified to be all-empty and four-bytes aligned, + * still flash the whole file even if ignoring message is printed. */ - err = stlink_write_flash(sl, addr, mf.base, (num_empty == mf.len) ? (uint32_t) mf.len : (uint32_t) mf.len - num_empty, num_empty == mf.len); + err = stlink_write_flash(sl, addr, mf.base, + (num_empty == mf.len) ? (uint32_t)mf.len : (uint32_t)mf.len - num_empty, + num_empty == mf.len); stlink_fwrite_finalize(sl, addr); unmap_file(&mf); - return err; + return(err); } /** @@ -2984,20 +3055,19 @@ int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr) { * @param base option bytes to write * @return 0 on success, -ve on failure. */ -static int stlink_write_option_bytes_gx(stlink_t *sl, uint8_t* base, stm32_addr_t addr, uint32_t len) { - +static int stlink_write_option_bytes_gx( + stlink_t *sl, uint8_t* base, stm32_addr_t addr, uint32_t len) { + /* Write options bytes */ uint32_t val; int ret = 0; - (void) len; - - /* Write options bytes */ + (void)len; uint32_t data; - write_uint32((unsigned char*) &data, *(uint32_t*) (base)); - WLOG("Writing option bytes %#10x to %#10x\n", data, addr); + write_uint32((unsigned char*)&data, *(uint32_t*)(base)); + WLOG("Writing option bytes %#10x to %#10x\n", data, addr); stlink_write_debug32(sl, STM32Gx_FLASH_OPTR, data); - /* Set Options Start bit */ + // Set Options Start bit stlink_read_debug32(sl, STM32Gx_FLASH_CR, &val); val |= (1 << STM32Gx_FLASH_CR_OPTSTRT); stlink_write_debug32(sl, STM32Gx_FLASH_CR, val); @@ -3006,12 +3076,12 @@ static int stlink_write_option_bytes_gx(stlink_t *sl, uint8_t* base, stm32_addr_ ret = check_flash_error(sl); - /* Reload options */ + // Reload options stlink_read_debug32(sl, STM32Gx_FLASH_CR, &val); val |= (1 << STM32Gx_FLASH_CR_OBL_LAUNCH); stlink_write_debug32(sl, STM32Gx_FLASH_CR, val); - return ret; + return(ret); } /** @@ -3021,38 +3091,36 @@ static int stlink_write_option_bytes_gx(stlink_t *sl, uint8_t* base, stm32_addr_ * @param base option bytes to write * @return 0 on success, -ve on failure. */ -static int stlink_write_option_bytes_l0(stlink_t *sl, uint8_t* base, stm32_addr_t addr, uint32_t len) { +static int stlink_write_option_bytes_l0( + stlink_t *sl, uint8_t* base, stm32_addr_t addr, uint32_t len) { uint32_t flash_base = get_stm32l0_flash_base(sl); uint32_t val; uint32_t data; int ret = 0; - /* Clear errors */ + // Clear errors stlink_write_debug32(sl, flash_base + FLASH_SR_OFF, STM32L0_FLASH_REGS_ADDR); while (len != 0) { - /* Write options bytes */ - write_uint32((unsigned char*) &data, *(uint32_t*) (base)); + write_uint32((unsigned char*)&data, *(uint32_t*)(base)); // write options bytes WLOG("Writing option bytes %#10x to %#10x\n", data, addr); stlink_write_debug32(sl, addr, data); - wait_flash_busy(sl); - if ((ret = check_flash_error(sl))) - break; + if ((ret = check_flash_error(sl))) { break; } - len-=4; - addr+=4; - base+=4; + len -= 4; + addr += 4; + base += 4; } - /* Reload options */ + // Reload options stlink_read_debug32(sl, flash_base + FLASH_PECR_OFF, &val); val |= (1 << STM32L0_FLASH_OBL_LAUNCH); stlink_write_debug32(sl, flash_base + FLASH_PECR_OFF, val); - return ret; + return(ret); } /** @@ -3062,36 +3130,34 @@ static int stlink_write_option_bytes_l0(stlink_t *sl, uint8_t* base, stm32_addr_ * @param base option bytes to write * @return 0 on success, -ve on failure. */ -static int stlink_write_option_bytes_l4(stlink_t *sl, uint8_t* base, stm32_addr_t addr, uint32_t len) { +static int stlink_write_option_bytes_l4( + stlink_t *sl, uint8_t* base, stm32_addr_t addr, uint32_t len) { uint32_t val; int ret = 0; + (void)addr; + (void)len; - (void) addr; - (void) len; - - /* Write options bytes */ + // write options bytes uint32_t data; - write_uint32((unsigned char*) &data, *(uint32_t*) (base)); + write_uint32((unsigned char*)&data, *(uint32_t*)(base)); WLOG("Writing option bytes 0x%04x\n", data); stlink_write_debug32(sl, STM32L4_FLASH_OPTR, data); - /* Set Options Start bit */ + // set options start bit stlink_read_debug32(sl, STM32L4_FLASH_CR, &val); val |= (1 << STM32L4_FLASH_CR_OPTSTRT); stlink_write_debug32(sl, STM32L4_FLASH_CR, val); - /* Wait for 'busy' bit in FLASH_SR to clear. */ wait_flash_busy(sl); - ret = check_flash_error(sl); - /* apply options bytes immediate */ + // apply options bytes immediate stlink_read_debug32(sl, STM32L4_FLASH_CR, &val); val |= (1 << STM32L4_FLASH_CR_OBL_LAUNCH); stlink_write_debug32(sl, STM32L4_FLASH_CR, val); - return ret; + return(ret); } @@ -3101,25 +3167,24 @@ static int stlink_write_option_bytes_l4(stlink_t *sl, uint8_t* base, stm32_addr_ * @param option_byte value to write * @return 0 on success, -ve on failure. */ -static int stlink_write_option_bytes_f4(stlink_t *sl, uint8_t* base, stm32_addr_t addr, uint32_t len) { +static int stlink_write_option_bytes_f4( + stlink_t *sl, uint8_t* base, stm32_addr_t addr, uint32_t len) { uint32_t option_byte; int ret = 0; + (void)addr; + (void)len; - (void) addr; - (void) len; - - write_uint32((unsigned char*) &option_byte, *(uint32_t*) (base)); + write_uint32((unsigned char*)&option_byte, *(uint32_t*)(base)); - /* write option byte, ensuring we dont lock opt, and set strt bit */ - stlink_write_debug32(sl, FLASH_F4_OPTCR, (option_byte & ~(1 << FLASH_F4_OPTCR_LOCK)) | (1 << FLASH_F4_OPTCR_START)); + // write option byte, ensuring we dont lock opt, and set strt bit + stlink_write_debug32(sl, FLASH_F4_OPTCR, + (option_byte & ~(1 << FLASH_F4_OPTCR_LOCK)) | (1 << FLASH_F4_OPTCR_START)); wait_flash_busy(sl); - ret = check_flash_error(sl); - /* option bytes are reloaded at reset only, no obl. */ - - return ret; + // option bytes are reloaded at reset only, no obl. */ + return(ret); } /** @@ -3129,7 +3194,7 @@ static int stlink_write_option_bytes_f4(stlink_t *sl, uint8_t* base, stm32_addr_ * @return 0 on success, -ve on failure. */ int stlink_read_option_bytes_Gx(stlink_t *sl, uint32_t* option_byte) { - return stlink_read_debug32(sl, STM32Gx_FLASH_OPTR, option_byte); + return(stlink_read_debug32(sl, STM32Gx_FLASH_OPTR, option_byte)); } /** @@ -3139,7 +3204,7 @@ int stlink_read_option_bytes_Gx(stlink_t *sl, uint32_t* option_byte) { * @return 0 on success, -ve on failure. */ int stlink_read_option_bytes_f2(stlink_t *sl, uint32_t* option_byte) { - return stlink_read_debug32(sl, FLASH_F2_OPT_CR, option_byte); + return(stlink_read_debug32(sl, FLASH_F2_OPT_CR, option_byte)); } /** @@ -3149,16 +3214,16 @@ int stlink_read_option_bytes_f2(stlink_t *sl, uint32_t* option_byte) { * @return 0 on success, -ve on failure. */ int stlink_read_option_bytes_f4(stlink_t *sl, uint32_t* option_byte) { - return stlink_read_debug32(sl, FLASH_F4_OPTCR, option_byte); + return(stlink_read_debug32(sl, FLASH_F4_OPTCR, option_byte)); } /** * Read first option bytes -* @param sl -* @param option_byte option value -* @return 0 on success, -ve on failure. -*/ + * @param sl + * @param option_byte option value + * @return 0 on success, -ve on failure. + */ int stlink_read_option_bytes_generic(stlink_t *sl, uint32_t* option_byte) { - return stlink_read_debug32(sl, sl->option_base, option_byte); + return(stlink_read_debug32(sl, sl->option_base, option_byte)); } /** @@ -3170,21 +3235,21 @@ int stlink_read_option_bytes_generic(stlink_t *sl, uint32_t* option_byte) { int stlink_read_option_bytes32(stlink_t *sl, uint32_t* option_byte) { if (sl->option_base == 0) { ELOG("Option bytes read is currently not supported for connected chip\n"); - return -1; + return(-1); } switch (sl->chip_id) { - case STLINK_CHIPID_STM32_F2: - return stlink_read_option_bytes_f2(sl, option_byte); - case STLINK_CHIPID_STM32_F446: - return stlink_read_option_bytes_f4(sl, option_byte); - case STLINK_CHIPID_STM32_G0_CAT1: - case STLINK_CHIPID_STM32_G0_CAT2: - case STLINK_CHIPID_STM32_G4_CAT2: - case STLINK_CHIPID_STM32_G4_CAT3: - return stlink_read_option_bytes_Gx(sl, option_byte); - default: - return stlink_read_option_bytes_generic(sl, option_byte); + case STLINK_CHIPID_STM32_F2: + return(stlink_read_option_bytes_f2(sl, option_byte)); + case STLINK_CHIPID_STM32_F446: + return(stlink_read_option_bytes_f4(sl, option_byte)); + case STLINK_CHIPID_STM32_G0_CAT1: + case STLINK_CHIPID_STM32_G0_CAT2: + case STLINK_CHIPID_STM32_G4_CAT2: + case STLINK_CHIPID_STM32_G4_CAT3: + return(stlink_read_option_bytes_Gx(sl, option_byte)); + default: + return(stlink_read_option_bytes_generic(sl, option_byte)); } } @@ -3196,7 +3261,7 @@ int stlink_read_option_bytes32(stlink_t *sl, uint32_t* option_byte) { */ int stlink_write_option_bytes32(stlink_t *sl, uint32_t option_byte) { WLOG("About to write option byte %#10x to target.\n", option_byte); - return stlink_write_option_bytes(sl, sl->option_base, (uint8_t *) &option_byte, 4); + return(stlink_write_option_bytes(sl, sl->option_base, (uint8_t *)&option_byte, 4)); } /** @@ -3211,60 +3276,60 @@ int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t* base, ui if (sl->option_base == 0) { ELOG("Option bytes writing is currently not supported for connected chip\n"); - return -1; + return(-1); } if ((addr < sl->option_base) || addr > sl->option_base + sl->option_size) { ELOG("Option bytes start address out of Option bytes range\n"); - return -1; + return(-1); } if (addr + len > sl->option_base + sl->option_size) { ELOG("Option bytes data too long\n"); - return -1; + return(-1); } wait_flash_busy(sl); if (unlock_flash_if(sl)) { ELOG("Flash unlock failed! System reset required to be able to unlock it again!\n"); - return -1; + return(-1); } if (unlock_flash_option_if(sl)) { ELOG("Flash option unlock failed!\n"); - return -1; + return(-1); } switch (sl->flash_type) { - case STLINK_FLASH_TYPE_F4: - ret = stlink_write_option_bytes_f4(sl, base, addr, len); - break; - case STLINK_FLASH_TYPE_L0: - ret = stlink_write_option_bytes_l0(sl, base, addr, len); - break; - case STLINK_FLASH_TYPE_L4: - ret = stlink_write_option_bytes_l4(sl, base, addr, len); - break; - case STLINK_FLASH_TYPE_G0: - case STLINK_FLASH_TYPE_G4: - ret = stlink_write_option_bytes_gx(sl, base, addr, len); - break; - default: - ELOG("Option bytes writing is currently not implemented for connected chip\n"); - break; + case STLINK_FLASH_TYPE_F4: + ret = stlink_write_option_bytes_f4(sl, base, addr, len); + break; + case STLINK_FLASH_TYPE_L0: + ret = stlink_write_option_bytes_l0(sl, base, addr, len); + break; + case STLINK_FLASH_TYPE_L4: + ret = stlink_write_option_bytes_l4(sl, base, addr, len); + break; + case STLINK_FLASH_TYPE_G0: + case STLINK_FLASH_TYPE_G4: + ret = stlink_write_option_bytes_gx(sl, base, addr, len); + break; + default: + ELOG("Option bytes writing is currently not implemented for connected chip\n"); + break; } - if (ret) + if (ret) { ELOG("Flash option write failed!\n"); - else - ILOG("Wrote %d option bytes to %#010x!\n", len, addr); + } else { + ILOG("Wrote %d option bytes to %#010x!\n", len, addr); + } - /* Re-lock flash. */ lock_flash_option(sl); lock_flash(sl); - return ret; + return(ret); } /** @@ -3275,21 +3340,22 @@ int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t* base, ui * @return 0 on success, -ve on failure. */ int stlink_fwrite_option_bytes(stlink_t *sl, const char* path, stm32_addr_t addr) { - /* write the file in flash at addr */ + /* Write the file in flash at addr */ int err; mapped_file_t mf = MAPPED_FILE_INITIALIZER; if (map_file(&mf, path) == -1) { ELOG("map_file() == -1\n"); - return -1; + return(-1); } printf("file %s ", path); md5_calculate(&mf); stlink_checksum(&mf); - err = stlink_write_option_bytes(sl, addr, mf.base, (uint32_t) mf.len); + err = stlink_write_option_bytes(sl, addr, mf.base, (uint32_t)mf.len); stlink_fwrite_finalize(sl, addr); unmap_file(&mf); - return err; + + return(err); } diff --git a/src/reg.h b/src/reg.h deleted file mode 100644 index 765ac9525..000000000 --- a/src/reg.h +++ /dev/null @@ -1,20 +0,0 @@ -#ifndef STLINK_REG_H_ -#define STLINK_REG_H_ - -#define STLINK_REG_CM3_CPUID 0xE000ED00 -#define STLINK_REG_CM3_FP_CTRL 0xE0002000 -#define STLINK_REG_CM3_FP_COMP0 0xE0002008 - -/* Cortex™-M3 Technical Reference Manual */ -/* Debug Halting Control and Status Register */ -#define STLINK_REG_DHCSR 0xe000edf0 -#define STLINK_REG_DHCSR_DBGKEY 0xa05f0000 -#define STLINK_REG_DCRSR 0xe000edf4 -#define STLINK_REG_DCRDR 0xe000edf8 - -/* Application Interrupt and Reset Control Register */ -#define STLINK_REG_AIRCR 0xe000ed0c -#define STLINK_REG_AIRCR_VECTKEY 0x05fa0000 -#define STLINK_REG_AIRCR_SYSRESETREQ 0x00000004 - -#endif /* STLINK_REG_H_ */ diff --git a/src/st-flash/flash.c b/src/st-flash/flash.c index fc62bcf15..43378965c 100644 --- a/src/st-flash/flash.c +++ b/src/st-flash/flash.c @@ -1,4 +1,4 @@ -/* simple wrapper around the stlink_flash_write function */ +/* Simple wrapper around the stlink_flash_write function */ // TODO - this should be done as just a simple flag to the st-util command line... @@ -16,8 +16,7 @@ static stlink_t *connected_stlink = NULL; static void cleanup(int signum) { (void)signum; - if (connected_stlink) { - /* Switch back to mass storage mode before closing. */ + if (connected_stlink) { // switch back to mass storage mode before closing stlink_run(connected_stlink); stlink_exit_debug_mode(connected_stlink); stlink_close(connected_stlink); @@ -26,8 +25,7 @@ static void cleanup(int signum) { exit(1); } -static void usage(void) -{ +static void usage(void) { puts("command line: ./st-flash [--debug] [--reset] [--opt] [--serial ] [--format ] [--flash=] [--freq=] {read|write} [addr] [size]"); puts("command line: ./st-flash [--debug] [--freq=] [--serial ] erase"); puts("command line: ./st-flash [--debug] [--freq=] [--serial ] reset"); @@ -39,37 +37,34 @@ static void usage(void) puts("example read option byte: ./st-flash --debug --reset --area=option read > option_byte"); } -int main(int ac, char** av) -{ +int main(int ac, char** av) { stlink_t* sl = NULL; struct flash_opts o; int err = -1; uint8_t * mem = NULL; o.size = 0; - if (flash_get_opts(&o, ac - 1, av + 1) == -1) - { + + if (flash_get_opts(&o, ac - 1, av + 1) == -1) { printf("invalid command line\n"); usage(); - return -1; + return(-1); } printf("st-flash %s\n", STLINK_VERSION); sl = stlink_open_usb(o.log_level, 1, (char *)o.serial, o.freq); - if (sl == NULL) { - return -1; - } + if (sl == NULL) { return(-1); } if (sl->flash_type == STLINK_FLASH_TYPE_UNKNOWN) { printf("Failed to connect to target\n"); - return -1; + return(-1); } if ( o.flash_size != 0u && o.flash_size != sl->flash_size ) { sl->flash_size = o.flash_size; - printf("Forcing flash size: --flash=0x%08X\n",(unsigned int)sl->flash_size); + printf("Forcing flash size: --flash=0x%08X\n", (unsigned int)sl->flash_size); } sl->verbose = o.log_level; @@ -94,7 +89,7 @@ int main(int ac, char** av) } } - if (o.reset){ + if (o.reset) { if (sl->version.stlink_v > 1) { if (stlink_jtag_reset(sl, 2)) { printf("Failed to reset JTAG\n"); @@ -108,19 +103,19 @@ int main(int ac, char** av) } } - // Disable DMA - Set All DMA CCR Registers to zero. - AKS 1/7/2013 - if (sl->chip_id == STLINK_CHIPID_STM32_F4) - { - memset(sl->q_buf,0,4); - for (int i=0;i<8;i++) { - stlink_write_mem32(sl,0x40026000+0x10+0x18*i,4); - stlink_write_mem32(sl,0x40026400+0x10+0x18*i,4); - stlink_write_mem32(sl,0x40026000+0x24+0x18*i,4); - stlink_write_mem32(sl,0x40026400+0x24+0x18*i,4); + // disable DMA - Set All DMA CCR Registers to zero. - AKS 1/7/2013 + if (sl->chip_id == STLINK_CHIPID_STM32_F4) { + memset(sl->q_buf, 0, 4); + + for (int i = 0; i < 8; i++) { + stlink_write_mem32(sl, 0x40026000 + 0x10 + 0x18 * i, 4); + stlink_write_mem32(sl, 0x40026400 + 0x10 + 0x18 * i, 4); + stlink_write_mem32(sl, 0x40026000 + 0x24 + 0x18 * i, 4); + stlink_write_mem32(sl, 0x40026400 + 0x24 + 0x18 * i, 4); } } - // Core must be halted to use RAM based flashloaders + // core must be halted to use RAM based flashloaders if (stlink_force_debug(sl)) { printf("Failed to halt the core\n"); goto on_error; @@ -131,77 +126,75 @@ int main(int ac, char** av) goto on_error; } - if (o.cmd == FLASH_CMD_WRITE) /* write */ - { + if (o.cmd == FLASH_CMD_WRITE) { // write size_t size = 0; + if (o.format == FLASH_FORMAT_IHEX) { err = stlink_parse_ihex(o.filename, stlink_get_erased_pattern(sl), &mem, &size, &o.addr); + if (err == -1) { printf("Cannot parse %s as Intel-HEX file\n", o.filename); goto on_error; } } + if ((o.addr >= sl->flash_base) && - (o.addr < sl->flash_base + sl->flash_size)) { - if (o.format == FLASH_FORMAT_IHEX) + (o.addr < sl->flash_base + sl->flash_size)) { + if (o.format == FLASH_FORMAT_IHEX) { err = stlink_mwrite_flash(sl, mem, (uint32_t)size, o.addr); - else + } else { err = stlink_fwrite_flash(sl, o.filename, o.addr); - if (err == -1) - { + } + + if (err == -1) { printf("stlink_fwrite_flash() == -1\n"); goto on_error; } - } - else if ((o.addr >= sl->sram_base) && - (o.addr < sl->sram_base + sl->sram_size)) { - if (o.format == FLASH_FORMAT_IHEX) + } else if ((o.addr >= sl->sram_base) && + (o.addr < sl->sram_base + sl->sram_size)) { + if (o.format == FLASH_FORMAT_IHEX) { err = stlink_mwrite_sram(sl, mem, (uint32_t)size, o.addr); - else + } else { err = stlink_fwrite_sram(sl, o.filename, o.addr); - if (err == -1) - { + } + + if (err == -1) { printf("stlink_fwrite_sram() == -1\n"); goto on_error; } - } - else if ((o.addr >= sl->option_base) && - (o.addr < sl->option_base + sl->option_size)) { + } else if ((o.addr >= sl->option_base) && + (o.addr < sl->option_base + sl->option_size)) { err = stlink_fwrite_option_bytes(sl, o.filename, o.addr); - if (err == -1) - { + + if (err == -1) { printf("stlink_fwrite_option_bytes() == -1\n"); goto on_error; } - } - else if (o.area == FLASH_OPTION_BYTES){ + } else if (o.area == FLASH_OPTION_BYTES) { if (o.val == 0) { printf("attempting to set option byte to 0, abort.\n"); goto on_error; - } + } err = stlink_write_option_bytes32(sl, o.val); - if (err == -1) - { + + if (err == -1) { printf("stlink_write_option_bytes32() == -1\n"); goto on_error; } - } - else { + } else { err = -1; printf("Unknown memory region\n"); goto on_error; } - } else if (o.cmd == FLASH_CMD_ERASE) - { + } else if (o.cmd == FLASH_CMD_ERASE) { err = stlink_erase_flash_mass(sl); - if (err == -1) - { + + if (err == -1) { printf("stlink_erase_flash_mass() == -1\n"); goto on_error; } - } else if (o.cmd == CMD_RESET) - { + } else if (o.cmd == CMD_RESET) { if (sl->version.stlink_v > 1) { if (stlink_jtag_reset(sl, 2)) { printf("Failed to reset JTAG\n"); @@ -213,49 +206,47 @@ int main(int ac, char** av) printf("Failed to reset device\n"); goto on_error; } - } - else /* read */ - { - if(o.area == FLASH_OPTION_BYTES){ - uint32_t option_byte; - err = stlink_read_option_bytes32(sl, &option_byte); - if (err == -1) { - printf("could not read option bytes (%d)\n", err); - goto on_error; - } else { - printf("%x\n",option_byte); + } else { // read + if (o.area == FLASH_OPTION_BYTES) { + uint32_t option_byte; + err = stlink_read_option_bytes32(sl, &option_byte); + + if (err == -1) { + printf("could not read option bytes (%d)\n", err); + goto on_error; + } else { + printf("%x\n", option_byte); } - }else{ + } else { if ((o.addr >= sl->flash_base) && (o.size == 0) && - (o.addr < sl->flash_base + sl->flash_size)){ + (o.addr < sl->flash_base + sl->flash_size)) { o.size = sl->flash_size; - } - else if ((o.addr >= sl->sram_base) && (o.size == 0) && - (o.addr < sl->sram_base + sl->sram_size)){ + } else if ((o.addr >= sl->sram_base) && (o.size == 0) && + (o.addr < sl->sram_base + sl->sram_size)) { o.size = sl->sram_size; } + err = stlink_fread(sl, o.filename, o.format == FLASH_FORMAT_IHEX, o.addr, o.size); - if (err == -1) - { + if (err == -1) { printf("stlink_fread() == -1\n"); goto on_error; } } } - if (o.reset){ - if (sl->version.stlink_v > 1) stlink_jtag_reset(sl, 2); + if (o.reset) { + if (sl->version.stlink_v > 1) { stlink_jtag_reset(sl, 2); } + stlink_reset(sl); } - /* success */ - err = 0; + err = 0; // success on_error: stlink_exit_debug_mode(sl); stlink_close(sl); free(mem); - return err; + return(err); } diff --git a/src/st-flash/flash.h b/src/st-flash/flash.h index 3a4dc3ec4..0b7555188 100644 --- a/src/st-flash/flash.h +++ b/src/st-flash/flash.h @@ -11,9 +11,8 @@ enum flash_cmd {FLASH_CMD_NONE = 0, FLASH_CMD_WRITE = 1, FLASH_CMD_READ = 2, FLASH_CMD_ERASE = 3, CMD_RESET = 4}; enum flash_format {FLASH_FORMAT_BINARY = 0, FLASH_FORMAT_IHEX = 1}; -enum flash_area {FLASH_MAIN_MEMORY = 0, FLASH_SYSTEM_MEMORY = 1,FLASH_OTP = 2, FLASH_OPTION_BYTES = 3}; -struct flash_opts -{ +enum flash_area {FLASH_MAIN_MEMORY = 0, FLASH_SYSTEM_MEMORY = 1, FLASH_OTP = 2, FLASH_OPTION_BYTES = 3}; +struct flash_opts { enum flash_cmd cmd; uint8_t serial[STLINK_SERIAL_MAX_SIZE]; const char* filename; @@ -24,9 +23,9 @@ struct flash_opts enum flash_format format; enum flash_area area; uint32_t val; - size_t flash_size; /* --flash=n[k][m] */ - int opt; /* enable empty tail data drop optimization */ - int freq; /* --freq=n[k][m] frequency of JTAG/SWD */ + size_t flash_size; // --flash=n[k][m] + int opt; // enable empty tail data drop optimization + int freq; // --freq=n[k][m] frequency of JTAG/SWD bool connect_under_reset; }; diff --git a/src/st-flash/flash_opts.c b/src/st-flash/flash_opts.c index 9d8d3225b..6d1940675 100644 --- a/src/st-flash/flash_opts.c +++ b/src/st-flash/flash_opts.c @@ -6,7 +6,8 @@ static bool starts_with(const char * str, const char * prefix) { size_t n = strlen(prefix); - if (strlen(str) < n) return false; + + if (strlen(str) < n) { return(false); } return (0 == strncmp(str, prefix, n)); } @@ -19,37 +20,28 @@ static int get_long_integer_from_char_array (const char *const str, uint64_t *re uint64_t value; char *tail; - // hexadecimal - if (starts_with (str, "0x") || starts_with (str, "0X")) { + if (starts_with (str, "0x") || starts_with (str, "0X")) { // hexadecimal value = strtoul (str + 2, &tail, 16); - } - // binary - else if (starts_with (str, "0b") || starts_with (str, "0B")) { + } else if (starts_with (str, "0b") || starts_with (str, "0B")) { // binary value = strtoul (str + 2, &tail, 2); - } - // octal - else if (starts_with (str, "0")) { + } else if (starts_with (str, "0")) { // octal value = strtoul (str + 1, &tail, 8); - } - // decimal - else { + } else { // decimal value = strtoul (str, &tail, 10); } if (((tail[0] == 'k') || (tail[0] == 'K')) && (tail[1] == '\0')) { value = value * 1024; - } - else if (((tail[0] == 'm') || (tail[0] == 'M')) && (tail[1] == '\0')) { + } else if (((tail[0] == 'm') || (tail[0] == 'M')) && (tail[1] == '\0')) { value = value * 1024 * 1024; + } else if (tail[0] == '\0') { + /* value not changed */ + } else { + return(-1); } - else if (tail[0] == '\0') { - // value not change - } - else { - return -1; - } + *read_value = value; - return 0; + return(0); } // support positive integer from 0 to UINT32_MAX @@ -59,28 +51,26 @@ static int get_long_integer_from_char_array (const char *const str, uint64_t *re static int get_integer_from_char_array (const char *const str, uint32_t *read_value) { uint64_t value; int result = get_long_integer_from_char_array (str, &value); + if (result != 0) { - return result; - } - else if (value > UINT32_MAX) { - fprintf (stderr, "*** Error: Integer greater than UINT32_MAX, \ -cannot convert to int32_t\n"); - return -1; - } - else { + return(result); + } else if (value > UINT32_MAX) { + fprintf (stderr, "*** Error: Integer greater than UINT32_MAX, cannot convert to int32_t\n"); + return(-1); + } else { *read_value = (uint32_t)value; - return 0; + return(0); } } static int invalid_args(const char *expected) { fprintf(stderr, "*** Error: Expected args for this command: %s\n", expected); - return -1; + return(-1); } static int bad_arg(const char *arg) { fprintf(stderr, "*** Error: Invalid value for %s\n", arg); - return -1; + return(-1); } int flash_get_opts(struct flash_opts* o, int ac, char** av) { @@ -91,170 +81,177 @@ int flash_get_opts(struct flash_opts* o, int ac, char** av) { // options int result; + while (ac >= 1) { if (strcmp(av[0], "--version") == 0) { printf("v%s\n", STLINK_VERSION); exit(EXIT_SUCCESS); - } - else if (strcmp(av[0], "--debug") == 0) { + } else if (strcmp(av[0], "--debug") == 0) { o->log_level = DEBUG_LOG_LEVEL; - } - else if (strcmp(av[0], "--opt") == 0) { + } else if (strcmp(av[0], "--opt") == 0) { o->opt = ENABLE_OPT; - } - else if (strcmp(av[0], "--reset") == 0) { + } else if (strcmp(av[0], "--reset") == 0) { o->reset = 1; - } - else if (strcmp(av[0], "--serial") == 0 || starts_with(av[0], "--serial=")) { + } else if (strcmp(av[0], "--serial") == 0 || starts_with(av[0], "--serial=")) { const char * serial; + if (strcmp(av[0], "--serial") == 0) { ac--; av++; - if (ac < 1) return -1; + + if (ac < 1) { return(-1); } + serial = av[0]; - } - else { + } else { serial = av[0] + strlen("--serial="); } - /** @todo This is not really portable, as strlen really returns size_t we need to obey and not cast it to a signed type. */ + + /** @todo This is not really portable, as strlen really returns size_t we need to obey + and not cast it to a signed type. */ int j = (int)strlen(serial); - int length = j / 2; // the length of the destination-array - if (j % 2 != 0) return -1; + int length = j / 2; // the length of the destination-array + + if (j % 2 != 0) { return(-1); } + for (size_t k = 0; j >= 0 && k < sizeof(o->serial); ++k, j -= 2) { char buffer[3] = {0}; memcpy(buffer, serial + j, 2); o->serial[length - k] = (uint8_t)strtol(buffer, NULL, 16); } - } - else if (strcmp(av[0], "--area") == 0 || starts_with(av[0], "--area=")) { + } else if (strcmp(av[0], "--area") == 0 || starts_with(av[0], "--area=")) { const char * area; + if (strcmp(av[0], "--area") == 0) { ac--; av++; - if (ac < 1) return -1; + + if (ac < 1) { return(-1); } + area = av[0]; - } - else { + } else { area = av[0] + strlen("--area="); } - if (strcmp(area, "main") == 0) + + if (strcmp(area, "main") == 0) { o->area = FLASH_MAIN_MEMORY; - else if (strcmp(area, "system") == 0) + } else if (strcmp(area, "system") == 0) { o->area = FLASH_SYSTEM_MEMORY; - else if (strcmp(area, "otp") == 0) + } else if (strcmp(area, "otp") == 0) { o->area = FLASH_OTP; - else if (strcmp(area, "option") == 0) + } else if (strcmp(area, "option") == 0) { o->area = FLASH_OPTION_BYTES; - else - return -1; + } else { + return(-1); + } - } - else if (strcmp(av[0], "--freq") == 0 || starts_with(av[0], "--freq=")) { + } else if (strcmp(av[0], "--freq") == 0 || starts_with(av[0], "--freq=")) { const char* freq; + if (strcmp(av[0], "--freq") == 0) { ac--; av++; - if (ac < 1) return -1; + + if (ac < 1) { + return(-1); + } + freq = av[0]; - } - else { + } else { freq = av[0] + strlen("--freq="); } + if (strcmp(freq, "5K") == 0 || strcmp(freq, "5k") == 0) { o->freq = 5; - } - else if (strcmp(freq, "15K") == 0 || strcmp(freq, "15k") == 0) { + } else if (strcmp(freq, "15K") == 0 || strcmp(freq, "15k") == 0) { o->freq = 15; - } - else if (strcmp(freq, "25K") == 0 || strcmp(freq, "25k") == 0) { + } else if (strcmp(freq, "25K") == 0 || strcmp(freq, "25k") == 0) { o->freq = 25; - } - else if (strcmp(freq, "50K") == 0 || strcmp(freq, "50k") == 0) { + } else if (strcmp(freq, "50K") == 0 || strcmp(freq, "50k") == 0) { o->freq = 50; - } - else if (strcmp(freq, "100K") == 0 || strcmp(freq, "100k") == 0) { + } else if (strcmp(freq, "100K") == 0 || strcmp(freq, "100k") == 0) { o->freq = 100; - } - else if (strcmp(freq, "125K") == 0 || strcmp(freq, "125k") == 0) { + } else if (strcmp(freq, "125K") == 0 || strcmp(freq, "125k") == 0) { o->freq = 125; - } - else if (strcmp(freq, "240K") == 0 || strcmp(freq, "240k") == 0) { + } else if (strcmp(freq, "240K") == 0 || strcmp(freq, "240k") == 0) { o->freq = 240; - } - else if (strcmp(freq, "480K") == 0 || strcmp(freq, "480k") == 0) { + } else if (strcmp(freq, "480K") == 0 || strcmp(freq, "480k") == 0) { o->freq = 480; - } - else if (strcmp(freq, "950K") == 0 || strcmp(freq, "950k") == 0) { + } else if (strcmp(freq, "950K") == 0 || strcmp(freq, "950k") == 0) { o->freq = 950; - } - else if (strcmp(freq, "1200K") == 0 || strcmp(freq, "1200k") == 0 || strcmp(freq, "1.2M") == 0 || strcmp(freq, "1.2m") == 0) { + } else if (strcmp(freq, "1200K") == 0 || strcmp(freq, "1200k") == 0 || + strcmp(freq, "1.2M") == 0 || strcmp(freq, "1.2m") == 0) { o->freq = 1200; - } - else if (strcmp(freq, "1800K") == 0 || strcmp(freq, "1800k") == 0 || strcmp(freq, "1.8M") == 0 || strcmp(freq, "1.8m") == 0) { + } else if (strcmp(freq, "1800K") == 0 || strcmp(freq, "1800k") == 0 || + strcmp(freq, "1.8M") == 0 || strcmp(freq, "1.8m") == 0) { o->freq = 1800; - } - else if (strcmp(freq, "4000K") == 0 || strcmp(freq, "4000k") == 0 || strcmp(freq, "4M") == 0 || strcmp(freq, "4m") == 0) { + } else if (strcmp(freq, "4000K") == 0 || strcmp(freq, "4000k") == 0 || + strcmp(freq, "4M") == 0 || strcmp(freq, "4m") == 0) { o->freq = 4000; + } else { + return(-1); } - else - return -1; - } - else if (strcmp(av[0], "--format") == 0 || starts_with(av[0], "--format=")) { + } else if (strcmp(av[0], "--format") == 0 || starts_with(av[0], "--format=")) { const char * format; + if (strcmp(av[0], "--format") == 0) { ac--; av++; - if (ac < 1) return -1; + + if (ac < 1) { return(-1); } + format = av[0]; - } - else { + } else { format = av[0] + strlen("--format="); } - if (strcmp(format, "binary") == 0) + + if (strcmp(format, "binary") == 0) { o->format = FLASH_FORMAT_BINARY; - else if (strcmp(format, "ihex") == 0) + } else if (strcmp(format, "ihex") == 0) { o->format = FLASH_FORMAT_IHEX; - else - return bad_arg("format"); - } - else if ( starts_with(av[0], "--flash=") ) { + } else { + return(bad_arg("format")); + } + } else if ( starts_with(av[0], "--flash=")) { const char *arg = av[0] + strlen("--flash="); uint32_t flash_size; result = get_integer_from_char_array(arg, &flash_size); - if (result != 0) return bad_arg ("--flash"); - else o->flash_size = (size_t) flash_size; - } - else if (strcmp(av[0],"--connect-under-reset")== 0){ + + if (result != 0) { + return(bad_arg ("--flash")); + } else { + o->flash_size = (size_t)flash_size; + } + } else if (strcmp(av[0], "--connect-under-reset") == 0) { o->connect_under_reset = true; - } - else { - break; // non-option found + } else { + break; // non-option found + } ac--; av++; } - // command and (optional) device name + /* command and (optional) device name */ while (ac >= 1) { if (strcmp(av[0], "erase") == 0) { - if (o->cmd != FLASH_CMD_NONE) return -1; + if (o->cmd != FLASH_CMD_NONE) { return(-1); } + o->cmd = FLASH_CMD_ERASE; - } - else if (strcmp(av[0], "read") == 0) { - if (o->cmd != FLASH_CMD_NONE) return -1; + } else if (strcmp(av[0], "read") == 0) { + if (o->cmd != FLASH_CMD_NONE) { return(-1); } + o->cmd = FLASH_CMD_READ; - } - else if (strcmp(av[0], "write") == 0) { - if (o->cmd != FLASH_CMD_NONE) return -1; + } else if (strcmp(av[0], "write") == 0) { + if (o->cmd != FLASH_CMD_NONE) { return(-1); } + o->cmd = FLASH_CMD_WRITE; - } - else if (strcmp(av[0], "reset") == 0) { - if (o->cmd != FLASH_CMD_NONE) return -1; + } else if (strcmp(av[0], "reset") == 0) { + if (o->cmd != FLASH_CMD_NONE) { return(-1); } + o->cmd = CMD_RESET; - } - else { + } else { break; } @@ -262,60 +259,83 @@ int flash_get_opts(struct flash_opts* o, int ac, char** av) { av++; } - switch(o->cmd) { - case FLASH_CMD_NONE: // no command found - return -1; + switch (o->cmd) { + case FLASH_CMD_NONE: // no command found + return(-1); - case FLASH_CMD_ERASE: // no more arguments expected - if (ac != 0) return -1; - break; + case FLASH_CMD_ERASE: // no more arguments expected - case FLASH_CMD_READ: // expect filename, addr and size - if ((o->area == FLASH_OPTION_BYTES) &&(ac == 0)) break; - if (ac != 3) return invalid_args("read "); - if (ac != 3) return -1; - o->filename = av[0]; - uint32_t address; - result = get_integer_from_char_array(av[1], &address); - if (result != 0) return bad_arg ("addr"); - else o->addr = (stm32_addr_t) address; + if (ac != 0) { return(-1); } - uint32_t size; - result = get_integer_from_char_array(av[2], &size); - if (result != 0) return bad_arg ("size"); - else o->size = (size_t) size; + break; - break; + case FLASH_CMD_READ: // expect filename, addr and size - case FLASH_CMD_WRITE: - if (o->area == FLASH_OPTION_BYTES){ - if (ac != 1) return -1; + if ((o->area == FLASH_OPTION_BYTES) && (ac == 0)) { break; } - uint32_t val; - result = get_integer_from_char_array(av[0], &val); - if (result != 0) return bad_arg ("val"); - else o->val = (uint32_t) val; + if (ac != 3) { return(invalid_args("read ")); } + if (ac != 3) { return(-1); } + + o->filename = av[0]; + uint32_t address; + result = get_integer_from_char_array(av[1], &address); + + if (result != 0) { + return(bad_arg ("addr")); + } else { + o->addr = (stm32_addr_t)address; + } + + uint32_t size; + result = get_integer_from_char_array(av[2], &size); + + if (result != 0) { + return(bad_arg ("size")); + } else { + o->size = (size_t)size; + } + + break; + + case FLASH_CMD_WRITE: + + if (o->area == FLASH_OPTION_BYTES) { + if (ac != 1) { return(-1); } + + uint32_t val; + result = get_integer_from_char_array(av[0], &val); + + if (result != 0) { + return(bad_arg ("val")); + } else { + o->val = (uint32_t)val; } - else if (o->format == FLASH_FORMAT_BINARY) { // expect filename and addr - if (ac != 2) return invalid_args("write "); - o->filename = av[0]; - uint32_t addr; - result = get_integer_from_char_array(av[1], &addr); - if (result != 0) return bad_arg ("addr"); - else o->addr = (stm32_addr_t) addr; - } - else if (o->format == FLASH_FORMAT_IHEX) { // expect filename - if (ac != 1) return invalid_args("write "); - o->filename = av[0]; - } - else { - return -1; // should have been caught during format parsing + + } else if (o->format == FLASH_FORMAT_BINARY) { // expect filename and addr + if (ac != 2) { return(invalid_args("write ")); } + + o->filename = av[0]; + uint32_t addr; + result = get_integer_from_char_array(av[1], &addr); + + if (result != 0) { + return(bad_arg ("addr")); + } else { + o->addr = (stm32_addr_t)addr; } - break; + } else if (o->format == FLASH_FORMAT_IHEX) { // expect filename + if (ac != 1) { return(invalid_args("write ")); } + + o->filename = av[0]; + } else { + return(-1); // should have been caught during format parsing + } + + break; - default: break ; + default: break; } - return 0; + return(0); } diff --git a/src/st-info/info.c b/src/st-info/info.c index 8464d8632..1bc48a05e 100644 --- a/src/st-info/info.c +++ b/src/st-info/info.c @@ -5,8 +5,7 @@ #include -static void usage(void) -{ +static void usage(void) { puts("st-info --version"); puts("st-info --probe"); puts("st-info --serial"); @@ -19,31 +18,32 @@ static void usage(void) } /* Print normal or OpenOCD hla_serial with newline */ -static void stlink_print_serial(stlink_t *sl, bool openocd) -{ +static void stlink_print_serial(stlink_t *sl, bool openocd) { const char *fmt; if (openocd) { - printf("\""); - fmt = "\\x%02x"; + printf("\""); + fmt = "\\x%02x"; } else { - fmt = "%02x"; + fmt = "%02x"; } for (int n = 0; n < sl->serial_size; n++) printf(fmt, sl->serial[n]); - if (openocd) - printf("\""); + if (openocd) { + printf("\""); + } + printf("\n"); } -static void stlink_print_info(stlink_t *sl) -{ +static void stlink_print_info(stlink_t *sl) { const struct stlink_chipid_params *params = NULL; - if (!sl) + if (!sl) { return; + } printf(" serial: "); stlink_print_serial(sl, false); @@ -51,18 +51,17 @@ static void stlink_print_info(stlink_t *sl) stlink_print_serial(sl, true); printf(" flash: %u (pagesize: %u)\n", - (unsigned int)sl->flash_size, (unsigned int)sl->flash_pgsz); + (unsigned int)sl->flash_size, (unsigned int)sl->flash_pgsz); printf(" sram: %u\n", (unsigned int)sl->sram_size); printf(" chipid: 0x%.4x\n", sl->chip_id); - params = stlink_chipid_get_params(sl->chip_id); - if (params) - printf(" descr: %s\n", params->description); + params = stlink_chipid_get_params(sl->chip_id); + + if (params) { printf(" descr: %s\n", params->description); } } -static void stlink_probe(void) -{ +static void stlink_probe(void) { stlink_t **stdevs; size_t size; @@ -70,16 +69,15 @@ static void stlink_probe(void) printf("Found %u stlink programmers\n", (unsigned int)size); - for (size_t n = 0; n < size; n++) - stlink_print_info(stdevs[n]); + for (size_t n = 0; n < size; n++) stlink_print_info(stdevs[n]); stlink_probe_usb_free(&stdevs, size); } -static stlink_t *stlink_open_first(bool under_reset) -{ +static stlink_t *stlink_open_first(bool under_reset) { stlink_t* sl = NULL; sl = stlink_v1_open(0, 1); + if (sl == NULL) { if (under_reset) { sl = stlink_open_usb(0, 2, NULL, 0); @@ -87,84 +85,79 @@ static stlink_t *stlink_open_first(bool under_reset) sl = stlink_open_usb(0, 1, NULL, 0); } } - - return sl; + + return(sl); } -static int print_data(int ac, char **av) -{ +static int print_data(int ac, char **av) { stlink_t* sl = NULL; bool under_reset = false; - // Probe needs all devices unclaimed + // probe needs all devices unclaimed if (strcmp(av[1], "--probe") == 0) { stlink_probe(); - return 0; + return(0); } else if (strcmp(av[1], "--version") == 0) { printf("v%s\n", STLINK_VERSION); - return 0; + return(0); } if (ac == 3) { - if (strcmp(av[2],"--connect-under-reset") == 0) { + if (strcmp(av[2], "--connect-under-reset") == 0) { under_reset = true; } else { usage(); - return -1; + return(-1); } } sl = stlink_open_first(under_reset); - if (sl == NULL) { - return -1; - } + if (sl == NULL) { return(-1); } sl->verbose = 0; - if (stlink_current_mode(sl) == STLINK_DEV_DFU_MODE) - stlink_exit_dfu_mode(sl); + if (stlink_current_mode(sl) == STLINK_DEV_DFU_MODE) { stlink_exit_dfu_mode(sl); } - if (stlink_current_mode(sl) != STLINK_DEV_DEBUG_MODE) - stlink_enter_swd_mode(sl); + if (stlink_current_mode(sl) != STLINK_DEV_DEBUG_MODE) { stlink_enter_swd_mode(sl); } - if (strcmp(av[1], "--serial") == 0) + if (strcmp(av[1], "--serial") == 0) { stlink_print_serial(sl, false); - else if (strcmp(av[1], "--hla-serial") == 0) + } else if (strcmp(av[1], "--hla-serial") == 0) { stlink_print_serial(sl, true); - else if (strcmp(av[1], "--flash") == 0) + } else if (strcmp(av[1], "--flash") == 0) { printf("0x%x\n", (unsigned int)sl->flash_size); - else if (strcmp(av[1], "--pagesize") == 0) + } else if (strcmp(av[1], "--pagesize") == 0) { printf("0x%x\n", (unsigned int)sl->flash_pgsz); - else if (strcmp(av[1], "--sram") == 0) + } else if (strcmp(av[1], "--sram") == 0) { printf("0x%x\n", (unsigned int)sl->sram_size); - else if (strcmp(av[1], "--chipid") == 0) + } else if (strcmp(av[1], "--chipid") == 0) { printf("0x%.4x\n", sl->chip_id); - else if (strcmp(av[1], "--descr") == 0) { + } else if (strcmp(av[1], "--descr") == 0) { const struct stlink_chipid_params *params = stlink_chipid_get_params(sl->chip_id); - if (params == NULL) - return -1; + + if (params == NULL) { return(-1); } + printf("%s\n", params->description); } - if (sl) - { + if (sl) { stlink_exit_debug_mode(sl); stlink_close(sl); } - return 0; + return(0); } -int main(int ac, char** av) -{ +int main(int ac, char** av) { int err = -1; + if (ac < 2) { usage(); - return -1; + return(-1); } - err = print_data(ac,av); + err = print_data(ac, av); - return err; + return(err); } diff --git a/src/st-util/gdb-remote.c b/src/st-util/gdb-remote.c index 04729cc75..bdf8afd24 100644 --- a/src/st-util/gdb-remote.c +++ b/src/st-util/gdb-remote.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2011 Peter Zotov + * Copyright (c) 2011 Peter Zotov * Use of this source code is governed by a BSD-style license that can be found in the LICENSE file. */ @@ -20,7 +20,7 @@ static const char hex[] = "0123456789abcdef"; int gdb_send_packet(int fd, char* data) { - unsigned int data_length = (unsigned int) strlen(data); + unsigned int data_length = (unsigned int)strlen(data); int length = data_length + 4; char* packet = malloc(length); // '$' data (hex) '#' cksum (hex) @@ -29,6 +29,7 @@ int gdb_send_packet(int fd, char* data) { packet[0] = '$'; uint8_t cksum = 0; + for (unsigned int i = 0; i < data_length; i++) { packet[i + 1] = data[i]; cksum += data[i]; @@ -41,18 +42,19 @@ int gdb_send_packet(int fd, char* data) { while (1) { if (write(fd, packet, length) != length) { free(packet); - return -2; + return(-2); } char ack; + if (read(fd, &ack, 1) != 1) { free(packet); - return -2; + return(-2); } if (ack == '+') { free(packet); - return 0; + return(0); } } } @@ -66,7 +68,9 @@ int gdb_recv_packet(int fd, char** buffer) { char* packet_buffer = malloc(packet_size); unsigned state; - if (packet_buffer == NULL) return -2; + if (packet_buffer == NULL) { + return(-2); + } start: state = 0; @@ -80,18 +84,25 @@ int gdb_recv_packet(int fd, char** buffer) { */ char c; + while (state != 4) { if (read(fd, &c, 1) != 1) { free(packet_buffer); - return -2; + return(-2); } - switch(state) { + switch (state) { case 0: - if (c != '$') { /* ignore */ } else { state = 1; } + + if (c != '$') { /* ignore */ + } else { + state = 1; + } + break; case 1: + if (c == '#') { state = 2; } else { @@ -101,14 +112,16 @@ int gdb_recv_packet(int fd, char** buffer) { if (packet_idx == packet_size) { packet_size += ALLOC_STEP; void* p = realloc(packet_buffer, packet_size); + if (p != NULL) { packet_buffer = p; } else { free(packet_buffer); - return -2; + return(-2); } } } + break; case 2: @@ -124,25 +137,29 @@ int gdb_recv_packet(int fd, char** buffer) { } uint8_t recv_cksum_int = strtoul(recv_cksum, NULL, 16); + if (recv_cksum_int != cksum) { char nack = '-'; + if (write(fd, &nack, 1) != 1) { free(packet_buffer); - return -2; + return(-2); } + goto start; } else { char ack = '+'; + if (write(fd, &ack, 1) != 1) { free(packet_buffer); - return -2; + return(-2); } } packet_buffer[packet_idx] = 0; *buffer = packet_buffer; - return packet_idx; + return(packet_idx); } /* @@ -157,9 +174,15 @@ int gdb_check_for_interrupt(int fd) { if (poll(&pfd, 1, 0) != 0) { char c; - if (read(fd, &c, 1) != 1) return -2; - if (c == '\x03') return 1; // ^C + + if (read(fd, &c, 1) != 1) { + return(-2); + } + + if (c == '\x03') { + return(1); // ^C + } } - return 0; + return(0); } diff --git a/src/st-util/gdb-remote.h b/src/st-util/gdb-remote.h index bfa01046c..6e76746b7 100644 --- a/src/st-util/gdb-remote.h +++ b/src/st-util/gdb-remote.h @@ -5,4 +5,4 @@ int gdb_send_packet(int fd, char* data); int gdb_recv_packet(int fd, char** buffer); int gdb_check_for_interrupt(int fd); -#endif +#endif // _GDB_REMOTE_H_ diff --git a/src/st-util/gdb-server.c b/src/st-util/gdb-server.c index 119d0ff9a..94cd6fda7 100644 --- a/src/st-util/gdb-server.c +++ b/src/st-util/gdb-server.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2011 Peter Zotov + * Copyright (c) 2011 Peter Zotov * Use of this source code is governed by a BSD-style license that can be found in the LICENSE file. */ @@ -69,13 +69,13 @@ typedef struct _st_state_t { int serve(stlink_t *sl, st_state_t *st); char* make_memory_map(stlink_t *sl); -static void init_cache (stlink_t *sl); +static void init_cache(stlink_t *sl); static void cleanup(int signum) { (void)signum; if (connected_stlink) { - /* Switch back to mass storage mode before closing. */ + // Switch back to mass storage mode before closing stlink_run(connected_stlink); stlink_exit_debug_mode(connected_stlink); stlink_close(connected_stlink); @@ -87,12 +87,14 @@ static void cleanup(int signum) { static stlink_t* do_connect(st_state_t *st) { stlink_t *sl = NULL; + if (serial_specified) { sl = stlink_open_usb(st->logging_level, st->reset, serialnumber, 0); } else { sl = stlink_open_usb(st->logging_level, st->reset, NULL, 0); } - return sl; + + return(sl); } @@ -109,92 +111,104 @@ int parse_options(int argc, char** argv, st_state_t *st) { {0, 0, 0, 0}, }; const char * help_str = "%s - usage:\n\n" - " -h, --help\t\tPrint this help\n" - " -V, --version\t\tPrint the version\n" - " -vXX, --verbose=XX\tSpecify a specific verbosity level (0..99)\n" - " -v, --verbose\t\tSpecify generally verbose logging\n" - "\t\t\tChoose what version of stlink to use, (defaults to 2)\n" - " -1, --stlinkv1\tForce stlink version 1\n" - " -p 4242, --listen_port=1234\n" - "\t\t\tSet the gdb server listen port. " - "(default port: " STRINGIFY(DEFAULT_GDB_LISTEN_PORT) ")\n" - " -m, --multi\n" - "\t\t\tSet gdb server to extended mode.\n" - "\t\t\tst-util will continue listening for connections after disconnect.\n" - " -n, --no-reset\n" - "\t\t\tDo not reset board on connection.\n" - " --semihosting\n" - "\t\t\tEnable semihosting support.\n" - " --serial \n" - "\t\t\tUse a specific serial number.\n" - "\n" - "The STLINK device to use can be specified in the environment\n" - "variable STLINK_DEVICE on the format :.\n" - "\n" - ; + " -h, --help\t\tPrint this help\n" + " -V, --version\t\tPrint the version\n" + " -vXX, --verbose=XX\tSpecify a specific verbosity level (0..99)\n" + " -v, --verbose\t\tSpecify generally verbose logging\n" + "\t\t\tChoose what version of stlink to use, (defaults to 2)\n" + " -1, --stlinkv1\tForce stlink version 1\n" + " -p 4242, --listen_port=1234\n" + "\t\t\tSet the gdb server listen port. " + "(default port: " STRINGIFY(DEFAULT_GDB_LISTEN_PORT) ")\n" + " -m, --multi\n" + "\t\t\tSet gdb server to extended mode.\n" + "\t\t\tst-util will continue listening for connections after disconnect.\n" + " -n, --no-reset\n" + "\t\t\tDo not reset board on connection.\n" + " --semihosting\n" + "\t\t\tEnable semihosting support.\n" + " --serial \n" + "\t\t\tUse a specific serial number.\n" + "\n" + "The STLINK device to use can be specified in the environment\n" + "variable STLINK_DEVICE on the format :.\n" + "\n" + ; int option_index = 0; int c; int q; - while ((c = getopt_long(argc, argv, "hv::p:mn", long_options, &option_index)) != -1) { + + while ((c = getopt_long(argc, argv, "hv::p:mn", long_options, &option_index)) != -1) switch (c) { - case 0: - break; - case 'h': - printf(help_str, argv[0]); - exit(EXIT_SUCCESS); - break; - case 'v': - if (optarg) { - st->logging_level = atoi(optarg); - } else { - st->logging_level = DEBUG_LOGGING_LEVEL; - } - break; - case 'p': - sscanf(optarg, "%i", &q); - if (q < 0) { - fprintf(stderr, "Can't use a negative port to listen on: %d\n", q); - exit(EXIT_FAILURE); - } - st->listen_port = q; - break; - case 'm': - st->persistent = 1; - break; - case 'n': - st->reset = 0; - break; - case 'V': - printf("v%s\n", STLINK_VERSION); - exit(EXIT_SUCCESS); - case SEMIHOSTING_OPTION: - semihosting = true; - break; - case SERIAL_OPTION: - printf("use serial %s\n",optarg); - /** @todo This is not really portable, as strlen really returns size_t we need to obey and not cast it to a signed type. */ - int j = (int)strlen(optarg); - int length = j / 2; //the length of the destination-array - if (j % 2 != 0) return -1; - for (size_t k = 0; j >= 0 && k < sizeof(serialnumber); ++k, j -= 2) { - char buffer[3] = {0}; - memcpy(buffer, optarg + j, 2); - serialnumber[length - k] = (uint8_t)strtol(buffer, NULL, 16); - } - serial_specified = true; - break; + case 0: + break; + case 'h': + printf(help_str, argv[0]); + exit(EXIT_SUCCESS); + break; + case 'v': + + if (optarg) { + st->logging_level = atoi(optarg); + } else { + st->logging_level = DEBUG_LOGGING_LEVEL; + } + + break; + case 'p': + sscanf(optarg, "%i", &q); + + if (q < 0) { + fprintf(stderr, "Can't use a negative port to listen on: %d\n", q); + exit(EXIT_FAILURE); + } + + st->listen_port = q; + break; + case 'm': + st->persistent = 1; + break; + case 'n': + st->reset = 0; + break; + case 'V': + printf("v%s\n", STLINK_VERSION); + exit(EXIT_SUCCESS); + case SEMIHOSTING_OPTION: + semihosting = true; + break; + case SERIAL_OPTION: + printf("use serial %s\n", optarg); + /* TODO: This is not really portable, as strlen really returns size_t, + * we need to obey and not cast it to a signed type. + */ + int j = (int)strlen(optarg); + int length = j / 2; // the length of the destination-array + + if (j % 2 != 0) { return(-1); } + + for (size_t k = 0; j >= 0 && k < sizeof(serialnumber); ++k, j -= 2) { + char buffer[3] = {0}; + memcpy(buffer, optarg + j, 2); + serialnumber[length - k] = (uint8_t)strtol(buffer, NULL, 16); + } + + serial_specified = true; + break; } - } + if (optind < argc) { printf("non-option ARGV-elements: "); - while (optind < argc) - printf("%s ", argv[optind++]); + + while (optind < argc) { printf("%s ", argv[optind++]); } + printf("\n"); } - return 0; + + return(0); } int main(int argc, char** argv) { @@ -211,11 +225,12 @@ int main(int argc, char** argv) { printf("st-util\n"); sl = do_connect(&state); - if (sl == NULL) return 1; - if (sl->chip_id == STLINK_CHIPID_UNKNOWN) { + if (sl == NULL) { return(1); } + + if (sl->chip_id == STLINK_CHIPID_UNKNOWN) { ELOG("Unsupported Target (Chip ID is %#010x, Core ID is %#010x).\n", sl->chip_id, sl->core_id); - return 1; + return(1); } connected_stlink = sl; @@ -223,22 +238,25 @@ int main(int argc, char** argv) { signal(SIGTERM, &cleanup); signal(SIGSEGV, &cleanup); - if (state.reset) stlink_reset(sl); + if (state.reset) { stlink_reset(sl); } DLOG("Chip ID is %#010x, Core ID is %#08x.\n", sl->chip_id, sl->core_id); - sl->verbose=0; + sl->verbose = 0; current_memory_map = make_memory_map(sl); #if defined(_WIN32) - WSADATA wsadata; - if (WSAStartup(MAKEWORD(2,2),&wsadata) !=0) goto winsock_error; + WSADATA wsadata; + + if (WSAStartup(MAKEWORD(2, 2), &wsadata) != 0) { goto winsock_error; } + #endif init_cache(sl); - do { - if (serve(sl, &state)) { usleep (1 * 1000); } // don't go beserk if serve returns with error + do { // don't go beserk if serve() returns with error + if (serve(sl, &state)) { usleep (1 * 1000); } + sl = connected_stlink; // in case serve() changed the connection stlink_run(sl); // continue } while (state.persistent); @@ -252,7 +270,7 @@ int main(int argc, char** argv) { stlink_exit_debug_mode(sl); stlink_close(sl); - return 0; + return(0); } static const char* const target_description_F4 = @@ -328,14 +346,14 @@ static const char* const memory_map_template_F4 = " " // code = sram, bootrom or flash; flash is bigger " " // ccm ram " " // sram - " " //Sectors 0..3 - " 0x4000" //16kB + " " // Sectors 0..3 + " 0x4000" // 16kB " " - " " //Sector 4 - " 0x10000" //64kB + " " // Sector 4 + " 0x10000" // 64kB " " - " " //Sectors 5..11 - " 0x20000" //128kB + " " // Sectors 5..11 + " 0x20000" // 128kB " " " " // peripheral regs " " // AHB3 Peripherals @@ -356,14 +374,14 @@ static const char* const memory_map_template_F4_HD = " " // fmc bank 2 & 3 (nand flash) " " // fmc bank 4 (pc card) " " // fmc sdram bank 1 & 2 - " " //Sectors 0..3 - " 0x4000" //16kB + " " // Sectors 0..3 + " 0x4000" // 16kB " " - " " //Sector 4 - " 0x10000" //64kB + " " // Sector 4 + " 0x10000" // 64kB " " - " " //Sectors 5..11 - " 0x20000" //128kB + " " // Sectors 5..11 + " 0x20000" // 128kB " " " " // peripheral regs " " // cortex regs @@ -376,20 +394,20 @@ static const char* const memory_map_template_F2 = "" "" - " " // code = sram, bootrom or flash; flash is bigger - " " // sram - " " //Sectors 0..3 - " 0x4000" //16kB + " " // code = sram, bootrom or flash; flash is bigger + " " // sram + " " // Sectors 0..3 + " 0x4000" // 16kB " " - " " //Sector 4 - " 0x10000" //64kB + " " // Sector 4 + " 0x10000" // 64kB " " - " " //Sectors 5.. - " 0x20000" //128kB + " " // Sectors 5.. + " 0x20000" // 128kB " " " " // peripheral regs " " // cortex regs - " " // bootrom + " " // bootrom " " // option byte area ""; @@ -398,9 +416,9 @@ static const char* const memory_map_template_L4 = "" "" - " " // code = sram, bootrom or flash; flash is bigger - " " // SRAM2 (32 KB) - " " // SRAM1 (96 KB) + " " // code = sram, bootrom or flash; flash is bigger + " " // SRAM2 (32kB) + " " // SRAM1 (96kB) " " " 0x800" " " @@ -417,9 +435,9 @@ static const char* const memory_map_template_L496 = "" "" - " " // code = sram, bootrom or flash; flash is bigger - " " // SRAM2 (64 KB) - " " // SRAM1 + aliased SRAM2 (256+64=320 KB) + " " // code = sram, bootrom or flash; flash is bigger + " " // SRAM2 (64kB) + " " // SRAM1 + aliased SRAM2 (256 + 64 = 320kB) " " " 0x800" " " @@ -436,14 +454,14 @@ static const char* const memory_map_template = "" "" - " " // code = sram, bootrom or flash; flash is bigger - " " // sram 8k + " " // code = sram, bootrom or flash; flash is bigger + " " // sram 8kB " " " 0x%x" " " " " // peripheral regs " " // cortex regs - " " // bootrom + " " // bootrom " " // option byte area ""; @@ -454,7 +472,7 @@ static const char* const memory_map_template_F7 = "" " " // ITCM ram 16kB " " // ITCM flash - " " // sram + " " // sram " " // Sectors 0..3 " 0x8000" // 32kB " " @@ -479,14 +497,14 @@ static const char* const memory_map_template_F4_DE = "" " " // code = sram, bootrom or flash; flash is bigger " " // sram - " " //Sectors 0..3 - " 0x4000" //16kB + " " // Sectors 0..3 + " 0x4000" // 16kB " " - " " //Sector 4 - " 0x10000" //64kB + " " // Sector 4 + " 0x10000" // 64kB " " - " " //Sectors 5..7 - " 0x20000" //128kB + " " // Sectors 5..7 + " 0x20000" // 128kB " " " " // peripheral regs " " // cortex regs @@ -501,37 +519,45 @@ char* make_memory_map(stlink_t *sl) { char* map = malloc(sz); map[0] = '\0'; - if (sl->chip_id==STLINK_CHIPID_STM32_F4 || sl->chip_id==STLINK_CHIPID_STM32_F446 || sl->chip_id==STLINK_CHIPID_STM32_F411RE) { - strcpy(map, memory_map_template_F4); - } else if (sl->chip_id==STLINK_CHIPID_STM32_F4_DE) { + if (sl->chip_id == STLINK_CHIPID_STM32_F4 || + sl->chip_id == STLINK_CHIPID_STM32_F446 || + sl->chip_id == STLINK_CHIPID_STM32_F411RE) { + strcpy(map, memory_map_template_F4); + } else if (sl->chip_id == STLINK_CHIPID_STM32_F4_DE) { strcpy(map, memory_map_template_F4_DE); - } else if (sl->core_id==STM32F7_CORE_ID) { + } else if (sl->core_id == STM32F7_CORE_ID) { snprintf(map, sz, memory_map_template_F7, - (unsigned int)sl->sram_size); - } else if (sl->chip_id==STLINK_CHIPID_STM32_F4_HD) { + (unsigned int)sl->sram_size); + } else if (sl->chip_id == STLINK_CHIPID_STM32_F4_HD) { strcpy(map, memory_map_template_F4_HD); - } else if (sl->chip_id==STLINK_CHIPID_STM32_F2) { + } else if (sl->chip_id == STLINK_CHIPID_STM32_F2) { snprintf(map, sz, memory_map_template_F2, - (unsigned int)sl->flash_size, - (unsigned int)sl->sram_size, - (unsigned int)sl->flash_size - 0x20000, - (unsigned int)sl->sys_base, (unsigned int)sl->sys_size); - } else if ((sl->chip_id==STLINK_CHIPID_STM32_L4) || - (sl->chip_id==STLINK_CHIPID_STM32_L43X) || - (sl->chip_id==STLINK_CHIPID_STM32_L46X)) { + (unsigned int)sl->flash_size, + (unsigned int)sl->sram_size, + (unsigned int)sl->flash_size - 0x20000, + (unsigned int)sl->sys_base, + (unsigned int)sl->sys_size); + } else if ((sl->chip_id == STLINK_CHIPID_STM32_L4) || + (sl->chip_id == STLINK_CHIPID_STM32_L43X) || + (sl->chip_id == STLINK_CHIPID_STM32_L46X)) { snprintf(map, sz, memory_map_template_L4, - (unsigned int)sl->flash_size, (unsigned int)sl->flash_size); - } else if (sl->chip_id==STLINK_CHIPID_STM32_L496X) { + (unsigned int)sl->flash_size, + (unsigned int)sl->flash_size); + } else if (sl->chip_id == STLINK_CHIPID_STM32_L496X) { snprintf(map, sz, memory_map_template_L496, - (unsigned int)sl->flash_size, (unsigned int)sl->flash_size); + (unsigned int)sl->flash_size, + (unsigned int)sl->flash_size); } else { snprintf(map, sz, memory_map_template, - (unsigned int)sl->flash_size, - (unsigned int)sl->sram_size, - (unsigned int)sl->flash_size, (unsigned int)sl->flash_pgsz, - (unsigned int)sl->sys_base, (unsigned int)sl->sys_size); + (unsigned int)sl->flash_size, + (unsigned int)sl->sram_size, + (unsigned int)sl->flash_size, + (unsigned int)sl->flash_pgsz, + (unsigned int)sl->sys_base, + (unsigned int)sl->sys_size); } - return map; + + return(map); } /* @@ -566,7 +592,7 @@ static void init_data_watchpoints(stlink_t *sl) { DLOG("init watchpoints\n"); stlink_read_debug32(sl, 0xE000EDFC, &data); - data |= 1<<24; + data |= 1 << 24; // set trcena in debug command to turn on dwt unit stlink_write_debug32(sl, 0xE000EDFC, data); @@ -577,8 +603,7 @@ static void init_data_watchpoints(stlink_t *sl) { } } -static int add_data_watchpoint( - stlink_t *sl, enum watchfun wf, stm32_addr_t addr, unsigned int len) { +static int add_data_watchpoint(stlink_t *sl, enum watchfun wf, stm32_addr_t addr, unsigned int len) { int i = 0; uint32_t mask, dummy; @@ -588,13 +613,14 @@ static int add_data_watchpoint( mask = -1; i = len; + while (i) { i >>= 1; mask++; } if ((mask != (uint32_t)-1) && (mask < 16)) { - for (i = 0; i < DATA_WATCH_NUM; i++) { + for (i = 0; i < DATA_WATCH_NUM; i++) // is this an empty slot ? if (data_watches[i].fun == WATCHDISABLED) { DLOG("insert watchpoint %d addr %x wf %u mask %u len %d\n", i, addr, wf, mask, len); @@ -614,43 +640,42 @@ static int add_data_watchpoint( // just to make sure the matched bit is clear ! stlink_read_debug32(sl, 0xE0001028 + i * 16, &dummy); - return 0; + return(0); } - } } DLOG("failure: add watchpoints addr %x wf %u len %u\n", addr, wf, len); - return -1; + return(-1); } static int delete_data_watchpoint(stlink_t *sl, stm32_addr_t addr) { int i; - for (i = 0 ; i < DATA_WATCH_NUM; i++) { + for (i = 0; i < DATA_WATCH_NUM; i++) { if ((data_watches[i].addr == addr) && (data_watches[i].fun != WATCHDISABLED)) { DLOG("delete watchpoint %d addr %x\n", i, addr); data_watches[i].fun = WATCHDISABLED; stlink_write_debug32(sl, 0xe0001028 + i * 16, 0); - return 0; + return(0); } } DLOG("failure: delete watchpoint addr %x\n", addr); - return -1; + return(-1); } static int code_break_num; static int code_lit_num; -#define CODE_BREAK_NUM_MAX 15 -#define CODE_BREAK_LOW 0x01 +#define CODE_BREAK_NUM_MAX 15 +#define CODE_BREAK_LOW 0x01 #define CODE_BREAK_HIGH 0x02 struct code_hw_breakpoint { stm32_addr_t addr; - int type; + int type; }; static struct code_hw_breakpoint code_breaks[CODE_BREAK_NUM_MAX]; @@ -658,7 +683,7 @@ static struct code_hw_breakpoint code_breaks[CODE_BREAK_NUM_MAX]; static void init_code_breakpoints(stlink_t *sl) { unsigned int val; memset(sl->q_buf, 0, 4); - stlink_write_debug32(sl, STLINK_REG_CM3_FP_CTRL, 0x03 /*KEY | ENABLE4*/); + stlink_write_debug32(sl, STLINK_REG_CM3_FP_CTRL, 0x03 /* KEY | ENABLE4 */); stlink_read_debug32(sl, STLINK_REG_CM3_FP_CTRL, &val); code_break_num = ((val >> 4) & 0xf); code_lit_num = ((val >> 8) & 0xf); @@ -671,12 +696,11 @@ static void init_code_breakpoints(stlink_t *sl) { } } -static int has_breakpoint(stm32_addr_t addr) -{ - for (int i = 0; i < code_break_num; i++) { - if (code_breaks[i].addr == addr) return 1; - } - return 0; +static int has_breakpoint(stm32_addr_t addr) { + for (int i = 0; i < code_break_num; i++) + if (code_breaks[i].addr == addr) { return(1); } + + return(0); } static int update_code_breakpoint(stlink_t *sl, stm32_addr_t addr, int set) { @@ -686,37 +710,53 @@ static int update_code_breakpoint(stlink_t *sl, stm32_addr_t addr, int set) { if (addr & 1) { ELOG("update_code_breakpoint: unaligned address %08x\n", addr); - return -1; + return(-1); } - if (sl->core_id==STM32F7_CORE_ID) { + if (sl->core_id == STM32F7_CORE_ID) { fpb_addr = addr; } else { fpb_addr = addr & ~0x3; } int id = -1; - for (int i = 0; i < code_break_num; i++) { + + for (int i = 0; i < code_break_num; i++) if (fpb_addr == code_breaks[i].addr || (set && code_breaks[i].type == 0)) { id = i; break; } - } + if (id == -1) { - if (set) { return -1; } // free slot not found - else { return 0; } // breakpoint is already removed + if (set) { + return(-1); + } // free slot not found + else { + return(0); + } // breakpoint is already removed + } struct code_hw_breakpoint* bp = &code_breaks[id]; bp->addr = fpb_addr; - if (sl->core_id==STM32F7_CORE_ID) { - if (set) { bp->type = type; } else { bp->type = 0; } + if (sl->core_id == STM32F7_CORE_ID) { + if (set) { + bp->type = type; + } else { + bp->type = 0; + } + mask = (bp->addr) | 1; } else { - if (set) { bp->type |= type; } else { bp->type &= ~type; } + if (set) { + bp->type |= type; + } else { + bp->type &= ~type; + } + mask = (bp->addr) | 1 | (bp->type << 30); } @@ -729,13 +769,13 @@ static int update_code_breakpoint(stlink_t *sl, stm32_addr_t addr, int set) { stlink_write_debug32(sl, 0xe0002008 + id * 4, mask); } - return 0; + return(0); } struct flash_block { stm32_addr_t addr; - unsigned length; + unsigned length; uint8_t* data; struct flash_block* next; @@ -747,13 +787,14 @@ static int flash_add_block(stm32_addr_t addr, unsigned length, stlink_t *sl) { if (addr < FLASH_BASE || addr + length > FLASH_BASE + sl->flash_size) { ELOG("flash_add_block: incorrect bounds\n"); - return -1; + return(-1); } stlink_calculate_pagesize(sl, addr); + if (addr % FLASH_PAGE != 0 || length % FLASH_PAGE != 0) { ELOG("flash_add_block: unaligned block\n"); - return -1; + return(-1); } struct flash_block* new = malloc(sizeof(struct flash_block)); @@ -763,15 +804,15 @@ static int flash_add_block(stm32_addr_t addr, unsigned length, stlink_t *sl) { new->data = calloc(length, 1); flash_root = new; - - return 0; + return(0); } static int flash_populate(stm32_addr_t addr, uint8_t* data, unsigned length) { unsigned int fit_blocks = 0, fit_length = 0; for (struct flash_block* fb = flash_root; fb; fb = fb->next) { - /* Block: ------X------Y-------- + /* + * Block: ------X------Y-------- * Data: a-----b * a--b * a-----------b @@ -781,6 +822,7 @@ static int flash_populate(stm32_addr_t addr, uint8_t* data, unsigned length) { unsigned X = fb->addr, Y = fb->addr + fb->length; unsigned a = addr, b = addr + length; + if (a < Y && b > X) { // from start of the block unsigned start = (a > X ? a : X) - X; @@ -795,7 +837,7 @@ static int flash_populate(stm32_addr_t addr, uint8_t* data, unsigned length) { if (fit_blocks == 0) { ELOG("Unfit data block %08x -> %04x\n", addr, length); - return -1; + return(-1); } if (fit_length != length) { @@ -803,7 +845,7 @@ static int flash_populate(stm32_addr_t addr, uint8_t* data, unsigned length) { WLOG("(this is not an error, just a GDB glitch)\n"); } - return 0; + return(0); } static int flash_go(stlink_t *sl) { @@ -823,17 +865,18 @@ static int flash_go(stlink_t *sl) { stlink_calculate_pagesize(sl, page); DLOG("flash_do: page %08x\n", page); - unsigned len = (length > FLASH_PAGE) ? (unsigned int) FLASH_PAGE : length; + unsigned len = (length > FLASH_PAGE) ? (unsigned int)FLASH_PAGE : length; int ret = stlink_write_flash(sl, page, fb->data + (page - fb->addr), len, 0); - if (ret < 0) goto error; + + if (ret < 0) { goto error; } } } stlink_reset(sl); - error = 0; error: + for (struct flash_block* fb = flash_root, *next; fb; fb = next) { next = fb->next; free(fb->data); @@ -841,8 +884,7 @@ static int flash_go(stlink_t *sl) { } flash_root = NULL; - - return error; + return(error); } #define CLIDR 0xE000ED78 @@ -863,11 +905,11 @@ struct cache_level_desc { }; struct cache_desc_t { - // Minimal line size in bytes + // minimal line size in bytes unsigned int dminline; unsigned int iminline; - // Last level of unification (uniprocessor) + // last level of unification (uniprocessor) unsigned int louu; struct cache_level_desc icache[7]; @@ -879,8 +921,10 @@ static struct cache_desc_t cache_desc; // return the smallest R so that V <= (1 << R); not performance critical static unsigned ceil_log2(unsigned v) { unsigned res; - for (res = 0; (1U << res) < v; res++) ; - return res; + + for (res = 0; (1U << res) < v; res++); + + return(res); } static void read_cache_level_desc(stlink_t *sl, struct cache_level_desc *desc) { @@ -894,7 +938,7 @@ static void read_cache_level_desc(stlink_t *sl, struct cache_level_desc *desc) { log2_nsets = ceil_log2 (desc->nsets); desc->width = 4 + (ccsidr & 7) + log2_nsets; ILOG("%08x LineSize: %u, ways: %u, sets: %u (width: %u)\n", - ccsidr, 4 << (ccsidr & 7), desc->nways, desc->nsets, desc->width); + ccsidr, 4 << (ccsidr & 7), desc->nways, desc->nsets, desc->width); } static void init_cache (stlink_t *sl) { @@ -903,8 +947,8 @@ static void init_cache (stlink_t *sl) { unsigned int ctr; int i; - // Assume only F7 has a cache - if (sl->core_id!=STM32F7_CORE_ID) return; + // assume only F7 has a cache + if (sl->core_id != STM32F7_CORE_ID) { return; } stlink_read_debug32(sl, CLIDR, &clidr); stlink_read_debug32(sl, CCR, &ccr); @@ -914,23 +958,24 @@ static void init_cache (stlink_t *sl) { cache_desc.louu = (clidr >> 27) & 7; ILOG("Chip clidr: %08x, I-Cache: %s, D-Cache: %s\n", - clidr, ccr & CCR_IC ? "on" : "off", ccr & CCR_DC ? "on" : "off"); + clidr, ccr & CCR_IC ? "on" : "off", ccr & CCR_DC ? "on" : "off"); ILOG(" cache: LoUU: %u, LoC: %u, LoUIS: %u\n", - (clidr >> 27) & 7, (clidr >> 24) & 7, (clidr >> 21) & 7); + (clidr >> 27) & 7, (clidr >> 24) & 7, (clidr >> 21) & 7); ILOG(" cache: ctr: %08x, DminLine: %u bytes, IminLine: %u bytes\n", ctr, - cache_desc.dminline, cache_desc.iminline); + cache_desc.dminline, cache_desc.iminline); + for (i = 0; i < 7; i++) { unsigned int ct = (clidr >> (3 * i)) & 0x07; cache_desc.dcache[i].width = 0; cache_desc.icache[i].width = 0; - if (ct == 2 || ct == 3 || ct == 4) { // Data + if (ct == 2 || ct == 3 || ct == 4) { // data stlink_write_debug32(sl, CSSELR, i << 1); ILOG("D-Cache L%d: ", i); read_cache_level_desc(sl, &cache_desc.dcache[i]); } - if (ct == 1 || ct == 3) { // Instruction + if (ct == 1 || ct == 3) { // instruction stlink_write_debug32(sl, CSSELR, (i << 1) | 1); ILOG("I-Cache L%d: ", i); read_cache_level_desc(sl, &cache_desc.icache[i]); @@ -941,7 +986,7 @@ static void init_cache (stlink_t *sl) { static void cache_flush(stlink_t *sl, unsigned ccr) { int level; - if (ccr & CCR_DC) + if (ccr & CCR_DC) { for (level = cache_desc.louu - 1; level >= 0; level--) { struct cache_level_desc *desc = &cache_desc.dcache[level]; unsigned addr; @@ -951,19 +996,25 @@ static void cache_flush(stlink_t *sl, unsigned ccr) { // D-cache clean by set-ways. for (addr = (level << 1); addr < max_addr; addr += cache_desc.dminline) { unsigned int way; - for (way = 0; way < desc->nways; way++) + + for (way = 0; way < desc->nways; way++) { stlink_write_debug32(sl, DCCSW, addr | (way << way_sh)); + } } } + } // invalidate all I-cache to oPU - if (ccr & CCR_IC) stlink_write_debug32(sl, ICIALLU, 0); + if (ccr & CCR_IC) { + stlink_write_debug32(sl, ICIALLU, 0); + } } static int cache_modified; static void cache_change(stm32_addr_t start, unsigned count) { - if (count == 0) return; + if (count == 0) { return; } + (void)start; cache_modified = 1; } @@ -971,12 +1022,14 @@ static void cache_change(stm32_addr_t start, unsigned count) { static void cache_sync(stlink_t *sl) { unsigned ccr; - if (sl->core_id!=STM32F7_CORE_ID) return; - if (!cache_modified) return; - cache_modified = 0; + if (sl->core_id != STM32F7_CORE_ID) { return; } + if (!cache_modified) { return; } + + cache_modified = 0; stlink_read_debug32(sl, CCR, &ccr); - if (ccr & (CCR_IC | CCR_DC)) cache_flush(sl, ccr); + + if (ccr & (CCR_IC | CCR_DC)) { cache_flush(sl, ccr); } } static size_t unhexify(const char *in, char *out, size_t out_count) { @@ -984,55 +1037,60 @@ static size_t unhexify(const char *in, char *out, size_t out_count) { unsigned int c; for (i = 0; i < out_count; i++) { - if (sscanf(in + (2 * i), "%02x", &c) != 1) return i; + if (sscanf(in + (2 * i), "%02x", &c) != 1) { return(i); } + out[i] = (char)c; } - return i; + return(i); } int serve(stlink_t *sl, st_state_t *st) { SOCKET sock = socket(AF_INET, SOCK_STREAM, 0); + if (!IS_SOCK_VALID(sock)) { perror("socket"); - return 1; + return(1); } unsigned int val = 1; setsockopt(sock, SOL_SOCKET, SO_REUSEADDR, (char *)&val, sizeof(val)); struct sockaddr_in serv_addr; - memset(&serv_addr,0,sizeof(struct sockaddr_in)); + memset(&serv_addr, 0, sizeof(struct sockaddr_in)); serv_addr.sin_family = AF_INET; serv_addr.sin_addr.s_addr = INADDR_ANY; serv_addr.sin_port = htons(st->listen_port); - if (bind(sock, (struct sockaddr *) &serv_addr, sizeof(serv_addr)) < 0) { + if (bind(sock, (struct sockaddr *)&serv_addr, sizeof(serv_addr)) < 0) { perror("bind"); close_socket(sock); - return 1; + return(1); } if (listen(sock, 5) < 0) { perror("listen"); close_socket(sock); - return 1; + return(1); } ILOG("Listening at *:%d...\n", st->listen_port); SOCKET client = accept(sock, NULL, NULL); - //signal (SIGINT, SIG_DFL); + + // signal (SIGINT, SIG_DFL); if (!IS_SOCK_VALID(client)) { perror("accept"); close_socket(sock); - return 1; + return(1); } close_socket(sock); stlink_force_debug(sl); - if (st->reset) stlink_reset(sl); + + if (st->reset) { stlink_reset(sl); } + init_code_breakpoints(sl); init_data_watchpoints(sl); @@ -1052,10 +1110,11 @@ int serve(stlink_t *sl, st_state_t *st) { char* packet; int status = gdb_recv_packet(client, &packet); + if (status < 0) { ELOG("cannot recv: %d\n", status); close_socket(client); - return 1; + return(1); } DLOG("recv: %s\n", packet); @@ -1063,686 +1122,736 @@ int serve(stlink_t *sl, st_state_t *st) { char* reply = NULL; struct stlink_reg regp; - switch(packet[0]) { - case 'q': { - if (packet[1] == 'P' || packet[1] == 'C' || packet[1] == 'L') { - reply = strdup(""); - break; - } + switch (packet[0]) { + case 'q': { + if (packet[1] == 'P' || packet[1] == 'C' || packet[1] == 'L') { + reply = strdup(""); + break; + } - char *separator = strstr(packet, ":"), *params = ""; - if (separator == NULL) { - separator = packet + strlen(packet); + char *separator = strstr(packet, ":"), *params = ""; + + if (separator == NULL) { + separator = packet + strlen(packet); + } else { + params = separator + 1; + } + + unsigned queryNameLength = (unsigned int)(separator - &packet[1]); + char* queryName = calloc(queryNameLength + 1, 1); + strncpy(queryName, &packet[1], queryNameLength); + + DLOG("query: %s;%s\n", queryName, params); + + if (!strcmp(queryName, "Supported")) { + if (sl->chip_id == STLINK_CHIPID_STM32_F4 || + sl->chip_id == STLINK_CHIPID_STM32_F4_HD || + sl->core_id == STM32F7_CORE_ID) { + reply = strdup("PacketSize=3fff;qXfer:memory-map:read+;qXfer:features:read+"); } else { - params = separator + 1; + reply = strdup("PacketSize=3fff;qXfer:memory-map:read+"); } + } else if (!strcmp(queryName, "Xfer")) { + char *type, *op, *__s_addr, *s_length; + char *tok = params; + char *annex __attribute__((unused)); - unsigned queryNameLength = (unsigned int) (separator - &packet[1]); - char* queryName = calloc(queryNameLength + 1, 1); - strncpy(queryName, &packet[1], queryNameLength); + type = strsep(&tok, ":"); + op = strsep(&tok, ":"); + annex = strsep(&tok, ":"); + __s_addr = strsep(&tok, ","); + s_length = tok; - DLOG("query: %s;%s\n", queryName, params); + unsigned addr = (unsigned int)strtoul(__s_addr, NULL, 16), + length = (unsigned int)strtoul(s_length, NULL, 16); - if (!strcmp(queryName, "Supported")) { - if (sl->chip_id==STLINK_CHIPID_STM32_F4 || - sl->chip_id==STLINK_CHIPID_STM32_F4_HD || - sl->core_id==STM32F7_CORE_ID) { - reply = strdup("PacketSize=3fff;qXfer:memory-map:read+;qXfer:features:read+"); - } else { - reply = strdup("PacketSize=3fff;qXfer:memory-map:read+"); - } - } else if (!strcmp(queryName, "Xfer")) { - char *type, *op, *__s_addr, *s_length; - char *tok = params; - char *annex __attribute__((unused)); - - type = strsep(&tok, ":"); - op = strsep(&tok, ":"); - annex = strsep(&tok, ":"); - __s_addr = strsep(&tok, ","); - s_length = tok; - - unsigned addr = (unsigned int) strtoul(__s_addr, NULL, 16), - length = (unsigned int) strtoul(s_length, NULL, 16); - - DLOG("Xfer: type:%s;op:%s;annex:%s;addr:%d;length:%d\n", - type, op, annex, addr, length); - - const char* data = NULL; - - if (!strcmp(type, "memory-map") && !strcmp(op, "read")) - data = current_memory_map; - - if (!strcmp(type, "features") && !strcmp(op, "read")) - data = target_description_F4; - - if (data) { - unsigned data_length = (unsigned int) strlen(data); - if (addr + length > data_length) - length = data_length - addr; - if (length == 0) { - reply = strdup("l"); - } else { - reply = calloc(length + 2, 1); - reply[0] = 'm'; - strncpy(&reply[1], data, length); - } - } - } else if (!strncmp(queryName, "Rcmd,",4)) { - // Rcmd uses the wrong separator - separator = strstr(packet, ","); - params = ""; - if (separator == NULL) { - separator = packet + strlen(packet); - } else { - params = separator + 1; - } + DLOG("Xfer: type:%s;op:%s;annex:%s;addr:%d;length:%d\n", + type, op, annex, addr, length); - size_t hex_len = strlen(params); - size_t alloc_size = (hex_len / 2) + 1; - size_t cmd_len; - char *cmd = malloc(alloc_size); + const char* data = NULL; - if (cmd == NULL) { - DLOG("Rcmd unhexify allocation error\n"); - break; - } + if (!strcmp(type, "memory-map") && !strcmp(op, "read")) { + data = current_memory_map; + } - cmd_len = unhexify(params, cmd, alloc_size - 1); - cmd[cmd_len] = 0; + if (!strcmp(type, "features") && !strcmp(op, "read")) { + data = target_description_F4; + } - DLOG("unhexified Rcmd: '%s'\n", cmd); + if (data) { + unsigned data_length = (unsigned int)strlen(data); - if (!strncmp(cmd, "resume", 6)) { // resume - DLOG("Rcmd: resume\n"); - cache_sync(sl); - ret = stlink_run(sl); - if (ret) { - DLOG("Rcmd: resume failed\n"); - reply = strdup("E00"); - } else { - reply = strdup("OK"); - } - - } else if (!strncmp(cmd, "halt", 4)) { // halt - ret = stlink_force_debug(sl); - if (ret) { - DLOG("Rcmd: halt failed\n"); - reply = strdup("E00"); - } else { - reply = strdup("OK"); - DLOG("Rcmd: halt\n"); - } - - } else if (!strncmp(cmd, "jtag_reset", 10)) { // jtag_reset - reply = strdup("OK"); + if (addr + length > data_length) { length = data_length - addr; } - ret = stlink_jtag_reset(sl, 0); - if (ret) { - DLOG("Rcmd: jtag_reset failed with jtag_reset\n"); - reply = strdup("E00"); - } - - ret = stlink_jtag_reset(sl, 1); - if (ret) { - DLOG("Rcmd: jtag_reset failed with jtag_reset\n"); - reply = strdup("E00"); - } - - ret = stlink_force_debug(sl); - if (ret) { - DLOG("Rcmd: jtag_reset failed with force_debug\n"); - reply = strdup("E00"); - } - - if (strcmp(reply, "E00")) { - // no errors have been found - DLOG("Rcmd: jtag_reset\n"); - } - } else if (!strncmp(cmd, "reset", 5)) { //reset - - ret = stlink_force_debug(sl); - if (ret) { - DLOG("Rcmd: reset failed with force_debug\n"); - reply = strdup("E00"); - } - - ret = stlink_reset(sl); - if (ret) { - DLOG("Rcmd: reset failed with reset\n"); - reply = strdup("E00"); - } - - init_code_breakpoints(sl); - init_data_watchpoints(sl); - - if (reply == NULL) { - reply = strdup("OK"); - DLOG("Rcmd: reset\n"); - } - - } else if (!strncmp(cmd, "semihosting ", 12)) { - DLOG("Rcmd: got semihosting cmd '%s'", cmd); - char *arg = cmd + 12; - - // Skip whitespaces - while (isspace(*arg)) { arg++; } - - if (!strncmp(arg, "enable", 6) || !strncmp(arg, "1", 1)) { - semihosting = true; - reply = strdup("OK"); - } else if (!strncmp(arg, "disable", 7) || !strncmp(arg, "0", 1)) { - semihosting = false; - reply = strdup("OK"); - } else { - DLOG("Rcmd: unknown semihosting arg: '%s'\n", arg); - } + if (length == 0) { + reply = strdup("l"); } else { - DLOG("Rcmd: %s\n", cmd); + reply = calloc(length + 2, 1); + reply[0] = 'm'; + strncpy(&reply[1], data, length); } - free(cmd); } + } else if (!strncmp(queryName, "Rcmd,", 4)) { + // Rcmd uses the wrong separator + separator = strstr(packet, ","); + params = ""; - if (reply == NULL) - reply = strdup(""); + if (separator == NULL) { + separator = packet + strlen(packet); + } else { + params = separator + 1; + } - free(queryName); + size_t hex_len = strlen(params); + size_t alloc_size = (hex_len / 2) + 1; + size_t cmd_len; + char *cmd = malloc(alloc_size); - break; - } - - case 'v': { - char *params = NULL; - char *cmdName = strtok_r(packet, ":;", ¶ms); + if (cmd == NULL) { + DLOG("Rcmd unhexify allocation error\n"); + break; + } - cmdName++; // vCommand -> Command + cmd_len = unhexify(params, cmd, alloc_size - 1); + cmd[cmd_len] = 0; - if (!strcmp(cmdName, "FlashErase")) { - char *__s_addr, *s_length; - char *tok = params; + DLOG("unhexified Rcmd: '%s'\n", cmd); - __s_addr = strsep(&tok, ","); - s_length = tok; + if (!strncmp(cmd, "resume", 6)) { // resume + DLOG("Rcmd: resume\n"); + cache_sync(sl); + ret = stlink_run(sl); - unsigned addr = (unsigned int) strtoul(__s_addr, NULL, 16), - length = (unsigned int) strtoul(s_length, NULL, 16); + if (ret) { + DLOG("Rcmd: resume failed\n"); + reply = strdup("E00"); + } else { + reply = strdup("OK"); + } - DLOG("FlashErase: addr:%08x,len:%04x\n", - addr, length); + } else if (!strncmp(cmd, "halt", 4)) { // halt + ret = stlink_force_debug(sl); - if (flash_add_block(addr, length, sl) < 0) { + if (ret) { + DLOG("Rcmd: halt failed\n"); reply = strdup("E00"); } else { reply = strdup("OK"); + DLOG("Rcmd: halt\n"); } - } else if (!strcmp(cmdName, "FlashWrite")) { - char *__s_addr, *data; - char *tok = params; - - __s_addr = strsep(&tok, ":"); - data = tok; - - unsigned addr = (unsigned int) strtoul(__s_addr, NULL, 16); - unsigned data_length = status - (unsigned int) (data - packet); - - // Length of decoded data cannot be more than encoded, as escapes are removed. - // Additional byte is reserved for alignment fix. - uint8_t *decoded = calloc(data_length + 1, 1); - unsigned dec_index = 0; - for (unsigned int i = 0; i < data_length; i++) { - if (data[i] == 0x7d) { - i++; - decoded[dec_index++] = data[i] ^ 0x20; - } else { - decoded[dec_index++] = data[i]; - } + + } else if (!strncmp(cmd, "jtag_reset", 10)) { // jtag_reset + reply = strdup("OK"); + ret = stlink_jtag_reset(sl, 0); + + if (ret) { + DLOG("Rcmd: jtag_reset failed with jtag_reset\n"); + reply = strdup("E00"); } - // fix alignment - if (dec_index % 2 != 0) dec_index++; + ret = stlink_jtag_reset(sl, 1); - DLOG("binary packet %d -> %d\n", data_length, dec_index); + if (ret) { + DLOG("Rcmd: jtag_reset failed with jtag_reset\n"); + reply = strdup("E00"); + } - if (flash_populate(addr, decoded, dec_index) < 0) { + ret = stlink_force_debug(sl); + + if (ret) { + DLOG("Rcmd: jtag_reset failed with force_debug\n"); reply = strdup("E00"); - } else { - reply = strdup("OK"); } - free(decoded); - } else if (!strcmp(cmdName, "FlashDone")) { - if (flash_go(sl) < 0) { + if (strcmp(reply, "E00")) { + // no errors have been found + DLOG("Rcmd: jtag_reset\n"); + } + } else if (!strncmp(cmd, "reset", 5)) { // reset + + ret = stlink_force_debug(sl); + + if (ret) { + DLOG("Rcmd: reset failed with force_debug\n"); reply = strdup("E00"); - } else { - reply = strdup("OK"); } - } else if (!strcmp(cmdName, "Kill")) { - attached = 0; - reply = strdup("OK"); - } - if (reply == NULL) - reply = strdup(""); + ret = stlink_reset(sl); - break; - } + if (ret) { + DLOG("Rcmd: reset failed with reset\n"); + reply = strdup("E00"); + } + + init_code_breakpoints(sl); + init_data_watchpoints(sl); - case 'c': - cache_sync(sl); - ret = stlink_run(sl); - if (ret) DLOG("Semihost: run failed\n"); - - while (1) { - status = gdb_check_for_interrupt(client); - if (status < 0) { - ELOG("cannot check for int: %d\n", status); - close_socket(client); - return 1; + if (reply == NULL) { + reply = strdup("OK"); + DLOG("Rcmd: reset\n"); } - if (status == 1) { - stlink_force_debug(sl); - break; + } else if (!strncmp(cmd, "semihosting ", 12)) { + DLOG("Rcmd: got semihosting cmd '%s'", cmd); + char *arg = cmd + 12; + + while (isspace(*arg)) { arg++; } // skip whitespaces + + if (!strncmp(arg, "enable", 6) || !strncmp(arg, "1", 1)) { + semihosting = true; + reply = strdup("OK"); + } else if (!strncmp(arg, "disable", 7) || !strncmp(arg, "0", 1)) { + semihosting = false; + reply = strdup("OK"); + } else { + DLOG("Rcmd: unknown semihosting arg: '%s'\n", arg); } + } else { + DLOG("Rcmd: %s\n", cmd); + } - ret = stlink_status(sl); - if (ret) DLOG("Semihost: status failed\n"); - if(sl->core_stat == TARGET_HALTED) { - struct stlink_reg reg; - stm32_addr_t pc; - stm32_addr_t addr; - int offset = 0; - uint16_t insn; + free(cmd); + } - if (!semihosting) break; + if (reply == NULL) { reply = strdup(""); } - ret = stlink_read_all_regs (sl, ®); - if (ret) DLOG("Semihost: read_all_regs failed\n"); + free(queryName); + break; + } - // Read PC - pc = reg.r[15]; + case 'v': { + char *params = NULL; + char *cmdName = strtok_r(packet, ":;", ¶ms); - // Compute aligned value - offset = pc % 4; - addr = pc - offset; + cmdName++; // vCommand -> Command - // Read instructions (address and length must be aligned). - ret = stlink_read_mem32(sl, addr, (offset > 2 ? 8 : 4)); + if (!strcmp(cmdName, "FlashErase")) { + char *__s_addr, *s_length; + char *tok = params; - if (ret != 0) { - DLOG("Semihost: cannot read instructions at: 0x%08x\n", addr); - break; - } + __s_addr = strsep(&tok, ","); + s_length = tok; - memcpy(&insn, &sl->q_buf[offset], sizeof(insn)); + unsigned addr = (unsigned int)strtoul(__s_addr, NULL, 16), + length = (unsigned int)strtoul(s_length, NULL, 16); - if (insn == 0xBEAB && !has_breakpoint(addr)) { + DLOG("FlashErase: addr:%08x,len:%04x\n", + addr, length); - ret = do_semihosting (sl, reg.r[0], reg.r[1], ®.r[0]); - if (ret) DLOG("Semihost: do_semihosting failed\n"); + if (flash_add_block(addr, length, sl) < 0) { + reply = strdup("E00"); + } else { + reply = strdup("OK"); + } + } else if (!strcmp(cmdName, "FlashWrite")) { + char *__s_addr, *data; + char *tok = params; - // Write return value - ret = stlink_write_reg(sl, reg.r[0], 0); - if (ret) DLOG("Semihost: write_reg failed for return value\n"); + __s_addr = strsep(&tok, ":"); + data = tok; - // Jump over the break instruction - ret = stlink_write_reg(sl, reg.r[15] + 2, 15); - if (ret) DLOG("Semihost: write_reg failed for jumping over break\n"); + unsigned addr = (unsigned int)strtoul(__s_addr, NULL, 16); + unsigned data_length = status - (unsigned int)(data - packet); - // Continue execution - cache_sync(sl); - ret = stlink_run(sl); - if (ret) DLOG("Semihost: continue execution failed with stlink_run\n"); - } else { - break; - } - } + // Length of decoded data cannot be more than encoded, as escapes are removed. + // Additional byte is reserved for alignment fix. + uint8_t *decoded = calloc(data_length + 1, 1); + unsigned dec_index = 0; - usleep(100000); + for (unsigned int i = 0; i < data_length; i++) { + if (data[i] == 0x7d) { + i++; + decoded[dec_index++] = data[i] ^ 0x20; + } else { + decoded[dec_index++] = data[i]; + } } - reply = strdup("S05"); // TRAP - break; + // fix alignment + if (dec_index % 2 != 0) { dec_index++; } + + DLOG("binary packet %d -> %d\n", data_length, dec_index); - case 's': - cache_sync(sl); - ret = stlink_step(sl); - if (ret) { - // ... having a problem sending step packet - ELOG("Step: cannot send step request\n"); + if (flash_populate(addr, decoded, dec_index) < 0) { reply = strdup("E00"); - critical_error = 1; // absolutely critical } else { - reply = strdup("S05"); // TRAP + reply = strdup("OK"); } - break; - - case '?': - if (attached) { - reply = strdup("S05"); // TRAP + free(decoded); + } else if (!strcmp(cmdName, "FlashDone")) { + if (flash_go(sl) < 0) { + reply = strdup("E00"); } else { - // Stub shall reply OK if not attached. reply = strdup("OK"); } - break; + } else if (!strcmp(cmdName, "Kill")) { + attached = 0; + reply = strdup("OK"); + } - case 'g': - ret = stlink_read_all_regs(sl, ®p); - if (ret) DLOG("g packet: read_all_regs failed\n"); + if (reply == NULL) { reply = strdup(""); } - reply = calloc(8 * 16 + 1, 1); - for (int i = 0; i < 16; i++) - sprintf(&reply[i * 8], "%08x", (uint32_t)htonl(regp.r[i])); - break; + break; + } - case 'p': { - unsigned id = (unsigned int) strtoul(&packet[1], NULL, 16); - unsigned myreg = 0xDEADDEAD; - - if (id < 16) { - ret = stlink_read_reg(sl, id, ®p); - myreg = htonl(regp.r[id]); - } else if (id == 0x19) { - ret = stlink_read_reg(sl, 16, ®p); - myreg = htonl(regp.xpsr); - } else if (id == 0x1A) { - ret = stlink_read_reg(sl, 17, ®p); - myreg = htonl(regp.main_sp); - } else if (id == 0x1B) { - ret = stlink_read_reg(sl, 18, ®p); - myreg = htonl(regp.process_sp); - } else if (id == 0x1C) { - ret = stlink_read_unsupported_reg(sl, id, ®p); - myreg = htonl(regp.control); - } else if (id == 0x1D) { - ret = stlink_read_unsupported_reg(sl, id, ®p); - myreg = htonl(regp.faultmask); - } else if (id == 0x1E) { - ret = stlink_read_unsupported_reg(sl, id, ®p); - myreg = htonl(regp.basepri); - } else if (id == 0x1F) { - ret = stlink_read_unsupported_reg(sl, id, ®p); - myreg = htonl(regp.primask); - } else if (id >= 0x20 && id < 0x40) { - ret = stlink_read_unsupported_reg(sl, id, ®p); - myreg = htonl(regp.s[id-0x20]); - } else if (id == 0x40) { - ret = stlink_read_unsupported_reg(sl, id, ®p); - myreg = htonl(regp.fpscr); - } else { - ret = 1; - reply = strdup("E00"); + case 'c': + cache_sync(sl); + ret = stlink_run(sl); + + if (ret) { DLOG("Semihost: run failed\n"); } + + while (1) { + status = gdb_check_for_interrupt(client); + + if (status < 0) { + ELOG("cannot check for int: %d\n", status); + close_socket(client); + return(1); } - if (ret) DLOG("p packet: stlink_read_unsupported_reg failed with id %u\n", id); - if (reply == NULL) { - // If reply is set to "E00", skip - reply = calloc(8 + 1, 1); - sprintf(reply, "%08x", myreg); + if (status == 1) { + stlink_force_debug(sl); + break; } - break; - } + ret = stlink_status(sl); - case 'P': { - char* s_reg = &packet[1]; - char* s_value = strstr(&packet[1], "=") + 1; - - unsigned reg = (unsigned int) strtoul(s_reg, NULL, 16); - unsigned value = (unsigned int) strtoul(s_value, NULL, 16); - - - if (reg < 16) { - ret = stlink_write_reg(sl, ntohl(value), reg); - } else if (reg == 0x19) { - ret = stlink_write_reg(sl, ntohl(value), 16); - } else if (reg == 0x1A) { - ret = stlink_write_reg(sl, ntohl(value), 17); - } else if (reg == 0x1B) { - ret = stlink_write_reg(sl, ntohl(value), 18); - } else if (reg == 0x1C) { - ret = stlink_write_unsupported_reg(sl, ntohl(value), reg, ®p); - } else if (reg == 0x1D) { - ret = stlink_write_unsupported_reg(sl, ntohl(value), reg, ®p); - } else if (reg == 0x1E) { - ret = stlink_write_unsupported_reg(sl, ntohl(value), reg, ®p); - } else if (reg == 0x1F) { - ret = stlink_write_unsupported_reg(sl, ntohl(value), reg, ®p); - } else if (reg >= 0x20 && reg < 0x40) { - ret = stlink_write_unsupported_reg(sl, ntohl(value), reg, ®p); - } else if (reg == 0x40) { - ret = stlink_write_unsupported_reg(sl, ntohl(value), reg, ®p); - } else { - ret = 1; - reply = strdup("E00"); + if (ret) { DLOG("Semihost: status failed\n"); } + + if (sl->core_stat == TARGET_HALTED) { + struct stlink_reg reg; + stm32_addr_t pc; + stm32_addr_t addr; + int offset = 0; + uint16_t insn; + + if (!semihosting) { break; } + + ret = stlink_read_all_regs (sl, ®); + + if (ret) { DLOG("Semihost: read_all_regs failed\n"); } + + // read PC + pc = reg.r[15]; + + // compute aligned value + offset = pc % 4; + addr = pc - offset; + + // read instructions (address and length must be aligned). + ret = stlink_read_mem32(sl, addr, (offset > 2 ? 8 : 4)); + + if (ret != 0) { + DLOG("Semihost: cannot read instructions at: 0x%08x\n", addr); + break; + } + + memcpy(&insn, &sl->q_buf[offset], sizeof(insn)); + + if (insn == 0xBEAB && !has_breakpoint(addr)) { + + ret = do_semihosting (sl, reg.r[0], reg.r[1], ®.r[0]); + + if (ret) { DLOG("Semihost: do_semihosting failed\n"); } + + // write return value + ret = stlink_write_reg(sl, reg.r[0], 0); + + if (ret) { DLOG("Semihost: write_reg failed for return value\n"); } + + // jump over the break instruction + ret = stlink_write_reg(sl, reg.r[15] + 2, 15); + + if (ret) { DLOG("Semihost: write_reg failed for jumping over break\n"); } + + // continue execution + cache_sync(sl); + ret = stlink_run(sl); + + if (ret) { DLOG("Semihost: continue execution failed with stlink_run\n"); } + } else { + break; + } } - if (ret) DLOG("P packet: stlink_write_unsupported_reg failed with reg %u\n", reg); - if (reply == NULL) reply = strdup("OK"); // note that NULL may not be zero - break; + usleep(100000); } - case 'G': - for (int i = 0; i < 16; i++) { - char str[9] = {0}; - strncpy(str, &packet[1 + i * 8], 8); - uint32_t reg = (uint32_t) strtoul(str, NULL, 16); - ret = stlink_write_reg(sl, ntohl(reg), i); - if (ret) DLOG("G packet: stlink_write_reg failed"); - } + reply = strdup("S05"); // TRAP + break; - reply = strdup("OK"); - break; + case 's': + cache_sync(sl); + ret = stlink_step(sl); - case 'm': { - char* s_start = &packet[1]; - char* s_count = strstr(&packet[1], ",") + 1; + if (ret) { + // ... having a problem sending step packet + ELOG("Step: cannot send step request\n"); + reply = strdup("E00"); + critical_error = 1; // absolutely critical + } else { + reply = strdup("S05"); // TRAP + } - stm32_addr_t start = (stm32_addr_t) strtoul(s_start, NULL, 16); - unsigned count = (unsigned int) strtoul(s_count, NULL, 16); + break; - unsigned adj_start = start % 4; - unsigned count_rnd = (count + adj_start + 4 - 1) / 4 * 4; - if (count_rnd > sl->flash_pgsz) count_rnd = (unsigned int) sl->flash_pgsz; - if (count_rnd > 0x1800) count_rnd = 0x1800; - if (count_rnd < count) count = count_rnd; + case '?': - if (stlink_read_mem32(sl, start - adj_start, count_rnd) != 0) count = 0; - // read failed somehow, don't return stale buffer + if (attached) { + reply = strdup("S05"); // TRAP + } else { + reply = strdup("OK"); // stub shall reply OK if not attached + } - reply = calloc(count * 2 + 1, 1); - for (unsigned int i = 0; i < count; i++) { - reply[i * 2 + 0] = hex[sl->q_buf[i + adj_start] >> 4]; - reply[i * 2 + 1] = hex[sl->q_buf[i + adj_start] & 0xf]; - } + break; - break; + case 'g': + ret = stlink_read_all_regs(sl, ®p); + + if (ret) { DLOG("g packet: read_all_regs failed\n"); } + + reply = calloc(8 * 16 + 1, 1); + + for (int i = 0; i < 16; i++) { + sprintf(&reply[i * 8], "%08x", (uint32_t)htonl(regp.r[i])); } - case 'M': { - char* s_start = &packet[1]; - char* s_count = strstr(&packet[1], ",") + 1; - char* hexdata = strstr(packet, ":") + 1; - - stm32_addr_t start = (stm32_addr_t) strtoul(s_start, NULL, 16); - unsigned count = (unsigned int) strtoul(s_count, NULL, 16); - int err = 0; - - if (start % 4) { - unsigned align_count = 4 - start % 4; - if (align_count > count) align_count = count; - for (unsigned int i = 0; i < align_count; i ++) { - char hextmp[3] = { hexdata[i*2], hexdata[i*2+1], 0 }; - uint8_t byte = strtoul(hextmp, NULL, 16); - sl->q_buf[i] = byte; - } - err |= stlink_write_mem8(sl, start, align_count); - cache_change(start, align_count); - start += align_count; - count -= align_count; - hexdata += 2*align_count; - } + break; - if (count - count % 4) { - unsigned aligned_count = count - count % 4; + case 'p': { + unsigned id = (unsigned int)strtoul(&packet[1], NULL, 16); + unsigned myreg = 0xDEADDEAD; + + if (id < 16) { + ret = stlink_read_reg(sl, id, ®p); + myreg = htonl(regp.r[id]); + } else if (id == 0x19) { + ret = stlink_read_reg(sl, 16, ®p); + myreg = htonl(regp.xpsr); + } else if (id == 0x1A) { + ret = stlink_read_reg(sl, 17, ®p); + myreg = htonl(regp.main_sp); + } else if (id == 0x1B) { + ret = stlink_read_reg(sl, 18, ®p); + myreg = htonl(regp.process_sp); + } else if (id == 0x1C) { + ret = stlink_read_unsupported_reg(sl, id, ®p); + myreg = htonl(regp.control); + } else if (id == 0x1D) { + ret = stlink_read_unsupported_reg(sl, id, ®p); + myreg = htonl(regp.faultmask); + } else if (id == 0x1E) { + ret = stlink_read_unsupported_reg(sl, id, ®p); + myreg = htonl(regp.basepri); + } else if (id == 0x1F) { + ret = stlink_read_unsupported_reg(sl, id, ®p); + myreg = htonl(regp.primask); + } else if (id >= 0x20 && id < 0x40) { + ret = stlink_read_unsupported_reg(sl, id, ®p); + myreg = htonl(regp.s[id - 0x20]); + } else if (id == 0x40) { + ret = stlink_read_unsupported_reg(sl, id, ®p); + myreg = htonl(regp.fpscr); + } else { + ret = 1; + reply = strdup("E00"); + } - for (unsigned int i = 0; i < aligned_count; i ++) { - char hextmp[3] = { hexdata[i*2], hexdata[i*2+1], 0 }; - uint8_t byte = strtoul(hextmp, NULL, 16); - sl->q_buf[i] = byte; - } - err |= stlink_write_mem32(sl, start, aligned_count); - cache_change(start, aligned_count); - count -= aligned_count; - start += aligned_count; - hexdata += 2*aligned_count; - } + if (ret) { DLOG("p packet: stlink_read_unsupported_reg failed with id %u\n", id); } - if (count) { - for (unsigned int i = 0; i < count; i ++) { - char hextmp[3] = { hexdata[i*2], hexdata[i*2+1], 0 }; - uint8_t byte = strtoul(hextmp, NULL, 16); - sl->q_buf[i] = byte; - } - err |= stlink_write_mem8(sl, start, count); - cache_change(start, count); - } - reply = strdup(err ? "E00" : "OK"); - break; + if (reply == NULL) { + // if reply is set to "E00", skip + reply = calloc(8 + 1, 1); + sprintf(reply, "%08x", myreg); } - case 'Z': { - char *endptr; - stm32_addr_t addr = (stm32_addr_t) strtoul(&packet[3], &endptr, 16); - stm32_addr_t len = (stm32_addr_t) strtoul(&endptr[1], NULL, 16); - - switch (packet[1]) { - case '1': - if (update_code_breakpoint(sl, addr, 1) < 0) { - reply = strdup("E00"); - } else { - reply = strdup("OK"); - } - break; + break; + } - case '2': // insert write watchpoint - case '3': // insert read watchpoint - case '4': { // insert access watchpoint - enum watchfun wf; - if (packet[1] == '2') { - wf = WATCHWRITE; - } else if (packet[1] == '3') { - wf = WATCHREAD; - } else { - wf = WATCHACCESS; - } - - if (add_data_watchpoint(sl, wf, addr, len) < 0) { - reply = strdup("E00"); - } else { - reply = strdup("OK"); - break; - } - } - break; + case 'P': { + char* s_reg = &packet[1]; + char* s_value = strstr(&packet[1], "=") + 1; + + unsigned reg = (unsigned int)strtoul(s_reg, NULL, 16); + unsigned value = (unsigned int)strtoul(s_value, NULL, 16); + + + if (reg < 16) { + ret = stlink_write_reg(sl, ntohl(value), reg); + } else if (reg == 0x19) { + ret = stlink_write_reg(sl, ntohl(value), 16); + } else if (reg == 0x1A) { + ret = stlink_write_reg(sl, ntohl(value), 17); + } else if (reg == 0x1B) { + ret = stlink_write_reg(sl, ntohl(value), 18); + } else if (reg == 0x1C) { + ret = stlink_write_unsupported_reg(sl, ntohl(value), reg, ®p); + } else if (reg == 0x1D) { + ret = stlink_write_unsupported_reg(sl, ntohl(value), reg, ®p); + } else if (reg == 0x1E) { + ret = stlink_write_unsupported_reg(sl, ntohl(value), reg, ®p); + } else if (reg == 0x1F) { + ret = stlink_write_unsupported_reg(sl, ntohl(value), reg, ®p); + } else if (reg >= 0x20 && reg < 0x40) { + ret = stlink_write_unsupported_reg(sl, ntohl(value), reg, ®p); + } else if (reg == 0x40) { + ret = stlink_write_unsupported_reg(sl, ntohl(value), reg, ®p); + } else { + ret = 1; + reply = strdup("E00"); + } - default: - reply = strdup(""); - } - break; + if (ret) { DLOG("P packet: stlink_write_unsupported_reg failed with reg %u\n", reg); } + + if (reply == NULL) { reply = strdup("OK"); /* Note: NULL may not be zero */ } + + break; + } + + case 'G': + + for (int i = 0; i < 16; i++) { + char str[9] = {0}; + strncpy(str, &packet[1 + i * 8], 8); + uint32_t reg = (uint32_t)strtoul(str, NULL, 16); + ret = stlink_write_reg(sl, ntohl(reg), i); + + if (ret) { DLOG("G packet: stlink_write_reg failed"); } } - case 'z': { - char *endptr; - stm32_addr_t addr = (stm32_addr_t) strtoul(&packet[3], &endptr, 16); - //stm32_addr_t len = strtoul(&endptr[1], NULL, 16); - - switch (packet[1]) { - case '1': // remove breakpoint - update_code_breakpoint(sl, addr, 0); - reply = strdup("OK"); - break; - case '2' : // remove write watchpoint - case '3' : // remove read watchpoint - case '4' : // remove access watchpoint - if (delete_data_watchpoint(sl, addr) < 0) { - reply = strdup("E00"); - break; - } else { - reply = strdup("OK"); - break; - } - - default: - reply = strdup(""); - } - break; + reply = strdup("OK"); + break; + + case 'm': { + char* s_start = &packet[1]; + char* s_count = strstr(&packet[1], ",") + 1; + + stm32_addr_t start = (stm32_addr_t)strtoul(s_start, NULL, 16); + unsigned count = (unsigned int)strtoul(s_count, NULL, 16); + + unsigned adj_start = start % 4; + unsigned count_rnd = (count + adj_start + 4 - 1) / 4 * 4; + + if (count_rnd > sl->flash_pgsz) { count_rnd = (unsigned int)sl->flash_pgsz; } + + if (count_rnd > 0x1800) { count_rnd = 0x1800; } + + if (count_rnd < count) { count = count_rnd; } + + if (stlink_read_mem32(sl, start - adj_start, count_rnd) != 0) { count = 0; } + + // read failed somehow, don't return stale buffer + + reply = calloc(count * 2 + 1, 1); + + for (unsigned int i = 0; i < count; i++) { + reply[i * 2 + 0] = hex[sl->q_buf[i + adj_start] >> 4]; + reply[i * 2 + 1] = hex[sl->q_buf[i + adj_start] & 0xf]; } - case '!': { - // Enter extended mode which allows restarting. We do support that always. + break; + } - // Also, set to persistent mode to allow GDB disconnect. - st->persistent = 1; + case 'M': { + char* s_start = &packet[1]; + char* s_count = strstr(&packet[1], ",") + 1; + char* hexdata = strstr(packet, ":") + 1; - reply = strdup("OK"); + stm32_addr_t start = (stm32_addr_t)strtoul(s_start, NULL, 16); + unsigned count = (unsigned int)strtoul(s_count, NULL, 16); + int err = 0; - break; + if (start % 4) { + unsigned align_count = 4 - start % 4; + + if (align_count > count) { align_count = count; } + + for (unsigned int i = 0; i < align_count; i++) { + char hextmp[3] = { hexdata[i * 2], hexdata[i * 2 + 1], 0 }; + uint8_t byte = strtoul(hextmp, NULL, 16); + sl->q_buf[i] = byte; + } + + err |= stlink_write_mem8(sl, start, align_count); + cache_change(start, align_count); + start += align_count; + count -= align_count; + hexdata += 2 * align_count; } - case 'R': { - // Reset the core. - ret = stlink_reset(sl); - if (ret) { - DLOG("R packet : stlink_reset failed\n"); + if (count - count % 4) { + unsigned aligned_count = count - count % 4; + + for (unsigned int i = 0; i < aligned_count; i++) { + char hextmp[3] = { hexdata[i * 2], hexdata[i * 2 + 1], 0 }; + uint8_t byte = strtoul(hextmp, NULL, 16); + sl->q_buf[i] = byte; } - init_code_breakpoints(sl); - init_data_watchpoints(sl); - attached = 1; + err |= stlink_write_mem32(sl, start, aligned_count); + cache_change(start, aligned_count); + count -= aligned_count; + start += aligned_count; + hexdata += 2 * aligned_count; + } - reply = strdup("OK"); + if (count) { + for (unsigned int i = 0; i < count; i++) { + char hextmp[3] = { hexdata[i * 2], hexdata[i * 2 + 1], 0 }; + uint8_t byte = strtoul(hextmp, NULL, 16); + sl->q_buf[i] = byte; + } + + err |= stlink_write_mem8(sl, start, count); + cache_change(start, count); + } + + reply = strdup(err ? "E00" : "OK"); + break; + } + + case 'Z': { + char *endptr; + stm32_addr_t addr = (stm32_addr_t)strtoul(&packet[3], &endptr, 16); + stm32_addr_t len = (stm32_addr_t)strtoul(&endptr[1], NULL, 16); + + switch (packet[1]) { + case '1': + + if (update_code_breakpoint(sl, addr, 1) < 0) { + reply = strdup("E00"); + } else { + reply = strdup("OK"); + } break; + + case '2': // insert write watchpoint + case '3': // insert read watchpoint + case '4': { // insert access watchpoint + enum watchfun wf; + + if (packet[1] == '2') { + wf = WATCHWRITE; + } else if (packet[1] == '3') { + wf = WATCHREAD; + } else { + wf = WATCHACCESS; + } + + if (add_data_watchpoint(sl, wf, addr, len) < 0) { + reply = strdup("E00"); + } else { + reply = strdup("OK"); + break; + } } - case 'k': - // Kill request - reset the connection itself - ret = stlink_run(sl); - if (ret) DLOG("Kill: stlink_run failed\n"); - ret = stlink_exit_debug_mode(sl); - if (ret) DLOG("Kill: stlink_exit_debug_mode failed\n"); - stlink_close(sl); - - sl = do_connect(st); - if (sl == NULL || sl->chip_id == STLINK_CHIPID_UNKNOWN) cleanup(0); - connected_stlink = sl; - - if (st->reset) stlink_reset(sl); - ret = stlink_force_debug(sl); - if (ret) DLOG("Kill: stlink_force_debug failed\n"); - init_cache(sl); - init_code_breakpoints(sl); - init_data_watchpoints(sl); - - reply = NULL; // no response + break; + default: + reply = strdup(""); + } + break; + } + case 'z': { + char *endptr; + stm32_addr_t addr = (stm32_addr_t)strtoul(&packet[3], &endptr, 16); + // stm32_addr_t len = strtoul(&endptr[1], NULL, 16); + + switch (packet[1]) { + case '1': // remove breakpoint + update_code_breakpoint(sl, addr, 0); + reply = strdup("OK"); break; + case '2': // remove write watchpoint + case '3': // remove read watchpoint + case '4': // remove access watchpoint + + if (delete_data_watchpoint(sl, addr) < 0) { + reply = strdup("E00"); + break; + } else { + reply = strdup("OK"); + break; + } + default: reply = strdup(""); + } + break; + } + + case '!': { + // enter extended mode which allows restarting. We do support that always. + // also, set to persistent mode to allow GDB disconnect. + st->persistent = 1; + + reply = strdup("OK"); + break; + } + + case 'R': { + // reset the core. + ret = stlink_reset(sl); + + if (ret) { DLOG("R packet : stlink_reset failed\n"); } + + init_code_breakpoints(sl); + init_data_watchpoints(sl); + + attached = 1; + + reply = strdup("OK"); + break; + } + case 'k': + // kill request - reset the connection itself + ret = stlink_run(sl); + + if (ret) { DLOG("Kill: stlink_run failed\n"); } + + ret = stlink_exit_debug_mode(sl); + + if (ret) { DLOG("Kill: stlink_exit_debug_mode failed\n"); } + + stlink_close(sl); + + sl = do_connect(st); + + if (sl == NULL || sl->chip_id == STLINK_CHIPID_UNKNOWN) { cleanup(0); } + + connected_stlink = sl; + + if (st->reset) { stlink_reset(sl); } + + ret = stlink_force_debug(sl); + + if (ret) { DLOG("Kill: stlink_force_debug failed\n"); } + + init_cache(sl); + init_code_breakpoints(sl); + init_data_watchpoints(sl); + + reply = NULL; // no response + break; + + default: + reply = strdup(""); } if (reply) { DLOG("send: %s\n", reply); int result = gdb_send_packet(client, reply); + if (result != 0) { ELOG("cannot send: %d\n", result); free(reply); free(packet); close_socket(client); - return 1; + return(1); } free(reply); @@ -1750,13 +1859,12 @@ int serve(stlink_t *sl, st_state_t *st) { if (critical_error) { close_socket(client); - return 1; + return(1); } free(packet); } close_socket(client); - - return 0; + return(0); } diff --git a/src/st-util/gdb-server.h b/src/st-util/gdb-server.h index 8c8d47114..b50a7941d 100644 --- a/src/st-util/gdb-server.h +++ b/src/st-util/gdb-server.h @@ -8,4 +8,4 @@ #define DEBUG_LOGGING_LEVEL 100 #define DEFAULT_GDB_LISTEN_PORT 4242 -#endif +#endif // _GDB_SERVER_H diff --git a/src/st-util/semihosting.c b/src/st-util/semihosting.c index cb03868cd..821dcdbbb 100644 --- a/src/st-util/semihosting.c +++ b/src/st-util/semihosting.c @@ -13,13 +13,13 @@ static int mem_read_u8(stlink_t *sl, uint32_t addr, uint8_t *data) { int offset = addr % 4; int len = 4; - if (sl == NULL || data == NULL) return -1; + if (sl == NULL || data == NULL) { return(-1); } - /* Read address and length must be aligned */ - if (stlink_read_mem32(sl, addr - offset, len) != 0) return -1; + // read address and length must be aligned + if (stlink_read_mem32(sl, addr - offset, len) != 0) { return(-1); } *data = sl->q_buf[offset]; - return 0; + return(0); } #ifdef UNUSED @@ -27,26 +27,26 @@ static int mem_read_u16(stlink_t *sl, uint32_t addr, uint16_t *data) { int offset = addr % 4; int len = (offset > 2 ? 8 : 4); - if (sl == NULL || data == NULL) return -1; + if (sl == NULL || data == NULL) { return(-1); } - /* Read address and length must be aligned */ - if (stlink_read_mem32(sl, addr - offset, len) != 0) return -1; + // read address and length must be aligned + if (stlink_read_mem32(sl, addr - offset, len) != 0) { return(-1); } memcpy(data, &sl->q_buf[offset], sizeof(*data)); - return 0; + return(0); } static int mem_read_u32(stlink_t *sl, uint32_t addr, uint32_t *data) { int offset = addr % 4; int len = (offset > 0 ? 8 : 4); - if (sl == NULL || data == NULL) return -1; + if (sl == NULL || data == NULL) { return(-1); } - /* Read address and length must be aligned */ - if (stlink_read_mem32(sl, addr - offset, len) != 0) return -1; + // read address and length must be aligned + if (stlink_read_mem32(sl, addr - offset, len) != 0) { return(-1); } memcpy(data, &sl->q_buf[offset], sizeof(*data)); - return 0; + return(0); } #endif @@ -54,50 +54,42 @@ static int mem_read(stlink_t *sl, uint32_t addr, void *data, uint16_t len) { int offset = addr % 4; int read_len = len + offset; - if (sl == NULL || data == NULL) return -1; + if (sl == NULL || data == NULL) { return(-1); } - /* Align read size */ - if ((read_len % 4) != 0) { - read_len += 4 - (read_len % 4); - } + // align read size + if ((read_len % 4) != 0) { read_len += 4 - (read_len % 4); } - /* Address and length must be aligned */ - if (stlink_read_mem32(sl, addr - offset, read_len) != 0) return -1; + // address and length must be aligned + if (stlink_read_mem32(sl, addr - offset, read_len) != 0) { return(-1); } memcpy(data, &sl->q_buf[offset], len); - return 0; + return(0); } static int mem_write(stlink_t *sl, uint32_t addr, void *data, uint16_t len) { - // Note: this function can write more than it is asked to! - // If addr is not an even 32 bit boundary, or len is not a multiple of 4. - // - // If only 32 bit values can be written to the target, - // then this function should read the target memory at the - // start and end of the buffer where it will write more that - // the requested bytes. (perhaps reading the whole area is faster??). - // - // If 16 and 8 bit writes are available, then they could be used instead. - - // Just return when the length is zero avoiding unneeded work. - if (len == 0) return 0; + /* Note: this function can write more than it is asked to! + * If addr is not an even 32 bit boundary, or len is not a multiple of 4. + * If only 32 bit values can be written to the target, then this function should read + * the target memory at the start and end of the buffer where it will write more that + * the requested bytes. (perhaps reading the whole area is faster??). + * If 16 and 8 bit writes are available, then they could be used instead. + * Just return when the length is zero avoiding unneeded work. */ + if (len == 0) { return(0); } int offset = addr % 4; int write_len = len + offset; - if (sl == NULL || data == NULL) return -1; + if (sl == NULL || data == NULL) { return(-1); } - /* Align read size */ - if ((write_len % 4) != 0) { - write_len += 4 - (write_len % 4); - } + // align read size + if ((write_len % 4) != 0) { write_len += 4 - (write_len % 4); } memcpy(&sl->q_buf[offset], data, len); - /* Address and length must be aligned */ - if (stlink_write_mem32(sl, addr - offset, write_len) != 0) return -1; + // address and length must be aligned + if (stlink_write_mem32(sl, addr - offset, write_len) != 0) { return(-1); } - return 0; + return(0); } /* For the SYS_WRITE0 call, we don't know the size of the null-terminated buffer @@ -137,7 +129,7 @@ static int saved_errno = 0; int do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { - if (sl == NULL || ret == NULL) return -1; + if (sl == NULL || ret == NULL) { return(-1); } DLOG("Do semihosting R0=0x%08x R1=0x%08x\n", r0, r1); @@ -150,11 +142,10 @@ int do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { uint32_t name_len; char *name; - if (mem_read(sl, r1, args, sizeof (args)) != 0){ - DLOG("Semihosting SYS_OPEN error: " - "cannot read args from target memory\n"); + if (mem_read(sl, r1, args, sizeof(args)) != 0) { + DLOG("Semihosting SYS_OPEN error: cannot read args from target memory\n"); *ret = -1; - return -1; + return(-1); } name_address = args[0]; @@ -165,7 +156,7 @@ int do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { /* Invalid mode */ DLOG("Semihosting SYS_OPEN error: invalid mode %d\n", mode); *ret = -1; - return -1; + return(-1); } /* Add the trailing zero that is not counted in the length argument (see @@ -174,25 +165,24 @@ int do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { name_len += 1; if (name_len > MAX_BUFFER_SIZE) { - DLOG("Semihosting SYS_OPEN error: name buffer size is too big %d\n", - name_len); + DLOG("Semihosting SYS_OPEN error: name buffer size is too big %d\n", name_len); *ret = -1; - return -1; + return(-1); } + name = malloc(name_len); if (name == NULL) { DLOG("Semihosting SYS_OPEN error: cannot allocate name buffer\n"); *ret = -1; - return -1; + return(-1); } - if (mem_read(sl, name_address, name, name_len) != 0){ + if (mem_read(sl, name_address, name, name_len) != 0) { free(name); *ret = -1; - DLOG("Semihosting SYS_OPEN error: " - "cannot read name from target memory\n"); - return -1; + DLOG("Semihosting SYS_OPEN error: cannot read name from target memory\n"); + return(-1); } DLOG("Semihosting: open('%s', (SH open mode)%d, 0644)\n", name, mode); @@ -208,13 +198,12 @@ int do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { case SEMIHOST_SYS_CLOSE: { uint32_t args[1]; - int fd; + int fd; - if (mem_read(sl, r1, args, sizeof (args)) != 0){ - DLOG("Semihosting SYS_CLOSE error: " - "cannot read args from target memory\n"); + if (mem_read(sl, r1, args, sizeof(args)) != 0) { + DLOG("Semihosting SYS_CLOSE error: cannot read args from target memory\n"); *ret = -1; - return -1; + return(-1); } fd = (int)args[0]; @@ -231,15 +220,14 @@ int do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { { uint32_t args[3]; uint32_t buffer_address; - int fd; + int fd; uint32_t buffer_len; void *buffer; - if (mem_read(sl, r1, args, sizeof (args)) != 0){ - DLOG("Semihosting SYS_WRITE error: " - "cannot read args from target memory\n"); + if (mem_read(sl, r1, args, sizeof(args)) != 0) { + DLOG("Semihosting SYS_WRITE error: cannot read args from target memory\n"); *ret = -1; - return -1; + return(-1); } fd = (int)args[0]; @@ -248,9 +236,9 @@ int do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { if (buffer_len > MAX_BUFFER_SIZE) { DLOG("Semihosting SYS_WRITE error: buffer size is too big %d\n", - buffer_len); + buffer_len); *ret = buffer_len; - return -1; + return(-1); } buffer = malloc(buffer_len); @@ -258,19 +246,18 @@ int do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { if (buffer == NULL) { DLOG("Semihosting SYS_WRITE error: cannot allocate buffer\n"); *ret = buffer_len; - return -1; + return(-1); } - if (mem_read(sl, buffer_address, buffer, buffer_len) != 0){ - DLOG("Semihosting SYS_WRITE error: " - "cannot read buffer from target memory\n"); + if (mem_read(sl, buffer_address, buffer, buffer_len) != 0) { + DLOG("Semihosting SYS_WRITE error: cannot read buffer from target memory\n"); free(buffer); *ret = buffer_len; - return -1; + return(-1); } - DLOG("Semihosting: write(%d, target_addr:0x%08x, %zu)\n", fd, - buffer_address, buffer_len); + DLOG("Semihosting: write(%d, target_addr:0x%08x, %zu)\n", fd, buffer_address, + buffer_len); *ret = (uint32_t)write(fd, buffer, buffer_len); saved_errno = errno; @@ -289,16 +276,15 @@ int do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { { uint32_t args[3]; uint32_t buffer_address; - int fd; + int fd; uint32_t buffer_len; void *buffer; - ssize_t read_result; + ssize_t read_result; - if (mem_read(sl, r1, args, sizeof (args)) != 0){ - DLOG("Semihosting SYS_READ error: " - "cannot read args from target memory\n"); + if (mem_read(sl, r1, args, sizeof(args)) != 0) { + DLOG("Semihosting SYS_READ error: cannot read args from target memory\n"); *ret = -1; - return -1; + return(-1); } fd = (int)args[0]; @@ -306,10 +292,9 @@ int do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { buffer_len = args[2]; if (buffer_len > MAX_BUFFER_SIZE) { - DLOG("Semihosting SYS_READ error: buffer size is too big %d\n", - buffer_len); + DLOG("Semihosting SYS_READ error: buffer size is too big %d\n", buffer_len); *ret = buffer_len; - return -1; + return(-1); } buffer = malloc(buffer_len); @@ -317,11 +302,11 @@ int do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { if (buffer == NULL) { DLOG("Semihosting SYS_READ error: cannot allocatebuffer\n"); *ret = buffer_len; - return -1; + return(-1); } - DLOG("Semihosting: read(%d, target_addr:0x%08x, %zu)\n", fd, - buffer_address, buffer_len); + DLOG("Semihosting: read(%d, target_addr:0x%08x, %zu)\n", fd, buffer_address, + buffer_len); read_result = read(fd, buffer, buffer_len); saved_errno = errno; @@ -329,12 +314,11 @@ int do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { if (read_result == -1) { *ret = buffer_len; } else { - if (mem_write(sl, buffer_address, buffer, read_result) != 0){ - DLOG("Semihosting SYS_READ error: " - "cannot write buffer to target memory\n"); + if (mem_write(sl, buffer_address, buffer, read_result) != 0) { + DLOG("Semihosting SYS_READ error: cannot write buffer to target memory\n"); free(buffer); *ret = buffer_len; - return -1; + return(-1); } else { *ret = buffer_len - (uint32_t)read_result; } @@ -357,11 +341,10 @@ int do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { uint32_t name_len; char *name; - if (mem_read(sl, r1, args, sizeof (args)) != 0){ - DLOG("Semihosting SYS_REMOVE error: " - "cannot read args from target memory\n"); + if (mem_read(sl, r1, args, sizeof(args)) != 0) { + DLOG("Semihosting SYS_REMOVE error: cannot read args from target memory\n"); *ret = -1; - return -1; + return(-1); } name_address = args[0]; @@ -373,74 +356,68 @@ int do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { name_len += 1; if (name_len > MAX_BUFFER_SIZE) { - DLOG("Semihosting SYS_REMOVE error: " - "name buffer size is too big %d\n", name_len); + DLOG("Semihosting SYS_REMOVE error: name buffer size is too big %d\n", + name_len); *ret = -1; - return -1; + return(-1); } + name = malloc(name_len); if (name == NULL) { DLOG("Semihosting SYS_REMOVE error: cannot allocate name buffer\n"); *ret = -1; - return -1; + return(-1); } - if (mem_read(sl, name_address, name, name_len) != 0){ + if (mem_read(sl, name_address, name, name_len) != 0) { free(name); *ret = -1; - DLOG("Semihosting SYS_REMOVE error: " - "cannot read name from target memory\n"); - return -1; + DLOG("Semihosting SYS_REMOVE error: cannot read name from target memory\n"); + return(-1); } DLOG("Semihosting: unlink('%s')\n", name); - *ret = (uint32_t)unlink(name); saved_errno = errno; - DLOG("Semihosting: return %d\n", *ret); - free(name); break; } case SEMIHOST_SYS_SEEK: { uint32_t args[2]; - int fd; - off_t offset; + int fd; + off_t offset; - if (mem_read(sl, r1, args, sizeof (args)) != 0){ - DLOG("Semihosting SYS_SEEK error: " - "cannot read args from target memory\n"); + if (mem_read(sl, r1, args, sizeof(args)) != 0) { + DLOG("Semihosting SYS_SEEK error: cannot read args from target memory\n"); *ret = -1; - return -1; + return(-1); } fd = (int)args[0]; offset = (off_t)args[1]; DLOG("Semihosting: lseek(%d, %d, SEEK_SET)\n", fd, offset); - *ret = (uint32_t)lseek(fd, offset, SEEK_SET); saved_errno = errno; - if (*ret != (uint32_t)-1) { - /* Success */ - *ret = 0; - } + if (*ret != (uint32_t)-1) { *ret = 0; /* Success */ } + DLOG("Semihosting: return %d\n", *ret); break; } case SEMIHOST_SYS_WRITEC: { uint8_t c; + if (mem_read_u8(sl, r1, &c) == 0) { fprintf(stderr, "%c", c); } else { - DLOG("Semihosting WRITEC: " - "cannot read target memory at 0x%08x\n", r1); + DLOG("Semihosting WRITEC: cannot read target memory at 0x%08x\n", r1); } + break; } case SEMIHOST_SYS_READC: @@ -454,24 +431,25 @@ int do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { uint8_t buf[WRITE0_BUFFER_SIZE]; while (true) { - if (mem_read(sl, r1, buf, WRITE0_BUFFER_SIZE) != 0){ - DLOG("Semihosting WRITE0: " - "cannot read target memory at 0x%08x\n", r1); - return -1; + if (mem_read(sl, r1, buf, WRITE0_BUFFER_SIZE) != 0) { + DLOG("Semihosting WRITE0: cannot read target memory at 0x%08x\n", r1); + return(-1); } + for (int i = 0; i < WRITE0_BUFFER_SIZE; i++) { - if (buf[i] == 0) { - return 0; - } + if (buf[i] == 0) { return(0); } + fprintf(stderr, "%c", buf[i]); } + r1 += WRITE0_BUFFER_SIZE; } + break; } default: fprintf(stderr, "semihosting: unsupported call %#x\n", r0); - return -1; + return(-1); } - return 0; + return(0); } diff --git a/src/st-util/semihosting.h b/src/st-util/semihosting.h index 8157df9df..8c1ac15f0 100644 --- a/src/st-util/semihosting.h +++ b/src/st-util/semihosting.h @@ -29,6 +29,6 @@ #define SEMIHOST_SYS_ELAPSED 0x30 #define SEMIHOST_SYS_TICKFREQ 0x31 -int do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret); +int do_semihosting(stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret); -#endif /* ! _SEMIHOSTING_H_ */ +#endif // _SEMIHOSTING_H_ diff --git a/src/stlink-gui/gui.c b/src/stlink-gui/gui.c index 7ae591f2d..ed38fcc7c 100644 --- a/src/stlink-gui/gui.c +++ b/src/stlink-gui/gui.c @@ -13,23 +13,23 @@ #define G_VALUE_INIT {0, {{0}}} #endif -G_DEFINE_TYPE (STlinkGUI, stlink_gui, G_TYPE_OBJECT); +G_DEFINE_TYPE(STlinkGUI, stlink_gui, G_TYPE_OBJECT); -static void stlink_gui_dispose (GObject *gobject) { - G_OBJECT_CLASS (stlink_gui_parent_class)->dispose (gobject); +static void stlink_gui_dispose(GObject *gobject) { + G_OBJECT_CLASS(stlink_gui_parent_class)->dispose(gobject); } -static void stlink_gui_finalize (GObject *gobject) { - G_OBJECT_CLASS (stlink_gui_parent_class)->finalize (gobject); +static void stlink_gui_finalize(GObject *gobject) { + G_OBJECT_CLASS(stlink_gui_parent_class)->finalize(gobject); } -static void stlink_gui_class_init (STlinkGUIClass *klass) { - GObjectClass *gobject_class = G_OBJECT_CLASS (klass); +static void stlink_gui_class_init(STlinkGUIClass *klass) { + GObjectClass *gobject_class = G_OBJECT_CLASS(klass); gobject_class->dispose = stlink_gui_dispose; gobject_class->finalize = stlink_gui_finalize; } -static void stlink_gui_init (STlinkGUI *self) { +static void stlink_gui_init(STlinkGUI *self) { self->sl = NULL; self->filename = NULL; @@ -45,162 +45,159 @@ static void stlink_gui_init (STlinkGUI *self) { self->file_mem.base = 0; } -static gboolean set_info_error_message_idle (STlinkGUI *gui) { +static gboolean set_info_error_message_idle(STlinkGUI *gui) { if (gui->error_message != NULL) { gchar *markup; - markup = g_markup_printf_escaped ("%s", gui->error_message); - gtk_label_set_markup (gui->infolabel, markup); - gtk_info_bar_set_message_type (gui->infobar, GTK_MESSAGE_ERROR); - gtk_widget_show (GTK_WIDGET (gui->infobar)); + markup = g_markup_printf_escaped("%s", gui->error_message); + gtk_label_set_markup(gui->infolabel, markup); + gtk_info_bar_set_message_type(gui->infobar, GTK_MESSAGE_ERROR); + gtk_widget_show(GTK_WIDGET(gui->infobar)); - g_free (markup); - g_free (gui->error_message); + g_free(markup); + g_free(gui->error_message); gui->error_message = NULL; } - return FALSE; + + return(FALSE); } -static void stlink_gui_set_info_error_message (STlinkGUI *gui, const gchar *message) { - gui->error_message = g_strdup (message); - g_idle_add ((GSourceFunc) set_info_error_message_idle, gui); +static void stlink_gui_set_info_error_message(STlinkGUI *gui, const gchar *message) { + gui->error_message = g_strdup(message); + g_idle_add((GSourceFunc)set_info_error_message_idle, gui); } -static void stlink_gui_set_sensitivity (STlinkGUI *gui, gboolean sensitivity) { - gtk_widget_set_sensitive (GTK_WIDGET (gui->open_button), sensitivity); - if (sensitivity && gui->sl) - gtk_widget_set_sensitive (GTK_WIDGET (gui->disconnect_button), sensitivity); - if (sensitivity && !gui->sl) - gtk_widget_set_sensitive (GTK_WIDGET (gui->connect_button), sensitivity); - if (sensitivity && gui->sl && gui->filename) - gtk_widget_set_sensitive (GTK_WIDGET (gui->flash_button), sensitivity); - gtk_widget_set_sensitive (GTK_WIDGET (gui->export_button), sensitivity && (gui->sl != NULL)); +static void stlink_gui_set_sensitivity(STlinkGUI *gui, gboolean sensitivity) { + gtk_widget_set_sensitive(GTK_WIDGET(gui->open_button), sensitivity); + + if (sensitivity && gui->sl) { + gtk_widget_set_sensitive(GTK_WIDGET(gui->disconnect_button), sensitivity); + } + + if (sensitivity && !gui->sl) { + gtk_widget_set_sensitive(GTK_WIDGET(gui->connect_button), sensitivity); + } + + if (sensitivity && gui->sl && gui->filename) { + gtk_widget_set_sensitive(GTK_WIDGET(gui->flash_button), sensitivity); + } + + gtk_widget_set_sensitive(GTK_WIDGET(gui->export_button), sensitivity && (gui->sl != NULL)); } -static void mem_view_init_headers (GtkTreeView *view) { +static void mem_view_init_headers(GtkTreeView *view) { GtkCellRenderer *renderer; - gint i; - - g_return_if_fail (view != NULL); - - renderer = gtk_cell_renderer_text_new (); - gtk_tree_view_insert_column_with_attributes ( - view, - -1, - "Address", - renderer, - "text", - 0, /* column */ - NULL); + gint i; + + g_return_if_fail(view != NULL); + + renderer = gtk_cell_renderer_text_new(); + gtk_tree_view_insert_column_with_attributes(view, -1, "Address", renderer, "text", 0, /* column */ NULL); + for (i = 0; i < 4; i++) { gchar *label; - label = g_strdup_printf ("%X", i * 4); - renderer = gtk_cell_renderer_text_new (); - gtk_tree_view_insert_column_with_attributes (view, - -1, - label, - renderer, - "text", - (i + 1), /* column */ - NULL); - g_free (label); + label = g_strdup_printf("%X", i * 4); + renderer = gtk_cell_renderer_text_new(); + gtk_tree_view_insert_column_with_attributes(view, -1, label, renderer, "text", (i + 1), /* column */ NULL); + g_free(label); } for (i = 0; i < 5; i++) { - GtkTreeViewColumn *column = gtk_tree_view_get_column (view, i); - gtk_tree_view_column_set_expand (column, TRUE); + GtkTreeViewColumn *column = gtk_tree_view_get_column(view, i); + gtk_tree_view_column_set_expand(column, TRUE); } } -static void mem_view_add_as_hex ( - GtkListStore *store, - GtkTreeIter *iter, - gint column, - guint32 value) { +static void mem_view_add_as_hex(GtkListStore *store, + GtkTreeIter *iter, + gint column, + guint32 value) { gchar *hex_str; - hex_str = g_strdup_printf ("0x%08X", value); + hex_str = g_strdup_printf("0x%08X", value); gtk_list_store_set(store, iter, column, hex_str, -1); - g_free (hex_str); + g_free(hex_str); } -static void mem_view_add_buffer ( - GtkListStore *store, - GtkTreeIter *iter, - guint32 address, - guchar *buffer, - gint len) { +static void mem_view_add_buffer(GtkListStore *store, + GtkTreeIter *iter, + guint32 address, + guchar *buffer, + gint len) { guint32 *word; - gint i, step; - gint column = 0; + gint i, step; + gint column = 0; - step = sizeof (*word); + step = sizeof(*word); for (i = 0; i < len; i += step) { - word = (guint *) &buffer[i]; + word = (guint *)&buffer[i]; if (column == 0) { - /* new row */ - gtk_list_store_append (store, iter); - - /* add address */ - mem_view_add_as_hex (store, iter, column, (address + i)); + gtk_list_store_append(store, iter); // new row + mem_view_add_as_hex(store, iter, column, (address + i)); // add address } - mem_view_add_as_hex (store, iter, (column + 1), *word); + + mem_view_add_as_hex(store, iter, (column + 1), *word); column = (column + 1) % step; } } -static guint32 hexstr_to_guint32 (const gchar *str, GError **err) { - guint32 val; - gchar *end_ptr; +static guint32 hexstr_to_guint32(const gchar *str, GError **err) { + guint32 val; + gchar *end_ptr; + + val = (guint32)strtoul(str, &end_ptr, 16); - val = (guint32) strtoul (str, &end_ptr, 16); if ((errno == ERANGE && val == UINT_MAX) || (errno != 0 && val == 0)) { - g_set_error (err, g_quark_from_string ("hextou32"), 1, "Invalid hexstring"); - return UINT32_MAX; + g_set_error(err, g_quark_from_string("hextou32"), 1, "Invalid hexstring"); + return(UINT32_MAX); } + if (end_ptr == str) { - g_set_error (err, g_quark_from_string ("hextou32"), 2, "Invalid hexstring"); - return UINT32_MAX; + g_set_error(err, g_quark_from_string("hextou32"), 2, "Invalid hexstring"); + return(UINT32_MAX); } - return val; + + return(val); } -static void stlink_gui_update_mem_view (STlinkGUI *gui, struct mem_t *mem, GtkTreeView *view) { +static void stlink_gui_update_mem_view(STlinkGUI *gui, struct mem_t *mem, GtkTreeView *view) { GtkListStore *store; - GtkTreeIter iter; + GtkTreeIter iter; - store = GTK_LIST_STORE (gtk_tree_view_get_model (view)); + store = GTK_LIST_STORE(gtk_tree_view_get_model(view)); - mem_view_add_buffer (store, &iter, mem->base, mem->memory, (gint) mem->size); + mem_view_add_buffer(store, &iter, mem->base, mem->memory, (gint)mem->size); - gtk_widget_hide (GTK_WIDGET (gui->progress.bar)); - gtk_progress_bar_set_fraction (gui->progress.bar, 0); - stlink_gui_set_sensitivity (gui, TRUE); + gtk_widget_hide(GTK_WIDGET(gui->progress.bar)); + gtk_progress_bar_set_fraction(gui->progress.bar, 0); + stlink_gui_set_sensitivity(gui, TRUE); } -static gboolean stlink_gui_update_devmem_view (STlinkGUI *gui) { - stlink_gui_update_mem_view (gui, &gui->flash_mem, gui->devmem_treeview); - return FALSE; +static gboolean stlink_gui_update_devmem_view(STlinkGUI *gui) { + stlink_gui_update_mem_view(gui, &gui->flash_mem, gui->devmem_treeview); + return(FALSE); } -static gpointer stlink_gui_populate_devmem_view (gpointer data) { - guint off; - stm32_addr_t addr; +static gpointer stlink_gui_populate_devmem_view(gpointer data) { + guint off; + stm32_addr_t addr; - g_return_val_if_fail (STLINK_IS_GUI (data), NULL); + g_return_val_if_fail(STLINK_IS_GUI(data), NULL); STlinkGUI *gui = (STlinkGUI *)data; - g_return_val_if_fail ((gui != NULL), NULL); - g_return_val_if_fail ((gui->sl != NULL), NULL); + g_return_val_if_fail((gui != NULL), NULL); + g_return_val_if_fail((gui->sl != NULL), NULL); addr = gui->sl->flash_base; - if (gui->flash_mem.memory) - g_free (gui->flash_mem.memory); - gui->flash_mem.memory = g_malloc (gui->sl->flash_size); + if (gui->flash_mem.memory) { + g_free(gui->flash_mem.memory); + } + + gui->flash_mem.memory = g_malloc(gui->sl->flash_size); gui->flash_mem.size = gui->sl->flash_size; gui->flash_mem.base = gui->sl->flash_base; @@ -208,304 +205,319 @@ static gpointer stlink_gui_populate_devmem_view (gpointer data) { guint n_read = MEM_READ_SIZE; if (off + MEM_READ_SIZE > gui->sl->flash_size) { - n_read = (guint) gui->sl->flash_size - off; + n_read = (guint)gui->sl->flash_size - off; - /* align if needed */ - if (n_read & 3) - n_read = (n_read + 4) & ~(3); + if (n_read & 3) { n_read = (n_read + 4) & ~(3); } // align if needed } - /* reads to sl->q_buf */ - stlink_read_mem32(gui->sl, addr + off, n_read); + + stlink_read_mem32(gui->sl, addr + off, n_read); // reads to sl->q_buf + if (gui->sl->q_len < 0) { - stlink_gui_set_info_error_message (gui, "Failed to read memory"); - g_free (gui->flash_mem.memory); + stlink_gui_set_info_error_message(gui, "Failed to read memory"); + g_free(gui->flash_mem.memory); gui->flash_mem.memory = NULL; - return NULL; + return(NULL); } - memcpy (gui->flash_mem.memory + off, gui->sl->q_buf, n_read); - gui->progress.fraction = (gdouble) (off + n_read) / gui->sl->flash_size; + + memcpy(gui->flash_mem.memory + off, gui->sl->q_buf, n_read); + gui->progress.fraction = (gdouble)(off + n_read) / gui->sl->flash_size; } - g_idle_add ((GSourceFunc) stlink_gui_update_devmem_view, gui); - return NULL; + + g_idle_add((GSourceFunc)stlink_gui_update_devmem_view, gui); + return(NULL); } -static gboolean stlink_gui_update_filemem_view (STlinkGUI *gui) { +static gboolean stlink_gui_update_filemem_view(STlinkGUI *gui) { gchar *basename; - basename = g_path_get_basename (gui->filename); - gtk_notebook_set_tab_label_text (gui->notebook, - GTK_WIDGET (gtk_notebook_get_nth_page (gui->notebook, 1)), basename); - g_free (basename); + basename = g_path_get_basename(gui->filename); + gtk_notebook_set_tab_label_text( + gui->notebook, GTK_WIDGET(gtk_notebook_get_nth_page(gui->notebook, 1)), basename); + g_free(basename); - stlink_gui_update_mem_view (gui, &gui->file_mem, gui->filemem_treeview); - return FALSE; + stlink_gui_update_mem_view(gui, &gui->file_mem, gui->filemem_treeview); + return(FALSE); } -static gpointer stlink_gui_populate_filemem_view (gpointer data) { - guchar buffer[MEM_READ_SIZE]; - GFile *file; - GFileInfo *file_info; +static gpointer stlink_gui_populate_filemem_view(gpointer data) { + guchar buffer[MEM_READ_SIZE]; + GFile *file; + GFileInfo *file_info; GInputStream *input_stream; - gint off; - GError *err = NULL; + gint off; + GError *err = NULL; - g_return_val_if_fail (STLINK_IS_GUI (data), NULL); + g_return_val_if_fail(STLINK_IS_GUI(data), NULL); STlinkGUI *gui = (STlinkGUI *)data; - g_return_val_if_fail (gui != NULL, NULL); - g_return_val_if_fail (gui->filename != NULL, NULL); + g_return_val_if_fail(gui != NULL, NULL); + g_return_val_if_fail(gui->filename != NULL, NULL); - if (g_str_has_suffix (gui->filename, ".hex")) { - // If the file has prefix .hex - try to interpret it as Intel-HEX. - // It's difficult to merge the world of standard functions and GLib, - // so do it simple - load whole file into buffer and copy the data to the - // destination afterwards. - // We loose meanwhile the displaying of the progress and need double memory. + if (g_str_has_suffix(gui->filename, ".hex")) { + /* If the file has prefix .hex - try to interpret it as Intel-HEX. + * It's difficult to merge the world of standard functions and GLib, so do it simple: + * Load whole file into buffer and copy the data to the destination afterwards. + * In the meanwhile we loose the displaying of the progress and need double memory. + */ uint8_t* mem = NULL; - size_t size = 0; + size_t size = 0; uint32_t begin = 0; - int res = stlink_parse_ihex (gui->filename, 0, &mem, &size, &begin); + int res = stlink_parse_ihex(gui->filename, 0, &mem, &size, &begin); if (res == 0) { - if (gui->file_mem.memory) - g_free (gui->file_mem.memory); + if (gui->file_mem.memory) { + g_free(gui->file_mem.memory); + } + gui->file_mem.size = size; - gui->file_mem.memory = g_malloc (size); + gui->file_mem.memory = g_malloc(size); gui->file_mem.base = begin; - memcpy (gui->file_mem.memory, mem, size); + memcpy(gui->file_mem.memory, mem, size); } else { - stlink_gui_set_info_error_message (gui, "Cannot interpret the file as Intel-HEX"); + stlink_gui_set_info_error_message(gui, "Cannot interpret the file as Intel-HEX"); } free(mem); } else { - file = g_file_new_for_path (gui->filename); - input_stream = G_INPUT_STREAM (g_file_read (file, NULL, &err)); + file = g_file_new_for_path(gui->filename); + input_stream = G_INPUT_STREAM(g_file_read(file, NULL, &err)); + if (err) { - stlink_gui_set_info_error_message (gui, err->message); - g_error_free (err); + stlink_gui_set_info_error_message(gui, err->message); + g_error_free(err); goto out; } - file_info = g_file_input_stream_query_info (G_FILE_INPUT_STREAM (input_stream), - G_FILE_ATTRIBUTE_STANDARD_SIZE, NULL, &err); + file_info = g_file_input_stream_query_info( + G_FILE_INPUT_STREAM(input_stream), G_FILE_ATTRIBUTE_STANDARD_SIZE, NULL, &err); + if (err) { - stlink_gui_set_info_error_message (gui, err->message); - g_error_free (err); + stlink_gui_set_info_error_message(gui, err->message); + g_error_free(err); goto out_input; } - if (gui->file_mem.memory) - g_free (gui->file_mem.memory); - gui->file_mem.size = g_file_info_get_size (file_info); - gui->file_mem.memory = g_malloc (gui->file_mem.size); - for (off = 0; off < (gint) gui->file_mem.size; off += MEM_READ_SIZE) { + if (gui->file_mem.memory) { g_free(gui->file_mem.memory); } + + gui->file_mem.size = g_file_info_get_size(file_info); + gui->file_mem.memory = g_malloc(gui->file_mem.size); + + for (off = 0; off < (gint)gui->file_mem.size; off += MEM_READ_SIZE) { guint n_read = MEM_READ_SIZE; - if (off + MEM_READ_SIZE > (gint) gui->file_mem.size) - n_read = (guint) gui->file_mem.size - off; + if (off + MEM_READ_SIZE > (gint)gui->file_mem.size) { + n_read = (guint)gui->file_mem.size - off; + } - if (g_input_stream_read (G_INPUT_STREAM (input_stream), - &buffer, n_read, NULL, &err) == -1) { - stlink_gui_set_info_error_message (gui, err->message); - g_error_free (err); + if (g_input_stream_read( + G_INPUT_STREAM(input_stream), &buffer, n_read, NULL, &err) == -1) { + stlink_gui_set_info_error_message(gui, err->message); + g_error_free(err); goto out_input; } - memcpy (gui->file_mem.memory + off, buffer, n_read); - gui->progress.fraction = (gdouble) (off + n_read) / gui->file_mem.size; + + memcpy(gui->file_mem.memory + off, buffer, n_read); + gui->progress.fraction = (gdouble)(off + n_read) / gui->file_mem.size; } - out_input: g_object_unref (input_stream); - out: g_object_unref (file); +out_input: g_object_unref(input_stream); +out: g_object_unref(file); } - g_idle_add ((GSourceFunc) stlink_gui_update_filemem_view, gui); - return NULL; + g_idle_add((GSourceFunc)stlink_gui_update_filemem_view, gui); + return(NULL); } -static void mem_jmp (GtkTreeView *view, - GtkEntry *entry, - guint32 base_addr, - gsize size, - GError **err) { +static void mem_jmp(GtkTreeView *view, + GtkEntry *entry, + guint32 base_addr, + gsize size, + GError **err) { GtkTreeModel *model; - guint32 jmp_addr; - GtkTreeIter iter; + guint32 jmp_addr; + GtkTreeIter iter; - jmp_addr = hexstr_to_guint32 (gtk_entry_get_text (entry), err); - if (err && *err) - return; + jmp_addr = hexstr_to_guint32(gtk_entry_get_text(entry), err); + + if (err && *err) { return; } if (jmp_addr < base_addr || jmp_addr > base_addr + size) { - g_set_error (err, g_quark_from_string ("mem_jmp"), 1, "Invalid address"); + g_set_error(err, g_quark_from_string("mem_jmp"), 1, "Invalid address"); return; } - model = gtk_tree_view_get_model (view); - if (!model) - return; + model = gtk_tree_view_get_model(view); + + if (!model) { return; } - if (gtk_tree_model_get_iter_first (model, &iter)) { + if (gtk_tree_model_get_iter_first(model, &iter)) { do { guint32 addr; - GValue value = G_VALUE_INIT; + GValue value = G_VALUE_INIT; + + gtk_tree_model_get_value(model, &iter, 0, &value); + + if (G_VALUE_HOLDS_STRING(&value)) { + addr = hexstr_to_guint32(g_value_get_string(&value), err); - gtk_tree_model_get_value (model, &iter, 0, &value); - if (G_VALUE_HOLDS_STRING (&value)) { - addr = hexstr_to_guint32 (g_value_get_string (&value), err); if (!*err) { if (addr == (jmp_addr & 0xFFFFFFF0)) { GtkTreeSelection *selection; - GtkTreePath *path; + GtkTreePath *path; - selection = gtk_tree_view_get_selection (view); - path = gtk_tree_model_get_path (model, &iter); + selection = gtk_tree_view_get_selection(view); + path = gtk_tree_model_get_path(model, &iter); - gtk_tree_selection_select_iter (selection, &iter); - gtk_tree_view_scroll_to_cell (view, path, NULL, TRUE, 0.0, 0.0); - gtk_tree_path_free (path); + gtk_tree_selection_select_iter(selection, &iter); + gtk_tree_view_scroll_to_cell(view, path, NULL, TRUE, 0.0, 0.0); + gtk_tree_path_free(path); } } } + g_value_unset(&value); - } while (gtk_tree_model_iter_next (model, &iter)); + } while (gtk_tree_model_iter_next(model, &iter)); } } -static void devmem_jmp_cb (GtkWidget *widget, gpointer data) { +static void devmem_jmp_cb(GtkWidget *widget, gpointer data) { STlinkGUI *gui; - GError *err = NULL; - (void) widget; + GError *err = NULL; + (void)widget; - gui = STLINK_GUI (data); + gui = STLINK_GUI(data); - mem_jmp (gui->devmem_treeview, + mem_jmp(gui->devmem_treeview, gui->devmem_jmp_entry, gui->sl->flash_base, gui->sl->flash_size, &err); if (err) { - stlink_gui_set_info_error_message (gui, err->message); - g_error_free (err); + stlink_gui_set_info_error_message(gui, err->message); + g_error_free(err); } } -static void filemem_jmp_cb (GtkWidget *widget, gpointer data) { +static void filemem_jmp_cb(GtkWidget *widget, gpointer data) { STlinkGUI *gui; - GError *err = NULL; - (void) widget; + GError *err = NULL; + (void)widget; - gui = STLINK_GUI (data); + gui = STLINK_GUI(data); - g_return_if_fail (gui->filename != NULL); + g_return_if_fail(gui->filename != NULL); - mem_jmp (gui->filemem_treeview, + mem_jmp(gui->filemem_treeview, gui->filemem_jmp_entry, 0, gui->file_mem.size, &err); if (err) { - stlink_gui_set_info_error_message (gui, err->message); - g_error_free (err); + stlink_gui_set_info_error_message(gui, err->message); + g_error_free(err); } } -static gchar *dev_format_chip_id (guint32 chip_id) { +static gchar *dev_format_chip_id(guint32 chip_id) { const struct stlink_chipid_params *params; params = stlink_chipid_get_params(chip_id); - if (!params) - return g_strdup_printf ("0x%x", chip_id); - return g_strdup (params->description); + if (!params) { return(g_strdup_printf("0x%x", chip_id)); } + + return(g_strdup(params->description)); } -static gchar *dev_format_mem_size (gsize flash_size) { - return g_strdup_printf ("%u kB", (unsigned int)(flash_size / 1024)); +static gchar *dev_format_mem_size(gsize flash_size) { + return(g_strdup_printf("%u kB", (unsigned int)(flash_size / 1024))); } -static void stlink_gui_set_connected (STlinkGUI *gui) { - gchar *tmp_str; +static void stlink_gui_set_connected(STlinkGUI *gui) { + gchar *tmp_str; GtkListStore *store; - GtkTreeIter iter; + GtkTreeIter iter; + + gtk_statusbar_push(gui->statusbar, gtk_statusbar_get_context_id(gui->statusbar, "conn"), "Connected"); - gtk_statusbar_push (gui->statusbar, - gtk_statusbar_get_context_id (gui->statusbar, "conn"), "Connected"); + gtk_widget_set_sensitive(GTK_WIDGET(gui->device_frame), TRUE); + gtk_widget_set_sensitive(GTK_WIDGET(gui->devmem_box), TRUE); + gtk_widget_set_sensitive(GTK_WIDGET(gui->connect_button), FALSE); - gtk_widget_set_sensitive (GTK_WIDGET (gui->device_frame), TRUE); - gtk_widget_set_sensitive (GTK_WIDGET (gui->devmem_box), TRUE); - gtk_widget_set_sensitive (GTK_WIDGET (gui->connect_button), FALSE); + if (gui->filename) { + gtk_widget_set_sensitive(GTK_WIDGET(gui->flash_button), TRUE); + } - if (gui->filename) - gtk_widget_set_sensitive (GTK_WIDGET (gui->flash_button), TRUE); + tmp_str = dev_format_chip_id(gui->sl->chip_id); + gtk_label_set_text(gui->chip_id_label, tmp_str); + g_free(tmp_str); - tmp_str = dev_format_chip_id (gui->sl->chip_id); - gtk_label_set_text (gui->chip_id_label, tmp_str); - g_free (tmp_str); + tmp_str = g_strdup_printf("0x%x", gui->sl->core_id); + gtk_label_set_text(gui->core_id_label, tmp_str); + g_free(tmp_str); - tmp_str = g_strdup_printf ("0x%x", gui->sl->core_id); - gtk_label_set_text (gui->core_id_label, tmp_str); - g_free (tmp_str); + tmp_str = dev_format_mem_size(gui->sl->flash_size); + gtk_label_set_text(gui->flash_size_label, tmp_str); + g_free(tmp_str); - tmp_str = dev_format_mem_size (gui->sl->flash_size); - gtk_label_set_text (gui->flash_size_label, tmp_str); - g_free (tmp_str); + tmp_str = dev_format_mem_size(gui->sl->sram_size); + gtk_label_set_text(gui->ram_size_label, tmp_str); + g_free(tmp_str); - tmp_str = dev_format_mem_size (gui->sl->sram_size); - gtk_label_set_text (gui->ram_size_label, tmp_str); - g_free (tmp_str); + tmp_str = g_strdup_printf("0x%08X", gui->sl->flash_base); + gtk_entry_set_text(gui->devmem_jmp_entry, tmp_str); + gtk_editable_set_editable(GTK_EDITABLE(gui->devmem_jmp_entry), TRUE); + g_free(tmp_str); - tmp_str = g_strdup_printf ("0x%08X", gui->sl->flash_base); - gtk_entry_set_text (gui->devmem_jmp_entry, tmp_str); - gtk_editable_set_editable (GTK_EDITABLE (gui->devmem_jmp_entry), TRUE); - g_free (tmp_str); + store = GTK_LIST_STORE(gtk_tree_view_get_model(gui->devmem_treeview)); - store = GTK_LIST_STORE (gtk_tree_view_get_model (gui->devmem_treeview)); - if (gtk_tree_model_get_iter_first (GTK_TREE_MODEL (store), &iter)) - gtk_list_store_clear (store); + if (gtk_tree_model_get_iter_first(GTK_TREE_MODEL(store), &iter)) { + gtk_list_store_clear(store); + } - stlink_gui_set_sensitivity (gui, FALSE); - gtk_notebook_set_current_page (gui->notebook, PAGE_DEVMEM); - gtk_widget_show (GTK_WIDGET (gui->progress.bar)); - gtk_progress_bar_set_text (gui->progress.bar, "Reading memory"); + stlink_gui_set_sensitivity(gui, FALSE); + gtk_notebook_set_current_page(gui->notebook, PAGE_DEVMEM); + gtk_widget_show(GTK_WIDGET(gui->progress.bar)); + gtk_progress_bar_set_text(gui->progress.bar, "Reading memory"); - g_thread_new ("devmem", (GThreadFunc) stlink_gui_populate_devmem_view, gui); + g_thread_new("devmem", (GThreadFunc)stlink_gui_populate_devmem_view, gui); } -static void connect_button_cb (GtkWidget *widget, gpointer data) { +static void connect_button_cb(GtkWidget *widget, gpointer data) { STlinkGUI *gui; - gint i; - (void) widget; + gint i; + (void)widget; - gui = STLINK_GUI (data); + gui = STLINK_GUI(data); - if (gui->sl != NULL) - return; + if (gui->sl != NULL) { return; } + + gui->sl = stlink_v1_open(0, 1); // try version 1 then version 2 + + if (gui->sl == NULL) { gui->sl = stlink_open_usb(0, 1, NULL, 0); } - /* try version 1 then version 2 */ - gui->sl = stlink_v1_open(0, 1); - if (gui->sl == NULL) - gui->sl = stlink_open_usb(0, 1, NULL, 0); if (gui->sl == NULL) { - stlink_gui_set_info_error_message (gui, "Failed to connect to STLink."); + stlink_gui_set_info_error_message(gui, "Failed to connect to STLink."); return; } - /* code below taken from flash/main.c, refactoring might be in order */ - if (stlink_current_mode(gui->sl) == STLINK_DEV_DFU_MODE) + // code below taken from flash/main.c, refactoring might be in order + if (stlink_current_mode(gui->sl) == STLINK_DEV_DFU_MODE) { stlink_exit_dfu_mode(gui->sl); + } - if (stlink_current_mode(gui->sl) != STLINK_DEV_DEBUG_MODE) + if (stlink_current_mode(gui->sl) != STLINK_DEV_DEBUG_MODE) { stlink_enter_swd_mode(gui->sl); + } - /* Disable DMA - Set All DMA CCR Registers to zero. - AKS 1/7/2013 */ + // disable DMA - Set All DMA CCR Registers to zero. - AKS 1/7/2013 if (gui->sl->chip_id == STLINK_CHIPID_STM32_F4) { memset(gui->sl->q_buf, 0, 4); + for (i = 0; i < 8; i++) { stlink_write_mem32(gui->sl, 0x40026000 + 0x10 + 0x18 * i, 4); stlink_write_mem32(gui->sl, 0x40026400 + 0x10 + 0x18 * i, 4); @@ -513,128 +525,133 @@ static void connect_button_cb (GtkWidget *widget, gpointer data) { stlink_write_mem32(gui->sl, 0x40026400 + 0x24 + 0x18 * i, 4); } } - stlink_gui_set_connected (gui); + + stlink_gui_set_connected(gui); } -static void stlink_gui_set_disconnected (STlinkGUI *gui) { - gtk_statusbar_push (gui->statusbar, - gtk_statusbar_get_context_id (gui->statusbar, "conn"), - "Disconnected"); +static void stlink_gui_set_disconnected(STlinkGUI *gui) { + gtk_statusbar_push(gui->statusbar, gtk_statusbar_get_context_id(gui->statusbar, "conn"), "Disconnected"); - gtk_widget_set_sensitive (GTK_WIDGET (gui->device_frame), FALSE); - gtk_widget_set_sensitive (GTK_WIDGET (gui->flash_button), FALSE); - gtk_widget_set_sensitive (GTK_WIDGET (gui->export_button), FALSE); - gtk_widget_set_sensitive (GTK_WIDGET (gui->disconnect_button), FALSE); - gtk_widget_set_sensitive (GTK_WIDGET (gui->connect_button), TRUE); + gtk_widget_set_sensitive(GTK_WIDGET(gui->device_frame), FALSE); + gtk_widget_set_sensitive(GTK_WIDGET(gui->flash_button), FALSE); + gtk_widget_set_sensitive(GTK_WIDGET(gui->export_button), FALSE); + gtk_widget_set_sensitive(GTK_WIDGET(gui->disconnect_button), FALSE); + gtk_widget_set_sensitive(GTK_WIDGET(gui->connect_button), TRUE); } -static void disconnect_button_cb (GtkWidget *widget, gpointer data) { +static void disconnect_button_cb(GtkWidget *widget, gpointer data) { STlinkGUI *gui; - (void) widget; + (void)widget; - gui = STLINK_GUI (data); + gui = STLINK_GUI(data); if (gui->sl != NULL) { stlink_exit_debug_mode(gui->sl); stlink_close(gui->sl); gui->sl = NULL; } - stlink_gui_set_disconnected (gui); + + stlink_gui_set_disconnected(gui); } -static void stlink_gui_open_file (STlinkGUI *gui) { - GtkWidget *dialog; +static void stlink_gui_open_file(STlinkGUI *gui) { + GtkWidget *dialog; GtkListStore *store; - GtkTreeIter iter; + GtkTreeIter iter; - dialog = gtk_file_chooser_dialog_new ("Open file", - gui->window, - GTK_FILE_CHOOSER_ACTION_OPEN, - "_Cancel", GTK_RESPONSE_CANCEL, - "_Open", GTK_RESPONSE_ACCEPT, - NULL); + dialog = gtk_file_chooser_dialog_new("Open file", + gui->window, + GTK_FILE_CHOOSER_ACTION_OPEN, + "_Cancel", GTK_RESPONSE_CANCEL, + "_Open", GTK_RESPONSE_ACCEPT, + NULL); - if (gtk_dialog_run (GTK_DIALOG (dialog)) == GTK_RESPONSE_ACCEPT) { - gui->filename = gtk_file_chooser_get_filename (GTK_FILE_CHOOSER (dialog)); + if (gtk_dialog_run(GTK_DIALOG(dialog)) == GTK_RESPONSE_ACCEPT) { + gui->filename = gtk_file_chooser_get_filename(GTK_FILE_CHOOSER(dialog)); - store = GTK_LIST_STORE (gtk_tree_view_get_model (gui->filemem_treeview)); - if (gtk_tree_model_get_iter_first (GTK_TREE_MODEL (store), &iter)) - gtk_list_store_clear (store); + store = GTK_LIST_STORE(gtk_tree_view_get_model(gui->filemem_treeview)); - stlink_gui_set_sensitivity (gui, FALSE); - gtk_notebook_set_current_page (gui->notebook, PAGE_FILEMEM); - gtk_widget_show (GTK_WIDGET (gui->progress.bar)); - gtk_progress_bar_set_text (gui->progress.bar, "Reading file"); - g_thread_new ("file", (GThreadFunc) stlink_gui_populate_filemem_view, gui); + if (gtk_tree_model_get_iter_first(GTK_TREE_MODEL(store), &iter)) { + gtk_list_store_clear(store); + } + + stlink_gui_set_sensitivity(gui, FALSE); + gtk_notebook_set_current_page(gui->notebook, PAGE_FILEMEM); + gtk_widget_show(GTK_WIDGET(gui->progress.bar)); + gtk_progress_bar_set_text(gui->progress.bar, "Reading file"); + g_thread_new("file", (GThreadFunc)stlink_gui_populate_filemem_view, gui); } - gtk_widget_destroy (dialog); + + gtk_widget_destroy(dialog); } -static void open_button_cb (GtkWidget *widget, gpointer data) { - STlinkGUI *gui; - (void) widget; +static void open_button_cb(GtkWidget *widget, gpointer data) { + STlinkGUI *gui; + (void)widget; - gui = STLINK_GUI (data); - stlink_gui_open_file (gui); + gui = STLINK_GUI(data); + stlink_gui_open_file(gui); } -static gboolean stlink_gui_write_flash_update (STlinkGUI *gui) { - stlink_gui_set_sensitivity (gui, TRUE); +static gboolean stlink_gui_write_flash_update(STlinkGUI *gui) { + stlink_gui_set_sensitivity(gui, TRUE); gui->progress.activity_mode = FALSE; - gtk_widget_hide (GTK_WIDGET (gui->progress.bar)); - return FALSE; + gtk_widget_hide(GTK_WIDGET(gui->progress.bar)); + return(FALSE); } -static gpointer stlink_gui_write_flash (gpointer data) { - g_return_val_if_fail (STLINK_IS_GUI (data), NULL); +static gpointer stlink_gui_write_flash(gpointer data) { + g_return_val_if_fail(STLINK_IS_GUI(data), NULL); STlinkGUI *gui = (STlinkGUI *)data; - g_return_val_if_fail ((gui->sl != NULL), NULL); - g_return_val_if_fail ((gui->filename != NULL), NULL); + g_return_val_if_fail((gui->sl != NULL), NULL); + g_return_val_if_fail((gui->filename != NULL), NULL); - if (stlink_mwrite_flash(gui->sl, gui->file_mem.memory, - (uint32_t)gui->file_mem.size, gui->sl->flash_base) < 0) { - stlink_gui_set_info_error_message (gui, "Failed to write to flash"); + if (stlink_mwrite_flash( + gui->sl, gui->file_mem.memory, (uint32_t)gui->file_mem.size, gui->sl->flash_base) < 0) { + stlink_gui_set_info_error_message(gui, "Failed to write to flash"); } - g_idle_add ((GSourceFunc) stlink_gui_write_flash_update, gui); - return NULL; + g_idle_add((GSourceFunc)stlink_gui_write_flash_update, gui); + return(NULL); } -static void flash_button_cb (GtkWidget *widget, gpointer data) { +static void flash_button_cb(GtkWidget *widget, gpointer data) { STlinkGUI *gui; - gchar *tmp_str; - guint32 address; - gint result; - GError *err = NULL; - (void) widget; + gchar *tmp_str; + guint32 address; + gint result; + GError *err = NULL; + (void)widget; - gui = STLINK_GUI (data); - g_return_if_fail (gui->sl != NULL); + gui = STLINK_GUI(data); + g_return_if_fail(gui->sl != NULL); - if (!g_strcmp0 (gtk_entry_get_text (gui->flash_dialog_entry), "")) { - tmp_str = g_strdup_printf ("0x%08X", gui->sl->flash_base); - gtk_entry_set_text (gui->flash_dialog_entry, tmp_str); - g_free (tmp_str); + if (!g_strcmp0(gtk_entry_get_text(gui->flash_dialog_entry), "")) { + tmp_str = g_strdup_printf("0x%08X", gui->sl->flash_base); + gtk_entry_set_text(gui->flash_dialog_entry, tmp_str); + g_free(tmp_str); } - result = gtk_dialog_run (gui->flash_dialog); + result = gtk_dialog_run(gui->flash_dialog); + if (result == GTK_RESPONSE_OK) { - address = hexstr_to_guint32 (gtk_entry_get_text (gui->flash_dialog_entry), &err); + address = hexstr_to_guint32(gtk_entry_get_text(gui->flash_dialog_entry), &err); + if (err) { - stlink_gui_set_info_error_message (gui, err->message); + stlink_gui_set_info_error_message(gui, err->message); } else { if (address > gui->sl->flash_base + gui->sl->flash_size || address < gui->sl->flash_base) { - stlink_gui_set_info_error_message (gui, "Invalid address"); + stlink_gui_set_info_error_message(gui, "Invalid address"); } else if (address + gui->file_mem.size > gui->sl->flash_base + gui->sl->flash_size) { - stlink_gui_set_info_error_message (gui, "Binary overwrites flash"); + stlink_gui_set_info_error_message(gui, "Binary overwrites flash"); } else { - stlink_gui_set_sensitivity (gui, FALSE); - gtk_progress_bar_set_text (gui->progress.bar, "Writing to flash"); + stlink_gui_set_sensitivity(gui, FALSE); + gtk_progress_bar_set_text(gui->progress.bar, "Writing to flash"); gui->progress.activity_mode = TRUE; - gtk_widget_show (GTK_WIDGET (gui->progress.bar)); - g_thread_new ("flash", (GThreadFunc) stlink_gui_write_flash, gui); + gtk_widget_show(GTK_WIDGET(gui->progress.bar)); + g_thread_new("flash", (GThreadFunc)stlink_gui_write_flash, gui); } } } @@ -642,248 +659,258 @@ static void flash_button_cb (GtkWidget *widget, gpointer data) { int export_to_file(const char*filename, const struct mem_t flash_mem) { printf("%s\n", filename); - FILE * f=fopen(filename, "w"); - if (f == NULL) - return -1; - for (gsize i=0;iwindow, - GTK_FILE_CHOOSER_ACTION_SAVE, - "_Cancel", - GTK_RESPONSE_CANCEL, - "_Open", - GTK_RESPONSE_ACCEPT, - NULL); - GtkFileChooser *chooser = GTK_FILE_CHOOSER (dialog); - gtk_file_chooser_set_do_overwrite_confirmation (chooser, TRUE); - gint res = gtk_dialog_run (GTK_DIALOG (dialog)); + dialog = gtk_file_chooser_dialog_new("Save as", + gui->window, + GTK_FILE_CHOOSER_ACTION_SAVE, + "_Cancel", + GTK_RESPONSE_CANCEL, + "_Open", + GTK_RESPONSE_ACCEPT, + NULL); + GtkFileChooser *chooser = GTK_FILE_CHOOSER(dialog); + gtk_file_chooser_set_do_overwrite_confirmation(chooser, TRUE); + gint res = gtk_dialog_run(GTK_DIALOG(dialog)); + if (res == GTK_RESPONSE_ACCEPT) { char *filename; - filename = gtk_file_chooser_get_filename (chooser); - if (export_to_file (filename, gui->flash_mem) != 0) { + filename = gtk_file_chooser_get_filename(chooser); + + if (export_to_file(filename, gui->flash_mem) != 0) { stlink_gui_set_info_error_message(gui, "Failed to export flash"); } else { stlink_gui_set_info_error_message(gui, "Export successful"); } - g_free (filename); + + g_free(filename); } - gtk_widget_destroy (dialog); + gtk_widget_destroy(dialog); } -static gboolean progress_pulse_timeout (STlinkGUI *gui) { +static gboolean progress_pulse_timeout(STlinkGUI *gui) { if (gui->progress.activity_mode) { - gtk_progress_bar_pulse (gui->progress.bar); + gtk_progress_bar_pulse(gui->progress.bar); } else { - gtk_progress_bar_set_fraction (gui->progress.bar, gui->progress.fraction); + gtk_progress_bar_set_fraction(gui->progress.bar, gui->progress.fraction); } - return TRUE; + + return(TRUE); } -static void notebook_switch_page_cb ( - GtkNotebook *notebook, - GtkWidget *widget, - guint page_num, - gpointer data) { +static void notebook_switch_page_cb(GtkNotebook *notebook, + GtkWidget *widget, + guint page_num, + gpointer data) { STlinkGUI *gui; - (void) notebook; - (void) widget; + (void)notebook; + (void)widget; - gui = STLINK_GUI (data); + gui = STLINK_GUI(data); if (page_num == 1) { - if (gui->filename == NULL) - stlink_gui_open_file (gui); - } -} - -static void dnd_received_cb ( - GtkWidget *widget, - GdkDragContext *context, - gint x, - gint y, - GtkSelectionData *selection_data, - guint target_type, - guint timestamp, - gpointer data) { - GFile *file_uri; - gchar **file_list; + if (gui->filename == NULL) { stlink_gui_open_file(gui); } + } +} + +static void dnd_received_cb(GtkWidget *widget, + GdkDragContext *context, + gint x, + gint y, + GtkSelectionData *selection_data, + guint target_type, + guint timestamp, + gpointer data) { + GFile *file_uri; + gchar **file_list; const guchar *file_data; - STlinkGUI *gui = STLINK_GUI (data); + STlinkGUI *gui = STLINK_GUI(data); GtkListStore *store; - GtkTreeIter iter; - (void) widget; - (void) x; - (void) y; + GtkTreeIter iter; + (void)widget; + (void)x; + (void)y; - if (selection_data != NULL && gtk_selection_data_get_length (selection_data) > 0) { + if (selection_data != NULL && gtk_selection_data_get_length(selection_data) > 0) { switch (target_type) { case TARGET_FILENAME: - if (gui->filename) - g_free (gui->filename); + if (gui->filename) { + g_free(gui->filename); + } - file_data = gtk_selection_data_get_data (selection_data); - file_list = g_strsplit ((gchar *)file_data, "\r\n", 0); + file_data = gtk_selection_data_get_data(selection_data); + file_list = g_strsplit((gchar *)file_data, "\r\n", 0); - file_uri = g_file_new_for_uri (file_list[0]); - gui->filename = g_file_get_path (file_uri); + file_uri = g_file_new_for_uri(file_list[0]); + gui->filename = g_file_get_path(file_uri); - g_strfreev (file_list); - g_object_unref (file_uri); + g_strfreev(file_list); + g_object_unref(file_uri); - store = GTK_LIST_STORE (gtk_tree_view_get_model (gui->devmem_treeview)); - if (gtk_tree_model_get_iter_first (GTK_TREE_MODEL (store), &iter)) - gtk_list_store_clear (store); + store = GTK_LIST_STORE(gtk_tree_view_get_model(gui->devmem_treeview)); + + if (gtk_tree_model_get_iter_first(GTK_TREE_MODEL(store), &iter)) { + gtk_list_store_clear(store); + } - stlink_gui_set_sensitivity (gui, FALSE); - gtk_notebook_set_current_page (gui->notebook, PAGE_FILEMEM); - gtk_widget_show (GTK_WIDGET (gui->progress.bar)); - gtk_progress_bar_set_text (gui->progress.bar, "Reading file"); - g_thread_new ("file", (GThreadFunc) stlink_gui_populate_filemem_view, gui); + stlink_gui_set_sensitivity(gui, FALSE); + gtk_notebook_set_current_page(gui->notebook, PAGE_FILEMEM); + gtk_widget_show(GTK_WIDGET(gui->progress.bar)); + gtk_progress_bar_set_text(gui->progress.bar, "Reading file"); + g_thread_new("file", (GThreadFunc)stlink_gui_populate_filemem_view, gui); break; } } - gtk_drag_finish ( - context, - TRUE, - gdk_drag_context_get_suggested_action (context) == GDK_ACTION_MOVE, - timestamp); + + gtk_drag_finish( + context, + TRUE, + gdk_drag_context_get_suggested_action(context) == GDK_ACTION_MOVE, + timestamp); } -void stlink_gui_init_dnd (STlinkGUI *gui) { - GtkTargetEntry target_list[] = { { "text/uri-list", 0, TARGET_FILENAME }, }; +void stlink_gui_init_dnd(STlinkGUI *gui) { + GtkTargetEntry target_list[] = { + { "text/uri-list", 0, TARGET_FILENAME }, + }; gtk_drag_dest_set( - GTK_WIDGET (gui->window), - GTK_DEST_DEFAULT_ALL, - target_list, - G_N_ELEMENTS (target_list), - GDK_ACTION_COPY); + GTK_WIDGET(gui->window), + GTK_DEST_DEFAULT_ALL, + target_list, + G_N_ELEMENTS(target_list), + GDK_ACTION_COPY); - g_signal_connect (gui->window, "drag-data-received", G_CALLBACK (dnd_received_cb), gui); + g_signal_connect(gui->window, "drag-data-received", G_CALLBACK(dnd_received_cb), gui); } -static void stlink_gui_build_ui (STlinkGUI *gui) { - GtkBuilder *builder; +static void stlink_gui_build_ui(STlinkGUI *gui) { + GtkBuilder *builder; GtkListStore *devmem_store; GtkListStore *filemem_store; gchar *ui_file = STLINK_UI_DIR "/stlink-gui.ui"; - if (!g_file_test (ui_file, G_FILE_TEST_EXISTS)) ui_file = "stlink-gui.ui"; - builder = gtk_builder_new (); - if (!gtk_builder_add_from_file (builder, ui_file, NULL)) { - g_printerr ("Failed to load UI file: %s\n", ui_file); - exit (1); - } - - gui->window = GTK_WINDOW (gtk_builder_get_object (builder, "window")); - g_signal_connect (G_OBJECT (gui->window), "destroy", G_CALLBACK (gtk_main_quit), NULL); - - /* set up toolutton clicked callbacks */ - gui->open_button = GTK_TOOL_BUTTON (gtk_builder_get_object (builder, "open_button")); - g_signal_connect (G_OBJECT (gui->open_button), "clicked", G_CALLBACK (open_button_cb), gui); - - gui->connect_button = GTK_TOOL_BUTTON (gtk_builder_get_object (builder, "connect_button")); - g_signal_connect (G_OBJECT (gui->connect_button), "clicked", G_CALLBACK (connect_button_cb), gui); - - gui->disconnect_button = GTK_TOOL_BUTTON (gtk_builder_get_object (builder, "disconnect_button")); - g_signal_connect (G_OBJECT (gui->disconnect_button), "clicked", G_CALLBACK (disconnect_button_cb), gui); - - gui->flash_button = GTK_TOOL_BUTTON (gtk_builder_get_object (builder, "flash_button")); - g_signal_connect (G_OBJECT (gui->flash_button), "clicked", G_CALLBACK (flash_button_cb), gui); - - gui->export_button = GTK_TOOL_BUTTON (gtk_builder_get_object (builder, "export_button")); - g_signal_connect (G_OBJECT (gui->export_button), "clicked", G_CALLBACK (export_button_cb), gui); - - gui->devmem_treeview = GTK_TREE_VIEW (gtk_builder_get_object (builder, "devmem_treeview")); - mem_view_init_headers (gui->devmem_treeview); - devmem_store = gtk_list_store_new (5, - G_TYPE_STRING, - G_TYPE_STRING, - G_TYPE_STRING, - G_TYPE_STRING, - G_TYPE_STRING); - gtk_tree_view_set_model (gui->devmem_treeview, GTK_TREE_MODEL (devmem_store)); - g_object_unref (devmem_store); - - gui->filemem_treeview = GTK_TREE_VIEW (gtk_builder_get_object (builder, "filemem_treeview")); - mem_view_init_headers (gui->filemem_treeview); - filemem_store = gtk_list_store_new (5, - G_TYPE_STRING, - G_TYPE_STRING, - G_TYPE_STRING, - G_TYPE_STRING, - G_TYPE_STRING); - gtk_tree_view_set_model (gui->filemem_treeview, GTK_TREE_MODEL (filemem_store)); - g_object_unref (filemem_store); - - gui->core_id_label = GTK_LABEL (gtk_builder_get_object (builder, "core_id_value")); - gui->chip_id_label = GTK_LABEL (gtk_builder_get_object (builder, "chip_id_value")); - gui->flash_size_label = GTK_LABEL (gtk_builder_get_object (builder, "flash_size_value")); - gui->ram_size_label = GTK_LABEL (gtk_builder_get_object (builder, "ram_size_value")); - gui->device_frame = GTK_FRAME (gtk_builder_get_object (builder, "device_frame")); - - gui->notebook = GTK_NOTEBOOK (gtk_builder_get_object (builder, "mem_notebook")); - g_signal_connect (gui->notebook, "switch-page", G_CALLBACK (notebook_switch_page_cb), gui); - - gui->devmem_box = GTK_BOX (gtk_builder_get_object (builder, "devmem_box")); - gui->filemem_box = GTK_BOX (gtk_builder_get_object (builder, "filemem_box")); - - gui->devmem_jmp_entry = GTK_ENTRY (gtk_builder_get_object (builder, "devmem_jmp_entry")); - g_signal_connect (gui->devmem_jmp_entry, "activate", G_CALLBACK (devmem_jmp_cb), gui); - - gui->filemem_jmp_entry = GTK_ENTRY (gtk_builder_get_object (builder, "filemem_jmp_entry")); - g_signal_connect (gui->filemem_jmp_entry, "activate", G_CALLBACK (filemem_jmp_cb), gui); - gtk_editable_set_editable (GTK_EDITABLE (gui->filemem_jmp_entry), TRUE); - - gui->progress.bar = GTK_PROGRESS_BAR (gtk_builder_get_object (builder, "progressbar")); - gtk_progress_bar_set_show_text (gui->progress.bar, TRUE); - gui->progress.timer = g_timeout_add (100, (GSourceFunc) progress_pulse_timeout, gui); - - gui->statusbar = GTK_STATUSBAR (gtk_builder_get_object (builder, "statusbar")); - - gui->infobar = GTK_INFO_BAR (gtk_builder_get_object (builder, "infobar")); - gtk_info_bar_add_button (gui->infobar, "_OK", GTK_RESPONSE_OK); - gui->infolabel = GTK_LABEL (gtk_label_new ("")); - gtk_container_add (GTK_CONTAINER (gtk_info_bar_get_content_area (gui->infobar)), GTK_WIDGET (gui->infolabel)); - g_signal_connect (gui->infobar, "response", G_CALLBACK (gtk_widget_hide), NULL); - - /* flash dialog */ - gui->flash_dialog = GTK_DIALOG (gtk_builder_get_object (builder, "flash_dialog")); - g_signal_connect_swapped (gui->flash_dialog, "response", G_CALLBACK (gtk_widget_hide), gui->flash_dialog); - gui->flash_dialog_ok = GTK_BUTTON (gtk_builder_get_object (builder, "flash_dialog_ok_button")); - gui->flash_dialog_cancel = GTK_BUTTON (gtk_builder_get_object (builder, "flash_dialog_cancel_button")); - gui->flash_dialog_entry = GTK_ENTRY (gtk_builder_get_object (builder, "flash_dialog_entry")); - - /* make it so */ - gtk_widget_show_all (GTK_WIDGET (gui->window)); - gtk_widget_hide (GTK_WIDGET (gui->infobar)); - gtk_widget_hide (GTK_WIDGET (gui->progress.bar)); - - stlink_gui_set_disconnected (gui); -} - -int main (int argc, char **argv) { + if (!g_file_test(ui_file, G_FILE_TEST_EXISTS)) { ui_file = "stlink-gui.ui"; } + + builder = gtk_builder_new(); + + if (!gtk_builder_add_from_file(builder, ui_file, NULL)) { + g_printerr("Failed to load UI file: %s\n", ui_file); + exit(1); + } + + gui->window = GTK_WINDOW(gtk_builder_get_object(builder, "window")); + g_signal_connect(G_OBJECT(gui->window), "destroy", G_CALLBACK(gtk_main_quit), NULL); + + /* Setup for toolbutton clicked callbacks */ + gui->open_button = GTK_TOOL_BUTTON(gtk_builder_get_object(builder, "open_button")); + g_signal_connect(G_OBJECT(gui->open_button), "clicked", G_CALLBACK(open_button_cb), gui); + + gui->connect_button = GTK_TOOL_BUTTON(gtk_builder_get_object(builder, "connect_button")); + g_signal_connect(G_OBJECT(gui->connect_button), "clicked", G_CALLBACK(connect_button_cb), gui); + + gui->disconnect_button = GTK_TOOL_BUTTON(gtk_builder_get_object(builder, "disconnect_button")); + g_signal_connect(G_OBJECT(gui->disconnect_button), "clicked", G_CALLBACK(disconnect_button_cb), gui); + + gui->flash_button = GTK_TOOL_BUTTON(gtk_builder_get_object(builder, "flash_button")); + g_signal_connect(G_OBJECT(gui->flash_button), "clicked", G_CALLBACK(flash_button_cb), gui); + + gui->export_button = GTK_TOOL_BUTTON(gtk_builder_get_object(builder, "export_button")); + g_signal_connect(G_OBJECT(gui->export_button), "clicked", G_CALLBACK(export_button_cb), gui); + + gui->devmem_treeview = GTK_TREE_VIEW(gtk_builder_get_object(builder, "devmem_treeview")); + mem_view_init_headers(gui->devmem_treeview); + devmem_store = gtk_list_store_new(5, + G_TYPE_STRING, + G_TYPE_STRING, + G_TYPE_STRING, + G_TYPE_STRING, + G_TYPE_STRING); + gtk_tree_view_set_model(gui->devmem_treeview, GTK_TREE_MODEL(devmem_store)); + g_object_unref(devmem_store); + + gui->filemem_treeview = GTK_TREE_VIEW(gtk_builder_get_object(builder, "filemem_treeview")); + mem_view_init_headers(gui->filemem_treeview); + filemem_store = gtk_list_store_new(5, + G_TYPE_STRING, + G_TYPE_STRING, + G_TYPE_STRING, + G_TYPE_STRING, + G_TYPE_STRING); + gtk_tree_view_set_model(gui->filemem_treeview, GTK_TREE_MODEL(filemem_store)); + g_object_unref(filemem_store); + + gui->core_id_label = GTK_LABEL(gtk_builder_get_object(builder, "core_id_value")); + gui->chip_id_label = GTK_LABEL(gtk_builder_get_object(builder, "chip_id_value")); + gui->flash_size_label = GTK_LABEL(gtk_builder_get_object(builder, "flash_size_value")); + gui->ram_size_label = GTK_LABEL(gtk_builder_get_object(builder, "ram_size_value")); + gui->device_frame = GTK_FRAME(gtk_builder_get_object(builder, "device_frame")); + + gui->notebook = GTK_NOTEBOOK(gtk_builder_get_object(builder, "mem_notebook")); + g_signal_connect(gui->notebook, "switch-page", G_CALLBACK(notebook_switch_page_cb), gui); + + gui->devmem_box = GTK_BOX(gtk_builder_get_object(builder, "devmem_box")); + gui->filemem_box = GTK_BOX(gtk_builder_get_object(builder, "filemem_box")); + + gui->devmem_jmp_entry = GTK_ENTRY(gtk_builder_get_object(builder, "devmem_jmp_entry")); + g_signal_connect(gui->devmem_jmp_entry, "activate", G_CALLBACK(devmem_jmp_cb), gui); + + gui->filemem_jmp_entry = GTK_ENTRY(gtk_builder_get_object(builder, "filemem_jmp_entry")); + g_signal_connect(gui->filemem_jmp_entry, "activate", G_CALLBACK(filemem_jmp_cb), gui); + gtk_editable_set_editable(GTK_EDITABLE(gui->filemem_jmp_entry), TRUE); + + gui->progress.bar = GTK_PROGRESS_BAR(gtk_builder_get_object(builder, "progressbar")); + gtk_progress_bar_set_show_text(gui->progress.bar, TRUE); + gui->progress.timer = g_timeout_add(100, (GSourceFunc)progress_pulse_timeout, gui); + + gui->statusbar = GTK_STATUSBAR(gtk_builder_get_object(builder, "statusbar")); + + gui->infobar = GTK_INFO_BAR(gtk_builder_get_object(builder, "infobar")); + gtk_info_bar_add_button(gui->infobar, "_OK", GTK_RESPONSE_OK); + gui->infolabel = GTK_LABEL(gtk_label_new("")); + gtk_container_add(GTK_CONTAINER(gtk_info_bar_get_content_area(gui->infobar)), GTK_WIDGET(gui->infolabel)); + g_signal_connect(gui->infobar, "response", G_CALLBACK(gtk_widget_hide), NULL); + + /* Flash dialog */ + gui->flash_dialog = GTK_DIALOG(gtk_builder_get_object(builder, "flash_dialog")); + g_signal_connect_swapped(gui->flash_dialog, "response", G_CALLBACK(gtk_widget_hide), gui->flash_dialog); + gui->flash_dialog_ok = GTK_BUTTON(gtk_builder_get_object(builder, "flash_dialog_ok_button")); + gui->flash_dialog_cancel = GTK_BUTTON(gtk_builder_get_object(builder, "flash_dialog_cancel_button")); + gui->flash_dialog_entry = GTK_ENTRY(gtk_builder_get_object(builder, "flash_dialog_entry")); + + // make it so + gtk_widget_show_all(GTK_WIDGET(gui->window)); + gtk_widget_hide(GTK_WIDGET(gui->infobar)); + gtk_widget_hide(GTK_WIDGET(gui->progress.bar)); + + stlink_gui_set_disconnected(gui); +} + +int main(int argc, char **argv) { STlinkGUI *gui; - gtk_init (&argc, &argv); + gtk_init(&argc, &argv); - gui = g_object_new (STLINK_TYPE_GUI, NULL); - stlink_gui_build_ui (gui); - stlink_gui_init_dnd (gui); + gui = g_object_new(STLINK_TYPE_GUI, NULL); + stlink_gui_build_ui(gui); + stlink_gui_init_dnd(gui); - gtk_main (); - return 0; + gtk_main(); + return(0); } diff --git a/src/stlink-gui/gui.h b/src/stlink-gui/gui.h index c83e638f6..b3d5dfff8 100644 --- a/src/stlink-gui/gui.h +++ b/src/stlink-gui/gui.h @@ -1,19 +1,18 @@ - #ifndef __STLINK_GUI_H__ #define __STLINK_GUI_H__ #include -#define STLINK_TYPE_GUI (stlink_gui_get_type ()) -#define STLINK_GUI(obj) (G_TYPE_CHECK_INSTANCE_CAST ((obj), STLINK_TYPE_GUI, STlinkGUI)) -#define STLINK_IS_GUI(obj) (G_TYPE_CHECK_INSTANCE_TYPE ((obj), STLINK_TYPE_GUI)) -#define STLINK_GUI_CLASS(klass) (G_TYPE_CHECK_CLASS_CAST ((klass), STLINK_TYPE_GUI, STlinkGUIClass)) -#define STLINK_IS_GUI_CLASS(klass) (G_TYPE_CHECK_CLASS_TYPE ((klass), STLINK_TYPE_GUI)) -#define STLINK_GUI_GET_CLASS(obj) (G_TYPE_INSTANCE_GET_CLASS ((obj), STLINK_TYPE_GUI, STlinkGUIlass)) -#define STLINK_GUI_GET_PRIVATE(obj) (G_TYPE_INSTANCE_GET_PRIVATE ((obj), STLINK_TYPE_GUI, STlinkGUIPrivate)) +#define STLINK_TYPE_GUI (stlink_gui_get_type()) +#define STLINK_GUI(obj) (G_TYPE_CHECK_INSTANCE_CAST((obj), STLINK_TYPE_GUI, STlinkGUI)) +#define STLINK_IS_GUI(obj) (G_TYPE_CHECK_INSTANCE_TYPE((obj), STLINK_TYPE_GUI)) +#define STLINK_GUI_CLASS(klass) (G_TYPE_CHECK_CLASS_CAST((klass), STLINK_TYPE_GUI, STlinkGUIClass)) +#define STLINK_IS_GUI_CLASS(klass) (G_TYPE_CHECK_CLASS_TYPE((klass), STLINK_TYPE_GUI)) +#define STLINK_GUI_GET_CLASS(obj) (G_TYPE_INSTANCE_GET_CLASS((obj), STLINK_TYPE_GUI, STlinkGUIlass)) +#define STLINK_GUI_GET_PRIVATE(obj) (G_TYPE_INSTANCE_GET_PRIVATE((obj), STLINK_TYPE_GUI, STlinkGUIPrivate)) -typedef struct _STlinkGUI STlinkGUI; -typedef struct _STlinkGUIClass STlinkGUIClass; +typedef struct _STlinkGUI STlinkGUI; +typedef struct _STlinkGUIClass STlinkGUIClass; typedef struct _STlinkGUIPrivate STlinkGUIPrivate; enum stlink_gui_pages_t { @@ -28,21 +27,21 @@ enum stlink_gui_dnd_targets_t { struct progress_t { GtkProgressBar *bar; - guint timer; - gboolean activity_mode; - gdouble fraction; + guint timer; + gboolean activity_mode; + gdouble fraction; }; struct mem_t { guchar *memory; - gsize size; + gsize size; guint32 base; }; struct _STlinkGUI { GObject parent_instance; - /*< private >*/ + /* < private > */ GtkWindow *window; GtkTreeView *devmem_treeview; GtkTreeView *filemem_treeview; @@ -72,9 +71,9 @@ struct _STlinkGUI { GtkButton *flash_dialog_cancel; GtkEntry *flash_dialog_entry; - struct progress_t progress; - struct mem_t flash_mem; - struct mem_t file_mem; + struct progress_t progress; + struct mem_t flash_mem; + struct mem_t file_mem; gchar *error_message; gchar *filename; @@ -87,7 +86,7 @@ struct _STlinkGUIClass { /* class members */ }; -GType stlink_gui_get_type (void); +GType stlink_gui_get_type(void); int export_to_file(const char*filename, const struct mem_t flash_mem); -#endif +#endif // __STLINK_GUI_H__ diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index e6a82a2a9..bf0a56c96 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -2,636 +2,637 @@ #include "chipid.h" static const struct stlink_chipid_params devices[] = { - { - //RM0410 document was used to find these paramaters - .chip_id = STLINK_CHIPID_STM32_F7XXXX, - .description = "F76xxx", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1ff0f442, // section 45.2 - .flash_pagesize = 0x800, // No flash pages - .sram_size = 0x80000, // "SRAM" byte size in hex from - .bootrom_base = 0x00200000, //! "System memory" starting address from - .bootrom_size = 0xEDC0 //! @todo "System memory" byte size in hex from - }, - { - //RM0385 and DS10916 document was used to find these paramaters - .chip_id = STLINK_CHIPID_STM32_F7, - .description = "F7xx", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1ff0f442, // section 41.2 - .flash_pagesize = 0x800, // No flash pages - .sram_size = 0x50000, // "SRAM" byte size in hex from DS Fig 18 - .bootrom_base = 0x00100000, // "System memory" starting address from DS Fig 18 - .bootrom_size = 0xEDC0 // "System memory" byte size in hex from DS Fig 18 - }, - { - //RM0431 and DS document was used to find these paramaters - .chip_id = STLINK_CHIPID_STM32_F72XXX, - .description = "F72x/F73x", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1ff07a22, // section 35.2 - .flash_pagesize = 0x800, // No flash pages - .sram_size = 0x40000, // "SRAM" byte size in hex from DS Fig 24 - .bootrom_base = 0x00100000, // "System memory" starting address from DS Fig 24 - .bootrom_size = 0xEDC0 // "System memory" byte size in hex from DS Fig 24 - }, - { // table 2, PM0063 - .chip_id = STLINK_CHIPID_STM32_F1_MEDIUM, - .description = "F1xx Medium-density", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7e0, - .flash_pagesize = 0x400, - .sram_size = 0x5000, - .bootrom_base = 0x1ffff000, - .bootrom_size = 0x800 - }, - { // table 1, PM0059 - .chip_id = STLINK_CHIPID_STM32_F2, - .description = "F2xx", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1fff7a22, /* As in RM0033 Rev 5*/ - .flash_pagesize = 0x20000, - .sram_size = 0x20000, - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7800, - .option_base = 0x1FFFC000, - .option_size = 4, - }, - { // PM0063 - .chip_id = STLINK_CHIPID_STM32_F1_LOW, - .description = "F1 Low-density device", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7e0, - .flash_pagesize = 0x400, - .sram_size = 0x2800, - .bootrom_base = 0x1ffff000, - .bootrom_size = 0x800 - }, - { - .chip_id = STLINK_CHIPID_STM32_F4, - .description = "F4xx", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1FFF7A22, /* As in rm0090 since Rev 2*/ - .flash_pagesize = 0x4000, - .sram_size = 0x30000, - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7800 - }, - { - .chip_id = STLINK_CHIPID_STM32_F4_DSI, - .description = "F46x/F47x", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1FFF7A22, /* As in rm0090 since Rev 2*/ - .flash_pagesize = 0x4000, - .sram_size = 0x40000, - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7800 - }, - { - .chip_id = STLINK_CHIPID_STM32_F4_HD, - .description = "F42x/F43x", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1FFF7A22, /* As in rm0090 since Rev 2*/ - .flash_pagesize = 0x4000, - .sram_size = 0x40000, - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7800 - }, - { - .chip_id = STLINK_CHIPID_STM32_F4_LP, - .description = "F4xx (low power)", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1FFF7A22, - .flash_pagesize = 0x4000, - .sram_size = 0x10000, - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7800 - }, - { - .chip_id = STLINK_CHIPID_STM32_F411RE, - .description = "stm32f411re", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1FFF7A22, - .flash_pagesize = 0x4000, - .sram_size = 0x20000, - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7800 - }, - { - .chip_id = STLINK_CHIPID_STM32_F4_DE, - .description = "F4xx (Dynamic Efficency)", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1FFF7A22, - .flash_pagesize = 0x4000, - .sram_size = 0x18000, - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7800 - }, - { - .chip_id = STLINK_CHIPID_STM32_F1_HIGH, - .description = "F1xx High-density", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7e0, - .flash_pagesize = 0x800, - .sram_size = 0x10000, - .bootrom_base = 0x1ffff000, - .bootrom_size = 0x800 - }, - { - // This ignores the EEPROM! (and uses the page erase size, - // not the sector write protection...) - .chip_id = STLINK_CHIPID_STM32_L1_MEDIUM, - .description = "L1xx Medium-density", - .flash_type = STLINK_FLASH_TYPE_L0, - .flash_size_reg = 0x1ff8004c, - .flash_pagesize = 0x100, - .sram_size = 0x4000, - .bootrom_base = 0x1ff00000, - .bootrom_size = 0x1000 - }, - { - .chip_id = STLINK_CHIPID_STM32_L1_CAT2, - .description = "L1xx Cat.2", - .flash_type = STLINK_FLASH_TYPE_L0, - .flash_size_reg = 0x1ff8004c, - .flash_pagesize = 0x100, - .sram_size = 0x8000, - .bootrom_base = 0x1ff00000, - .bootrom_size = 0x1000 - }, - { - .chip_id = STLINK_CHIPID_STM32_L1_MEDIUM_PLUS, - .description = "L1xx Medium-Plus-density", - .flash_type = STLINK_FLASH_TYPE_L0, - .flash_size_reg = 0x1ff800cc, - .flash_pagesize = 0x100, - .sram_size = 0x8000,/*Not completely clear if there are some with 48K*/ - .bootrom_base = 0x1ff00000, - .bootrom_size = 0x1000 - }, - { - .chip_id = STLINK_CHIPID_STM32_L1_HIGH, - .description = "L1xx High-density", - .flash_type = STLINK_FLASH_TYPE_L0, - .flash_size_reg = 0x1ff800cc, - .flash_pagesize = 0x100, - .sram_size = 0xC000, /*Not completely clear if there are some with 32K*/ - .bootrom_base = 0x1ff00000, - .bootrom_size = 0x1000, - .option_base = STM32_L1_OPTION_BYTES_BASE, - .option_size = 8, - }, - { - .chip_id = STLINK_CHIPID_STM32_L152_RE, - .description = "L152RE", - .flash_type = STLINK_FLASH_TYPE_L0, - .flash_size_reg = 0x1ff800cc, - .flash_pagesize = 0x100, - .sram_size = 0x14000, /*Not completely clear if there are some with 32K*/ - .bootrom_base = 0x1ff00000, - .bootrom_size = 0x1000 - }, - { - .chip_id = STLINK_CHIPID_STM32_F1_CONN, - .description = "F1 Connectivity line", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7e0, - .flash_pagesize = 0x800, - .sram_size = 0x10000, - .bootrom_base = 0x1fffb000, - .bootrom_size = 0x4800 - }, - {//Low and Medium density VL have same chipid. RM0041 25.6.1 - .chip_id = STLINK_CHIPID_STM32_F1_VL_MEDIUM_LOW, - .description = "F1xx Value Line", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7e0, - .flash_pagesize = 0x400, - .sram_size = 0x2000,//0x1000 for low density devices - .bootrom_base = 0x1ffff000, - .bootrom_size = 0x800 - }, - { - // STM32F446x family. Support based on DM00135183.pdf (RM0390) document. - .chip_id = STLINK_CHIPID_STM32_F446, - .description = "F446", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1fff7a22, - .flash_pagesize = 0x20000, - .sram_size = 0x20000, - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7800, - .option_base = 0x1FFFC000, - .option_size = 4, - }, - { - // STM32F410 MCUs. Support based on DM00180366.pdf (RM0401) document. - .chip_id = STLINK_CHIPID_STM32_F410, - .description = "F410", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1fff7a22, - .flash_pagesize = 0x4000, - .sram_size = 0x8000, - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7800 - }, - { - // This is STK32F303VCT6 device from STM32 F3 Discovery board. - // Support based on DM00043574.pdf (RM0316) document. - .chip_id = STLINK_CHIPID_STM32_F3, - .description = "F3xx", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7cc, - .flash_pagesize = 0x800, - .sram_size = 0xa000, - .bootrom_base = 0x1ffff000, - .bootrom_size = 0x800 - }, - { - // This is STK32F373VCT6 device from STM32 F373 eval board - // Support based on 303 above (37x and 30x have same memory map) - .chip_id = STLINK_CHIPID_STM32_F37x, - .description = "F3xx", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7cc, - .flash_pagesize = 0x800, - .sram_size = 0xa000, - .bootrom_base = 0x1ffff000, - .bootrom_size = 0x800 - }, - { - .chip_id = STLINK_CHIPID_STM32_F1_VL_HIGH, - .description = "F1xx High-density value line", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7e0, - .flash_pagesize = 0x800, - .sram_size = 0x8000, - .bootrom_base = 0x1ffff000, - .bootrom_size = 0x800 - }, - { - .chip_id = STLINK_CHIPID_STM32_F1_XL, - .description = "F1xx XL-density", - .flash_type = STLINK_FLASH_TYPE_F1_XL, - .flash_size_reg = 0x1ffff7e0, - .flash_pagesize = 0x800, - .sram_size = 0x18000, - .bootrom_base = 0x1fffe000, - .bootrom_size = 0x1800 - }, - { - //Use this as an example for mapping future chips: - //RM0091 document was used to find these paramaters - .chip_id = STLINK_CHIPID_STM32_F0_CAN, - .description = "F07x", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) - .flash_pagesize = 0x800, // Page sizes listed in Table 4 - .sram_size = 0x4000, // "SRAM" byte size in hex from Table 2 - .bootrom_base = 0x1fffC800, // "System memory" starting address from Table 2 - .bootrom_size = 0x3000 // "System memory" byte size in hex from Table 2 - }, - { - //Use this as an example for mapping future chips: - //RM0091 document was used to find these paramaters - .chip_id = STLINK_CHIPID_STM32_F0, - .description = "F0xx", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) - .flash_pagesize = 0x400, // Page sizes listed in Table 4 - .sram_size = 0x2000, // "SRAM" byte size in hex from Table 2 - .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2 - .bootrom_size = 0xC00 // "System memory" byte size in hex from Table 2 - }, - { - // RM0402 document was used to find these parameters - // Table 4. - .chip_id = STLINK_CHIPID_STM32_F412, - .description = "F412", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1FFF7A22, // "Flash size data register" (pg1135) - .flash_pagesize = 0x4000, // Table 5. Flash module organization ? - .sram_size = 0x40000, // "SRAM" byte size in hex from Table 4 - .bootrom_base = 0x1FFF0000, // "System memory" starting address from Table 4 - .bootrom_size = 0x7800 // "System memory" byte size in hex from Table 4 - }, - { - // RM0430 DocID029473 Rev 2 document was used to find these parameters - // Figure 2, Table 4, Table 5, Section 35.2 - .chip_id = STLINK_CHIPID_STM32_F413, - .description = "F413", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1FFF7A22, // "Flash size data register" Section 35.2 - .flash_pagesize = 0x4000, // Table 5. Flash module organization (variable sector sizes, but 0x4000 is smallest) - .sram_size = 0x50000, // "SRAM" byte size in hex from Figure 2 (Table 4 only says 0x40000) - .bootrom_base = 0x1FFF0000, // "System memory" starting address from Table 4 - .bootrom_size = 0x7800 // "System memory" byte size in hex from Table 4 - }, - { - .chip_id = STLINK_CHIPID_STM32_F09X, - .description = "F09X", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) - .flash_pagesize = 0x800, // Page sizes listed in Table 4 (pg 56) - .sram_size = 0x8000, // "SRAM" byte size in hex from Table 2 (pg 50) - .bootrom_base = 0x1fffd800, // "System memory" starting address from Table 2 - .bootrom_size = 0x2000 // "System memory" byte size in hex from Table 2 - }, - { - //Use this as an example for mapping future chips: - //RM0091 document was used to find these paramaters - .chip_id = STLINK_CHIPID_STM32_F04, - .description = "F04x", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) - .flash_pagesize = 0x400, // Page sizes listed in Table 4 - .sram_size = 0x1800, // "SRAM" byte size in hex from Table 2 - .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2 - .bootrom_size = 0xC00 // "System memory" byte size in hex from Table 2 - }, - { - //Use this as an example for mapping future chips: - //RM0091 document was used to find these paramaters - .chip_id = STLINK_CHIPID_STM32_F0_SMALL, - .description = "F0xx small", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) - .flash_pagesize = 0x400, // Page sizes listed in Table 4 - .sram_size = 0x1000, // "SRAM" byte size in hex from Table 2 - .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2 - .bootrom_size = 0xC00 // "System memory" byte size in hex from Table 2 - }, - { - // STM32F30x - .chip_id = STLINK_CHIPID_STM32_F3_SMALL, - .description = "F3xx small", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7cc, - .flash_pagesize = 0x800, - .sram_size = 0xa000, - .bootrom_base = 0x1fffd800, - .bootrom_size = 0x2000 - }, - { - // STM32L0x - // RM0367,RM0377 documents was used to find these parameters - .chip_id = STLINK_CHIPID_STM32_L0, - .description = "L0x3", - .flash_type = STLINK_FLASH_TYPE_L0, - .flash_size_reg = 0x1ff8007c, - .flash_pagesize = 0x80, - .sram_size = 0x2000, - .bootrom_base = 0x1ff0000, - .bootrom_size = 0x1000, - .option_base = STM32_L0_CATx_OPTION_BYTES_BASE, - .option_size = 4, - }, - { - // STM32L0x Category 5 - // RM0367,RM0377 documents was used to find these parameters - .chip_id = STLINK_CHIPID_STM32_L0_CAT5, - .description = "L0xx Category 5", - .flash_type = STLINK_FLASH_TYPE_L0, - .flash_size_reg = 0x1ff8007c, - .flash_pagesize = 0x80, - .sram_size = 0x5000, - .bootrom_base = 0x1ff0000, - .bootrom_size = 0x2000, - .option_base = STM32_L0_CATx_OPTION_BYTES_BASE, - .option_size = 4, - }, - { - // STM32L0x Category 2 - // RM0367,RM0377 documents was used to find these parameters - .chip_id = STLINK_CHIPID_STM32_L0_CAT2, - .description = "L0xx Category 2", - .flash_type = STLINK_FLASH_TYPE_L0, - .flash_size_reg = 0x1ff8007c, - .flash_pagesize = 0x80, - .sram_size = 0x2000, - .bootrom_base = 0x1ff0000, - .bootrom_size = 0x1000, - .option_base = STM32_L0_CATx_OPTION_BYTES_BASE, - .option_size = 4, - }, - { - // STM32F334, STM32F303x6/8, and STM32F328 - // From RM0364 and RM0316 - .chip_id = STLINK_CHIPID_STM32_F334, - .description = "F334 medium density", // (RM0316 sec 33.6.1) - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7cc, - .flash_pagesize = 0x800, - .sram_size = 0x3000, - .bootrom_base = 0x1fffd800, - .bootrom_size = 0x2000 - }, - { - // This is STK32F303RET6 device from STM32 F3 Nucelo board. - // Support based on DM00043574.pdf (RM0316) document rev 5. - .chip_id = STLINK_CHIPID_STM32_F303_HIGH, - .description = "F303 high density", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7cc, // 34.2.1 Flash size data register - .flash_pagesize = 0x800, // 4.2.1 Flash memory organization - .sram_size = 0x10000, // 3.3 Embedded SRAM - .bootrom_base = 0x1fffd800, // 3.3.2 / Table 4 System Memory - .bootrom_size = 0x2000 - }, - { - // STM32L4x6 - // From RM0351. - .chip_id = STLINK_CHIPID_STM32_L4, - .description = "L4xx", - .flash_type = STLINK_FLASH_TYPE_L4, - .flash_size_reg = 0x1FFF75e0, // "Flash size data register" (sec 45.2, page 1671) - .flash_pagesize = 0x800, // 2K (sec 3.2, page 78; also appears in sec 3.3.1 and tables 4-6 on pages 79-81) - // SRAM1 is "up to" 96k in the standard Cortex-M memory map; - // SRAM2 is 32k mapped at at 0x10000000 (sec 2.3, page 73 for - // sizes; table 2, page 74 for SRAM2 location) - .sram_size = 0x18000, - .bootrom_base = 0x1fff0000, // Tables 4-6, pages 80-81 (Bank 1 system memory) - .bootrom_size = 0x7000, // 28k (per bank), same source as base - .option_base = STM32_L4_OPTION_BYTES_BASE, - .option_size = 4, - }, - { - // STM32L4RX - // From DM00310109.pdf - .chip_id = STLINK_CHIPID_STM32_L4RX, - .description = "L4Rx", - .flash_type = STLINK_FLASH_TYPE_L4, - .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 52.2, page 2049) - .flash_pagesize = 0x1000, // 4k, section 3.3, pg 97 - .sram_size = 0xa0000, // 192k (SRAM1) + 64k SRAM2 + 384k SRAM3 = 640k, or 0xA0000 - .bootrom_base = 0x1fff0000, // 3.3.1, pg 99 - .bootrom_size = 0x7000 // 28k (per bank), same source as base (pg 99) - }, - { - // STLINK_CHIPID_STM32_L41X - // From RM0394 Rev 4 and DS12469 Rev 5 - .chip_id = STLINK_CHIPID_STM32_L41X, - .description = "L41x", - .flash_type = STLINK_FLASH_TYPE_L4, - .flash_size_reg = 0x1fff75e0, // "Flash size data register" (RM0394, sec 47.2, page 1586) - .flash_pagesize = 0x800, // 2K (DS12469, sec 3.4, page 17) - // SRAM1 is 32k at 0x20000000 - // SRAM2 is 8k at 0x10000000 and 0x20008000 (DS12469, sec 3.5, page 18) - .sram_size = 0xa000, // 40K (DS12469, sec 3.5, page 18) - .bootrom_base = 0x1fff0000, // System Memory (RM0394, sec 3.3.1, table 8) - .bootrom_size = 0x7000 // 28k, same source as base - }, - { - // STLINK_CHIPID_STM32_L43X - // From RM0392. - .chip_id = STLINK_CHIPID_STM32_L43X, - .description = "L43x/L44x", - .flash_type = STLINK_FLASH_TYPE_L4, - .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 43.2, page 1410) - .flash_pagesize = 0x800, // 2K (sec 3.2, page 74; also appears in sec 3.3.1 and tables 7-8 on pages 75-76) - // SRAM1 is "up to" 64k in the standard Cortex-M memory map; - // SRAM2 is 16k mapped at 0x10000000 (sec 2.3, page 73 for - // sizes; table 2, page 74 for SRAM2 location) - .sram_size = 0xc000, - .bootrom_base = 0x1fff0000, // Tables 4-6, pages 80-81 (Bank 1 system memory) - .bootrom_size = 0x7000, // 28k (per bank), same source as base - .option_base = STM32_L4_OPTION_BYTES_BASE, - .option_size = 4, - }, - { - // STLINK_CHIPID_STM32_L496X - // Support based on en.DM00083560.pdf (RM0351) document rev 5. - .chip_id = STLINK_CHIPID_STM32_L496X, - .description = "L496x/L4A6x", - .flash_type = STLINK_FLASH_TYPE_L4, - .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 49.2, page 1809) - .flash_pagesize = 0x800, // Page erase (2 Kbyte) (sec 3.2, page 93) - // SRAM1 is 256k at 0x20000000 - // SRAM2 is 64k at 0x20040000 (sec 2.2.1, fig 2, page 74) - .sram_size = 0x40000, // Embedded SRAM (sec 2.4, page 84) - .bootrom_base = 0x1fff0000, // System Memory (Bank 1) (sec 3.3.1) - .bootrom_size = 0x7000, // 28k (per bank), same source as base - .option_base = STM32_L4_OPTION_BYTES_BASE, - .option_size = 4, - }, - { - // STLINK_CHIPID_STM32_L46X - // From RM0394 (updated version of RM0392?). - .chip_id = STLINK_CHIPID_STM32_L46X, - .description = "L45x/46x", - .flash_type = STLINK_FLASH_TYPE_L4, - .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 45.2, page 1463) - .flash_pagesize = 0x800, // 2K (sec 3.2, page 73; also appears in sec 3.3.1 and tables 7 on pages 73-74) - // SRAM1 is 128k at 0x20000000; - // SRAM2 is 32k mapped at 0x10000000 (sec 2.4.2, table 3-4, page 68, also fig 2 on page 63) - .sram_size = 0x20000, - .bootrom_base = 0x1fff0000, // Tables 6, pages 71-72 (Bank 1 system memory, also fig 2 on page 63) - .bootrom_size = 0x7000 // 28k (per bank), same source as base - }, - { - // STM32L011 - .chip_id = STLINK_CHIPID_STM32_L011, - .description = "L011", - .flash_type = STLINK_FLASH_TYPE_L0, - .flash_size_reg = 0x1ff8007c, - .flash_pagesize = 0x80, - .sram_size = 0x2000, - .bootrom_base = 0x1ff00000, - .bootrom_size = 0x2000 - }, - { - // STM32G030/031/041 (from RM0454 & RM0444) - .chip_id = STLINK_CHIPID_STM32_G0_CAT1, - .description = "G030/G031/G041", - .flash_type = STLINK_FLASH_TYPE_G0, - .flash_size_reg = 0x1FFF75E0, // Section 38.2 - .flash_pagesize = 0x800, // 2K (sec 3.2) - .sram_size = 0x2000, // 8K (sec 2.3) - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x2000, // 8K (sec 2.2.2 table 3) - .option_base = STM32_G0_OPTION_BYTES_BASE, - .option_size = 4, - }, - { - // STM32G071/081 (from RM0444) - .chip_id = STLINK_CHIPID_STM32_G0_CAT2, - .description = "G070/G071/G081", - .flash_type = STLINK_FLASH_TYPE_G0, - .flash_size_reg = 0x1FFF75E0, // Section 38.2 - .flash_pagesize = 0x800, // 2K (sec 3.2) - .sram_size = 0x9000, // 36K (sec 2.3) - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7000, // 28K (sec 2.2.2 table 2) - .option_base = STM32_G0_OPTION_BYTES_BASE, - .option_size = 4, - }, - { - // STM32G431/441 (from RM0440) - .chip_id = STLINK_CHIPID_STM32_G4_CAT2, - .description = "G4 Category-2", - .flash_type = STLINK_FLASH_TYPE_G4, - .flash_size_reg = 0x1FFF75E0, // Section 47.2 - .flash_pagesize = 0x800, // 2K (sec 3.3.1) - // SRAM1 is 16k at 0x20000000 - // SRAM2 is 6k at 0x20014000 - // SRAM3/CCM is 10k at 0x10000000, aliased at 0x20018000 - .sram_size = 0x8000, // 32K (sec 2.4) - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7000, // 28K (table 2) - .option_base = STM32_G4_OPTION_BYTES_BASE, - .option_size = 4, - }, - { - // STM32G471/473/474/483/484 (from RM0440) - .chip_id = STLINK_CHIPID_STM32_G4_CAT3, - .description = "G4 Category-3", - .flash_type = STLINK_FLASH_TYPE_G4, - .has_dual_bank = true, - .flash_size_reg = 0x1FFF75E0, // Section 47.2 - .flash_pagesize = 0x800, // 2K (sec 3.3.1) - // SRAM1 is 80k at 0x20000000 - // SRAM2 is 16k at 0x20014000 - // SRAM3/CCM is 32k at 0x10000000, aliased at 0x20018000 - .sram_size = 0x18000, // 128K (sec 2.4) - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7000, // 28K (table 2) - .option_base = STM32_G4_OPTION_BYTES_BASE, - .option_size = 4, - }, - { - // STM32WB55 (from RM0434) - .chip_id = STLINK_CHIPID_STM32_WB55, - .description = "WB55", - .flash_type = STLINK_FLASH_TYPE_WB, - .flash_size_reg = 0x1FFF75E0, - .flash_pagesize = 0x1000, // 4K - .sram_size = 0x40000, - .bootrom_base = 0x1fff0000, // See the memory map - .bootrom_size = 0x7000 - }, - { - // unknown - .chip_id = STLINK_CHIPID_UNKNOWN, - .description = "unknown device", - .flash_type = STLINK_FLASH_TYPE_UNKNOWN, - .flash_size_reg = 0x0, - .flash_pagesize = 0x0, - .sram_size = 0x0, - .bootrom_base = 0x0, - .bootrom_size = 0x0 - }, - }; + { + // RM0410 document was used to find these paramaters + .chip_id = STLINK_CHIPID_STM32_F7XXXX, + .description = "F76xxx", + .flash_type = STLINK_FLASH_TYPE_F4, + .flash_size_reg = 0x1ff0f442, // section 45.2 + .flash_pagesize = 0x800, // No flash pages + .sram_size = 0x80000, // "SRAM" byte size in hex from + .bootrom_base = 0x00200000, // ! "System memory" starting address from + .bootrom_size = 0xEDC0 // ! @todo "System memory" byte size in hex from + }, + { + // RM0385 and DS10916 document was used to find these paramaters + .chip_id = STLINK_CHIPID_STM32_F7, + .description = "F7xx", + .flash_type = STLINK_FLASH_TYPE_F4, + .flash_size_reg = 0x1ff0f442, // section 41.2 + .flash_pagesize = 0x800, // No flash pages + .sram_size = 0x50000, // "SRAM" byte size in hex from DS Fig 18 + .bootrom_base = 0x00100000, // "System memory" starting address from DS Fig 18 + .bootrom_size = 0xEDC0 // "System memory" byte size in hex from DS Fig 18 + }, + { + // RM0431 and DS document was used to find these paramaters + .chip_id = STLINK_CHIPID_STM32_F72XXX, + .description = "F72x/F73x", + .flash_type = STLINK_FLASH_TYPE_F4, + .flash_size_reg = 0x1ff07a22, // section 35.2 + .flash_pagesize = 0x800, // No flash pages + .sram_size = 0x40000, // "SRAM" byte size in hex from DS Fig 24 + .bootrom_base = 0x00100000, // "System memory" starting address from DS Fig 24 + .bootrom_size = 0xEDC0 // "System memory" byte size in hex from DS Fig 24 + }, + { // table 2, PM0063 + .chip_id = STLINK_CHIPID_STM32_F1_MEDIUM, + .description = "F1xx Medium-density", + .flash_type = STLINK_FLASH_TYPE_F0, + .flash_size_reg = 0x1ffff7e0, + .flash_pagesize = 0x400, + .sram_size = 0x5000, + .bootrom_base = 0x1ffff000, + .bootrom_size = 0x800 + }, + { // table 1, PM0059 + .chip_id = STLINK_CHIPID_STM32_F2, + .description = "F2xx", + .flash_type = STLINK_FLASH_TYPE_F4, + .flash_size_reg = 0x1fff7a22, // as in RM0033 Rev 5 + .flash_pagesize = 0x20000, + .sram_size = 0x20000, + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x7800, + .option_base = 0x1FFFC000, + .option_size = 4, + }, + { // PM0063 + .chip_id = STLINK_CHIPID_STM32_F1_LOW, + .description = "F1 Low-density device", + .flash_type = STLINK_FLASH_TYPE_F0, + .flash_size_reg = 0x1ffff7e0, + .flash_pagesize = 0x400, + .sram_size = 0x2800, + .bootrom_base = 0x1ffff000, + .bootrom_size = 0x800 + }, + { + .chip_id = STLINK_CHIPID_STM32_F4, + .description = "F4xx", + .flash_type = STLINK_FLASH_TYPE_F4, + .flash_size_reg = 0x1FFF7A22, // As in rm0090 since Rev 2 + .flash_pagesize = 0x4000, + .sram_size = 0x30000, + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x7800 + }, + { + .chip_id = STLINK_CHIPID_STM32_F4_DSI, + .description = "F46x/F47x", + .flash_type = STLINK_FLASH_TYPE_F4, + .flash_size_reg = 0x1FFF7A22, // As in rm0090 since Rev 2 + .flash_pagesize = 0x4000, + .sram_size = 0x40000, + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x7800 + }, + { + .chip_id = STLINK_CHIPID_STM32_F4_HD, + .description = "F42x/F43x", + .flash_type = STLINK_FLASH_TYPE_F4, + .flash_size_reg = 0x1FFF7A22, // As in rm0090 since Rev 2 + .flash_pagesize = 0x4000, + .sram_size = 0x40000, + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x7800 + }, + { + .chip_id = STLINK_CHIPID_STM32_F4_LP, + .description = "F4xx (low power)", + .flash_type = STLINK_FLASH_TYPE_F4, + .flash_size_reg = 0x1FFF7A22, + .flash_pagesize = 0x4000, + .sram_size = 0x10000, + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x7800 + }, + { + .chip_id = STLINK_CHIPID_STM32_F411RE, + .description = "stm32f411re", + .flash_type = STLINK_FLASH_TYPE_F4, + .flash_size_reg = 0x1FFF7A22, + .flash_pagesize = 0x4000, + .sram_size = 0x20000, + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x7800 + }, + { + .chip_id = STLINK_CHIPID_STM32_F4_DE, + .description = "F4xx (Dynamic Efficency)", + .flash_type = STLINK_FLASH_TYPE_F4, + .flash_size_reg = 0x1FFF7A22, + .flash_pagesize = 0x4000, + .sram_size = 0x18000, + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x7800 + }, + { + .chip_id = STLINK_CHIPID_STM32_F1_HIGH, + .description = "F1xx High-density", + .flash_type = STLINK_FLASH_TYPE_F0, + .flash_size_reg = 0x1ffff7e0, + .flash_pagesize = 0x800, + .sram_size = 0x10000, + .bootrom_base = 0x1ffff000, + .bootrom_size = 0x800 + }, + { + // This ignores the EEPROM! (and uses the page erase size, + // not the sector write protection...) + .chip_id = STLINK_CHIPID_STM32_L1_MEDIUM, + .description = "L1xx Medium-density", + .flash_type = STLINK_FLASH_TYPE_L0, + .flash_size_reg = 0x1ff8004c, + .flash_pagesize = 0x100, + .sram_size = 0x4000, + .bootrom_base = 0x1ff00000, + .bootrom_size = 0x1000 + }, + { + .chip_id = STLINK_CHIPID_STM32_L1_CAT2, + .description = "L1xx Cat.2", + .flash_type = STLINK_FLASH_TYPE_L0, + .flash_size_reg = 0x1ff8004c, + .flash_pagesize = 0x100, + .sram_size = 0x8000, + .bootrom_base = 0x1ff00000, + .bootrom_size = 0x1000 + }, + { + .chip_id = STLINK_CHIPID_STM32_L1_MEDIUM_PLUS, + .description = "L1xx Medium-Plus-density", + .flash_type = STLINK_FLASH_TYPE_L0, + .flash_size_reg = 0x1ff800cc, + .flash_pagesize = 0x100, + .sram_size = 0x8000, // not completely clear if there are some with 48k + .bootrom_base = 0x1ff00000, + .bootrom_size = 0x1000 + }, + { + .chip_id = STLINK_CHIPID_STM32_L1_HIGH, + .description = "L1xx High-density", + .flash_type = STLINK_FLASH_TYPE_L0, + .flash_size_reg = 0x1ff800cc, + .flash_pagesize = 0x100, + .sram_size = 0xC000, // not completely clear if there are some with 32k + .bootrom_base = 0x1ff00000, + .bootrom_size = 0x1000, + .option_base = STM32_L1_OPTION_BYTES_BASE, + .option_size = 8, + }, + { + .chip_id = STLINK_CHIPID_STM32_L152_RE, + .description = "L152RE", + .flash_type = STLINK_FLASH_TYPE_L0, + .flash_size_reg = 0x1ff800cc, + .flash_pagesize = 0x100, + .sram_size = 0x14000, // not completely clear if there are some with 32k + .bootrom_base = 0x1ff00000, + .bootrom_size = 0x1000 + }, + { + .chip_id = STLINK_CHIPID_STM32_F1_CONN, + .description = "F1 Connectivity line", + .flash_type = STLINK_FLASH_TYPE_F0, + .flash_size_reg = 0x1ffff7e0, + .flash_pagesize = 0x800, + .sram_size = 0x10000, + .bootrom_base = 0x1fffb000, + .bootrom_size = 0x4800 + }, + { // Low and Medium density VL have same chipid. RM0041 25.6.1 + .chip_id = STLINK_CHIPID_STM32_F1_VL_MEDIUM_LOW, + .description = "F1xx Value Line", + .flash_type = STLINK_FLASH_TYPE_F0, + .flash_size_reg = 0x1ffff7e0, + .flash_pagesize = 0x400, + .sram_size = 0x2000, // 0x1000 for low density devices + .bootrom_base = 0x1ffff000, + .bootrom_size = 0x800 + }, + { + // STM32F446x family. Support based on DM00135183.pdf (RM0390) document. + .chip_id = STLINK_CHIPID_STM32_F446, + .description = "F446", + .flash_type = STLINK_FLASH_TYPE_F4, + .flash_size_reg = 0x1fff7a22, + .flash_pagesize = 0x20000, + .sram_size = 0x20000, + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x7800, + .option_base = 0x1FFFC000, + .option_size = 4, + }, + { + // STM32F410 MCUs. Support based on DM00180366.pdf (RM0401) document. + .chip_id = STLINK_CHIPID_STM32_F410, + .description = "F410", + .flash_type = STLINK_FLASH_TYPE_F4, + .flash_size_reg = 0x1fff7a22, + .flash_pagesize = 0x4000, + .sram_size = 0x8000, + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x7800 + }, + { + // This is STK32F303VCT6 device from STM32 F3 Discovery board. + // Support based on DM00043574.pdf (RM0316) document. + .chip_id = STLINK_CHIPID_STM32_F3, + .description = "F3xx", + .flash_type = STLINK_FLASH_TYPE_F0, + .flash_size_reg = 0x1ffff7cc, + .flash_pagesize = 0x800, + .sram_size = 0xa000, + .bootrom_base = 0x1ffff000, + .bootrom_size = 0x800 + }, + { + // This is STK32F373VCT6 device from STM32 F373 eval board + // Support based on 303 above (37x and 30x have same memory map) + .chip_id = STLINK_CHIPID_STM32_F37x, + .description = "F3xx", + .flash_type = STLINK_FLASH_TYPE_F0, + .flash_size_reg = 0x1ffff7cc, + .flash_pagesize = 0x800, + .sram_size = 0xa000, + .bootrom_base = 0x1ffff000, + .bootrom_size = 0x800 + }, + { + .chip_id = STLINK_CHIPID_STM32_F1_VL_HIGH, + .description = "F1xx High-density value line", + .flash_type = STLINK_FLASH_TYPE_F0, + .flash_size_reg = 0x1ffff7e0, + .flash_pagesize = 0x800, + .sram_size = 0x8000, + .bootrom_base = 0x1ffff000, + .bootrom_size = 0x800 + }, + { + .chip_id = STLINK_CHIPID_STM32_F1_XL, + .description = "F1xx XL-density", + .flash_type = STLINK_FLASH_TYPE_F1_XL, + .flash_size_reg = 0x1ffff7e0, + .flash_pagesize = 0x800, + .sram_size = 0x18000, + .bootrom_base = 0x1fffe000, + .bootrom_size = 0x1800 + }, + { + // Use this as an example for mapping future chips: + // RM0091 document was used to find these paramaters + .chip_id = STLINK_CHIPID_STM32_F0_CAN, + .description = "F07x", + .flash_type = STLINK_FLASH_TYPE_F0, + .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) + .flash_pagesize = 0x800, // Page sizes listed in Table 4 + .sram_size = 0x4000, // "SRAM" byte size in hex from Table 2 + .bootrom_base = 0x1fffC800, // "System memory" starting address from Table 2 + .bootrom_size = 0x3000 // "System memory" byte size in hex from Table 2 + }, + { + // Use this as an example for mapping future chips: + // RM0091 document was used to find these paramaters + .chip_id = STLINK_CHIPID_STM32_F0, + .description = "F0xx", + .flash_type = STLINK_FLASH_TYPE_F0, + .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) + .flash_pagesize = 0x400, // Page sizes listed in Table 4 + .sram_size = 0x2000, // "SRAM" byte size in hex from Table 2 + .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2 + .bootrom_size = 0xC00 // "System memory" byte size in hex from Table 2 + }, + { + // RM0402 document was used to find these parameters + // Table 4. + .chip_id = STLINK_CHIPID_STM32_F412, + .description = "F412", + .flash_type = STLINK_FLASH_TYPE_F4, + .flash_size_reg = 0x1FFF7A22, // "Flash size data register" (pg1135) + .flash_pagesize = 0x4000, // Table 5. Flash module organization ? + .sram_size = 0x40000, // "SRAM" byte size in hex from Table 4 + .bootrom_base = 0x1FFF0000, // "System memory" starting address from Table 4 + .bootrom_size = 0x7800 // "System memory" byte size in hex from Table 4 + }, + { + // RM0430 DocID029473 Rev 2 document was used to find these parameters + // Figure 2, Table 4, Table 5, Section 35.2 + .chip_id = STLINK_CHIPID_STM32_F413, + .description = "F413", + .flash_type = STLINK_FLASH_TYPE_F4, + .flash_size_reg = 0x1FFF7A22, // "Flash size data register" Section 35.2 + .flash_pagesize = 0x4000, // Table 5. Flash module organization (variable sector sizes, but 0x4000 is smallest) + .sram_size = 0x50000, // "SRAM" byte size in hex from Figure 2 (Table 4 only says 0x40000) + .bootrom_base = 0x1FFF0000, // "System memory" starting address from Table 4 + .bootrom_size = 0x7800 // "System memory" byte size in hex from Table 4 + }, + { + .chip_id = STLINK_CHIPID_STM32_F09X, + .description = "F09X", + .flash_type = STLINK_FLASH_TYPE_F0, + .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) + .flash_pagesize = 0x800, // Page sizes listed in Table 4 (pg 56) + .sram_size = 0x8000, // "SRAM" byte size in hex from Table 2 (pg 50) + .bootrom_base = 0x1fffd800, // "System memory" starting address from Table 2 + .bootrom_size = 0x2000 // "System memory" byte size in hex from Table 2 + }, + { + // Use this as an example for mapping future chips: + // RM0091 document was used to find these paramaters + .chip_id = STLINK_CHIPID_STM32_F04, + .description = "F04x", + .flash_type = STLINK_FLASH_TYPE_F0, + .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) + .flash_pagesize = 0x400, // Page sizes listed in Table 4 + .sram_size = 0x1800, // "SRAM" byte size in hex from Table 2 + .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2 + .bootrom_size = 0xC00 // "System memory" byte size in hex from Table 2 + }, + { + // Use this as an example for mapping future chips: + // RM0091 document was used to find these paramaters + .chip_id = STLINK_CHIPID_STM32_F0_SMALL, + .description = "F0xx small", + .flash_type = STLINK_FLASH_TYPE_F0, + .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) + .flash_pagesize = 0x400, // Page sizes listed in Table 4 + .sram_size = 0x1000, // "SRAM" byte size in hex from Table 2 + .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2 + .bootrom_size = 0xC00 // "System memory" byte size in hex from Table 2 + }, + { + // STM32F30x + .chip_id = STLINK_CHIPID_STM32_F3_SMALL, + .description = "F3xx small", + .flash_type = STLINK_FLASH_TYPE_F0, + .flash_size_reg = 0x1ffff7cc, + .flash_pagesize = 0x800, + .sram_size = 0xa000, + .bootrom_base = 0x1fffd800, + .bootrom_size = 0x2000 + }, + { + // STM32L0x + // RM0367,RM0377 documents was used to find these parameters + .chip_id = STLINK_CHIPID_STM32_L0, + .description = "L0x3", + .flash_type = STLINK_FLASH_TYPE_L0, + .flash_size_reg = 0x1ff8007c, + .flash_pagesize = 0x80, + .sram_size = 0x2000, + .bootrom_base = 0x1ff0000, + .bootrom_size = 0x1000, + .option_base = STM32_L0_CATx_OPTION_BYTES_BASE, + .option_size = 4, + }, + { + // STM32L0x Category 5 + // RM0367,RM0377 documents was used to find these parameters + .chip_id = STLINK_CHIPID_STM32_L0_CAT5, + .description = "L0xx Category 5", + .flash_type = STLINK_FLASH_TYPE_L0, + .flash_size_reg = 0x1ff8007c, + .flash_pagesize = 0x80, + .sram_size = 0x5000, + .bootrom_base = 0x1ff0000, + .bootrom_size = 0x2000, + .option_base = STM32_L0_CATx_OPTION_BYTES_BASE, + .option_size = 4, + }, + { + // STM32L0x Category 2 + // RM0367,RM0377 documents was used to find these parameters + .chip_id = STLINK_CHIPID_STM32_L0_CAT2, + .description = "L0xx Category 2", + .flash_type = STLINK_FLASH_TYPE_L0, + .flash_size_reg = 0x1ff8007c, + .flash_pagesize = 0x80, + .sram_size = 0x2000, + .bootrom_base = 0x1ff0000, + .bootrom_size = 0x1000, + .option_base = STM32_L0_CATx_OPTION_BYTES_BASE, + .option_size = 4, + }, + { + // STM32F334, STM32F303x6/8, and STM32F328 + // From RM0364 and RM0316 + .chip_id = STLINK_CHIPID_STM32_F334, + .description = "F334 medium density", // (RM0316 sec 33.6.1) + .flash_type = STLINK_FLASH_TYPE_F0, + .flash_size_reg = 0x1ffff7cc, + .flash_pagesize = 0x800, + .sram_size = 0x3000, + .bootrom_base = 0x1fffd800, + .bootrom_size = 0x2000 + }, + { + // This is STK32F303RET6 device from STM32 F3 Nucelo board. + // Support based on DM00043574.pdf (RM0316) document rev 5. + .chip_id = STLINK_CHIPID_STM32_F303_HIGH, + .description = "F303 high density", + .flash_type = STLINK_FLASH_TYPE_F0, + .flash_size_reg = 0x1ffff7cc, // 34.2.1 Flash size data register + .flash_pagesize = 0x800, // 4.2.1 Flash memory organization + .sram_size = 0x10000, // 3.3 Embedded SRAM + .bootrom_base = 0x1fffd800, // 3.3.2 / Table 4 System Memory + .bootrom_size = 0x2000 + }, + { + // STM32L4x6 + // From RM0351. + .chip_id = STLINK_CHIPID_STM32_L4, + .description = "L4xx", + .flash_type = STLINK_FLASH_TYPE_L4, + .flash_size_reg = 0x1FFF75e0, // "Flash size data register" (sec 45.2, page 1671) + .flash_pagesize = 0x800, // 2k (sec 3.2, page 78; also appears in sec 3.3.1 + // and tables 4-6 on pages 79-81) + // SRAM1 is "up to" 96k in the standard Cortex-M memory map; + // SRAM2 is 32k mapped at at 0x10000000 (sec 2.3, page 73 for + // sizes; table 2, page 74 for SRAM2 location) + .sram_size = 0x18000, + .bootrom_base = 0x1fff0000, // Tables 4-6, pages 80-81 (Bank 1 system memory) + .bootrom_size = 0x7000, // 28k (per bank), same source as base + .option_base = STM32_L4_OPTION_BYTES_BASE, + .option_size = 4, + }, + { + // STM32L4RX + // From DM00310109.pdf + .chip_id = STLINK_CHIPID_STM32_L4RX, + .description = "L4Rx", + .flash_type = STLINK_FLASH_TYPE_L4, + .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 52.2, page 2049) + .flash_pagesize = 0x1000, // 4k, section 3.3, pg 97 + .sram_size = 0xa0000, // 192k (SRAM1) + 64k SRAM2 + 384k SRAM3 = 640k, or 0xA0000 + .bootrom_base = 0x1fff0000, // 3.3.1, pg 99 + .bootrom_size = 0x7000 // 28k (per bank), same source as base (pg 99) + }, + { + // STLINK_CHIPID_STM32_L41X + // From RM0394 Rev 4 and DS12469 Rev 5 + .chip_id = STLINK_CHIPID_STM32_L41X, + .description = "L41x", + .flash_type = STLINK_FLASH_TYPE_L4, + .flash_size_reg = 0x1fff75e0, // "Flash size data register" (RM0394, sec 47.2, page 1586) + .flash_pagesize = 0x800, // 2k (DS12469, sec 3.4, page 17) + // SRAM1 is 32k at 0x20000000 + // SRAM2 is 8k at 0x10000000 and 0x20008000 (DS12469, sec 3.5, page 18) + .sram_size = 0xa000, // 40k (DS12469, sec 3.5, page 18) + .bootrom_base = 0x1fff0000, // System Memory (RM0394, sec 3.3.1, table 8) + .bootrom_size = 0x7000 // 28k, same source as base + }, + { + // STLINK_CHIPID_STM32_L43X + // From RM0392. + .chip_id = STLINK_CHIPID_STM32_L43X, + .description = "L43x/L44x", + .flash_type = STLINK_FLASH_TYPE_L4, + .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 43.2, page 1410) + .flash_pagesize = 0x800, // 2k (sec 3.2, page 74; also appears in sec 3.3.1 + // and tables 7-8 on pages 75-76) + // SRAM1 is "up to" 64k in the standard Cortex-M memory map; + // SRAM2 is 16k mapped at 0x10000000 (sec 2.3, page 73 for + // sizes; table 2, page 74 for SRAM2 location) + .sram_size = 0xc000, + .bootrom_base = 0x1fff0000, // Tables 4-6, pages 80-81 (Bank 1 system memory) + .bootrom_size = 0x7000, // 28k (per bank), same source as base + .option_base = STM32_L4_OPTION_BYTES_BASE, + .option_size = 4, + }, + { + // STLINK_CHIPID_STM32_L496X + // Support based on en.DM00083560.pdf (RM0351) document rev 5. + .chip_id = STLINK_CHIPID_STM32_L496X, + .description = "L496x/L4A6x", + .flash_type = STLINK_FLASH_TYPE_L4, + .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 49.2, page 1809) + .flash_pagesize = 0x800, // Page erase (2 Kbyte) (sec 3.2, page 93) + // SRAM1 is 256k at 0x20000000 + // SRAM2 is 64k at 0x20040000 (sec 2.2.1, fig 2, page 74) + .sram_size = 0x40000, // Embedded SRAM (sec 2.4, page 84) + .bootrom_base = 0x1fff0000, // System Memory (Bank 1) (sec 3.3.1) + .bootrom_size = 0x7000, // 28k (per bank), same source as base + .option_base = STM32_L4_OPTION_BYTES_BASE, + .option_size = 4, + }, + { + // STLINK_CHIPID_STM32_L46X + // From RM0394 (updated version of RM0392?). + .chip_id = STLINK_CHIPID_STM32_L46X, + .description = "L45x/46x", + .flash_type = STLINK_FLASH_TYPE_L4, + .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 45.2, page 1463) + .flash_pagesize = 0x800, // 2k (sec 3.2, page 73; also appears in sec 3.3.1 + // and tables 7 on pages 73-74) + // SRAM1 is 128k at 0x20000000; + // SRAM2 is 32k mapped at 0x10000000 (sec 2.4.2, table 3-4, page 68, also fig 2 on page 63) + .sram_size = 0x20000, + .bootrom_base = 0x1fff0000, // Tables 6, pages 71-72 (Bank 1 system memory, also fig 2 on page 63) + .bootrom_size = 0x7000 // 28k (per bank), same source as base + }, + { + // STM32L011 + .chip_id = STLINK_CHIPID_STM32_L011, + .description = "L011", + .flash_type = STLINK_FLASH_TYPE_L0, + .flash_size_reg = 0x1ff8007c, + .flash_pagesize = 0x80, + .sram_size = 0x2000, + .bootrom_base = 0x1ff00000, + .bootrom_size = 0x2000 + }, + { + // STM32G030/031/041 (from RM0454 & RM0444) + .chip_id = STLINK_CHIPID_STM32_G0_CAT1, + .description = "G030/G031/G041", + .flash_type = STLINK_FLASH_TYPE_G0, + .flash_size_reg = 0x1FFF75E0, // Section 38.2 + .flash_pagesize = 0x800, // 2k (sec 3.2) + .sram_size = 0x2000, // 8k (sec 2.3) + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x2000, // 8k (sec 2.2.2 table 3) + .option_base = STM32_G0_OPTION_BYTES_BASE, + .option_size = 4, + }, + { + // STM32G071/081 (from RM0444) + .chip_id = STLINK_CHIPID_STM32_G0_CAT2, + .description = "G070/G071/G081", + .flash_type = STLINK_FLASH_TYPE_G0, + .flash_size_reg = 0x1FFF75E0, // Section 38.2 + .flash_pagesize = 0x800, // 2k (sec 3.2) + .sram_size = 0x9000, // 36k (sec 2.3) + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x7000, // 28k (sec 2.2.2 table 2) + .option_base = STM32_G0_OPTION_BYTES_BASE, + .option_size = 4, + }, + { + // STM32G431/441 (from RM0440) + .chip_id = STLINK_CHIPID_STM32_G4_CAT2, + .description = "G4 Category-2", + .flash_type = STLINK_FLASH_TYPE_G4, + .flash_size_reg = 0x1FFF75E0, // Section 47.2 + .flash_pagesize = 0x800, // 2k (sec 3.3.1) + // SRAM1 is 16k at 0x20000000 + // SRAM2 is 6k at 0x20014000 + // SRAM3/CCM is 10k at 0x10000000, aliased at 0x20018000 + .sram_size = 0x8000, // 32k (sec 2.4) + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x7000, // 28k (table 2) + .option_base = STM32_G4_OPTION_BYTES_BASE, + .option_size = 4, + }, + { + // STM32G471/473/474/483/484 (from RM0440) + .chip_id = STLINK_CHIPID_STM32_G4_CAT3, + .description = "G4 Category-3", + .flash_type = STLINK_FLASH_TYPE_G4, + .has_dual_bank = true, + .flash_size_reg = 0x1FFF75E0, // Section 47.2 + .flash_pagesize = 0x800, // 2k (sec 3.3.1) + // SRAM1 is 80k at 0x20000000 + // SRAM2 is 16k at 0x20014000 + // SRAM3/CCM is 32k at 0x10000000, aliased at 0x20018000 + .sram_size = 0x18000, // 128k (sec 2.4) + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x7000, // 28k (table 2) + .option_base = STM32_G4_OPTION_BYTES_BASE, + .option_size = 4, + }, + { + // STM32WB55 (from RM0434) + .chip_id = STLINK_CHIPID_STM32_WB55, + .description = "WB55", + .flash_type = STLINK_FLASH_TYPE_WB, + .flash_size_reg = 0x1FFF75E0, + .flash_pagesize = 0x1000, // 4k + .sram_size = 0x40000, + .bootrom_base = 0x1fff0000, // see the memory map + .bootrom_size = 0x7000 + }, + { + // unknown + .chip_id = STLINK_CHIPID_UNKNOWN, + .description = "unknown device", + .flash_type = STLINK_FLASH_TYPE_UNKNOWN, + .flash_size_reg = 0x0, + .flash_pagesize = 0x0, + .sram_size = 0x0, + .bootrom_base = 0x0, + .bootrom_size = 0x0 + }, +}; -const struct stlink_chipid_params *stlink_chipid_get_params(uint32_t chipid) -{ - const struct stlink_chipid_params *params = NULL; +const struct stlink_chipid_params *stlink_chipid_get_params(uint32_t chipid) { + const struct stlink_chipid_params *params = NULL; - for (size_t n = 0; n < STLINK_ARRAY_SIZE(devices); n++) { - if (devices[n].chip_id == chipid) { - params = &devices[n]; - break; - } - } + for (size_t n = 0; n < STLINK_ARRAY_SIZE(devices); n++) + if (devices[n].chip_id == chipid) { + params = &devices[n]; + break; + } - return params; + return(params); } diff --git a/src/stlink-lib/chipid.h b/src/stlink-lib/chipid.h index 98164a8fc..b591f0012 100644 --- a/src/stlink-lib/chipid.h +++ b/src/stlink-lib/chipid.h @@ -8,79 +8,77 @@ extern "C" { /** * Chip IDs are explained in the appropriate programming manual for the * DBGMCU_IDCODE register (0xE0042000) - * stm32 chipids, only lower 12 bits.. + * stm32 chipids, only lower 12 bits... */ enum stlink_stm32_chipids { - STLINK_CHIPID_UNKNOWN = 0x000, + STLINK_CHIPID_UNKNOWN = 0x000, - STLINK_CHIPID_STM32_F1_MEDIUM = 0x410, - STLINK_CHIPID_STM32_F2 = 0x411, - STLINK_CHIPID_STM32_F1_LOW = 0x412, - STLINK_CHIPID_STM32_F4 = 0x413, - STLINK_CHIPID_STM32_F1_HIGH = 0x414, - STLINK_CHIPID_STM32_L4 = 0x415, - STLINK_CHIPID_STM32_L1_MEDIUM = 0x416, - STLINK_CHIPID_STM32_L0 = 0x417, - STLINK_CHIPID_STM32_F1_CONN = 0x418, - STLINK_CHIPID_STM32_F4_HD = 0x419, - STLINK_CHIPID_STM32_F1_VL_MEDIUM_LOW = 0x420, - STLINK_CHIPID_STM32_F446 = 0x421, - STLINK_CHIPID_STM32_F3 = 0x422, - STLINK_CHIPID_STM32_F4_LP = 0x423, - STLINK_CHIPID_STM32_L0_CAT2 = 0x425, - STLINK_CHIPID_STM32_L1_MEDIUM_PLUS = 0x427, /* assigned to some L1 "Medium-plus" chips */ - STLINK_CHIPID_STM32_F1_VL_HIGH = 0x428, - STLINK_CHIPID_STM32_L1_CAT2 = 0x429, - STLINK_CHIPID_STM32_F1_XL = 0x430, - STLINK_CHIPID_STM32_F411RE = 0x431, - STLINK_CHIPID_STM32_F37x = 0x432, - STLINK_CHIPID_STM32_F4_DE = 0x433, - STLINK_CHIPID_STM32_F4_DSI = 0x434, - STLINK_CHIPID_STM32_L43X = 0x435, /* covers STM32L43xxx and STM32L44xxx devices */ - STLINK_CHIPID_STM32_L496X = 0x461, /* covers STM32L496xx and STM32L4A6xx devices */ - STLINK_CHIPID_STM32_L46X = 0x462, /* covers STM32L45xxx and STM32L46xxx devices */ - STLINK_CHIPID_STM32_L41X = 0x464, /* covers STM32L41xxx and STM32L42xxx devices */ - STLINK_CHIPID_STM32_L1_HIGH = 0x436, /* assigned to some L1 chips called "Medium-Plus" and to some called "High" */ - STLINK_CHIPID_STM32_L152_RE = 0x437, - STLINK_CHIPID_STM32_F334 = 0x438, - STLINK_CHIPID_STM32_F3_SMALL = 0x439, - STLINK_CHIPID_STM32_F0 = 0x440, - STLINK_CHIPID_STM32_F412 = 0x441, - STLINK_CHIPID_STM32_F09X = 0x442, - STLINK_CHIPID_STM32_F0_SMALL = 0x444, - STLINK_CHIPID_STM32_F04 = 0x445, - STLINK_CHIPID_STM32_F303_HIGH = 0x446, - STLINK_CHIPID_STM32_L0_CAT5 = 0x447, - STLINK_CHIPID_STM32_F0_CAN = 0x448, - STLINK_CHIPID_STM32_F7 = 0x449, /* This ID is found on the NucleoF746ZG board */ - STLINK_CHIPID_STM32_F7XXXX = 0x451, - STLINK_CHIPID_STM32_F72XXX = 0x452, /* This ID is found on the NucleoF722ZE board */ - STLINK_CHIPID_STM32_L011 = 0x457, - STLINK_CHIPID_STM32_F410 = 0x458, - STLINK_CHIPID_STM32_G0_CAT2 = 0x460, /* G070/G071/081 */ - STLINK_CHIPID_STM32_F413 = 0x463, - STLINK_CHIPID_STM32_G0_CAT1 = 0x466, /* G030/G031/041 */ - STLINK_CHIPID_STM32_G4_CAT2 = 0x468, /* See: RM 0440 s46.6.1 "MCU device ID code" */ - STLINK_CHIPID_STM32_G4_CAT3 = 0x469, - STLINK_CHIPID_STM32_L4RX = 0x470, /* taken from the STM32L4R9I-DISCO board */ - STLINK_CHIPID_STM32_WB55 = 0x495 + STLINK_CHIPID_STM32_F1_MEDIUM = 0x410, + STLINK_CHIPID_STM32_F2 = 0x411, + STLINK_CHIPID_STM32_F1_LOW = 0x412, + STLINK_CHIPID_STM32_F4 = 0x413, + STLINK_CHIPID_STM32_F1_HIGH = 0x414, + STLINK_CHIPID_STM32_L4 = 0x415, + STLINK_CHIPID_STM32_L1_MEDIUM = 0x416, + STLINK_CHIPID_STM32_L0 = 0x417, + STLINK_CHIPID_STM32_F1_CONN = 0x418, + STLINK_CHIPID_STM32_F4_HD = 0x419, + STLINK_CHIPID_STM32_F1_VL_MEDIUM_LOW = 0x420, + STLINK_CHIPID_STM32_F446 = 0x421, + STLINK_CHIPID_STM32_F3 = 0x422, + STLINK_CHIPID_STM32_F4_LP = 0x423, + STLINK_CHIPID_STM32_L0_CAT2 = 0x425, + STLINK_CHIPID_STM32_L1_MEDIUM_PLUS = 0x427, /* assigned to some L1 "Medium-plus" chips */ + STLINK_CHIPID_STM32_F1_VL_HIGH = 0x428, + STLINK_CHIPID_STM32_L1_CAT2 = 0x429, + STLINK_CHIPID_STM32_F1_XL = 0x430, + STLINK_CHIPID_STM32_F411RE = 0x431, + STLINK_CHIPID_STM32_F37x = 0x432, + STLINK_CHIPID_STM32_F4_DE = 0x433, + STLINK_CHIPID_STM32_F4_DSI = 0x434, + STLINK_CHIPID_STM32_L43X = 0x435, /* covers STM32L43xxx and STM32L44xxx devices */ + STLINK_CHIPID_STM32_L496X = 0x461, /* covers STM32L496xx and STM32L4A6xx devices */ + STLINK_CHIPID_STM32_L46X = 0x462, /* covers STM32L45xxx and STM32L46xxx devices */ + STLINK_CHIPID_STM32_L41X = 0x464, /* covers STM32L41xxx and STM32L42xxx devices */ + STLINK_CHIPID_STM32_L1_HIGH = 0x436, /* assigned to some L1 "Medium-Plus" and "High" chips */ + STLINK_CHIPID_STM32_L152_RE = 0x437, + STLINK_CHIPID_STM32_F334 = 0x438, + STLINK_CHIPID_STM32_F3_SMALL = 0x439, + STLINK_CHIPID_STM32_F0 = 0x440, + STLINK_CHIPID_STM32_F412 = 0x441, + STLINK_CHIPID_STM32_F09X = 0x442, + STLINK_CHIPID_STM32_F0_SMALL = 0x444, + STLINK_CHIPID_STM32_F04 = 0x445, + STLINK_CHIPID_STM32_F303_HIGH = 0x446, + STLINK_CHIPID_STM32_L0_CAT5 = 0x447, + STLINK_CHIPID_STM32_F0_CAN = 0x448, + STLINK_CHIPID_STM32_F7 = 0x449, /* ID found on the NucleoF746ZG board */ + STLINK_CHIPID_STM32_F7XXXX = 0x451, + STLINK_CHIPID_STM32_F72XXX = 0x452, /* ID found on the NucleoF722ZE board */ + STLINK_CHIPID_STM32_L011 = 0x457, + STLINK_CHIPID_STM32_F410 = 0x458, + STLINK_CHIPID_STM32_G0_CAT2 = 0x460, /* G070/G071/081 */ + STLINK_CHIPID_STM32_F413 = 0x463, + STLINK_CHIPID_STM32_G0_CAT1 = 0x466, /* G030/G031/041 */ + STLINK_CHIPID_STM32_G4_CAT2 = 0x468, /* See: RM 0440 s46.6.1 "MCU device ID code" */ + STLINK_CHIPID_STM32_G4_CAT3 = 0x469, + STLINK_CHIPID_STM32_L4RX = 0x470, /* ID found on the STM32L4R9I-DISCO board */ + STLINK_CHIPID_STM32_WB55 = 0x495 }; -/** - * Chipid parameters - */ +/** Chipid parameters */ struct stlink_chipid_params { - uint32_t chip_id; - char *description; - enum stlink_flash_type flash_type; - bool has_dual_bank; - uint32_t flash_size_reg; - uint32_t flash_pagesize; - uint32_t sram_size; - uint32_t bootrom_base; - uint32_t bootrom_size; - uint32_t option_base; - uint32_t option_size; + uint32_t chip_id; + char *description; + enum stlink_flash_type flash_type; + bool has_dual_bank; + uint32_t flash_size_reg; + uint32_t flash_pagesize; + uint32_t sram_size; + uint32_t bootrom_base; + uint32_t bootrom_size; + uint32_t option_base; + uint32_t option_size; }; const struct stlink_chipid_params *stlink_chipid_get_params(uint32_t chipid); @@ -89,4 +87,4 @@ const struct stlink_chipid_params *stlink_chipid_get_params(uint32_t chipid); } #endif -#endif /* STLINK_CHIPID_H_ */ +#endif // STLINK_CHIPID_H_ diff --git a/src/commands.h b/src/stlink-lib/commands.h similarity index 97% rename from src/commands.h rename to src/stlink-lib/commands.h index a6830ff26..0925e8e67 100644 --- a/src/commands.h +++ b/src/stlink-lib/commands.h @@ -33,4 +33,4 @@ enum stlink_debug_commands { STLINK_DEBUG_ENTER_SWD = 0xa3 }; -#endif /* STLINK_COMMANDS_H_ */ +#endif // STLINK_COMMANDS_H_ diff --git a/src/stlink-lib/flash_loader.c b/src/stlink-lib/flash_loader.c index b97a6edaa..71601e3da 100644 --- a/src/stlink-lib/flash_loader.c +++ b/src/stlink-lib/flash_loader.c @@ -10,207 +10,203 @@ /* DO NOT MODIFY SOURCECODE DIRECTLY, EDIT ASSEMBLY FILES INSTEAD */ - /* flashloaders/stm32f0.s -- compiled with thumb2 */ - static const uint8_t loader_code_stm32vl[] = { - 0x16, 0x4f, 0x3c, 0x68, - 0x16, 0x4f, 0x3e, 0x68, - 0x36, 0x19, 0x16, 0x4f, - 0x3d, 0x68, 0x2d, 0x19, - 0x4f, 0xf0, 0x01, 0x07, - 0x33, 0x68, 0x3b, 0x43, - 0x33, 0x60, 0x03, 0x88, - 0x0b, 0x80, 0x4f, 0xf0, - 0x02, 0x07, 0xc0, 0x19, - 0xc9, 0x19, 0x4f, 0xf0, - 0x01, 0x07, 0x2b, 0x68, - 0x3b, 0x42, 0xfa, 0xd0, - 0x4f, 0xf0, 0x04, 0x07, - 0x3b, 0x42, 0x04, 0xd1, - 0x4f, 0xf0, 0x01, 0x07, - 0xd2, 0x1b, 0x00, 0x2a, - 0xe6, 0xd1, 0x4f, 0xf0, - 0x01, 0x07, 0x33, 0x68, - 0xbb, 0x43, 0x33, 0x60, - 0x00, 0xbe, 0x00, 0xbf, - 0x00, 0x20, 0x02, 0x40, - 0x10, 0x00, 0x00, 0x00, - 0x0c, 0x00, 0x00, 0x00, - 0x50, 0x00, 0x00, 0x20, - 0x54, 0x00, 0x00, 0x20, - 0x58, 0x00, 0x00, 0x20 - }; - - /* flashloaders/stm32f0.s -- thumb1 only, same sequence as for STM32VL, bank ignored */ - static const uint8_t loader_code_stm32f0[] = { - 0xc0, 0x46, 0xc0, 0x46, - 0x13, 0x4f, 0x3c, 0x68, - 0x13, 0x4f, 0x3e, 0x68, - 0x36, 0x19, 0x13, 0x4f, - 0x3d, 0x68, 0x2d, 0x19, - 0x12, 0x4f, 0x33, 0x68, - 0x3b, 0x43, 0x33, 0x60, - 0x03, 0x88, 0x0b, 0x80, - 0x10, 0x4f, 0xc0, 0x19, - 0xc9, 0x19, 0x0e, 0x4f, - 0x2b, 0x68, 0x3b, 0x42, - 0xfb, 0xd0, 0x0e, 0x4f, - 0x3b, 0x42, 0x03, 0xd1, - 0x0a, 0x4f, 0xd2, 0x1b, - 0x00, 0x2a, 0xeb, 0xd1, - 0x08, 0x4f, 0x33, 0x68, - 0xbb, 0x43, 0x33, 0x60, - 0x00, 0xbe, 0xc0, 0x46, - 0x00, 0x20, 0x02, 0x40, - 0x10, 0x00, 0x00, 0x00, - 0x0c, 0x00, 0x00, 0x00, - 0x48, 0x00, 0x00, 0x20, - 0x4c, 0x00, 0x00, 0x20, - 0x50, 0x00, 0x00, 0x20, - 0x01, 0x00, 0x00, 0x00, - 0x02, 0x00, 0x00, 0x00, - 0x04, 0x00, 0x00, 0x00 - }; - - static const uint8_t loader_code_stm32l[] = { - // flashloaders/stm32lx.s - - 0x03, 0x68, 0x0b, 0x60, - 0x4f, 0xf0, 0x04, 0x07, - 0x38, 0x44, 0x39, 0x44, - 0x4f, 0xf0, 0x01, 0x07, - 0xd2, 0x1b, 0x00, 0x2a, - 0xf4, 0xd1, 0x00, 0xbe, - }; - - static const uint8_t loader_code_stm32f4[] = { - // flashloaders/stm32f4.s - - 0xdf, 0xf8, 0x28, 0xc0, - 0xdf, 0xf8, 0x28, 0xa0, - 0xe2, 0x44, 0x03, 0x68, - 0x0b, 0x60, 0x00, 0xf1, - 0x04, 0x00, 0x01, 0xf1, - 0x04, 0x01, 0xba, 0xf8, - 0x00, 0x30, 0x13, 0xf0, - 0x01, 0x0f, 0xfa, 0xd0, - 0xa2, 0xf1, 0x01, 0x02, - 0x00, 0x2a, 0xf0, 0xd1, - 0x00, 0xbe, 0x00, 0xbf, - 0x00, 0x3c, 0x02, 0x40, - 0x0e, 0x00, 0x00, 0x00 - }; - - static const uint8_t loader_code_stm32f4_lv[] = { - // flashloaders/stm32f4lv.s - 0xdf, 0xf8, 0x2c, 0xc0, - 0xdf, 0xf8, 0x2c, 0xa0, - 0xe2, 0x44, 0x4f, 0xea, - 0x82, 0x02, 0x03, 0x78, - 0x0b, 0x70, 0x00, 0xf1, - 0x01, 0x00, 0x01, 0xf1, - 0x01, 0x01, 0xba, 0xf8, - 0x00, 0x30, 0x13, 0xf0, - 0x01, 0x0f, 0xfa, 0xd0, - 0xa2, 0xf1, 0x01, 0x02, - 0x00, 0x2a, 0xf0, 0xd1, - 0x00, 0xbe, 0x00, 0xbf, - 0x00, 0x3c, 0x02, 0x40, - 0x0e, 0x00, 0x00, 0x00 - }; - - static const uint8_t loader_code_stm32l4[] = { - // flashloaders/stm32l4.s - 0xdf, 0xf8, 0x2c, 0xc0, - 0xdf, 0xf8, 0x2c, 0xa0, - 0xe2, 0x44, 0x03, 0x68, - 0x44, 0x68, 0x0b, 0x60, - 0x4c, 0x60, 0x00, 0xf1, - 0x08, 0x00, 0x01, 0xf1, - 0x08, 0x01, 0xba, 0xf8, - 0x00, 0x30, 0x13, 0xf0, - 0x01, 0x0f, 0xfa, 0xd0, - 0xa2, 0xf1, 0x01, 0x02, - 0x00, 0x2a, 0xee, 0xd1, - 0x00, 0xbe, 0x00, 0xbf, - 0x00, 0x20, 0x02, 0x40, - 0x12, 0x00, 0x00, 0x00 - }; - - static const uint8_t loader_code_stm32f7[] = { - // flashloaders/stm32f7.s - 0xdf, 0xf8, 0x2c, 0xc0, - 0xdf, 0xf8, 0x2c, 0xa0, - 0xe2, 0x44, 0x03, 0x68, - 0x0b, 0x60, 0x00, 0xf1, - 0x04, 0x00, 0x01, 0xf1, - 0x04, 0x01, 0xbf, 0xf3, - 0x4f, 0x8f, 0xba, 0xf8, - 0x00, 0x30, 0x13, 0xf0, - 0x01, 0x0f, 0xfa, 0xd0, - 0xa2, 0xf1, 0x01, 0x02, - 0x00, 0x2a, 0xee, 0xd1, - 0x00, 0xbe, 0x00, 0xbf, - 0x00, 0x3c, 0x02, 0x40, - 0x0e, 0x00, 0x00, 0x00 - }; - - static const uint8_t loader_code_stm32f7_lv[] = { - // flashloaders/stm32f7lv.s - 0xdf, 0xf8, 0x30, 0xc0, - 0xdf, 0xf8, 0x30, 0xa0, - 0xe2, 0x44, 0x4f, 0xea, - 0x82, 0x02, 0x03, 0x78, - 0x0b, 0x70, 0x00, 0xf1, - 0x01, 0x00, 0x01, 0xf1, - 0x01, 0x01, 0xbf, 0xf3, - 0x4f, 0x8f, 0xba, 0xf8, - 0x00, 0x30, 0x13, 0xf0, - 0x01, 0x0f, 0xfa, 0xd0, - 0xa2, 0xf1, 0x01, 0x02, - 0x00, 0x2a, 0xee, 0xd1, - 0x00, 0xbe, 0x00, 0xbf, - 0x00, 0x3c, 0x02, 0x40, - 0x0e, 0x00, 0x00, 0x00 - }; - - - -int stlink_flash_loader_init(stlink_t *sl, flash_loader_t *fl) -{ - size_t size = 0; - - /* allocate the loader in sram */ - if (stlink_flash_loader_write_to_sram(sl, &fl->loader_addr, &size) == -1) { - WLOG("Failed to write flash loader to sram!\n"); - return -1; - } - - /* allocate a one page buffer in sram right after loader */ - fl->buf_addr = fl->loader_addr + (uint32_t) size; - ILOG("Successfully loaded flash loader in sram\n"); - - return 0; +/* flashloaders/stm32f0.s -- compiled with thumb2 */ +static const uint8_t loader_code_stm32vl[] = { + 0x16, 0x4f, 0x3c, 0x68, + 0x16, 0x4f, 0x3e, 0x68, + 0x36, 0x19, 0x16, 0x4f, + 0x3d, 0x68, 0x2d, 0x19, + 0x4f, 0xf0, 0x01, 0x07, + 0x33, 0x68, 0x3b, 0x43, + 0x33, 0x60, 0x03, 0x88, + 0x0b, 0x80, 0x4f, 0xf0, + 0x02, 0x07, 0xc0, 0x19, + 0xc9, 0x19, 0x4f, 0xf0, + 0x01, 0x07, 0x2b, 0x68, + 0x3b, 0x42, 0xfa, 0xd0, + 0x4f, 0xf0, 0x04, 0x07, + 0x3b, 0x42, 0x04, 0xd1, + 0x4f, 0xf0, 0x01, 0x07, + 0xd2, 0x1b, 0x00, 0x2a, + 0xe6, 0xd1, 0x4f, 0xf0, + 0x01, 0x07, 0x33, 0x68, + 0xbb, 0x43, 0x33, 0x60, + 0x00, 0xbe, 0x00, 0xbf, + 0x00, 0x20, 0x02, 0x40, + 0x10, 0x00, 0x00, 0x00, + 0x0c, 0x00, 0x00, 0x00, + 0x50, 0x00, 0x00, 0x20, + 0x54, 0x00, 0x00, 0x20, + 0x58, 0x00, 0x00, 0x20 +}; + +/* flashloaders/stm32f0.s -- thumb1 only, same sequence as for STM32VL, bank ignored */ +static const uint8_t loader_code_stm32f0[] = { + 0xc0, 0x46, 0xc0, 0x46, + 0x13, 0x4f, 0x3c, 0x68, + 0x13, 0x4f, 0x3e, 0x68, + 0x36, 0x19, 0x13, 0x4f, + 0x3d, 0x68, 0x2d, 0x19, + 0x12, 0x4f, 0x33, 0x68, + 0x3b, 0x43, 0x33, 0x60, + 0x03, 0x88, 0x0b, 0x80, + 0x10, 0x4f, 0xc0, 0x19, + 0xc9, 0x19, 0x0e, 0x4f, + 0x2b, 0x68, 0x3b, 0x42, + 0xfb, 0xd0, 0x0e, 0x4f, + 0x3b, 0x42, 0x03, 0xd1, + 0x0a, 0x4f, 0xd2, 0x1b, + 0x00, 0x2a, 0xeb, 0xd1, + 0x08, 0x4f, 0x33, 0x68, + 0xbb, 0x43, 0x33, 0x60, + 0x00, 0xbe, 0xc0, 0x46, + 0x00, 0x20, 0x02, 0x40, + 0x10, 0x00, 0x00, 0x00, + 0x0c, 0x00, 0x00, 0x00, + 0x48, 0x00, 0x00, 0x20, + 0x4c, 0x00, 0x00, 0x20, + 0x50, 0x00, 0x00, 0x20, + 0x01, 0x00, 0x00, 0x00, + 0x02, 0x00, 0x00, 0x00, + 0x04, 0x00, 0x00, 0x00 +}; + +static const uint8_t loader_code_stm32l[] = { + // flashloaders/stm32lx.s + + 0x03, 0x68, 0x0b, 0x60, + 0x4f, 0xf0, 0x04, 0x07, + 0x38, 0x44, 0x39, 0x44, + 0x4f, 0xf0, 0x01, 0x07, + 0xd2, 0x1b, 0x00, 0x2a, + 0xf4, 0xd1, 0x00, 0xbe, +}; + +static const uint8_t loader_code_stm32f4[] = { + // flashloaders/stm32f4.s + + 0xdf, 0xf8, 0x28, 0xc0, + 0xdf, 0xf8, 0x28, 0xa0, + 0xe2, 0x44, 0x03, 0x68, + 0x0b, 0x60, 0x00, 0xf1, + 0x04, 0x00, 0x01, 0xf1, + 0x04, 0x01, 0xba, 0xf8, + 0x00, 0x30, 0x13, 0xf0, + 0x01, 0x0f, 0xfa, 0xd0, + 0xa2, 0xf1, 0x01, 0x02, + 0x00, 0x2a, 0xf0, 0xd1, + 0x00, 0xbe, 0x00, 0xbf, + 0x00, 0x3c, 0x02, 0x40, + 0x0e, 0x00, 0x00, 0x00 +}; + +static const uint8_t loader_code_stm32f4_lv[] = { + // flashloaders/stm32f4lv.s + 0xdf, 0xf8, 0x2c, 0xc0, + 0xdf, 0xf8, 0x2c, 0xa0, + 0xe2, 0x44, 0x4f, 0xea, + 0x82, 0x02, 0x03, 0x78, + 0x0b, 0x70, 0x00, 0xf1, + 0x01, 0x00, 0x01, 0xf1, + 0x01, 0x01, 0xba, 0xf8, + 0x00, 0x30, 0x13, 0xf0, + 0x01, 0x0f, 0xfa, 0xd0, + 0xa2, 0xf1, 0x01, 0x02, + 0x00, 0x2a, 0xf0, 0xd1, + 0x00, 0xbe, 0x00, 0xbf, + 0x00, 0x3c, 0x02, 0x40, + 0x0e, 0x00, 0x00, 0x00 +}; + +static const uint8_t loader_code_stm32l4[] = { + // flashloaders/stm32l4.s + 0xdf, 0xf8, 0x2c, 0xc0, + 0xdf, 0xf8, 0x2c, 0xa0, + 0xe2, 0x44, 0x03, 0x68, + 0x44, 0x68, 0x0b, 0x60, + 0x4c, 0x60, 0x00, 0xf1, + 0x08, 0x00, 0x01, 0xf1, + 0x08, 0x01, 0xba, 0xf8, + 0x00, 0x30, 0x13, 0xf0, + 0x01, 0x0f, 0xfa, 0xd0, + 0xa2, 0xf1, 0x01, 0x02, + 0x00, 0x2a, 0xee, 0xd1, + 0x00, 0xbe, 0x00, 0xbf, + 0x00, 0x20, 0x02, 0x40, + 0x12, 0x00, 0x00, 0x00 +}; + +static const uint8_t loader_code_stm32f7[] = { + // flashloaders/stm32f7.s + 0xdf, 0xf8, 0x2c, 0xc0, + 0xdf, 0xf8, 0x2c, 0xa0, + 0xe2, 0x44, 0x03, 0x68, + 0x0b, 0x60, 0x00, 0xf1, + 0x04, 0x00, 0x01, 0xf1, + 0x04, 0x01, 0xbf, 0xf3, + 0x4f, 0x8f, 0xba, 0xf8, + 0x00, 0x30, 0x13, 0xf0, + 0x01, 0x0f, 0xfa, 0xd0, + 0xa2, 0xf1, 0x01, 0x02, + 0x00, 0x2a, 0xee, 0xd1, + 0x00, 0xbe, 0x00, 0xbf, + 0x00, 0x3c, 0x02, 0x40, + 0x0e, 0x00, 0x00, 0x00 +}; + +static const uint8_t loader_code_stm32f7_lv[] = { + // flashloaders/stm32f7lv.s + 0xdf, 0xf8, 0x30, 0xc0, + 0xdf, 0xf8, 0x30, 0xa0, + 0xe2, 0x44, 0x4f, 0xea, + 0x82, 0x02, 0x03, 0x78, + 0x0b, 0x70, 0x00, 0xf1, + 0x01, 0x00, 0x01, 0xf1, + 0x01, 0x01, 0xbf, 0xf3, + 0x4f, 0x8f, 0xba, 0xf8, + 0x00, 0x30, 0x13, 0xf0, + 0x01, 0x0f, 0xfa, 0xd0, + 0xa2, 0xf1, 0x01, 0x02, + 0x00, 0x2a, 0xee, 0xd1, + 0x00, 0xbe, 0x00, 0xbf, + 0x00, 0x3c, 0x02, 0x40, + 0x0e, 0x00, 0x00, 0x00 +}; + + +int stlink_flash_loader_init(stlink_t *sl, flash_loader_t *fl) { + size_t size = 0; + + // allocate the loader in SRAM + if (stlink_flash_loader_write_to_sram(sl, &fl->loader_addr, &size) == -1) { + WLOG("Failed to write flash loader to sram!\n"); + return(-1); + } + + // allocate a one page buffer in SRAM right after loader + fl->buf_addr = fl->loader_addr + (uint32_t)size; + ILOG("Successfully loaded flash loader in sram\n"); + + return(0); } static int loader_v_dependent_assignment(stlink_t *sl, const uint8_t **loader_code, size_t *loader_size, const uint8_t *high_v_loader, size_t high_v_loader_size, - const uint8_t *low_v_loader, size_t low_v_loader_size) -{ + const uint8_t *low_v_loader, size_t low_v_loader_size) { int retval = 0; - if ( sl->version.stlink_v == 1){ + if ( sl->version.stlink_v == 1) { printf("STLINK V1 cannot read voltage, defaulting to 32-bit writes\n"); *loader_code = high_v_loader; *loader_size = high_v_loader_size; - } - else { + } else { int voltage = stlink_target_voltage(sl); + if (voltage == -1) { retval = -1; printf("Failed to read Target voltage\n"); - } - else { + } else { if (voltage > 2700) { *loader_code = high_v_loader; *loader_size = high_v_loader_size; @@ -220,11 +216,11 @@ static int loader_v_dependent_assignment(stlink_t *sl, } } } - return retval; + + return(retval); } -int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) -{ +int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) { const uint8_t* loader_code; size_t loader_size; @@ -236,7 +232,7 @@ int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* sl->chip_id == STLINK_CHIPID_STM32_L011 || sl->chip_id == STLINK_CHIPID_STM32_L0 || sl->chip_id == STLINK_CHIPID_STM32_L0_CAT5 || - sl->chip_id == STLINK_CHIPID_STM32_L0_CAT2) { /* stm32l */ + sl->chip_id == STLINK_CHIPID_STM32_L0_CAT2) { // STM32l loader_code = loader_code_stm32l; loader_size = sizeof(loader_code_stm32l); } else if (sl->core_id == STM32VL_CORE_ID || @@ -249,38 +245,34 @@ int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* loader_code = loader_code_stm32vl; loader_size = sizeof(loader_code_stm32vl); } else if (sl->chip_id == STLINK_CHIPID_STM32_F2 || - sl->chip_id == STLINK_CHIPID_STM32_F4 || - sl->chip_id == STLINK_CHIPID_STM32_F4_DE || - sl->chip_id == STLINK_CHIPID_STM32_F4_LP || - sl->chip_id == STLINK_CHIPID_STM32_F4_HD || - sl->chip_id == STLINK_CHIPID_STM32_F4_DSI || - sl->chip_id == STLINK_CHIPID_STM32_F410 || - sl->chip_id == STLINK_CHIPID_STM32_F411RE || - sl->chip_id == STLINK_CHIPID_STM32_F412 || - sl->chip_id == STLINK_CHIPID_STM32_F413 || - sl->chip_id == STLINK_CHIPID_STM32_F446 - ) { + sl->chip_id == STLINK_CHIPID_STM32_F4 || + sl->chip_id == STLINK_CHIPID_STM32_F4_DE || + sl->chip_id == STLINK_CHIPID_STM32_F4_LP || + sl->chip_id == STLINK_CHIPID_STM32_F4_HD || + sl->chip_id == STLINK_CHIPID_STM32_F4_DSI || + sl->chip_id == STLINK_CHIPID_STM32_F410 || + sl->chip_id == STLINK_CHIPID_STM32_F411RE || + sl->chip_id == STLINK_CHIPID_STM32_F412 || + sl->chip_id == STLINK_CHIPID_STM32_F413 || + sl->chip_id == STLINK_CHIPID_STM32_F446) { int retval; retval = loader_v_dependent_assignment(sl, &loader_code, &loader_size, loader_code_stm32f4, sizeof(loader_code_stm32f4), loader_code_stm32f4_lv, sizeof(loader_code_stm32f4_lv)); - if (retval == -1) { - return retval; - } + + if (retval == -1) { return(retval); } } else if (sl->core_id == STM32F7_CORE_ID || sl->chip_id == STLINK_CHIPID_STM32_F7 || sl->chip_id == STLINK_CHIPID_STM32_F7XXXX || - sl->chip_id == STLINK_CHIPID_STM32_F72XXX - ) { + sl->chip_id == STLINK_CHIPID_STM32_F72XXX) { int retval; retval = loader_v_dependent_assignment(sl, &loader_code, &loader_size, loader_code_stm32f7, sizeof(loader_code_stm32f7), loader_code_stm32f7_lv, sizeof(loader_code_stm32f7_lv)); - if (retval == -1) { - return retval; - } + + if (retval == -1) { return(retval); } } else if (sl->chip_id == STLINK_CHIPID_STM32_F0 || sl->chip_id == STLINK_CHIPID_STM32_F04 || sl->chip_id == STLINK_CHIPID_STM32_F0_CAN || @@ -293,101 +285,102 @@ int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* (sl->chip_id == STLINK_CHIPID_STM32_L43X) || (sl->chip_id == STLINK_CHIPID_STM32_L46X) || (sl->chip_id == STLINK_CHIPID_STM32_L4RX) || - (sl->chip_id == STLINK_CHIPID_STM32_L496X)) - { + (sl->chip_id == STLINK_CHIPID_STM32_L496X)) { loader_code = loader_code_stm32l4; loader_size = sizeof(loader_code_stm32l4); } else { - ELOG("unknown coreid, not sure what flash loader to use, aborting! coreid: %x, chipid: %x\n", sl->core_id, sl->chip_id); - return -1; + ELOG("unknown coreid, not sure what flash loader to use, aborting! coreid: %x, chipid: %x\n", + sl->core_id, sl->chip_id); + return(-1); } memcpy(sl->q_buf, loader_code, loader_size); int ret = stlink_write_mem32(sl, sl->sram_base, loader_size); - if (ret) - return ret; + + if (ret) { return(ret); } *addr = sl->sram_base; *size = loader_size; - /* success */ - return 0; + return(0); // success } -int stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, const uint8_t* buf, size_t size) -{ +int stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, const uint8_t* buf, size_t size) { struct stlink_reg rr; int i = 0; size_t count = 0; uint32_t flash_base = 0; DLOG("Running flash loader, write address:%#x, size: %u\n", target, (unsigned int)size); - // FIXME This can never return -1 + + // TODO: This can never return -1 if (write_buffer_to_sram(sl, fl, buf, size) == -1) { // IMPOSSIBLE! ELOG("write_buffer_to_sram() == -1\n"); - return -1; + return(-1); } if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || (sl->flash_type == STLINK_FLASH_TYPE_F1_XL)) { count = size / sizeof(uint16_t); - if (size % sizeof(uint16_t)) - ++count; + + if (size % sizeof(uint16_t)) { ++count; } } else if (sl->flash_type == STLINK_FLASH_TYPE_F4 || sl->flash_type == STLINK_FLASH_TYPE_L0) { count = size / sizeof(uint32_t); - if (size % sizeof(uint32_t)) - ++count; + + if (size % sizeof(uint32_t)) { ++count; } } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { count = size / sizeof(uint64_t); - if (size % sizeof(uint64_t)) - ++count; + + if (size % sizeof(uint64_t)) { ++count; } } if ((sl->flash_type == STLINK_FLASH_TYPE_F1_XL) && (target >= FLASH_BANK2_START_ADDR)) { flash_base = FLASH_REGS_BANK2_OFS; } - /* setup core */ - stlink_write_reg(sl, fl->buf_addr, 0); /* source */ - stlink_write_reg(sl, target, 1); /* target */ - stlink_write_reg(sl, (uint32_t) count, 2); /* count */ - stlink_write_reg(sl, flash_base, 3); /* flash register base, only used on VL/F1_XL, but harmless for others */ - stlink_write_reg(sl, fl->loader_addr, 15); /* pc register */ + /* Setup core */ + stlink_write_reg(sl, fl->buf_addr, 0); // source + stlink_write_reg(sl, target, 1); // target + stlink_write_reg(sl, (uint32_t)count, 2); // count + stlink_write_reg(sl, flash_base, 3); // flash register base + // only used on VL/F1_XL, but harmless for others + stlink_write_reg(sl, fl->loader_addr, 15); // pc register - /* run loader */ + /* Run loader */ stlink_run(sl); -// This piece of code used to try to spin for .1 second by waiting -// doing 10000 rounds of 10 microseconds. But because this usually runs -// on Unix-like OSes, the 10 microseconds get rounded up to the "tick" -// (actually almost two ticks) of the system. 1 milisecond. Thus, the -// ten thousand attempts, when "something goes wrong" that requires -// the error message "flash loader run error" would wait for something -// like 20 seconds before coming up with the error. -// by increasing the sleep-per-round to the same order-of-magnitude as -// the tick-rounding that the OS uses, the wait until the error message is -// reduced to the same order of magnitude as what was intended. -- REW. +/* This piece of code used to try to spin for .1 second by waiting doing 10000 rounds of 10 µs. + * But because this usually runs on Unix-like OSes, the 10 µs get rounded up to the "tick" + * (actually almost two ticks) of the system. 1 ms. Thus, the ten thousand attempts, when + * "something goes wrong" that requires the error message "flash loader run error" would wait + * for something like 20 seconds before coming up with the error. + * By increasing the sleep-per-round to the same order-of-magnitude as the tick-rounding that + * the OS uses, the wait until the error message is reduced to the same order of magnitude + * as what was intended. -- REW. + */ #define WAIT_ROUNDS 100 - /* wait until done (reaches breakpoint) */ + + // wait until done (reaches breakpoint) for (i = 0; i < WAIT_ROUNDS; i++) { usleep(1000); - if (stlink_is_core_halted(sl)) - break; + + if (stlink_is_core_halted(sl)) { break; } } if (i >= WAIT_ROUNDS) { ELOG("flash loader run error\n"); - return -1; + return(-1); } - /* check written byte count */ + // check written byte count stlink_read_reg(sl, 2, &rr); + if (rr.r[2] != 0) { ELOG("write error, count == %u\n", rr.r[2]); - return -1; + return(-1); } - return 0; + return(0); } diff --git a/src/stlink-lib/flash_loader.h b/src/stlink-lib/flash_loader.h index 5f4526114..29fd5b068 100644 --- a/src/stlink-lib/flash_loader.h +++ b/src/stlink-lib/flash_loader.h @@ -1,8 +1,8 @@ /* - * File: stlink.h + * File: stlink.h * - * This should contain all the common top level stlink interfaces, regardless - * of how the backend does the work.... + * This should contain all the common top level stlink interfaces, + * regardless of how the backend does the work.... */ #ifndef STLINK_FLASH_LOADER_H_ #define STLINK_FLASH_LOADER_H_ @@ -24,4 +24,4 @@ int stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t targe } #endif -#endif /* STLINK_FLASH_LOADER_H_ */ +#endif // STLINK_FLASH_LOADER_H_ diff --git a/src/libusb_settings.h b/src/stlink-lib/libusb_settings.h similarity index 53% rename from src/libusb_settings.h rename to src/stlink-lib/libusb_settings.h index c2e2df923..046c0b33d 100644 --- a/src/libusb_settings.h +++ b/src/stlink-lib/libusb_settings.h @@ -5,24 +5,24 @@ /* - libusb ver | LIBUSB_API_VERSION --------------+-------------------- - v1.0.13 | 0x01000100 - v1.0.14 | 0x010000FF - v1.0.15 | 0x01000101 - v1.0.16 | 0x01000102 - v1.0.17 | 0x01000102 - v1.0.18 | 0x01000102 - v1.0.19 | 0x01000103 - v1.0.20 | 0x01000104 - v1.0.21 | 0x01000105 - v1.0.22 | 0x01000106 - v1.0.23 | 0x01000107 - -*/ + libusb ver | LIBUSB_API_VERSION + -----------+-------------------- + v1.0.13 | 0x01000100 + v1.0.14 | 0x010000FF + v1.0.15 | 0x01000101 + v1.0.16 | 0x01000102 + v1.0.17 | 0x01000102 + v1.0.18 | 0x01000102 + v1.0.19 | 0x01000103 + v1.0.20 | 0x01000104 + v1.0.21 | 0x01000105 + v1.0.22 | 0x01000106 + v1.0.23 | 0x01000107 + + */ #if defined (__FreeBSD__) - #if !defined ( LIBUSBX_API_VERSION ) + #if !defined (LIBUSBX_API_VERSION) #define LIBUSBX_API_VERSION LIBUSB_API_VERSION #elif !defined (LIBUSB_API_VERSION) #error unsupported libusb version @@ -39,8 +39,8 @@ #define MINIMAL_API_VERSION 0x01000104 // v1.0.20 #endif -#if ( LIBUSB_API_VERSION < MINIMAL_API_VERSION ) +#if (LIBUSB_API_VERSION < MINIMAL_API_VERSION) #error unsupported libusb version #endif -#endif // STLINKUSB_H +#endif // LIBUSB_SETTINGS_H diff --git a/src/stlink-lib/logging.c b/src/stlink-lib/logging.c index ad144f6a4..a5eef9e17 100644 --- a/src/stlink-lib/logging.c +++ b/src/stlink-lib/logging.c @@ -1,7 +1,7 @@ /* - * UglyLogging. Slow, yet another wheel reinvented, but enough to make the - * rest of our code pretty enough. + * UglyLogging * + * Slow, yet another wheel reinvented, but enough to make the rest of our code pretty enough. */ #include #include @@ -15,23 +15,24 @@ static int max_level = UDEBUG; int ugly_init(int maximum_threshold) { max_level = maximum_threshold; - return 0; + return(0); } int ugly_log(int level, const char *tag, const char *format, ...) { if (level > max_level) { - return 0; + return(0); } - // Flush to maintain order of streams - fflush(stdout); + fflush(stdout); // flush to maintain order of streams va_list args; va_start(args, format); time_t mytt = time(NULL); struct tm *tt; tt = localtime(&mytt); - fprintf(stderr, "%d-%02d-%02dT%02d:%02d:%02d ", tt->tm_year + 1900, tt->tm_mon + 1, tt->tm_mday, tt->tm_hour, tt->tm_min, tt->tm_sec); + fprintf(stderr, "%d-%02d-%02dT%02d:%02d:%02d ", tt->tm_year + 1900, tt->tm_mon + 1, + tt->tm_mday, tt->tm_hour, tt->tm_min, tt->tm_sec); + switch (level) { case UDEBUG: fprintf(stderr, "DEBUG %s: ", tag); @@ -49,13 +50,13 @@ int ugly_log(int level, const char *tag, const char *format, ...) { fprintf(stderr, "%d %s: ", level, tag); break; } + vfprintf(stderr, format, args); fflush(stderr); va_end(args); - return 1; + return(1); } - /* * Log message levels. * - LIBUSB_LOG_LEVEL_NONE (0) : no messages ever printed by the library (default) @@ -63,15 +64,14 @@ int ugly_log(int level, const char *tag, const char *format, ...) { * - LIBUSB_LOG_LEVEL_WARNING (2) : warning and error messages are printed to stderr * - LIBUSB_LOG_LEVEL_INFO (3) : informational messages are printed to stderr * - LIBUSB_LOG_LEVEL_DEBUG (4) : debug and informational messages are printed to stderr -*/ -int ugly_libusb_log_level(enum ugly_loglevel v) -{ + */ +int ugly_libusb_log_level(enum ugly_loglevel v) { switch (v) { - case UDEBUG: return 4; - case UINFO: return 3; - case UWARN: return 2; - case UERROR: return 1; - }; + case UDEBUG: return(4); + case UINFO: return(3); + case UWARN: return(2); + case UERROR: return(1); + } - return 2; + return(2); } diff --git a/src/stlink-lib/logging.h b/src/stlink-lib/logging.h index 1083b2c55..78562b0d9 100644 --- a/src/stlink-lib/logging.h +++ b/src/stlink-lib/logging.h @@ -3,9 +3,9 @@ */ #ifndef UGLYLOGGING_H -#define UGLYLOGGING_H +#define UGLYLOGGING_H -#ifdef __cplusplus +#ifdef __cplusplus extern "C" { #endif @@ -21,11 +21,11 @@ int ugly_log(int level, const char *tag, const char *format, ...); int ugly_libusb_log_level(enum ugly_loglevel v); #define UGLY_LOG_FILE (strstr(__FILE__, "/") != NULL ? \ - strrchr(__FILE__, '/') + 1 : strstr(__FILE__, "\\") != NULL ? \ - strrchr(__FILE__, '\\') + 1 : __FILE__) + strrchr(__FILE__, '/') + 1 : strstr(__FILE__, "\\") != NULL ? \ + strrchr(__FILE__, '\\') + 1 : __FILE__) -/** @todo we need to write this in a more generic way, for now this should compile - on visual studio (See http://stackoverflow.com/a/8673872/1836746) */ +// TODO: we need to write this in a more generic way, for now this should compile +// on visual studio (See http://stackoverflow.com/a/8673872/1836746) #define DLOG_HELPER(format, ...) ugly_log(UDEBUG, UGLY_LOG_FILE, format, __VA_ARGS__) #define DLOG(...) DLOG_HELPER(__VA_ARGS__, "") #define ILOG_HELPER(format, ...) ugly_log(UINFO, UGLY_LOG_FILE, format, __VA_ARGS__) @@ -35,9 +35,8 @@ int ugly_libusb_log_level(enum ugly_loglevel v); #define ELOG_HELPER(format, ...) ugly_log(UERROR, UGLY_LOG_FILE, format, __VA_ARGS__) #define ELOG(...) ELOG_HELPER(__VA_ARGS__, "") -#ifdef __cplusplus +#ifdef __cplusplus } #endif -#endif /* UGLYLOGGING_H */ - +#endif // UGLYLOGGING_H diff --git a/src/stlink-lib/md5.c b/src/stlink-lib/md5.c index 521c52969..4c353bfd6 100755 --- a/src/stlink-lib/md5.c +++ b/src/stlink-lib/md5.c @@ -1,80 +1,53 @@ /* - * Retrieved from https://github.com/WaterJuice/WjCryptLib + * WjCryptLib_Md5 (https://github.com/WaterJuice/WjCryptLib) + * Implementation of MD5 hash function. Originally written by Alexander Peslyak. + * Modified by WaterJuice retaining Public Domain license. + * This is free and unencumbered software released into the public domain - June 2013 - waterjuice.org */ -//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -// WjCryptLib_Md5 -// -// Implementation of MD5 hash function. Originally written by Alexander Peslyak. Modified by WaterJuice retaining -// Public Domain license. -// -// This is free and unencumbered software released into the public domain - June 2013 waterjuice.org -//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// - -//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -// IMPORTS -//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// - #include #include "md5.h" -//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -// INTERNAL FUNCTIONS -//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// - -//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -// F, G, H, I -// -// The basic MD5 functions. F and G are optimised compared to their RFC 1321 definitions for architectures that lack -// an AND-NOT instruction, just like in Colin Plumb's implementation. -//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -#define F( x, y, z ) ( (z) ^ ((x) & ((y) ^ (z))) ) -#define G( x, y, z ) ( (y) ^ ((z) & ((x) ^ (y))) ) -#define H( x, y, z ) ( (x) ^ (y) ^ (z) ) -#define I( x, y, z ) ( (y) ^ ((x) | ~(z)) ) - -//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -// STEP -// -// The MD5 transformation for all four rounds. -//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +/* INTERNAL FUNCTIONS */ + +/* F, G, H, I + * + * The basic MD5 functions. + * F and G are optimised compared to their RFC 1321 definitions for architectures + * that lack an AND-NOT instruction, just like in Colin Plumb's implementation. + */ +#define F( x, y, z ) ((z) ^ ((x) & ((y) ^ (z)))) +#define G( x, y, z ) ((y) ^ ((z) & ((x) ^ (y)))) +#define H( x, y, z ) ((x) ^ (y) ^ (z)) +#define I( x, y, z ) ((y) ^ ((x) | ~(z))) + +/* STEP: The MD5 transformation for all four rounds. */ #define STEP( f, a, b, c, d, x, t, s ) \ (a) += f((b), (c), (d)) + (x) + (t); \ (a) = (((a) << (s)) | (((a) & 0xffffffff) >> (32 - (s)))); \ (a) += (b); -//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -// TransformFunction -// -// This processes one or more 64-byte data blocks, but does NOT update the bit counters. There are no alignment -// requirements. -//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -static -void* - TransformFunction - ( - Md5Context* ctx, - void const* data, - uintmax_t size - ) -{ +/* TransformFunction + * This processes one or more 64-byte data blocks, but does NOT update the bit counters. + * There are no alignment requirements. + */ +static void* TransformFunction(Md5Context* ctx, void const* data, uintmax_t size) { uint8_t* ptr; - uint32_t a; - uint32_t b; - uint32_t c; - uint32_t d; - uint32_t saved_a; - uint32_t saved_b; - uint32_t saved_c; - uint32_t saved_d; + uint32_t a; + uint32_t b; + uint32_t c; + uint32_t d; + uint32_t saved_a; + uint32_t saved_b; + uint32_t saved_c; + uint32_t saved_d; #define GET(n) (ctx->block[(n)]) - #define SET(n) (ctx->block[(n)] = \ - ((uint32_t)ptr[(n)*4 + 0] << 0) \ - | ((uint32_t)ptr[(n)*4 + 1] << 8 ) \ - | ((uint32_t)ptr[(n)*4 + 2] << 16) \ - | ((uint32_t)ptr[(n)*4 + 3] << 24) ) + #define SET(n) (ctx->block[(n)] = ((uint32_t)ptr[(n) * 4 + 0] << 0) | \ + ((uint32_t)ptr[(n) * 4 + 1] << 8) | \ + ((uint32_t)ptr[(n) * 4 + 2] << 16) | \ + ((uint32_t)ptr[(n) * 4 + 3] << 24)) ptr = (uint8_t*)data; @@ -83,8 +56,7 @@ void* c = ctx->c; d = ctx->d; - do - { + do { saved_a = a; saved_b = b; saved_c = c; @@ -178,24 +150,16 @@ void* #undef GET #undef SET - return ptr; + return(ptr); } -//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -// EXPORTED FUNCTIONS -//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// - -//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -// Md5Initialise -// -// Initialises an MD5 Context. Use this to initialise/reset a context. -//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -void - Md5Initialise - ( - Md5Context* Context // [out] - ) -{ +/* EXPORTED FUNCTIONS */ + +/* Md5Initialise + * Initialises an MD5 Context. + * Use this to initialise/reset a context. + */ +void Md5Initialise(Md5Context* Context /* [out] */) { Context->a = 0x67452301; Context->b = 0xefcdab89; Context->c = 0x98badcfe; @@ -205,39 +169,31 @@ void Context->hi = 0; } -//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -// Md5Update -// -// Adds data to the MD5 context. This will process the data and update the internal state of the context. Keep on -// calling this function until all the data has been added. Then call Md5Finalise to calculate the hash. -//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -void - Md5Update - ( - Md5Context* Context, // [in out] - void const* Buffer, // [in] - uint32_t BufferSize // [in] - ) -{ - uint32_t saved_lo; - uint32_t used; - uint32_t free; +/* Md5Update + * Adds data to the MD5 context. + * This will process the data and update the internal state of the context. + * Keep on calling this function until all the data has been added. + * Then call Md5Finalise to calculate the hash. + */ +void Md5Update(Md5Context* Context /* [in out] */, void const* Buffer /* [in] */, uint32_t BufferSize /* [in] */) { + uint32_t saved_lo; + uint32_t used; + uint32_t free; saved_lo = Context->lo; - if ( (Context->lo = (saved_lo + BufferSize) & 0x1fffffff) < saved_lo ) - { + + if ((Context->lo = (saved_lo + BufferSize) & 0x1fffffff) < saved_lo) { Context->hi++; } - Context->hi += (uint32_t)( BufferSize >> 29 ); + + Context->hi += (uint32_t)(BufferSize >> 29); used = saved_lo & 0x3f; - if ( used ) - { + if ( used ) { free = 64 - used; - if ( BufferSize < free ) - { + if ( BufferSize < free ) { memcpy( &Context->buffer[used], Buffer, BufferSize ); return; } @@ -248,8 +204,7 @@ void TransformFunction(Context, Context->buffer, 64); } - if ( BufferSize >= 64 ) - { + if ( BufferSize >= 64 ) { Buffer = TransformFunction( Context, Buffer, BufferSize & ~(unsigned long)0x3f ); BufferSize &= 0x3f; } @@ -257,21 +212,14 @@ void memcpy( Context->buffer, Buffer, BufferSize ); } -//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -// Md5Finalise -// -// Performs the final calculation of the hash and returns the digest (16 byte buffer containing 128bit hash). After -// calling this, Md5Initialised must be used to reuse the context. -//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -void - Md5Finalise - ( - Md5Context* Context, // [in out] - MD5_HASH* Digest // [in] - ) -{ - uint32_t used; - uint32_t free; +/* Md5Finalise + * Performs the final calculation of the hash and returns the digest + * (16 byte buffer containing 128bit hash). + * After calling this, Md5Initialised must be used to reuse the context. + */ +void Md5Finalise(Md5Context* Context /* [in out] */, MD5_HASH* Digest /* [in] */) { + uint32_t used; + uint32_t free; used = Context->lo & 0x3f; @@ -279,8 +227,7 @@ void free = 64 - used; - if (free < 8) - { + if (free < 8) { memset( &Context->buffer[used], 0, free ); TransformFunction( Context, Context->buffer, 64 ); used = 0; @@ -290,48 +237,40 @@ void memset( &Context->buffer[used], 0, free - 8 ); Context->lo <<= 3; - Context->buffer[56] = (uint8_t)( Context->lo ); - Context->buffer[57] = (uint8_t)( Context->lo >> 8 ); - Context->buffer[58] = (uint8_t)( Context->lo >> 16 ); - Context->buffer[59] = (uint8_t)( Context->lo >> 24 ); - Context->buffer[60] = (uint8_t)( Context->hi ); - Context->buffer[61] = (uint8_t)( Context->hi >> 8 ); - Context->buffer[62] = (uint8_t)( Context->hi >> 16 ); - Context->buffer[63] = (uint8_t)( Context->hi >> 24 ); + Context->buffer[56] = (uint8_t)(Context->lo); + Context->buffer[57] = (uint8_t)(Context->lo >> 8); + Context->buffer[58] = (uint8_t)(Context->lo >> 16); + Context->buffer[59] = (uint8_t)(Context->lo >> 24); + Context->buffer[60] = (uint8_t)(Context->hi); + Context->buffer[61] = (uint8_t)(Context->hi >> 8); + Context->buffer[62] = (uint8_t)(Context->hi >> 16); + Context->buffer[63] = (uint8_t)(Context->hi >> 24); TransformFunction( Context, Context->buffer, 64 ); - Digest->bytes[0] = (uint8_t)( Context->a ); - Digest->bytes[1] = (uint8_t)( Context->a >> 8 ); - Digest->bytes[2] = (uint8_t)( Context->a >> 16 ); - Digest->bytes[3] = (uint8_t)( Context->a >> 24 ); - Digest->bytes[4] = (uint8_t)( Context->b ); - Digest->bytes[5] = (uint8_t)( Context->b >> 8 ); - Digest->bytes[6] = (uint8_t)( Context->b >> 16 ); - Digest->bytes[7] = (uint8_t)( Context->b >> 24 ); - Digest->bytes[8] = (uint8_t)( Context->c ); - Digest->bytes[9] = (uint8_t)( Context->c >> 8 ); - Digest->bytes[10] = (uint8_t)( Context->c >> 16 ); - Digest->bytes[11] = (uint8_t)( Context->c >> 24 ); - Digest->bytes[12] = (uint8_t)( Context->d ); - Digest->bytes[13] = (uint8_t)( Context->d >> 8 ); - Digest->bytes[14] = (uint8_t)( Context->d >> 16 ); - Digest->bytes[15] = (uint8_t)( Context->d >> 24 ); + Digest->bytes[0] = (uint8_t)(Context->a); + Digest->bytes[1] = (uint8_t)(Context->a >> 8); + Digest->bytes[2] = (uint8_t)(Context->a >> 16); + Digest->bytes[3] = (uint8_t)(Context->a >> 24); + Digest->bytes[4] = (uint8_t)(Context->b); + Digest->bytes[5] = (uint8_t)(Context->b >> 8); + Digest->bytes[6] = (uint8_t)(Context->b >> 16); + Digest->bytes[7] = (uint8_t)(Context->b >> 24); + Digest->bytes[8] = (uint8_t)(Context->c); + Digest->bytes[9] = (uint8_t)(Context->c >> 8); + Digest->bytes[10] = (uint8_t)(Context->c >> 16); + Digest->bytes[11] = (uint8_t)(Context->c >> 24); + Digest->bytes[12] = (uint8_t)(Context->d); + Digest->bytes[13] = (uint8_t)(Context->d >> 8); + Digest->bytes[14] = (uint8_t)(Context->d >> 16); + Digest->bytes[15] = (uint8_t)(Context->d >> 24); } -//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -// Md5Calculate -// -// Combines Md5Initialise, Md5Update, and Md5Finalise into one function. Calculates the MD5 hash of the buffer. -//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -void - Md5Calculate - ( - void const* Buffer, // [in] - uint32_t BufferSize, // [in] - MD5_HASH* Digest // [in] - ) -{ +/* Md5Calculate + * Combines Md5Initialise, Md5Update, and Md5Finalise into one function. + * Calculates the MD5 hash of the buffer. + */ +void Md5Calculate(void const* Buffer /* [in] */, uint32_t BufferSize /* [in] */, MD5_HASH* Digest /* [in] */) { Md5Context context; Md5Initialise( &context ); diff --git a/src/stlink-lib/md5.h b/src/stlink-lib/md5.h index 5ef252221..a69d7fc6b 100755 --- a/src/stlink-lib/md5.h +++ b/src/stlink-lib/md5.h @@ -1,100 +1,63 @@ /* - * Retrieved from https://github.com/WaterJuice/WjCryptLib + * WjCryptLib_Md5 (https://github.com/WaterJuice/WjCryptLib) + * Implementation of MD5 hash function. Originally written by Alexander Peslyak. + * Modified by WaterJuice retaining Public Domain license. + * This is free and unencumbered software released into the public domain - June 2013 - waterjuice.org */ -//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -// WjCryptLib_Md5 -// -// Implementation of MD5 hash function. Originally written by Alexander Peslyak. Modified by WaterJuice retaining -// Public Domain license. -// -// This is free and unencumbered software released into the public domain - June 2013 waterjuice.org -//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// - #pragma once -//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -// IMPORTS -//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// - #include #include -//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -// TYPES -//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +/* TYPES */ -// Md5Context - This must be initialised using Md5Initialised. Do not modify the contents of this structure directly. -typedef struct -{ - uint32_t lo; - uint32_t hi; - uint32_t a; - uint32_t b; - uint32_t c; - uint32_t d; - uint8_t buffer[64]; - uint32_t block[16]; +/* Md5Context + * This must be initialised using Md5Initialised. + * Do not modify the contents of this structure directly. + */ +typedef struct { + uint32_t lo; + uint32_t hi; + uint32_t a; + uint32_t b; + uint32_t c; + uint32_t d; + uint8_t buffer[64]; + uint32_t block[16]; } Md5Context; -#define MD5_HASH_SIZE ( 128 / 8 ) +#define MD5_HASH_SIZE (128 / 8) -typedef struct -{ - uint8_t bytes [MD5_HASH_SIZE]; +typedef struct { + uint8_t bytes [MD5_HASH_SIZE]; } MD5_HASH; -//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -// PUBLIC FUNCTIONS -//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +/* PUBLIC FUNCTIONS */ -//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -// Md5Initialise -// -// Initialises an MD5 Context. Use this to initialise/reset a context. -//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -void - Md5Initialise - ( - Md5Context* Context // [out] - ); +/* Md5Initialise + * Initialises an MD5 Context. + * Use this to initialise/reset a context. + */ +void Md5Initialise(Md5Context* Context /* [out] */); -//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -// Md5Update -// -// Adds data to the MD5 context. This will process the data and update the internal state of the context. Keep on -// calling this function until all the data has been added. Then call Md5Finalise to calculate the hash. -//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -void - Md5Update - ( - Md5Context* Context, // [in out] - void const* Buffer, // [in] - uint32_t BufferSize // [in] - ); +/* Md5Update + * Adds data to the MD5 context. + * This will process the data and update the internal state of the context. + * Keep on calling this function until all the data has been added. + * Then call Md5Finalise to calculate the hash. + */ +void Md5Update(Md5Context* Context /* [in out] */, void const* Buffer /* [in] */, uint32_t BufferSize /* [in] */); -//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -// Md5Finalise -// -// Performs the final calculation of the hash and returns the digest (16 byte buffer containing 128bit hash). After -// calling this, Md5Initialised must be used to reuse the context. -//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -void - Md5Finalise - ( - Md5Context* Context, // [in out] - MD5_HASH* Digest // [in] - ); +/* Md5Finalise + * Performs the final calculation of the hash and returns the digest + * (16 byte buffer containing 128bit hash). + * After calling this, Md5Initialised must be used to reuse the context. + */ +void Md5Finalise(Md5Context* Context /* [in out] */, MD5_HASH* Digest /* [in] */); -//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -// Md5Calculate -// -// Combines Md5Initialise, Md5Update, and Md5Finalise into one function. Calculates the MD5 hash of the buffer. -//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -void - Md5Calculate - ( - void const* Buffer, // [in] - uint32_t BufferSize, // [in] - MD5_HASH* Digest // [in] - ); +/* Md5Calculate + * Combines Md5Initialise, Md5Update, and Md5Finalise into one function. + * Calculates the MD5 hash of the buffer. + */ +void Md5Calculate(void const* Buffer /* [in] */, uint32_t BufferSize /* [in] */, MD5_HASH* Digest /* [in] */); diff --git a/src/stlink-lib/reg.h b/src/stlink-lib/reg.h new file mode 100644 index 000000000..dde77ef50 --- /dev/null +++ b/src/stlink-lib/reg.h @@ -0,0 +1,20 @@ +#ifndef STLINK_REG_H_ +#define STLINK_REG_H_ + +#define STLINK_REG_CM3_CPUID 0xE000ED00 +#define STLINK_REG_CM3_FP_CTRL 0xE0002000 +#define STLINK_REG_CM3_FP_COMP0 0xE0002008 + +/* Cortex™-M3 Technical Reference Manual */ +/* Debug Halting Control and Status Register */ +#define STLINK_REG_DHCSR 0xe000edf0 +#define STLINK_REG_DHCSR_DBGKEY 0xa05f0000 +#define STLINK_REG_DCRSR 0xe000edf4 +#define STLINK_REG_DCRDR 0xe000edf8 + +/* Application Interrupt and Reset Control Register */ +#define STLINK_REG_AIRCR 0xe000ed0c +#define STLINK_REG_AIRCR_VECTKEY 0x05fa0000 +#define STLINK_REG_AIRCR_SYSRESETREQ 0x00000004 + +#endif // STLINK_REG_H_ diff --git a/src/stlink-lib/sg.c b/src/stlink-lib/sg.c index 7fae19976..5cc27b1fe 100644 --- a/src/stlink-lib/sg.c +++ b/src/stlink-lib/sg.c @@ -27,7 +27,7 @@ * www.usb.org/developers/devclass_docs/usbmassbulk_10.pdf * * dt - Data Transfer (IN/OUT) - * CBW - Command Block Wrapper + * CBW - Command Block Wrapper * CSW - Command Status Wrapper * RFU - Reserved for Future Use * @@ -90,8 +90,8 @@ #define STLINK_FALSE 0x81 static void clear_cdb(struct stlink_libsg *sl) { - for (size_t i = 0; i < sizeof (sl->cdb_cmd_blk); i++) - sl->cdb_cmd_blk[i] = 0; + for (size_t i = 0; i < sizeof(sl->cdb_cmd_blk); i++) { sl->cdb_cmd_blk[i] = 0; } + // set default sl->cdb_cmd_blk[0] = STLINK_DEBUG_COMMAND; sl->q_data_dir = Q_DATA_IN; @@ -116,46 +116,53 @@ static int get_usb_mass_storage_status(libusb_device_handle *handle, uint8_t end int transferred; int ret; int try = 0; + do { ret = libusb_bulk_transfer(handle, endpoint, (unsigned char *)&csw, sizeof(csw), - &transferred, SG_TIMEOUT_MSEC); - if (ret == LIBUSB_ERROR_PIPE) { - libusb_clear_halt(handle, endpoint); - } + &transferred, SG_TIMEOUT_MSEC); + + if (ret == LIBUSB_ERROR_PIPE) { libusb_clear_halt(handle, endpoint); } + try++; } while ((ret == LIBUSB_ERROR_PIPE) && (try < 3)); + if (ret != LIBUSB_SUCCESS) { WLOG("%s: receiving failed: %d\n", __func__, ret); - return -1; + return(-1); } + if (transferred != sizeof(csw)) { WLOG("%s: received unexpected amount: %d\n", __func__, transferred); - return -1; + return(-1); } uint32_t rsig = read_uint32(csw, 0); uint32_t rtag = read_uint32(csw, 4); /* uint32_t residue = read_uint32(csw, 8); */ #define USB_CSW_SIGNATURE 0x53425355 // 'U' 'S' 'B' 'S' (reversed) + if (rsig != USB_CSW_SIGNATURE) { WLOG("status signature was invalid: %#x\n", rsig); - return -1; + return(-1); } + *tag = rtag; uint8_t rstatus = csw[12]; - return rstatus; + return(rstatus); } static int dump_CDB_command(uint8_t *cdb, uint8_t cdb_len) { char dbugblah[100]; char *dbugp = dbugblah; dbugp += sprintf(dbugp, "Sending CDB ["); + for (uint8_t i = 0; i < cdb_len; i++) { - dbugp += sprintf(dbugp, " %#02x", (unsigned int) cdb[i]); + dbugp += sprintf(dbugp, " %#02x", (unsigned int)cdb[i]); } + sprintf(dbugp, "]\n"); DLOG(dbugblah); - return 0; + return(0); } /** @@ -170,15 +177,14 @@ static int dump_CDB_command(uint8_t *cdb, uint8_t cdb_len) { * @return */ int send_usb_mass_storage_command(libusb_device_handle *handle, uint8_t endpoint_out, - uint8_t *cdb, uint8_t cdb_length, - uint8_t lun, uint8_t flags, uint32_t expected_rx_size) { + uint8_t *cdb, uint8_t cdb_length, + uint8_t lun, uint8_t flags, uint32_t expected_rx_size) { DLOG("Sending usb m-s cmd: cdblen:%d, rxsize=%d\n", cdb_length, expected_rx_size); dump_CDB_command(cdb, cdb_length); static uint32_t tag; - if (tag == 0) { - tag = 1; - } + + if (tag == 0) { tag = 1; } int try = 0; int ret = 0; @@ -193,14 +199,14 @@ int send_usb_mass_storage_command(libusb_device_handle *handle, uint8_t endpoint c_buf[i++] = 'C'; write_uint32(&c_buf[i], tag); uint32_t this_tag = tag++; - write_uint32(&c_buf[i+4], expected_rx_size); - i+= 8; + write_uint32(&c_buf[i + 4], expected_rx_size); + i += 8; c_buf[i++] = flags; c_buf[i++] = lun; c_buf[i++] = cdb_length; - // Now the actual CDB request + // now the actual CDB request assert(cdb_length <= CDB_SL); memcpy(&(c_buf[i]), cdb, cdb_length); @@ -209,19 +215,22 @@ int send_usb_mass_storage_command(libusb_device_handle *handle, uint8_t endpoint // send.... do { ret = libusb_bulk_transfer(handle, endpoint_out, c_buf, sending_length, - &real_transferred, SG_TIMEOUT_MSEC); + &real_transferred, SG_TIMEOUT_MSEC); + if (ret == LIBUSB_ERROR_PIPE) { libusb_clear_halt(handle, endpoint_out); } + try++; } while ((ret == LIBUSB_ERROR_PIPE) && (try < 3)); + if (ret != LIBUSB_SUCCESS) { WLOG("sending failed: %d\n", ret); - return -1; + return(-1); } - return this_tag; -} + return(this_tag); +} /** * Straight from stm8 stlink code... @@ -238,36 +247,44 @@ static void get_sense(libusb_device_handle *handle, uint8_t endpoint_in, uint8_t cdb[0] = REQUEST_SENSE; cdb[4] = REQUEST_SENSE_LENGTH; uint32_t tag = send_usb_mass_storage_command(handle, endpoint_out, cdb, sizeof(cdb), 0, - LIBUSB_ENDPOINT_IN, REQUEST_SENSE_LENGTH); + LIBUSB_ENDPOINT_IN, REQUEST_SENSE_LENGTH); + if (tag == 0) { WLOG("refusing to send request sense with tag 0\n"); return; } + unsigned char sense[REQUEST_SENSE_LENGTH]; int transferred; int ret; int try = 0; + do { ret = libusb_bulk_transfer(handle, endpoint_in, sense, sizeof(sense), - &transferred, SG_TIMEOUT_MSEC); - if (ret == LIBUSB_ERROR_PIPE) { - libusb_clear_halt(handle, endpoint_in); - } + &transferred, SG_TIMEOUT_MSEC); + + if (ret == LIBUSB_ERROR_PIPE) { libusb_clear_halt(handle, endpoint_in); } + try++; } while ((ret == LIBUSB_ERROR_PIPE) && (try < 3)); + if (ret != LIBUSB_SUCCESS) { WLOG("receiving sense failed: %d\n", ret); return; } + if (transferred != sizeof(sense)) { WLOG("received unexpected amount of sense: %d != %d\n", transferred, sizeof(sense)); } + uint32_t received_tag; int status = get_usb_mass_storage_status(handle, endpoint_in, &received_tag); + if (status != 0) { WLOG("receiving sense failed with status: %02x\n", status); return; } + if (sense[0] != 0x70 && sense[0] != 0x71) { WLOG("No sense data\n"); } else { @@ -286,49 +303,55 @@ static void get_sense(libusb_device_handle *handle, uint8_t endpoint_in, uint8_t * @return number of bytes actually sent, or -1 for failures. */ int send_usb_data_only(libusb_device_handle *handle, unsigned char endpoint_out, - unsigned char endpoint_in, unsigned char *cbuf, unsigned int length) { + unsigned char endpoint_in, unsigned char *cbuf, unsigned int length) { int ret; int real_transferred; int try = 0; + do { ret = libusb_bulk_transfer(handle, endpoint_out, cbuf, length, - &real_transferred, SG_TIMEOUT_MSEC); - if (ret == LIBUSB_ERROR_PIPE) { - libusb_clear_halt(handle, endpoint_out); - } + &real_transferred, SG_TIMEOUT_MSEC); + + if (ret == LIBUSB_ERROR_PIPE) { libusb_clear_halt(handle, endpoint_out); } + try++; } while ((ret == LIBUSB_ERROR_PIPE) && (try < 3)); + if (ret != LIBUSB_SUCCESS) { WLOG("sending failed: %d\n", ret); - return -1; + return(-1); } // now, swallow up the status, so that things behave nicely... uint32_t received_tag; // -ve is for my errors, 0 is good, +ve is libusb sense status bytes int status = get_usb_mass_storage_status(handle, endpoint_in, &received_tag); + if (status < 0) { WLOG("receiving status failed: %d\n", status); - return -1; + return(-1); } + if (status != 0) { WLOG("receiving status not passed :(: %02x\n", status); } + if (status == 1) { get_sense(handle, endpoint_in, endpoint_out); - return -1; + return(-1); } - return real_transferred; + return(real_transferred); } int stlink_q(stlink_t *sl) { struct stlink_libsg* sg = sl->backend_data; - //uint8_t cdb_len = 6; // FIXME varies!!! + // uint8_t cdb_len = 6; // FIXME varies!!! uint8_t cdb_len = 10; // FIXME varies!!! uint8_t lun = 0; // always zero... uint32_t tag = send_usb_mass_storage_command(sg->usb_handle, sg->ep_req, - sg->cdb_cmd_blk, cdb_len, lun, LIBUSB_ENDPOINT_IN, sl->q_len); + sg->cdb_cmd_blk, cdb_len, lun, + LIBUSB_ENDPOINT_IN, sl->q_len); // now wait for our response... @@ -337,19 +360,20 @@ int stlink_q(stlink_t *sl) { int try = 0; int real_transferred; int ret; + if (rx_length > 0) { do { ret = libusb_bulk_transfer(sg->usb_handle, sg->ep_rep, sl->q_buf, rx_length, - &real_transferred, SG_TIMEOUT_MSEC); - if (ret == LIBUSB_ERROR_PIPE) { - libusb_clear_halt(sg->usb_handle, sg->ep_req); - } + &real_transferred, SG_TIMEOUT_MSEC); + + if (ret == LIBUSB_ERROR_PIPE) { libusb_clear_halt(sg->usb_handle, sg->ep_req); } + try++; } while ((ret == LIBUSB_ERROR_PIPE) && (try < 3)); if (ret != LIBUSB_SUCCESS) { WLOG("Receiving failed: %d\n", ret); - return -1; + return(-1); } if (real_transferred != rx_length) { @@ -360,31 +384,36 @@ int stlink_q(stlink_t *sl) { uint32_t received_tag; // -ve is for my errors, 0 is good, +ve is libusb sense status bytes int status = get_usb_mass_storage_status(sg->usb_handle, sg->ep_rep, &received_tag); + if (status < 0) { WLOG("receiving status failed: %d\n", status); - return -1; + return(-1); } + if (status != 0) { WLOG("receiving status not passed :(: %02x\n", status); } + if (status == 1) { get_sense(sg->usb_handle, sg->ep_rep, sg->ep_req); - return -1; + return(-1); } + if (received_tag != tag) { WLOG("received tag %d but expected %d\n", received_tag, tag); - //return -1; + // return -1; } + if (rx_length > 0 && real_transferred != rx_length) { - return -1; + return(-1); } - return 0; + + return(0); } -// TODO thinking, cleanup +// TODO: thinking, cleanup void stlink_stat(stlink_t *stl, char *txt) { - if (stl->q_len <= 0) - return; + if (stl->q_len <= 0) { return; } stlink_print_data(stl); @@ -406,7 +435,7 @@ int _stlink_sg_version(stlink_t *stl) { sl->cdb_cmd_blk[0] = STLINK_GET_VERSION; stl->q_len = 6; sl->q_addr = 0; - return stlink_q(stl); + return(stlink_q(stl)); } // Get stlink mode: @@ -418,23 +447,23 @@ int _stlink_sg_current_mode(stlink_t *stl) { sl->cdb_cmd_blk[0] = STLINK_GET_CURRENT_MODE; stl->q_len = 2; sl->q_addr = 0; - if (stlink_q(stl)) - return -1; - return stl->q_buf[0]; + if (stlink_q(stl)) { return(-1); } + + return(stl->q_buf[0]); } -// Exit the mass mode and enter the swd debug mode. +// exit the mass mode and enter the swd debug mode. int _stlink_sg_enter_swd_mode(stlink_t *sl) { struct stlink_libsg *sg = sl->backend_data; clear_cdb(sg); sg->cdb_cmd_blk[1] = STLINK_DEBUG_APIV1_ENTER; sg->cdb_cmd_blk[2] = STLINK_DEBUG_ENTER_SWD; sl->q_len = 0; // >0 -> aboard - return stlink_q(sl); + return(stlink_q(sl)); } -// Exit the mass mode and enter the jtag debug mode. +// exit the mass mode and enter the jtag debug mode. // (jtag is disabled in the discovery's stlink firmware) int _stlink_sg_enter_jtag_mode(stlink_t *sl) { struct stlink_libsg *sg = sl->backend_data; @@ -443,7 +472,7 @@ int _stlink_sg_enter_jtag_mode(stlink_t *sl) { sg->cdb_cmd_blk[1] = STLINK_DEBUG_APIV1_ENTER; sg->cdb_cmd_blk[2] = STLINK_DEBUG_ENTER_JTAG; sl->q_len = 0; - return stlink_q(sl); + return(stlink_q(sl)); } // XXX kernel driver performs reset, the device temporally disappears @@ -455,7 +484,7 @@ int _stlink_sg_exit_dfu_mode(stlink_t *sl) { sg->cdb_cmd_blk[0] = STLINK_DFU_COMMAND; sg->cdb_cmd_blk[1] = STLINK_DFU_EXIT; sl->q_len = 0; // ?? - return stlink_q(sl); + return(stlink_q(sl)); /* [135121.844564] sd 19:0:0:0: [sdb] Unhandled error code [135121.844569] sd 19:0:0:0: [sdb] Result: hostbyte=DID_ERROR driverbyte=DRIVER_OK @@ -498,7 +527,7 @@ int _stlink_sg_exit_dfu_mode(stlink_t *sl) { [135131.678551] end_request: I/O error, dev sdb, sector 63872 ... [135131.853565] end_request: I/O error, dev sdb, sector 4096 - */ + */ } int _stlink_sg_core_id(stlink_t *sl) { @@ -509,73 +538,75 @@ int _stlink_sg_core_id(stlink_t *sl) { sl->q_len = 4; sg->q_addr = 0; ret = stlink_q(sl); - if (ret) - return ret; + + if (ret) { return(ret); } sl->core_id = read_uint32(sl->q_buf, 0); - return 0; + return(0); } -// Arm-core reset -> halted state. +// arm-core reset -> halted state. int _stlink_sg_reset(stlink_t *sl) { struct stlink_libsg *sg = sl->backend_data; clear_cdb(sg); sg->cdb_cmd_blk[1] = STLINK_DEBUG_APIV1_RESETSYS; sl->q_len = 2; sg->q_addr = 0; - if (stlink_q(sl)) - return -1; + + if (stlink_q(sl)) { return(-1); } // Reset through AIRCR so NRST does not need to be connected if (stlink_write_debug32(sl, STLINK_REG_AIRCR, - STLINK_REG_AIRCR_VECTKEY | STLINK_REG_AIRCR_SYSRESETREQ)) - return -1; + STLINK_REG_AIRCR_VECTKEY | \ + STLINK_REG_AIRCR_SYSRESETREQ)) { + return(-1); + } stlink_stat(sl, "core reset"); - return 0; + return(0); } -// Arm-core reset -> halted state. +// arm-core reset -> halted state. int _stlink_sg_jtag_reset(stlink_t *sl, int value) { struct stlink_libsg *sg = sl->backend_data; clear_cdb(sg); sg->cdb_cmd_blk[1] = STLINK_JTAG_DRIVE_NRST; - sg->cdb_cmd_blk[2] = (value)?0:1; + sg->cdb_cmd_blk[2] = (value) ? 0 : 1; sl->q_len = 3; sg->q_addr = 2; - if (stlink_q(sl)) - return -1; + + if (stlink_q(sl)) { return(-1); } stlink_stat(sl, "core reset"); - return 0; + return(0); } -// Arm-core status: halted or running. +// arm-core status: halted or running. int _stlink_sg_status(stlink_t *sl) { struct stlink_libsg *sg = sl->backend_data; clear_cdb(sg); sg->cdb_cmd_blk[1] = STLINK_DEBUG_GETSTATUS; sl->q_len = 2; sg->q_addr = 0; - return stlink_q(sl); + return(stlink_q(sl)); } -// Force the core into the debug mode -> halted state. +// force the core into the debug mode -> halted state. int _stlink_sg_force_debug(stlink_t *sl) { struct stlink_libsg *sg = sl->backend_data; clear_cdb(sg); sg->cdb_cmd_blk[1] = STLINK_DEBUG_FORCEDEBUG; sl->q_len = 2; sg->q_addr = 0; - if (stlink_q(sl)) - return -1; + + if (stlink_q(sl)) { return(-1); } stlink_stat(sl, "force debug"); - return 0; + return(0); } -// Read all arm-core registers. +// read all arm-core registers. int _stlink_sg_read_all_regs(stlink_t *sl, struct stlink_reg *regp) { struct stlink_libsg *sg = sl->backend_data; @@ -583,27 +614,28 @@ int _stlink_sg_read_all_regs(stlink_t *sl, struct stlink_reg *regp) { sg->cdb_cmd_blk[1] = STLINK_DEBUG_APIV1_READALLREGS; sl->q_len = 84; sg->q_addr = 0; - if (stlink_q(sl)) - return -1; + + if (stlink_q(sl)) { return(-1); } stlink_print_data(sl); - // TODO - most of this should be re-extracted up.... + // TODO: most of this should be re-extracted up.... // 0-3 | 4-7 | ... | 60-63 | 64-67 | 68-71 | 72-75 | 76-79 | 80-83 // r0 | r1 | ... | r15 | xpsr | main_sp | process_sp | rw | rw2 for (int i = 0; i < 16; i++) { regp->r[i] = read_uint32(sl->q_buf, 4 * i); - if (sl->verbose > 1) - DLOG("r%2d = 0x%08x\n", i, regp->r[i]); + + if (sl->verbose > 1) { DLOG("r%2d = 0x%08x\n", i, regp->r[i]); } } + regp->xpsr = read_uint32(sl->q_buf, 64); regp->main_sp = read_uint32(sl->q_buf, 68); regp->process_sp = read_uint32(sl->q_buf, 72); regp->rw = read_uint32(sl->q_buf, 76); regp->rw2 = read_uint32(sl->q_buf, 80); - if (sl->verbose < 2) - return 0; + + if (sl->verbose < 2) { return(0); } DLOG("xpsr = 0x%08x\n", regp->xpsr); DLOG("main_sp = 0x%08x\n", regp->main_sp); @@ -611,10 +643,10 @@ int _stlink_sg_read_all_regs(stlink_t *sl, struct stlink_reg *regp) { DLOG("rw = 0x%08x\n", regp->rw); DLOG("rw2 = 0x%08x\n", regp->rw2); - return 0; + return(0); } -// Read an arm-core register, the index must be in the range 0..20. +// read an arm-core register, the index must be in the range 0..20. // 0 | 1 | ... | 15 | 16 | 17 | 18 | 19 | 20 // r0 | r1 | ... | r15 | xpsr | main_sp | process_sp | rw | rw2 @@ -625,8 +657,8 @@ int _stlink_sg_read_reg(stlink_t *sl, int r_idx, struct stlink_reg *regp) { sg->cdb_cmd_blk[2] = r_idx; sl->q_len = 4; sg->q_addr = 0; - if (stlink_q(sl)) - return -1; + + if (stlink_q(sl)) { return(-1); } // 0 | 1 | ... | 15 | 16 | 17 | 18 | 19 | 20 // 0-3 | 4-7 | ... | 60-63 | 64-67 | 68-71 | 72-75 | 76-79 | 80-83 @@ -647,19 +679,19 @@ int _stlink_sg_read_reg(stlink_t *sl, int r_idx, struct stlink_reg *regp) { regp->process_sp = r; break; case 19: - regp->rw = r; //XXX ?(primask, basemask etc.) + regp->rw = r; // XXX ?(primask, basemask etc.) break; case 20: - regp->rw2 = r; //XXX ?(primask, basemask etc.) + regp->rw2 = r; // XXX ?(primask, basemask etc.) break; default: regp->r[r_idx] = r; } - return 0; + return(0); } -// Write an arm-core register. Index: +// write an arm-core register. Index: // 0 | 1 | ... | 15 | 16 | 17 | 18 | 19 | 20 // r0 | r1 | ... | r15 | xpsr | main_sp | process_sp | rw | rw2 @@ -673,16 +705,16 @@ int _stlink_sg_write_reg(stlink_t *sl, uint32_t reg, int idx) { write_uint32(sg->cdb_cmd_blk + 3, reg); sl->q_len = 2; sg->q_addr = 0; - if (stlink_q(sl)) - return -1; + + if (stlink_q(sl)) { return(-1); } stlink_stat(sl, "write reg"); - return 0; + return(0); } -// Write a register of the debug module of the core. +// write a register of the debug module of the core. // XXX ?(atomic writes) -// TODO test +// TODO: test void stlink_write_dreg(stlink_t *sl, uint32_t reg, uint32_t addr) { struct stlink_libsg *sg = sl->backend_data; DLOG("\n*** stlink_write_dreg ***\n"); @@ -698,38 +730,37 @@ void stlink_write_dreg(stlink_t *sl, uint32_t reg, uint32_t addr) { stlink_stat(sl, "write debug reg"); } -// Force the core exit the debug mode. +// force the core exit the debug mode. int _stlink_sg_run(stlink_t *sl) { struct stlink_libsg *sg = sl->backend_data; clear_cdb(sg); sg->cdb_cmd_blk[1] = STLINK_DEBUG_RUNCORE; sl->q_len = 2; sg->q_addr = 0; - if (stlink_q(sl)) - return -1; + + if (stlink_q(sl)) { return(-1); } stlink_stat(sl, "run core"); - return 0; + return(0); } -// Step the arm-core. +// step the arm-core. int _stlink_sg_step(stlink_t *sl) { struct stlink_libsg *sg = sl->backend_data; clear_cdb(sg); sg->cdb_cmd_blk[1] = STLINK_DEBUG_STEPCORE; sl->q_len = 2; sg->q_addr = 0; - if (stlink_q(sl)) - return -1; + + if (stlink_q(sl)) { return(-1); } stlink_stat(sl, "step core"); - return 0; + return(0); } -// TODO test +// TODO: test and make delegate! // see Cortex-M3 Technical Reference Manual -// TODO make delegate! void stlink_set_hw_bp(stlink_t *sl, int fp_nr, uint32_t addr, int fp) { DLOG("\n*** stlink_set_hw_bp ***\n"); struct stlink_libsg *sg = sl->backend_data; @@ -747,8 +778,7 @@ void stlink_set_hw_bp(stlink_t *sl, int fp_nr, uint32_t addr, int fp) { stlink_stat(sl, "set flash breakpoint"); } -// TODO test -// TODO make delegate! +// TODO: test and make delegate! void stlink_clr_hw_bp(stlink_t *sl, int fp_nr) { struct stlink_libsg *sg = sl->backend_data; DLOG("\n*** stlink_clr_hw_bp ***\n"); @@ -761,7 +791,7 @@ void stlink_clr_hw_bp(stlink_t *sl, int fp_nr) { stlink_stat(sl, "clear flash breakpoint"); } -// Read a "len" bytes to the sl->q_buf from the memory, max 6kB (6144 bytes) +// read a "len" bytes to the sl->q_buf from the memory, max 6kB (6144 bytes) int _stlink_sg_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { struct stlink_libsg *sg = sl->backend_data; clear_cdb(sg); @@ -778,14 +808,14 @@ int _stlink_sg_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { // (broken residue issue) sl->q_len = len; sg->q_addr = addr; - if (stlink_q(sl)) - return -1; + + if (stlink_q(sl)) { return(-1); } stlink_print_data(sl); - return 0; + return(0); } -// Write a "len" bytes from the sl->q_buf to the memory, max 64 Bytes. +// write a "len" bytes from the sl->q_buf to the memory, max 64 Bytes. int _stlink_sg_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len) { struct stlink_libsg *sg = sl->backend_data; int ret; @@ -799,21 +829,21 @@ int _stlink_sg_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len) { // this sends the command... ret = send_usb_mass_storage_command(sg->usb_handle, - sg->ep_req, sg->cdb_cmd_blk, CDB_SL, 0, 0, 0); - if (ret == -1) - return ret; + sg->ep_req, sg->cdb_cmd_blk, CDB_SL, 0, 0, 0); + + if (ret == -1) { return(ret); } // This sends the data... ret = send_usb_data_only(sg->usb_handle, - sg->ep_req, sg->ep_rep, sl->q_buf, len); - if (ret == -1) - return ret; + sg->ep_req, sg->ep_rep, sl->q_buf, len); + + if (ret == -1) { return(ret); } stlink_print_data(sl); - return 0; + return(0); } -// Write a "len" bytes from the sl->q_buf to the memory, max Q_BUF_LEN bytes. +// write a "len" bytes from the sl->q_buf to the memory, max Q_BUF_LEN bytes. int _stlink_sg_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { struct stlink_libsg *sg = sl->backend_data; int ret; @@ -827,21 +857,21 @@ int _stlink_sg_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { // this sends the command... ret = send_usb_mass_storage_command(sg->usb_handle, - sg->ep_req, sg->cdb_cmd_blk, CDB_SL, 0, 0, 0); - if (ret == -1) - return ret; + sg->ep_req, sg->cdb_cmd_blk, CDB_SL, 0, 0, 0); + + if (ret == -1) { return(ret); } // This sends the data... ret = send_usb_data_only(sg->usb_handle, - sg->ep_req, sg->ep_rep, sl->q_buf, len); - if (ret == -1) - return ret; + sg->ep_req, sg->ep_rep, sl->q_buf, len); + + if (ret == -1) { return(ret); } stlink_print_data(sl); - return 0; + return(0); } -// Write one DWORD data to memory +// write one DWORD data to memory int _stlink_sg_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data) { struct stlink_libsg *sg = sl->backend_data; clear_cdb(sg); @@ -850,10 +880,10 @@ int _stlink_sg_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data) { write_uint32(sg->cdb_cmd_blk + 2, addr); write_uint32(sg->cdb_cmd_blk + 6, data); sl->q_len = 2; - return stlink_q(sl); + return(stlink_q(sl)); } -// Read one DWORD data from memory +// read one DWORD data from memory int _stlink_sg_read_debug32(stlink_t *sl, uint32_t addr, uint32_t *data) { struct stlink_libsg *sg = sl->backend_data; clear_cdb(sg); @@ -861,24 +891,24 @@ int _stlink_sg_read_debug32(stlink_t *sl, uint32_t addr, uint32_t *data) { // 2-5: addr write_uint32(sg->cdb_cmd_blk + 2, addr); sl->q_len = 8; - if (stlink_q(sl)) - return -1; + + if (stlink_q(sl)) { return(-1); } *data = read_uint32(sl->q_buf, 4); - return 0; + return(0); } -// Exit the jtag or swd mode and enter the mass mode. +// exit the jtag or swd mode and enter the mass mode. int _stlink_sg_exit_debug_mode(stlink_t *stl) { if (stl) { struct stlink_libsg* sl = stl->backend_data; clear_cdb(sl); sl->cdb_cmd_blk[1] = STLINK_DEBUG_EXIT; stl->q_len = 0; // >0 -> aboard - return stlink_q(stl); + return(stlink_q(stl)); } - return 0; + return(0); } // 1) open a sg device, switch the stlink from dfu to mass mode @@ -906,35 +936,38 @@ static stlink_backend_t _stlink_sg_backend = { _stlink_sg_write_mem8, _stlink_sg_read_all_regs, _stlink_sg_read_reg, - NULL, /* read_all_unsupported_regs */ - NULL, /* read_unsupported_regs */ - NULL, /* write_unsupported_regs */ + NULL, // read_all_unsupported_regs + NULL, // read_unsupported_regs + NULL, // write_unsupported_regs _stlink_sg_write_reg, _stlink_sg_step, _stlink_sg_current_mode, _stlink_sg_force_debug, - NULL, /* target_voltage */ - NULL /* set_swdclk */ + NULL, // target_voltage + NULL // set_swdclk }; static stlink_t* stlink_open(const int verbose) { - stlink_t *sl = malloc(sizeof (stlink_t)); - struct stlink_libsg *slsg = malloc(sizeof (struct stlink_libsg)); + stlink_t *sl = malloc(sizeof(stlink_t)); + struct stlink_libsg *slsg = malloc(sizeof(struct stlink_libsg)); + if (sl == NULL || slsg == NULL) { WLOG("Couldn't malloc stlink and stlink_sg structures out of memory!\n"); - if (sl != NULL) - free(sl); - if (slsg != NULL) - free(slsg); - return NULL; + + if (sl != NULL) { free(sl); } + + if (slsg != NULL) { free(slsg); } + + return(NULL); } + memset(sl, 0, sizeof(stlink_t)); if (libusb_init(&(slsg->libusb_ctx))) { WLOG("failed to init libusb context, wrong version of libraries?\n"); free(sl); free(slsg); - return NULL; + return(NULL); } #if LIBUSB_API_VERSION < 0x01000106 @@ -944,32 +977,35 @@ static stlink_t* stlink_open(const int verbose) { #endif slsg->usb_handle = libusb_open_device_with_vid_pid(slsg->libusb_ctx, STLINK_USB_VID_ST, STLINK_USB_PID_STLINK); + if (slsg->usb_handle == NULL) { WLOG("Failed to find an stlink v1 by VID:PID\n"); libusb_close(slsg->usb_handle); libusb_exit(slsg->libusb_ctx); free(sl); free(slsg); - return NULL; + return(NULL); } - // TODO - // Could read the interface config descriptor, and assert lots of the assumptions + // TODO: Could read the interface config descriptor, and assert lots of the assumptions // assumption: numInterfaces is always 1... if (libusb_kernel_driver_active(slsg->usb_handle, 0) == 1) { int r = libusb_detach_kernel_driver(slsg->usb_handle, 0); + if (r < 0) { WLOG("libusb_detach_kernel_driver(() error %s\n", strerror(-r)); libusb_close(slsg->usb_handle); libusb_exit(slsg->libusb_ctx); free(sl); free(slsg); - return NULL; + return(NULL); } + DLOG("Kernel driver was successfully detached\n"); } int config; + if (libusb_get_configuration(slsg->usb_handle, &config)) { /* this may fail for a previous configured device */ WLOG("libusb_get_configuration()\n"); @@ -977,7 +1013,7 @@ static stlink_t* stlink_open(const int verbose) { libusb_exit(slsg->libusb_ctx); free(sl); free(slsg); - return NULL; + return(NULL); } @@ -985,6 +1021,7 @@ static stlink_t* stlink_open(const int verbose) { if (config != 1) { WLOG("Your stlink got into a real weird configuration, trying to fix it!\n"); DLOG("setting new configuration (%d -> 1)\n", config); + if (libusb_set_configuration(slsg->usb_handle, 1)) { /* this may fail for a previous configured device */ WLOG("libusb_set_configuration() failed\n"); @@ -992,7 +1029,7 @@ static stlink_t* stlink_open(const int verbose) { libusb_exit(slsg->libusb_ctx); free(sl); free(slsg); - return NULL; + return(NULL); } } @@ -1002,7 +1039,7 @@ static stlink_t* stlink_open(const int verbose) { libusb_exit(slsg->libusb_ctx); free(sl); free(slsg); - return NULL; + return(NULL); } // assumption: endpoint config is fixed mang. really. @@ -1018,31 +1055,34 @@ static stlink_t* stlink_open(const int verbose) { sl->core_stat = TARGET_UNKNOWN; slsg->q_addr = 0; - return sl; + return(sl); } stlink_t* stlink_v1_open_inner(const int verbose) { ugly_init(verbose); stlink_t *sl = stlink_open(verbose); + if (sl == NULL) { ELOG("Could not open stlink device\n"); - return NULL; + return(NULL); } stlink_version(sl); + if ((sl->version.st_vid != STLINK_USB_VID_ST) || (sl->version.stlink_pid != STLINK_USB_PID_STLINK)) { ELOG("WTF? successfully opened, but unable to read version details. BROKEN!\n"); - return NULL; + return(NULL); } DLOG("Reading current mode...\n"); + switch (stlink_current_mode(sl)) { case STLINK_DEV_MASS_MODE: - return sl; + return(sl); case STLINK_DEV_DEBUG_MODE: // TODO go to mass? - return sl; + return(sl); default: ILOG("Current mode unusable, trying to get back to a useful state...\n"); break; @@ -1053,26 +1093,27 @@ stlink_t* stlink_v1_open_inner(const int verbose) { // re-query device info (and retest) stlink_version(sl); + if ((sl->version.st_vid != STLINK_USB_VID_ST) || (sl->version.stlink_pid != STLINK_USB_PID_STLINK)) { ELOG("WTF? successfully opened, but unable to read version details. BROKEN!\n"); - return NULL; + return(NULL); } - return sl; + return(sl); } stlink_t* stlink_v1_open(const int verbose, int reset) { stlink_t *sl = stlink_v1_open_inner(verbose); - if (sl == NULL) - return NULL; + + if (sl == NULL) { return(NULL); } // by now, it _must_ be fully open and in a useful mode.... stlink_enter_swd_mode(sl); - /* Now we are ready to read the parameters */ - if (reset) { - stlink_reset(sl); - } + + // now we are ready to read the parameters + if (reset) { stlink_reset(sl); } + stlink_load_device_params(sl); ILOG("Successfully opened a stlink v1 debugger\n"); - return sl; + return(sl); } diff --git a/src/stlink-lib/sg.h b/src/stlink-lib/sg.h index 811b339c7..f34b2e122 100644 --- a/src/stlink-lib/sg.h +++ b/src/stlink-lib/sg.h @@ -1,8 +1,6 @@ /* * File: sg.h * Author: karl - * - * Created on October 1, 2011, 11:29 PM */ #ifndef STLINK_SG_H @@ -15,31 +13,28 @@ extern "C" { #endif - // device access -#define RDWR 0 -#define RO 1 -#define SG_TIMEOUT_SEC 1 // actually 1 is about 2 sec -#define SG_TIMEOUT_MSEC 3 * 1000 - // Each CDB can be a total of 6, 10, 12, or 16 bytes, later version - // of the SCSI standard also allow for variable-length CDBs (min. CDB is 6). - // the stlink needs max. 10 bytes. -#define CDB_6 6 -#define CDB_10 10 -#define CDB_12 12 -#define CDB_16 16 +/* Device access */ +#define RDWR 0 +#define RO 1 +#define SG_TIMEOUT_SEC 1 // actually 1 is about 2 sec +#define SG_TIMEOUT_MSEC 3 * 1000 -#define CDB_SL 10 +// Each CDB can be a total of 6, 10, 12, or 16 bytes, later version of the SCSI standard +// also allow for variable-length CDBs (min. CDB is 6). The stlink needs max. 10 bytes. +#define CDB_6 6 +#define CDB_10 10 +#define CDB_12 12 +#define CDB_16 16 - // Query data flow direction. -#define Q_DATA_OUT 0 -#define Q_DATA_IN 1 - - // The SCSI Request Sense command is used to obtain sense data - // (error information) from a target device. - // http://en.wikipedia.org/wiki/SCSI_Request_Sense_Command -#define SENSE_BUF_LEN 32 +#define CDB_SL 10 +/* Query data flow direction */ +#define Q_DATA_OUT 0 +#define Q_DATA_IN 1 +// The SCSI Request Sense command is used to obtain sense data (error information) from +// a target device. (http://en.wikipedia.org/wiki/SCSI_Request_Sense_Command) +#define SENSE_BUF_LEN 32 struct stlink_libsg { libusb_context* libusb_ctx; @@ -65,8 +60,8 @@ struct stlink_libsg { stlink_t* stlink_v1_open(const int verbose, int reset); -#ifdef __cplusplus +#ifdef __cplusplus } #endif -#endif /* STLINK_SG_H */ +#endif // STLINK_SG_H diff --git a/src/stlink-lib/usb.c b/src/stlink-lib/usb.c index c22f2fe5e..f9b4775f3 100644 --- a/src/stlink-lib/usb.c +++ b/src/stlink-lib/usb.c @@ -19,10 +19,10 @@ #include #include "usb.h" -enum SCSI_Generic_Direction {SG_DXFER_TO_DEV=0, SG_DXFER_FROM_DEV=0x80}; +enum SCSI_Generic_Direction {SG_DXFER_TO_DEV = 0, SG_DXFER_FROM_DEV = 0x80}; static inline uint32_t le_to_h_u32(const uint8_t* buf) { - return (uint32_t)((uint32_t)buf[0] | (uint32_t)buf[1] << 8 | (uint32_t)buf[2] << 16 | (uint32_t)buf[3] << 24); + return((uint32_t)((uint32_t)buf[0] | (uint32_t)buf[1] << 8 | (uint32_t)buf[2] << 16 | (uint32_t)buf[3] << 24)); } static int _stlink_match_speed_map(const uint32_t *map, unsigned int map_size, uint32_t khz) { @@ -33,15 +33,18 @@ static int _stlink_match_speed_map(const uint32_t *map, unsigned int map_size, u bool match = true; for (i = 0; i < map_size; i++) { - if (!map[i]) continue; + if (!map[i]) { continue; } + last_valid_speed = i; + if (khz == map[i]) { speed_index = i; break; } else { int current_diff = khz - map[i]; - // Get abs value for comparison + // get abs value for comparison current_diff = (current_diff > 0) ? current_diff : -current_diff; + if ((current_diff < speed_diff) && khz >= map[i]) { speed_diff = current_diff; speed_index = i; @@ -50,72 +53,80 @@ static int _stlink_match_speed_map(const uint32_t *map, unsigned int map_size, u } if (speed_index == -1) { - // This will only be here if we cannot match the slow speed. Use the slowest speed we support. + // This will only be here if we cannot match the slow speed. + // Use the slowest speed we support. speed_index = last_valid_speed; match = false; } else if (i == map_size) { match = false; } + if (!match) { ILOG("Unable to match requested speed %d kHz, using %d kHz\n", khz, map[speed_index]); } - return speed_index; + return(speed_index); } void _stlink_usb_close(stlink_t* sl) { - if (!sl) return; + if (!sl) { return; } struct stlink_libusb * const handle = sl->backend_data; - // Maybe we couldn't even get the usb device? + + // maybe we couldn't even get the usb device? if (handle != NULL) { - if (handle->usb_handle != NULL) libusb_close(handle->usb_handle); + if (handle->usb_handle != NULL) { libusb_close(handle->usb_handle); } + libusb_exit(handle->libusb_ctx); free(handle); } } ssize_t send_recv(struct stlink_libusb* handle, int terminate, - unsigned char* txbuf, size_t txsize, unsigned char* rxbuf, size_t rxsize) { - /* Note: txbuf and rxbuf can point to the same area */ + unsigned char* txbuf, size_t txsize, unsigned char* rxbuf, size_t rxsize) { + // Note: txbuf and rxbuf can point to the same area int res = 0; int t; - t = libusb_bulk_transfer(handle->usb_handle, handle->ep_req, txbuf, (int) txsize, &res, 3000); + t = libusb_bulk_transfer(handle->usb_handle, handle->ep_req, txbuf, (int)txsize, &res, 3000); + if (t) { printf("[!] send_recv send request failed: %s\n", libusb_error_name(t)); - return -1; + return(-1); } else if ((size_t)res != txsize) { printf("[!] send_recv send request wrote %u bytes (instead of %u).\n", - (unsigned int)res, (unsigned int)txsize); + (unsigned int)res, (unsigned int)txsize); } if (rxsize != 0) { - t = libusb_bulk_transfer(handle->usb_handle, handle->ep_rep, rxbuf, (int) rxsize, &res, 3000); + t = libusb_bulk_transfer(handle->usb_handle, handle->ep_rep, rxbuf, (int)rxsize, &res, 3000); + if (t) { printf("[!] send_recv read reply failed: %s\n", libusb_error_name(t)); - return -1; + return(-1); } } if ((handle->protocoll == 1) && terminate) { - // Read the SG reply + // read the SG reply unsigned char sg_buf[13]; t = libusb_bulk_transfer(handle->usb_handle, handle->ep_rep, sg_buf, 13, &res, 3000); + if (t) { printf("[!] send_recv read storage failed: %s\n", libusb_error_name(t)); - return -1; + return(-1); } + // The STLink doesn't seem to evaluate the sequence number. handle->sg_transfer_idx++; } - return res; + return(res); } static inline int send_only(struct stlink_libusb* handle, int terminate, - unsigned char* txbuf, size_t txsize) { - return (int) send_recv(handle, terminate, txbuf, txsize, NULL, 0); + unsigned char* txbuf, size_t txsize) { + return((int)send_recv(handle, terminate, txbuf, txsize, NULL, 0)); } @@ -123,7 +134,8 @@ static int fill_command(stlink_t * sl, enum SCSI_Generic_Direction dir, uint32_t struct stlink_libusb * const slu = sl->backend_data; unsigned char* const cmd = sl->c_buf; int i = 0; - memset(cmd, 0, sizeof (sl->c_buf)); + memset(cmd, 0, sizeof(sl->c_buf)); + if (slu->protocoll == 1) { cmd[i++] = 'U'; cmd[i++] = 'S'; @@ -133,10 +145,11 @@ static int fill_command(stlink_t * sl, enum SCSI_Generic_Direction dir, uint32_t write_uint32(&cmd[i + 4], len); i += 8; cmd[i++] = (dir == SG_DXFER_FROM_DEV) ? 0x80 : 0; - cmd[i++] = 0; // Logical unit - cmd[i++] = 0xa; // Command length + cmd[i++] = 0; // logical unit + cmd[i++] = 0xa; // command length } - return i; + + return(i); } int _stlink_usb_version(stlink_t *sl) { @@ -150,9 +163,10 @@ int _stlink_usb_version(stlink_t *sl) { cmd[i++] = STLINK_GET_VERSION; size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); + if (size == -1) { printf("[!] send_recv STLINK_GET_VERSION\n"); - return (int) size; + return((int)size); } /* STLINK-V3 requires a specific command */ @@ -162,13 +176,14 @@ int _stlink_usb_version(stlink_t *sl) { cmd[i++] = STLINK_APIV3_GET_VERSION_EX; size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); + if (size != (ssize_t)rep_len) { printf("[!] send_recv STLINK_APIV3_GET_VERSION_EX\n"); - return (int) size; + return((int)size); } } - return 0; + return(0); } int32_t _stlink_usb_target_voltage(stlink_t *sl) { @@ -184,19 +199,20 @@ int32_t _stlink_usb_target_voltage(stlink_t *sl) { cmd[i++] = STLINK_GET_TARGET_VOLTAGE; size = send_recv(slu, 1, cmd, slu->cmd_len, rdata, rep_len); + if (size == -1) { printf("[!] send_recv STLINK_GET_TARGET_VOLTAGE\n"); - return -1; + return(-1); } else if (size != 8) { printf("[!] wrong length STLINK_GET_TARGET_VOLTAGE\n"); - return -1; + return(-1); } factor = (rdata[3] << 24) | (rdata[2] << 16) | (rdata[1] << 8) | (rdata[0] << 0); reading = (rdata[7] << 24) | (rdata[6] << 16) | (rdata[5] << 8) | (rdata[4] << 0); voltage = 2400 * reading / factor; - return voltage; + return(voltage); } int _stlink_usb_read_debug32(stlink_t *sl, uint32_t addr, uint32_t *data) { @@ -211,13 +227,15 @@ int _stlink_usb_read_debug32(stlink_t *sl, uint32_t addr, uint32_t *data) { cmd[i++] = STLINK_JTAG_READDEBUG_32BIT; write_uint32(&cmd[i], addr); size = send_recv(slu, 1, cmd, slu->cmd_len, rdata, rep_len); + if (size == -1) { printf("[!] send_recv STLINK_JTAG_READDEBUG_32BIT\n"); - return (int) size; + return((int)size); } + *data = read_uint32(rdata, 4); - return 0; + return(0); } int _stlink_usb_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data) { @@ -233,16 +251,17 @@ int _stlink_usb_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data) { write_uint32(&cmd[i], addr); write_uint32(&cmd[i + 4], data); size = send_recv(slu, 1, cmd, slu->cmd_len, rdata, rep_len); + if (size == -1) { printf("[!] send_recv STLINK_JTAG_WRITEDEBUG_32BIT\n"); - return (int) size; + return((int)size); } - return 0; + return(0); } int _stlink_usb_get_rw_status(stlink_t *sl) { - if (sl->version.jtag_api == STLINK_JTAG_API_V1) return -1; + if (sl->version.jtag_api == STLINK_JTAG_API_V1) { return(-1); } unsigned char* const rdata = sl->q_buf; struct stlink_libusb * const slu = sl->backend_data; @@ -252,6 +271,7 @@ int _stlink_usb_get_rw_status(stlink_t *sl) { i = fill_command(sl, SG_DXFER_FROM_DEV, 12); cmd[i++] = STLINK_DEBUG_COMMAND; + if (sl->version.flags & STLINK_F_HAS_GETLASTRWSTATUS2) { cmd[i++] = STLINK_DEBUG_APIV2_GETLASTRWSTATUS2; ret = send_recv(slu, 1, cmd, slu->cmd_len, rdata, 12); @@ -259,9 +279,10 @@ int _stlink_usb_get_rw_status(stlink_t *sl) { cmd[i++] = STLINK_DEBUG_APIV2_GETLASTRWSTATUS; ret = send_recv(slu, 1, cmd, slu->cmd_len, rdata, 2); } - if (ret < 0) return -1; - return 0; + if (ret < 0) { return(-1); } + + return(0); } int _stlink_usb_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { @@ -276,11 +297,14 @@ int _stlink_usb_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { write_uint32(&cmd[i], addr); write_uint16(&cmd[i + 4], len); ret = send_only(slu, 0, cmd, slu->cmd_len); - if (ret == -1) return ret; + + if (ret == -1) { return(ret); } + ret = send_only(slu, 0, data, len); - if (ret == -1) return ret; - return _stlink_usb_get_rw_status(sl); + if (ret == -1) { return(ret); } + + return(_stlink_usb_get_rw_status(sl)); } int _stlink_usb_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len) { @@ -295,11 +319,14 @@ int _stlink_usb_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len) { write_uint32(&cmd[i], addr); write_uint16(&cmd[i + 4], len); ret = send_only(slu, 0, cmd, slu->cmd_len); - if (ret == -1) return ret; + + if (ret == -1) { return(ret); } + ret = send_only(slu, 1, data, len); - if (ret == -1) return ret; - return 0; + if (ret == -1) { return(ret); } + + return(0); } @@ -313,12 +340,13 @@ int _stlink_usb_current_mode(stlink_t * sl) { cmd[i++] = STLINK_GET_CURRENT_MODE; size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); + if (size == -1) { printf("[!] send_recv STLINK_GET_CURRENT_MODE\n"); - return -1; + return(-1); } - return sl->q_buf[0]; + return(sl->q_buf[0]); } int _stlink_usb_core_id(stlink_t * sl) { @@ -330,15 +358,18 @@ int _stlink_usb_core_id(stlink_t * sl) { int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); cmd[i++] = STLINK_DEBUG_COMMAND; + if (sl->version.jtag_api == STLINK_JTAG_API_V1) { cmd[i++] = STLINK_DEBUG_READCOREID; } else { cmd[i++] = STLINK_DEBUG_APIV2_READ_IDCODES; } + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); + if (size == -1) { printf("[!] send_recv STLINK_DEBUG_READCOREID\n"); - return -1; + return(-1); } if (sl->version.jtag_api == STLINK_JTAG_API_V1) { @@ -346,16 +377,18 @@ int _stlink_usb_core_id(stlink_t * sl) { } else { sl->core_id = read_uint32(data, 4); } - return 0; + + return(0); } -int _stlink_usb_status_v2(stlink_t *sl) -{ + +int _stlink_usb_status_v2(stlink_t *sl) { int result; uint32_t status = 0; result = _stlink_usb_read_debug32(sl, DCB_DHCSR, &status); DLOG("core status: %08X\n", status); - if (result != 0) { + + if (result != 0) { sl->core_stat = TARGET_UNKNOWN; } else { if (status & S_HALT) { @@ -367,11 +400,11 @@ int _stlink_usb_status_v2(stlink_t *sl) } } - return result; + return(result); } int _stlink_usb_status(stlink_t * sl) { - if (sl->version.jtag_api != STLINK_JTAG_API_V1) return _stlink_usb_status_v2(sl); + if (sl->version.jtag_api != STLINK_JTAG_API_V1) { return(_stlink_usb_status_v2(sl)); } struct stlink_libusb * const slu = sl->backend_data; unsigned char* const data = sl->q_buf; @@ -383,21 +416,25 @@ int _stlink_usb_status(stlink_t * sl) { cmd[i++] = STLINK_DEBUG_COMMAND; cmd[i++] = STLINK_DEBUG_GETSTATUS; size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); + if (size == -1) { printf("[!] send_recv STLINK_DEBUG_GETSTATUS\n"); - return (int) size; + return((int)size); } - sl->q_len = (int) size; + + sl->q_len = (int)size; + if (sl->q_len > 1) { - if (sl->q_buf[0] == STLINK_CORE_RUNNING) + if (sl->q_buf[0] == STLINK_CORE_RUNNING) { sl->core_stat = TARGET_RUNNING; - else if (sl->q_buf[0] == STLINK_CORE_HALTED) + } else if (sl->q_buf[0] == STLINK_CORE_HALTED) { sl->core_stat = TARGET_HALTED; - else + } else { sl->core_stat = TARGET_UNKNOWN; + } } - return 0; + return(0); } int _stlink_usb_force_debug(stlink_t *sl) { @@ -411,12 +448,13 @@ int _stlink_usb_force_debug(stlink_t *sl) { cmd[i++] = STLINK_DEBUG_COMMAND; cmd[i++] = STLINK_DEBUG_FORCEDEBUG; size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); + if (size == -1) { printf("[!] send_recv STLINK_DEBUG_FORCEDEBUG\n"); - return (int) size; + return((int)size); } - return 0; + return(0); } int _stlink_usb_enter_swd_mode(stlink_t * sl) { @@ -428,7 +466,7 @@ int _stlink_usb_enter_swd_mode(stlink_t * sl) { int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); cmd[i++] = STLINK_DEBUG_COMMAND; - // Select correct API-Version for entering SWD mode: V1 API (0x20) or V2 API (0x30). + // select correct API-Version for entering SWD mode: V1 API (0x20) or V2 API (0x30). cmd[i++] = sl->version.jtag_api == STLINK_JTAG_API_V1 ? STLINK_DEBUG_APIV1_ENTER : STLINK_DEBUG_APIV2_ENTER; cmd[i++] = STLINK_DEBUG_ENTER_SWD; @@ -437,12 +475,13 @@ int _stlink_usb_enter_swd_mode(stlink_t * sl) { } else { size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); } + if (size == -1) { printf("[!] send_recv STLINK_DEBUG_ENTER\n"); - return (int) size; + return((int)size); } - return 0; + return(0); } int _stlink_usb_exit_dfu_mode(stlink_t* sl) { @@ -454,12 +493,13 @@ int _stlink_usb_exit_dfu_mode(stlink_t* sl) { cmd[i++] = STLINK_DFU_COMMAND; cmd[i++] = STLINK_DFU_EXIT; size = send_only(slu, 1, cmd, slu->cmd_len); + if (size == -1) { printf("[!] send_recv STLINK_DFU_EXIT\n"); - return (int) size; + return((int)size); } - return 0; + return(0); } @@ -472,6 +512,7 @@ int _stlink_usb_reset(stlink_t * sl) { int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); cmd[i++] = STLINK_DEBUG_COMMAND; + if (sl->version.jtag_api == STLINK_JTAG_API_V1) { cmd[i++] = STLINK_DEBUG_APIV1_RESETSYS; } else { @@ -479,14 +520,15 @@ int _stlink_usb_reset(stlink_t * sl) { } size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); + if (size == -1) { printf("[!] send_recv STLINK_DEBUG_RESETSYS\n"); - return (int) size; + return((int)size); } - // Reset through AIRCR so that NRST does not need to be connected. - return stlink_write_debug32(sl, STLINK_REG_AIRCR, STLINK_REG_AIRCR_VECTKEY | - STLINK_REG_AIRCR_SYSRESETREQ); + // reset through AIRCR so that NRST does not need to be connected + return(stlink_write_debug32(sl, STLINK_REG_AIRCR, STLINK_REG_AIRCR_VECTKEY | + STLINK_REG_AIRCR_SYSRESETREQ)); } int _stlink_usb_jtag_reset(stlink_t * sl, int value) { @@ -501,12 +543,13 @@ int _stlink_usb_jtag_reset(stlink_t * sl, int value) { cmd[i++] = STLINK_JTAG_DRIVE_NRST; cmd[i++] = value; size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); + if (size == -1) { printf("[!] send_recv STLINK_JTAG_DRIVE_NRST\n"); - return (int) size; + return((int)size); } - return 0; + return(0); } @@ -521,12 +564,13 @@ int _stlink_usb_step(stlink_t* sl) { cmd[i++] = STLINK_DEBUG_COMMAND; cmd[i++] = STLINK_DEBUG_STEPCORE; size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); + if (size == -1) { printf("[!] send_recv STLINK_DEBUG_STEPCORE\n"); - return (int) size; + return((int)size); } - return 0; + return(0); } /** @@ -539,8 +583,8 @@ int _stlink_usb_run(stlink_t* sl) { int res; if (sl->version.jtag_api != STLINK_JTAG_API_V1) { - res = _stlink_usb_write_debug32(sl, DCB_DHCSR, DBGKEY|C_DEBUGEN); - return res; + res = _stlink_usb_write_debug32(sl, DCB_DHCSR, DBGKEY | C_DEBUGEN); + return(res); } @@ -553,15 +597,15 @@ int _stlink_usb_run(stlink_t* sl) { cmd[i++] = STLINK_DEBUG_COMMAND; cmd[i++] = STLINK_DEBUG_RUNCORE; size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); + if (size == -1) { printf("[!] send_recv STLINK_DEBUG_RUNCORE\n"); - return (int) size; + return((int)size); } - return 0; + return(0); } - int _stlink_usb_set_swdclk(stlink_t* sl, uint16_t clk_divisor) { struct stlink_libusb * const slu = sl->backend_data; unsigned char* const data = sl->q_buf; @@ -579,12 +623,13 @@ int _stlink_usb_set_swdclk(stlink_t* sl, uint16_t clk_divisor) { cmd[i++] = clk_divisor & 0xFF; cmd[i++] = (clk_divisor >> 8) & 0xFF; size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); + if (size == -1) { printf("[!] send_recv STLINK_DEBUG_APIV2_SWD_SET_FREQ\n"); - return (int) size; + return((int)size); } - return 0; + return(0); } else if (sl->version.stlink_v == 3) { int speed_index; uint32_t map[STLINK_V3_MAX_FREQ_NB]; @@ -594,14 +639,17 @@ int _stlink_usb_set_swdclk(stlink_t* sl, uint16_t clk_divisor) { cmd[i++] = STLINK_APIV3_GET_COM_FREQ; cmd[i++] = 0; // SWD mode size = send_recv(slu, 1, cmd, slu->cmd_len, data, 52); + if (size == -1) { printf("[!] send_recv STLINK_APIV3_GET_COM_FREQ\n"); - return (int) size; + return((int)size); } int speeds_size = data[8]; - if (speeds_size > STLINK_V3_MAX_FREQ_NB) speeds_size = STLINK_V3_MAX_FREQ_NB; + if (speeds_size > STLINK_V3_MAX_FREQ_NB) { + speeds_size = STLINK_V3_MAX_FREQ_NB; + } for (i = 0; i < speeds_size; i++) map[i] = le_to_h_u32(&data[12 + 4 * i]); @@ -622,14 +670,16 @@ int _stlink_usb_set_swdclk(stlink_t* sl, uint16_t clk_divisor) { cmd[i++] = (uint8_t)((map[speed_index] >> 24) & 0xFF); size = send_recv(slu, 1, cmd, slu->cmd_len, data, 8); + if (size == -1) { printf("[!] send_recv STLINK_APIV3_SET_COM_FREQ\n"); - return (int) size; + return((int)size); } - return 0; + return(0); } - return -1; + + return(-1); } int _stlink_usb_exit_debug_mode(stlink_t *sl) { @@ -642,12 +692,13 @@ int _stlink_usb_exit_debug_mode(stlink_t *sl) { cmd[i++] = STLINK_DEBUG_EXIT; size = send_only(slu, 1, cmd, slu->cmd_len); + if (size == -1) { printf("[!] send_only STLINK_DEBUG_EXIT\n"); - return (int) size; + return((int)size); } - return 0; + return(0); } int _stlink_usb_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { @@ -665,13 +716,13 @@ int _stlink_usb_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { if (size == -1) { printf("[!] send_recv STLINK_DEBUG_READMEM_32BIT\n"); - return (int) size; + return((int)size); } - sl->q_len = (int) size; + sl->q_len = (int)size; stlink_print_data(sl); - return 0; + return(0); } int _stlink_usb_read_all_regs(stlink_t *sl, struct stlink_reg *regp) { @@ -694,23 +745,24 @@ int _stlink_usb_read_all_regs(stlink_t *sl, struct stlink_reg *regp) { if (size == -1) { printf("[!] send_recv STLINK_DEBUG_READALLREGS\n"); - return (int) size; + return((int)size); } /* V1: regs data from offset 0 */ /* V2: status at offset 0, regs data from offset 4 */ int reg_offset = sl->version.jtag_api == STLINK_JTAG_API_V1 ? 0 : 4; - sl->q_len = (int) size; + sl->q_len = (int)size; stlink_print_data(sl); - for(i=reg_offset; i<16; i++) regp->r[i]= read_uint32(sl->q_buf, i*4); + for (i = reg_offset; i < 16; i++) regp->r[i] = read_uint32(sl->q_buf, i * 4); + regp->xpsr = read_uint32(sl->q_buf, reg_offset + 64); regp->main_sp = read_uint32(sl->q_buf, reg_offset + 68); regp->process_sp = read_uint32(sl->q_buf, reg_offset + 72); regp->rw = read_uint32(sl->q_buf, reg_offset + 76); regp->rw2 = read_uint32(sl->q_buf, reg_offset + 80); - if (sl->verbose < 2) return 0; + if (sl->verbose < 2) { return(0); } DLOG("xpsr = 0x%08x\n", read_uint32(sl->q_buf, reg_offset + 64)); DLOG("main_sp = 0x%08x\n", read_uint32(sl->q_buf, reg_offset + 68)); @@ -718,7 +770,7 @@ int _stlink_usb_read_all_regs(stlink_t *sl, struct stlink_reg *regp) { DLOG("rw = 0x%08x\n", read_uint32(sl->q_buf, reg_offset + 76)); DLOG("rw2 = 0x%08x\n", read_uint32(sl->q_buf, reg_offset + 80)); - return 0; + return(0); } int _stlink_usb_read_reg(stlink_t *sl, int r_idx, struct stlink_reg *regp) { @@ -739,15 +791,15 @@ int _stlink_usb_read_reg(stlink_t *sl, int r_idx, struct stlink_reg *regp) { cmd[i++] = STLINK_DEBUG_APIV2_READREG; } - cmd[i++] = (uint8_t) r_idx; + cmd[i++] = (uint8_t)r_idx; size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); if (size == -1) { printf("[!] send_recv STLINK_DEBUG_READREG\n"); - return (int) size; + return((int)size); } - sl->q_len = (int) size; + sl->q_len = (int)size; stlink_print_data(sl); r = read_uint32(sl->q_buf, reg_offset); DLOG("r_idx (%2d) = 0x%08x\n", r_idx, r); @@ -772,7 +824,7 @@ int _stlink_usb_read_reg(stlink_t *sl, int r_idx, struct stlink_reg *regp) { regp->r[r_idx] = r; } - return 0; + return(0); } /* See section C1.6 of the ARMv7-M Architecture Reference Manual */ @@ -780,89 +832,96 @@ int _stlink_usb_read_unsupported_reg(stlink_t *sl, int r_idx, struct stlink_reg uint32_t r; int ret; - sl->q_buf[0] = (unsigned char) r_idx; + sl->q_buf[0] = (unsigned char)r_idx; + for (int i = 1; i < 4; i++) sl->q_buf[i] = 0; ret = _stlink_usb_write_mem32(sl, STLINK_REG_DCRSR, 4); - if (ret == -1) return ret; + + if (ret == -1) { return(ret); } ret = _stlink_usb_read_mem32(sl, STLINK_REG_DCRDR, 4); - if (ret == -1) return ret; + + if (ret == -1) { return(ret); } r = read_uint32(sl->q_buf, 0); DLOG("r_idx (%2d) = 0x%08x\n", r_idx, r); switch (r_idx) { - case 0x14: - regp->primask = (uint8_t) (r & 0xFF); - regp->basepri = (uint8_t) ((r>>8) & 0xFF); - regp->faultmask = (uint8_t) ((r>>16) & 0xFF); - regp->control = (uint8_t) ((r>>24) & 0xFF); - break; - case 0x21: - regp->fpscr = r; - break; - default: - regp->s[r_idx - 0x40] = r; - break; + case 0x14: + regp->primask = (uint8_t)(r & 0xFF); + regp->basepri = (uint8_t)((r >> 8) & 0xFF); + regp->faultmask = (uint8_t)((r >> 16) & 0xFF); + regp->control = (uint8_t)((r >> 24) & 0xFF); + break; + case 0x21: + regp->fpscr = r; + break; + default: + regp->s[r_idx - 0x40] = r; + break; } - return 0; + return(0); } int _stlink_usb_read_all_unsupported_regs(stlink_t *sl, struct stlink_reg *regp) { int ret; ret = _stlink_usb_read_unsupported_reg(sl, 0x14, regp); - if (ret == -1) return ret; + + if (ret == -1) { return(ret); } ret = _stlink_usb_read_unsupported_reg(sl, 0x21, regp); - if (ret == -1) return ret; + + if (ret == -1) { return(ret); } for (int i = 0; i < 32; i++) { - ret = _stlink_usb_read_unsupported_reg(sl, 0x40+i, regp); - if (ret == -1) return ret; + ret = _stlink_usb_read_unsupported_reg(sl, 0x40 + i, regp); + + if (ret == -1) { return(ret); } } - return 0; + return(0); } /* See section C1.6 of the ARMv7-M Architecture Reference Manual */ int _stlink_usb_write_unsupported_reg(stlink_t *sl, uint32_t val, int r_idx, struct stlink_reg *regp) { int ret; - if (r_idx >= 0x1C && r_idx <= 0x1F) { /* primask, basepri, faultmask, or control */ + if (r_idx >= 0x1C && r_idx <= 0x1F) { // primask, basepri, faultmask, or control /* These are held in the same register */ ret = _stlink_usb_read_unsupported_reg(sl, 0x14, regp); - if (ret == -1) return ret; - val = (uint8_t) (val>>24); + if (ret == -1) { return(ret); } + + val = (uint8_t)(val >> 24); switch (r_idx) { - case 0x1C: /* control */ - val = (((uint32_t) val) << 24) | - (((uint32_t) regp->faultmask) << 16) | - (((uint32_t) regp->basepri) << 8) | - ((uint32_t) regp->primask); - break; - case 0x1D: /* faultmask */ - val = (((uint32_t) regp->control) << 24) | - (((uint32_t) val) << 16) | - (((uint32_t) regp->basepri) << 8) | - ((uint32_t) regp->primask); - break; - case 0x1E: /* basepri */ - val = (((uint32_t) regp->control) << 24) | - (((uint32_t) regp->faultmask) << 16) | - (((uint32_t) val) << 8) | - ((uint32_t) regp->primask); - break; - case 0x1F: /* primask */ - val = (((uint32_t) regp->control) << 24) | - (((uint32_t) regp->faultmask) << 16) | - (((uint32_t) regp->basepri) << 8) | - ((uint32_t) val); - break; + case 0x1C: /* control */ + val = (((uint32_t)val) << 24) | + (((uint32_t)regp->faultmask) << 16) | + (((uint32_t)regp->basepri) << 8) | + ((uint32_t)regp->primask); + break; + case 0x1D: /* faultmask */ + val = (((uint32_t)regp->control) << 24) | + (((uint32_t)val) << 16) | + (((uint32_t)regp->basepri) << 8) | + ((uint32_t)regp->primask); + break; + case 0x1E: /* basepri */ + val = (((uint32_t)regp->control) << 24) | + (((uint32_t)regp->faultmask) << 16) | + (((uint32_t)val) << 8) | + ((uint32_t)regp->primask); + break; + case 0x1F: /* primask */ + val = (((uint32_t)regp->control) << 24) | + (((uint32_t)regp->faultmask) << 16) | + (((uint32_t)regp->basepri) << 8) | + ((uint32_t)val); + break; } r_idx = 0x14; @@ -871,14 +930,15 @@ int _stlink_usb_write_unsupported_reg(stlink_t *sl, uint32_t val, int r_idx, str write_uint32(sl->q_buf, val); ret = _stlink_usb_write_mem32(sl, STLINK_REG_DCRDR, 4); - if (ret == -1) return ret; - sl->q_buf[0] = (unsigned char) r_idx; + if (ret == -1) { return(ret); } + + sl->q_buf[0] = (unsigned char)r_idx; sl->q_buf[1] = 0; sl->q_buf[2] = 0x01; sl->q_buf[3] = 0; - return _stlink_usb_write_mem32(sl, STLINK_REG_DCRSR, 4); + return(_stlink_usb_write_mem32(sl, STLINK_REG_DCRSR, 4)); } int _stlink_usb_write_reg(stlink_t *sl, uint32_t reg, int idx) { @@ -903,19 +963,20 @@ int _stlink_usb_write_reg(stlink_t *sl, uint32_t reg, int idx) { if (size == -1) { printf("[!] send_recv STLINK_DEBUG_WRITEREG\n"); - return (int) size; + return((int)size); } - sl->q_len = (int) size; + + sl->q_len = (int)size; stlink_print_data(sl); - return 0; + return(0); } static stlink_backend_t _stlink_usb_backend = { _stlink_usb_close, _stlink_usb_exit_debug_mode, _stlink_usb_enter_swd_mode, - NULL, // no enter_jtag_mode here... + NULL, // don't enter_jtag_mode here... _stlink_usb_exit_dfu_mode, _stlink_usb_core_id, _stlink_usb_reset, @@ -947,17 +1008,19 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, int reset, char serial[STL int ret = -1; int config; - sl = calloc(1, sizeof (stlink_t)); - slu = calloc(1, sizeof (struct stlink_libusb)); + sl = calloc(1, sizeof(stlink_t)); + slu = calloc(1, sizeof(struct stlink_libusb)); - if (sl == NULL) goto on_malloc_error; - if (slu == NULL) goto on_malloc_error; + if (sl == NULL) { goto on_malloc_error; } + + if (slu == NULL) { goto on_malloc_error; } ugly_init(verbose); sl->backend = &_stlink_usb_backend; sl->backend_data = slu; sl->core_stat = TARGET_UNKNOWN; + if (libusb_init(&(slu->libusb_ctx))) { WLOG("failed to init libusb context, wrong version of libraries?\n"); goto on_error; @@ -970,53 +1033,58 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, int reset, char serial[STL #endif libusb_device **list; - /* @TODO: We should use ssize_t and use it as a counter if > 0. - * As per libusb API: ssize_t libusb_get_device_list (libusb_context *ctx, libusb_device ***list) - */ - int cnt = (int) libusb_get_device_list(slu->libusb_ctx, &list); + // TODO: We should use ssize_t and use it as a counter if > 0. + // As per libusb API: ssize_t libusb_get_device_list (libusb_context *ctx, libusb_device ***list) + int cnt = (int)libusb_get_device_list(slu->libusb_ctx, &list); struct libusb_device_descriptor desc; int devBus = 0; int devAddr = 0; - /* @TODO: Reading a environment variable in a usb open function is not very nice, this should be refactored - * and moved into the CLI tools, and instead of giving USB_BUS:USB_ADDR a real stlink serial string should - * be passed to this function. Probably people are using this but this is very odd because as programmer - * can change to multiple busses and it is better to detect them based on serial. - */ + // TODO: Reading a environment variable in a usb open function is not very nice, this should + // be refactored and moved into the CLI tools, and instead of giving USB_BUS:USB_ADDR a real + // stlink serial string should be passed to this function. Probably people are using this + // but this is very odd because as programmer can change to multiple busses and it is better + // to detect them based on serial. char *device = getenv("STLINK_DEVICE"); + if (device) { - char *c = strchr(device,':'); + char *c = strchr(device, ':'); + if (c == NULL) { WLOG("STLINK_DEVICE must be : format\n"); goto on_error; } + devBus = atoi(device); *c++ = 0; devAddr = atoi(c); - ILOG("bus %03d dev %03d\n",devBus, devAddr); + ILOG("bus %03d dev %03d\n", devBus, devAddr); } while (cnt--) { struct libusb_device_handle *handle; libusb_get_device_descriptor(list[cnt], &desc); - if (desc.idVendor != STLINK_USB_VID_ST) continue; + + if (desc.idVendor != STLINK_USB_VID_ST) { continue; } if (devBus && devAddr) { - if ((libusb_get_bus_number(list[cnt]) != devBus) || (libusb_get_device_address(list[cnt]) != devAddr)) { + if ((libusb_get_bus_number(list[cnt]) != devBus) || + (libusb_get_device_address(list[cnt]) != devAddr)) { continue; } } ret = libusb_open(list[cnt], &handle); - if (ret) continue; // could not open device + + if (ret) { continue; } // could not open device sl->serial_size = libusb_get_string_descriptor_ascii( - handle, desc.iSerialNumber, (unsigned char *)sl->serial, sizeof(sl->serial)); + handle, desc.iSerialNumber, (unsigned char *)sl->serial, sizeof(sl->serial)); libusb_close(handle); - if (sl->serial_size < 0) continue; // could not read serial + if (sl->serial_size < 0) { continue; } // could not read serial // if no serial provided, or if serial match device, fixup version and protocol if (((serial == NULL) || (*serial == 0)) || (memcmp(serial, &sl->serial, sl->serial_size) == 0)) { @@ -1028,18 +1096,23 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, int reset, char serial[STL } else if (STLINK_V3_USB_PID(desc.idProduct)) { sl->version.stlink_v = 3; } + break; } } if (cnt < 0) { - WLOG ("Couldn't find %s ST-Link devices\n", (devBus && devAddr) ? "matched":"any"); + WLOG ("Couldn't find %s ST-Link devices\n", (devBus && devAddr) ? "matched" : "any"); goto on_error; } else { ret = libusb_open(list[cnt], &slu->usb_handle); + if (ret != 0) { - WLOG("Error %d (%s) opening ST-Link v%d device %03d:%03d\n", ret, strerror (errno), - sl->version.stlink_v, libusb_get_bus_number(list[cnt]), libusb_get_device_address(list[cnt])); + WLOG("Error %d (%s) opening ST-Link v%d device %03d:%03d\n", ret, + strerror(errno), + sl->version.stlink_v, + libusb_get_bus_number(list[cnt]), + libusb_get_device_address(list[cnt])); libusb_free_device_list(list, 1); goto on_error; } @@ -1049,6 +1122,7 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, int reset, char serial[STL if (libusb_kernel_driver_active(slu->usb_handle, 0) == 1) { ret = libusb_detach_kernel_driver(slu->usb_handle, 0); + if (ret < 0) { WLOG("libusb_detach_kernel_driver(() error %s\n", strerror(-ret)); goto on_libusb_error; @@ -1056,15 +1130,16 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, int reset, char serial[STL } if (libusb_get_configuration(slu->usb_handle, &config)) { - /* this may fail for a previous configured device */ + // this may fail for a previous configured device WLOG("libusb_get_configuration()\n"); goto on_libusb_error; } if (config != 1) { printf("setting new configuration (%d -> 1)\n", config); + if (libusb_set_configuration(slu->usb_handle, 1)) { - /* this may fail for a previous configured device */ + // this may fail for a previous configured device WLOG("libusb_set_configuration() failed\n"); goto on_libusb_error; } @@ -1075,8 +1150,9 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, int reset, char serial[STL goto on_libusb_error; } - // TODO - could use the scanning techniq from stm8 code here... + // TODO: Could use the scanning technique from STM8 code here... slu->ep_rep = 1 /* ep rep */ | LIBUSB_ENDPOINT_IN; + if (desc.idProduct == STLINK_USB_PID_STLINK_NUCLEO || desc.idProduct == STLINK_USB_PID_STLINK_32L_AUDIO || desc.idProduct == STLINK_USB_PID_STLINK_V2_1 || @@ -1090,17 +1166,14 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, int reset, char serial[STL } slu->sg_transfer_idx = 0; - slu->cmd_len = (slu->protocoll == 1) ? STLINK_SG_SIZE: STLINK_CMD_SIZE; + slu->cmd_len = (slu->protocoll == 1) ? STLINK_SG_SIZE : STLINK_CMD_SIZE; - // Initialize stlink version (sl->version) - stlink_version(sl); - - // Initialize stlink version (sl->version) + // initialize stlink version (sl->version) stlink_version(sl); if (stlink_current_mode(sl) == STLINK_DEV_DFU_MODE) { - // This seems to work, and is unnecessary information for the user. - // Demoted to debug -- REW + // this seems to work, and is unnecessary information for the user. + // demoted to debug -- REW DLOG("-- exit_dfu_mode\n"); stlink_exit_dfu_mode(sl); } @@ -1108,78 +1181,86 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, int reset, char serial[STL sl->freq = freq; // set the speed before entering the mode as the chip discovery phase // should be done at this speed too - // Set the stlink clock speed (default is 1800kHz) + // set the stlink clock speed (default is 1800kHz) DLOG("JTAG/SWD freq set to %d\n", freq); + switch (freq) { - case 5: - stlink_set_swdclk(sl, STLINK_SWDCLK_5KHZ_DIVISOR); - break; - case 15: - stlink_set_swdclk(sl, STLINK_SWDCLK_15KHZ_DIVISOR); - break; - case 25: - stlink_set_swdclk(sl, STLINK_SWDCLK_25KHZ_DIVISOR); - break; - case 50: - stlink_set_swdclk(sl, STLINK_SWDCLK_50KHZ_DIVISOR); - break; - case 100: - stlink_set_swdclk(sl, STLINK_SWDCLK_100KHZ_DIVISOR); - break; - case 125: - stlink_set_swdclk(sl, STLINK_SWDCLK_125KHZ_DIVISOR); - break; - case 240: - stlink_set_swdclk(sl, STLINK_SWDCLK_240KHZ_DIVISOR); - break; - case 480: - stlink_set_swdclk(sl, STLINK_SWDCLK_480KHZ_DIVISOR); - break; - case 950: - stlink_set_swdclk(sl, STLINK_SWDCLK_950KHZ_DIVISOR); - break; - case 1200: - stlink_set_swdclk(sl, STLINK_SWDCLK_1P2MHZ_DIVISOR); - break; - case 0: case 1800: - stlink_set_swdclk(sl, STLINK_SWDCLK_1P8MHZ_DIVISOR); - break; - case 4000: - stlink_set_swdclk(sl, STLINK_SWDCLK_4MHZ_DIVISOR); - break; + case 5: + stlink_set_swdclk(sl, STLINK_SWDCLK_5KHZ_DIVISOR); + break; + case 15: + stlink_set_swdclk(sl, STLINK_SWDCLK_15KHZ_DIVISOR); + break; + case 25: + stlink_set_swdclk(sl, STLINK_SWDCLK_25KHZ_DIVISOR); + break; + case 50: + stlink_set_swdclk(sl, STLINK_SWDCLK_50KHZ_DIVISOR); + break; + case 100: + stlink_set_swdclk(sl, STLINK_SWDCLK_100KHZ_DIVISOR); + break; + case 125: + stlink_set_swdclk(sl, STLINK_SWDCLK_125KHZ_DIVISOR); + break; + case 240: + stlink_set_swdclk(sl, STLINK_SWDCLK_240KHZ_DIVISOR); + break; + case 480: + stlink_set_swdclk(sl, STLINK_SWDCLK_480KHZ_DIVISOR); + break; + case 950: + stlink_set_swdclk(sl, STLINK_SWDCLK_950KHZ_DIVISOR); + break; + case 1200: + stlink_set_swdclk(sl, STLINK_SWDCLK_1P2MHZ_DIVISOR); + break; + case 0: case 1800: + stlink_set_swdclk(sl, STLINK_SWDCLK_1P8MHZ_DIVISOR); + break; + case 4000: + stlink_set_swdclk(sl, STLINK_SWDCLK_4MHZ_DIVISOR); + break; } if (reset == 2) { - stlink_jtag_reset(sl,0); - if (stlink_current_mode(sl) != STLINK_DEV_DEBUG_MODE) stlink_enter_swd_mode(sl); - stlink_force_debug(sl); - stlink_jtag_reset(sl,1); - usleep(10000); + stlink_jtag_reset(sl, 0); + + if (stlink_current_mode(sl) != STLINK_DEV_DEBUG_MODE) { stlink_enter_swd_mode(sl); } + + stlink_force_debug(sl); + stlink_jtag_reset(sl, 1); + usleep(10000); } - if (stlink_current_mode(sl) != STLINK_DEV_DEBUG_MODE) stlink_enter_swd_mode(sl); + if (stlink_current_mode(sl) != STLINK_DEV_DEBUG_MODE) { stlink_enter_swd_mode(sl); } if (reset == 1) { - if ( sl->version.stlink_v > 1) stlink_jtag_reset(sl, 2); + if ( sl->version.stlink_v > 1) { stlink_jtag_reset(sl, 2); } + stlink_reset(sl); usleep(10000); } stlink_load_device_params(sl); - return sl; + return(sl); + +on_libusb_error: + stlink_close(sl); + return(NULL); - on_libusb_error: - stlink_close(sl); - return NULL; +on_error: - on_error: - if (slu->libusb_ctx) libusb_exit(slu->libusb_ctx); + if (slu->libusb_ctx) { libusb_exit(slu->libusb_ctx); } - on_malloc_error: - if (sl != NULL) free(sl); - if (slu != NULL) free(slu); - return NULL; +on_malloc_error: + + if (sl != NULL) { free(sl); } + + if (slu != NULL) { free(slu); } + + return(NULL); } static size_t stlink_probe_usb_devs(libusb_device **devs, stlink_t **sldevs[]) { @@ -1189,7 +1270,7 @@ static size_t stlink_probe_usb_devs(libusb_device **devs, stlink_t **sldevs[]) { size_t slcnt = 0; size_t slcur = 0; - /* Count stlink */ + /* Count STLINKs */ while ((dev = devs[i++]) != NULL) { struct libusb_device_descriptor desc; int ret = libusb_get_device_descriptor(dev, &desc); @@ -1199,7 +1280,7 @@ static size_t stlink_probe_usb_devs(libusb_device **devs, stlink_t **sldevs[]) { break; } - if (desc.idVendor != STLINK_USB_VID_ST) continue; + if (desc.idVendor != STLINK_USB_VID_ST) { continue; } if (!STLINK_SUPPORTED_USB_PID(desc.idProduct)) { WLOG("skipping ST device : %#04x:%#04x)\n", desc.idVendor, desc.idProduct); @@ -1209,15 +1290,16 @@ static size_t stlink_probe_usb_devs(libusb_device **devs, stlink_t **sldevs[]) { slcnt++; } - /* Allocate list of pointers */ - _sldevs = calloc(slcnt, sizeof(stlink_t *)); + _sldevs = calloc(slcnt, sizeof(stlink_t *)); // allocate list of pointers + if (!_sldevs) { *sldevs = NULL; - return 0; + return(0); } - /* Open stlinks and attach to list */ + /* Open STLINKS and attach them to list */ i = 0; + while ((dev = devs[i++]) != NULL) { struct libusb_device_descriptor desc; int ret = libusb_get_device_descriptor(dev, &desc); @@ -1227,10 +1309,10 @@ static size_t stlink_probe_usb_devs(libusb_device **devs, stlink_t **sldevs[]) { break; } - if (!STLINK_SUPPORTED_USB_PID(desc.idProduct)) continue; + if (!STLINK_SUPPORTED_USB_PID(desc.idProduct)) { continue; } struct libusb_device_handle* handle; - char serial[STLINK_SERIAL_MAX_SIZE] = {0,}; + char serial[STLINK_SERIAL_MAX_SIZE] = {0, }; ret = libusb_open(dev, &handle); @@ -1240,15 +1322,18 @@ static size_t stlink_probe_usb_devs(libusb_device **devs, stlink_t **sldevs[]) { } else { ELOG("Failed to open USB device %#06x:%#06x, libusb error: %d)\n", desc.idVendor, desc.idProduct, ret); } + break; } + ret = libusb_get_string_descriptor_ascii(handle, desc.iSerialNumber, (unsigned char *)&serial, sizeof(serial)); libusb_close(handle); - if (ret < 0) continue; + if (ret < 0) { continue; } stlink_t *sl = stlink_open_usb(0, 1, serial, 0); + if (!sl) { ELOG("Failed to open USB device %#06x:%#06x\n", desc.idVendor, desc.idProduct); continue; @@ -1259,7 +1344,7 @@ static size_t stlink_probe_usb_devs(libusb_device **devs, stlink_t **sldevs[]) { *sldevs = _sldevs; - return slcur; + return(slcur); } size_t stlink_probe_usb(stlink_t **stdevs[]) { @@ -1271,10 +1356,12 @@ size_t stlink_probe_usb(stlink_t **stdevs[]) { ssize_t cnt; r = libusb_init(NULL); - if (r < 0) return 0; + + if (r < 0) { return(0); } cnt = libusb_get_device_list(NULL, &devs); - if (cnt < 0) return 0; + + if (cnt < 0) { return(0); } slcnt = stlink_probe_usb_devs(devs, &sldevs); libusb_free_device_list(devs, 1); @@ -1283,12 +1370,14 @@ size_t stlink_probe_usb(stlink_t **stdevs[]) { *stdevs = sldevs; - return slcnt; + return(slcnt); } void stlink_probe_usb_free(stlink_t ***stdevs, size_t size) { - if (stdevs == NULL || *stdevs == NULL || size == 0) return; - for (size_t n = 0; n < size; n++) stlink_close((*stdevs)[n]); + if (stdevs == NULL || *stdevs == NULL || size == 0) { return; } + + for (size_t n = 0; n < size; n++) { stlink_close((*stdevs)[n]); } + free(*stdevs); *stdevs = NULL; } diff --git a/src/stlink-lib/usb.h b/src/stlink-lib/usb.h index 3581eabf1..d11f17381 100644 --- a/src/stlink-lib/usb.h +++ b/src/stlink-lib/usb.h @@ -1,8 +1,6 @@ /* * File: usb.h * Author: karl - * - * Created on October 1, 2011, 11:29 PM */ #ifndef STLINK_USB_H @@ -29,51 +27,51 @@ extern "C" { #define STLINK_USB_PID_STLINK_V3S_PID 0x374f #define STLINK_USB_PID_STLINK_V3_2VCP_PID 0x3753 -#define STLINK_V1_USB_PID(pid) ((pid) == STLINK_USB_PID_STLINK ) +#define STLINK_V1_USB_PID(pid) ((pid) == STLINK_USB_PID_STLINK) #define STLINK_V2_USB_PID(pid) ((pid) == STLINK_USB_PID_STLINK_32L || \ - (pid) == STLINK_USB_PID_STLINK_32L_AUDIO || \ - (pid) == STLINK_USB_PID_STLINK_NUCLEO) + (pid) == STLINK_USB_PID_STLINK_32L_AUDIO || \ + (pid) == STLINK_USB_PID_STLINK_NUCLEO) -#define STLINK_V2_1_USB_PID(pid) ( (pid) == STLINK_USB_PID_STLINK_V2_1 ) +#define STLINK_V2_1_USB_PID(pid) ((pid) == STLINK_USB_PID_STLINK_V2_1) #define STLINK_V3_USB_PID(pid) ((pid) == STLINK_USB_PID_STLINK_V3_USBLOADER || \ - (pid) == STLINK_USB_PID_STLINK_V3E_PID || \ - (pid) == STLINK_USB_PID_STLINK_V3S_PID || \ - (pid) == STLINK_USB_PID_STLINK_V3_2VCP_PID ) + (pid) == STLINK_USB_PID_STLINK_V3E_PID || \ + (pid) == STLINK_USB_PID_STLINK_V3S_PID || \ + (pid) == STLINK_USB_PID_STLINK_V3_2VCP_PID) -#define STLINK_SUPPORTED_USB_PID(pid) ( STLINK_V1_USB_PID(pid) || \ - STLINK_V2_USB_PID(pid) || \ - STLINK_V2_1_USB_PID(pid) || \ - STLINK_V3_USB_PID(pid)) +#define STLINK_SUPPORTED_USB_PID(pid) (STLINK_V1_USB_PID(pid) || \ + STLINK_V2_USB_PID(pid) || \ + STLINK_V2_1_USB_PID(pid) || \ + STLINK_V3_USB_PID(pid)) #define STLINK_SG_SIZE 31 #define STLINK_CMD_SIZE 16 - struct stlink_libusb { - libusb_context* libusb_ctx; - libusb_device_handle* usb_handle; - unsigned int ep_req; - unsigned int ep_rep; - int protocoll; - unsigned int sg_transfer_idx; - unsigned int cmd_len; - }; +struct stlink_libusb { + libusb_context* libusb_ctx; + libusb_device_handle* usb_handle; + unsigned int ep_req; + unsigned int ep_rep; + int protocoll; + unsigned int sg_transfer_idx; + unsigned int cmd_len; +}; - /** - * Open a stlink - * @param verbose Verbosity loglevel - * @param reset Reset stlink programmer - * @param serial Serial number to search for, when NULL the first stlink found is opened (binary format) - * @retval NULL Error while opening the stlink - * @retval !NULL Stlink found and ready to use - */ - stlink_t *stlink_open_usb(enum ugly_loglevel verbose, int reset, char serial[STLINK_SERIAL_MAX_SIZE], int freq); - size_t stlink_probe_usb(stlink_t **stdevs[]); - void stlink_probe_usb_free(stlink_t **stdevs[], size_t size); +/** + * Open a stlink + * @param verbose Verbosity loglevel + * @param reset Reset stlink programmer + * @param serial Serial number to search for, when NULL the first stlink found is opened (binary format) + * @retval NULL Error while opening the stlink + * @retval !NULL Stlink found and ready to use + */ +stlink_t *stlink_open_usb(enum ugly_loglevel verbose, int reset, char serial[STLINK_SERIAL_MAX_SIZE], int freq); +size_t stlink_probe_usb(stlink_t **stdevs[]); +void stlink_probe_usb_free(stlink_t **stdevs[], size_t size); #ifdef __cplusplus } #endif -#endif /* STLINK_USB_H */ +#endif // STLINK_USB_H diff --git a/src/win32/getopt/README.md b/src/win32/getopt/README.md index 9bf81fa73..2ec27c2d5 100644 --- a/src/win32/getopt/README.md +++ b/src/win32/getopt/README.md @@ -1,10 +1,11 @@ getopt_port =========== -[Kim Gräsman](http://grundlig.wordpress.com) +[Kim Gräsman](http://grundlig.wordpress.com) [@kimgr](http://twitter.com/kimgr) -An original implementation of `getopt` and `getopt_long` with limited GNU extensions. Provided under the BSD license, to allow non-GPL projects to use `getopt`-style command-line parsing. +An original implementation of `getopt` and `getopt_long` with limited GNU extensions. +Provided under the BSD license, to allow non-GPL projects to use `getopt`-style command-line parsing. So far only built with Visual C++, but has no inherently non-portable constructs. @@ -18,4 +19,4 @@ See also: * [XGetOpt](http://www.codeproject.com/Articles/1940/XGetopt-A-Unix-compatible-getopt-for-MFC-and-Win32) -- No `getopt_long` support. * [Free Getopt](https://sourceforge.net/projects/freegetopt/) -- No `getopt_long` support. -For license terms, see LICENSE.txt. \ No newline at end of file +For license terms, see LICENSE.txt. diff --git a/src/win32/getopt/getopt.c b/src/win32/getopt/getopt.c index 5dd45bff7..85e8804d8 100644 --- a/src/win32/getopt/getopt.c +++ b/src/win32/getopt/getopt.c @@ -11,196 +11,191 @@ const int optional_argument = 2; char* optarg; int optopt; -/* The variable optind [...] shall be initialized to 1 by the system. */ -int optind = 1; +int optind = 1; // The variable optind [...] shall be initialized to 1 by the system int opterr; static char* optcursor = NULL; /* Implemented based on [1] and [2] for optional arguments. - optopt is handled FreeBSD-style, per [3]. - Other GNU and FreeBSD extensions are purely accidental. - -[1] http://pubs.opengroup.org/onlinepubs/000095399/functions/getopt.html -[2] http://www.kernel.org/doc/man-pages/online/pages/man3/getopt.3.html -[3] http://www.freebsd.org/cgi/man.cgi?query=getopt&sektion=3&manpath=FreeBSD+9.0-RELEASE -*/ + * optopt is handled FreeBSD-style, per [3]. + * Other GNU and FreeBSD extensions are purely accidental. + * + * [1] http://pubs.opengroup.org/onlinepubs/000095399/functions/getopt.html + * [2] http://www.kernel.org/doc/man-pages/online/pages/man3/getopt.3.html + * [3] http://www.freebsd.org/cgi/man.cgi?query=getopt&sektion=3&manpath=FreeBSD+9.0-RELEASE + */ int getopt(int argc, char* const argv[], const char* optstring) { - int optchar = -1; - const char* optdecl = NULL; - - optarg = NULL; - opterr = 0; - optopt = 0; - - /* Unspecified, but we need it to avoid overrunning the argv bounds. */ - if (optind >= argc) - goto no_more_optchars; - - /* If, when getopt() is called argv[optind] is a null pointer, getopt() - shall return -1 without changing optind. */ - if (argv[optind] == NULL) - goto no_more_optchars; - - /* If, when getopt() is called *argv[optind] is not the character '-', - getopt() shall return -1 without changing optind. */ - if (*argv[optind] != '-') - goto no_more_optchars; - - /* If, when getopt() is called argv[optind] points to the string "-", - getopt() shall return -1 without changing optind. */ - if (strcmp(argv[optind], "-") == 0) - goto no_more_optchars; - - /* If, when getopt() is called argv[optind] points to the string "--", - getopt() shall return -1 after incrementing optind. */ - if (strcmp(argv[optind], "--") == 0) { - ++optind; - goto no_more_optchars; - } - - if (optcursor == NULL || *optcursor == '\0') - optcursor = argv[optind] + 1; - - optchar = *optcursor; - - /* FreeBSD: The variable optopt saves the last known option character - returned by getopt(). */ - optopt = optchar; - - /* The getopt() function shall return the next option character (if one is - found) from argv that matches a character in optstring, if there is - one that matches. */ - optdecl = strchr(optstring, optchar); - if (optdecl) { - /* [I]f a character is followed by a colon, the option takes an - argument. */ - if (optdecl[1] == ':') { - optarg = ++optcursor; - if (*optarg == '\0') { - /* GNU extension: Two colons mean an option takes an - optional arg; if there is text in the current argv-element - (i.e., in the same word as the option name itself, for example, - "-oarg"), then it is returned in optarg, otherwise optarg is set - to zero. */ - if (optdecl[2] != ':') { - /* If the option was the last character in the string pointed to by - an element of argv, then optarg shall contain the next element - of argv, and optind shall be incremented by 2. If the resulting - value of optind is greater than argc, this indicates a missing - option-argument, and getopt() shall return an error indication. - - Otherwise, optarg shall point to the string following the - option character in that element of argv, and optind shall be - incremented by 1. - */ - if (++optind < argc) { - optarg = argv[optind]; - } else { - /* If it detects a missing option-argument, it shall return the - colon character ( ':' ) if the first character of optstring - was a colon, or a question-mark character ( '?' ) otherwise. - */ - optarg = NULL; - optchar = (optstring[0] == ':') ? ':' : '?'; - } - } else { - optarg = NULL; - } - } + int optchar = -1; + const char* optdecl = NULL; + + optarg = NULL; + opterr = 0; + optopt = 0; + + /* Unspecified, but we need it to avoid overrunning the argv bounds. */ + if (optind >= argc) { goto no_more_optchars; } + + /* If, when getopt() is called argv[optind] is a null pointer, + * getopt() shall return -1 without changing optind. + */ + if (argv[optind] == NULL) { goto no_more_optchars; } + + /* If, when getopt() is called *argv[optind] is not the character '-', + * getopt() shall return -1 without changing optind. + */ + if (*argv[optind] != '-') { goto no_more_optchars; } + + /* If, when getopt() is called argv[optind] points to the string "-", + * getopt() shall return -1 without changing optind. + */ + if (strcmp(argv[optind], "-") == 0) { goto no_more_optchars; } + + /* If, when getopt() is called argv[optind] points to the string "--", + * getopt() shall return -1 after incrementing optind. + */ + if (strcmp(argv[optind], "--") == 0) { + ++optind; + goto no_more_optchars; + } - optcursor = NULL; + if (optcursor == NULL || *optcursor == '\0') { optcursor = argv[optind] + 1; } + + optchar = *optcursor; + + /* FreeBSD: The variable optopt saves the last known option character returned by getopt(). */ + optopt = optchar; + + /* The getopt() function shall return the next option character (if one is found) + * from argv that matches a character in optstring, if there is one that matches. + */ + optdecl = strchr(optstring, optchar); + + if (optdecl) { + /* [I]f a character is followed by a colon, the option takes an argument. */ + if (optdecl[1] == ':') { + optarg = ++optcursor; + + if (*optarg == '\0') { + /* GNU extension: Two colons mean an option takes an optional arg; + * if there is text in the current argv-element (i.e., in the same word + * as the option name itself, for example, "-oarg"), then it is returned + * in optarg, otherwise optarg is set to zero. + */ + if (optdecl[2] != ':') { + /* If the option was the last character in the string pointed to by + * an element of argv, then optarg shall contain the next element + * of argv, and optind shall be incremented by 2. If the resulting + * value of optind is greater than argc, this indicates a missing + * option-argument, and getopt() shall return an error indication. + * Otherwise, optarg shall point to the string following the + * option character in that element of argv, and optind shall be + * incremented by 1. + */ + if (++optind < argc) { + optarg = argv[optind]; + } else { + /* If it detects a missing option-argument, it shall return the + * colon character ( ':' ) if the first character of optstring + * was a colon, or a question-mark character ( '?' ) otherwise. + */ + optarg = NULL; + optchar = (optstring[0] == ':') ? ':' : '?'; + } + } else { + optarg = NULL; + } + } + + optcursor = NULL; + } + } else { + /* If getopt() encounters an option character that is not contained in + * optstring, it shall return the question-mark ( '?' ) character. + */ + optchar = '?'; } - } else { - /* If getopt() encounters an option character that is not contained in - optstring, it shall return the question-mark ( '?' ) character. */ - optchar = '?'; - } - if (optcursor == NULL || *++optcursor == '\0') - ++optind; + if (optcursor == NULL || *++optcursor == '\0') { ++optind; } - return optchar; + return(optchar); no_more_optchars: - optcursor = NULL; - return -1; + optcursor = NULL; + return(-1); } -/* Implementation based on [1]. - -[1] http://www.kernel.org/doc/man-pages/online/pages/man3/getopt.3.html -*/ -int getopt_long(int argc, char* const argv[], const char* optstring, - const struct option* longopts, int* longindex) { - const struct option* o = longopts; - const struct option* match = NULL; - int num_matches = 0; - size_t argument_name_length = 0; - const char* current_argument = NULL; - int retval = -1; - - optarg = NULL; - optopt = 0; - - if (optind >= argc) - return -1; - - if (strlen(argv[optind]) < 3 || strncmp(argv[optind], "--", 2) != 0) - return getopt(argc, argv, optstring); - - /* It's an option; starts with -- and is longer than two chars. */ - current_argument = argv[optind] + 2; - argument_name_length = strcspn(current_argument, "="); - for (; o->name; ++o) { - if (strncmp(o->name, current_argument, argument_name_length) == 0) { - match = o; - ++num_matches; +/* Implementation based on http://www.kernel.org/doc/man-pages/online/pages/man3/getopt.3.html */ +int getopt_long(int argc, + char* const argv[], + const char* optstring, + const struct option* longopts, + int* longindex) { + const struct option* o = longopts; + const struct option* match = NULL; + int num_matches = 0; + size_t argument_name_length = 0; + const char* current_argument = NULL; + int retval = -1; + + optarg = NULL; + optopt = 0; + + if (optind >= argc) { return(-1); } + + if (strlen(argv[optind]) < 3 || strncmp(argv[optind], "--", 2) != 0) { + return(getopt(argc, argv, optstring)); } - } - - if (num_matches == 1) { - /* If longindex is not NULL, it points to a variable which is set to the - index of the long option relative to longopts. */ - if (longindex) - *longindex = (match - longopts); - - /* If flag is NULL, then getopt_long() shall return val. - Otherwise, getopt_long() returns 0, and flag shall point to a variable - which shall be set to val if the option is found, but left unchanged if - the option is not found. */ - if (match->flag) - *(match->flag) = match->val; - - retval = match->flag ? 0 : match->val; - - if (match->has_arg != no_argument) { - optarg = strchr(argv[optind], '='); - if (optarg != NULL) - ++optarg; - - if (match->has_arg == required_argument) { - /* Only scan the next argv for required arguments. Behavior is not - specified, but has been observed with Ubuntu and Mac OSX. */ - if (optarg == NULL && ++optind < argc) { - optarg = argv[optind]; + + // it's an option; starts with -- and is longer than two chars + current_argument = argv[optind] + 2; + argument_name_length = strcspn(current_argument, "="); + + for ( ; o->name; ++o) + if (strncmp(o->name, current_argument, argument_name_length) == 0) { + match = o; + ++num_matches; } - if (optarg == NULL) - retval = ':'; - } - } else if (strchr(argv[optind], '=')) { - /* An argument was provided to a non-argument option. - I haven't seen this specified explicitly, but both GNU and BSD-based - implementations show this behavior. - */ - retval = '?'; + + if (num_matches == 1) { + /* If longindex is not NULL, it points to a variable which is set to the + * index of the long option relative to longopts. + */ + if (longindex) { *longindex = (match - longopts); } + + /* If flag is NULL, then getopt_long() shall return val. + * Otherwise, getopt_long() returns 0, and flag shall point to a variable + * which shall be set to val if the option is found, but left unchanged if + * the option is not found. + */ + if (match->flag) { *(match->flag) = match->val; } + + retval = match->flag ? 0 : match->val; + + if (match->has_arg != no_argument) { + optarg = strchr(argv[optind], '='); + + if (optarg != NULL) { ++optarg; } + + if (match->has_arg == required_argument) { + /* Only scan the next argv for required arguments. Behavior is not + specified, but has been observed with Ubuntu and macOS. */ + if (optarg == NULL && ++optind < argc) { optarg = argv[optind]; } + + if (optarg == NULL) { retval = ':'; } + } + } else if (strchr(argv[optind], '=')) { + /* An argument was provided to a non-argument option. + * I haven't seen this specified explicitly, but both GNU and BSD-based + * implementations show this behavior. + */ + retval = '?'; + } + } else { + // unknown option or ambiguous match + retval = '?'; } - } else { - /* Unknown option or ambiguous match. */ - retval = '?'; - } - ++optind; - return retval; + ++optind; + return(retval); } diff --git a/src/win32/getopt/getopt.h b/src/win32/getopt/getopt.h index bc189b9d4..3aaf73bed 100644 --- a/src/win32/getopt/getopt.h +++ b/src/win32/getopt/getopt.h @@ -20,16 +20,19 @@ extern char* optarg; extern int optind, opterr, optopt; struct option { - const char* name; - int has_arg; - int* flag; - int val; + const char* name; + int has_arg; + int* flag; + int val; }; int getopt(int argc, char* const argv[], const char* optstring); -int getopt_long(int argc, char* const argv[], - const char* optstring, const struct option* longopts, int* longindex); +int getopt_long(int argc, + char* const argv[], + const char* optstring, + const struct option* longopts, + int* longindex); #if defined(__cplusplus) } diff --git a/src/win32/mmap.c b/src/win32/mmap.c index 60bb440e9..d702a78f6 100644 --- a/src/win32/mmap.c +++ b/src/win32/mmap.c @@ -5,34 +5,34 @@ #include "mmap.h" -void *mmap (void *addr, size_t len, int prot, int flags, int fd, long long offset) { - +void *mmap (void *addr, size_t len, int prot, int flags, int fd, long long offset) { void *buf; ssize_t count; - if ( addr || fd == -1 || (prot & PROT_WRITE)) return MAP_FAILED; + if ( addr || fd == -1 || (prot & PROT_WRITE)) { return(MAP_FAILED); } buf = malloc(len); - if ( NULL == buf ) return MAP_FAILED; - if (lseek(fd,offset,SEEK_SET) != offset) { + if ( NULL == buf ) { return(MAP_FAILED); } + + if (lseek(fd, offset, SEEK_SET) != offset) { free(buf); - return MAP_FAILED; + return(MAP_FAILED); } count = read(fd, buf, len); if (count != (ssize_t)len) { free (buf); - return MAP_FAILED; + return(MAP_FAILED); } - return buf; + return(buf); (void)flags; } int munmap (void *addr, size_t len) { free (addr); - return 0; + return(0); (void)len; } diff --git a/src/win32/unistd/unistd.h b/src/win32/unistd/unistd.h index 0cdb9af7b..ac9d0add3 100644 --- a/src/win32/unistd/unistd.h +++ b/src/win32/unistd/unistd.h @@ -27,7 +27,7 @@ #define srandom srand #define random rand -/* values for the second argument to access. These may be OR'd together. */ +/* Values for the second argument to access. These may be OR'd together. */ #define R_OK 4 // Test for read permission #define W_OK 2 // Test for write permission // #define X_OK 1 // execute permission - unsupported in windows @@ -43,24 +43,27 @@ #define chdir _chdir #define isatty _isatty #define lseek _lseek -/* read, write, and close are NOT being defined here, + +/* + * Read, write, and close are NOT being defined here, * because while there are file handle specific versions for Windows, they probably don't work for sockets. - * You need to look at your app and consider whether to call e.g. closesocket(). */ + * You need to look at your app and consider whether to call e.g. closesocket(). + */ #define ssize_t int -#define STDIN_FILENO 0 +#define STDIN_FILENO 0 #define STDOUT_FILENO 1 #define STDERR_FILENO 2 // should be in some equivalent to -typedef __int8 int8_t; -typedef __int16 int16_t; -typedef __int32 int32_t; -typedef __int64 int64_t; -typedef unsigned __int8 uint8_t; -typedef unsigned __int16 uint16_t; -typedef unsigned __int32 uint32_t; -typedef unsigned __int64 uint64_t; +typedef __int8 int8_t; +typedef __int16 int16_t; +typedef __int32 int32_t; +typedef __int64 int64_t; +typedef unsigned __int8 uint8_t; +typedef unsigned __int16 uint16_t; +typedef unsigned __int32 uint32_t; +typedef unsigned __int64 uint64_t; #ifndef STLINK_HAVE_UNISTD_H int usleep(unsigned int waitTime); diff --git a/src/win32/win32_socket.c b/src/win32/win32_socket.c index 18f2351f8..de1c7e112 100644 --- a/src/win32/win32_socket.c +++ b/src/win32/win32_socket.c @@ -25,16 +25,20 @@ int win32_poll(struct pollfd *fds, unsigned int nfds, int timo) { FD_ZERO(&ifds); FD_ZERO(&ofds); FD_ZERO(&efds); + for (i = 0, op = ip = 0; i < nfds; ++i) { fds[i].revents = 0; + if (fds[i].events & (POLLIN | POLLPRI)) { ip = &ifds; FD_SET(fds[i].fd, ip); } + if (fds[i].events & POLLOUT) { op = &ofds; FD_SET(fds[i].fd, op); } + FD_SET(fds[i].fd, &efds); } @@ -53,7 +57,7 @@ int win32_poll(struct pollfd *fds, unsigned int nfds, int timo) { #ifdef DEBUG_POLL printf("Entering select() sec=%ld usec=%ld ip=%lx op=%lx\n", - (long)timeout.tv_sec, (long)timeout.tv_usec, (long)ip, (long)op); + (long)timeout.tv_sec, (long)timeout.tv_usec, (long)ip, (long)op); #endif rc = select(0, ip, op, &efds, toptr); @@ -62,33 +66,41 @@ int win32_poll(struct pollfd *fds, unsigned int nfds, int timo) { printf("Exiting select rc=%d\n", rc); #endif - if (rc <= 0) return rc; + if (rc <= 0) { return(rc); } if (rc > 0) { for ( i = 0; i < nfds; ++i) { int fd = fds[i].fd; - if (fds[i].events & (POLLIN|POLLPRI) && FD_ISSET(fd, &ifds)) + + if (fds[i].events & (POLLIN | POLLPRI) && FD_ISSET(fd, &ifds)) { fds[i].revents |= POLLIN; - if (fds[i].events & POLLOUT && FD_ISSET(fd, &ofds)) + } + + if (fds[i].events & POLLOUT && FD_ISSET(fd, &ofds)) { fds[i].revents |= POLLOUT; - if (FD_ISSET(fd, &efds)) - /* Some error was detected ... should be some way to know. */ + } + + if (FD_ISSET(fd, &efds)) { + // Some error was detected ... should be some way to know fds[i].revents |= POLLHUP; + } #ifdef DEBUG_POLL printf("%d %d %d revent = %x\n", - FD_ISSET(fd, &ifds), FD_ISSET(fd, &ofds), FD_ISSET(fd, &efds), - fds[i].revents - ); + FD_ISSET(fd, &ifds), + FD_ISSET(fd, &ofds), + FD_ISSET(fd, &efds), + fds[i].revents); #endif } } - return rc; + + return(rc); } static void set_connect_errno(int winsock_err) { - switch(winsock_err) { + switch (winsock_err) { case WSAEINVAL: case WSAEALREADY: case WSAEWOULDBLOCK: @@ -101,7 +113,7 @@ static void set_connect_errno(int winsock_err) { } static void set_socket_errno(int winsock_err) { - switch(winsock_err) { + switch (winsock_err) { case WSAEWOULDBLOCK: errno = EAGAIN; break; @@ -111,71 +123,81 @@ static void set_socket_errno(int winsock_err) { } } -/* - * A wrapper around the socket() function. +/* A wrapper around the socket() function. * The purpose of this wrapper is to ensure that the global errno symbol is set if an error occurs, * even if we are using winsock. */ SOCKET win32_socket(int domain, int type, int protocol) { SOCKET fd = socket(domain, type, protocol); - if (fd == INVALID_SOCKET) set_socket_errno(WSAGetLastError()); - return fd; + + if (fd == INVALID_SOCKET) { set_socket_errno(WSAGetLastError()); } + + return(fd); } -/* - * A wrapper around the connect() function. +/* A wrapper around the connect() function. * The purpose of this wrapper is to ensure that the global errno symbol is set if an error occurs, * even if we are using winsock. */ int win32_connect(SOCKET fd, struct sockaddr *addr, socklen_t addr_len) { int rc = connect(fd, addr, addr_len); assert(rc == 0 || rc == SOCKET_ERROR); - if (rc == SOCKET_ERROR) set_connect_errno(WSAGetLastError()); - return rc; + + if (rc == SOCKET_ERROR) { set_connect_errno(WSAGetLastError()); } + + return(rc); } -/* - * A wrapper around the accept() function. +/* A wrapper around the accept() function. * The purpose of this wrapper is to ensure that the global errno symbol is set if an error occurs, * even if we are using winsock. */ SOCKET win32_accept(SOCKET fd, struct sockaddr *addr, socklen_t *addr_len) { SOCKET newfd = accept(fd, addr, addr_len); + if (newfd == INVALID_SOCKET) { set_socket_errno(WSAGetLastError()); newfd = (SOCKET)-1; } - return newfd; + + return(newfd); } -/* - * A wrapper around the shutdown() function. +/* A wrapper around the shutdown() function. * The purpose of this wrapper is to ensure that the global errno symbol is set if an error occurs, * even if we are using winsock. */ int win32_shutdown(SOCKET fd, int mode) { int rc = shutdown(fd, mode); assert(rc == 0 || rc == SOCKET_ERROR); - if (rc == SOCKET_ERROR) set_socket_errno(WSAGetLastError()); - return rc; + + if (rc == SOCKET_ERROR) { set_socket_errno(WSAGetLastError()); } + + return(rc); } int win32_close_socket(SOCKET fd) { int rc = closesocket(fd); - if (rc == SOCKET_ERROR) set_socket_errno(WSAGetLastError()); - return rc; + + if (rc == SOCKET_ERROR) { set_socket_errno(WSAGetLastError()); } + + return(rc); } ssize_t win32_write_socket(SOCKET fd, void *buf, int n) { int rc = send(fd, buf, n, 0); - if (rc == SOCKET_ERROR) set_socket_errno(WSAGetLastError()); - return rc; + + if (rc == SOCKET_ERROR) { set_socket_errno(WSAGetLastError()); } + + return(rc); } ssize_t win32_read_socket(SOCKET fd, void *buf, int n) { int rc = recv(fd, buf, n, 0); - if (rc == SOCKET_ERROR) set_socket_errno(WSAGetLastError()); - return rc; + + if (rc == SOCKET_ERROR) { set_socket_errno(WSAGetLastError()); } + + return(rc); } @@ -185,41 +207,45 @@ char * win32_strtok_r(char *s, const char *delim, char **lasts) { char *tok; - if (s == NULL && (s = *lasts) == NULL) return (NULL); + if (s == NULL && (s = *lasts) == NULL) { return (NULL); } - // Skip (span) leading delimiters (s += strspn(s, delim), sort of). + // skip (span) leading delimiters (s += strspn(s, delim), sort of). cont: c = *s++; - for (spanp = (char *)delim; (sc = *spanp++) != 0;) { - if (c == sc) - goto cont; - } + + for (spanp = (char *)delim; (sc = *spanp++) != 0;) + if (c == sc) { goto cont; } + if (c == 0) { // no non-delimiter characters *lasts = NULL; return (NULL); } + tok = s - 1; - /* - * Scan token (scan for delimiters: s += strcspn(s, delim), sort of). + /* Scan token (scan for delimiters: s += strcspn(s, delim), sort of). * Note that delim must have one NUL; we stop if we see that, too. */ - for (;;) { + for ( ; ;) { c = *s++; spanp = (char *)delim; - do { + + do if ((sc = *spanp++) == c) { if (c == 0) { s = NULL; } else { s[-1] = 0; } + *lasts = s; - return (tok); + return(tok); } - } while (sc != 0); + + while (sc != 0); } + // NOT REACHED } @@ -229,22 +255,29 @@ char *win32_strsep (char **stringp, const char *delim) { register int c, sc; char *tok; - if ((s = *stringp) == NULL) return (NULL); - for (tok = s;;) { + if ((s = *stringp) == NULL) { + return(NULL); + } + + for (tok = s; ;) { c = *s++; spanp = delim; - do { + + do if ((sc = *spanp++) == c) { if (c == 0) { s = NULL; } else { s[-1] = 0; } + *stringp = s; - return (tok); + return(tok); } - } while (sc != 0); + + while (sc != 0); } + // NOT REACHED } @@ -264,18 +297,19 @@ int usleep(unsigned int waitTime) { WaitForSingleObject(timer, INFINITE); CloseHandle(timer); - return 0; + return(0); } + LARGE_INTEGER perf_cnt, start, now; QueryPerformanceFrequency(&perf_cnt); QueryPerformanceCounter(&start); - do { - QueryPerformanceCounter((LARGE_INTEGER*) &now); - } while ((now.QuadPart - start.QuadPart) / (float)perf_cnt.QuadPart * 1000 * 1000 < waitTime); + do + QueryPerformanceCounter((LARGE_INTEGER*)&now); + while ((now.QuadPart - start.QuadPart) / (float)perf_cnt.QuadPart * 1000 * 1000 < waitTime); - return 0; + return(0); } #endif diff --git a/src/win32/win32_socket.h b/src/win32/win32_socket.h index d2a3ac38c..ea1a39c93 100644 --- a/src/win32/win32_socket.h +++ b/src/win32/win32_socket.h @@ -62,8 +62,8 @@ SOCKET win32_accept(SOCKET, struct sockaddr*, socklen_t *); int win32_shutdown(SOCKET, int); int win32_close_socket(SOCKET fd); -#define strtok_r(x, y, z) win32_strtok_r(x, y, z) -#define strsep(x,y) win32_strsep(x,y) +#define strtok_r(x, y, z) win32_strtok_r(x, y, z) +#define strsep(x,y) win32_strsep(x,y) char *win32_strtok_r(char *s, const char *delim, char **lasts); char *win32_strsep(char **stringp, const char *delim); diff --git a/tests/flash.c b/tests/flash.c index d47b3564d..a8d479b2d 100644 --- a/tests/flash.c +++ b/tests/flash.c @@ -6,7 +6,7 @@ #include #if defined(_MSC_VER) - #include +#include #endif struct Test { @@ -37,25 +37,25 @@ static bool execute_test(const struct Test * test) { /* parse (tokenize) the test command line */ #if defined(_MSC_VER) - char *cmd_line = alloca(strlen(test->cmd_line) + 1); + char *cmd_line = alloca(strlen(test->cmd_line) + 1); #else - char cmd_line[strlen(test->cmd_line) + 1]; + char cmd_line[strlen(test->cmd_line) + 1]; #endif strcpy(cmd_line, test->cmd_line); for (char * tok = strtok(cmd_line, " "); tok; tok = strtok(NULL, " ")) { - if ((size_t)ac >= sizeof(av)/sizeof(av[0])) - return false; + if ((size_t)ac >= sizeof(av) / sizeof(av[0])) return(false); + av[ac] = tok; ++ac; } - /* call */ + /* Call */ struct flash_opts opts; int res = flash_get_opts(&opts, ac, av); - /* compare results */ + /* Compare results */ bool ret = (res == test->res); if (ret && (res == 0)) { @@ -71,87 +71,87 @@ static bool execute_test(const struct Test * test) { } printf("[%s] (%d) %s\n", ret ? "OK" : "ERROR", res, test->cmd_line); - return ret; + return(ret); } static struct Test tests[] = { { "", -1, FLASH_OPTS_INITIALIZER }, { "--debug --reset read test.bin 0x80000000 0x1000", 0, - { .cmd = FLASH_CMD_READ, - .serial = { 0 }, - .filename = "test.bin", - .addr = 0x80000000, - .size = 0x1000, - .reset = 1, - .log_level = DEBUG_LOG_LEVEL, - .freq = 0, - .format = FLASH_FORMAT_BINARY } + { .cmd = FLASH_CMD_READ, + .serial = { 0 }, + .filename = "test.bin", + .addr = 0x80000000, + .size = 0x1000, + .reset = 1, + .log_level = DEBUG_LOG_LEVEL, + .freq = 0, + .format = FLASH_FORMAT_BINARY } }, { "--debug --reset write test.bin 0x80000000", 0, - { .cmd = FLASH_CMD_WRITE, - .serial = { 0 }, - .filename = "test.bin", - .addr = 0x80000000, - .size = 0, - .reset = 1, - .log_level = DEBUG_LOG_LEVEL, - .freq = 0, - .format = FLASH_FORMAT_BINARY } + { .cmd = FLASH_CMD_WRITE, + .serial = { 0 }, + .filename = "test.bin", + .addr = 0x80000000, + .size = 0, + .reset = 1, + .log_level = DEBUG_LOG_LEVEL, + .freq = 0, + .format = FLASH_FORMAT_BINARY } }, { "--debug --freq 5k --reset write test.bin 0x80000000", 0, - { .cmd = FLASH_CMD_WRITE, - .serial = { 0 }, - .filename = "test.bin", - .addr = 0x80000000, - .size = 0, - .reset = 1, - .log_level = DEBUG_LOG_LEVEL, - .freq = 5, - .format = FLASH_FORMAT_BINARY } + { .cmd = FLASH_CMD_WRITE, + .serial = { 0 }, + .filename = "test.bin", + .addr = 0x80000000, + .size = 0, + .reset = 1, + .log_level = DEBUG_LOG_LEVEL, + .freq = 5, + .format = FLASH_FORMAT_BINARY } }, { "--debug --freq 15K --reset write test.bin 0x80000000", 0, - { .cmd = FLASH_CMD_WRITE, - .serial = { 0 }, - .filename = "test.bin", - .addr = 0x80000000, - .size = 0, - .reset = 1, - .log_level = DEBUG_LOG_LEVEL, - .freq = 15, - .format = FLASH_FORMAT_BINARY } + { .cmd = FLASH_CMD_WRITE, + .serial = { 0 }, + .filename = "test.bin", + .addr = 0x80000000, + .size = 0, + .reset = 1, + .log_level = DEBUG_LOG_LEVEL, + .freq = 15, + .format = FLASH_FORMAT_BINARY } }, { "--debug --freq=5k --reset write test.bin 0x80000000", 0, - { .cmd = FLASH_CMD_WRITE, - .serial = { 0 }, - .filename = "test.bin", - .addr = 0x80000000, - .size = 0, - .reset = 1, - .log_level = DEBUG_LOG_LEVEL, - .freq = 5, - .format = FLASH_FORMAT_BINARY } + { .cmd = FLASH_CMD_WRITE, + .serial = { 0 }, + .filename = "test.bin", + .addr = 0x80000000, + .size = 0, + .reset = 1, + .log_level = DEBUG_LOG_LEVEL, + .freq = 5, + .format = FLASH_FORMAT_BINARY } }, { "--debug --freq=6k --reset write test.bin 0x80000000", -1, - { .cmd = FLASH_CMD_WRITE, - .serial = { 0 }, - .filename = "test.bin", - .addr = 0x80000000, - .size = 0, - .reset = 1, - .log_level = DEBUG_LOG_LEVEL, - .freq = 6, - .format = FLASH_FORMAT_BINARY } + { .cmd = FLASH_CMD_WRITE, + .serial = { 0 }, + .filename = "test.bin", + .addr = 0x80000000, + .size = 0, + .reset = 1, + .log_level = DEBUG_LOG_LEVEL, + .freq = 6, + .format = FLASH_FORMAT_BINARY } }, { "--debug --reset read test.bin 0x80000000 1000", 0, - { .cmd = FLASH_CMD_READ, - .serial = { 0 }, - .filename = "test.bin", - .addr = 0x80000000, - .size = 1000, - .reset = 1, - .log_level = DEBUG_LOG_LEVEL, - .freq = 0, - .format = FLASH_FORMAT_BINARY } + { .cmd = FLASH_CMD_READ, + .serial = { 0 }, + .filename = "test.bin", + .addr = 0x80000000, + .size = 1000, + .reset = 1, + .log_level = DEBUG_LOG_LEVEL, + .freq = 0, + .format = FLASH_FORMAT_BINARY } }, { "--debug --reset read test.bin 0x80000000 1k", 0, { .cmd = FLASH_CMD_READ, @@ -176,71 +176,72 @@ static struct Test tests[] = { .format = FLASH_FORMAT_BINARY } }, { "--debug --reset write test.bin 0x80000000", 0, - { .cmd = FLASH_CMD_WRITE, - .serial = { 0 }, - .filename = "test.bin", - .addr = 0x80000000, - .size = 0, - .reset = 1, - .log_level = DEBUG_LOG_LEVEL, - .freq = 0, - .format = FLASH_FORMAT_BINARY } + { .cmd = FLASH_CMD_WRITE, + .serial = { 0 }, + .filename = "test.bin", + .addr = 0x80000000, + .size = 0, + .reset = 1, + .log_level = DEBUG_LOG_LEVEL, + .freq = 0, + .format = FLASH_FORMAT_BINARY } }, { "erase", 0, - { .cmd = FLASH_CMD_ERASE, - .serial = { 0 }, - .filename = NULL, - .addr = 0, - .size = 0, - .reset = 0, - .log_level = STND_LOG_LEVEL, - .freq = 0, - .format = FLASH_FORMAT_BINARY } + { .cmd = FLASH_CMD_ERASE, + .serial = { 0 }, + .filename = NULL, + .addr = 0, + .size = 0, + .reset = 0, + .log_level = STND_LOG_LEVEL, + .freq = 0, + .format = FLASH_FORMAT_BINARY } }, { "--debug --reset --format=ihex write test.hex", 0, - { .cmd = FLASH_CMD_WRITE, - .serial = { 0 }, - .filename = "test.hex", - .addr = 0, - .size = 0, - .reset = 1, - .log_level = DEBUG_LOG_LEVEL, - .freq = 0, - .format = FLASH_FORMAT_IHEX } + { .cmd = FLASH_CMD_WRITE, + .serial = { 0 }, + .filename = "test.hex", + .addr = 0, + .size = 0, + .reset = 1, + .log_level = DEBUG_LOG_LEVEL, + .freq = 0, + .format = FLASH_FORMAT_IHEX } }, { "--debug --reset --format=binary write test.hex", -1, FLASH_OPTS_INITIALIZER }, { "--debug --reset --format=ihex write test.hex 0x80000000", -1, FLASH_OPTS_INITIALIZER }, { "--debug --reset write test.hex sometext", -1, FLASH_OPTS_INITIALIZER }, { "--serial A1020304 erase sometext", -1, FLASH_OPTS_INITIALIZER }, { "--serial A1020304 erase", 0, - { .cmd = FLASH_CMD_ERASE, - .serial = "\xA1\x02\x03\x04", - .filename = NULL, - .addr = 0, - .size = 0, - .reset = 0, - .log_level = STND_LOG_LEVEL, - .freq = 0, - .format = FLASH_FORMAT_BINARY } + { .cmd = FLASH_CMD_ERASE, + .serial = "\xA1\x02\x03\x04", + .filename = NULL, + .addr = 0, + .size = 0, + .reset = 0, + .log_level = STND_LOG_LEVEL, + .freq = 0, + .format = FLASH_FORMAT_BINARY } }, { "--serial=A1020304 erase", 0, - { .cmd = FLASH_CMD_ERASE, - .serial = "\xA1\x02\x03\x04", - .filename = NULL, - .addr = 0, - .size = 0, - .reset = 0, - .log_level = STND_LOG_LEVEL, - .freq = 0, - .format = FLASH_FORMAT_BINARY } + { .cmd = FLASH_CMD_ERASE, + .serial = "\xA1\x02\x03\x04", + .filename = NULL, + .addr = 0, + .size = 0, + .reset = 0, + .log_level = STND_LOG_LEVEL, + .freq = 0, + .format = FLASH_FORMAT_BINARY } }, }; int main() { bool allOk = true; - for (size_t i = 0; i < sizeof(tests)/sizeof(tests[0]); ++i) { + + for (size_t i = 0; i < sizeof(tests) / sizeof(tests[0]); ++i) if (!execute_test(&tests[i])) allOk = false; - } + return (allOk ? 0 : 1); } diff --git a/tests/sg.c b/tests/sg.c index 1af177174..745df845f 100644 --- a/tests/sg.c +++ b/tests/sg.c @@ -1,9 +1,3 @@ -/* - * File: test_main.c - * - * main() ripped out of old stlink-hw.c - */ - #include #include #include @@ -11,7 +5,7 @@ #include #if defined(_MSC_VER) - #define __attribute__(x) +#define __attribute__(x) #endif static void __attribute__((unused)) mark_buf(stlink_t *sl) { @@ -30,28 +24,28 @@ static void __attribute__((unused)) mark_buf(stlink_t *sl) { } -int main(void) { +int main(void) { // main() ripped out of old stlink-hw.c /* Avoid unused parameter warning */ // set scpi lib debug level: 0 for no debug info, 10 for lots fputs( - "\nUsage: stlink-access-test [anything at all] ...\n" - "\n*** Notice: The stlink firmware violates the USB standard.\n" - "*** Because we just use libusb, we can just tell the kernel's\n" - "*** driver to simply ignore the device...\n" - "*** Unplug the stlink and execute once as root:\n" - "modprobe -r usb-storage && modprobe usb-storage quirks=483:3744:i\n\n", - stderr); + "\nUsage: stlink-access-test [anything at all] ...\n" + "\n*** Notice: The stlink firmware violates the USB standard.\n" + "*** Because we just use libusb, we can just tell the kernel's\n" + "*** driver to simply ignore the device...\n" + "*** Unplug the stlink and execute once as root:\n" + "modprobe -r usb-storage && modprobe usb-storage quirks=483:3744:i\n\n", + stderr); stlink_t *sl = stlink_v1_open(99, 1); - if (sl == NULL) - return 0; + + if (sl == NULL) return(0); // we are in mass mode, go to swd stlink_enter_swd_mode(sl); stlink_current_mode(sl); stlink_core_id(sl); stlink_status(sl); - //stlink_force_debug(sl); + // stlink_force_debug(sl); stlink_reset(sl); stlink_status(sl); // core system control block @@ -75,8 +69,8 @@ int main(void) { #define GPIOC 0x40011000 // port C #define GPIOC_CRH (GPIOC + 0x04) // port configuration register high #define GPIOC_ODR (GPIOC + 0x0c) // port output data register - #define LED_BLUE (1<<8) // pin 8 - #define LED_GREEN (1<<9) // pin 9 + #define LED_BLUE (1 << 8) // pin 8 + #define LED_GREEN (1 << 9) // pin 9 stlink_read_mem32(sl, GPIOC_CRH, 4); uint32_t io_conf = read_uint32(sl->q_buf, 0); DLOG("GPIOC_CRH = 0x%08x\n", io_conf); @@ -86,17 +80,19 @@ int main(void) { stlink_write_mem32(sl, GPIOC_CRH, 4); memset(sl->q_buf, 0, sizeof(sl->q_buf)); + for (int i = 0; i < 100; i++) { write_uint32(sl->q_buf, LED_BLUE | LED_GREEN); stlink_write_mem32(sl, GPIOC_ODR, 4); - //stlink_read_mem32(sl, 0x4001100c, 4); - //DD(sl, "GPIOC_ODR = 0x%08x", read_uint32(sl->q_buf, 0)); + // stlink_read_mem32(sl, 0x4001100c, 4); + // DD(sl, "GPIOC_ODR = 0x%08x", read_uint32(sl->q_buf, 0)); usleep(100 * 1000); memset(sl->q_buf, 0, sizeof(sl->q_buf)); stlink_write_mem32(sl, GPIOC_ODR, 4); // PC lo usleep(100 * 1000); } + write_uint32(sl->q_buf, io_conf); // set old state #endif @@ -104,10 +100,10 @@ int main(void) { // TODO rtfm: stlink doesn't have flash write routines // writing to the flash area confuses the fw for the next read access - //stlink_read_mem32(sl, 0, 1024*6); + // stlink_read_mem32(sl, 0, 1024*6); // flash 0x08000000 128kB fputs("++++++++++ read a flash at 0x0800 0000\n", stderr); - stlink_read_mem32(sl, 0x08000000, 1024 * 6); //max 6kB + stlink_read_mem32(sl, 0x08000000, 1024 * 6); // max 6kB clear_buf(sl); stlink_read_mem32(sl, 0x08000c00, 5); stlink_read_mem32(sl, 0x08000c00, 4); @@ -122,9 +118,9 @@ int main(void) { fputs("\n++++++++++ read/write 8bit, sram at 0x2000 0000 ++++++++++++++++\n\n", stderr); memset(sl->q_buf, 0, sizeof(sl->q_buf)); mark_buf(sl); - //stlink_write_mem8(sl, 0x20000000, 16); - //stlink_write_mem8(sl, 0x20000000, 1); - //stlink_write_mem8(sl, 0x20000001, 1); + // stlink_write_mem8(sl, 0x20000000, 16); + // stlink_write_mem8(sl, 0x20000000, 1); + // stlink_write_mem8(sl, 0x20000001, 1); stlink_write_mem8(sl, 0x2000000b, 3); stlink_read_mem32(sl, 0x20000000, 16); #endif @@ -157,7 +153,7 @@ int main(void) { stlink_read_mem32(sl, 0x20000000, 64); mark_buf(sl); - stlink_write_mem32(sl, 0x20000000, 1024 * 8); //8kB + stlink_write_mem32(sl, 0x20000000, 1024 * 8); // 8kB stlink_read_mem32(sl, 0x20000000, 1024 * 6); stlink_read_mem32(sl, 0x20000000 + 1024 * 6, 1024 * 2); #endif @@ -208,7 +204,7 @@ int main(void) { stlink_close(sl); #endif - //fflush(stderr); - //fflush(stdout); - return EXIT_SUCCESS; + // fflush(stderr); + // fflush(stdout); + return(EXIT_SUCCESS); } diff --git a/tests/usb.c b/tests/usb.c index ce72e24a5..03c135f00 100644 --- a/tests/usb.c +++ b/tests/usb.c @@ -3,14 +3,12 @@ #include #include -static void usage(void) -{ +static void usage(void) { puts("test-usb --reset"); puts("test-usb --no-reset"); } int main(int ac, char** av) { - stlink_t* sl; struct stlink_reg regs; int reset = 0; @@ -18,15 +16,18 @@ int main(int ac, char** av) { if (ac == 2) { if (strcmp(av[1], "--reset") == 0) reset = 2; - if (strcmp(av[1], "--no-reset") == 0) + + if (strcmp(av[1], "--no-reset") == 0) reset = 1; } + if (reset == 0) { usage(); - return 0; + return(0); } sl = stlink_open_usb(10, reset, NULL, 0); + if (sl != NULL) { printf("-- version\n"); stlink_version(sl); @@ -47,6 +48,7 @@ int main(int ac, char** av) { printf("-- core_id: %#x\n", sl->core_id); cortex_m3_cpuid_t cpuid; + if (stlink_cpu_id(sl, &cpuid)) { printf("Failed reading stlink_cpu_id\n"); } else { @@ -57,6 +59,7 @@ int main(int ac, char** av) { printf("-- read_sram\n"); static const uint32_t sram_base = STM32_SRAM_BASE; uint32_t off; + for (off = 0; off < 16; off += 4) stlink_read_mem32(sl, sram_base + off, 4); @@ -64,24 +67,24 @@ int main(int ac, char** av) { stlink_read_mem32(sl, STLINK_REG_CM3_FP_CTRL, 4); // no idea what reg this is... - //stlink_read_mem32(sl, 0xe000ed90, 4); + // stlink_read_mem32(sl, 0xe000ed90, 4); // no idea what register this is... - //stlink_read_mem32(sl, 0xe000edf0, 4); + // stlink_read_mem32(sl, 0xe000edf0, 4); // offset 0xC into TIM11 register? TIMx_DIER? - //stlink_read_mem32(sl, 0x4001100c, 4); + // stlink_read_mem32(sl, 0x4001100c, 4); - /* Test 32 bit Write */ - write_uint32(sl->q_buf,0x01234567); - stlink_write_mem32(sl,0x200000a8,4); - write_uint32(sl->q_buf,0x89abcdef); - stlink_write_mem32(sl,0x200000ac, 4); + /* Test 32 bit write */ + write_uint32(sl->q_buf, 0x01234567); + stlink_write_mem32(sl, 0x200000a8, 4); + write_uint32(sl->q_buf, 0x89abcdef); + stlink_write_mem32(sl, 0x200000ac, 4); stlink_read_mem32(sl, 0x200000a8, 4); stlink_read_mem32(sl, 0x200000ac, 4); /* Test 8 bit write */ - write_uint32(sl->q_buf,0x01234567); - stlink_write_mem8(sl,0x200001a8,3); - write_uint32(sl->q_buf,0x89abcdef); + write_uint32(sl->q_buf, 0x01234567); + stlink_write_mem8(sl, 0x200001a8, 3); + write_uint32(sl->q_buf, 0x89abcdef); stlink_write_mem8(sl, 0x200001ac, 3); stlink_read_mem32(sl, 0x200001a8, 4); stlink_read_mem32(sl, 0x200001ac, 4); @@ -96,8 +99,8 @@ int main(int ac, char** av) { stlink_write_reg(sl, 0x01234567, 3); stlink_write_reg(sl, 0x89abcdef, 4); stlink_write_reg(sl, 0x12345678, 15); - for (off = 0; off < 21; off += 1) - stlink_read_reg(sl, off, ®s); + + for (off = 0; off < 21; off += 1) stlink_read_reg(sl, off, ®s); stlink_read_all_regs(sl, ®s); @@ -115,5 +118,6 @@ int main(int ac, char** av) { stlink_close(sl); } - return 0; + + return(0); } From 06aec5b541ac0e97125dad5e14ce0f8e72e5e6c4 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sat, 13 Jun 2020 21:45:05 +0200 Subject: [PATCH 040/503] Code style fixes for win32_socket. --- src/win32/win32_socket.c | 12 ++++++------ src/win32/win32_socket.h | 4 ++-- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/src/win32/win32_socket.c b/src/win32/win32_socket.c index de1c7e112..9138a7679 100644 --- a/src/win32/win32_socket.c +++ b/src/win32/win32_socket.c @@ -231,7 +231,7 @@ char * win32_strtok_r(char *s, const char *delim, char **lasts) { c = *s++; spanp = (char *)delim; - do + do { if ((sc = *spanp++) == c) { if (c == 0) { s = NULL; @@ -243,7 +243,7 @@ char * win32_strtok_r(char *s, const char *delim, char **lasts) { return(tok); } - while (sc != 0); + } while (sc != 0); } // NOT REACHED @@ -263,7 +263,7 @@ char *win32_strsep (char **stringp, const char *delim) { c = *s++; spanp = delim; - do + do { if ((sc = *spanp++) == c) { if (c == 0) { s = NULL; @@ -275,7 +275,7 @@ char *win32_strsep (char **stringp, const char *delim) { return(tok); } - while (sc != 0); + } while (sc != 0); } // NOT REACHED @@ -305,9 +305,9 @@ int usleep(unsigned int waitTime) { QueryPerformanceFrequency(&perf_cnt); QueryPerformanceCounter(&start); - do + do { QueryPerformanceCounter((LARGE_INTEGER*)&now); - while ((now.QuadPart - start.QuadPart) / (float)perf_cnt.QuadPart * 1000 * 1000 < waitTime); + } while ((now.QuadPart - start.QuadPart) / (float)perf_cnt.QuadPart * 1000 * 1000 < waitTime); return(0); } diff --git a/src/win32/win32_socket.h b/src/win32/win32_socket.h index ea1a39c93..5f8f09589 100644 --- a/src/win32/win32_socket.h +++ b/src/win32/win32_socket.h @@ -20,9 +20,9 @@ #pragma warning(pop) #endif -/* winsock doesn't feature poll(), so there is a version implemented in terms of select() in mingw.c. +/* winsock doesn't feature poll(), so there is a version implemented in terms of select() in win32_socket.c. * The following definitions are copied from linux man pages. - * A poll() macro is defined to call the version in mingw.c. + * A poll() macro is defined to call the version in win32_socket.c. */ #if !defined(_WIN32_WINNT) || (_WIN32_WINNT < 0x0600) From d473c99f10ec10ca525c9cbe9b0e3d3c36bf5af7 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 14 Jun 2020 17:20:49 +0200 Subject: [PATCH 041/503] Fix for external CMAKE_MODULE_PATH (Closes #962) --- CMakeLists.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index 52f6867f4..59b9d963c 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -4,7 +4,7 @@ cmake_minimum_required(VERSION 3.4.2) cmake_policy(SET CMP0042 NEW) -set(CMAKE_MODULE_PATH "${CMAKE_MODULE_PATH};${CMAKE_SOURCE_DIR}/cmake/modules") +set(CMAKE_MODULE_PATH ${CMAKE_SOURCE_DIR}/cmake/modules) set(CMAKE_ARCHIVE_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}/lib) set(CMAKE_LIBRARY_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}/lib) set(CMAKE_RUNTIME_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}/bin) From ffe6240012d7cb83749bf00baf0e300cf7cab2ea Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Mon, 15 Jun 2020 10:46:09 +0200 Subject: [PATCH 042/503] Minor whitespace and code style fix --- cmake/modules/get_version.cmake | 2 +- src/stlink-lib/libusb_settings.h | 26 +++++++++++++------------- 2 files changed, 14 insertions(+), 14 deletions(-) diff --git a/cmake/modules/get_version.cmake b/cmake/modules/get_version.cmake index b80f0c9db..dddb35549 100644 --- a/cmake/modules/get_version.cmake +++ b/cmake/modules/get_version.cmake @@ -55,7 +55,7 @@ if (GIT_FOUND AND EXISTS "${PROJECT_SOURCE_DIR}/.git") message(STATUS "Rewrite ${PROJECT_SOURCE_DIR}/.version with ${__version_str}.") endif () - else (EXISTS "${PROJECT_SOURCE_DIR}/.version") + else (NOT EXISTS "${PROJECT_SOURCE_DIR}/.version") # No local .version file found: Create a new one... file(WRITE "${PROJECT_SOURCE_DIR}/.version" ${__version_str}) diff --git a/src/stlink-lib/libusb_settings.h b/src/stlink-lib/libusb_settings.h index 046c0b33d..fea28237b 100644 --- a/src/stlink-lib/libusb_settings.h +++ b/src/stlink-lib/libusb_settings.h @@ -5,19 +5,19 @@ /* - libusb ver | LIBUSB_API_VERSION - -----------+-------------------- - v1.0.13 | 0x01000100 - v1.0.14 | 0x010000FF - v1.0.15 | 0x01000101 - v1.0.16 | 0x01000102 - v1.0.17 | 0x01000102 - v1.0.18 | 0x01000102 - v1.0.19 | 0x01000103 - v1.0.20 | 0x01000104 - v1.0.21 | 0x01000105 - v1.0.22 | 0x01000106 - v1.0.23 | 0x01000107 + libusb ver | LIBUSB_API_VERSION + -----------+-------------------- + v1.0.13 | 0x01000100 + v1.0.14 | 0x010000FF + v1.0.15 | 0x01000101 + v1.0.16 | 0x01000102 + v1.0.17 | 0x01000102 + v1.0.18 | 0x01000102 + v1.0.19 | 0x01000103 + v1.0.20 | 0x01000104 + v1.0.21 | 0x01000105 + v1.0.22 | 0x01000106 + v1.0.23 | 0x01000107 */ From 15bdf0a4f0c29c14e81974d322bcf31ee5338de8 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Tue, 16 Jun 2020 16:54:46 +0200 Subject: [PATCH 043/503] Changed path for udev rules to default /etc/udev/rules.d/ -> /lib/udev/rules.d/ --- CMakeLists.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index 59b9d963c..82e5bf769 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -268,8 +268,8 @@ if (CMAKE_SYSTEM_NAME STREQUAL "Linux") set(STLINK_MODPROBED_DIR "/etc/modprobe.d" CACHE PATH "modprobe.d directory") install(FILES ${CMAKE_SOURCE_DIR}/config/modprobe.d/stlink_v1.conf DESTINATION ${STLINK_MODPROBED_DIR}) - ## Install udev rules files to /etc/udev/rules.d/ (explicitly hardcoded) - set(STLINK_UDEV_RULES_DIR "/etc/udev/rules.d" CACHE PATH "udev rules directory") + ## Install udev rules files to /lib/udev/rules.d/ (explicitly hardcoded) + set(STLINK_UDEV_RULES_DIR "/lib/udev/rules.d" CACHE PATH "udev rules directory") file(GLOB RULES_FILES ${CMAKE_SOURCE_DIR}/config/udev/rules.d/*.rules) install(FILES ${RULES_FILES} DESTINATION ${STLINK_UDEV_RULES_DIR}) endif () From e250773b88c915a9726a9eae112262fb74dcd193 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Wed, 17 Jun 2020 11:32:41 +0200 Subject: [PATCH 044/503] [doc] Added --reset option for st-flash (Closes #642) --- doc/tutorial.md | 1 + 1 file changed, 1 insertion(+) diff --git a/doc/tutorial.md b/doc/tutorial.md index 81315dbef..7b8b1d461 100644 --- a/doc/tutorial.md +++ b/doc/tutorial.md @@ -8,6 +8,7 @@ stlink Tools Tutorial | --flash=n[k][m] | st-flash | One can specify `--flash=128k` for example, to override the default value of 64k
for the STM32F103C8T6 to assume 128k of flash being present. This option accepts
decimal (128k), octal 0200k, or hex 0x80k values. Leaving the multiplier out is
equally valid, e.g.: `--flash=0x20000`. The size may be followed by an optional "k"
or "m" to multiply the given value by 1k (1024) or 1M respectively. | v1.4.0 | | --freq=n[k][m] | st-flash,
st-util | The frequency of the SWD/JTAG interface can be specified, to override the default
1800 kHz configuration. This option solely accepts decimal values (5K or 1.8M) with
the unit `Hz` being left out. Valid frequencies are `5K, 15K, 25K, 50K, 100K,`
`125K, 240K, 480K, 950K, 1200K(1.2M), 1800K(1.8M), 4000K(4M)`. | v1.6.1 | | --opt | st-flash | Optimisation can be enabled in order to skip flashing empty (0x00 or 0xff) bytes at
the end of binary file. This may cause some garbage data left after a flash operation.
This option was enabled by default in earlier releases. | v1.6.1 | +| --reset | st-flash | Trigger a reset both before and after flashing. | v1.0.0 | | --version | st-info,
st-flash,
st-util | Print version information. | | | --help | st-flash,
st-util | Print list of available commands. _(To be added to this table.)_ | | From 3f20a25cc0330b3a3e8093a93bba99d91227bbed Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Wed, 17 Jun 2020 15:15:33 +0200 Subject: [PATCH 045/503] Updated cmake-settings - Changed header installation path - Fix for cpack output directory --- CMakeLists.txt | 19 ++++++++----------- cmake/modules/get_version.cmake | 2 +- cmake/packaging/cpack_config.cmake | 1 + inc/CMakeLists.txt | 7 ++++--- 4 files changed, 14 insertions(+), 15 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index 82e5bf769..5171628ad 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -32,15 +32,6 @@ else () set(CMAKE_C_FLAGS_RELWITHDEBINFO_INIT "/MT /Zi /O2 /Ob1 /D NDEBUG") endif () -## Set installation directories for header files ### TODO: Clean this up... -if (IS_DIRECTORY ${INCLUDE_INSTALL_DIR}) - set(INCLUDE_INSTALL_DIR ${INCLUDE_INSTALL_DIR} CACHE PATH "Main include directory") - set(STLINK_INCLUDE_PATH "${INCLUDE_INSTALL_DIR}") -else () - set(INCLUDE_INSTALL_DIR "include" CACHE PATH "Main include directory") - set(STLINK_INCLUDE_PATH "${CMAKE_INSTALL_PREFIX}/${INCLUDE_INSTALL_DIR}") -endif () - ### # Dependencies @@ -94,12 +85,19 @@ include_directories(src) include_directories(src/st-flash) include_directories(src/stlink-lib) +## Set installation directory for header files +set(STLINK_INCLUDE_PATH ${CMAKE_INSTALL_INCLUDEDIR} CACHE PATH "Main include install directory") + +## Subordinate CMakeLists for version config & header installation +add_subdirectory(inc) + +## Define source- and headerfiles for stlink library set(STLINK_HEADERS inc/backend.h + inc/stlink.h src/stlink-lib/commands.h src/stlink-lib/libusb_settings.h src/stlink-lib/reg.h - inc/stlink.h src/stlink-lib/chipid.h src/stlink-lib/flash_loader.h src/stlink-lib/logging.h @@ -279,7 +277,6 @@ endif () # Additional build tasks ### -add_subdirectory(inc) # contains subordinate CMakeLists for version config add_subdirectory(src/stlink-gui) # contains subordinate CMakeLists to build GUI add_subdirectory(tests) # contains subordinate CMakeLists to build test executables add_subdirectory(cmake/packaging) # contains subordinate CMakeLists to build packages diff --git a/cmake/modules/get_version.cmake b/cmake/modules/get_version.cmake index dddb35549..70fbde816 100644 --- a/cmake/modules/get_version.cmake +++ b/cmake/modules/get_version.cmake @@ -52,7 +52,7 @@ if (GIT_FOUND AND EXISTS "${PROJECT_SOURCE_DIR}/.git") # ...the version does not match with git-version string if (NOT __version_str STREQUAL __version_file) - message(STATUS "Rewrite ${PROJECT_SOURCE_DIR}/.version with ${__version_str}.") + message(STATUS "Rewrite ${PROJECT_SOURCE_DIR}/.version with ${__version_str}!") endif () else (NOT EXISTS "${PROJECT_SOURCE_DIR}/.version") diff --git a/cmake/packaging/cpack_config.cmake b/cmake/packaging/cpack_config.cmake index f36a50b40..469e743ca 100644 --- a/cmake/packaging/cpack_config.cmake +++ b/cmake/packaging/cpack_config.cmake @@ -12,6 +12,7 @@ set(CPACK_PACKAGE_VENDOR "stlink-org") set(CMAKE_PROJECT_HOMEPAGE_URL "https://github.com/stlink-org/stlink") set(CPACK_SET_DESTDIR "ON") +file(MAKE_DIRECTORY ${CMAKE_BINARY_DIR}/dist) set(CPACK_OUTPUT_FILE_PREFIX "${CMAKE_BINARY_DIR}/dist") if (APPLE) # macOS diff --git a/inc/CMakeLists.txt b/inc/CMakeLists.txt index 66af7e33f..c816c7044 100644 --- a/inc/CMakeLists.txt +++ b/inc/CMakeLists.txt @@ -3,7 +3,8 @@ configure_file( "${CMAKE_BINARY_DIR}/inc/version.h" ) -file(GLOB STLINK_HEADERS "src/st-link-lib/*.h" "${CMAKE_BINARY_DIR}/inc/version.h") +file(GLOB STLINK_HEADERS + "${CMAKE_SOURCE_DIR}/inc/*.h" + "${CMAKE_SOURCE_DIR}/src/stlink-lib/*.h" + "${CMAKE_BINARY_DIR}/inc/version.h") install(FILES ${STLINK_HEADERS} DESTINATION ${STLINK_INCLUDE_PATH}) -install(FILES ${CMAKE_SOURCE_DIR}/inc/stlink.h DESTINATION ${STLINK_INCLUDE_PATH}) -install(FILES ${CMAKE_SOURCE_DIR}/inc/stm32.h DESTINATION ${STLINK_INCLUDE_PATH}) From ae0db2da1517ba0fc6273d8bb4b04a076e971cba Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Wed, 17 Jun 2020 17:19:58 +0200 Subject: [PATCH 046/503] st-info: Fixed width int sizes for casting --- src/st-info/info.c | 25 +++++++++---------------- 1 file changed, 9 insertions(+), 16 deletions(-) diff --git a/src/st-info/info.c b/src/st-info/info.c index 1bc48a05e..2343140de 100644 --- a/src/st-info/info.c +++ b/src/st-info/info.c @@ -28,12 +28,9 @@ static void stlink_print_serial(stlink_t *sl, bool openocd) { fmt = "%02x"; } - for (int n = 0; n < sl->serial_size; n++) - printf(fmt, sl->serial[n]); + for (int n = 0; n < sl->serial_size; n++) { printf(fmt, sl->serial[n]); } - if (openocd) { - printf("\""); - } + if (openocd) { printf("\""); } printf("\n"); } @@ -41,19 +38,15 @@ static void stlink_print_serial(stlink_t *sl, bool openocd) { static void stlink_print_info(stlink_t *sl) { const struct stlink_chipid_params *params = NULL; - if (!sl) { - return; - } + if (!sl) { return; } printf(" serial: "); stlink_print_serial(sl, false); printf(" hla-serial: "); stlink_print_serial(sl, true); - printf(" flash: %u (pagesize: %u)\n", - (unsigned int)sl->flash_size, (unsigned int)sl->flash_pgsz); - - printf(" sram: %u\n", (unsigned int)sl->sram_size); + (uint32_t)sl->flash_size, (uint32_t)sl->flash_pgsz); + printf(" sram: %u\n", (uint32_t)sl->sram_size); printf(" chipid: 0x%.4x\n", sl->chip_id); params = stlink_chipid_get_params(sl->chip_id); @@ -69,7 +62,7 @@ static void stlink_probe(void) { printf("Found %u stlink programmers\n", (unsigned int)size); - for (size_t n = 0; n < size; n++) stlink_print_info(stdevs[n]); + for (size_t n = 0; n < size; n++) { stlink_print_info(stdevs[n]); } stlink_probe_usb_free(&stdevs, size); } @@ -126,11 +119,11 @@ static int print_data(int ac, char **av) { } else if (strcmp(av[1], "--hla-serial") == 0) { stlink_print_serial(sl, true); } else if (strcmp(av[1], "--flash") == 0) { - printf("0x%x\n", (unsigned int)sl->flash_size); + printf("0x%x\n", (uint32_t)sl->flash_size); } else if (strcmp(av[1], "--pagesize") == 0) { - printf("0x%x\n", (unsigned int)sl->flash_pgsz); + printf("0x%x\n", (uint32_t)sl->flash_pgsz); } else if (strcmp(av[1], "--sram") == 0) { - printf("0x%x\n", (unsigned int)sl->sram_size); + printf("0x%x\n", (uint32_t)sl->sram_size); } else if (strcmp(av[1], "--chipid") == 0) { printf("0x%.4x\n", sl->chip_id); } else if (strcmp(av[1], "--descr") == 0) { From 2952859d61903f99555a7736e60b3237fbe0132a Mon Sep 17 00:00:00 2001 From: Geoffrey Brown Date: Wed, 17 Jun 2020 17:16:58 -0400 Subject: [PATCH 047/503] change timeout on flash write --- src/stlink-lib/flash_loader.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/stlink-lib/flash_loader.c b/src/stlink-lib/flash_loader.c index 71601e3da..0e79c3c0a 100644 --- a/src/stlink-lib/flash_loader.c +++ b/src/stlink-lib/flash_loader.c @@ -360,11 +360,11 @@ int stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t targe * the OS uses, the wait until the error message is reduced to the same order of magnitude * as what was intended. -- REW. */ -#define WAIT_ROUNDS 100 +#define WAIT_ROUNDS 30 // wait until done (reaches breakpoint) for (i = 0; i < WAIT_ROUNDS; i++) { - usleep(1000); + usleep(10000); if (stlink_is_core_halted(sl)) { break; } } From 1541dfcb0bfa3984e54b599d6b7d13c3f26c65d7 Mon Sep 17 00:00:00 2001 From: Oleksiy Slyshyk Date: Thu, 18 Jun 2020 17:17:51 +0300 Subject: [PATCH 048/503] fix #988 --- src/common.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/common.c b/src/common.c index 361a24dbf..3459a53a0 100644 --- a/src/common.c +++ b/src/common.c @@ -1624,7 +1624,7 @@ static int map_file(mapped_file_t* mf, const char* path) { if (sizeof(st.st_size) != sizeof(size_t)) { // on 32 bit systems, check if there is an overflow - if (st.st_size > (off_t)UINT32_MAX) { + if (st.st_size > (off_t)INT32_MAX) { fprintf(stderr, "mmap() size_t overflow for file %s\n", path); goto on_error; } From 54e5627a269dddcd00fd1476f7dee62c5b207a52 Mon Sep 17 00:00:00 2001 From: Jan Bramkamp Date: Sat, 20 Jun 2020 01:44:25 +0200 Subject: [PATCH 049/503] Add support for FreeBSD's libusb reimplementation FreeBSD reimplemented the libusb API, but their implementation of libusb_set_debug() expects an enum libusb_debug_level instead of an enum libusb_log_level. This causes excessive logging on FreeBSD drowning out all expected output. To keep the changes to other platforms minimal the FreeBSD specific code is kept inside an ifdef block and the enum values are recreated as magic numbers just like the log levels for other platforms. --- src/stlink-lib/logging.c | 25 +++++++++++++++++++------ 1 file changed, 19 insertions(+), 6 deletions(-) diff --git a/src/stlink-lib/logging.c b/src/stlink-lib/logging.c index a5eef9e17..744f1759d 100644 --- a/src/stlink-lib/logging.c +++ b/src/stlink-lib/logging.c @@ -66,12 +66,25 @@ int ugly_log(int level, const char *tag, const char *format, ...) { * - LIBUSB_LOG_LEVEL_DEBUG (4) : debug and informational messages are printed to stderr */ int ugly_libusb_log_level(enum ugly_loglevel v) { +#if __FreeBSD__ + // FreeBSD includes its own reimplementation of libusb. + // Its libusb_set_debug() function expects a lib_debug_level + // instead of a lib_log_level and is verbose enough to drown out + // all other output. switch (v) { - case UDEBUG: return(4); - case UINFO: return(3); - case UWARN: return(2); - case UERROR: return(1); + case UDEBUG: return (3); // LIBUSB_DEBUG_FUNCTION + LIBUSB_DEBUG_TRANSFER + case UINFO: return (1); // LIBUSB_DEBUG_FUNCTION only + case UWARN: return (0); // LIBUSB_DEBUG_NO + case UERROR: return (0); // LIBUSB_DEBUG_NO } - - return(2); + return (0); +#else + switch (v) { + case UDEBUG: return (4); + case UINFO: return (3); + case UWARN: return (2); + case UERROR: return (1); + } + return (2); +#endif } From 44c7de765fdae723c5e3fda1268f5df5f4587b7b Mon Sep 17 00:00:00 2001 From: Luca Boccassi Date: Sun, 21 Jun 2020 13:23:44 +0100 Subject: [PATCH 050/503] Update d/copyright to remove GPL-2+ stanza about flashloaders The 2 loaders were rewritten from scratch --- debian/copyright | 22 ---------------------- 1 file changed, 22 deletions(-) diff --git a/debian/copyright b/debian/copyright index cf13a5b4f..98af5a9d0 100644 --- a/debian/copyright +++ b/debian/copyright @@ -153,25 +153,3 @@ License: BSD-3-clause THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -Files: flashloaders/stm32l0x.s - flashloaders/stm32lx.s -Copyright: 2010 Spencer Oliver - 2011 Øyvind Harboe - 2011 Clement Burin des Roziers -License: GPL-2+ - This package is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - . - This package is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - . - You should have received a copy of the GNU General Public License - along with this program. If not, see - . - On Debian systems, the complete text of the GNU General - Public License version 2 can be found in "/usr/share/common-licenses/GPL-2". From 1195dae9e549fe0b474fe11a2b58bfcb2a31dab5 Mon Sep 17 00:00:00 2001 From: Luca Boccassi Date: Sun, 21 Jun 2020 13:24:37 +0100 Subject: [PATCH 051/503] Update upstream URLs for new Github org --- debian/control | 2 +- debian/copyright | 2 +- debian/watch | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/debian/control b/debian/control index 7172583e9..3ac6af91f 100644 --- a/debian/control +++ b/debian/control @@ -5,7 +5,7 @@ Build-Depends: debhelper-compat (= 12), cmake (>= 3.4.2), libusb-1.0-0-dev, libg Standards-Version: 4.5.0 Rules-Requires-Root: no Section: electronics -Homepage: https://github.com/texane/stlink +Homepage: https://github.com/stlink-org/stlink Vcs-Git: https://github.com/bluca/stlink.git -b debian Vcs-Browser: https://github.com/bluca/stlink diff --git a/debian/copyright b/debian/copyright index 98af5a9d0..1a0febd9c 100644 --- a/debian/copyright +++ b/debian/copyright @@ -1,7 +1,7 @@ Format: https://www.debian.org/doc/packaging-manuals/copyright-format/1.0/ Upstream-Name: stlink Upstream-Contact: Andrew 'Necromant' Andrianov -Source: https://github.com/texane/stlink +Source: https://github.com/stlink-org/stlink Comment: Upstream tarball has been repackaged to remove binary OSX kernel drivers that are of unknown license and of no use to Debian. Files-Excluded: stlinkv1_macos_driver diff --git a/debian/watch b/debian/watch index 45fece19b..6eb6b78d6 100644 --- a/debian/watch +++ b/debian/watch @@ -1,3 +1,3 @@ version=3 opts=dversionmangle=s/\+ds$//,repacksuffix=+ds,filenamemangle=s/.+\/v?(\d\S+)\.tar\.gz/stlink-$1\.tar\.gz/ \ - https://github.com/texane/stlink/tags .*/v?(\d\S+)\.tar\.gz + https://github.com/stlink-org/stlink/tags .*/v?(\d\S+)\.tar\.gz From 9fd796c0ffebe746b4383382161ee946c49889e6 Mon Sep 17 00:00:00 2001 From: Luca Boccassi Date: Sun, 21 Jun 2020 13:32:09 +0100 Subject: [PATCH 052/503] Patch CMake's hard-coded define of XML gui file location Closes: #963219 --- debian/patches/guipath.patch | 11 +++++++++++ debian/patches/series | 1 + 2 files changed, 12 insertions(+) create mode 100644 debian/patches/guipath.patch create mode 100644 debian/patches/series diff --git a/debian/patches/guipath.patch b/debian/patches/guipath.patch new file mode 100644 index 000000000..d3effc92b --- /dev/null +++ b/debian/patches/guipath.patch @@ -0,0 +1,11 @@ +--- a/src/stlink-gui/CMakeLists.txt ++++ b/src/stlink-gui/CMakeLists.txt +@@ -32,7 +32,7 @@ + add_executable(stlink-gui ${GUI_SOURCES}) + install(FILES stlink-gui.ui DESTINATION ${CMAKE_INSTALL_BINDIR}) + set_target_properties(stlink-gui PROPERTIES +- COMPILE_DEFINITIONS STLINK_UI_DIR="${CMAKE_INSTALL_PREFIX}/bin") ++ COMPILE_DEFINITIONS STLINK_UI_DIR="/usr/share/stlink") + target_link_libraries(stlink-gui ${STLINK_LIB_SHARED} ${SSP_LIB} ${GTK3_LDFLAGS}) + install(TARGETS stlink-gui DESTINATION ${CMAKE_INSTALL_BINDIR}) + diff --git a/debian/patches/series b/debian/patches/series new file mode 100644 index 000000000..1fdcf9977 --- /dev/null +++ b/debian/patches/series @@ -0,0 +1 @@ +guipath.patch From a741f41552927bae5580c06ae63dfe674765a5a6 Mon Sep 17 00:00:00 2001 From: Luca Boccassi Date: Sun, 21 Jun 2020 13:41:52 +0100 Subject: [PATCH 053/503] Update changelog for 1.6.1+ds-2 release --- debian/changelog | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/debian/changelog b/debian/changelog index 26f17b1fb..f1265ee32 100644 --- a/debian/changelog +++ b/debian/changelog @@ -1,3 +1,12 @@ +stlink (1.6.1+ds-2) unstable; urgency=medium + + * Update d/copyright to remove GPL-2+ stanza about flashloaders + * Update upstream URLs for new Github org + * Patch CMake's hard-coded define of XML gui file location (Closes: + #963219) + + -- Luca Boccassi Sun, 21 Jun 2020 13:41:37 +0100 + stlink (1.6.1+ds-1) unstable; urgency=medium * Merge tag 'v1.6.1' into debian From ff263131cf0d00657c308402762cdd591d313d5e Mon Sep 17 00:00:00 2001 From: Jan Bramkamp Date: Sun, 21 Jun 2020 16:40:51 +0200 Subject: [PATCH 054/503] Use #ifdef instead of #if --- src/stlink-lib/logging.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/stlink-lib/logging.c b/src/stlink-lib/logging.c index 744f1759d..ce0a2baab 100644 --- a/src/stlink-lib/logging.c +++ b/src/stlink-lib/logging.c @@ -66,7 +66,7 @@ int ugly_log(int level, const char *tag, const char *format, ...) { * - LIBUSB_LOG_LEVEL_DEBUG (4) : debug and informational messages are printed to stderr */ int ugly_libusb_log_level(enum ugly_loglevel v) { -#if __FreeBSD__ +#ifdef __FreeBSD__ // FreeBSD includes its own reimplementation of libusb. // Its libusb_set_debug() function expects a lib_debug_level // instead of a lib_log_level and is verbose enough to drown out From c1ea72d842702160173504f4e5869b55b8e986d7 Mon Sep 17 00:00:00 2001 From: Rutger Hendriks Date: Thu, 25 Jun 2020 10:48:51 +0200 Subject: [PATCH 055/503] Add support for writing option bytes to the Nucleo 144 STM32F767ZI. This adds --area=option_boot_add, --area=optcr and --area=optcr1 --- include/stlink.h | 14 +- include/stlink/tools/flash.h | 2 +- include/stm32.h | 1 + src/chipid.c | 14 +- src/common.c | 560 +++++++++++++++++++++++++++++++++-- src/flash_loader.c | 20 +- src/tools/flash.c | 131 +++++--- src/tools/flash_opts.c | 110 +++++-- src/usb.c | 1 + 9 files changed, 750 insertions(+), 103 deletions(-) diff --git a/include/stlink.h b/include/stlink.h index c87c6b173..c96cf2ef9 100644 --- a/include/stlink.h +++ b/include/stlink.h @@ -120,7 +120,8 @@ enum stlink_flash_type { STLINK_FLASH_TYPE_UNKNOWN = 0, STLINK_FLASH_TYPE_F0, // used by f0, f1 (except f1xl),f3. */ STLINK_FLASH_TYPE_F1_XL, // f0 flash with dual bank, apparently */ - STLINK_FLASH_TYPE_F4, // used by f2, f4, f7 */ + STLINK_FLASH_TYPE_F4, // used by f2, f4 */ + STLINK_FLASH_TYPE_F7, STLINK_FLASH_TYPE_L0, // l0, l1 */ STLINK_FLASH_TYPE_L4, // l4, l4+ */ STLINK_FLASH_TYPE_G0, @@ -146,8 +147,8 @@ struct stlink_reg { typedef uint32_t stm32_addr_t; typedef struct flash_loader { -stm32_addr_t loader_addr; // loader sram addr -stm32_addr_t buf_addr; // buffer sram address + stm32_addr_t loader_addr; // loader sram addr + stm32_addr_t buf_addr; // buffer sram address } flash_loader_t; typedef struct _cortex_m3_cpuid_ { @@ -288,7 +289,14 @@ int stlink_fread(stlink_t* sl, const char* path, bool is_ihex, stm32_addr_t addr int stlink_load_device_params(stlink_t *sl); int stlink_read_option_bytes32(stlink_t *sl, uint32_t* option_byte); +int stlink_read_option_bytes_boot_add32(stlink_t *sl, uint32_t* option_byte); +int stlink_read_option_control_register32(stlink_t *sl, uint32_t* option_byte); +int stlink_read_option_control_register1_32(stlink_t *sl, uint32_t* option_byte); + int stlink_write_option_bytes32(stlink_t *sl, uint32_t option_byte); +int stlink_write_option_bytes_boot_add32(stlink_t *sl, uint32_t option_bytes_boot_add); +int stlink_write_option_control_register32(stlink_t *sl, uint32_t option_control_register); +int stlink_write_option_control_register1_32(stlink_t *sl, uint32_t option_control_register1); int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t len); int stlink_fwrite_option_bytes(stlink_t *sl, const char* path, stm32_addr_t addr); diff --git a/include/stlink/tools/flash.h b/include/stlink/tools/flash.h index a912a14aa..e5b4d2572 100644 --- a/include/stlink/tools/flash.h +++ b/include/stlink/tools/flash.h @@ -11,7 +11,7 @@ enum flash_cmd {FLASH_CMD_NONE = 0, FLASH_CMD_WRITE = 1, FLASH_CMD_READ = 2, FLASH_CMD_ERASE = 3, CMD_RESET = 4}; enum flash_format {FLASH_FORMAT_BINARY = 0, FLASH_FORMAT_IHEX = 1}; -enum flash_area {FLASH_MAIN_MEMORY = 0, FLASH_SYSTEM_MEMORY = 1,FLASH_OTP = 2, FLASH_OPTION_BYTES = 3}; +enum flash_area {FLASH_MAIN_MEMORY = 0, FLASH_SYSTEM_MEMORY = 1, FLASH_OTP = 2, FLASH_OPTION_BYTES = 3, FLASH_OPTION_BYTES_BOOT_ADD = 4, FLASH_OPTCR = 5, FLASH_OPTCR1 = 6}; struct flash_opts { enum flash_cmd cmd; diff --git a/include/stm32.h b/include/stm32.h index c71718653..be5bb5bc7 100644 --- a/include/stm32.h +++ b/include/stm32.h @@ -20,5 +20,6 @@ #define STM32_F2_OPTION_BYTES_BASE ((uint32_t)0x1FFFC000) #define STM32_L4_OPTION_BYTES_BASE ((uint32_t)0x1FFF7800) #define STM32_L1_OPTION_BYTES_BASE ((uint32_t)0x1FF80000) +#define STM32_F7_OPTION_BYTES_BASE ((uint32_t)0x1FFF0000) #endif /* STM32_H */ diff --git a/src/chipid.c b/src/chipid.c index fcc1c55eb..abddb7dc5 100644 --- a/src/chipid.c +++ b/src/chipid.c @@ -6,12 +6,14 @@ static const struct stlink_chipid_params devices[] = { //RM0410 document was used to find these paramaters .chip_id = STLINK_CHIPID_STM32_F7XXXX, .description = "F76xxx", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1ff0f442, // section 45.2 - .flash_pagesize = 0x800, // No flash pages - .sram_size = 0x80000, // "SRAM" byte size in hex from - .bootrom_base = 0x00200000, //! "System memory" starting address from - .bootrom_size = 0xEDC0 //! @todo "System memory" byte size in hex from + .flash_type = STLINK_FLASH_TYPE_F7, + .flash_size_reg = 0x1ff0f442, // section 45.2 + .flash_pagesize = 0x800, // No flash pages + .sram_size = 0x80000, // "SRAM" byte size in hex from + .bootrom_base = 0x00200000, //! "System memory" starting address from + .bootrom_size = 0xEDC0, //! @todo "System memory" byte size in hex from + .option_base = STM32_F7_OPTION_BYTES_BASE, // Used for reading back the option bytes, writing uses FLASH_F7_OPTCR and FLASH_F7_OPTCR1 + .option_size = 0x20 }, { //RM0385 and DS10916 document was used to find these paramaters diff --git a/src/common.c b/src/common.c index e8f7cebc6..0c3b0fe69 100644 --- a/src/common.c +++ b/src/common.c @@ -236,6 +236,33 @@ #define FLASH_OBR_OFF ((uint32_t) 0x1c) #define FLASH_WRPR_OFF ((uint32_t) 0x20) +//STM32F7 +#define FLASH_F7_REGS_ADDR ((uint32_t)0x40023c00) +#define FLASH_F7_KEYR (FLASH_F7_REGS_ADDR + 0x04) +#define FLASH_F7_OPT_KEYR (FLASH_F7_REGS_ADDR + 0x08) +#define FLASH_F7_SR (FLASH_F7_REGS_ADDR + 0x0c) +#define FLASH_F7_CR (FLASH_F7_REGS_ADDR + 0x10) +#define FLASH_F7_OPTCR (FLASH_F7_REGS_ADDR + 0x14) +#define FLASH_F7_OPTCR1 (FLASH_F7_REGS_ADDR + 0x18) +#define FLASH_F7_OPTCR_LOCK 0 +#define FLASH_F7_OPTCR_START 1 +#define FLASH_F7_CR_STRT 16 +#define FLASH_F7_CR_LOCK 31 +#define FLASH_F7_CR_SER 1 +#define FLASH_F7_CR_SNB 3 +#define FLASH_F7_CR_SNB_MASK 0xf8 +#define FLASH_F7_SR_BSY 16 +#define FLASH_F7_SR_ERS_ERR 7 /* Erase Sequence Error */ +#define FLASH_F7_SR_PGP_ERR 6 /* Programming parallelism error */ +#define FLASH_F7_SR_PGA_ERR 5 /* Programming alignment error */ +#define FLASH_F7_SR_WRP_ERR 4 /* Write protection error */ +#define FLASH_F7_SR_OP_ERR 1 /* Operation error */ +#define FLASH_F7_SR_EOP 0 /* End of operation */ +#define FLASH_F7_OPTCR1_BOOT_ADD0 0 +#define FLASH_F7_OPTCR1_BOOT_ADD1 16 + +#define FLASH_F7_SR_ERROR_MASK ((1 << FLASH_F7_SR_ERS_ERR) | (1 << FLASH_F7_SR_PGP_ERR) | (1 << FLASH_F7_SR_PGA_ERR) | (1 << FLASH_F7_SR_WRP_ERR) | (1 << FLASH_F7_SR_OP_ERR)) + //STM32F4 #define FLASH_F4_REGS_ADDR ((uint32_t)0x40023c00) #define FLASH_F4_KEYR (FLASH_F4_REGS_ADDR + 0x04) @@ -337,6 +364,8 @@ static inline uint32_t read_flash_cr(stlink_t *sl) { if (sl->flash_type == STLINK_FLASH_TYPE_F4) reg = FLASH_F4_CR; + else if (sl->flash_type == STLINK_FLASH_TYPE_F7) + reg = FLASH_F7_CR; else if (sl->flash_type == STLINK_FLASH_TYPE_L4) reg = STM32L4_FLASH_CR; else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || @@ -377,6 +406,9 @@ static inline unsigned int is_flash_locked(stlink_t *sl) { } else if (sl->flash_type == STLINK_FLASH_TYPE_F4) { cr_reg = FLASH_F4_CR; cr_lock_shift = FLASH_F4_CR_LOCK; + } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { + cr_reg = FLASH_F7_CR; + cr_lock_shift = FLASH_F7_CR_LOCK; } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { cr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF; cr_lock_shift = STM32L0_FLASH_PELOCK; @@ -414,6 +446,8 @@ static void unlock_flash(stlink_t *sl) { key_reg = FLASH_KEYR; } else if (sl->flash_type == STLINK_FLASH_TYPE_F4) { key_reg = FLASH_F4_KEYR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { + key_reg = FLASH_F7_KEYR; } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { key_reg = get_stm32l0_flash_base(sl) + FLASH_PEKEYR_OFF; flash_key1 = FLASH_L0_PEKEY1; @@ -462,6 +496,9 @@ static void lock_flash(stlink_t *sl) { } else if (sl->flash_type == STLINK_FLASH_TYPE_F4) { cr_reg = FLASH_F4_CR; cr_lock_shift = FLASH_F4_CR_LOCK; + } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { + cr_reg = FLASH_F7_CR; + cr_lock_shift = FLASH_F7_CR_LOCK; } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { cr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF; cr_lock_shift = STM32L0_FLASH_PELOCK; @@ -506,6 +543,10 @@ static bool is_flash_option_locked(stlink_t *sl) { optcr_reg = FLASH_F4_OPTCR; optlock_shift = FLASH_F4_OPTCR_LOCK; break; + case STLINK_FLASH_TYPE_F7: + optcr_reg = FLASH_F7_OPTCR; + optlock_shift = FLASH_F7_OPTCR_LOCK; + break; case STLINK_FLASH_TYPE_L0: optcr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF; optlock_shift = STM32L0_FLASH_OPTLOCK; @@ -551,6 +592,10 @@ static int lock_flash_option(stlink_t *sl) { optcr_reg = FLASH_F4_OPTCR; optlock_shift = FLASH_F4_OPTCR_LOCK; break; + case STLINK_FLASH_TYPE_F7: + optcr_reg = FLASH_F7_OPTCR; + optlock_shift = FLASH_F7_OPTCR_LOCK; + break; case STLINK_FLASH_TYPE_L0: optcr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF; optlock_shift = STM32L0_FLASH_OPTLOCK; @@ -599,6 +644,9 @@ static int unlock_flash_option(stlink_t *sl) case STLINK_FLASH_TYPE_F4: optkey_reg = FLASH_F4_OPT_KEYR; break; + case STLINK_FLASH_TYPE_F7: + optkey_reg = FLASH_F7_OPT_KEYR; + break; case STLINK_FLASH_TYPE_L0: optkey_reg = get_stm32l0_flash_base(sl) + FLASH_OPTKEYR_OFF; optkey1 = FLASH_L0_OPTKEY1; @@ -649,6 +697,9 @@ static void set_flash_cr_pg(stlink_t *sl) { if (sl->flash_type == STLINK_FLASH_TYPE_F4) { cr_reg = FLASH_F4_CR; x |= 1 << FLASH_CR_PG; + } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { + cr_reg = FLASH_F7_CR; + x |= 1 << FLASH_CR_PG; } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { cr_reg = STM32L4_FLASH_CR; x &= ~STM32L4_FLASH_CR_OPBITS; @@ -673,6 +724,8 @@ static void clear_flash_cr_pg(stlink_t *sl) { if (sl->flash_type == STLINK_FLASH_TYPE_F4) cr_reg = FLASH_F4_CR; + else if (sl->flash_type == STLINK_FLASH_TYPE_F7) + cr_reg = FLASH_F7_CR; else if (sl->flash_type == STLINK_FLASH_TYPE_L4) cr_reg = STM32L4_FLASH_CR; else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || @@ -730,6 +783,10 @@ static void set_flash_cr_mer(stlink_t *sl, bool v) { cr_reg = FLASH_F4_CR; cr_mer = 1 << FLASH_CR_MER; cr_pg = 1 << FLASH_CR_PG; + } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { + cr_reg = FLASH_F7_CR; + cr_mer = 1 << FLASH_CR_MER; + cr_pg = 1 << FLASH_CR_PG; } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { cr_reg = STM32L4_FLASH_CR; cr_mer = (1 << STM32L4_FLASH_CR_MER1) | (1 << STM32L4_FLASH_CR_MER2); @@ -786,6 +843,9 @@ static void __attribute__((unused)) clear_flash_cr_mer(stlink_t *sl) { if (sl->flash_type == STLINK_FLASH_TYPE_F4) { cr_reg = FLASH_F4_CR; cr_mer = 1 << FLASH_CR_MER; + } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { + cr_reg = FLASH_F7_CR; + cr_mer = 1 << FLASH_CR_MER; } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { cr_reg = STM32L4_FLASH_CR; cr_mer = (1 << STM32L4_FLASH_CR_MER1) | (1 << STM32L4_FLASH_CR_MER2); @@ -805,6 +865,9 @@ static void set_flash_cr_strt(stlink_t *sl) { if (sl->flash_type == STLINK_FLASH_TYPE_F4) { cr_reg = FLASH_F4_CR; cr_strt = 1 << FLASH_F4_CR_STRT; + } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { + cr_reg = FLASH_F7_CR; + cr_strt = 1 << FLASH_F7_CR_STRT; } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { cr_reg = STM32L4_FLASH_CR; cr_strt = 1 << STM32L4_FLASH_CR_STRT; @@ -842,6 +905,8 @@ static inline uint32_t read_flash_sr(stlink_t *sl) { sr_reg = get_stm32l0_flash_base(sl) + FLASH_SR_OFF; } else if (sl->flash_type == STLINK_FLASH_TYPE_F4) { sr_reg = FLASH_F4_SR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { + sr_reg = FLASH_F7_SR; } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { sr_reg = STM32L4_FLASH_SR; } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || @@ -873,6 +938,8 @@ static inline unsigned int is_flash_busy(stlink_t *sl) { sr_busy_shift = FLASH_SR_BSY; } else if (sl->flash_type == STLINK_FLASH_TYPE_F4) { sr_busy_shift = FLASH_F4_SR_BSY; + } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { + sr_busy_shift = FLASH_F7_SR_BSY; } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { sr_busy_shift = STM32L4_FLASH_SR_BSY; } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || @@ -919,17 +986,20 @@ static int check_flash_error(stlink_t *sl) { uint32_t res = 0; switch (sl->flash_type) { - case STLINK_FLASH_TYPE_F0: - res = read_flash_sr(sl) & FLASH_SR_ERROR_MASK; - break; - case STLINK_FLASH_TYPE_G0: - case STLINK_FLASH_TYPE_G4: - res = read_flash_sr(sl) & STM32Gx_FLASH_SR_ERROR_MASK; - break; - case STLINK_FLASH_TYPE_L0: - res = read_flash_sr(sl) & STM32L0_FLASH_SR_ERROR_MASK; - default: - break; + case STLINK_FLASH_TYPE_F0: + res = read_flash_sr(sl) & FLASH_SR_ERROR_MASK; + break; + case STLINK_FLASH_TYPE_F7: + res = read_flash_sr(sl) & FLASH_F7_SR_ERROR_MASK; + break; + case STLINK_FLASH_TYPE_G0: + case STLINK_FLASH_TYPE_G4: + res = read_flash_sr(sl) & STM32Gx_FLASH_SR_ERROR_MASK; + break; + case STLINK_FLASH_TYPE_L0: + res = read_flash_sr(sl) & STM32L0_FLASH_SR_ERROR_MASK; + default: + break; } if (res) { @@ -1311,13 +1381,13 @@ int stlink_read_debug32(stlink_t *sl, uint32_t addr, uint32_t *data) { ret = sl->backend->read_debug32(sl, addr, data); if (!ret) - DLOG("*** stlink_read_debug32 %x is %#x\n", *data, addr); + DLOG("*** stlink_read_debug32 %#010x at %#010x\n", *data, addr); return ret; } int stlink_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data) { - DLOG("*** stlink_write_debug32 %x to %#x\n", data, addr); + DLOG("*** stlink_write_debug32 %#010x to %#010x\n", data, addr); return sl->backend->write_debug32(sl, addr, data); } @@ -1522,9 +1592,11 @@ void stlink_print_data(stlink_t * sl) { fprintf(stdout, "\n-> 0x%08x ", sl->q_addr + i); */ } - DLOG(" %02x", (unsigned int) sl->q_buf[i]); + //DLOG(" %02x", (unsigned int) sl->q_buf[i]); + fprintf(stderr, " %02x", (unsigned int) sl->q_buf[i]); } - DLOG("\n\n"); + //DLOG("\n\n"); + fprintf(stderr, "\n"); } /* memory mapped file */ @@ -1913,7 +1985,7 @@ static bool stlink_fread_ihex_finalize(struct stlink_fread_ihex_worker_arg* the_ int stlink_fread(stlink_t* sl, const char* path, bool is_ihex, stm32_addr_t addr, size_t size) { /* read size bytes from addr to file */ - + ILOG("read from address %#010x size %d\n", addr, size); int error; int fd = open(path, O_RDWR | O_TRUNC | O_CREAT | O_BINARY, 00700); @@ -2044,6 +2116,7 @@ uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr){ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { if (sl->flash_type == STLINK_FLASH_TYPE_F4 || + sl->flash_type == STLINK_FLASH_TYPE_F7 || sl->flash_type == STLINK_FLASH_TYPE_L4) { /* wait for ongoing op to finish */ wait_flash_busy(sl); @@ -2487,10 +2560,12 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t if (eraseonly) return 0; - if ((sl->flash_type == STLINK_FLASH_TYPE_F4) || (sl->flash_type == STLINK_FLASH_TYPE_L4)) { + if ((sl->flash_type == STLINK_FLASH_TYPE_F4) || + (sl->flash_type == STLINK_FLASH_TYPE_F7) || + (sl->flash_type == STLINK_FLASH_TYPE_L4)) { /* todo: check write operation */ - ILOG("Starting Flash write for F2/F4/L4\n"); + ILOG("Starting Flash write for F2/F4/F7/L4\n"); /* flash loader initialization */ if (stlink_flash_loader_init(sl, &fl) == -1) { ELOG("stlink_flash_loader_init() == -1\n"); @@ -3117,13 +3192,62 @@ static int stlink_write_option_bytes_f4(stlink_t *sl, uint8_t* base, stm32_addr_ return ret; } +/** + * Write option bytes + * @param sl + * @param option_byte value to write + * @return 0 on success, -ve on failure. + */ +static int stlink_write_option_bytes_f7(stlink_t *sl, uint8_t* base, stm32_addr_t addr, uint32_t len) { + uint32_t option_byte; + int ret = 0; + + //(void) addr; + //(void) len; + + ILOG("Asked to write option byte %#10x to %#010x.\n", *(uint32_t*) (base), addr); + write_uint32((unsigned char*) &option_byte, *(uint32_t*) (base)); + ILOG("Write %d option bytes %#010x to %#010x!\n", len, option_byte, addr); + + if ( addr == 0 ) { + addr = FLASH_F7_OPTCR; + ILOG("No address provided, using %#10x\n", addr); + } + + if ( addr == FLASH_F7_OPTCR ) { + /* write option byte, ensuring we dont lock opt, and set strt bit */ + stlink_write_debug32(sl, FLASH_F7_OPTCR, (option_byte & ~(1 << FLASH_F7_OPTCR_LOCK)) | (1 << FLASH_F7_OPTCR_START)); + } else if ( addr == FLASH_F7_OPTCR1 ) { + // Read FLASH_F7_OPTCR + uint32_t oldvalue; + stlink_read_debug32(sl, FLASH_F7_OPTCR, &oldvalue); + /* write option byte */ + stlink_write_debug32(sl, FLASH_F7_OPTCR1, option_byte); + // Write FLASH_F7_OPTCR lock and start address + stlink_write_debug32(sl, FLASH_F7_OPTCR, (oldvalue & ~(1 << FLASH_F7_OPTCR_LOCK)) | (1 << FLASH_F7_OPTCR_START)); + } else { + WLOG("WIP: write %#010x to address %#010x\n", option_byte, addr); + stlink_write_debug32(sl, addr, option_byte); + } + + wait_flash_busy(sl); + + ret = check_flash_error(sl); + if (!ret) + ILOG("Wrote %d option bytes %#010x to %#010x!\n", len, *(uint32_t*) base, addr); + + /* option bytes are reloaded at reset only, no obl. */ + + return ret; +} + /** * Read option bytes * @param sl * @param option_byte value to write * @return 0 on success, -ve on failure. */ -int stlink_read_option_bytes_Gx(stlink_t *sl, uint32_t* option_byte) { +int stlink_read_option_control_register_Gx(stlink_t *sl, uint32_t* option_byte) { return stlink_read_debug32(sl, STM32Gx_FLASH_OPTR, option_byte); } @@ -3133,19 +3257,106 @@ int stlink_read_option_bytes_Gx(stlink_t *sl, uint32_t* option_byte) { * @param option_byte value to write * @return 0 on success, -ve on failure. */ -int stlink_read_option_bytes_f2(stlink_t *sl, uint32_t* option_byte) { +int stlink_read_option_bytes_Gx(stlink_t *sl, uint32_t* option_byte) { + return stlink_read_option_control_register_Gx(sl, option_byte); +} + +/** + * Read option bytes + * @param sl + * @param option_byte value to write + * @return 0 on success, -ve on failure. + */ +int stlink_read_option_control_register_f2(stlink_t *sl, uint32_t* option_byte) { return stlink_read_debug32(sl, FLASH_F2_OPT_CR, option_byte); } +/** + * Read option bytes + * @param sl + * @param option_byte value to write + * @return 0 on success, -ve on failure. + */ +int stlink_read_option_bytes_f2(stlink_t *sl, uint32_t* option_byte) { + return stlink_read_option_control_register_f2(sl, option_byte); +} + /** * Read option bytes * @param sl * @param option_byte value to read * @return 0 on success, -ve on failure. */ -int stlink_read_option_bytes_f4(stlink_t *sl, uint32_t* option_byte) { +int stlink_read_option_control_register_f4(stlink_t *sl, uint32_t* option_byte) { return stlink_read_debug32(sl, FLASH_F4_OPTCR, option_byte); } + +/** + * Read option bytes + * @param sl + * @param option_byte value to read + * @return 0 on success, -ve on failure. + */ +int stlink_read_option_bytes_f4(stlink_t *sl, uint32_t* option_byte) { + return stlink_read_option_control_register_f4(sl, option_byte); +} + +/** + * Read option bytes + * @param sl + * @param option_byte value to read + * @return 0 on success, -ve on failure. + */ +int stlink_read_option_control_register_f7(stlink_t *sl, uint32_t* option_byte) { + DLOG("@@@@ Read option control register byte from %#10x\n", FLASH_F7_OPTCR); + return stlink_read_debug32(sl, FLASH_F7_OPTCR, option_byte); +} + +/** + * Read option bytes + * @param sl + * @param option_byte value to read + * @return 0 on success, -ve on failure. + */ +int stlink_read_option_control_register1_f7(stlink_t *sl, uint32_t* option_byte) { + DLOG("@@@@ Read option control register 1 byte from %#10x\n", FLASH_F7_OPTCR1); + return stlink_read_debug32(sl, FLASH_F7_OPTCR1, option_byte); +} + +/** + * Read option bytes + * @param sl + * @param option_byte value to read + * @return 0 on success, -ve on failure. + */ +int stlink_read_option_bytes_boot_add_f7(stlink_t *sl, uint32_t* option_byte) { + DLOG("@@@@ Read option byte boot address\n"); + return stlink_read_option_control_register1_f7(sl, option_byte); +} + +/** + * Read option bytes + * @param sl + * @param option_byte value to read + * @return 0 on success, -ve on failure. + * + * Since multiple bytes can be read, we read and print all but one here + * and then return the last one just like other devices + */ +int stlink_read_option_bytes_f7(stlink_t *sl, uint32_t* option_byte) { + int err = -1; + for (uint8_t counter = 0; counter < (sl->option_size / 4 - 1); counter++) { + err = stlink_read_debug32(sl, sl->option_base + counter * sizeof(uint32_t), option_byte); + if (err == -1) { + return err; + } else { + printf("%08x\n", *option_byte); + } + } + + return stlink_read_debug32(sl, sl->option_base + (sl->option_size / 4 - 1) * sizeof(uint32_t), option_byte); +} + /** * Read first option bytes * @param sl @@ -3153,9 +3364,43 @@ int stlink_read_option_bytes_f4(stlink_t *sl, uint32_t* option_byte) { * @return 0 on success, -ve on failure. */ int stlink_read_option_bytes_generic(stlink_t *sl, uint32_t* option_byte) { + DLOG("@@@@ Read option bytes boot address from %#10x\n", sl->option_base); return stlink_read_debug32(sl, sl->option_base, option_byte); } +/** + * Read option bytes + * @param sl + * @param option_byte value to read + * @return 0 on success, -ve on failure. + */ +//int stlink_read_option_bytes_boot_add_generic(stlink_t *sl, uint32_t* option_byte) { +// DLOG("@@@@ Read option bytes boot address from %#10x\n", sl->option_base); +// return stlink_read_debug32(sl, sl->option_base, option_byte); +//} + +/** + * Read option bytes + * @param sl + * @param option_byte value to read + * @return 0 on success, -ve on failure. + */ +//int stlink_read_option_control_register_generic(stlink_t *sl, uint32_t* option_byte) { +// DLOG("@@@@ Read option control register byte from %#10x\n", sl->option_base); +// return stlink_read_debug32(sl, sl->option_base, option_byte); +//} + +/** + * Read option bytes + * @param sl + * @param option_byte value to read + * @return 0 on success, -ve on failure. + */ +//int stlink_read_option_control_register1_generic(stlink_t *sl, uint32_t* option_byte) { +// DLOG("@@@@ Read option control register 1 byte from %#10x\n", sl->option_base); +// return stlink_read_debug32(sl, sl->option_base, option_byte); +//} + /** * Read option bytes * @param sl @@ -3174,6 +3419,8 @@ int stlink_read_option_bytes32(stlink_t *sl, uint32_t* option_byte) return stlink_read_option_bytes_f2(sl, option_byte); case STLINK_CHIPID_STM32_F446: return stlink_read_option_bytes_f4(sl, option_byte); + case STLINK_CHIPID_STM32_F7XXXX: + return stlink_read_option_bytes_f7(sl, option_byte); case STLINK_CHIPID_STM32_G0_CAT1: case STLINK_CHIPID_STM32_G0_CAT2: case STLINK_CHIPID_STM32_G4_CAT2: @@ -3184,6 +3431,72 @@ int stlink_read_option_bytes32(stlink_t *sl, uint32_t* option_byte) } } +/** + * Read option bytes + * @param sl + * @param option_byte option value + * @return 0 on success, -ve on failure. + */ +int stlink_read_option_bytes_boot_add32(stlink_t *sl, uint32_t* option_byte) +{ + if (sl->option_base == 0) { + ELOG("Option bytes boot address read is currently not supported for connected chip\n"); + return -1; + } + + switch (sl->chip_id) { + case STLINK_CHIPID_STM32_F7XXXX: + return stlink_read_option_bytes_boot_add_f7(sl, option_byte); + default: + return -1; + //return stlink_read_option_bytes_boot_add_generic(sl, option_byte); + } +} + +/** + * Read option bytes + * @param sl + * @param option_byte option value + * @return 0 on success, -ve on failure. + */ +int stlink_read_option_control_register32(stlink_t *sl, uint32_t* option_byte) +{ + if (sl->option_base == 0) { + ELOG("Option bytes read is currently not supported for connected chip\n"); + return -1; + } + + switch (sl->chip_id) { + case STLINK_CHIPID_STM32_F7XXXX: + return stlink_read_option_control_register_f7(sl, option_byte); + default: + return -1; + //return stlink_read_option_control_register_generic(sl, option_byte); + } +} + +/** + * Read option bytes + * @param sl + * @param option_byte option value + * @return 0 on success, -ve on failure. + */ +int stlink_read_option_control_register1_32(stlink_t *sl, uint32_t* option_byte) +{ + if (sl->option_base == 0) { + ELOG("Option bytes read is currently not supported for connected chip\n"); + return -1; + } + + switch (sl->chip_id) { + case STLINK_CHIPID_STM32_F7XXXX: + return stlink_read_option_control_register1_f7(sl, option_byte); + default: + return -1; + //return stlink_read_option_control_register1_generic(sl, option_byte); + } +} + /** * Write option bytes * @param sl @@ -3192,7 +3505,7 @@ int stlink_read_option_bytes32(stlink_t *sl, uint32_t* option_byte) */ int stlink_write_option_bytes32(stlink_t *sl, uint32_t option_byte) { - WLOG("About to write option byte %#10x to target.\n", option_byte); + WLOG("About to write option byte %#10x to %#10x.\n", option_byte, sl->option_base); return stlink_write_option_bytes(sl, sl->option_base, (uint8_t *) &option_byte, 4); } @@ -3212,6 +3525,7 @@ int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t* base, ui return -1; } + if ((addr < sl->option_base) || addr > sl->option_base + sl->option_size) { ELOG("Option bytes start address out of Option bytes range\n"); return -1; @@ -3238,6 +3552,9 @@ int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t* base, ui case STLINK_FLASH_TYPE_F4: ret = stlink_write_option_bytes_f4(sl, base, addr, len); break; + case STLINK_FLASH_TYPE_F7: + ret = stlink_write_option_bytes_f7(sl, base, addr, len); + break; case STLINK_FLASH_TYPE_L0: ret = stlink_write_option_bytes_l0(sl, base, addr, len); break; @@ -3255,8 +3572,203 @@ int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t* base, ui if (ret) ELOG("Flash option write failed!\n"); - else - ILOG("Wrote %d option bytes to %#010x!\n", len, addr); + else + ILOG("Wrote %d option bytes to %#010x!\n", len, addr); + + /* Re-lock flash. */ + lock_flash_option(sl); + lock_flash(sl); + + return ret; +} + +/** + * Write option bytes + * @param sl + * @param option_byte value to write + * @return 0 on success, -ve on failure. + */ +static int stlink_write_option_control_register_f7(stlink_t *sl, uint32_t option_control_register) { + int ret = 0; + + ILOG("Asked to write option control register 1 %#10x to %#010x.\n", option_control_register, FLASH_F7_OPTCR); + //write_uint32((unsigned char*) &option_byte, *(uint32_t*) (base)); + //ILOG("Write %d option bytes %#010x to %#010x!\n", len, option_byte, addr); + + /* write option byte, ensuring we dont lock opt, and set strt bit */ + stlink_write_debug32(sl, FLASH_F7_OPTCR, (option_control_register & ~(1 << FLASH_F7_OPTCR_LOCK)) | (1 << FLASH_F7_OPTCR_START)); + + wait_flash_busy(sl); + + ret = check_flash_error(sl); + if (!ret) + ILOG("Wrote option bytes %#010x to %#010x!\n", option_control_register, FLASH_F7_OPTCR1); + + return ret; +} + +/** + * Write option bytes + * @param sl + * @param option_byte value to write + * @return 0 on success, -ve on failure. + */ +static int stlink_write_option_control_register1_f7(stlink_t *sl, uint32_t option_control_register1) { + int ret = 0; + + ILOG("Asked to write option control register 1 %#010x to %#010x.\n", option_control_register1, FLASH_F7_OPTCR1); + //write_uint32((unsigned char*) &option_byte, *(uint32_t*) (base)); + //ILOG("Write %d option bytes %#010x to %#010x!\n", len, option_byte, addr); + + /* write option byte, ensuring we dont lock opt, and set strt bit */ + uint32_t current_control_register_value; + stlink_read_debug32(sl, FLASH_F7_OPTCR, ¤t_control_register_value); + + /* write option byte */ + stlink_write_debug32(sl, FLASH_F7_OPTCR1, option_control_register1); + stlink_write_debug32(sl, FLASH_F7_OPTCR, (current_control_register_value & ~(1 << FLASH_F7_OPTCR_LOCK)) | (1 << FLASH_F7_OPTCR_START)); + + wait_flash_busy(sl); + + ret = check_flash_error(sl); + if (!ret) + ILOG("Wrote option bytes %#010x to %#010x!\n", option_control_register1, FLASH_F7_OPTCR1); + + return ret; +} + +/** + * Write option bytes + * @param sl + * @param option_byte value to write + * @return 0 on success, -ve on failure. + */ +static int stlink_write_option_bytes_boot_add_f7(stlink_t *sl, uint32_t option_byte_boot_add) { + ILOG("Asked to write option byte boot add %#010x.\n", option_byte_boot_add); + return stlink_write_option_control_register1_f7(sl, option_byte_boot_add); +} + +/** + * Write option bytes + * @param sl + * @param option bytes boot address to write + * @return 0 on success, -ve on failure. + */ +int stlink_write_option_bytes_boot_add32(stlink_t *sl, uint32_t option_bytes_boot_add) +{ + int ret = -1; + + wait_flash_busy(sl); + + if (unlock_flash_if(sl)) { + ELOG("Flash unlock failed! System reset required to be able to unlock it again!\n"); + return -1; + } + + if (unlock_flash_option_if(sl)) { + ELOG("Flash option unlock failed!\n"); + return -1; + } + + switch (sl->flash_type) { + case STLINK_FLASH_TYPE_F7: + ret = stlink_write_option_bytes_boot_add_f7(sl, option_bytes_boot_add); + break; + default: + ELOG("Option bytes boot address writing is currently not implemented for connected chip\n"); + break; + } + + if (ret) + ELOG("Flash option write failed!\n"); + else + ILOG("Wrote option bytes boot address %#010x!\n", option_bytes_boot_add); + + /* Re-lock flash. */ + lock_flash_option(sl); + lock_flash(sl); + + return ret; +} + +/** + * Write option bytes + * @param sl + * @param option bytes boot address to write + * @return 0 on success, -ve on failure. + */ +int stlink_write_option_control_register32(stlink_t *sl, uint32_t option_control_register) +{ + int ret = -1; + + wait_flash_busy(sl); + + if (unlock_flash_if(sl)) { + ELOG("Flash unlock failed! System reset required to be able to unlock it again!\n"); + return -1; + } + + if (unlock_flash_option_if(sl)) { + ELOG("Flash option unlock failed!\n"); + return -1; + } + + switch (sl->flash_type) { + case STLINK_FLASH_TYPE_F7: + ret = stlink_write_option_control_register_f7(sl, option_control_register); + break; + default: + ELOG("Option control register writing is currently not implemented for connected chip\n"); + break; + } + + if (ret) + ELOG("Flash option write failed!\n"); + else + ILOG("Wrote option control register %#010x!\n", option_control_register); + + /* Re-lock flash. */ + lock_flash_option(sl); + lock_flash(sl); + + return ret; +} + +/** + * Write option bytes + * @param sl + * @param option bytes boot address to write + * @return 0 on success, -ve on failure. + */ +int stlink_write_option_control_register1_32(stlink_t *sl, uint32_t option_control_register1) +{ + int ret = -1; + + wait_flash_busy(sl); + + if (unlock_flash_if(sl)) { + ELOG("Flash unlock failed! System reset required to be able to unlock it again!\n"); + return -1; + } + + if (unlock_flash_option_if(sl)) { + ELOG("Flash option unlock failed!\n"); + return -1; + } + + switch (sl->flash_type) { + case STLINK_FLASH_TYPE_F7: + ret = stlink_write_option_control_register1_f7(sl, option_control_register1); + break; + default: + ELOG("Option control register 1 writing is currently not implemented for connected chip\n"); + break; + } + + if (ret) + ELOG("Flash option write failed!\n"); + else + ILOG("Wrote option control register 1 %#010x!\n", option_control_register1); /* Re-lock flash. */ lock_flash_option(sl); diff --git a/src/flash_loader.c b/src/flash_loader.c index a2c5879ce..b6058cd0e 100644 --- a/src/flash_loader.c +++ b/src/flash_loader.c @@ -176,19 +176,19 @@ int stlink_flash_loader_init(stlink_t *sl, flash_loader_t *fl) { - size_t size = 0; + size_t size = 0; - /* allocate the loader in sram */ - if (stlink_flash_loader_write_to_sram(sl, &fl->loader_addr, &size) == -1) { - WLOG("Failed to write flash loader to sram!\n"); - return -1; - } + /* allocate the loader in sram */ + if (stlink_flash_loader_write_to_sram(sl, &fl->loader_addr, &size) == -1) { + WLOG("Failed to write flash loader to sram!\n"); + return -1; + } - /* allocate a one page buffer in sram right after loader */ - fl->buf_addr = fl->loader_addr + (uint32_t) size; - ILOG("Successfully loaded flash loader in sram\n"); + /* allocate a one page buffer in sram right after loader */ + fl->buf_addr = fl->loader_addr + (uint32_t) size; + ILOG("Successfully loaded flash loader in sram\n"); - return 0; + return 0; } static int loader_v_dependent_assignment(stlink_t *sl, diff --git a/src/tools/flash.c b/src/tools/flash.c index 3a83daf8a..9c4e20dff 100644 --- a/src/tools/flash.c +++ b/src/tools/flash.c @@ -28,15 +28,23 @@ static void cleanup(int signum) { static void usage(void) { - puts("command line: ./st-flash [--debug] [--reset] [--opt] [--serial ] [--format ] [--flash=] [--freq=] {read|write} [addr] [size]"); + puts("command line: ./st-flash [--debug] [--reset] [--opt] [--serial ] [--format ] [--flash=] [--freq=] [--area=] {read|write} [path] [addr] [size]"); puts("command line: ./st-flash [--debug] [--freq=] [--serial ] erase"); puts("command line: ./st-flash [--debug] [--freq=] [--serial ] reset"); puts(" , and : Use hex format."); puts(" : Use decimal, octal or hex (prefix 0xXXX) format, optionally followed by k=KB, or m=MB (eg. --flash=128k)"); puts(" : Can be 'binary' (default) or 'ihex', although must be specified for binary format only."); + puts(" : Can be 'main' (default), 'system', 'otp', 'optcr', 'optcr1', 'option' or 'option_boot_add'"); puts("print tool version info: ./st-flash [--version]"); - puts("example write option byte: ./st-flash --debug --reset --area=option write 0xXXXXXXXX"); - puts("example read option byte: ./st-flash --debug --reset --area=option read > option_byte"); + puts("example read option byte: ./st-flash --area=option read [path] [size]"); + puts("example write option byte: ./st-flash --area=option write 0xXXXXXXXX"); + puts("On selected targets:"); + puts("example read boot_add option byte: ./st-flash --area=option_boot_add read"); + puts("example write boot_add option byte: ./st-flash --area=option_boot_add write 0xXXXXXXXX"); + puts("example read option control register byte: ./st-flash --area=optcr read"); + puts("example write option control register1 byte: ./st-flash --area=optcr write 0xXXXXXXXX"); + puts("example read option control register1 byte: ./st-flash --area=optcr1 read"); + puts("example write option control register1 byte: ./st-flash --area=optcr1 write 0xXXXXXXXX"); } int main(int ac, char** av) @@ -54,7 +62,7 @@ int main(int ac, char** av) return -1; } - printf("st-flash %s\n", STLINK_VERSION); + ILOG("st-flash %s\n", STLINK_VERSION); sl = stlink_open_usb(o.log_level, 1, (char *)o.serial, o.freq); @@ -62,7 +70,7 @@ int main(int ac, char** av) return -1; } - if (sl->flash_type == STLINK_FLASH_TYPE_UNKNOWN) { + if (STLINK_FLASH_TYPE_UNKNOWN == sl->flash_type) { printf("Failed to connect to target\n"); return -1; } @@ -80,14 +88,14 @@ int main(int ac, char** av) signal(SIGTERM, &cleanup); signal(SIGSEGV, &cleanup); - if (stlink_current_mode(sl) == STLINK_DEV_DFU_MODE) { + if (STLINK_DEV_DFU_MODE == stlink_current_mode(sl)) { if (stlink_exit_dfu_mode(sl)) { printf("Failed to exit DFU mode\n"); goto on_error; } } - if (stlink_current_mode(sl) != STLINK_DEV_DEBUG_MODE) { + if (STLINK_DEV_DEBUG_MODE != stlink_current_mode(sl)) { if (stlink_enter_swd_mode(sl)) { printf("Failed to enter SWD mode\n"); goto on_error; @@ -109,7 +117,7 @@ int main(int ac, char** av) } // Disable DMA - Set All DMA CCR Registers to zero. - AKS 1/7/2013 - if (sl->chip_id == STLINK_CHIPID_STM32_F4) + if (STLINK_CHIPID_STM32_F4 == sl->chip_id) { memset(sl->q_buf,0,4); for (int i=0;i<8;i++) { @@ -131,19 +139,20 @@ int main(int ac, char** av) goto on_error; } - if (o.cmd == FLASH_CMD_WRITE) /* write */ + if (FLASH_CMD_WRITE == o.cmd) // write { size_t size = 0; - if (o.format == FLASH_FORMAT_IHEX) { + if (FLASH_FORMAT_IHEX == o.format) { err = stlink_parse_ihex(o.filename, stlink_get_erased_pattern(sl), &mem, &size, &o.addr); if (err == -1) { printf("Cannot parse %s as Intel-HEX file\n", o.filename); goto on_error; } } + if ((o.addr >= sl->flash_base) && (o.addr < sl->flash_base + sl->flash_size)) { - if (o.format == FLASH_FORMAT_IHEX) + if (FLASH_FORMAT_IHEX == o.format) err = stlink_mwrite_flash(sl, mem, (uint32_t)size, o.addr); else err = stlink_fwrite_flash(sl, o.filename, o.addr); @@ -155,7 +164,7 @@ int main(int ac, char** av) } else if ((o.addr >= sl->sram_base) && (o.addr < sl->sram_base + sl->sram_size)) { - if (o.format == FLASH_FORMAT_IHEX) + if (FLASH_FORMAT_IHEX == o.format) err = stlink_mwrite_sram(sl, mem, (uint32_t)size, o.addr); else err = stlink_fwrite_sram(sl, o.filename, o.addr); @@ -174,25 +183,39 @@ int main(int ac, char** av) goto on_error; } } - else if (o.area == FLASH_OPTION_BYTES){ + else if (FLASH_OPTION_BYTES == o.area) { if (o.val == 0) { printf("attempting to set option byte to 0, abort.\n"); goto on_error; - } + } err = stlink_write_option_bytes32(sl, o.val); - if (err == -1) - { + if (err == -1) { printf("stlink_write_option_bytes32() == -1\n"); goto on_error; } } - else { + else if (FLASH_OPTCR == o.area) { + DLOG("@@@@ Write %d (%0#10x) to option control register\n", o.val, o.val); + + err = stlink_write_option_control_register32(sl, o.val); + } + else if (FLASH_OPTCR1 == o.area) { + DLOG("@@@@ Write %d (%0#10x) to option control register 1\n", o.val, o.val); + + err = stlink_write_option_control_register1_32(sl, o.val); + } + else if (FLASH_OPTION_BYTES_BOOT_ADD == o.area) { + DLOG("@@@@ Write %d (%0#10x) to option bytes boot address\n", o.val, o.val); + + err = stlink_write_option_bytes_boot_add32(sl, o.val); + } + else { err = -1; printf("Unknown memory region\n"); goto on_error; } - } else if (o.cmd == FLASH_CMD_ERASE) + } else if (FLASH_CMD_ERASE == o.cmd) { err = stlink_erase_flash_mass(sl); if (err == -1) @@ -200,7 +223,7 @@ int main(int ac, char** av) printf("stlink_erase_flash_mass() == -1\n"); goto on_error; } - } else if (o.cmd == CMD_RESET) + } else if (CMD_RESET == o.cmd) { if (sl->version.stlink_v > 1) { if (stlink_jtag_reset(sl, 2)) { @@ -216,35 +239,69 @@ int main(int ac, char** av) } else /* read */ { - if(o.area == FLASH_OPTION_BYTES){ - uint32_t option_byte; - err = stlink_read_option_bytes32(sl, &option_byte); - if (err == -1) { - printf("could not read option bytes (%d)\n", err); - goto on_error; - } else { - printf("%x\n",option_byte); - } - }else{ - if ((o.addr >= sl->flash_base) && (o.size == 0) && - (o.addr < sl->flash_base + sl->flash_size)){ + if ((FLASH_MAIN_MEMORY == o.area) || (FLASH_SYSTEM_MEMORY == o.area)) { + if ((o.size == 0) && (o.addr >= sl->flash_base) && (o.addr < sl->flash_base + sl->flash_size)) { o.size = sl->flash_size; } - else if ((o.addr >= sl->sram_base) && (o.size == 0) && - (o.addr < sl->sram_base + sl->sram_size)){ + else if ((o.size == 0) && (o.addr >= sl->sram_base) && (o.addr < sl->sram_base + sl->sram_size)) { o.size = sl->sram_size; } - err = stlink_fread(sl, o.filename, o.format == FLASH_FORMAT_IHEX, o.addr, o.size); + err = stlink_fread(sl, o.filename, FLASH_FORMAT_IHEX == o.format, o.addr, o.size); - if (err == -1) - { + if (err == -1) { printf("stlink_fread() == -1\n"); goto on_error; } + } else if (FLASH_OPTION_BYTES == o.area) { + uint8_t remaining_option_length = sl->option_size / 4; + DLOG("@@@@ Read %d (%#x) option bytes from %#10x\n", remaining_option_length, remaining_option_length, sl->option_base); + + if (NULL != o.filename) { + if (0 == o.size) { + o.size = sl->option_size; + } + err = stlink_fread(sl, o.filename, FLASH_FORMAT_IHEX == o.format, sl->option_base, o.size); + } else { + uint32_t option_byte = 0; + err = stlink_read_option_bytes32(sl, &option_byte); + if (err == -1) { + printf("could not read option bytes (%d)\n", err); + goto on_error; + } else { + printf("%08x\n", option_byte); + } + } + } else if (FLASH_OPTION_BYTES_BOOT_ADD == o.area) { + uint32_t option_byte = 0; + err = stlink_read_option_bytes_boot_add32(sl, &option_byte); + if (err == -1) { + printf("could not read option bytes boot address (%d)\n", err); + goto on_error; + } else { + printf("%08x\n",option_byte); + } + } else if (FLASH_OPTCR == o.area) { + uint32_t option_byte = 0; + err = stlink_read_option_control_register32(sl, &option_byte); + if (err == -1) { + printf("could not read option control register (%d)\n", err); + goto on_error; + } else { + printf("%08x\n",option_byte); + } + } else if (FLASH_OPTCR1 == o.area) { + uint32_t option_byte = 0; + err = stlink_read_option_control_register1_32(sl, &option_byte); + if (err == -1) { + printf("could not read option control register (%d)\n", err); + goto on_error; + } else { + printf("%08x\n",option_byte); + } } } - if (o.reset){ + if (o.reset) { if (sl->version.stlink_v > 1) stlink_jtag_reset(sl, 2); stlink_reset(sl); } diff --git a/src/tools/flash_opts.c b/src/tools/flash_opts.c index a5c9d287f..8557445e0 100644 --- a/src/tools/flash_opts.c +++ b/src/tools/flash_opts.c @@ -145,6 +145,12 @@ int flash_get_opts(struct flash_opts* o, int ac, char** av) { o->area = FLASH_OTP; else if (strcmp(area, "option") == 0) o->area = FLASH_OPTION_BYTES; + else if (strcmp(area, "option_boot_add") == 0) + o->area = FLASH_OPTION_BYTES_BOOT_ADD; + else if (strcmp(area, "optcr") == 0) + o->area = FLASH_OPTCR; + else if (strcmp(area, "optcr1") == 0) + o->area = FLASH_OPTCR1; else return -1; @@ -236,19 +242,19 @@ int flash_get_opts(struct flash_opts* o, int ac, char** av) { // command and (optional) device name while (ac >= 1) { if (strcmp(av[0], "erase") == 0) { - if (o->cmd != FLASH_CMD_NONE) return -1; + if (FLASH_CMD_NONE != o->cmd) return -1; o->cmd = FLASH_CMD_ERASE; } else if (strcmp(av[0], "read") == 0) { - if (o->cmd != FLASH_CMD_NONE) return -1; + if (FLASH_CMD_NONE != o->cmd) return -1; o->cmd = FLASH_CMD_READ; } else if (strcmp(av[0], "write") == 0) { - if (o->cmd != FLASH_CMD_NONE) return -1; + if (FLASH_CMD_NONE != o->cmd) return -1; o->cmd = FLASH_CMD_WRITE; } else if (strcmp(av[0], "reset") == 0) { - if (o->cmd != FLASH_CMD_NONE) return -1; + if (FLASH_CMD_NONE != o->cmd) return -1; o->cmd = CMD_RESET; } else { @@ -268,33 +274,93 @@ int flash_get_opts(struct flash_opts* o, int ac, char** av) { break; case FLASH_CMD_READ: // expect filename, addr and size - if ((o->area == FLASH_OPTION_BYTES) &&(ac == 0)) break; - if (ac != 3) return invalid_args("read "); - if (ac != 3) return -1; - o->filename = av[0]; - uint32_t address; - result = get_integer_from_char_array(av[1], &address); - if (result != 0) return bad_arg ("addr"); - else o->addr = (stm32_addr_t) address; + if ((FLASH_MAIN_MEMORY == o->area) || (FLASH_SYSTEM_MEMORY == o->area)) { + if (ac != 3) return invalid_args("read "); + o->filename = av[0]; + uint32_t address; + result = get_integer_from_char_array(av[1], &address); + if (result != 0) return bad_arg ("addr"); + else o->addr = (stm32_addr_t) address; - uint32_t size; - result = get_integer_from_char_array(av[2], &size); - if (result != 0) return bad_arg ("size"); - else o->size = (size_t) size; + uint32_t size; + result = get_integer_from_char_array(av[2], &size); + if (result != 0) return bad_arg ("size"); + else o->size = (size_t) size; + break; + } + else if ((FLASH_OTP == o->area)) { + return bad_arg("TODO: otp not implemented yet"); + if (ac > 1) return invalid_args("otp read: [path]"); + if (ac > 0) o->filename = av[0]; + break; + } + else if ((FLASH_OPTION_BYTES == o->area)) { + if (ac > 2) return invalid_args("option bytes read: [path] [size]"); + if (ac > 0) o->filename = av[0]; + if (ac > 1) { + uint32_t size; + result = get_integer_from_char_array(av[1], &size); + if (result != 0) return bad_arg("option bytes read: invalid size"); + else o->size = (size_t) size; + } + break; + } + else if ((FLASH_OPTION_BYTES_BOOT_ADD == o->area)) { + if (ac > 0) return invalid_args("option bytes boot_add read"); + break; + } + else if ((FLASH_OPTCR == o->area)) { + if (ac > 0) return invalid_args("option control register read"); + break; + } + else if ((FLASH_OPTCR1 == o->area)) { + if (ac > 0) return invalid_args("option control register 1 read"); + break; + } break; case FLASH_CMD_WRITE: - if (o->area == FLASH_OPTION_BYTES){ - if (ac != 1) return -1; - + // TODO: should be boot add 0 and boot add 1 uint32 + if (FLASH_OPTION_BYTES == o->area) { // expect filename and optional address + if (ac >=1 && ac <= 2) { + o->filename = av[0]; + } + else + return invalid_args("write [addr]"); + + if (ac == 2) { + uint32_t addr; + result = get_integer_from_char_array(av[1], &addr); + if (result != 0) return bad_arg ("addr"); + else o->addr = (stm32_addr_t) addr; + } + } + else if (FLASH_OPTION_BYTES_BOOT_ADD == o->area) { // expect option bytes boot address + if (ac != 1) return invalid_args("option bytes boot_add write "); + + uint32_t val; + result = get_integer_from_char_array(av[0], &val); + if (result != 0) return bad_arg ("val"); + else o->val = (uint32_t) val; + } + else if (FLASH_OPTCR == o->area) { // expect option control register value + if (ac != 1) return invalid_args("option control register write "); + + uint32_t val; + result = get_integer_from_char_array(av[0], &val); + if (result != 0) return bad_arg ("val"); + else o->val = (uint32_t) val; + } + else if (FLASH_OPTCR1 == o->area) { // expect option control register 1 value + if (ac != 1) return invalid_args("option control register 1 write "); + uint32_t val; result = get_integer_from_char_array(av[0], &val); if (result != 0) return bad_arg ("val"); else o->val = (uint32_t) val; - } - else if (o->format == FLASH_FORMAT_BINARY) { // expect filename and addr + else if (FLASH_FORMAT_BINARY == o->format) { // expect filename and addr if (ac != 2) return invalid_args("write "); o->filename = av[0]; uint32_t addr; @@ -302,7 +368,7 @@ int flash_get_opts(struct flash_opts* o, int ac, char** av) { if (result != 0) return bad_arg ("addr"); else o->addr = (stm32_addr_t) addr; } - else if (o->format == FLASH_FORMAT_IHEX) { // expect filename + else if (FLASH_FORMAT_IHEX == o->format) { // expect filename if (ac != 1) return invalid_args("write "); o->filename = av[0]; } diff --git a/src/usb.c b/src/usb.c index b986aed57..b492afed7 100644 --- a/src/usb.c +++ b/src/usb.c @@ -655,6 +655,7 @@ int _stlink_usb_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { cmd[i++] = STLINK_DEBUG_COMMAND; cmd[i++] = STLINK_DEBUG_READMEM_32BIT; + DLOG("using address %#010x\n", addr); write_uint32(&cmd[i], addr); write_uint16(&cmd[i + 4], len); size = send_recv(slu, 1, cmd, slu->cmd_len, data, len); From 972ecf8d960919d0c9433c73b809ddcc701f847b Mon Sep 17 00:00:00 2001 From: Rutger Hendriks Date: Thu, 25 Jun 2020 12:40:15 +0200 Subject: [PATCH 056/503] Continue merging upstream --- src/common.c | 3 +- src/st-flash/flash.c | 5 +- src/st-flash/flash_opts.c | 417 ++++++++++++++++------------- src/stlink-lib/chipid.c | 2 +- src/stlink-lib/flash_loader.c | 486 +++++++++++++++++----------------- 5 files changed, 481 insertions(+), 432 deletions(-) diff --git a/src/common.c b/src/common.c index 1703dee76..58e67d447 100644 --- a/src/common.c +++ b/src/common.c @@ -3637,8 +3637,9 @@ int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t* base, ui if (ret) { ELOG("Flash option write failed!\n"); - else + } else { ILOG("Wrote %d option bytes to %#010x!\n", len, addr); + } /* Re-lock flash. */ lock_flash_option(sl); diff --git a/src/st-flash/flash.c b/src/st-flash/flash.c index 6d70fc5e6..128b8acc0 100644 --- a/src/st-flash/flash.c +++ b/src/st-flash/flash.c @@ -140,7 +140,6 @@ int main(int ac, char** av) { { size_t size = 0; if (FLASH_FORMAT_IHEX == o.format) { - if (o.format == FLASH_FORMAT_IHEX) { err = stlink_parse_ihex(o.filename, stlink_get_erased_pattern(sl), &mem, &size, &o.addr); if (err == -1) { @@ -150,7 +149,7 @@ int main(int ac, char** av) { } if ((o.addr >= sl->flash_base) && (o.addr < sl->flash_base + sl->flash_size)) { - if (FLASH_FORMAT_IHEX == o.format) + if (FLASH_FORMAT_IHEX == o.format) { err = stlink_mwrite_flash(sl, mem, (uint32_t)size, o.addr); } else { err = stlink_fwrite_flash(sl, o.filename, o.addr); @@ -162,7 +161,7 @@ int main(int ac, char** av) { } } else if ((o.addr >= sl->sram_base) && (o.addr < sl->sram_base + sl->sram_size)) { - if (FLASH_FORMAT_IHEX == o.format) + if (FLASH_FORMAT_IHEX == o.format) { err = stlink_mwrite_sram(sl, mem, (uint32_t)size, o.addr); } else { err = stlink_fwrite_sram(sl, o.filename, o.addr); diff --git a/src/st-flash/flash_opts.c b/src/st-flash/flash_opts.c index 6d1940675..8557445e0 100644 --- a/src/st-flash/flash_opts.c +++ b/src/st-flash/flash_opts.c @@ -2,12 +2,11 @@ #include #include -#include "flash.h" +#include static bool starts_with(const char * str, const char * prefix) { size_t n = strlen(prefix); - - if (strlen(str) < n) { return(false); } + if (strlen(str) < n) return false; return (0 == strncmp(str, prefix, n)); } @@ -20,28 +19,37 @@ static int get_long_integer_from_char_array (const char *const str, uint64_t *re uint64_t value; char *tail; - if (starts_with (str, "0x") || starts_with (str, "0X")) { // hexadecimal + // hexadecimal + if (starts_with (str, "0x") || starts_with (str, "0X")) { value = strtoul (str + 2, &tail, 16); - } else if (starts_with (str, "0b") || starts_with (str, "0B")) { // binary + } + // binary + else if (starts_with (str, "0b") || starts_with (str, "0B")) { value = strtoul (str + 2, &tail, 2); - } else if (starts_with (str, "0")) { // octal + } + // octal + else if (starts_with (str, "0")) { value = strtoul (str + 1, &tail, 8); - } else { // decimal + } + // decimal + else { value = strtoul (str, &tail, 10); } if (((tail[0] == 'k') || (tail[0] == 'K')) && (tail[1] == '\0')) { value = value * 1024; - } else if (((tail[0] == 'm') || (tail[0] == 'M')) && (tail[1] == '\0')) { + } + else if (((tail[0] == 'm') || (tail[0] == 'M')) && (tail[1] == '\0')) { value = value * 1024 * 1024; - } else if (tail[0] == '\0') { - /* value not changed */ - } else { - return(-1); } - + else if (tail[0] == '\0') { + // value not change + } + else { + return -1; + } *read_value = value; - return(0); + return 0; } // support positive integer from 0 to UINT32_MAX @@ -51,26 +59,28 @@ static int get_long_integer_from_char_array (const char *const str, uint64_t *re static int get_integer_from_char_array (const char *const str, uint32_t *read_value) { uint64_t value; int result = get_long_integer_from_char_array (str, &value); - if (result != 0) { - return(result); - } else if (value > UINT32_MAX) { - fprintf (stderr, "*** Error: Integer greater than UINT32_MAX, cannot convert to int32_t\n"); - return(-1); - } else { + return result; + } + else if (value > UINT32_MAX) { + fprintf (stderr, "*** Error: Integer greater than UINT32_MAX, \ +cannot convert to int32_t\n"); + return -1; + } + else { *read_value = (uint32_t)value; - return(0); + return 0; } } static int invalid_args(const char *expected) { fprintf(stderr, "*** Error: Expected args for this command: %s\n", expected); - return(-1); + return -1; } static int bad_arg(const char *arg) { fprintf(stderr, "*** Error: Invalid value for %s\n", arg); - return(-1); + return -1; } int flash_get_opts(struct flash_opts* o, int ac, char** av) { @@ -81,177 +91,173 @@ int flash_get_opts(struct flash_opts* o, int ac, char** av) { // options int result; - while (ac >= 1) { if (strcmp(av[0], "--version") == 0) { printf("v%s\n", STLINK_VERSION); exit(EXIT_SUCCESS); - } else if (strcmp(av[0], "--debug") == 0) { + } + else if (strcmp(av[0], "--debug") == 0) { o->log_level = DEBUG_LOG_LEVEL; - } else if (strcmp(av[0], "--opt") == 0) { + } + else if (strcmp(av[0], "--opt") == 0) { o->opt = ENABLE_OPT; - } else if (strcmp(av[0], "--reset") == 0) { + } + else if (strcmp(av[0], "--reset") == 0) { o->reset = 1; - } else if (strcmp(av[0], "--serial") == 0 || starts_with(av[0], "--serial=")) { + } + else if (strcmp(av[0], "--serial") == 0 || starts_with(av[0], "--serial=")) { const char * serial; - if (strcmp(av[0], "--serial") == 0) { ac--; av++; - - if (ac < 1) { return(-1); } - + if (ac < 1) return -1; serial = av[0]; - } else { + } + else { serial = av[0] + strlen("--serial="); } - - /** @todo This is not really portable, as strlen really returns size_t we need to obey - and not cast it to a signed type. */ + /** @todo This is not really portable, as strlen really returns size_t we need to obey and not cast it to a signed type. */ int j = (int)strlen(serial); - int length = j / 2; // the length of the destination-array - - if (j % 2 != 0) { return(-1); } - + int length = j / 2; // the length of the destination-array + if (j % 2 != 0) return -1; for (size_t k = 0; j >= 0 && k < sizeof(o->serial); ++k, j -= 2) { char buffer[3] = {0}; memcpy(buffer, serial + j, 2); o->serial[length - k] = (uint8_t)strtol(buffer, NULL, 16); } - } else if (strcmp(av[0], "--area") == 0 || starts_with(av[0], "--area=")) { + } + else if (strcmp(av[0], "--area") == 0 || starts_with(av[0], "--area=")) { const char * area; - if (strcmp(av[0], "--area") == 0) { ac--; av++; - - if (ac < 1) { return(-1); } - + if (ac < 1) return -1; area = av[0]; - } else { + } + else { area = av[0] + strlen("--area="); } - - if (strcmp(area, "main") == 0) { + if (strcmp(area, "main") == 0) o->area = FLASH_MAIN_MEMORY; - } else if (strcmp(area, "system") == 0) { + else if (strcmp(area, "system") == 0) o->area = FLASH_SYSTEM_MEMORY; - } else if (strcmp(area, "otp") == 0) { + else if (strcmp(area, "otp") == 0) o->area = FLASH_OTP; - } else if (strcmp(area, "option") == 0) { + else if (strcmp(area, "option") == 0) o->area = FLASH_OPTION_BYTES; - } else { - return(-1); - } + else if (strcmp(area, "option_boot_add") == 0) + o->area = FLASH_OPTION_BYTES_BOOT_ADD; + else if (strcmp(area, "optcr") == 0) + o->area = FLASH_OPTCR; + else if (strcmp(area, "optcr1") == 0) + o->area = FLASH_OPTCR1; + else + return -1; - } else if (strcmp(av[0], "--freq") == 0 || starts_with(av[0], "--freq=")) { + } + else if (strcmp(av[0], "--freq") == 0 || starts_with(av[0], "--freq=")) { const char* freq; - if (strcmp(av[0], "--freq") == 0) { ac--; av++; - - if (ac < 1) { - return(-1); - } - + if (ac < 1) return -1; freq = av[0]; - } else { + } + else { freq = av[0] + strlen("--freq="); } - if (strcmp(freq, "5K") == 0 || strcmp(freq, "5k") == 0) { o->freq = 5; - } else if (strcmp(freq, "15K") == 0 || strcmp(freq, "15k") == 0) { + } + else if (strcmp(freq, "15K") == 0 || strcmp(freq, "15k") == 0) { o->freq = 15; - } else if (strcmp(freq, "25K") == 0 || strcmp(freq, "25k") == 0) { + } + else if (strcmp(freq, "25K") == 0 || strcmp(freq, "25k") == 0) { o->freq = 25; - } else if (strcmp(freq, "50K") == 0 || strcmp(freq, "50k") == 0) { + } + else if (strcmp(freq, "50K") == 0 || strcmp(freq, "50k") == 0) { o->freq = 50; - } else if (strcmp(freq, "100K") == 0 || strcmp(freq, "100k") == 0) { + } + else if (strcmp(freq, "100K") == 0 || strcmp(freq, "100k") == 0) { o->freq = 100; - } else if (strcmp(freq, "125K") == 0 || strcmp(freq, "125k") == 0) { + } + else if (strcmp(freq, "125K") == 0 || strcmp(freq, "125k") == 0) { o->freq = 125; - } else if (strcmp(freq, "240K") == 0 || strcmp(freq, "240k") == 0) { + } + else if (strcmp(freq, "240K") == 0 || strcmp(freq, "240k") == 0) { o->freq = 240; - } else if (strcmp(freq, "480K") == 0 || strcmp(freq, "480k") == 0) { + } + else if (strcmp(freq, "480K") == 0 || strcmp(freq, "480k") == 0) { o->freq = 480; - } else if (strcmp(freq, "950K") == 0 || strcmp(freq, "950k") == 0) { + } + else if (strcmp(freq, "950K") == 0 || strcmp(freq, "950k") == 0) { o->freq = 950; - } else if (strcmp(freq, "1200K") == 0 || strcmp(freq, "1200k") == 0 || - strcmp(freq, "1.2M") == 0 || strcmp(freq, "1.2m") == 0) { + } + else if (strcmp(freq, "1200K") == 0 || strcmp(freq, "1200k") == 0 || strcmp(freq, "1.2M") == 0 || strcmp(freq, "1.2m") == 0) { o->freq = 1200; - } else if (strcmp(freq, "1800K") == 0 || strcmp(freq, "1800k") == 0 || - strcmp(freq, "1.8M") == 0 || strcmp(freq, "1.8m") == 0) { + } + else if (strcmp(freq, "1800K") == 0 || strcmp(freq, "1800k") == 0 || strcmp(freq, "1.8M") == 0 || strcmp(freq, "1.8m") == 0) { o->freq = 1800; - } else if (strcmp(freq, "4000K") == 0 || strcmp(freq, "4000k") == 0 || - strcmp(freq, "4M") == 0 || strcmp(freq, "4m") == 0) { + } + else if (strcmp(freq, "4000K") == 0 || strcmp(freq, "4000k") == 0 || strcmp(freq, "4M") == 0 || strcmp(freq, "4m") == 0) { o->freq = 4000; - } else { - return(-1); } - } else if (strcmp(av[0], "--format") == 0 || starts_with(av[0], "--format=")) { + else + return -1; + } + else if (strcmp(av[0], "--format") == 0 || starts_with(av[0], "--format=")) { const char * format; - if (strcmp(av[0], "--format") == 0) { ac--; av++; - - if (ac < 1) { return(-1); } - + if (ac < 1) return -1; format = av[0]; - } else { + } + else { format = av[0] + strlen("--format="); } - - if (strcmp(format, "binary") == 0) { + if (strcmp(format, "binary") == 0) o->format = FLASH_FORMAT_BINARY; - } else if (strcmp(format, "ihex") == 0) { + else if (strcmp(format, "ihex") == 0) o->format = FLASH_FORMAT_IHEX; - } else { - return(bad_arg("format")); - } - } else if ( starts_with(av[0], "--flash=")) { + else + return bad_arg("format"); + } + else if ( starts_with(av[0], "--flash=") ) { const char *arg = av[0] + strlen("--flash="); uint32_t flash_size; result = get_integer_from_char_array(arg, &flash_size); - - if (result != 0) { - return(bad_arg ("--flash")); - } else { - o->flash_size = (size_t)flash_size; - } - } else if (strcmp(av[0], "--connect-under-reset") == 0) { - o->connect_under_reset = true; - } else { - break; // non-option found - + if (result != 0) return bad_arg ("--flash"); + else o->flash_size = (size_t) flash_size; + } + else { + break; // non-option found } ac--; av++; } - /* command and (optional) device name */ + // command and (optional) device name while (ac >= 1) { if (strcmp(av[0], "erase") == 0) { - if (o->cmd != FLASH_CMD_NONE) { return(-1); } - + if (FLASH_CMD_NONE != o->cmd) return -1; o->cmd = FLASH_CMD_ERASE; - } else if (strcmp(av[0], "read") == 0) { - if (o->cmd != FLASH_CMD_NONE) { return(-1); } - + } + else if (strcmp(av[0], "read") == 0) { + if (FLASH_CMD_NONE != o->cmd) return -1; o->cmd = FLASH_CMD_READ; - } else if (strcmp(av[0], "write") == 0) { - if (o->cmd != FLASH_CMD_NONE) { return(-1); } - + } + else if (strcmp(av[0], "write") == 0) { + if (FLASH_CMD_NONE != o->cmd) return -1; o->cmd = FLASH_CMD_WRITE; - } else if (strcmp(av[0], "reset") == 0) { - if (o->cmd != FLASH_CMD_NONE) { return(-1); } - + } + else if (strcmp(av[0], "reset") == 0) { + if (FLASH_CMD_NONE != o->cmd) return -1; o->cmd = CMD_RESET; - } else { + } + else { break; } @@ -259,83 +265,120 @@ int flash_get_opts(struct flash_opts* o, int ac, char** av) { av++; } - switch (o->cmd) { - case FLASH_CMD_NONE: // no command found - return(-1); - - case FLASH_CMD_ERASE: // no more arguments expected - - if (ac != 0) { return(-1); } - - break; - - case FLASH_CMD_READ: // expect filename, addr and size - - if ((o->area == FLASH_OPTION_BYTES) && (ac == 0)) { break; } - - if (ac != 3) { return(invalid_args("read ")); } - - if (ac != 3) { return(-1); } - - o->filename = av[0]; - uint32_t address; - result = get_integer_from_char_array(av[1], &address); - - if (result != 0) { - return(bad_arg ("addr")); - } else { - o->addr = (stm32_addr_t)address; - } - - uint32_t size; - result = get_integer_from_char_array(av[2], &size); - - if (result != 0) { - return(bad_arg ("size")); - } else { - o->size = (size_t)size; - } - - break; - - case FLASH_CMD_WRITE: - - if (o->area == FLASH_OPTION_BYTES) { - if (ac != 1) { return(-1); } + switch(o->cmd) { + case FLASH_CMD_NONE: // no command found + return -1; - uint32_t val; - result = get_integer_from_char_array(av[0], &val); + case FLASH_CMD_ERASE: // no more arguments expected + if (ac != 0) return -1; + break; - if (result != 0) { - return(bad_arg ("val")); - } else { - o->val = (uint32_t)val; + case FLASH_CMD_READ: // expect filename, addr and size + if ((FLASH_MAIN_MEMORY == o->area) || (FLASH_SYSTEM_MEMORY == o->area)) { + if (ac != 3) return invalid_args("read "); + o->filename = av[0]; + uint32_t address; + result = get_integer_from_char_array(av[1], &address); + if (result != 0) return bad_arg ("addr"); + else o->addr = (stm32_addr_t) address; + + uint32_t size; + result = get_integer_from_char_array(av[2], &size); + if (result != 0) return bad_arg ("size"); + else o->size = (size_t) size; + + break; } - - } else if (o->format == FLASH_FORMAT_BINARY) { // expect filename and addr - if (ac != 2) { return(invalid_args("write ")); } - - o->filename = av[0]; - uint32_t addr; - result = get_integer_from_char_array(av[1], &addr); - - if (result != 0) { - return(bad_arg ("addr")); - } else { - o->addr = (stm32_addr_t)addr; + else if ((FLASH_OTP == o->area)) { + return bad_arg("TODO: otp not implemented yet"); + if (ac > 1) return invalid_args("otp read: [path]"); + if (ac > 0) o->filename = av[0]; + break; } - } else if (o->format == FLASH_FORMAT_IHEX) { // expect filename - if (ac != 1) { return(invalid_args("write ")); } - - o->filename = av[0]; - } else { - return(-1); // should have been caught during format parsing - } + else if ((FLASH_OPTION_BYTES == o->area)) { + if (ac > 2) return invalid_args("option bytes read: [path] [size]"); + if (ac > 0) o->filename = av[0]; + if (ac > 1) { + uint32_t size; + result = get_integer_from_char_array(av[1], &size); + if (result != 0) return bad_arg("option bytes read: invalid size"); + else o->size = (size_t) size; + } + break; + } + else if ((FLASH_OPTION_BYTES_BOOT_ADD == o->area)) { + if (ac > 0) return invalid_args("option bytes boot_add read"); + break; + } + else if ((FLASH_OPTCR == o->area)) { + if (ac > 0) return invalid_args("option control register read"); + break; + } + else if ((FLASH_OPTCR1 == o->area)) { + if (ac > 0) return invalid_args("option control register 1 read"); + break; + } + break; - break; + case FLASH_CMD_WRITE: + // TODO: should be boot add 0 and boot add 1 uint32 + if (FLASH_OPTION_BYTES == o->area) { // expect filename and optional address + if (ac >=1 && ac <= 2) { + o->filename = av[0]; + } + else + return invalid_args("write [addr]"); + + if (ac == 2) { + uint32_t addr; + result = get_integer_from_char_array(av[1], &addr); + if (result != 0) return bad_arg ("addr"); + else o->addr = (stm32_addr_t) addr; + } + } + else if (FLASH_OPTION_BYTES_BOOT_ADD == o->area) { // expect option bytes boot address + if (ac != 1) return invalid_args("option bytes boot_add write "); + + uint32_t val; + result = get_integer_from_char_array(av[0], &val); + if (result != 0) return bad_arg ("val"); + else o->val = (uint32_t) val; + } + else if (FLASH_OPTCR == o->area) { // expect option control register value + if (ac != 1) return invalid_args("option control register write "); + + uint32_t val; + result = get_integer_from_char_array(av[0], &val); + if (result != 0) return bad_arg ("val"); + else o->val = (uint32_t) val; + } + else if (FLASH_OPTCR1 == o->area) { // expect option control register 1 value + if (ac != 1) return invalid_args("option control register 1 write "); + + uint32_t val; + result = get_integer_from_char_array(av[0], &val); + if (result != 0) return bad_arg ("val"); + else o->val = (uint32_t) val; + } + else if (FLASH_FORMAT_BINARY == o->format) { // expect filename and addr + if (ac != 2) return invalid_args("write "); + o->filename = av[0]; + uint32_t addr; + result = get_integer_from_char_array(av[1], &addr); + if (result != 0) return bad_arg ("addr"); + else o->addr = (stm32_addr_t) addr; + } + else if (FLASH_FORMAT_IHEX == o->format) { // expect filename + if (ac != 1) return invalid_args("write "); + o->filename = av[0]; + } + else { + return -1; // should have been caught during format parsing + } + break; - default: break; + default: break ; } - return(0); + return 0; } diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index 147b0e74e..3763587e1 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -11,7 +11,7 @@ static const struct stlink_chipid_params devices[] = { .flash_pagesize = 0x800, // No flash pages .sram_size = 0x80000, // "SRAM" byte size in hex from .bootrom_base = 0x00200000, // ! "System memory" starting address from - .bootrom_size = 0xEDC0 // ! @todo "System memory" byte size in hex from + .bootrom_size = 0xEDC0, // ! @todo "System memory" byte size in hex from .option_base = STM32_F7_OPTION_BYTES_BASE, // Used for reading back the option bytes, writing uses FLASH_F7_OPTCR and FLASH_F7_OPTCR1 .option_size = 0x20 }, diff --git a/src/stlink-lib/flash_loader.c b/src/stlink-lib/flash_loader.c index 0e79c3c0a..b6058cd0e 100644 --- a/src/stlink-lib/flash_loader.c +++ b/src/stlink-lib/flash_loader.c @@ -3,210 +3,213 @@ #include #include -#include "flash_loader.h" #define FLASH_REGS_BANK2_OFS 0x40 #define FLASH_BANK2_START_ADDR 0x08080000 /* DO NOT MODIFY SOURCECODE DIRECTLY, EDIT ASSEMBLY FILES INSTEAD */ -/* flashloaders/stm32f0.s -- compiled with thumb2 */ -static const uint8_t loader_code_stm32vl[] = { - 0x16, 0x4f, 0x3c, 0x68, - 0x16, 0x4f, 0x3e, 0x68, - 0x36, 0x19, 0x16, 0x4f, - 0x3d, 0x68, 0x2d, 0x19, - 0x4f, 0xf0, 0x01, 0x07, - 0x33, 0x68, 0x3b, 0x43, - 0x33, 0x60, 0x03, 0x88, - 0x0b, 0x80, 0x4f, 0xf0, - 0x02, 0x07, 0xc0, 0x19, - 0xc9, 0x19, 0x4f, 0xf0, - 0x01, 0x07, 0x2b, 0x68, - 0x3b, 0x42, 0xfa, 0xd0, - 0x4f, 0xf0, 0x04, 0x07, - 0x3b, 0x42, 0x04, 0xd1, - 0x4f, 0xf0, 0x01, 0x07, - 0xd2, 0x1b, 0x00, 0x2a, - 0xe6, 0xd1, 0x4f, 0xf0, - 0x01, 0x07, 0x33, 0x68, - 0xbb, 0x43, 0x33, 0x60, - 0x00, 0xbe, 0x00, 0xbf, - 0x00, 0x20, 0x02, 0x40, - 0x10, 0x00, 0x00, 0x00, - 0x0c, 0x00, 0x00, 0x00, - 0x50, 0x00, 0x00, 0x20, - 0x54, 0x00, 0x00, 0x20, - 0x58, 0x00, 0x00, 0x20 -}; - -/* flashloaders/stm32f0.s -- thumb1 only, same sequence as for STM32VL, bank ignored */ -static const uint8_t loader_code_stm32f0[] = { - 0xc0, 0x46, 0xc0, 0x46, - 0x13, 0x4f, 0x3c, 0x68, - 0x13, 0x4f, 0x3e, 0x68, - 0x36, 0x19, 0x13, 0x4f, - 0x3d, 0x68, 0x2d, 0x19, - 0x12, 0x4f, 0x33, 0x68, - 0x3b, 0x43, 0x33, 0x60, - 0x03, 0x88, 0x0b, 0x80, - 0x10, 0x4f, 0xc0, 0x19, - 0xc9, 0x19, 0x0e, 0x4f, - 0x2b, 0x68, 0x3b, 0x42, - 0xfb, 0xd0, 0x0e, 0x4f, - 0x3b, 0x42, 0x03, 0xd1, - 0x0a, 0x4f, 0xd2, 0x1b, - 0x00, 0x2a, 0xeb, 0xd1, - 0x08, 0x4f, 0x33, 0x68, - 0xbb, 0x43, 0x33, 0x60, - 0x00, 0xbe, 0xc0, 0x46, - 0x00, 0x20, 0x02, 0x40, - 0x10, 0x00, 0x00, 0x00, - 0x0c, 0x00, 0x00, 0x00, - 0x48, 0x00, 0x00, 0x20, - 0x4c, 0x00, 0x00, 0x20, - 0x50, 0x00, 0x00, 0x20, - 0x01, 0x00, 0x00, 0x00, - 0x02, 0x00, 0x00, 0x00, - 0x04, 0x00, 0x00, 0x00 -}; - -static const uint8_t loader_code_stm32l[] = { - // flashloaders/stm32lx.s - - 0x03, 0x68, 0x0b, 0x60, - 0x4f, 0xf0, 0x04, 0x07, - 0x38, 0x44, 0x39, 0x44, - 0x4f, 0xf0, 0x01, 0x07, - 0xd2, 0x1b, 0x00, 0x2a, - 0xf4, 0xd1, 0x00, 0xbe, -}; - -static const uint8_t loader_code_stm32f4[] = { - // flashloaders/stm32f4.s - - 0xdf, 0xf8, 0x28, 0xc0, - 0xdf, 0xf8, 0x28, 0xa0, - 0xe2, 0x44, 0x03, 0x68, - 0x0b, 0x60, 0x00, 0xf1, - 0x04, 0x00, 0x01, 0xf1, - 0x04, 0x01, 0xba, 0xf8, - 0x00, 0x30, 0x13, 0xf0, - 0x01, 0x0f, 0xfa, 0xd0, - 0xa2, 0xf1, 0x01, 0x02, - 0x00, 0x2a, 0xf0, 0xd1, - 0x00, 0xbe, 0x00, 0xbf, - 0x00, 0x3c, 0x02, 0x40, - 0x0e, 0x00, 0x00, 0x00 -}; - -static const uint8_t loader_code_stm32f4_lv[] = { - // flashloaders/stm32f4lv.s - 0xdf, 0xf8, 0x2c, 0xc0, - 0xdf, 0xf8, 0x2c, 0xa0, - 0xe2, 0x44, 0x4f, 0xea, - 0x82, 0x02, 0x03, 0x78, - 0x0b, 0x70, 0x00, 0xf1, - 0x01, 0x00, 0x01, 0xf1, - 0x01, 0x01, 0xba, 0xf8, - 0x00, 0x30, 0x13, 0xf0, - 0x01, 0x0f, 0xfa, 0xd0, - 0xa2, 0xf1, 0x01, 0x02, - 0x00, 0x2a, 0xf0, 0xd1, - 0x00, 0xbe, 0x00, 0xbf, - 0x00, 0x3c, 0x02, 0x40, - 0x0e, 0x00, 0x00, 0x00 -}; - -static const uint8_t loader_code_stm32l4[] = { - // flashloaders/stm32l4.s - 0xdf, 0xf8, 0x2c, 0xc0, - 0xdf, 0xf8, 0x2c, 0xa0, - 0xe2, 0x44, 0x03, 0x68, - 0x44, 0x68, 0x0b, 0x60, - 0x4c, 0x60, 0x00, 0xf1, - 0x08, 0x00, 0x01, 0xf1, - 0x08, 0x01, 0xba, 0xf8, - 0x00, 0x30, 0x13, 0xf0, - 0x01, 0x0f, 0xfa, 0xd0, - 0xa2, 0xf1, 0x01, 0x02, - 0x00, 0x2a, 0xee, 0xd1, - 0x00, 0xbe, 0x00, 0xbf, - 0x00, 0x20, 0x02, 0x40, - 0x12, 0x00, 0x00, 0x00 -}; - -static const uint8_t loader_code_stm32f7[] = { - // flashloaders/stm32f7.s - 0xdf, 0xf8, 0x2c, 0xc0, - 0xdf, 0xf8, 0x2c, 0xa0, - 0xe2, 0x44, 0x03, 0x68, - 0x0b, 0x60, 0x00, 0xf1, - 0x04, 0x00, 0x01, 0xf1, - 0x04, 0x01, 0xbf, 0xf3, - 0x4f, 0x8f, 0xba, 0xf8, - 0x00, 0x30, 0x13, 0xf0, - 0x01, 0x0f, 0xfa, 0xd0, - 0xa2, 0xf1, 0x01, 0x02, - 0x00, 0x2a, 0xee, 0xd1, - 0x00, 0xbe, 0x00, 0xbf, - 0x00, 0x3c, 0x02, 0x40, - 0x0e, 0x00, 0x00, 0x00 -}; - -static const uint8_t loader_code_stm32f7_lv[] = { - // flashloaders/stm32f7lv.s - 0xdf, 0xf8, 0x30, 0xc0, - 0xdf, 0xf8, 0x30, 0xa0, - 0xe2, 0x44, 0x4f, 0xea, - 0x82, 0x02, 0x03, 0x78, - 0x0b, 0x70, 0x00, 0xf1, - 0x01, 0x00, 0x01, 0xf1, - 0x01, 0x01, 0xbf, 0xf3, - 0x4f, 0x8f, 0xba, 0xf8, - 0x00, 0x30, 0x13, 0xf0, - 0x01, 0x0f, 0xfa, 0xd0, - 0xa2, 0xf1, 0x01, 0x02, - 0x00, 0x2a, 0xee, 0xd1, - 0x00, 0xbe, 0x00, 0xbf, - 0x00, 0x3c, 0x02, 0x40, - 0x0e, 0x00, 0x00, 0x00 -}; - - -int stlink_flash_loader_init(stlink_t *sl, flash_loader_t *fl) { + /* flashloaders/stm32f0.s -- compiled with thumb2 */ + static const uint8_t loader_code_stm32vl[] = { + 0x16, 0x4f, 0x3c, 0x68, + 0x16, 0x4f, 0x3e, 0x68, + 0x36, 0x19, 0x16, 0x4f, + 0x3d, 0x68, 0x2d, 0x19, + 0x4f, 0xf0, 0x01, 0x07, + 0x33, 0x68, 0x3b, 0x43, + 0x33, 0x60, 0x03, 0x88, + 0x0b, 0x80, 0x4f, 0xf0, + 0x02, 0x07, 0xc0, 0x19, + 0xc9, 0x19, 0x4f, 0xf0, + 0x01, 0x07, 0x2b, 0x68, + 0x3b, 0x42, 0xfa, 0xd0, + 0x4f, 0xf0, 0x04, 0x07, + 0x3b, 0x42, 0x04, 0xd1, + 0x4f, 0xf0, 0x01, 0x07, + 0xd2, 0x1b, 0x00, 0x2a, + 0xe6, 0xd1, 0x4f, 0xf0, + 0x01, 0x07, 0x33, 0x68, + 0xbb, 0x43, 0x33, 0x60, + 0x00, 0xbe, 0x00, 0xbf, + 0x00, 0x20, 0x02, 0x40, + 0x10, 0x00, 0x00, 0x00, + 0x0c, 0x00, 0x00, 0x00, + 0x50, 0x00, 0x00, 0x20, + 0x54, 0x00, 0x00, 0x20, + 0x58, 0x00, 0x00, 0x20 + }; + + /* flashloaders/stm32f0.s -- thumb1 only, same sequence as for STM32VL, bank ignored */ + static const uint8_t loader_code_stm32f0[] = { + 0xc0, 0x46, 0xc0, 0x46, + 0x13, 0x4f, 0x3c, 0x68, + 0x13, 0x4f, 0x3e, 0x68, + 0x36, 0x19, 0x13, 0x4f, + 0x3d, 0x68, 0x2d, 0x19, + 0x12, 0x4f, 0x33, 0x68, + 0x3b, 0x43, 0x33, 0x60, + 0x03, 0x88, 0x0b, 0x80, + 0x10, 0x4f, 0xc0, 0x19, + 0xc9, 0x19, 0x0e, 0x4f, + 0x2b, 0x68, 0x3b, 0x42, + 0xfb, 0xd0, 0x0e, 0x4f, + 0x3b, 0x42, 0x03, 0xd1, + 0x0a, 0x4f, 0xd2, 0x1b, + 0x00, 0x2a, 0xeb, 0xd1, + 0x08, 0x4f, 0x33, 0x68, + 0xbb, 0x43, 0x33, 0x60, + 0x00, 0xbe, 0xc0, 0x46, + 0x00, 0x20, 0x02, 0x40, + 0x10, 0x00, 0x00, 0x00, + 0x0c, 0x00, 0x00, 0x00, + 0x48, 0x00, 0x00, 0x20, + 0x4c, 0x00, 0x00, 0x20, + 0x50, 0x00, 0x00, 0x20, + 0x01, 0x00, 0x00, 0x00, + 0x02, 0x00, 0x00, 0x00, + 0x04, 0x00, 0x00, 0x00 + }; + + static const uint8_t loader_code_stm32l[] = { + // flashloaders/stm32lx.s + + 0x03, 0x68, 0x0b, 0x60, + 0x4f, 0xf0, 0x04, 0x07, + 0x38, 0x44, 0x39, 0x44, + 0x4f, 0xf0, 0x01, 0x07, + 0xd2, 0x1b, 0x00, 0x2a, + 0xf4, 0xd1, 0x00, 0xbe, + }; + + static const uint8_t loader_code_stm32f4[] = { + // flashloaders/stm32f4.s + + 0xdf, 0xf8, 0x28, 0xc0, + 0xdf, 0xf8, 0x28, 0xa0, + 0xe2, 0x44, 0x03, 0x68, + 0x0b, 0x60, 0x00, 0xf1, + 0x04, 0x00, 0x01, 0xf1, + 0x04, 0x01, 0xba, 0xf8, + 0x00, 0x30, 0x13, 0xf0, + 0x01, 0x0f, 0xfa, 0xd0, + 0xa2, 0xf1, 0x01, 0x02, + 0x00, 0x2a, 0xf0, 0xd1, + 0x00, 0xbe, 0x00, 0xbf, + 0x00, 0x3c, 0x02, 0x40, + 0x0e, 0x00, 0x00, 0x00 + }; + + static const uint8_t loader_code_stm32f4_lv[] = { + // flashloaders/stm32f4lv.s + 0xdf, 0xf8, 0x2c, 0xc0, + 0xdf, 0xf8, 0x2c, 0xa0, + 0xe2, 0x44, 0x4f, 0xea, + 0x82, 0x02, 0x03, 0x78, + 0x0b, 0x70, 0x00, 0xf1, + 0x01, 0x00, 0x01, 0xf1, + 0x01, 0x01, 0xba, 0xf8, + 0x00, 0x30, 0x13, 0xf0, + 0x01, 0x0f, 0xfa, 0xd0, + 0xa2, 0xf1, 0x01, 0x02, + 0x00, 0x2a, 0xf0, 0xd1, + 0x00, 0xbe, 0x00, 0xbf, + 0x00, 0x3c, 0x02, 0x40, + 0x0e, 0x00, 0x00, 0x00 + }; + + static const uint8_t loader_code_stm32l4[] = { + // flashloaders/stm32l4.s + 0xdf, 0xf8, 0x2c, 0xc0, + 0xdf, 0xf8, 0x2c, 0xa0, + 0xe2, 0x44, 0x03, 0x68, + 0x44, 0x68, 0x0b, 0x60, + 0x4c, 0x60, 0x00, 0xf1, + 0x08, 0x00, 0x01, 0xf1, + 0x08, 0x01, 0xba, 0xf8, + 0x00, 0x30, 0x13, 0xf0, + 0x01, 0x0f, 0xfa, 0xd0, + 0xa2, 0xf1, 0x01, 0x02, + 0x00, 0x2a, 0xee, 0xd1, + 0x00, 0xbe, 0x00, 0xbf, + 0x00, 0x20, 0x02, 0x40, + 0x12, 0x00, 0x00, 0x00 + }; + + static const uint8_t loader_code_stm32f7[] = { + // flashloaders/stm32f7.s + 0xdf, 0xf8, 0x2c, 0xc0, + 0xdf, 0xf8, 0x2c, 0xa0, + 0xe2, 0x44, 0x03, 0x68, + 0x0b, 0x60, 0x00, 0xf1, + 0x04, 0x00, 0x01, 0xf1, + 0x04, 0x01, 0xbf, 0xf3, + 0x4f, 0x8f, 0xba, 0xf8, + 0x00, 0x30, 0x13, 0xf0, + 0x01, 0x0f, 0xfa, 0xd0, + 0xa2, 0xf1, 0x01, 0x02, + 0x00, 0x2a, 0xee, 0xd1, + 0x00, 0xbe, 0x00, 0xbf, + 0x00, 0x3c, 0x02, 0x40, + 0x0e, 0x00, 0x00, 0x00 + }; + + static const uint8_t loader_code_stm32f7_lv[] = { + // flashloaders/stm32f7lv.s + 0xdf, 0xf8, 0x30, 0xc0, + 0xdf, 0xf8, 0x30, 0xa0, + 0xe2, 0x44, 0x4f, 0xea, + 0x82, 0x02, 0x03, 0x78, + 0x0b, 0x70, 0x00, 0xf1, + 0x01, 0x00, 0x01, 0xf1, + 0x01, 0x01, 0xbf, 0xf3, + 0x4f, 0x8f, 0xba, 0xf8, + 0x00, 0x30, 0x13, 0xf0, + 0x01, 0x0f, 0xfa, 0xd0, + 0xa2, 0xf1, 0x01, 0x02, + 0x00, 0x2a, 0xee, 0xd1, + 0x00, 0xbe, 0x00, 0xbf, + 0x00, 0x3c, 0x02, 0x40, + 0x0e, 0x00, 0x00, 0x00 + }; + + + +int stlink_flash_loader_init(stlink_t *sl, flash_loader_t *fl) +{ size_t size = 0; - // allocate the loader in SRAM + /* allocate the loader in sram */ if (stlink_flash_loader_write_to_sram(sl, &fl->loader_addr, &size) == -1) { WLOG("Failed to write flash loader to sram!\n"); - return(-1); + return -1; } - // allocate a one page buffer in SRAM right after loader - fl->buf_addr = fl->loader_addr + (uint32_t)size; + /* allocate a one page buffer in sram right after loader */ + fl->buf_addr = fl->loader_addr + (uint32_t) size; ILOG("Successfully loaded flash loader in sram\n"); - return(0); + return 0; } static int loader_v_dependent_assignment(stlink_t *sl, const uint8_t **loader_code, size_t *loader_size, const uint8_t *high_v_loader, size_t high_v_loader_size, - const uint8_t *low_v_loader, size_t low_v_loader_size) { + const uint8_t *low_v_loader, size_t low_v_loader_size) +{ int retval = 0; - if ( sl->version.stlink_v == 1) { + if ( sl->version.stlink_v == 1){ printf("STLINK V1 cannot read voltage, defaulting to 32-bit writes\n"); *loader_code = high_v_loader; *loader_size = high_v_loader_size; - } else { + } + else { int voltage = stlink_target_voltage(sl); - if (voltage == -1) { retval = -1; printf("Failed to read Target voltage\n"); - } else { + } + else { if (voltage > 2700) { *loader_code = high_v_loader; *loader_size = high_v_loader_size; @@ -216,11 +219,11 @@ static int loader_v_dependent_assignment(stlink_t *sl, } } } - - return(retval); + return retval; } -int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) { +int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) +{ const uint8_t* loader_code; size_t loader_size; @@ -232,7 +235,7 @@ int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* sl->chip_id == STLINK_CHIPID_STM32_L011 || sl->chip_id == STLINK_CHIPID_STM32_L0 || sl->chip_id == STLINK_CHIPID_STM32_L0_CAT5 || - sl->chip_id == STLINK_CHIPID_STM32_L0_CAT2) { // STM32l + sl->chip_id == STLINK_CHIPID_STM32_L0_CAT2) { /* stm32l */ loader_code = loader_code_stm32l; loader_size = sizeof(loader_code_stm32l); } else if (sl->core_id == STM32VL_CORE_ID || @@ -245,34 +248,38 @@ int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* loader_code = loader_code_stm32vl; loader_size = sizeof(loader_code_stm32vl); } else if (sl->chip_id == STLINK_CHIPID_STM32_F2 || - sl->chip_id == STLINK_CHIPID_STM32_F4 || - sl->chip_id == STLINK_CHIPID_STM32_F4_DE || - sl->chip_id == STLINK_CHIPID_STM32_F4_LP || - sl->chip_id == STLINK_CHIPID_STM32_F4_HD || - sl->chip_id == STLINK_CHIPID_STM32_F4_DSI || - sl->chip_id == STLINK_CHIPID_STM32_F410 || - sl->chip_id == STLINK_CHIPID_STM32_F411RE || - sl->chip_id == STLINK_CHIPID_STM32_F412 || - sl->chip_id == STLINK_CHIPID_STM32_F413 || - sl->chip_id == STLINK_CHIPID_STM32_F446) { + sl->chip_id == STLINK_CHIPID_STM32_F4 || + sl->chip_id == STLINK_CHIPID_STM32_F4_DE || + sl->chip_id == STLINK_CHIPID_STM32_F4_LP || + sl->chip_id == STLINK_CHIPID_STM32_F4_HD || + sl->chip_id == STLINK_CHIPID_STM32_F4_DSI || + sl->chip_id == STLINK_CHIPID_STM32_F410 || + sl->chip_id == STLINK_CHIPID_STM32_F411RE || + sl->chip_id == STLINK_CHIPID_STM32_F412 || + sl->chip_id == STLINK_CHIPID_STM32_F413 || + sl->chip_id == STLINK_CHIPID_STM32_F446 + ) { int retval; retval = loader_v_dependent_assignment(sl, &loader_code, &loader_size, loader_code_stm32f4, sizeof(loader_code_stm32f4), loader_code_stm32f4_lv, sizeof(loader_code_stm32f4_lv)); - - if (retval == -1) { return(retval); } + if (retval == -1) { + return retval; + } } else if (sl->core_id == STM32F7_CORE_ID || sl->chip_id == STLINK_CHIPID_STM32_F7 || sl->chip_id == STLINK_CHIPID_STM32_F7XXXX || - sl->chip_id == STLINK_CHIPID_STM32_F72XXX) { + sl->chip_id == STLINK_CHIPID_STM32_F72XXX + ) { int retval; retval = loader_v_dependent_assignment(sl, &loader_code, &loader_size, loader_code_stm32f7, sizeof(loader_code_stm32f7), loader_code_stm32f7_lv, sizeof(loader_code_stm32f7_lv)); - - if (retval == -1) { return(retval); } + if (retval == -1) { + return retval; + } } else if (sl->chip_id == STLINK_CHIPID_STM32_F0 || sl->chip_id == STLINK_CHIPID_STM32_F04 || sl->chip_id == STLINK_CHIPID_STM32_F0_CAN || @@ -285,102 +292,101 @@ int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* (sl->chip_id == STLINK_CHIPID_STM32_L43X) || (sl->chip_id == STLINK_CHIPID_STM32_L46X) || (sl->chip_id == STLINK_CHIPID_STM32_L4RX) || - (sl->chip_id == STLINK_CHIPID_STM32_L496X)) { + (sl->chip_id == STLINK_CHIPID_STM32_L496X)) + { loader_code = loader_code_stm32l4; loader_size = sizeof(loader_code_stm32l4); } else { - ELOG("unknown coreid, not sure what flash loader to use, aborting! coreid: %x, chipid: %x\n", - sl->core_id, sl->chip_id); - return(-1); + ELOG("unknown coreid, not sure what flash loader to use, aborting! coreid: %x, chipid: %x\n", sl->core_id, sl->chip_id); + return -1; } memcpy(sl->q_buf, loader_code, loader_size); int ret = stlink_write_mem32(sl, sl->sram_base, loader_size); - - if (ret) { return(ret); } + if (ret) + return ret; *addr = sl->sram_base; *size = loader_size; - return(0); // success + /* success */ + return 0; } -int stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, const uint8_t* buf, size_t size) { +int stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, const uint8_t* buf, size_t size) +{ struct stlink_reg rr; int i = 0; size_t count = 0; uint32_t flash_base = 0; DLOG("Running flash loader, write address:%#x, size: %u\n", target, (unsigned int)size); - - // TODO: This can never return -1 + // FIXME This can never return -1 if (write_buffer_to_sram(sl, fl, buf, size) == -1) { // IMPOSSIBLE! ELOG("write_buffer_to_sram() == -1\n"); - return(-1); + return -1; } if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || (sl->flash_type == STLINK_FLASH_TYPE_F1_XL)) { count = size / sizeof(uint16_t); - - if (size % sizeof(uint16_t)) { ++count; } + if (size % sizeof(uint16_t)) + ++count; } else if (sl->flash_type == STLINK_FLASH_TYPE_F4 || sl->flash_type == STLINK_FLASH_TYPE_L0) { count = size / sizeof(uint32_t); - - if (size % sizeof(uint32_t)) { ++count; } + if (size % sizeof(uint32_t)) + ++count; } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { count = size / sizeof(uint64_t); - - if (size % sizeof(uint64_t)) { ++count; } + if (size % sizeof(uint64_t)) + ++count; } if ((sl->flash_type == STLINK_FLASH_TYPE_F1_XL) && (target >= FLASH_BANK2_START_ADDR)) { flash_base = FLASH_REGS_BANK2_OFS; } - /* Setup core */ - stlink_write_reg(sl, fl->buf_addr, 0); // source - stlink_write_reg(sl, target, 1); // target - stlink_write_reg(sl, (uint32_t)count, 2); // count - stlink_write_reg(sl, flash_base, 3); // flash register base - // only used on VL/F1_XL, but harmless for others - stlink_write_reg(sl, fl->loader_addr, 15); // pc register + /* setup core */ + stlink_write_reg(sl, fl->buf_addr, 0); /* source */ + stlink_write_reg(sl, target, 1); /* target */ + stlink_write_reg(sl, (uint32_t) count, 2); /* count */ + stlink_write_reg(sl, flash_base, 3); /* flash register base, only used on VL/F1_XL, but harmless for others */ + stlink_write_reg(sl, fl->loader_addr, 15); /* pc register */ - /* Run loader */ + /* run loader */ stlink_run(sl); -/* This piece of code used to try to spin for .1 second by waiting doing 10000 rounds of 10 µs. - * But because this usually runs on Unix-like OSes, the 10 µs get rounded up to the "tick" - * (actually almost two ticks) of the system. 1 ms. Thus, the ten thousand attempts, when - * "something goes wrong" that requires the error message "flash loader run error" would wait - * for something like 20 seconds before coming up with the error. - * By increasing the sleep-per-round to the same order-of-magnitude as the tick-rounding that - * the OS uses, the wait until the error message is reduced to the same order of magnitude - * as what was intended. -- REW. - */ -#define WAIT_ROUNDS 30 - - // wait until done (reaches breakpoint) +// This piece of code used to try to spin for .1 second by waiting +// doing 10000 rounds of 10 microseconds. But because this usually runs +// on Unix-like OSes, the 10 microseconds get rounded up to the "tick" +// (actually almost two ticks) of the system. 1 milisecond. Thus, the +// ten thousand attempts, when "something goes wrong" that requires +// the error message "flash loader run error" would wait for something +// like 20 seconds before coming up with the error. +// by increasing the sleep-per-round to the same order-of-magnitude as +// the tick-rounding that the OS uses, the wait until the error message is +// reduced to the same order of magnitude as what was intended. -- REW. +#define WAIT_ROUNDS 100 + /* wait until done (reaches breakpoint) */ for (i = 0; i < WAIT_ROUNDS; i++) { - usleep(10000); - - if (stlink_is_core_halted(sl)) { break; } + usleep(1000); + if (stlink_is_core_halted(sl)) + break; } if (i >= WAIT_ROUNDS) { ELOG("flash loader run error\n"); - return(-1); + return -1; } - // check written byte count + /* check written byte count */ stlink_read_reg(sl, 2, &rr); - if (rr.r[2] != 0) { ELOG("write error, count == %u\n", rr.r[2]); - return(-1); + return -1; } - return(0); + return 0; } From 77c58f054e091f9c2c4c2db7cdb44e242901b24b Mon Sep 17 00:00:00 2001 From: Rutger Hendriks Date: Thu, 25 Jun 2020 14:55:34 +0200 Subject: [PATCH 057/503] re-applied the changes to the original files --- src/st-flash/flash_opts.c | 455 ++++++++++++++++--------------- src/stlink-lib/flash_loader.c | 486 +++++++++++++++++----------------- 2 files changed, 478 insertions(+), 463 deletions(-) diff --git a/src/st-flash/flash_opts.c b/src/st-flash/flash_opts.c index 8557445e0..6653c6e62 100644 --- a/src/st-flash/flash_opts.c +++ b/src/st-flash/flash_opts.c @@ -2,11 +2,12 @@ #include #include -#include +#include "flash.h" static bool starts_with(const char * str, const char * prefix) { size_t n = strlen(prefix); - if (strlen(str) < n) return false; + + if (strlen(str) < n) { return(false); } return (0 == strncmp(str, prefix, n)); } @@ -19,37 +20,28 @@ static int get_long_integer_from_char_array (const char *const str, uint64_t *re uint64_t value; char *tail; - // hexadecimal - if (starts_with (str, "0x") || starts_with (str, "0X")) { + if (starts_with (str, "0x") || starts_with (str, "0X")) { // hexadecimal value = strtoul (str + 2, &tail, 16); - } - // binary - else if (starts_with (str, "0b") || starts_with (str, "0B")) { + } else if (starts_with (str, "0b") || starts_with (str, "0B")) { // binary value = strtoul (str + 2, &tail, 2); - } - // octal - else if (starts_with (str, "0")) { + } else if (starts_with (str, "0")) { // octal value = strtoul (str + 1, &tail, 8); - } - // decimal - else { + } else { // decimal value = strtoul (str, &tail, 10); } if (((tail[0] == 'k') || (tail[0] == 'K')) && (tail[1] == '\0')) { value = value * 1024; - } - else if (((tail[0] == 'm') || (tail[0] == 'M')) && (tail[1] == '\0')) { + } else if (((tail[0] == 'm') || (tail[0] == 'M')) && (tail[1] == '\0')) { value = value * 1024 * 1024; + } else if (tail[0] == '\0') { + /* value not changed */ + } else { + return(-1); } - else if (tail[0] == '\0') { - // value not change - } - else { - return -1; - } + *read_value = value; - return 0; + return(0); } // support positive integer from 0 to UINT32_MAX @@ -59,28 +51,26 @@ static int get_long_integer_from_char_array (const char *const str, uint64_t *re static int get_integer_from_char_array (const char *const str, uint32_t *read_value) { uint64_t value; int result = get_long_integer_from_char_array (str, &value); + if (result != 0) { - return result; - } - else if (value > UINT32_MAX) { - fprintf (stderr, "*** Error: Integer greater than UINT32_MAX, \ -cannot convert to int32_t\n"); - return -1; - } - else { + return(result); + } else if (value > UINT32_MAX) { + fprintf (stderr, "*** Error: Integer greater than UINT32_MAX, cannot convert to int32_t\n"); + return(-1); + } else { *read_value = (uint32_t)value; - return 0; + return(0); } } static int invalid_args(const char *expected) { fprintf(stderr, "*** Error: Expected args for this command: %s\n", expected); - return -1; + return(-1); } static int bad_arg(const char *arg) { fprintf(stderr, "*** Error: Invalid value for %s\n", arg); - return -1; + return(-1); } int flash_get_opts(struct flash_opts* o, int ac, char** av) { @@ -91,148 +81,158 @@ int flash_get_opts(struct flash_opts* o, int ac, char** av) { // options int result; + while (ac >= 1) { if (strcmp(av[0], "--version") == 0) { printf("v%s\n", STLINK_VERSION); exit(EXIT_SUCCESS); - } - else if (strcmp(av[0], "--debug") == 0) { + } else if (strcmp(av[0], "--debug") == 0) { o->log_level = DEBUG_LOG_LEVEL; - } - else if (strcmp(av[0], "--opt") == 0) { + } else if (strcmp(av[0], "--opt") == 0) { o->opt = ENABLE_OPT; - } - else if (strcmp(av[0], "--reset") == 0) { + } else if (strcmp(av[0], "--reset") == 0) { o->reset = 1; - } - else if (strcmp(av[0], "--serial") == 0 || starts_with(av[0], "--serial=")) { + } else if (strcmp(av[0], "--serial") == 0 || starts_with(av[0], "--serial=")) { const char * serial; + if (strcmp(av[0], "--serial") == 0) { ac--; av++; - if (ac < 1) return -1; + + if (ac < 1) { return(-1); } + serial = av[0]; - } - else { + } else { serial = av[0] + strlen("--serial="); } - /** @todo This is not really portable, as strlen really returns size_t we need to obey and not cast it to a signed type. */ + + /** @todo This is not really portable, as strlen really returns size_t we need to obey + and not cast it to a signed type. */ int j = (int)strlen(serial); - int length = j / 2; // the length of the destination-array - if (j % 2 != 0) return -1; + int length = j / 2; // the length of the destination-array + + if (j % 2 != 0) { return(-1); } + for (size_t k = 0; j >= 0 && k < sizeof(o->serial); ++k, j -= 2) { char buffer[3] = {0}; memcpy(buffer, serial + j, 2); o->serial[length - k] = (uint8_t)strtol(buffer, NULL, 16); } - } - else if (strcmp(av[0], "--area") == 0 || starts_with(av[0], "--area=")) { + } else if (strcmp(av[0], "--area") == 0 || starts_with(av[0], "--area=")) { const char * area; + if (strcmp(av[0], "--area") == 0) { ac--; av++; - if (ac < 1) return -1; + + if (ac < 1) { return(-1); } + area = av[0]; - } - else { + } else { area = av[0] + strlen("--area="); } - if (strcmp(area, "main") == 0) + + if (strcmp(area, "main") == 0) { o->area = FLASH_MAIN_MEMORY; - else if (strcmp(area, "system") == 0) + } else if (strcmp(area, "system") == 0) { o->area = FLASH_SYSTEM_MEMORY; - else if (strcmp(area, "otp") == 0) + } else if (strcmp(area, "otp") == 0) { o->area = FLASH_OTP; - else if (strcmp(area, "option") == 0) + } else if (strcmp(area, "option") == 0) { o->area = FLASH_OPTION_BYTES; - else if (strcmp(area, "option_boot_add") == 0) + } else if (strcmp(area, "option_boot_add") == 0) { o->area = FLASH_OPTION_BYTES_BOOT_ADD; - else if (strcmp(area, "optcr") == 0) + } else if (strcmp(area, "optcr") == 0) { o->area = FLASH_OPTCR; - else if (strcmp(area, "optcr1") == 0) + } else if (strcmp(area, "optcr1") == 0) { o->area = FLASH_OPTCR1; - else - return -1; + } else { + return(-1); + } - } - else if (strcmp(av[0], "--freq") == 0 || starts_with(av[0], "--freq=")) { + } else if (strcmp(av[0], "--freq") == 0 || starts_with(av[0], "--freq=")) { const char* freq; + if (strcmp(av[0], "--freq") == 0) { ac--; av++; - if (ac < 1) return -1; + + if (ac < 1) { + return(-1); + } + freq = av[0]; - } - else { + } else { freq = av[0] + strlen("--freq="); } + if (strcmp(freq, "5K") == 0 || strcmp(freq, "5k") == 0) { o->freq = 5; - } - else if (strcmp(freq, "15K") == 0 || strcmp(freq, "15k") == 0) { + } else if (strcmp(freq, "15K") == 0 || strcmp(freq, "15k") == 0) { o->freq = 15; - } - else if (strcmp(freq, "25K") == 0 || strcmp(freq, "25k") == 0) { + } else if (strcmp(freq, "25K") == 0 || strcmp(freq, "25k") == 0) { o->freq = 25; - } - else if (strcmp(freq, "50K") == 0 || strcmp(freq, "50k") == 0) { + } else if (strcmp(freq, "50K") == 0 || strcmp(freq, "50k") == 0) { o->freq = 50; - } - else if (strcmp(freq, "100K") == 0 || strcmp(freq, "100k") == 0) { + } else if (strcmp(freq, "100K") == 0 || strcmp(freq, "100k") == 0) { o->freq = 100; - } - else if (strcmp(freq, "125K") == 0 || strcmp(freq, "125k") == 0) { + } else if (strcmp(freq, "125K") == 0 || strcmp(freq, "125k") == 0) { o->freq = 125; - } - else if (strcmp(freq, "240K") == 0 || strcmp(freq, "240k") == 0) { + } else if (strcmp(freq, "240K") == 0 || strcmp(freq, "240k") == 0) { o->freq = 240; - } - else if (strcmp(freq, "480K") == 0 || strcmp(freq, "480k") == 0) { + } else if (strcmp(freq, "480K") == 0 || strcmp(freq, "480k") == 0) { o->freq = 480; - } - else if (strcmp(freq, "950K") == 0 || strcmp(freq, "950k") == 0) { + } else if (strcmp(freq, "950K") == 0 || strcmp(freq, "950k") == 0) { o->freq = 950; - } - else if (strcmp(freq, "1200K") == 0 || strcmp(freq, "1200k") == 0 || strcmp(freq, "1.2M") == 0 || strcmp(freq, "1.2m") == 0) { + } else if (strcmp(freq, "1200K") == 0 || strcmp(freq, "1200k") == 0 || + strcmp(freq, "1.2M") == 0 || strcmp(freq, "1.2m") == 0) { o->freq = 1200; - } - else if (strcmp(freq, "1800K") == 0 || strcmp(freq, "1800k") == 0 || strcmp(freq, "1.8M") == 0 || strcmp(freq, "1.8m") == 0) { + } else if (strcmp(freq, "1800K") == 0 || strcmp(freq, "1800k") == 0 || + strcmp(freq, "1.8M") == 0 || strcmp(freq, "1.8m") == 0) { o->freq = 1800; - } - else if (strcmp(freq, "4000K") == 0 || strcmp(freq, "4000k") == 0 || strcmp(freq, "4M") == 0 || strcmp(freq, "4m") == 0) { + } else if (strcmp(freq, "4000K") == 0 || strcmp(freq, "4000k") == 0 || + strcmp(freq, "4M") == 0 || strcmp(freq, "4m") == 0) { o->freq = 4000; + } else { + return(-1); } - else - return -1; - } - else if (strcmp(av[0], "--format") == 0 || starts_with(av[0], "--format=")) { + } else if (strcmp(av[0], "--format") == 0 || starts_with(av[0], "--format=")) { const char * format; + if (strcmp(av[0], "--format") == 0) { ac--; av++; - if (ac < 1) return -1; + + if (ac < 1) { return(-1); } + format = av[0]; - } - else { + } else { format = av[0] + strlen("--format="); } - if (strcmp(format, "binary") == 0) + + if (strcmp(format, "binary") == 0) { o->format = FLASH_FORMAT_BINARY; - else if (strcmp(format, "ihex") == 0) + } else if (strcmp(format, "ihex") == 0) { o->format = FLASH_FORMAT_IHEX; - else - return bad_arg("format"); - } - else if ( starts_with(av[0], "--flash=") ) { + } else { + return(bad_arg("format")); + } + } else if ( starts_with(av[0], "--flash=")) { const char *arg = av[0] + strlen("--flash="); uint32_t flash_size; result = get_integer_from_char_array(arg, &flash_size); - if (result != 0) return bad_arg ("--flash"); - else o->flash_size = (size_t) flash_size; - } - else { - break; // non-option found + + if (result != 0) { + return(bad_arg ("--flash")); + } else { + o->flash_size = (size_t)flash_size; + } + } else if (strcmp(av[0], "--connect-under-reset") == 0) { + o->connect_under_reset = true; + } else { + break; // non-option found + } ac--; @@ -242,22 +242,21 @@ int flash_get_opts(struct flash_opts* o, int ac, char** av) { // command and (optional) device name while (ac >= 1) { if (strcmp(av[0], "erase") == 0) { - if (FLASH_CMD_NONE != o->cmd) return -1; + if (FLASH_CMD_NONE != o->cmd) { return(-1); } o->cmd = FLASH_CMD_ERASE; - } - else if (strcmp(av[0], "read") == 0) { - if (FLASH_CMD_NONE != o->cmd) return -1; + } else if (strcmp(av[0], "read") == 0) { + if (FLASH_CMD_NONE != o->cmd) { return(-1); } + o->cmd = FLASH_CMD_READ; - } - else if (strcmp(av[0], "write") == 0) { - if (FLASH_CMD_NONE != o->cmd) return -1; + } else if (strcmp(av[0], "write") == 0) { + if (FLASH_CMD_NONE != o->cmd) { return(-1); } + o->cmd = FLASH_CMD_WRITE; - } - else if (strcmp(av[0], "reset") == 0) { - if (FLASH_CMD_NONE != o->cmd) return -1; + } else if (strcmp(av[0], "reset") == 0) { + if (FLASH_CMD_NONE != o->cmd) { return(-1); } + o->cmd = CMD_RESET; - } - else { + } else { break; } @@ -265,120 +264,142 @@ int flash_get_opts(struct flash_opts* o, int ac, char** av) { av++; } - switch(o->cmd) { - case FLASH_CMD_NONE: // no command found - return -1; - - case FLASH_CMD_ERASE: // no more arguments expected - if (ac != 0) return -1; - break; + switch (o->cmd) { + case FLASH_CMD_NONE: // no command found + return(-1); - case FLASH_CMD_READ: // expect filename, addr and size - if ((FLASH_MAIN_MEMORY == o->area) || (FLASH_SYSTEM_MEMORY == o->area)) { - if (ac != 3) return invalid_args("read "); - o->filename = av[0]; - uint32_t address; - result = get_integer_from_char_array(av[1], &address); - if (result != 0) return bad_arg ("addr"); - else o->addr = (stm32_addr_t) address; + case FLASH_CMD_ERASE: // no more arguments expected + if (ac != 0) { return(-1); } - uint32_t size; - result = get_integer_from_char_array(av[2], &size); - if (result != 0) return bad_arg ("size"); - else o->size = (size_t) size; + break; - break; + case FLASH_CMD_READ: // expect filename, addr and size + if ((FLASH_MAIN_MEMORY == o->area) || (FLASH_SYSTEM_MEMORY == o->area)) { + if (ac != 3) { return invalid_args("read "); } + + o->filename = av[0]; + uint32_t address; + result = get_integer_from_char_array(av[1], &address); + if (result != 0) { + return bad_arg ("addr"); + } else { + o->addr = (stm32_addr_t) address; } - else if ((FLASH_OTP == o->area)) { - return bad_arg("TODO: otp not implemented yet"); - if (ac > 1) return invalid_args("otp read: [path]"); - if (ac > 0) o->filename = av[0]; - break; + + uint32_t size; + result = get_integer_from_char_array(av[2], &size); + if (result != 0) { + return bad_arg ("size"); + } else { + o->size = (size_t) size; } - else if ((FLASH_OPTION_BYTES == o->area)) { - if (ac > 2) return invalid_args("option bytes read: [path] [size]"); - if (ac > 0) o->filename = av[0]; - if (ac > 1) { - uint32_t size; - result = get_integer_from_char_array(av[1], &size); - if (result != 0) return bad_arg("option bytes read: invalid size"); - else o->size = (size_t) size; + + break; + } else if ((FLASH_OTP == o->area)) { + return bad_arg("TODO: otp not implemented yet"); + if (ac > 1) { return invalid_args("otp read: [path]"); } + if (ac > 0) { o->filename = av[0]; } + break; + } else if ((FLASH_OPTION_BYTES == o->area)) { + if (ac > 2) { return invalid_args("option bytes read: [path] [size]"); } + if (ac > 0) { o->filename = av[0]; } + if (ac > 1) { + uint32_t size; + result = get_integer_from_char_array(av[1], &size); + if (result != 0) { + return bad_arg("option bytes read: invalid size"); + } else { + o->size = (size_t) size; } - break; - } - else if ((FLASH_OPTION_BYTES_BOOT_ADD == o->area)) { - if (ac > 0) return invalid_args("option bytes boot_add read"); - break; - } - else if ((FLASH_OPTCR == o->area)) { - if (ac > 0) return invalid_args("option control register read"); - break; - } - else if ((FLASH_OPTCR1 == o->area)) { - if (ac > 0) return invalid_args("option control register 1 read"); - break; } break; + } else if ((FLASH_OPTION_BYTES_BOOT_ADD == o->area)) { + if (ac > 0) { return invalid_args("option bytes boot_add read"); } + break; + } else if ((FLASH_OPTCR == o->area)) { + if (ac > 0) { return invalid_args("option control register read"); } + break; + } else if ((FLASH_OPTCR1 == o->area)) { + if (ac > 0) { return invalid_args("option control register 1 read"); } + break; + } - case FLASH_CMD_WRITE: - // TODO: should be boot add 0 and boot add 1 uint32 - if (FLASH_OPTION_BYTES == o->area) { // expect filename and optional address - if (ac >=1 && ac <= 2) { - o->filename = av[0]; - } - else - return invalid_args("write [addr]"); - - if (ac == 2) { - uint32_t addr; - result = get_integer_from_char_array(av[1], &addr); - if (result != 0) return bad_arg ("addr"); - else o->addr = (stm32_addr_t) addr; - } - } - else if (FLASH_OPTION_BYTES_BOOT_ADD == o->area) { // expect option bytes boot address - if (ac != 1) return invalid_args("option bytes boot_add write "); - - uint32_t val; - result = get_integer_from_char_array(av[0], &val); - if (result != 0) return bad_arg ("val"); - else o->val = (uint32_t) val; - } - else if (FLASH_OPTCR == o->area) { // expect option control register value - if (ac != 1) return invalid_args("option control register write "); - - uint32_t val; - result = get_integer_from_char_array(av[0], &val); - if (result != 0) return bad_arg ("val"); - else o->val = (uint32_t) val; - } - else if (FLASH_OPTCR1 == o->area) { // expect option control register 1 value - if (ac != 1) return invalid_args("option control register 1 write "); - - uint32_t val; - result = get_integer_from_char_array(av[0], &val); - if (result != 0) return bad_arg ("val"); - else o->val = (uint32_t) val; - } - else if (FLASH_FORMAT_BINARY == o->format) { // expect filename and addr - if (ac != 2) return invalid_args("write "); + break; + + case FLASH_CMD_WRITE: + // TODO: should be boot add 0 and boot add 1 uint32 + if (FLASH_OPTION_BYTES == o->area) { // expect filename and optional address + if (ac >=1 && ac <= 2) { o->filename = av[0]; + } else { + return invalid_args("write [addr]"); + } + + if (ac == 2) { uint32_t addr; result = get_integer_from_char_array(av[1], &addr); - if (result != 0) return bad_arg ("addr"); - else o->addr = (stm32_addr_t) addr; - } - else if (FLASH_FORMAT_IHEX == o->format) { // expect filename - if (ac != 1) return invalid_args("write "); - o->filename = av[0]; + if (result != 0) { + return bad_arg ("addr"); + } else { + o->addr = (stm32_addr_t) addr; + } } - else { - return -1; // should have been caught during format parsing + } else if (FLASH_OPTION_BYTES_BOOT_ADD == o->area) { // expect option bytes boot address + if (ac != 1) { return invalid_args("option bytes boot_add write "); } + + uint32_t val; + result = get_integer_from_char_array(av[0], &val); + + if (result != 0) { + return(bad_arg ("val")); + } else { + o->val = (uint32_t)val; + } + } else if (FLASH_OPTCR == o->area) { // expect option control register value + if (ac != 1) { return invalid_args("option control register write "); } + + uint32_t val; + result = get_integer_from_char_array(av[0], &val); + + if (result != 0) { + return bad_arg ("val"); + } else { + o->val = (uint32_t) val; + } + } else if (FLASH_OPTCR1 == o->area) { // expect option control register 1 value + if (ac != 1) { return invalid_args("option control register 1 write "); } + + uint32_t val; + result = get_integer_from_char_array(av[0], &val); + if (result != 0) { + return bad_arg ("val"); + } else { + o->val = (uint32_t) val; + } + } else if (FLASH_FORMAT_BINARY == o->format) { // expect filename and addr + if (ac != 2) { return invalid_args("write "); } + + o->filename = av[0]; + uint32_t addr; + result = get_integer_from_char_array(av[1], &addr); + + if (result != 0) { + return(bad_arg ("addr")); + } else { + o->addr = (stm32_addr_t)addr; } - break; + } else if (o->format == FLASH_FORMAT_IHEX) { // expect filename + if (ac != 1) { return(invalid_args("write ")); } + + o->filename = av[0]; + } else { + return(-1); // should have been caught during format parsing + } + + break; - default: break ; + default: break; } - return 0; + return(0); } diff --git a/src/stlink-lib/flash_loader.c b/src/stlink-lib/flash_loader.c index b6058cd0e..0e79c3c0a 100644 --- a/src/stlink-lib/flash_loader.c +++ b/src/stlink-lib/flash_loader.c @@ -3,213 +3,210 @@ #include #include +#include "flash_loader.h" #define FLASH_REGS_BANK2_OFS 0x40 #define FLASH_BANK2_START_ADDR 0x08080000 /* DO NOT MODIFY SOURCECODE DIRECTLY, EDIT ASSEMBLY FILES INSTEAD */ - /* flashloaders/stm32f0.s -- compiled with thumb2 */ - static const uint8_t loader_code_stm32vl[] = { - 0x16, 0x4f, 0x3c, 0x68, - 0x16, 0x4f, 0x3e, 0x68, - 0x36, 0x19, 0x16, 0x4f, - 0x3d, 0x68, 0x2d, 0x19, - 0x4f, 0xf0, 0x01, 0x07, - 0x33, 0x68, 0x3b, 0x43, - 0x33, 0x60, 0x03, 0x88, - 0x0b, 0x80, 0x4f, 0xf0, - 0x02, 0x07, 0xc0, 0x19, - 0xc9, 0x19, 0x4f, 0xf0, - 0x01, 0x07, 0x2b, 0x68, - 0x3b, 0x42, 0xfa, 0xd0, - 0x4f, 0xf0, 0x04, 0x07, - 0x3b, 0x42, 0x04, 0xd1, - 0x4f, 0xf0, 0x01, 0x07, - 0xd2, 0x1b, 0x00, 0x2a, - 0xe6, 0xd1, 0x4f, 0xf0, - 0x01, 0x07, 0x33, 0x68, - 0xbb, 0x43, 0x33, 0x60, - 0x00, 0xbe, 0x00, 0xbf, - 0x00, 0x20, 0x02, 0x40, - 0x10, 0x00, 0x00, 0x00, - 0x0c, 0x00, 0x00, 0x00, - 0x50, 0x00, 0x00, 0x20, - 0x54, 0x00, 0x00, 0x20, - 0x58, 0x00, 0x00, 0x20 - }; - - /* flashloaders/stm32f0.s -- thumb1 only, same sequence as for STM32VL, bank ignored */ - static const uint8_t loader_code_stm32f0[] = { - 0xc0, 0x46, 0xc0, 0x46, - 0x13, 0x4f, 0x3c, 0x68, - 0x13, 0x4f, 0x3e, 0x68, - 0x36, 0x19, 0x13, 0x4f, - 0x3d, 0x68, 0x2d, 0x19, - 0x12, 0x4f, 0x33, 0x68, - 0x3b, 0x43, 0x33, 0x60, - 0x03, 0x88, 0x0b, 0x80, - 0x10, 0x4f, 0xc0, 0x19, - 0xc9, 0x19, 0x0e, 0x4f, - 0x2b, 0x68, 0x3b, 0x42, - 0xfb, 0xd0, 0x0e, 0x4f, - 0x3b, 0x42, 0x03, 0xd1, - 0x0a, 0x4f, 0xd2, 0x1b, - 0x00, 0x2a, 0xeb, 0xd1, - 0x08, 0x4f, 0x33, 0x68, - 0xbb, 0x43, 0x33, 0x60, - 0x00, 0xbe, 0xc0, 0x46, - 0x00, 0x20, 0x02, 0x40, - 0x10, 0x00, 0x00, 0x00, - 0x0c, 0x00, 0x00, 0x00, - 0x48, 0x00, 0x00, 0x20, - 0x4c, 0x00, 0x00, 0x20, - 0x50, 0x00, 0x00, 0x20, - 0x01, 0x00, 0x00, 0x00, - 0x02, 0x00, 0x00, 0x00, - 0x04, 0x00, 0x00, 0x00 - }; - - static const uint8_t loader_code_stm32l[] = { - // flashloaders/stm32lx.s - - 0x03, 0x68, 0x0b, 0x60, - 0x4f, 0xf0, 0x04, 0x07, - 0x38, 0x44, 0x39, 0x44, - 0x4f, 0xf0, 0x01, 0x07, - 0xd2, 0x1b, 0x00, 0x2a, - 0xf4, 0xd1, 0x00, 0xbe, - }; - - static const uint8_t loader_code_stm32f4[] = { - // flashloaders/stm32f4.s - - 0xdf, 0xf8, 0x28, 0xc0, - 0xdf, 0xf8, 0x28, 0xa0, - 0xe2, 0x44, 0x03, 0x68, - 0x0b, 0x60, 0x00, 0xf1, - 0x04, 0x00, 0x01, 0xf1, - 0x04, 0x01, 0xba, 0xf8, - 0x00, 0x30, 0x13, 0xf0, - 0x01, 0x0f, 0xfa, 0xd0, - 0xa2, 0xf1, 0x01, 0x02, - 0x00, 0x2a, 0xf0, 0xd1, - 0x00, 0xbe, 0x00, 0xbf, - 0x00, 0x3c, 0x02, 0x40, - 0x0e, 0x00, 0x00, 0x00 - }; - - static const uint8_t loader_code_stm32f4_lv[] = { - // flashloaders/stm32f4lv.s - 0xdf, 0xf8, 0x2c, 0xc0, - 0xdf, 0xf8, 0x2c, 0xa0, - 0xe2, 0x44, 0x4f, 0xea, - 0x82, 0x02, 0x03, 0x78, - 0x0b, 0x70, 0x00, 0xf1, - 0x01, 0x00, 0x01, 0xf1, - 0x01, 0x01, 0xba, 0xf8, - 0x00, 0x30, 0x13, 0xf0, - 0x01, 0x0f, 0xfa, 0xd0, - 0xa2, 0xf1, 0x01, 0x02, - 0x00, 0x2a, 0xf0, 0xd1, - 0x00, 0xbe, 0x00, 0xbf, - 0x00, 0x3c, 0x02, 0x40, - 0x0e, 0x00, 0x00, 0x00 - }; - - static const uint8_t loader_code_stm32l4[] = { - // flashloaders/stm32l4.s - 0xdf, 0xf8, 0x2c, 0xc0, - 0xdf, 0xf8, 0x2c, 0xa0, - 0xe2, 0x44, 0x03, 0x68, - 0x44, 0x68, 0x0b, 0x60, - 0x4c, 0x60, 0x00, 0xf1, - 0x08, 0x00, 0x01, 0xf1, - 0x08, 0x01, 0xba, 0xf8, - 0x00, 0x30, 0x13, 0xf0, - 0x01, 0x0f, 0xfa, 0xd0, - 0xa2, 0xf1, 0x01, 0x02, - 0x00, 0x2a, 0xee, 0xd1, - 0x00, 0xbe, 0x00, 0xbf, - 0x00, 0x20, 0x02, 0x40, - 0x12, 0x00, 0x00, 0x00 - }; - - static const uint8_t loader_code_stm32f7[] = { - // flashloaders/stm32f7.s - 0xdf, 0xf8, 0x2c, 0xc0, - 0xdf, 0xf8, 0x2c, 0xa0, - 0xe2, 0x44, 0x03, 0x68, - 0x0b, 0x60, 0x00, 0xf1, - 0x04, 0x00, 0x01, 0xf1, - 0x04, 0x01, 0xbf, 0xf3, - 0x4f, 0x8f, 0xba, 0xf8, - 0x00, 0x30, 0x13, 0xf0, - 0x01, 0x0f, 0xfa, 0xd0, - 0xa2, 0xf1, 0x01, 0x02, - 0x00, 0x2a, 0xee, 0xd1, - 0x00, 0xbe, 0x00, 0xbf, - 0x00, 0x3c, 0x02, 0x40, - 0x0e, 0x00, 0x00, 0x00 - }; - - static const uint8_t loader_code_stm32f7_lv[] = { - // flashloaders/stm32f7lv.s - 0xdf, 0xf8, 0x30, 0xc0, - 0xdf, 0xf8, 0x30, 0xa0, - 0xe2, 0x44, 0x4f, 0xea, - 0x82, 0x02, 0x03, 0x78, - 0x0b, 0x70, 0x00, 0xf1, - 0x01, 0x00, 0x01, 0xf1, - 0x01, 0x01, 0xbf, 0xf3, - 0x4f, 0x8f, 0xba, 0xf8, - 0x00, 0x30, 0x13, 0xf0, - 0x01, 0x0f, 0xfa, 0xd0, - 0xa2, 0xf1, 0x01, 0x02, - 0x00, 0x2a, 0xee, 0xd1, - 0x00, 0xbe, 0x00, 0xbf, - 0x00, 0x3c, 0x02, 0x40, - 0x0e, 0x00, 0x00, 0x00 - }; - - - -int stlink_flash_loader_init(stlink_t *sl, flash_loader_t *fl) -{ +/* flashloaders/stm32f0.s -- compiled with thumb2 */ +static const uint8_t loader_code_stm32vl[] = { + 0x16, 0x4f, 0x3c, 0x68, + 0x16, 0x4f, 0x3e, 0x68, + 0x36, 0x19, 0x16, 0x4f, + 0x3d, 0x68, 0x2d, 0x19, + 0x4f, 0xf0, 0x01, 0x07, + 0x33, 0x68, 0x3b, 0x43, + 0x33, 0x60, 0x03, 0x88, + 0x0b, 0x80, 0x4f, 0xf0, + 0x02, 0x07, 0xc0, 0x19, + 0xc9, 0x19, 0x4f, 0xf0, + 0x01, 0x07, 0x2b, 0x68, + 0x3b, 0x42, 0xfa, 0xd0, + 0x4f, 0xf0, 0x04, 0x07, + 0x3b, 0x42, 0x04, 0xd1, + 0x4f, 0xf0, 0x01, 0x07, + 0xd2, 0x1b, 0x00, 0x2a, + 0xe6, 0xd1, 0x4f, 0xf0, + 0x01, 0x07, 0x33, 0x68, + 0xbb, 0x43, 0x33, 0x60, + 0x00, 0xbe, 0x00, 0xbf, + 0x00, 0x20, 0x02, 0x40, + 0x10, 0x00, 0x00, 0x00, + 0x0c, 0x00, 0x00, 0x00, + 0x50, 0x00, 0x00, 0x20, + 0x54, 0x00, 0x00, 0x20, + 0x58, 0x00, 0x00, 0x20 +}; + +/* flashloaders/stm32f0.s -- thumb1 only, same sequence as for STM32VL, bank ignored */ +static const uint8_t loader_code_stm32f0[] = { + 0xc0, 0x46, 0xc0, 0x46, + 0x13, 0x4f, 0x3c, 0x68, + 0x13, 0x4f, 0x3e, 0x68, + 0x36, 0x19, 0x13, 0x4f, + 0x3d, 0x68, 0x2d, 0x19, + 0x12, 0x4f, 0x33, 0x68, + 0x3b, 0x43, 0x33, 0x60, + 0x03, 0x88, 0x0b, 0x80, + 0x10, 0x4f, 0xc0, 0x19, + 0xc9, 0x19, 0x0e, 0x4f, + 0x2b, 0x68, 0x3b, 0x42, + 0xfb, 0xd0, 0x0e, 0x4f, + 0x3b, 0x42, 0x03, 0xd1, + 0x0a, 0x4f, 0xd2, 0x1b, + 0x00, 0x2a, 0xeb, 0xd1, + 0x08, 0x4f, 0x33, 0x68, + 0xbb, 0x43, 0x33, 0x60, + 0x00, 0xbe, 0xc0, 0x46, + 0x00, 0x20, 0x02, 0x40, + 0x10, 0x00, 0x00, 0x00, + 0x0c, 0x00, 0x00, 0x00, + 0x48, 0x00, 0x00, 0x20, + 0x4c, 0x00, 0x00, 0x20, + 0x50, 0x00, 0x00, 0x20, + 0x01, 0x00, 0x00, 0x00, + 0x02, 0x00, 0x00, 0x00, + 0x04, 0x00, 0x00, 0x00 +}; + +static const uint8_t loader_code_stm32l[] = { + // flashloaders/stm32lx.s + + 0x03, 0x68, 0x0b, 0x60, + 0x4f, 0xf0, 0x04, 0x07, + 0x38, 0x44, 0x39, 0x44, + 0x4f, 0xf0, 0x01, 0x07, + 0xd2, 0x1b, 0x00, 0x2a, + 0xf4, 0xd1, 0x00, 0xbe, +}; + +static const uint8_t loader_code_stm32f4[] = { + // flashloaders/stm32f4.s + + 0xdf, 0xf8, 0x28, 0xc0, + 0xdf, 0xf8, 0x28, 0xa0, + 0xe2, 0x44, 0x03, 0x68, + 0x0b, 0x60, 0x00, 0xf1, + 0x04, 0x00, 0x01, 0xf1, + 0x04, 0x01, 0xba, 0xf8, + 0x00, 0x30, 0x13, 0xf0, + 0x01, 0x0f, 0xfa, 0xd0, + 0xa2, 0xf1, 0x01, 0x02, + 0x00, 0x2a, 0xf0, 0xd1, + 0x00, 0xbe, 0x00, 0xbf, + 0x00, 0x3c, 0x02, 0x40, + 0x0e, 0x00, 0x00, 0x00 +}; + +static const uint8_t loader_code_stm32f4_lv[] = { + // flashloaders/stm32f4lv.s + 0xdf, 0xf8, 0x2c, 0xc0, + 0xdf, 0xf8, 0x2c, 0xa0, + 0xe2, 0x44, 0x4f, 0xea, + 0x82, 0x02, 0x03, 0x78, + 0x0b, 0x70, 0x00, 0xf1, + 0x01, 0x00, 0x01, 0xf1, + 0x01, 0x01, 0xba, 0xf8, + 0x00, 0x30, 0x13, 0xf0, + 0x01, 0x0f, 0xfa, 0xd0, + 0xa2, 0xf1, 0x01, 0x02, + 0x00, 0x2a, 0xf0, 0xd1, + 0x00, 0xbe, 0x00, 0xbf, + 0x00, 0x3c, 0x02, 0x40, + 0x0e, 0x00, 0x00, 0x00 +}; + +static const uint8_t loader_code_stm32l4[] = { + // flashloaders/stm32l4.s + 0xdf, 0xf8, 0x2c, 0xc0, + 0xdf, 0xf8, 0x2c, 0xa0, + 0xe2, 0x44, 0x03, 0x68, + 0x44, 0x68, 0x0b, 0x60, + 0x4c, 0x60, 0x00, 0xf1, + 0x08, 0x00, 0x01, 0xf1, + 0x08, 0x01, 0xba, 0xf8, + 0x00, 0x30, 0x13, 0xf0, + 0x01, 0x0f, 0xfa, 0xd0, + 0xa2, 0xf1, 0x01, 0x02, + 0x00, 0x2a, 0xee, 0xd1, + 0x00, 0xbe, 0x00, 0xbf, + 0x00, 0x20, 0x02, 0x40, + 0x12, 0x00, 0x00, 0x00 +}; + +static const uint8_t loader_code_stm32f7[] = { + // flashloaders/stm32f7.s + 0xdf, 0xf8, 0x2c, 0xc0, + 0xdf, 0xf8, 0x2c, 0xa0, + 0xe2, 0x44, 0x03, 0x68, + 0x0b, 0x60, 0x00, 0xf1, + 0x04, 0x00, 0x01, 0xf1, + 0x04, 0x01, 0xbf, 0xf3, + 0x4f, 0x8f, 0xba, 0xf8, + 0x00, 0x30, 0x13, 0xf0, + 0x01, 0x0f, 0xfa, 0xd0, + 0xa2, 0xf1, 0x01, 0x02, + 0x00, 0x2a, 0xee, 0xd1, + 0x00, 0xbe, 0x00, 0xbf, + 0x00, 0x3c, 0x02, 0x40, + 0x0e, 0x00, 0x00, 0x00 +}; + +static const uint8_t loader_code_stm32f7_lv[] = { + // flashloaders/stm32f7lv.s + 0xdf, 0xf8, 0x30, 0xc0, + 0xdf, 0xf8, 0x30, 0xa0, + 0xe2, 0x44, 0x4f, 0xea, + 0x82, 0x02, 0x03, 0x78, + 0x0b, 0x70, 0x00, 0xf1, + 0x01, 0x00, 0x01, 0xf1, + 0x01, 0x01, 0xbf, 0xf3, + 0x4f, 0x8f, 0xba, 0xf8, + 0x00, 0x30, 0x13, 0xf0, + 0x01, 0x0f, 0xfa, 0xd0, + 0xa2, 0xf1, 0x01, 0x02, + 0x00, 0x2a, 0xee, 0xd1, + 0x00, 0xbe, 0x00, 0xbf, + 0x00, 0x3c, 0x02, 0x40, + 0x0e, 0x00, 0x00, 0x00 +}; + + +int stlink_flash_loader_init(stlink_t *sl, flash_loader_t *fl) { size_t size = 0; - /* allocate the loader in sram */ + // allocate the loader in SRAM if (stlink_flash_loader_write_to_sram(sl, &fl->loader_addr, &size) == -1) { WLOG("Failed to write flash loader to sram!\n"); - return -1; + return(-1); } - /* allocate a one page buffer in sram right after loader */ - fl->buf_addr = fl->loader_addr + (uint32_t) size; + // allocate a one page buffer in SRAM right after loader + fl->buf_addr = fl->loader_addr + (uint32_t)size; ILOG("Successfully loaded flash loader in sram\n"); - return 0; + return(0); } static int loader_v_dependent_assignment(stlink_t *sl, const uint8_t **loader_code, size_t *loader_size, const uint8_t *high_v_loader, size_t high_v_loader_size, - const uint8_t *low_v_loader, size_t low_v_loader_size) -{ + const uint8_t *low_v_loader, size_t low_v_loader_size) { int retval = 0; - if ( sl->version.stlink_v == 1){ + if ( sl->version.stlink_v == 1) { printf("STLINK V1 cannot read voltage, defaulting to 32-bit writes\n"); *loader_code = high_v_loader; *loader_size = high_v_loader_size; - } - else { + } else { int voltage = stlink_target_voltage(sl); + if (voltage == -1) { retval = -1; printf("Failed to read Target voltage\n"); - } - else { + } else { if (voltage > 2700) { *loader_code = high_v_loader; *loader_size = high_v_loader_size; @@ -219,11 +216,11 @@ static int loader_v_dependent_assignment(stlink_t *sl, } } } - return retval; + + return(retval); } -int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) -{ +int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) { const uint8_t* loader_code; size_t loader_size; @@ -235,7 +232,7 @@ int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* sl->chip_id == STLINK_CHIPID_STM32_L011 || sl->chip_id == STLINK_CHIPID_STM32_L0 || sl->chip_id == STLINK_CHIPID_STM32_L0_CAT5 || - sl->chip_id == STLINK_CHIPID_STM32_L0_CAT2) { /* stm32l */ + sl->chip_id == STLINK_CHIPID_STM32_L0_CAT2) { // STM32l loader_code = loader_code_stm32l; loader_size = sizeof(loader_code_stm32l); } else if (sl->core_id == STM32VL_CORE_ID || @@ -248,38 +245,34 @@ int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* loader_code = loader_code_stm32vl; loader_size = sizeof(loader_code_stm32vl); } else if (sl->chip_id == STLINK_CHIPID_STM32_F2 || - sl->chip_id == STLINK_CHIPID_STM32_F4 || - sl->chip_id == STLINK_CHIPID_STM32_F4_DE || - sl->chip_id == STLINK_CHIPID_STM32_F4_LP || - sl->chip_id == STLINK_CHIPID_STM32_F4_HD || - sl->chip_id == STLINK_CHIPID_STM32_F4_DSI || - sl->chip_id == STLINK_CHIPID_STM32_F410 || - sl->chip_id == STLINK_CHIPID_STM32_F411RE || - sl->chip_id == STLINK_CHIPID_STM32_F412 || - sl->chip_id == STLINK_CHIPID_STM32_F413 || - sl->chip_id == STLINK_CHIPID_STM32_F446 - ) { + sl->chip_id == STLINK_CHIPID_STM32_F4 || + sl->chip_id == STLINK_CHIPID_STM32_F4_DE || + sl->chip_id == STLINK_CHIPID_STM32_F4_LP || + sl->chip_id == STLINK_CHIPID_STM32_F4_HD || + sl->chip_id == STLINK_CHIPID_STM32_F4_DSI || + sl->chip_id == STLINK_CHIPID_STM32_F410 || + sl->chip_id == STLINK_CHIPID_STM32_F411RE || + sl->chip_id == STLINK_CHIPID_STM32_F412 || + sl->chip_id == STLINK_CHIPID_STM32_F413 || + sl->chip_id == STLINK_CHIPID_STM32_F446) { int retval; retval = loader_v_dependent_assignment(sl, &loader_code, &loader_size, loader_code_stm32f4, sizeof(loader_code_stm32f4), loader_code_stm32f4_lv, sizeof(loader_code_stm32f4_lv)); - if (retval == -1) { - return retval; - } + + if (retval == -1) { return(retval); } } else if (sl->core_id == STM32F7_CORE_ID || sl->chip_id == STLINK_CHIPID_STM32_F7 || sl->chip_id == STLINK_CHIPID_STM32_F7XXXX || - sl->chip_id == STLINK_CHIPID_STM32_F72XXX - ) { + sl->chip_id == STLINK_CHIPID_STM32_F72XXX) { int retval; retval = loader_v_dependent_assignment(sl, &loader_code, &loader_size, loader_code_stm32f7, sizeof(loader_code_stm32f7), loader_code_stm32f7_lv, sizeof(loader_code_stm32f7_lv)); - if (retval == -1) { - return retval; - } + + if (retval == -1) { return(retval); } } else if (sl->chip_id == STLINK_CHIPID_STM32_F0 || sl->chip_id == STLINK_CHIPID_STM32_F04 || sl->chip_id == STLINK_CHIPID_STM32_F0_CAN || @@ -292,101 +285,102 @@ int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* (sl->chip_id == STLINK_CHIPID_STM32_L43X) || (sl->chip_id == STLINK_CHIPID_STM32_L46X) || (sl->chip_id == STLINK_CHIPID_STM32_L4RX) || - (sl->chip_id == STLINK_CHIPID_STM32_L496X)) - { + (sl->chip_id == STLINK_CHIPID_STM32_L496X)) { loader_code = loader_code_stm32l4; loader_size = sizeof(loader_code_stm32l4); } else { - ELOG("unknown coreid, not sure what flash loader to use, aborting! coreid: %x, chipid: %x\n", sl->core_id, sl->chip_id); - return -1; + ELOG("unknown coreid, not sure what flash loader to use, aborting! coreid: %x, chipid: %x\n", + sl->core_id, sl->chip_id); + return(-1); } memcpy(sl->q_buf, loader_code, loader_size); int ret = stlink_write_mem32(sl, sl->sram_base, loader_size); - if (ret) - return ret; + + if (ret) { return(ret); } *addr = sl->sram_base; *size = loader_size; - /* success */ - return 0; + return(0); // success } -int stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, const uint8_t* buf, size_t size) -{ +int stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, const uint8_t* buf, size_t size) { struct stlink_reg rr; int i = 0; size_t count = 0; uint32_t flash_base = 0; DLOG("Running flash loader, write address:%#x, size: %u\n", target, (unsigned int)size); - // FIXME This can never return -1 + + // TODO: This can never return -1 if (write_buffer_to_sram(sl, fl, buf, size) == -1) { // IMPOSSIBLE! ELOG("write_buffer_to_sram() == -1\n"); - return -1; + return(-1); } if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || (sl->flash_type == STLINK_FLASH_TYPE_F1_XL)) { count = size / sizeof(uint16_t); - if (size % sizeof(uint16_t)) - ++count; + + if (size % sizeof(uint16_t)) { ++count; } } else if (sl->flash_type == STLINK_FLASH_TYPE_F4 || sl->flash_type == STLINK_FLASH_TYPE_L0) { count = size / sizeof(uint32_t); - if (size % sizeof(uint32_t)) - ++count; + + if (size % sizeof(uint32_t)) { ++count; } } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { count = size / sizeof(uint64_t); - if (size % sizeof(uint64_t)) - ++count; + + if (size % sizeof(uint64_t)) { ++count; } } if ((sl->flash_type == STLINK_FLASH_TYPE_F1_XL) && (target >= FLASH_BANK2_START_ADDR)) { flash_base = FLASH_REGS_BANK2_OFS; } - /* setup core */ - stlink_write_reg(sl, fl->buf_addr, 0); /* source */ - stlink_write_reg(sl, target, 1); /* target */ - stlink_write_reg(sl, (uint32_t) count, 2); /* count */ - stlink_write_reg(sl, flash_base, 3); /* flash register base, only used on VL/F1_XL, but harmless for others */ - stlink_write_reg(sl, fl->loader_addr, 15); /* pc register */ + /* Setup core */ + stlink_write_reg(sl, fl->buf_addr, 0); // source + stlink_write_reg(sl, target, 1); // target + stlink_write_reg(sl, (uint32_t)count, 2); // count + stlink_write_reg(sl, flash_base, 3); // flash register base + // only used on VL/F1_XL, but harmless for others + stlink_write_reg(sl, fl->loader_addr, 15); // pc register - /* run loader */ + /* Run loader */ stlink_run(sl); -// This piece of code used to try to spin for .1 second by waiting -// doing 10000 rounds of 10 microseconds. But because this usually runs -// on Unix-like OSes, the 10 microseconds get rounded up to the "tick" -// (actually almost two ticks) of the system. 1 milisecond. Thus, the -// ten thousand attempts, when "something goes wrong" that requires -// the error message "flash loader run error" would wait for something -// like 20 seconds before coming up with the error. -// by increasing the sleep-per-round to the same order-of-magnitude as -// the tick-rounding that the OS uses, the wait until the error message is -// reduced to the same order of magnitude as what was intended. -- REW. -#define WAIT_ROUNDS 100 - /* wait until done (reaches breakpoint) */ +/* This piece of code used to try to spin for .1 second by waiting doing 10000 rounds of 10 µs. + * But because this usually runs on Unix-like OSes, the 10 µs get rounded up to the "tick" + * (actually almost two ticks) of the system. 1 ms. Thus, the ten thousand attempts, when + * "something goes wrong" that requires the error message "flash loader run error" would wait + * for something like 20 seconds before coming up with the error. + * By increasing the sleep-per-round to the same order-of-magnitude as the tick-rounding that + * the OS uses, the wait until the error message is reduced to the same order of magnitude + * as what was intended. -- REW. + */ +#define WAIT_ROUNDS 30 + + // wait until done (reaches breakpoint) for (i = 0; i < WAIT_ROUNDS; i++) { - usleep(1000); - if (stlink_is_core_halted(sl)) - break; + usleep(10000); + + if (stlink_is_core_halted(sl)) { break; } } if (i >= WAIT_ROUNDS) { ELOG("flash loader run error\n"); - return -1; + return(-1); } - /* check written byte count */ + // check written byte count stlink_read_reg(sl, 2, &rr); + if (rr.r[2] != 0) { ELOG("write error, count == %u\n", rr.r[2]); - return -1; + return(-1); } - return 0; + return(0); } From a5b98f58756b6a1414ca8175c578e07998a59061 Mon Sep 17 00:00:00 2001 From: Rutger Hendriks Date: Thu, 25 Jun 2020 15:00:53 +0200 Subject: [PATCH 058/503] Fix compiler warning implicit cast --- src/common.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/common.c b/src/common.c index 58e67d447..86d2ca8ea 100644 --- a/src/common.c +++ b/src/common.c @@ -3421,7 +3421,7 @@ int stlink_read_option_bytes_f7(stlink_t *sl, uint32_t* option_byte) { } } - return stlink_read_debug32(sl, sl->option_base + (sl->option_size / 4 - 1) * sizeof(uint32_t), option_byte); + return stlink_read_debug32(sl, sl->option_base + (uint32_t) (sl->option_size / 4 - 1) * sizeof(uint32_t), option_byte); } /** From fc56f2412d80f09843b8f37a670ffc516640faaa Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sat, 27 Jun 2020 02:28:00 +0200 Subject: [PATCH 059/503] General Project Update - Updated CHANGELOG.md - cpack: corrections for pkg config --- CHANGELOG.md | 3 ++- cmake/packaging/deb/changelog | 50 +++-------------------------------- cmake/packaging/deb/control | 4 +-- cmake/packaging/deb/copyright | 5 ++-- cmake/packaging/deb/rules | 3 +-- cmake/packaging/rpm/changelog | 4 +-- doc/version_support.md | 2 +- 7 files changed, 13 insertions(+), 58 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index 3195bae3c..7717ca6f4 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -19,7 +19,7 @@ Features: * Support for STM32L1, SM32L4 option bytes write ([#596](https://github.com/stlink-org/stlink/pull/596), [#844](https://github.com/stlink-org/stlink/pull/844), [#847](https://github.com/stlink-org/stlink/pull/847)) * Added CMAKEFLAGS and install target ([#804](https://github.com/stlink-org/stlink/pull/804), [#935](https://github.com/stlink-org/stlink/pull/935)) * Support for STM32G4 ([#822](https://github.com/stlink-org/stlink/pull/822)) -* Add aliased SRAM2 region in the L496 memory map ([#824](https://github.com/stlink-org/stlink/pull/824)) +* Added aliased SRAM2 region in the L496 memory map ([#824](https://github.com/stlink-org/stlink/pull/824)) * Improved support for STM32G0 ([#825](https://github.com/stlink-org/stlink/pull/825), [#850](https://github.com/stlink-org/stlink/pull/850), [#856](https://github.com/stlink-org/stlink/pull/856), [#857](https://github.com/stlink-org/stlink/pull/857)) * Added postinst script with 'depmod -a' for 'make package' ([#845](https://github.com/stlink-org/stlink/pull/845), [#931](https://github.com/stlink-org/stlink/pull/931)) * Calculate checksums for flash operations ([#862](https://github.com/stlink-org/stlink/pull/862), [#924](https://github.com/stlink-org/stlink/pull/924)) @@ -358,6 +358,7 @@ Chip support added for: * STM32F469/STM32F479 ([#345](https://github.com/stlink-org/stlink/pull/345), [#555](https://github.com/stlink-org/stlink/pull/555)) (Release v1.2.0) * STM32L1xx Cat.2 devices (Nicolas Schodet) * STM32L1xx (chip-ID 0x427) ([#152](https://github.com/stlink-org/stlink/pull/152), [#163](https://github.com/stlink-org/stlink/pull/163), [#165](https://github.com/stlink-org/stlink/pull/165)) (Release v1.0.0) +* Added SIGINT handler for stlink cleanup ([#31](https://github.com/stlink-org/stlink/pull/31), [#135](https://github.com/stlink-org/stlink/pull/135)) (Release v1.0.0) Board support added for: diff --git a/cmake/packaging/deb/changelog b/cmake/packaging/deb/changelog index f4b644176..ec65e6744 100644 --- a/cmake/packaging/deb/changelog +++ b/cmake/packaging/deb/changelog @@ -1,49 +1,5 @@ -stlink (1.6.0+ds-1) unstable; urgency=medium +stlink (1.6.1+ds-1) unstable; urgency=medium - * Merge tag 'v1.6.0' into debian - * Bump Standards-Version to 4.5.0, no changes. - * Update libstlink1 symbols file for 1.6.0. + * Initial cpack-based package release for Debian/Ubuntu - -- Luca Boccassi Tue, 25 Feb 2020 22:08:33 +0000 - -stlink (1.5.1+ds-2) unstable; urgency=medium - - * Mark library packages as Multi-Arch: same. - * Apply cross.patch to fix cross-compiling the GUI. Thanks Helmut for the patch! (Closes: #941320) - * Vcs-Git: add -b debian - * Set Rules-Requires-Root: no - * Bump Standards-Version to 4.4.0 - - -- Luca Boccassi Sun, 29 Sep 2019 12:50:58 +0100 - -stlink (1.5.1+ds-1) unstable; urgency=medium - - * Merge tag 'v1.5.1' into debian. See upstream changelog for info: - https://github.com/stlink-org/stlink/releases/tag/v1.5.1 - * Mark packages as linux-any, other systems not supported. - - -- Luca Boccassi Fri, 28 Sep 2018 10:26:39 +0100 - -stlink (1.5.0+ds-1) unstable; urgency=medium - - * Upload to unstable. (Closes: #869421) - - -- Luca Boccassi Fri, 16 Mar 2018 16:56:17 +0000 - -stlink (1.4.0) unstable; urgency=low - - -- Andrew 'Necromant' Andrianov Sat, 01 Jul 2017 00:00:00 +0000 - -stlink (1.3.1) unstable; urgency=low - - -- Andrew 'Necromant' Andrianov Sat, 25 Feb 2017 00:00:00 +0000 - -stlink (1.3.0) unstable; urgency=low - - -- Andrew 'Necromant' Andrianov Sat, 28 Jan 2017 00:00:00 +0000 - -stlink (1.2.1) unstable; urgency=low - - * Initial Debian-Packaged Release. - - -- Andrew 'Necromant' Andrianov Sat, 09 Jul 2016 23:16:07 +0300 + -- Nightwalker-87 Sat, 06 Jun 2020 00:00:00 +0100 diff --git a/cmake/packaging/deb/control b/cmake/packaging/deb/control index d96746e65..9f17b0042 100644 --- a/cmake/packaging/deb/control +++ b/cmake/packaging/deb/control @@ -1,7 +1,7 @@ Source: stlink -Maintainer: Luca Bocassi +Maintainer: stlink-org Build-Depends: cmake, dh-cmake, debhelper (>= 9), libusb-1.0-0-dev, libgtk-3-dev -Standards-Version: 4.1.3 +Standards-Version: 4.5.0 Section: electronics Priority: optional Homepage: https://github.com/stlink-org/stlink diff --git a/cmake/packaging/deb/copyright b/cmake/packaging/deb/copyright index a14d4eb6e..fb1c49d74 100644 --- a/cmake/packaging/deb/copyright +++ b/cmake/packaging/deb/copyright @@ -1,9 +1,8 @@ Format: https://www.debian.org/doc/packaging-manuals/copyright-format/1.0/ Upstream-Name: stlink -Upstream-Contact: Luca Bocassi +Upstream-Contact: stlink-org Source: https://github.com/stlink-org/stlink -Disclaimer: -Comment: + Files: * Copyright: 2011-2020 stlink-org Martin Capitanio [capnm] diff --git a/cmake/packaging/deb/rules b/cmake/packaging/deb/rules index 2f80faeac..ae3abcabe 100755 --- a/cmake/packaging/deb/rules +++ b/cmake/packaging/deb/rules @@ -1,7 +1,7 @@ #!/usr/bin/make -f # See debhelper(7) (uncomment to enable) # output every command that modifies files on the build system. -DH_VERBOSE = 1 +#DH_VERBOSE = 1 # see EXAMPLES in dpkg-buildflags(1) and read /usr/share/dpkg/* DPKG_EXPORT_BUILDFLAGS = 1 @@ -15,5 +15,4 @@ export DEB_BUILD_MAINT_OPTIONS = hardening=+all override_dh_auto_configure: dh_auto_configure -- \ - -DLIB_INSTALL_DIR=/usr/lib/$(DEB_HOST_MULTIARCH) \ -DSTLINK_UDEV_RULES_DIR='/lib/udev/rules.d' diff --git a/cmake/packaging/rpm/changelog b/cmake/packaging/rpm/changelog index de2400d65..564bd95ae 100644 --- a/cmake/packaging/rpm/changelog +++ b/cmake/packaging/rpm/changelog @@ -1,2 +1,2 @@ -* Mon Jun 01 2020 Vasiliy Glazov - 1.6.1 -- Initial RPM-packaged release +* Mon Jun 01 2020 Nightwalker-87 - 1.6.1 +- Initial cpack-based RPM package release diff --git a/doc/version_support.md b/doc/version_support.md index 4d1f724f7..4076fb422 100644 --- a/doc/version_support.md +++ b/doc/version_support.md @@ -68,7 +68,7 @@ NOTE: In order to use a STLINK/v1 programmer on macOS, versions 10.13, 10.14 or ## Unsupported Operating Systems (as of Release v1.6.1) -| Operating System | libusb
version | cmake
version | End of OS-Support | Notes | +| Operating System | libusb
version | cmake
version | End of
OS-Support | Notes | | --- | --- | --- | --- | --- | | CentOS 7 | 1.0.21 | **2.8.12.2** | | named `libusbx`, but
`libusb`-codebase is used | | Debian 8 (Jessie) | 1.0.**19** | 3.**0.2** | Jun 2020 | From 31b1fa16201521e2aaf464576f2f169981abede0 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 28 Jun 2020 21:01:59 +0200 Subject: [PATCH 060/503] Fixed install paths (headers & stlink-gui.ui) --- CMakeLists.txt | 4 ++-- src/stlink-gui/CMakeLists.txt | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index 5171628ad..fae458dd7 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -86,7 +86,7 @@ include_directories(src/st-flash) include_directories(src/stlink-lib) ## Set installation directory for header files -set(STLINK_INCLUDE_PATH ${CMAKE_INSTALL_INCLUDEDIR} CACHE PATH "Main include install directory") +set(STLINK_INCLUDE_PATH ${CMAKE_INSTALL_INCLUDEDIR}/${PROJECT_NAME} CACHE PATH "Main include install directory") ## Subordinate CMakeLists for version config & header installation add_subdirectory(inc) @@ -147,7 +147,7 @@ endif () set(STLINK_LIBRARY_PATH ${CMAKE_INSTALL_LIBDIR} CACHE PATH "Main library install directory") # Set the environment variable LD_LIBRARY_PATH to point to /usr/local/lib (per default). -execute_process (COMMAND bash -c "export LD_LIBRARY_PATH=${CMAKE_INSTALL_LIBDIR}") +execute_process(COMMAND bash -c "export LD_LIBRARY_PATH=${CMAKE_INSTALL_LIBDIR}") ### diff --git a/src/stlink-gui/CMakeLists.txt b/src/stlink-gui/CMakeLists.txt index 89e5403d8..258f83cc1 100644 --- a/src/stlink-gui/CMakeLists.txt +++ b/src/stlink-gui/CMakeLists.txt @@ -33,9 +33,9 @@ if (NOT WIN32 AND NOT CMAKE_CROSSCOMPILING) ## stlink-gui add_executable(stlink-gui ${GUI_SOURCES}) - install(FILES stlink-gui.ui DESTINATION ${CMAKE_INSTALL_BINDIR}) + install(FILES stlink-gui.ui DESTINATION ${CMAKE_INSTALL_DATAROOTDIR}/${PROJECT_NAME}) set_target_properties(stlink-gui PROPERTIES - COMPILE_DEFINITIONS STLINK_UI_DIR="${CMAKE_INSTALL_PREFIX}/bin") + COMPILE_DEFINITIONS STLINK_UI_DIR="${CMAKE_INSTALL_DATAROOTDIR}/${PROJECT_NAME}") target_link_libraries(stlink-gui ${STLINK_LIB_SHARED} ${SSP_LIB} ${GTK3_LDFLAGS}) install(TARGETS stlink-gui DESTINATION ${CMAKE_INSTALL_BINDIR}) endif () From 66c6696337c2e6e3db5036422e0cd10726b428ab Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 28 Jun 2020 22:48:30 +0200 Subject: [PATCH 061/503] Corrected settings for deb pkg distribution --- cmake/packaging/deb/changelog | 50 +--------- cmake/packaging/deb/control | 7 +- cmake/packaging/deb/copyright | 8 +- cmake/packaging/deb/rules | 3 +- debian/changelog | 122 +---------------------- debian/control | 22 ++--- debian/copyright | 178 ++++++---------------------------- debian/libstlink-dev.install | 1 - debian/stlink-gui.install | 6 +- debian/stlink.pc.in | 2 +- 10 files changed, 58 insertions(+), 341 deletions(-) diff --git a/cmake/packaging/deb/changelog b/cmake/packaging/deb/changelog index f4b644176..196da940e 100644 --- a/cmake/packaging/deb/changelog +++ b/cmake/packaging/deb/changelog @@ -1,49 +1,5 @@ -stlink (1.6.0+ds-1) unstable; urgency=medium +stlink (1.6.1) unstable; urgency=medium - * Merge tag 'v1.6.0' into debian - * Bump Standards-Version to 4.5.0, no changes. - * Update libstlink1 symbols file for 1.6.0. + * Initial Debian-packaged Release. - -- Luca Boccassi Tue, 25 Feb 2020 22:08:33 +0000 - -stlink (1.5.1+ds-2) unstable; urgency=medium - - * Mark library packages as Multi-Arch: same. - * Apply cross.patch to fix cross-compiling the GUI. Thanks Helmut for the patch! (Closes: #941320) - * Vcs-Git: add -b debian - * Set Rules-Requires-Root: no - * Bump Standards-Version to 4.4.0 - - -- Luca Boccassi Sun, 29 Sep 2019 12:50:58 +0100 - -stlink (1.5.1+ds-1) unstable; urgency=medium - - * Merge tag 'v1.5.1' into debian. See upstream changelog for info: - https://github.com/stlink-org/stlink/releases/tag/v1.5.1 - * Mark packages as linux-any, other systems not supported. - - -- Luca Boccassi Fri, 28 Sep 2018 10:26:39 +0100 - -stlink (1.5.0+ds-1) unstable; urgency=medium - - * Upload to unstable. (Closes: #869421) - - -- Luca Boccassi Fri, 16 Mar 2018 16:56:17 +0000 - -stlink (1.4.0) unstable; urgency=low - - -- Andrew 'Necromant' Andrianov Sat, 01 Jul 2017 00:00:00 +0000 - -stlink (1.3.1) unstable; urgency=low - - -- Andrew 'Necromant' Andrianov Sat, 25 Feb 2017 00:00:00 +0000 - -stlink (1.3.0) unstable; urgency=low - - -- Andrew 'Necromant' Andrianov Sat, 28 Jan 2017 00:00:00 +0000 - -stlink (1.2.1) unstable; urgency=low - - * Initial Debian-Packaged Release. - - -- Andrew 'Necromant' Andrianov Sat, 09 Jul 2016 23:16:07 +0300 + -- Nightwalker-87 Mon, 01 Jun 2020 00:00:00 +0100 diff --git a/cmake/packaging/deb/control b/cmake/packaging/deb/control index d96746e65..759668ba6 100644 --- a/cmake/packaging/deb/control +++ b/cmake/packaging/deb/control @@ -1,9 +1,10 @@ Source: stlink -Maintainer: Luca Bocassi +Priority: optional +Maintainer: stlink-org Build-Depends: cmake, dh-cmake, debhelper (>= 9), libusb-1.0-0-dev, libgtk-3-dev -Standards-Version: 4.1.3 +Standards-Version: 4.5.0 +Rules-Requires-Root: no Section: electronics -Priority: optional Homepage: https://github.com/stlink-org/stlink Vcs-Git: https://github.com/stlink-org/stlink.git Vcs-Browser: https://github.com/stlink-org/stlink diff --git a/cmake/packaging/deb/copyright b/cmake/packaging/deb/copyright index a14d4eb6e..f5dfdc51b 100644 --- a/cmake/packaging/deb/copyright +++ b/cmake/packaging/deb/copyright @@ -1,9 +1,9 @@ Format: https://www.debian.org/doc/packaging-manuals/copyright-format/1.0/ Upstream-Name: stlink -Upstream-Contact: Luca Bocassi +Upstream-Contact: Nightwalker-87 Source: https://github.com/stlink-org/stlink -Disclaimer: -Comment: +Files-Excluded: stlinkv1_macos_driver + Files: * Copyright: 2011-2020 stlink-org Martin Capitanio [capnm] @@ -11,7 +11,7 @@ Copyright: 2011-2020 stlink-org Jerry Jacobs [xor-gate] [Nightwalker-87] and many others... - A list of contributors can be found in "contributors.txt". + An extended list of contributors can be found in "contributors.txt". License: BSD-3-clause Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: diff --git a/cmake/packaging/deb/rules b/cmake/packaging/deb/rules index 2f80faeac..ae3abcabe 100755 --- a/cmake/packaging/deb/rules +++ b/cmake/packaging/deb/rules @@ -1,7 +1,7 @@ #!/usr/bin/make -f # See debhelper(7) (uncomment to enable) # output every command that modifies files on the build system. -DH_VERBOSE = 1 +#DH_VERBOSE = 1 # see EXAMPLES in dpkg-buildflags(1) and read /usr/share/dpkg/* DPKG_EXPORT_BUILDFLAGS = 1 @@ -15,5 +15,4 @@ export DEB_BUILD_MAINT_OPTIONS = hardening=+all override_dh_auto_configure: dh_auto_configure -- \ - -DLIB_INSTALL_DIR=/usr/lib/$(DEB_HOST_MULTIARCH) \ -DSTLINK_UDEV_RULES_DIR='/lib/udev/rules.d' diff --git a/debian/changelog b/debian/changelog index f1265ee32..c54850340 100644 --- a/debian/changelog +++ b/debian/changelog @@ -44,7 +44,7 @@ stlink (1.5.1+ds-2) unstable; urgency=medium stlink (1.5.1+ds-1) unstable; urgency=medium * Merge tag 'v1.5.1' into debian. See upstream changelog for info: - https://github.com/texane/stlink/releases/tag/v1.5.1 + https://github.com/stlink-org/stlink/releases/tag/v1.5.1 * Mark packages as linux-any, other systems not supported. -- Luca Boccassi Fri, 28 Sep 2018 10:26:39 +0100 @@ -55,131 +55,19 @@ stlink (1.5.0+ds-1) unstable; urgency=medium -- Luca Boccassi Fri, 16 Mar 2018 16:56:17 +0000 -stlink (1.5.0) unstable; urgency=medium - - [ Jerry Jacobs ] - * README.md: Update version badge to v1.4.0 - - [ Viallard Anthony ] - * Add support of STM32L496xx/4A6xx devices (#615) - - [ rdlim ] - * Fix verification of flash error for STM32L496x device (#617) (#618) - - [ dflogeras ] - * Add note about availability in Gentoo package manager (#622) - - [ yaofei zheng ] - * update debian package version (#630) - - [ Lyle Cheatham ] - * Minor formatting fix in FAQ section of README.md (#631) - - [ Vasiliy Glazov ] - * README.md: Added information about Fedora and RedHat/CentOS packages. - (#635) - * Added LIB_INSTALL_DIR to correct libs install on 64-bit systems (#636) - - [ Gwenhael Goavec-Merou ] - * fix write for microcontroler with RAM size less or equal to 32K (#637) - - [ Mateusz Krawiec ] - * Fix memory map for stm32l496xx boards. (#639) - - [ Rüdiger Fortanier ] - * Add unknown chip output (#641) - - [ Slyshyk Oleksiy ] - * fix __FILE__ base name extraction, #628 (#648) - - [ texane ] - * STM32F72xx73xx support, from bob.feretich@rafresearch.com - - [ Kirill Kolyshkin ] - * debian/triggers: add (to run ldconfig) (#664) - - [ Slyshyk Oleksiy ] - * Try to fix #666 issue (#667) - * Try to fix 666 issue (#668) - - [ Jerry Jacobs ] - * Update ChangeLog.md - * Update README.md - - [ texane ] - * STM32F042K6 Nucleo-32 Board reported to work, by frank@bauernoeppel.de - - [ Anatol Pomozov ] - * Update .version file to match release number (#670) - - -- Anatol Pomozov Mon, 19 Feb 2018 11:00:29 -0800 - -libstlink (1.4.0) unstable; urgency=low - - * Major changes and added features - - Add support for STM32L452 target (#608) - - Initial support to compile with Microsoft Visual Studio 2017 (#602) - - Added support for flashing second bank on STM32F10x_XL (#592) - - Add support for STM32L011 target (#572) - - Allow building of debian package with CPack (@xor-gate) - * Updates and fixes - - Fix compilation with GCC 7 (#590) - - Skip GTK detection if we're cross-compiling (#588) - - Fix possible memory leak (#570) - - Fix building with mingw64 (#569, #610) - - Update libusb to 1.0.21 for Windows (#562) - - Fixing low-voltage flashing on STM32F7 parts. (#567) - - Update libusb to 1.0.21 for Windows (#562) +stlink (1.4.0) unstable; urgency=low -- Andrew 'Necromant' Andrianov Sat, 01 Jul 2017 00:00:00 +0000 -libstlink (1.3.1) unstable; urgency=low - - * Major changes and added features: - - Add preliminary support for STM32L011 to see it after probe (chipid 0x457) (@xor-gate) - - Strip full paths to source files in log (commit #2c0ab7f) - - Add support for STM32F413 target (#549) - - Add support for Semihosting SYS_READC (#546) - * Updates and fixes: - - Update documentation markdown files - - Compilation fixes (#552) - - Fix compilation when path includes spaces (#561) +stlink (1.3.1) unstable; urgency=low -- Andrew 'Necromant' Andrianov Sat, 25 Feb 2017 00:00:00 +0000 -libstlink (1.3.0) unstable; urgency=low - - * Major changes and added features: - - Deprecation of autotools (autoconf, automake) (@xor-gate) - - Removal of undocumented st-term utility, which is now replaced by st-util ARM semihosting feature (#3fd0f09) - - Add support for native debian packaging (#444, #485) - - Add intel hex file reading for st-flash (#459) - - Add --reset command to st-flash (#505) - - Support serial numbers argument for st-util and st-flash for multi-programmer setups (#541) - - Add kill ('k') command to gdb-server for st-util (#9804416) - - Add manpages (generated with pandoc from Markdown) (#464) - - Rewrite commandline parsing for st-flash (#459) - - Add support for ARM semihosting to st-util (#454, #455) - * Chip support added for: - - STM32L432 (#501) - - STM32F412 (#538) - - STM32F410 (#9c635e4) - - Add memory map for STM32F401XE (#460) - - L0x Category 5 devices (#406) - - Add L0 Category 2 device (chip id: 0x425) (#72b8e5e) - * Updates and fixes: - - Fixed STM32F030 erase error (#442) - - Fixed Cygwin build (#68b0f3b) - - Reset flash mass erase (MER) bit after mass erase for safety (#489) - - Fix memory map for STM32F4 (@zulusw) - - Fix STM32L-problem with flash loader (issue #390) (Tom de Boer) - - st-util don't read target voltage on startup as it crashes STM32F100 (probably stlink/v1) (Greg Alexander) - - Do a JTAG reset prior to reading CPU information when processor is in deep sleep (@andyg24) - - Redesign of st-flash commandline options parsing (pull-request #459) (@dev26th) +stlink (1.3.0) unstable; urgency=low -- Andrew 'Necromant' Andrianov Sat, 28 Jan 2017 00:00:00 +0000 -libstlink (1.2.1) unstable; urgency=low +stlink (1.2.1) unstable; urgency=low * Initial Debian-Packaged Release. diff --git a/debian/control b/debian/control index 3ac6af91f..598e0e89f 100644 --- a/debian/control +++ b/debian/control @@ -14,9 +14,7 @@ Section: libdevel Architecture: linux-any Multi-Arch: same Depends: libstlink1 (= ${binary:Version}), ${misc:Depends} -Description: OpenSource ST-Link tools replacement. - Flashing tools for STMicroelectronics STM32VL and STM32L. The transport layers - STLINKv1 and STLINKv2 are supported. +Description: Open source STM32 MCU programming toolset. . This package contains the development files for stlink. @@ -25,28 +23,22 @@ Section: libs Architecture: linux-any Multi-Arch: same Depends: ${shlibs:Depends}, ${misc:Depends} -Description: OpenSource ST-Link tools replacement. - Flashing tools for STMicroelectronics STM32VL and STM32L. The transport layers - STLINKv1 and STLINKv2 are supported. +Description: Open source STM32 MCU programming toolset. . This package contains the shared library for stlink. Package: stlink-tools Architecture: linux-any Depends: libstlink1 (= ${binary:Version}), ${shlibs:Depends}, ${misc:Depends} -Description: OpenSource ST-Link tools replacement. - Flashing tools for STMicroelectronics STM32VL and STM32L. The transport layers - STLINKv1 and STLINKv2 are supported. +Description: Open source STM32 MCU programming toolset. . - This package contains commandline utilities for stlink, and modprobe and - udev rules. + This package contains commandline utilities for stlink, modprobe- and + udev-rules. Package: stlink-gui Architecture: linux-any Depends: libstlink1 (= ${binary:Version}), stlink-tools (= ${binary:Version}), ${shlibs:Depends}, ${misc:Depends} -Description: OpenSource ST-Link tools replacement. - Flashing tools for STMicroelectronics STM32VL and STM32L. The transport layers - STLINKv1 and STLINKv2 are supported. +Description: Open source STM32 MCU programming toolset. . - This package contains a GUI tool for stlink. + This package contains a GUI for stlink. diff --git a/debian/copyright b/debian/copyright index 1a0febd9c..8329cc250 100644 --- a/debian/copyright +++ b/debian/copyright @@ -1,155 +1,37 @@ Format: https://www.debian.org/doc/packaging-manuals/copyright-format/1.0/ Upstream-Name: stlink -Upstream-Contact: Andrew 'Necromant' Andrianov +Upstream-Contact: Luca Boccassi Source: https://github.com/stlink-org/stlink -Comment: Upstream tarball has been repackaged to remove binary OSX kernel - drivers that are of unknown license and of no use to Debian. Files-Excluded: stlinkv1_macos_driver Files: * -Copyright: 2011-2018 agpanarin - 2011-2018 Alexey Cherevatenko - 2011-2018 Anatoli - 2011-2018 Andrea Mucignat - 2011-2018 Andrew 'Necromant' Andrianov - 2011-2018 Andrey Yurovsky - 2011-2018 Andy Isaacson - 2011-2018 Áron RADICS - 2011-2018 A Sheaff - 2011-2018 Björn Hauffe - 2011-2018 bob - 2011-2018 Breton M. Saunders - 2011-2018 Bruno Dal Bo - 2011-2018 Burns - 2011-2018 Chris Dew - 2011-2018 Chris Hiszpanski - 2011-2018 Chris Li - 2011-2018 Chris Samuelson - 2011-2018 Christophe Levantis - 2011-2018 Craig Lilley - 2011-2018 dandev37 - 2011-2018 Dan Hepler - 2011-2018 Daniel Campoverde [alx741] - 2011-2018 Daniel O'Connor - 2011-2018 Dave Flogeras - 2011-2018 Dave Murphy - 2011-2018 Dave Vandervies - 2011-2018 Denis Fokin - 2011-2018 Denis Osterland - 2011-2018 Dmitry Bravikov - 2011-2018 Efe Can İçöz - 2011-2018 Ethan Zonca - 2011-2018 Fabien Chouteau - 2011-2018 Fabien Le Mentec - 2011-2018 fhars - 2011-2018 Friedrich Beckmann - 2011-2018 Geoffrey Brown - 2011-2018 George Talusan - 2011-2018 Georg von Zengen - 2011-2018 giuseppe barba - 2011-2018 Greg Alexander - 2011-2018 Greg Meiste - 2011-2018 Hakkavélin - 2011-2018 htk - 2011-2018 Ian Griffiths <6thimage@gmail.com> - 2011-2018 Jack Peel - 2011-2018 Jakub Tyszkowski - 2011-2018 Jan Sarenik - 2011-2018 Jean-Luc Béchennec - 2011-2018 Jean-Marie Lemetayer - 2011-2018 Jeff Kent - 2011-2018 Jeffrey Nelson - 2011-2018 Jens Hoffmann - 2011-2018 Jerome Lambourg - 2011-2018 Jerry Jacobs - 2011-2018 Jim Paris - 2011-2018 Jiří Netolický - 2011-2018 jnosky - 2011-2018 jnosky - 2011-2018 JohannesTaelman - 2011-2018 Jonas Danielsson - 2011-2018 Jonas Norling - 2011-2018 Josh Bialkowski - 2011-2018 Karl Palsson - 2011-2018 kevin - 2011-2018 Kyle Manna - 2011-2018 Lari Lehtomäki - 2011-2018 le mentec fabien - 2011-2018 Martin Nowak - 2011-2018 Matteo Collina - 2011-2018 Max Chen - 2011-2018 Maxime Coquelin - 2011-2018 Maxime Vincent - 2011-2018 Michael Pratt - 2011-2018 Michael Sparmann - 2011-2018 Mike Szczys - 2011-2018 mlundinse - 2011-2018 mux - 2011-2018 Ned Konz - 2011-2018 Nic McDonald - 2011-2018 Nicolas Schodet - 2011-2018 Nikolay - 2011-2018 nullsub - 2011-2018 Olivier Croquette - 2011-2018 Olivier Gay - 2011-2018 Onno Kortmann - 2011-2018 orangeudav - 2011-2018 Pavel Kirienko - 2011-2018 Pekka Nikander - 2011-2018 Pete - 2011-2018 Peter Zotov - 2011-2018 Petteri Aimonen - 2011-2018 Piotr Haber - 2011-2018 Rene Hopf - 2011-2018 Robin Kreis - 2011-2018 Rob Spanton - 2011-2018 Rytis Karpuska - 2011-2018 Sean Simmons - 2011-2018 Sergey Alirzaev - 2011-2018 Simon Wright - 2011-2018 Stany MARCEL - 2011-2018 Stefan Misik - 2011-2018 Sven Wegener - 2011-2018 Tectu - 2011-2018 tekaikko - 2011-2018 texane - 2011-2018 Theodore A. Roth - 2011-2018 Thomas Gärtner - 2011-2018 Tobias Badertscher - 2011-2018 Tom de Boer - 2011-2018 Tristan Gingold - 2011-2018 Uli Köhler - 2011-2018 Uwe Bonnes - 2011-2018 Vadim Kaushan - 2011-2018 Vegard Storheil Eriksen - 2011-2018 Viacheslav Dobromyslov - 2011-2018 Victor Mayoral Vilches - 2011-2018 Wojciech A. Koszek - 2011-2018 Woodrow Douglass - 2011-2018 The "Capt'ns Missing Link" Authors. +Copyright: 2011-2020 stlink-org + Martin Capitanio [capnm] + Fabien Le Mentec [texane] + Jerry Jacobs [xor-gate] + [Nightwalker-87] + and many others... + An extended list of contributors can be found in "contributors.txt". License: BSD-3-clause - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions - are met: - . - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - * Neither the name of Intel Corporation nor the names of its - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - . - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + . + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its + contributors may be used to endorse or promote products derived from + this software without specific prior written permission. + . + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. diff --git a/debian/libstlink-dev.install b/debian/libstlink-dev.install index 0c3543cd9..4e0e0d184 100644 --- a/debian/libstlink-dev.install +++ b/debian/libstlink-dev.install @@ -2,4 +2,3 @@ usr/include/* usr/lib/*/lib*.a usr/lib/*/pkgconfig/* usr/lib/*/lib*.so - diff --git a/debian/stlink-gui.install b/debian/stlink-gui.install index 5620a25e5..96c55213f 100644 --- a/debian/stlink-gui.install +++ b/debian/stlink-gui.install @@ -1,4 +1,4 @@ /usr/bin/stlink-gui -/usr/bin/stlink-gui.ui /usr/share/stlink/ -/usr/share/stlink/applications/stlink-gui.desktop /usr/share/applications/ -/usr/share/stlink/icons/hicolor/scalable/apps/stlink-gui.svg /usr/share/icons/hicolor/scalable/apps/stlink-gui.svg +/usr/share/stlink/stlink-gui.ui +/usr/share/applications/stlink-gui.desktop +/usr/share/icons/hicolor/scalable/apps/stlink-gui.svg diff --git a/debian/stlink.pc.in b/debian/stlink.pc.in index 7fde2d968..9f740ba09 100644 --- a/debian/stlink.pc.in +++ b/debian/stlink.pc.in @@ -3,7 +3,7 @@ includedir=${prefix}/include/stlink libdir=${prefix}/lib/@DEB_HOST_MULTIARCH@ Name: stlink -Description: Open source version of the STMicroelectronics Stlink Tools +Description: Open source STM32 MCU programming toolset Version: @VERSION@ Requires: libusb-1.0 Libs: -L${libdir} -lstlink From 2694214df73557ef30ed234845a0d0f4de9df56b Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Mon, 29 Jun 2020 08:48:43 +0200 Subject: [PATCH 062/503] Corrected install paths & changelog files - man-pages - desktop-file and icons - Fix for external CMAKE_MODULE_PATH - udev-rules - headers & stlink-gui.ui --- CHANGELOG.md | 3 ++- CMakeLists.txt | 15 +++++++++++---- cmake/packaging/deb/changelog | 4 ++-- cmake/packaging/rpm/changelog | 4 ++-- doc/man/CMakeLists.txt | 2 +- doc/version_support.md | 2 +- src/stlink-gui/CMakeLists.txt | 8 ++++---- 7 files changed, 23 insertions(+), 15 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index 3195bae3c..7717ca6f4 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -19,7 +19,7 @@ Features: * Support for STM32L1, SM32L4 option bytes write ([#596](https://github.com/stlink-org/stlink/pull/596), [#844](https://github.com/stlink-org/stlink/pull/844), [#847](https://github.com/stlink-org/stlink/pull/847)) * Added CMAKEFLAGS and install target ([#804](https://github.com/stlink-org/stlink/pull/804), [#935](https://github.com/stlink-org/stlink/pull/935)) * Support for STM32G4 ([#822](https://github.com/stlink-org/stlink/pull/822)) -* Add aliased SRAM2 region in the L496 memory map ([#824](https://github.com/stlink-org/stlink/pull/824)) +* Added aliased SRAM2 region in the L496 memory map ([#824](https://github.com/stlink-org/stlink/pull/824)) * Improved support for STM32G0 ([#825](https://github.com/stlink-org/stlink/pull/825), [#850](https://github.com/stlink-org/stlink/pull/850), [#856](https://github.com/stlink-org/stlink/pull/856), [#857](https://github.com/stlink-org/stlink/pull/857)) * Added postinst script with 'depmod -a' for 'make package' ([#845](https://github.com/stlink-org/stlink/pull/845), [#931](https://github.com/stlink-org/stlink/pull/931)) * Calculate checksums for flash operations ([#862](https://github.com/stlink-org/stlink/pull/862), [#924](https://github.com/stlink-org/stlink/pull/924)) @@ -358,6 +358,7 @@ Chip support added for: * STM32F469/STM32F479 ([#345](https://github.com/stlink-org/stlink/pull/345), [#555](https://github.com/stlink-org/stlink/pull/555)) (Release v1.2.0) * STM32L1xx Cat.2 devices (Nicolas Schodet) * STM32L1xx (chip-ID 0x427) ([#152](https://github.com/stlink-org/stlink/pull/152), [#163](https://github.com/stlink-org/stlink/pull/163), [#165](https://github.com/stlink-org/stlink/pull/165)) (Release v1.0.0) +* Added SIGINT handler for stlink cleanup ([#31](https://github.com/stlink-org/stlink/pull/31), [#135](https://github.com/stlink-org/stlink/pull/135)) (Release v1.0.0) Board support added for: diff --git a/CMakeLists.txt b/CMakeLists.txt index 86282775e..096291b88 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -4,7 +4,7 @@ cmake_minimum_required(VERSION 3.4.2) cmake_policy(SET CMP0042 NEW) -set(CMAKE_MODULE_PATH "${CMAKE_MODULE_PATH};${CMAKE_SOURCE_DIR}/cmake/modules") +set(CMAKE_MODULE_PATH ${CMAKE_SOURCE_DIR}/cmake/modules) set(CMAKE_ARCHIVE_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}/lib) set(CMAKE_LIBRARY_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}/lib) set(CMAKE_RUNTIME_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}/bin) @@ -94,6 +94,13 @@ include_directories(${PROJECT_SOURCE_DIR}/include/stlink/tools) include_directories(src) include_directories(src/tools) ### TODO: Clean this up... +## Set installation directory for header files +set(STLINK_INCLUDE_PATH ${CMAKE_INSTALL_INCLUDEDIR}/${PROJECT_NAME} CACHE PATH "Main include install directory") + +## Subordinate CMakeLists for version config & header installation +#add_subdirectory(inc) + +## Define source- and headerfiles for stlink library set(STLINK_HEADERS include/stlink.h include/stlink/backend.h @@ -143,7 +150,7 @@ endif () set(STLINK_LIBRARY_PATH ${CMAKE_INSTALL_LIBDIR} CACHE PATH "Main library install directory") # Set the environment variable LD_LIBRARY_PATH to point to /usr/local/lib (per default). -execute_process (COMMAND bash -c "export LD_LIBRARY_PATH="${CMAKE_INSTALL_LIBDIR}" ") +execute_process(COMMAND bash -c "export LD_LIBRARY_PATH=${CMAKE_INSTALL_LIBDIR}") ### @@ -259,8 +266,8 @@ if (CMAKE_SYSTEM_NAME STREQUAL "Linux") set(STLINK_MODPROBED_DIR "/etc/modprobe.d" CACHE PATH "modprobe.d directory") install(FILES ${CMAKE_SOURCE_DIR}/config/modprobe.d/stlink_v1.conf DESTINATION ${STLINK_MODPROBED_DIR}) - ## Install udev rules files to /etc/udev/rules.d/ (explicitly hardcoded) - set(STLINK_UDEV_RULES_DIR "/etc/udev/rules.d" CACHE PATH "udev rules directory") + ## Install udev rules files to /lib/udev/rules.d/ (explicitly hardcoded) + set(STLINK_UDEV_RULES_DIR "/lib/udev/rules.d" CACHE PATH "udev rules directory") file(GLOB RULES_FILES ${CMAKE_SOURCE_DIR}/config/udev/rules.d/*.rules) install(FILES ${RULES_FILES} DESTINATION ${STLINK_UDEV_RULES_DIR}) endif () diff --git a/cmake/packaging/deb/changelog b/cmake/packaging/deb/changelog index 196da940e..997ed4056 100644 --- a/cmake/packaging/deb/changelog +++ b/cmake/packaging/deb/changelog @@ -1,5 +1,5 @@ -stlink (1.6.1) unstable; urgency=medium +stlink (1.6.1+ds-1) unstable; urgency=medium - * Initial Debian-packaged Release. + * Initial cpack-based package release for Debian/Ubuntu -- Nightwalker-87 Mon, 01 Jun 2020 00:00:00 +0100 diff --git a/cmake/packaging/rpm/changelog b/cmake/packaging/rpm/changelog index de2400d65..564bd95ae 100644 --- a/cmake/packaging/rpm/changelog +++ b/cmake/packaging/rpm/changelog @@ -1,2 +1,2 @@ -* Mon Jun 01 2020 Vasiliy Glazov - 1.6.1 -- Initial RPM-packaged release +* Mon Jun 01 2020 Nightwalker-87 - 1.6.1 +- Initial cpack-based RPM package release diff --git a/doc/man/CMakeLists.txt b/doc/man/CMakeLists.txt index 23da9e150..9b3c50764 100644 --- a/doc/man/CMakeLists.txt +++ b/doc/man/CMakeLists.txt @@ -30,7 +30,7 @@ foreach (manpage ${MANPAGES}) endif () if (f AND NOT WIN32) - install(FILES ${f} DESTINATION ${CMAKE_INSTALL_DATAROOTDIR}/${PROJECT_NAME}/man/man1) + install(FILES ${f} DESTINATION ${CMAKE_INSTALL_DATAROOTDIR}/man/man1) unset(f) endif () endforeach () diff --git a/doc/version_support.md b/doc/version_support.md index 4d1f724f7..4076fb422 100644 --- a/doc/version_support.md +++ b/doc/version_support.md @@ -68,7 +68,7 @@ NOTE: In order to use a STLINK/v1 programmer on macOS, versions 10.13, 10.14 or ## Unsupported Operating Systems (as of Release v1.6.1) -| Operating System | libusb
version | cmake
version | End of OS-Support | Notes | +| Operating System | libusb
version | cmake
version | End of
OS-Support | Notes | | --- | --- | --- | --- | --- | | CentOS 7 | 1.0.21 | **2.8.12.2** | | named `libusbx`, but
`libusb`-codebase is used | | Debian 8 (Jessie) | 1.0.**19** | 3.**0.2** | Jun 2020 | diff --git a/src/stlink-gui/CMakeLists.txt b/src/stlink-gui/CMakeLists.txt index 8c36e5a1f..db29a72dd 100644 --- a/src/stlink-gui/CMakeLists.txt +++ b/src/stlink-gui/CMakeLists.txt @@ -13,11 +13,11 @@ if (NOT WIN32) # Install desktop application entry install(FILES stlink-gui.desktop - DESTINATION ${CMAKE_INSTALL_DATAROOTDIR}/${PROJECT_NAME}/applications) + DESTINATION ${CMAKE_INSTALL_DATAROOTDIR}/applications) # Install icons install(FILES icons/stlink-gui.svg - DESTINATION ${CMAKE_INSTALL_DATAROOTDIR}/${PROJECT_NAME}/icons/hicolor/scalable/apps) + DESTINATION ${CMAKE_INSTALL_DATAROOTDIR}/icons/hicolor/scalable/apps) set(GUI_SOURCES gui.c gui.h) @@ -30,9 +30,9 @@ if (NOT WIN32) ## stlink-gui add_executable(stlink-gui ${GUI_SOURCES}) - install(FILES stlink-gui.ui DESTINATION ${CMAKE_INSTALL_BINDIR}) + install(FILES stlink-gui.ui DESTINATION ${CMAKE_INSTALL_DATAROOTDIR}/${PROJECT_NAME}) set_target_properties(stlink-gui PROPERTIES - COMPILE_DEFINITIONS STLINK_UI_DIR="${CMAKE_INSTALL_PREFIX}/bin") + COMPILE_DEFINITIONS STLINK_UI_DIR="${CMAKE_INSTALL_DATAROOTDIR}/${PROJECT_NAME}") target_link_libraries(stlink-gui ${STLINK_LIB_SHARED} ${SSP_LIB} ${GTK3_LDFLAGS}) install(TARGETS stlink-gui DESTINATION ${CMAKE_INSTALL_BINDIR}) From 77652688f21253f94e23a7d1c02d5a5bf0008295 Mon Sep 17 00:00:00 2001 From: rutgerhendriks <3134550+rutgerhendriks@users.noreply.github.com> Date: Mon, 6 Jul 2020 09:37:32 +0200 Subject: [PATCH 063/503] Delete ccpp.yml Remove ccpp.yml from workflows --- .github/workflows/ccpp.yml | 17 ----------------- 1 file changed, 17 deletions(-) delete mode 100644 .github/workflows/ccpp.yml diff --git a/.github/workflows/ccpp.yml b/.github/workflows/ccpp.yml deleted file mode 100644 index 23aa0bfc5..000000000 --- a/.github/workflows/ccpp.yml +++ /dev/null @@ -1,17 +0,0 @@ -name: C/C++ CI - -on: - push: - branches: [ master ] - pull_request: - branches: [ master ] - -jobs: - build: - - runs-on: ubuntu-latest - - steps: - - uses: actions/checkout@v2 - - name: make - run: make From e273ec53e8cf2d3df68ada1095f39232f3d7b14f Mon Sep 17 00:00:00 2001 From: Rutger Hendriks Date: Mon, 6 Jul 2020 09:55:19 +0200 Subject: [PATCH 064/503] Revert changing all compiler warning preventions --- src/st-flash/flash.c | 48 +++++++++++++++++++-------------------- src/st-flash/flash_opts.c | 22 +++++++++--------- src/stlink-lib/usb.c | 1 - 3 files changed, 34 insertions(+), 37 deletions(-) diff --git a/src/st-flash/flash.c b/src/st-flash/flash.c index 128b8acc0..4bdc20a16 100644 --- a/src/st-flash/flash.c +++ b/src/st-flash/flash.c @@ -25,8 +25,7 @@ static void cleanup(int signum) { exit(1); } -static void usage(void) -{ +static void usage(void) { puts("command line: ./st-flash [--debug] [--reset] [--opt] [--serial ] [--format ] [--flash=] [--freq=] [--area=] {read|write} [path] [addr] [size]"); puts("command line: ./st-flash [--debug] [--freq=] [--serial ] erase"); puts("command line: ./st-flash [--debug] [--freq=] [--serial ] reset"); @@ -60,13 +59,13 @@ int main(int ac, char** av) { return(-1); } - ILOG("st-flash %s\n", STLINK_VERSION); + printf("st-flash %s\n", STLINK_VERSION); sl = stlink_open_usb(o.log_level, 1, (char *)o.serial, o.freq); if (sl == NULL) { return(-1); } - if (STLINK_FLASH_TYPE_UNKNOWN == sl->flash_type) { + if (sl->flash_type == STLINK_FLASH_TYPE_UNKNOWN) { printf("Failed to connect to target\n"); return(-1); } @@ -84,14 +83,14 @@ int main(int ac, char** av) { signal(SIGTERM, &cleanup); signal(SIGSEGV, &cleanup); - if (STLINK_DEV_DFU_MODE == stlink_current_mode(sl)) { + if (stlink_current_mode(sl) == STLINK_DEV_DFU_MODE) { if (stlink_exit_dfu_mode(sl)) { printf("Failed to exit DFU mode\n"); goto on_error; } } - if (STLINK_DEV_DEBUG_MODE != stlink_current_mode(sl)) { + if (stlink_current_mode(sl) != STLINK_DEV_DEBUG_MODE) { if (stlink_enter_swd_mode(sl)) { printf("Failed to enter SWD mode\n"); goto on_error; @@ -113,7 +112,7 @@ int main(int ac, char** av) { } // disable DMA - Set All DMA CCR Registers to zero. - AKS 1/7/2013 - if (STLINK_CHIPID_STM32_F4 == sl->chip_id) { + if (sl->chip_id == STLINK_CHIPID_STM32_F4) { memset(sl->q_buf, 0, 4); for (int i = 0; i < 8; i++) { @@ -136,10 +135,9 @@ int main(int ac, char** av) { goto on_error; } - if (FLASH_CMD_WRITE == o.cmd) // write - { + if (o.cmd == FLASH_CMD_WRITE) { // write size_t size = 0; - if (FLASH_FORMAT_IHEX == o.format) { + if (o.format == FLASH_FORMAT_IHEX) { err = stlink_parse_ihex(o.filename, stlink_get_erased_pattern(sl), &mem, &size, &o.addr); if (err == -1) { @@ -149,7 +147,7 @@ int main(int ac, char** av) { } if ((o.addr >= sl->flash_base) && (o.addr < sl->flash_base + sl->flash_size)) { - if (FLASH_FORMAT_IHEX == o.format) { + if (o.format == FLASH_FORMAT_IHEX) { err = stlink_mwrite_flash(sl, mem, (uint32_t)size, o.addr); } else { err = stlink_fwrite_flash(sl, o.filename, o.addr); @@ -161,7 +159,7 @@ int main(int ac, char** av) { } } else if ((o.addr >= sl->sram_base) && (o.addr < sl->sram_base + sl->sram_size)) { - if (FLASH_FORMAT_IHEX == o.format) { + if (o.format == FLASH_FORMAT_IHEX) { err = stlink_mwrite_sram(sl, mem, (uint32_t)size, o.addr); } else { err = stlink_fwrite_sram(sl, o.filename, o.addr); @@ -179,7 +177,7 @@ int main(int ac, char** av) { printf("stlink_fwrite_option_bytes() == -1\n"); goto on_error; } - } else if (FLASH_OPTION_BYTES == o.area) { + } else if (o.area == FLASH_OPTION_BYTES) { if (o.val == 0) { printf("attempting to set option byte to 0, abort.\n"); goto on_error; @@ -191,15 +189,15 @@ int main(int ac, char** av) { printf("stlink_write_option_bytes32() == -1\n"); goto on_error; } - } else if (FLASH_OPTCR == o.area) { + } else if (o.area == FLASH_OPTCR) { DLOG("@@@@ Write %d (%0#10x) to option control register\n", o.val, o.val); err = stlink_write_option_control_register32(sl, o.val); - } else if (FLASH_OPTCR1 == o.area) { + } else if (o.area == FLASH_OPTCR1) { DLOG("@@@@ Write %d (%0#10x) to option control register 1\n", o.val, o.val); err = stlink_write_option_control_register1_32(sl, o.val); - } else if (FLASH_OPTION_BYTES_BOOT_ADD == o.area) { + } else if (o.area == FLASH_OPTION_BYTES_BOOT_ADD) { DLOG("@@@@ Write %d (%0#10x) to option bytes boot address\n", o.val, o.val); err = stlink_write_option_bytes_boot_add32(sl, o.val); @@ -208,14 +206,14 @@ int main(int ac, char** av) { printf("Unknown memory region\n"); goto on_error; } - } else if (FLASH_CMD_ERASE == o.cmd) { + } else if (o.cmd == FLASH_CMD_ERASE) { err = stlink_erase_flash_mass(sl); if (err == -1) { printf("stlink_erase_flash_mass() == -1\n"); goto on_error; } - } else if (CMD_RESET == o.cmd) { + } else if (o.cmd == CMD_RESET) { if (sl->version.stlink_v > 1) { if (stlink_jtag_reset(sl, 2)) { printf("Failed to reset JTAG\n"); @@ -228,20 +226,20 @@ int main(int ac, char** av) { goto on_error; } } else { // read - if ((FLASH_MAIN_MEMORY == o.area) || (FLASH_SYSTEM_MEMORY == o.area)) { + if ((o.area == FLASH_MAIN_MEMORY) || (o.area == FLASH_SYSTEM_MEMORY)) { if ((o.size == 0) && (o.addr >= sl->flash_base) && (o.addr < sl->flash_base + sl->flash_size)) { o.size = sl->flash_size; } else if ((o.size == 0) && (o.addr >= sl->sram_base) && (o.addr < sl->sram_base + sl->sram_size)) { o.size = sl->sram_size; } - err = stlink_fread(sl, o.filename, FLASH_FORMAT_IHEX == o.format, o.addr, o.size); + err = stlink_fread(sl, o.filename, o.format == FLASH_FORMAT_IHEX, o.addr, o.size); if (err == -1) { printf("stlink_fread() == -1\n"); goto on_error; } - } else if (FLASH_OPTION_BYTES == o.area) { + } else if (o.area == FLASH_OPTION_BYTES) { uint8_t remaining_option_length = sl->option_size / 4; DLOG("@@@@ Read %d (%#x) option bytes from %#10x\n", remaining_option_length, remaining_option_length, sl->option_base); @@ -249,7 +247,7 @@ int main(int ac, char** av) { if (0 == o.size) { o.size = sl->option_size; } - err = stlink_fread(sl, o.filename, FLASH_FORMAT_IHEX == o.format, sl->option_base, o.size); + err = stlink_fread(sl, o.filename, o.format == FLASH_FORMAT_IHEX, sl->option_base, o.size); } else { uint32_t option_byte = 0; err = stlink_read_option_bytes32(sl, &option_byte); @@ -260,7 +258,7 @@ int main(int ac, char** av) { printf("%08x\n", option_byte); } } - } else if (FLASH_OPTION_BYTES_BOOT_ADD == o.area) { + } else if (o.area == FLASH_OPTION_BYTES_BOOT_ADD) { uint32_t option_byte = 0; err = stlink_read_option_bytes_boot_add32(sl, &option_byte); if (err == -1) { @@ -269,7 +267,7 @@ int main(int ac, char** av) { } else { printf("%08x\n",option_byte); } - } else if (FLASH_OPTCR == o.area) { + } else if (o.area == FLASH_OPTCR) { uint32_t option_byte = 0; err = stlink_read_option_control_register32(sl, &option_byte); if (err == -1) { @@ -278,7 +276,7 @@ int main(int ac, char** av) { } else { printf("%08x\n",option_byte); } - } else if (FLASH_OPTCR1 == o.area) { + } else if (o.area == FLASH_OPTCR1) { uint32_t option_byte = 0; err = stlink_read_option_control_register1_32(sl, &option_byte); if (err == -1) { diff --git a/src/st-flash/flash_opts.c b/src/st-flash/flash_opts.c index 6653c6e62..1cfd6fe89 100644 --- a/src/st-flash/flash_opts.c +++ b/src/st-flash/flash_opts.c @@ -274,7 +274,7 @@ int flash_get_opts(struct flash_opts* o, int ac, char** av) { break; case FLASH_CMD_READ: // expect filename, addr and size - if ((FLASH_MAIN_MEMORY == o->area) || (FLASH_SYSTEM_MEMORY == o->area)) { + if ((o->area == FLASH_MAIN_MEMORY) || (o->area == FLASH_SYSTEM_MEMORY)) { if (ac != 3) { return invalid_args("read "); } o->filename = av[0]; @@ -295,12 +295,12 @@ int flash_get_opts(struct flash_opts* o, int ac, char** av) { } break; - } else if ((FLASH_OTP == o->area)) { + } else if ((o->area == FLASH_OTP)) { return bad_arg("TODO: otp not implemented yet"); if (ac > 1) { return invalid_args("otp read: [path]"); } if (ac > 0) { o->filename = av[0]; } break; - } else if ((FLASH_OPTION_BYTES == o->area)) { + } else if ((o->area == FLASH_OPTION_BYTES)) { if (ac > 2) { return invalid_args("option bytes read: [path] [size]"); } if (ac > 0) { o->filename = av[0]; } if (ac > 1) { @@ -313,13 +313,13 @@ int flash_get_opts(struct flash_opts* o, int ac, char** av) { } } break; - } else if ((FLASH_OPTION_BYTES_BOOT_ADD == o->area)) { + } else if ((o->area == FLASH_OPTION_BYTES_BOOT_ADD)) { if (ac > 0) { return invalid_args("option bytes boot_add read"); } break; - } else if ((FLASH_OPTCR == o->area)) { + } else if ((o->area == FLASH_OPTCR)) { if (ac > 0) { return invalid_args("option control register read"); } break; - } else if ((FLASH_OPTCR1 == o->area)) { + } else if ((o->area == FLASH_OPTCR1)) { if (ac > 0) { return invalid_args("option control register 1 read"); } break; } @@ -328,7 +328,7 @@ int flash_get_opts(struct flash_opts* o, int ac, char** av) { case FLASH_CMD_WRITE: // TODO: should be boot add 0 and boot add 1 uint32 - if (FLASH_OPTION_BYTES == o->area) { // expect filename and optional address + if (o->area == FLASH_OPTION_BYTES) { // expect filename and optional address if (ac >=1 && ac <= 2) { o->filename = av[0]; } else { @@ -344,7 +344,7 @@ int flash_get_opts(struct flash_opts* o, int ac, char** av) { o->addr = (stm32_addr_t) addr; } } - } else if (FLASH_OPTION_BYTES_BOOT_ADD == o->area) { // expect option bytes boot address + } else if (o->area == FLASH_OPTION_BYTES_BOOT_ADD) { // expect option bytes boot address if (ac != 1) { return invalid_args("option bytes boot_add write "); } uint32_t val; @@ -355,7 +355,7 @@ int flash_get_opts(struct flash_opts* o, int ac, char** av) { } else { o->val = (uint32_t)val; } - } else if (FLASH_OPTCR == o->area) { // expect option control register value + } else if (o->area == FLASH_OPTCR) { // expect option control register value if (ac != 1) { return invalid_args("option control register write "); } uint32_t val; @@ -366,7 +366,7 @@ int flash_get_opts(struct flash_opts* o, int ac, char** av) { } else { o->val = (uint32_t) val; } - } else if (FLASH_OPTCR1 == o->area) { // expect option control register 1 value + } else if (o->area == FLASH_OPTCR1) { // expect option control register 1 value if (ac != 1) { return invalid_args("option control register 1 write "); } uint32_t val; @@ -376,7 +376,7 @@ int flash_get_opts(struct flash_opts* o, int ac, char** av) { } else { o->val = (uint32_t) val; } - } else if (FLASH_FORMAT_BINARY == o->format) { // expect filename and addr + } else if (o->format == FLASH_FORMAT_BINARY) { // expect filename and addr if (ac != 2) { return invalid_args("write "); } o->filename = av[0]; diff --git a/src/stlink-lib/usb.c b/src/stlink-lib/usb.c index a7875eb57..f9b4775f3 100644 --- a/src/stlink-lib/usb.c +++ b/src/stlink-lib/usb.c @@ -710,7 +710,6 @@ int _stlink_usb_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { cmd[i++] = STLINK_DEBUG_COMMAND; cmd[i++] = STLINK_DEBUG_READMEM_32BIT; - DLOG("using address %#010x\n", addr); write_uint32(&cmd[i], addr); write_uint16(&cmd[i + 4], len); size = send_recv(slu, 1, cmd, slu->cmd_len, data, len); From ca02a8d507430e2a45e5c6fa9b019ab042c91770 Mon Sep 17 00:00:00 2001 From: Rutger Hendriks Date: Mon, 6 Jul 2020 10:07:26 +0200 Subject: [PATCH 065/503] src/st-flash/flash.c: improved error message --- src/st-flash/flash.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/st-flash/flash.c b/src/st-flash/flash.c index 4bdc20a16..9116f9c80 100644 --- a/src/st-flash/flash.c +++ b/src/st-flash/flash.c @@ -236,7 +236,7 @@ int main(int ac, char** av) { err = stlink_fread(sl, o.filename, o.format == FLASH_FORMAT_IHEX, o.addr, o.size); if (err == -1) { - printf("stlink_fread() == -1\n"); + printf("could not read main memory (%d)\n", err); goto on_error; } } else if (o.area == FLASH_OPTION_BYTES) { From ebb3164d903f9780beaf6d5f7c95b27f2b64ddc1 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sat, 18 Jul 2020 00:46:26 +0200 Subject: [PATCH 066/503] Updated CHANGELOG & README --- CHANGELOG.md | 27 ++++++++++++++++++++++++++- README.md | 8 +++++--- 2 files changed, 31 insertions(+), 4 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index 7717ca6f4..5ad1ec2d4 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -1,6 +1,31 @@ stlink ChangeLog ================ +v1.6.2 +====== + +Release date: (TBD) + +Features: + +Updates & changes: + +* [doc] st-flash --reset parameter (one solution for #356) ([#642](https://github.com/stlink-org/stlink/pull/642)) +* [refactoring] General maintenance ([#864](https://github.com/stlink-org/stlink/pull/864), [#976](https://github.com/stlink-org/stlink/pull/976), [#978](https://github.com/stlink-org/stlink/pull/978)) +* Imported debian pkg-settings ([#986](https://github.com/stlink-org/stlink/pull/986)) +* Add support for FreeBSD's libusb reimplementation ([#992](https://github.com/stlink-org/stlink/pull/992), [#993](https://github.com/stlink-org/stlink/pull/993)) + +Fixes: + +* [regression] Changed timeout on flash write ([#787](https://github.com/stlink-org/stlink/pull/787), [#981](https://github.com/stlink-org/stlink/pull/981), [#987](https://github.com/stlink-org/stlink/pull/987)) +* cmake compile failure with external CMAKE_MODULE_PATH set ([#962](https://github.com/stlink-org/stlink/pull/962)) +* doc/man: Fixed installation directory ([#970](https://github.com/stlink-org/stlink/pull/970)) +* Fixed installation path for desktop-file and icons ([#972](https://github.com/stlink-org/stlink/pull/972)) +* Fix for static linking of libssp ([#973](https://github.com/stlink-org/stlink/pull/973), [#974](https://github.com/stlink-org/stlink/pull/974)) +* Fixed connect under reset for st-flash and st-util ([#983](https://github.com/stlink-org/stlink/pull/983)) +* Fix for mmap() size_t overflow in st-flash ([#988](https://github.com/stlink-org/stlink/pull/988), [#989](https://github.com/stlink-org/stlink/pull/989)) + + v1.6.1 ====== @@ -139,7 +164,7 @@ Updates and fixes: * Fixed relative path to the UI files needed by stlink-gui-local (GUI) ([#770](https://github.com/stlink-org/stlink/pull/770), [#771](https://github.com/stlink-org/stlink/pull/771)) * Added howto for sending NRST signal through GDB ([#774](https://github.com/stlink-org/stlink/pull/774), [#776](https://github.com/stlink-org/stlink/pull/776), [#779](https://github.com/stlink-org/stlink/pull/779)) * Fixed package name "devscripts" in doc/compiling.md ([#775](https://github.com/stlink-org/stlink/pull/775)) -* Fixed few potential memory/resource leaks ([#803](https://github.com/stlink-org/stlink/pull/803)) +* Fixed few potential memory/resource leaks ([#803](https://github.com/stlink-org/stlink/pull/803), [#831](https://github.com/stlink-org/stlink/pull/831)) * Updated Linux source repositories in README.md: Debian and Ubuntu ([#821](https://github.com/stlink-org/stlink/pull/821), [#835](https://github.com/stlink-org/stlink/pull/835), [#859](https://github.com/stlink-org/stlink/pull/859)) * Do not issue JTAG reset on stlink-v1 ([#828](https://github.com/stlink-org/stlink/pull/828)) * Fixed flash size of STM32 Discovery vl ([#829](https://github.com/stlink-org/stlink/pull/829)) diff --git a/README.md b/README.md index 21ab9f48b..5be842156 100644 --- a/README.md +++ b/README.md @@ -23,7 +23,7 @@ The stlink library and tools are licensed under the **[BSD-3 License](LICENSE.md STLink is an open source toolset to program and debug STM32 devices and boards manufactured by STMicroelectronics. It supports several so called STLINK programmer boards (and clones thereof) which use a microcontroller chip to translate commands from USB to JTAG/SWD. There are four generations available on the market which are _all_ supported by this toolset: -* **STLINK/v1** _(obsolete as of 21-11-2019)_ +* **STLINK/v1** _(obsolete as of 21-11-2019, continued support by this toolset)_ - transport layer: SCSI passthru commands over USB - stand-alone programmer and present on STM32VL Discovery boards * **STLINK/v2** @@ -83,8 +83,10 @@ Alternatively one can compile and install from source as described in our [compi We recommend to install `stlink-tools` from the package repository of the used distribution: -* Debian Linux: [(Link)](https://packages.debian.org/buster/stlink-tools) -* Ubuntu Linux: [(Link)](https://packages.ubuntu.com/stlink-tools) +**Note:** As packages distributed via the [Debian](https://packages.debian.org/buster/stlink-tools) and [Ubuntu](https://packages.ubuntu.com/stlink-tools) repositories differ from our self-maintained deb-package, we recommend to use the latter instead (see link below). It provides the opportunity to handle and fix user-reported package issues directly within the project and is not redundant to any limitations deriving from external maintenance guidelines. + +* Debian Linux: [(Link)](https://github.com/stlink-org/stlink/releases) +* Ubuntu Linux: [(Link)](https://github.com/stlink-org/stlink/releases) * Arch Linux: [(Link)](https://www.archlinux.org/packages/community/x86_64/stlink) * Alpine Linux: [(Link)](https://pkgs.alpinelinux.org/packages?name=stlink) * Fedora: [(Link)](https://src.fedoraproject.org/rpms/stlink) From 56a699d37569caf591497427d42b5ad466c7a480 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sat, 18 Jul 2020 00:56:49 +0200 Subject: [PATCH 067/503] Added missing cmake install prefix (Closes #1006) --- src/stlink-gui/CMakeLists.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/stlink-gui/CMakeLists.txt b/src/stlink-gui/CMakeLists.txt index 258f83cc1..46224dddb 100644 --- a/src/stlink-gui/CMakeLists.txt +++ b/src/stlink-gui/CMakeLists.txt @@ -35,7 +35,7 @@ if (NOT WIN32 AND NOT CMAKE_CROSSCOMPILING) add_executable(stlink-gui ${GUI_SOURCES}) install(FILES stlink-gui.ui DESTINATION ${CMAKE_INSTALL_DATAROOTDIR}/${PROJECT_NAME}) set_target_properties(stlink-gui PROPERTIES - COMPILE_DEFINITIONS STLINK_UI_DIR="${CMAKE_INSTALL_DATAROOTDIR}/${PROJECT_NAME}") + COMPILE_DEFINITIONS STLINK_UI_DIR="${CMAKE_INSTALL_PREFIX}/${CMAKE_INSTALL_DATAROOTDIR}/${PROJECT_NAME}") target_link_libraries(stlink-gui ${STLINK_LIB_SHARED} ${SSP_LIB} ${GTK3_LDFLAGS}) install(TARGETS stlink-gui DESTINATION ${CMAKE_INSTALL_BINDIR}) endif () From f57ae0c7142dd86b2dd5b0c298f7105ab65d574e Mon Sep 17 00:00:00 2001 From: Rutger Hendriks Date: Sun, 19 Jul 2020 16:55:02 +0200 Subject: [PATCH 068/503] Remove double parantheses --- src/st-flash/flash_opts.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/src/st-flash/flash_opts.c b/src/st-flash/flash_opts.c index 1cfd6fe89..ab716bb31 100644 --- a/src/st-flash/flash_opts.c +++ b/src/st-flash/flash_opts.c @@ -295,12 +295,12 @@ int flash_get_opts(struct flash_opts* o, int ac, char** av) { } break; - } else if ((o->area == FLASH_OTP)) { + } else if (o->area == FLASH_OTP) { return bad_arg("TODO: otp not implemented yet"); if (ac > 1) { return invalid_args("otp read: [path]"); } if (ac > 0) { o->filename = av[0]; } break; - } else if ((o->area == FLASH_OPTION_BYTES)) { + } else if (o->area == FLASH_OPTION_BYTES) { if (ac > 2) { return invalid_args("option bytes read: [path] [size]"); } if (ac > 0) { o->filename = av[0]; } if (ac > 1) { @@ -313,13 +313,13 @@ int flash_get_opts(struct flash_opts* o, int ac, char** av) { } } break; - } else if ((o->area == FLASH_OPTION_BYTES_BOOT_ADD)) { + } else if (o->area == FLASH_OPTION_BYTES_BOOT_ADD) { if (ac > 0) { return invalid_args("option bytes boot_add read"); } break; - } else if ((o->area == FLASH_OPTCR)) { + } else if (o->area == FLASH_OPTCR) { if (ac > 0) { return invalid_args("option control register read"); } break; - } else if ((o->area == FLASH_OPTCR1)) { + } else if (o->area == FLASH_OPTCR1) { if (ac > 0) { return invalid_args("option control register 1 read"); } break; } From 2dd47a432710c77f9dfd9a661212643a9667361f Mon Sep 17 00:00:00 2001 From: Rutger Hendriks Date: Sun, 19 Jul 2020 17:35:38 +0200 Subject: [PATCH 069/503] Reverted the last comparison changes --- src/st-flash/flash_opts.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/st-flash/flash_opts.c b/src/st-flash/flash_opts.c index ab716bb31..e74ecc1ce 100644 --- a/src/st-flash/flash_opts.c +++ b/src/st-flash/flash_opts.c @@ -242,18 +242,18 @@ int flash_get_opts(struct flash_opts* o, int ac, char** av) { // command and (optional) device name while (ac >= 1) { if (strcmp(av[0], "erase") == 0) { - if (FLASH_CMD_NONE != o->cmd) { return(-1); } + if (o->cmd != FLASH_CMD_NONE) { return(-1); } o->cmd = FLASH_CMD_ERASE; } else if (strcmp(av[0], "read") == 0) { - if (FLASH_CMD_NONE != o->cmd) { return(-1); } + if (o->cmd != FLASH_CMD_NONE) { return(-1); } o->cmd = FLASH_CMD_READ; } else if (strcmp(av[0], "write") == 0) { - if (FLASH_CMD_NONE != o->cmd) { return(-1); } + if (o->cmd != FLASH_CMD_NONE) { return(-1); } o->cmd = FLASH_CMD_WRITE; } else if (strcmp(av[0], "reset") == 0) { - if (FLASH_CMD_NONE != o->cmd) { return(-1); } + if (o->cmd != FLASH_CMD_NONE) { return(-1); } o->cmd = CMD_RESET; } else { From 1bcfdf5d42a29dedb44821ce30bbe6b915ebbb9a Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sat, 8 Aug 2020 13:22:56 +0200 Subject: [PATCH 070/503] Updated CHANGELOG.md & contributors.txt --- CHANGELOG.md | 2 ++ cmake/packaging/deb/control | 2 +- contributors.txt | 1 + 3 files changed, 4 insertions(+), 1 deletion(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index 5ad1ec2d4..01e679b3c 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -8,6 +8,8 @@ Release date: (TBD) Features: +* Option bytes on the STM32F767 ZIT6 Nucleo-144 ([#968](https://github.com/stlink-org/stlink/pull/968), [#997](https://github.com/stlink-org/stlink/pull/997)) + Updates & changes: * [doc] st-flash --reset parameter (one solution for #356) ([#642](https://github.com/stlink-org/stlink/pull/642)) diff --git a/cmake/packaging/deb/control b/cmake/packaging/deb/control index 759668ba6..ef51a6cea 100644 --- a/cmake/packaging/deb/control +++ b/cmake/packaging/deb/control @@ -1,6 +1,6 @@ Source: stlink Priority: optional -Maintainer: stlink-org +Maintainer: Nightwalker-87 Build-Depends: cmake, dh-cmake, debhelper (>= 9), libusb-1.0-0-dev, libgtk-3-dev Standards-Version: 4.5.0 Rules-Requires-Root: no diff --git a/contributors.txt b/contributors.txt index fec7510c3..cc9403456 100644 --- a/contributors.txt +++ b/contributors.txt @@ -103,6 +103,7 @@ Robin Kreis Roger Wolff [rewolff] Rob Spanton Rytis Karpuska +Rutger Hendriks [rutgerhendriks] Sean Simmons Sergey Alirzaev Simon Derr [sderr] From baab8ca2f9f7b5fcfd9a15c0bc61069a846e1f4f Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sat, 15 Aug 2020 21:31:52 +0200 Subject: [PATCH 071/503] Updated ISSUE_TEMPLATES (Closes #1014) --- ...ort--only-valid-if-template-is-reused--.md | 38 ------------------- .github/ISSUE_TEMPLATE/bug-report.md | 15 ++++---- .github/ISSUE_TEMPLATE/feature-request.md | 16 ++++---- 3 files changed, 14 insertions(+), 55 deletions(-) delete mode 100644 .github/ISSUE_TEMPLATE/bug-report--only-valid-if-template-is-reused--.md diff --git a/.github/ISSUE_TEMPLATE/bug-report--only-valid-if-template-is-reused--.md b/.github/ISSUE_TEMPLATE/bug-report--only-valid-if-template-is-reused--.md deleted file mode 100644 index 255596955..000000000 --- a/.github/ISSUE_TEMPLATE/bug-report--only-valid-if-template-is-reused--.md +++ /dev/null @@ -1,38 +0,0 @@ ---- -name: Bug Report (only valid if template is reused!) -about: 'Please read #906 before submitting a ticket.' -title: "[STM32 device name]: [Title]" -labels: '' -assignees: '' - ---- - -Thank you for giving feedback to the stlink project. - -In order to allow developers and other contributors to isolate and target your respective issue, please take some time to fill out each of the following items appropriate to your specific problem: - -- Programmer/board type: [enter here] (e.g Stlink /v1, /v2, /v2-clone, /v2-1) -- Programmer firmware version: [enter here] (e.g STSW-LINK007 2.27.15) -- Operating system and version: [enter here] (e.g Linux, Mac OS X, Windows) -- **Stlink tools version** and/or git commit hash: [enter here] (e.g v1.1.0/git-c722056) -- Stlink commandline tool name: [enter here] (e.g `st-info`, `st-flash`, `st-util`) -- Target chip (and board if applicable): [enter here] (e.g STM32F402VG) - -Futher we kindly ask you to describe the detected problem as detailed as possible and to add debug output if available, by using the following template: - -Commandline-Output: - -``` -OUTPUT/ERROR of the commandline tool(s) -``` - -Expected/description: - -`short description of the expected value` - - -**NOTICE: This bug report may be closed without further notice, if not enough information is provided!** - -Thank you for your support. - -The stlink project maintainers diff --git a/.github/ISSUE_TEMPLATE/bug-report.md b/.github/ISSUE_TEMPLATE/bug-report.md index 344a53ea6..fc30f3993 100644 --- a/.github/ISSUE_TEMPLATE/bug-report.md +++ b/.github/ISSUE_TEMPLATE/bug-report.md @@ -1,18 +1,19 @@ --- -name: Bug Report -about: 'Please read #906 before submitting a ticket.' -title: "[STM32 device name]: [Title]" +name: "Bug Report" +about: "Report a bug" +title: "[STM32 device name]: [_$YourTitle_]" labels: '' -assignees: '' - --- Thank you for giving feedback to the stlink project. +**NOTICE: Please read and follow instructions in #906 before submitting a ticket. This feature request will be deleted without notice when not enough information is provided! So please ensure that all fields are filled out.** + +- [ ] I made serious effort to avoid creating duplicate or nearly similar issue + In order to allow developers and other contributors to isolate and target your respective issue, please take some time to fill out each of the following items appropriate to your specific problem: - Programmer/board type: [enter here] (e.g Stlink /v1, /v2, /v2-clone, /v2-1) -- Programmer firmware version: [enter here] (e.g STSW-LINK007 2.27.15) - Operating system and version: [enter here] (e.g Linux, Mac OS X, Windows) - **Stlink tools version** and/or git commit hash: [enter here] (e.g v1.1.0/git-c722056) - Stlink commandline tool name: [enter here] (e.g `st-info`, `st-flash`, `st-util`) @@ -31,8 +32,6 @@ Expected/description: `short description of the expected value` -**NOTICE: This bug report may be closed without further notice, if not enough information is provided!** - Thank you for your support. The stlink project maintainers diff --git a/.github/ISSUE_TEMPLATE/feature-request.md b/.github/ISSUE_TEMPLATE/feature-request.md index 2aa7a5c7f..133b895b2 100644 --- a/.github/ISSUE_TEMPLATE/feature-request.md +++ b/.github/ISSUE_TEMPLATE/feature-request.md @@ -1,18 +1,19 @@ --- -name: Feature Request -about: Suggest an idea for this project -title: "[feature] " +name: "Feature Request" +about: "Suggest an idea for this project" +title: "[feature] [_$YourTitle_]" labels: code/feature-request -assignees: '' - --- Thank you for giving feedback to the stlink project. +**NOTICE: Please read and follow instructions in #906 before submitting a ticket. This feature request will be deleted without notice when not enough information is provided! So please ensure that all fields are filled out.** + +- [ ] I made serious effort to avoid creating duplicate or nearly similar issue + In order to allow developers and other contributors to isolate and target your respective issue, please take some time to fill out the check boxes below by setting a 'x' into the checkboxes ( [x] ) and edit each item appropriate to your specific problem. - [ ] Programmer/board type: e.g Stlink/v1, Stlink/v2, Stlink/v2-onboard -- [ ] Programmer firmware version: e.g STSW-LINK007 2.27.15 - [ ] Operating system: e.g Linux, Mac OS X, Windows (with specific version) - [ ] Stlink tools version and/or git commit hash: e.g v1.1.0/git-c722056 - [ ] Stlink commandline tool name: e.g `st-info`, `st-flash`, `st-util` @@ -31,9 +32,6 @@ Expected/description: `short description of the expected value` -**NOTICE: This feature request may be closed without notice when not enough information is provided!** - - Thank you for your support. The stlink project maintainers From 6f3657477739582a437693797136267c45009415 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sat, 15 Aug 2020 21:38:36 +0200 Subject: [PATCH 072/503] Updated ISSUE_TEMPLATES (Closes #1014) --- .github/ISSUE_TEMPLATE/bug-report.md | 15 +++++++-------- .github/ISSUE_TEMPLATE/feature-request.md | 16 +++++++--------- 2 files changed, 14 insertions(+), 17 deletions(-) diff --git a/.github/ISSUE_TEMPLATE/bug-report.md b/.github/ISSUE_TEMPLATE/bug-report.md index 344a53ea6..fc30f3993 100644 --- a/.github/ISSUE_TEMPLATE/bug-report.md +++ b/.github/ISSUE_TEMPLATE/bug-report.md @@ -1,18 +1,19 @@ --- -name: Bug Report -about: 'Please read #906 before submitting a ticket.' -title: "[STM32 device name]: [Title]" +name: "Bug Report" +about: "Report a bug" +title: "[STM32 device name]: [_$YourTitle_]" labels: '' -assignees: '' - --- Thank you for giving feedback to the stlink project. +**NOTICE: Please read and follow instructions in #906 before submitting a ticket. This feature request will be deleted without notice when not enough information is provided! So please ensure that all fields are filled out.** + +- [ ] I made serious effort to avoid creating duplicate or nearly similar issue + In order to allow developers and other contributors to isolate and target your respective issue, please take some time to fill out each of the following items appropriate to your specific problem: - Programmer/board type: [enter here] (e.g Stlink /v1, /v2, /v2-clone, /v2-1) -- Programmer firmware version: [enter here] (e.g STSW-LINK007 2.27.15) - Operating system and version: [enter here] (e.g Linux, Mac OS X, Windows) - **Stlink tools version** and/or git commit hash: [enter here] (e.g v1.1.0/git-c722056) - Stlink commandline tool name: [enter here] (e.g `st-info`, `st-flash`, `st-util`) @@ -31,8 +32,6 @@ Expected/description: `short description of the expected value` -**NOTICE: This bug report may be closed without further notice, if not enough information is provided!** - Thank you for your support. The stlink project maintainers diff --git a/.github/ISSUE_TEMPLATE/feature-request.md b/.github/ISSUE_TEMPLATE/feature-request.md index 2aa7a5c7f..133b895b2 100644 --- a/.github/ISSUE_TEMPLATE/feature-request.md +++ b/.github/ISSUE_TEMPLATE/feature-request.md @@ -1,18 +1,19 @@ --- -name: Feature Request -about: Suggest an idea for this project -title: "[feature] " +name: "Feature Request" +about: "Suggest an idea for this project" +title: "[feature] [_$YourTitle_]" labels: code/feature-request -assignees: '' - --- Thank you for giving feedback to the stlink project. +**NOTICE: Please read and follow instructions in #906 before submitting a ticket. This feature request will be deleted without notice when not enough information is provided! So please ensure that all fields are filled out.** + +- [ ] I made serious effort to avoid creating duplicate or nearly similar issue + In order to allow developers and other contributors to isolate and target your respective issue, please take some time to fill out the check boxes below by setting a 'x' into the checkboxes ( [x] ) and edit each item appropriate to your specific problem. - [ ] Programmer/board type: e.g Stlink/v1, Stlink/v2, Stlink/v2-onboard -- [ ] Programmer firmware version: e.g STSW-LINK007 2.27.15 - [ ] Operating system: e.g Linux, Mac OS X, Windows (with specific version) - [ ] Stlink tools version and/or git commit hash: e.g v1.1.0/git-c722056 - [ ] Stlink commandline tool name: e.g `st-info`, `st-flash`, `st-util` @@ -31,9 +32,6 @@ Expected/description: `short description of the expected value` -**NOTICE: This feature request may be closed without notice when not enough information is provided!** - - Thank you for your support. The stlink project maintainers From 61c5e395e2a850c0bc593d086d858091939ce238 Mon Sep 17 00:00:00 2001 From: Hassan DRAGA <61518789+dragahassan@users.noreply.github.com> Date: Fri, 28 Aug 2020 10:35:16 -0300 Subject: [PATCH 073/503] Fixing wrong path It's seem etc folder no longer exist, now it's on "stlink/config/udev/rules.d" instead of "stlink/etc/udev/rules.d". --- doc/compiling.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/doc/compiling.md b/doc/compiling.md index c278c9ca8..48a429774 100644 --- a/doc/compiling.md +++ b/doc/compiling.md @@ -159,7 +159,7 @@ The rules are located in the subdirectory `config/udev/rules.d` within the sourc Afterwards it may be necessary to reload the udev rules: ```sh -$ cp etc/udev/rules.d /etc/udev/rules.d +$ cp config/udev/rules.d /etc/udev/rules.d $ udevadm control --reload-rules $ udevadm trigger ``` From 00a6ae027725e9850da5f550e193fa3dc7297eb5 Mon Sep 17 00:00:00 2001 From: Hassan DRAGA <61518789+dragahassan@users.noreply.github.com> Date: Fri, 28 Aug 2020 10:43:06 -0300 Subject: [PATCH 074/503] Updating commands Updating commands for "rules.d" --- doc/compiling.md | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/doc/compiling.md b/doc/compiling.md index 48a429774..7f2ba698e 100644 --- a/doc/compiling.md +++ b/doc/compiling.md @@ -159,9 +159,9 @@ The rules are located in the subdirectory `config/udev/rules.d` within the sourc Afterwards it may be necessary to reload the udev rules: ```sh -$ cp config/udev/rules.d /etc/udev/rules.d -$ udevadm control --reload-rules -$ udevadm trigger +$ sudo cp -a config/udev/rules.d/. /etc/udev/rules.d +$ sudo udevadm control --reload-rules +$ sudo udevadm trigger ``` Udev will now create device node files `/dev/stlinkv2_XX`, `/dev/stlinkv1_XX`.
From 5ea485de396ce004604a0adc4bf1278c6a3a845f Mon Sep 17 00:00:00 2001 From: Oleksiy Slyshyk Date: Fri, 28 Aug 2020 23:35:45 +0300 Subject: [PATCH 075/503] use SetConsoleCtrlHandler for windows --- .gitignore | 1 + src/st-util/gdb-server.c | 21 ++++++++++++++++++--- 2 files changed, 19 insertions(+), 3 deletions(-) diff --git a/.gitignore b/.gitignore index 229242a53..9fbe0139c 100644 --- a/.gitignore +++ b/.gitignore @@ -3,3 +3,4 @@ build-mingw .project obj-* *.user* +.cmake/ diff --git a/src/st-util/gdb-server.c b/src/st-util/gdb-server.c index 94cd6fda7..60c9c16d3 100644 --- a/src/st-util/gdb-server.c +++ b/src/st-util/gdb-server.c @@ -71,19 +71,30 @@ int serve(stlink_t *sl, st_state_t *st); char* make_memory_map(stlink_t *sl); static void init_cache(stlink_t *sl); -static void cleanup(int signum) { - (void)signum; - +static void _cleanup() { if (connected_stlink) { // Switch back to mass storage mode before closing stlink_run(connected_stlink); stlink_exit_debug_mode(connected_stlink); stlink_close(connected_stlink); } +} +static void cleanup(int signum) { + printf("Receive signal %i. Exiting...\n", signum); + _cleanup(); exit(1); + (void)signum; } +#if defined(_WIN32) +BOOL WINAPI CtrlHandler(DWORD fdwCtrlType) { + printf("Receive signal %i. Exiting...\r\n", (int)fdwCtrlType); + _cleanup(); + return FALSE; +} +#endif + static stlink_t* do_connect(st_state_t *st) { stlink_t *sl = NULL; @@ -234,9 +245,13 @@ int main(int argc, char** argv) { } connected_stlink = sl; +#if defined(_WIN32) + SetConsoleCtrlHandler((PHANDLER_ROUTINE) CtrlHandler, TRUE); +#else signal(SIGINT, &cleanup); signal(SIGTERM, &cleanup); signal(SIGSEGV, &cleanup); +#endif if (state.reset) { stlink_reset(sl); } From 203d68544b5fe4858854c06df66e1142d12b27bd Mon Sep 17 00:00:00 2001 From: Alex Suykov Date: Wed, 9 Sep 2020 23:47:58 +0300 Subject: [PATCH 076/503] Fix reg_offset handling in stlink_usb_read_all_regs --- src/stlink-lib/usb.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/stlink-lib/usb.c b/src/stlink-lib/usb.c index f9b4775f3..9726ddc4a 100644 --- a/src/stlink-lib/usb.c +++ b/src/stlink-lib/usb.c @@ -754,7 +754,7 @@ int _stlink_usb_read_all_regs(stlink_t *sl, struct stlink_reg *regp) { sl->q_len = (int)size; stlink_print_data(sl); - for (i = reg_offset; i < 16; i++) regp->r[i] = read_uint32(sl->q_buf, i * 4); + for (i = 0; i < 16; i++) regp->r[i] = read_uint32(sl->q_buf, reg_offset + i * 4); regp->xpsr = read_uint32(sl->q_buf, reg_offset + 64); regp->main_sp = read_uint32(sl->q_buf, reg_offset + 68); From bf41f1404562ac5b632edd31bc4ba9afcf2f33d8 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 20 Sep 2020 14:26:26 +0200 Subject: [PATCH 077/503] General Project Update - Updated list of required packages - Fixed install path of stlink-gui.ui file - Minor fixes in compiling.md - Updated CHANGELOG.md --- CHANGELOG.md | 2 ++ doc/compiling.md | 7 +++-- doc/version_support.md | 52 +++++++++++++++++------------------ src/stlink-gui/CMakeLists.txt | 2 +- 4 files changed, 33 insertions(+), 30 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index 01e679b3c..d9dc64a11 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -26,6 +26,8 @@ Fixes: * Fix for static linking of libssp ([#973](https://github.com/stlink-org/stlink/pull/973), [#974](https://github.com/stlink-org/stlink/pull/974)) * Fixed connect under reset for st-flash and st-util ([#983](https://github.com/stlink-org/stlink/pull/983)) * Fix for mmap() size_t overflow in st-flash ([#988](https://github.com/stlink-org/stlink/pull/988), [#989](https://github.com/stlink-org/stlink/pull/989)) +* [regression] stlink-gui installation issue on Ubuntu-18.04 ([#1006](https://github.com/stlink-org/stlink/pull/1006)) +* st-util: wrong register values passed to gdb (st-link v2) ([#1026](https://github.com/stlink-org/stlink/pull/1026), [#1027](https://github.com/stlink-org/stlink/pull/1027)) v1.6.1 diff --git a/doc/compiling.md b/doc/compiling.md index 7f2ba698e..d8cb62ebb 100644 --- a/doc/compiling.md +++ b/doc/compiling.md @@ -159,7 +159,7 @@ The rules are located in the subdirectory `config/udev/rules.d` within the sourc Afterwards it may be necessary to reload the udev rules: ```sh -$ sudo cp -a config/udev/rules.d/. /etc/udev/rules.d +$ sudo cp -a config/udev/rules.d/* /etc/udev/rules.d/ $ sudo udevadm control --reload-rules $ sudo udevadm trigger ``` @@ -217,8 +217,9 @@ To do this with only one simple command, type: ### Building 1. Change into the project source directory: `cd stlink` -2. Run `make release` to create the _Release_ target -3. Run `make debug` to create the _Debug_ target (_optional_)
+2. Run `make clean` to clean remnants of any previous builds. +3. Run `make release` to create the _Release_ target +4. Run `make debug` to create the _Debug_ target (_optional_)
The debug target is only necessary in order to modify the sources and to run under a debugger. diff --git a/doc/version_support.md b/doc/version_support.md index 4076fb422..43c201101 100644 --- a/doc/version_support.md +++ b/doc/version_support.md @@ -28,39 +28,39 @@ NOTE: In order to use a STLINK/v1 programmer on macOS, versions 10.13, 10.14 or | Operating System | libusb
version | cmake
version | gtk-3
version | Notes | | --- | --- | --- | --- | --- | -| Alpine Edge | 1.0.23 | 3.17.0 | 3.24.18
gtk+3.0-dev | | -| ALT Linux Sisyphus | 1.0.23 | 3.17.0 | 3.24.18
libgtk+3-devel | | +| Alpine Edge | 1.0.23 | 3.17.0 | 3.99.0
gtk+3.0 | | +| ALT Linux Sisyphus | 1.0.23 | 3.17.0 | 3.24.18
libgtk+3 | | | Arch Linux | 1.0.23 | 3.17.0 | 3.24.18
gtk3 | | -| Fedora Rawhide | 1.0.23 | 3.17.0 | 3.24.18
gtk3-devel | | named `libusbx`, but
`libusb`-codebase is used | +| Fedora Rawhide | 1.0.23 | 3.17.0 | 3.24.18
gtk3 | | named `libusbx`, but
`libusb`-codebase is used | | KaOS | 1.0.23 | 3.17.0 | 3.24.18
gtk3 | | -| OpenMandriva Cooker | 1.0.23 | 3.17.0 | 3.24.18
libgtk+3.0-devel
lib64gtk+3.0-devel | | -| PCLinuxOS | 1.0.23
lib64usb1.0 | 3.17.0 | 3.24.18
lib64gtk+3.0-devel | | +| OpenMandriva Cooker | 1.0.23 | 3.17.0 | 3.24.18
libgtk+3.0
lib64gtk+3.0 | | +| PCLinuxOS | 1.0.23
lib64usb1.0 | 3.17.0 | 3.24.18
lib64gtk+3.0 | | | Slackware Current | 1.0.23 | 3.17.0 | 3.24.18
gtk+3 | | -| Solus | 1.0.23 | 3.16.5 | 3.24.16
libgtk-3-devel | | -| Debian Sid | 1.0.23 | 3.16.3 | 3.24.18
libgtk-3-dev | | -| OpenMandriva Lx 4.1 | 1.0.23 | 3.16.3 | 3.24.13
libgtk+3.0-devel
lib64gtk+3.0-devel | | -| Ubuntu 20.04 LTS (Focal Fossa) | 1.0.23 | 3.16.3 | 3.24.17
libgtk-3-dev | | -| openSUSE Tumbleweed | 1.0.23 | 3.16.2 | 3.24.16
gtk3-devel | | -| Alpine 3.11 | 1.0.23 | 3.15.5 | 3.24.13
gtk+3.0-dev | | -| Ubuntu 19.10 (Eoan Ermine) | 1.0.23 | 3.13.4 | 3.24.12
libgtk-3-dev | | -| Mageia Cauldron | 1.0.22 | 3.17.0 | 3.24.18
libgtk+3.0-devel
lib64gtk+3.0-devel | | +| Solus | 1.0.23 | 3.16.5 | 3.24.16
libgtk-3 | | +| Debian Sid | 1.0.23 | 3.16.3 | 3.24.18
libgtk-3 | | +| OpenMandriva Lx 4.1 | 1.0.23 | 3.16.3 | 3.24.13
libgtk+3.0
lib64gtk+3.0 | | +| Ubuntu 20.04 LTS (Focal Fossa) | 1.0.23 | 3.16.3 | 3.24.17
libgtk-3 | | +| openSUSE Tumbleweed | 1.0.23 | 3.16.2 | 3.24.16
gtk3 | | +| Alpine 3.11 | 1.0.23 | 3.15.5 | 3.24.13
gtk+3.0 | | +| Ubuntu 19.10 (Eoan Ermine) | 1.0.23 | 3.13.4 | 3.24.12
libgtk-3 | | +| Mageia Cauldron | 1.0.22 | 3.17.0 | 3.24.18
libgtk+3.0
lib64gtk+3.0 | | | NetBSD 9.0 | 1.0.22 | 3.16.1 | 3.24.12
gtk+3 | | | NetBSD 8.1 | 1.0.22 | 3.16.1 | 3.24.12
gtk+3 | | | NetBSD 7.2 | 1.0.22 | 3.16.1 | _N/A_ | | -| Alpine 3.10 | 1.0.22 | 3.14.5 | 3.24.8
gtk+3.0-dev | | -| Fedora 31 | 1.0.22 | 3.14.5 | 3.24.12
gtk3-devel | named `libusbx`, but
`libusb`-codebase is used | -| Mageia 7.1 | 1.0.22 | 3.14.3 | 3.24.8
libgtk+3.0-devel
lib64gtk+3.0-devel | | -| Fedora 30 | 1.0.22 | 3.14.2 | 3.24.8
gtk3-devel | named `libusbx`, but
`libusb`-codebase is used | -| Debian 10 (Buster) | 1.0.22 | 3.13.4 | 3.24.5
libgtk-3-dev | | -| Alpine 3.9 | 1.0.22 | 3.13.0 | 3.24.1
gtk+3.0-dev | | -| CentOS 8 | 1.0.22 | 3.11.4 | 3.22.30
gtk3-devel | named `libusbx`, but
`libusb`-codebase is used | -| openSUSE Leap 15.2 | 1.0.21 | 3.15.5 | 3.24.14
gtk3-devel | | -| openSUSE Leap 15.1 | 1.0.21 | 3.10.2 | 3.22.30
gtk3-devel | | -| Ubuntu 18.04 LTS (Bionic Beaver) | 1.0.21 | 3.10.2 | 3.22.30
libgtk-3-dev | | -| Debian 9 (Stretch) | 1.0.21 | 3.7.2 | 3.22.11
libgtk-3-dev | | +| Alpine 3.10 | 1.0.22 | 3.14.5 | 3.24.8
gtk+3.0 | | +| Fedora 31 | 1.0.22 | 3.14.5 | 3.24.12
gtk3 | named `libusbx`, but
`libusb`-codebase is used | +| Mageia 7.1 | 1.0.22 | 3.14.3 | 3.24.8
libgtk+3.0
lib64gtk+3.0 | | +| Fedora 30 | 1.0.22 | 3.14.2 | 3.24.8
gtk3 | named `libusbx`, but
`libusb`-codebase is used | +| Debian 10 (Buster) | 1.0.22 | 3.13.4 | 3.24.5
libgtk-3 | | +| Alpine 3.9 | 1.0.22 | 3.13.0 | 3.24.1
gtk+3.0 | | +| CentOS 8 | 1.0.22 | 3.11.4 | 3.22.30
gtk3 | named `libusbx`, but
`libusb`-codebase is used | +| openSUSE Leap 15.2 | 1.0.21 | 3.15.5 | 3.24.14
gtk3 | | +| openSUSE Leap 15.1 | 1.0.21 | 3.10.2 | 3.22.30
gtk3 | | +| Ubuntu 18.04 LTS (Bionic Beaver) | 1.0.21 | 3.10.2 | 3.22.30
libgtk-3 | | +| Debian 9 (Stretch) | 1.0.21 | 3.7.2 | 3.22.11
libgtk-3 | | | Slackware 14.2 | **1.0.20** | 3.5.2 | 3.18.9
gtk+3 | | -| Ubuntu 16.04 LTS (Xenial Xerus) | **1.0.20** | 3.5.1 | 3.18.9
libgtk-3-dev | | -| OpenMandriva Lx 3.0 | **1.0.20** | **3.4.2** | 3.18.9
libgtk+3.0-devel
lib64gtk+3.0-devel | | +| Ubuntu 16.04 LTS (Xenial Xerus) | **1.0.20** | 3.5.1 | 3.18.9
libgtk-3 | | +| OpenMandriva Lx 3.0 | **1.0.20** | **3.4.2** | 3.18.9
libgtk+3.0
lib64gtk+3.0 | | | FreeBSD 13 | **1.0.16** - 1.0.18 | 3.15.5 | 3.24.10
gtk3 | linux_libusb-13.0r358841
(integrated) | | FreeBSD 12 | **1.0.16** - 1.0.18 | 3.15.5 | 3.24.10
gtk3 | linux_libusb-11.0r261448_4
(integrated) | | FreeBSD 11 | **1.0.16** - 1.0.18 | 3.15.5 | 3.24.10
gtk3 | linux_libusb-11.0r261448_4
(integrated) | diff --git a/src/stlink-gui/CMakeLists.txt b/src/stlink-gui/CMakeLists.txt index 46224dddb..22a22f59d 100644 --- a/src/stlink-gui/CMakeLists.txt +++ b/src/stlink-gui/CMakeLists.txt @@ -35,7 +35,7 @@ if (NOT WIN32 AND NOT CMAKE_CROSSCOMPILING) add_executable(stlink-gui ${GUI_SOURCES}) install(FILES stlink-gui.ui DESTINATION ${CMAKE_INSTALL_DATAROOTDIR}/${PROJECT_NAME}) set_target_properties(stlink-gui PROPERTIES - COMPILE_DEFINITIONS STLINK_UI_DIR="${CMAKE_INSTALL_PREFIX}/${CMAKE_INSTALL_DATAROOTDIR}/${PROJECT_NAME}") + COMPILE_DEFINITIONS STLINK_UI_DIR="${CMAKE_INSTALL_FULL_DATAROOTDIR}/${PROJECT_NAME}") target_link_libraries(stlink-gui ${STLINK_LIB_SHARED} ${SSP_LIB} ${GTK3_LDFLAGS}) install(TARGETS stlink-gui DESTINATION ${CMAKE_INSTALL_BINDIR}) endif () From 304635af647843eed06b16c3cc5806d23cd4c2d0 Mon Sep 17 00:00:00 2001 From: Ant-ON Date: Sat, 26 Sep 2020 17:27:00 +0500 Subject: [PATCH 078/503] Using vl flashoader with all F1 series --- src/stlink-lib/flash_loader.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/stlink-lib/flash_loader.c b/src/stlink-lib/flash_loader.c index 0e79c3c0a..7de485ca3 100644 --- a/src/stlink-lib/flash_loader.c +++ b/src/stlink-lib/flash_loader.c @@ -237,6 +237,12 @@ int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* loader_size = sizeof(loader_code_stm32l); } else if (sl->core_id == STM32VL_CORE_ID || sl->chip_id == STLINK_CHIPID_STM32_F1_MEDIUM || + sl->chip_id == STLINK_CHIPID_STM32_F1_HIGH || + sl->chip_id == STLINK_CHIPID_STM32_F1_LOW || + sl->chip_id == STLINK_CHIPID_STM32_F1_VL_MEDIUM_LOW || + sl->chip_id == STLINK_CHIPID_STM32_F1_VL_HIGH || + sl->chip_id == STLINK_CHIPID_STM32_F1_XL || + sl->chip_id == STLINK_CHIPID_STM32_F1_CONN || sl->chip_id == STLINK_CHIPID_STM32_F3 || sl->chip_id == STLINK_CHIPID_STM32_F3_SMALL || sl->chip_id == STLINK_CHIPID_STM32_F303_HIGH || From 2a746afa8ba27d8ebf5d4d5b833aba5cc0641312 Mon Sep 17 00:00:00 2001 From: Timothy Lee Date: Thu, 8 Oct 2020 20:42:09 +1100 Subject: [PATCH 079/503] Increase STM32L0 option_size to 20 The FLASH_OPTR, FLASH_WRPROT1 and FLASH_WRPROT2 registers are spread across 20 option bytes. With the original option_size of 4, only the lower 16 bits of FLASH_OPTR could be modified. --- src/stlink-lib/chipid.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index 3763587e1..dc9f31e44 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -386,7 +386,7 @@ static const struct stlink_chipid_params devices[] = { .bootrom_base = 0x1ff0000, .bootrom_size = 0x1000, .option_base = STM32_L0_CATx_OPTION_BYTES_BASE, - .option_size = 4, + .option_size = 20, }, { // STM32L0x Category 5 @@ -400,7 +400,7 @@ static const struct stlink_chipid_params devices[] = { .bootrom_base = 0x1ff0000, .bootrom_size = 0x2000, .option_base = STM32_L0_CATx_OPTION_BYTES_BASE, - .option_size = 4, + .option_size = 20, }, { // STM32L0x Category 2 @@ -414,7 +414,7 @@ static const struct stlink_chipid_params devices[] = { .bootrom_base = 0x1ff0000, .bootrom_size = 0x1000, .option_base = STM32_L0_CATx_OPTION_BYTES_BASE, - .option_size = 4, + .option_size = 20, }, { // STM32F334, STM32F303x6/8, and STM32F328 From cdac31075590578ff67bbfd4221ab892d50fab42 Mon Sep 17 00:00:00 2001 From: Geert Stappers Date: Sat, 10 Oct 2020 22:10:42 +0200 Subject: [PATCH 080/503] [manual] Added st-info --probe example output To show what to expect: information about the ST-link and the target. Bumped date to this month and removed a trailing space. Modified: doc/man/st-info.md --- doc/man/st-info.md | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/doc/man/st-info.md b/doc/man/st-info.md index 94a430000..9164642f2 100644 --- a/doc/man/st-info.md +++ b/doc/man/st-info.md @@ -1,6 +1,6 @@ % st-flash(1) Open Source STMicroelectronics Stlink Tools | stlink % -% Feb 2018 +% Oct 2020 # NAME st-info - Provides information about connected STLink and STM32 devices @@ -15,7 +15,7 @@ st-info - Provides information about connected STLink and STM32 devices Provides information about connected STLink programmers and STM32 devices: Serial code, OpenOCD hla-serial, flash, page size, sram, chipid, description. -The STLink device to probe can be specified via the environment variable +The STLink device to probe can be specified via the environment variable STLINK_DEVICE on the format :. # OPTIONS @@ -52,6 +52,13 @@ STLINK_DEVICE on the format :. Display information about connected programmers and devices $ st-info --probe + Found 1 stlink programmers + serial: 303033413030323233343338353130323334333133393339 + hla-serial: "\x30\x30\x33\x41\x30\x30\x32\x32\x33\x34\x33\x38\x35\x31\x30\x32\x33\x34\x33\x31\x33\x39\x33\x39" + flash: 131072 (pagesize: 128) + sram: 20480 + chipid: 0x0447 + descr: L0xx Category 5 # SEE ALSO From 1c137bf07fb0e4e17acf73bb0229979971af7389 Mon Sep 17 00:00:00 2001 From: Timothy Lee Date: Wed, 14 Oct 2020 15:28:22 +1100 Subject: [PATCH 081/503] st-flash: respect --connect-under-reset option when opening USB connection --- src/st-flash/flash.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/st-flash/flash.c b/src/st-flash/flash.c index 9116f9c80..d8bd8772c 100644 --- a/src/st-flash/flash.c +++ b/src/st-flash/flash.c @@ -61,7 +61,9 @@ int main(int ac, char** av) { printf("st-flash %s\n", STLINK_VERSION); - sl = stlink_open_usb(o.log_level, 1, (char *)o.serial, o.freq); + sl = stlink_open_usb(o.log_level, + o.connect_under_reset ? 2 : 1, + (char *)o.serial, o.freq); if (sl == NULL) { return(-1); } From e8254501a1ce4832c3df9511180ffd6860446353 Mon Sep 17 00:00:00 2001 From: Timothy Lee Date: Sun, 18 Oct 2020 22:33:57 +1100 Subject: [PATCH 082/503] Add ability to identify STM32H742/743/753 --- inc/stlink.h | 3 ++- src/common.c | 5 +++++ src/stlink-lib/chipid.c | 11 +++++++++++ src/stlink-lib/chipid.h | 1 + 4 files changed, 19 insertions(+), 1 deletion(-) diff --git a/inc/stlink.h b/inc/stlink.h index 1566a0bd6..39f5f283c 100644 --- a/inc/stlink.h +++ b/inc/stlink.h @@ -126,7 +126,8 @@ enum stlink_flash_type { STLINK_FLASH_TYPE_L4, // l4, l4+ */ STLINK_FLASH_TYPE_G0, STLINK_FLASH_TYPE_G4, - STLINK_FLASH_TYPE_WB + STLINK_FLASH_TYPE_WB, + STLINK_FLASH_TYPE_H7, }; struct stlink_reg { diff --git a/src/common.c b/src/common.c index 86d2ca8ea..9aaae9073 100644 --- a/src/common.c +++ b/src/common.c @@ -1172,6 +1172,11 @@ int stlink_chip_id(stlink_t *sl, uint32_t *chip_id) { return(ret); } + if (*chip_id == 0) { + // STM32H7 chipid in 0x5c001000 (RM0433 pg3189) + ret = stlink_read_debug32(sl, 0x5c001000, chip_id); + } + if (*chip_id == 0) { // Try Corex M0 DBGMCU_IDCODE register address ret = stlink_read_debug32(sl, 0x40015800, chip_id); diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index dc9f31e44..a9fb5af9d 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -614,6 +614,17 @@ static const struct stlink_chipid_params devices[] = { .bootrom_base = 0x1fff0000, // see the memory map .bootrom_size = 0x7000 }, + { + // STM32H742/743/753 (from RM0433) + .chip_id = STLINK_CHIPID_STM32_H74XXX, + .description = "H742/743/753", + .flash_type = STLINK_FLASH_TYPE_H7, + .flash_size_reg = 0x1ff1e880, // "Flash size register" (pg3272) + .flash_pagesize = 0x20000, // 128k sector (pg147) + .sram_size = 0x20000, // 128k "DTCM" from Table 7 + .bootrom_base = 0x1ff00000, // "System memory" starting address from Table 7 + .bootrom_size = 0x20000 // "System memory" byte size in hex from Table 7 + }, { // unknown .chip_id = STLINK_CHIPID_UNKNOWN, diff --git a/src/stlink-lib/chipid.h b/src/stlink-lib/chipid.h index b591f0012..f717022ca 100644 --- a/src/stlink-lib/chipid.h +++ b/src/stlink-lib/chipid.h @@ -53,6 +53,7 @@ enum stlink_stm32_chipids { STLINK_CHIPID_STM32_L0_CAT5 = 0x447, STLINK_CHIPID_STM32_F0_CAN = 0x448, STLINK_CHIPID_STM32_F7 = 0x449, /* ID found on the NucleoF746ZG board */ + STLINK_CHIPID_STM32_H74XXX = 0x450, /* Found on page 3189 in the RM0433*/ STLINK_CHIPID_STM32_F7XXXX = 0x451, STLINK_CHIPID_STM32_F72XXX = 0x452, /* ID found on the NucleoF722ZE board */ STLINK_CHIPID_STM32_L011 = 0x457, From aada8fc2ddb56debe5900d4affd63e6fb352dc67 Mon Sep 17 00:00:00 2001 From: Timothy Lee Date: Sun, 18 Oct 2020 23:32:06 +1100 Subject: [PATCH 083/503] Support flashing of STM32H7xx --- src/common.c | 118 +++++++++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 109 insertions(+), 9 deletions(-) diff --git a/src/common.c b/src/common.c index 9aaae9073..26275c175 100644 --- a/src/common.c +++ b/src/common.c @@ -302,6 +302,22 @@ #define FLASH_F2_CR_SNB_MASK 0x78 #define FLASH_F2_SR_BSY 16 +// STM32H7xx +#define FLASH_H7_CR_LOCK 0 +#define FLASH_H7_CR_PG 1 +#define FLASH_H7_CR_SER 2 +#define FLASH_H7_CR_PSIZE 4 +#define FLASH_H7_CR_START 7 +#define FLASH_H7_CR_SNB 8 +#define FLASH_H7_CR_SNB_MASK 0x700 + +#define FLASH_H7_SR_QW 2 + +#define FLASH_H7_REGS_ADDR ((uint32_t)0x52002000) +#define FLASH_H7_KEYR1 (FLASH_H7_REGS_ADDR + 0x04) +#define FLASH_H7_CR1 (FLASH_H7_REGS_ADDR + 0x0c) +#define FLASH_H7_SR1 (FLASH_H7_REGS_ADDR + 0x10) + #define L1_WRITE_BLOCK_SIZE 0x80 #define L0_WRITE_BLOCK_SIZE 0x40 @@ -381,6 +397,8 @@ static inline uint32_t read_flash_cr(stlink_t *sl) { reg = STM32Gx_FLASH_CR; } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { reg = STM32WB_FLASH_CR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + reg = FLASH_H7_CR1; } else { reg = FLASH_CR; } @@ -431,6 +449,9 @@ static inline unsigned int is_flash_locked(stlink_t *sl) { } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { cr_reg = STM32WB_FLASH_CR; cr_lock_shift = STM32WB_FLASH_CR_LOCK; + } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + cr_reg = FLASH_H7_CR1; + cr_lock_shift = FLASH_H7_CR_LOCK; } else { ELOG("unsupported flash method, abort\n"); return(-1); @@ -467,6 +488,8 @@ static void unlock_flash(stlink_t *sl) { key_reg = STM32Gx_FLASH_KEYR; } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { key_reg = STM32WB_FLASH_KEYR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + key_reg = FLASH_H7_KEYR1; } else { ELOG("unsupported flash method, abort\n"); return; @@ -498,6 +521,7 @@ static int unlock_flash_if(stlink_t *sl) { static void lock_flash(stlink_t *sl) { uint32_t cr_lock_shift, cr_reg, n; + uint32_t cr_mask = 0xffffffffu; if (sl->flash_type == STLINK_FLASH_TYPE_F0 || sl->flash_type == STLINK_FLASH_TYPE_F1_XL) { @@ -522,12 +546,17 @@ static void lock_flash(stlink_t *sl) { } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { cr_reg = STM32WB_FLASH_CR; cr_lock_shift = STM32WB_FLASH_CR_LOCK; + } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + cr_reg = FLASH_H7_CR1; + cr_lock_shift = FLASH_H7_CR_LOCK; + cr_mask = ~(1u << FLASH_H7_CR_SER); } else { ELOG("unsupported flash method, abort\n"); return; } stlink_read_debug32(sl, cr_reg, &n); + n &= cr_mask; n |= (1u << cr_lock_shift); stlink_write_debug32(sl, cr_reg, n); @@ -724,6 +753,9 @@ static void set_flash_cr_pg(stlink_t *sl) { } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { cr_reg = STM32WB_FLASH_CR; x |= (1 << FLASH_CR_PG); + } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + cr_reg = FLASH_H7_CR1; + x |= (1 << FLASH_H7_CR_PG); } else { cr_reg = FLASH_CR; x = (1 << FLASH_CR_PG); @@ -902,6 +934,9 @@ static void set_flash_cr_strt(stlink_t *sl) { } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { cr_reg = STM32WB_FLASH_CR; cr_strt = (1 << STM32WB_FLASH_CR_STRT); + } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + cr_reg = FLASH_H7_CR1; + cr_strt = 1 << FLASH_H7_CR_START; } else { cr_reg = FLASH_CR; cr_strt = (1 << FLASH_CR_STRT); @@ -939,6 +974,8 @@ static inline uint32_t read_flash_sr(stlink_t *sl) { sr_reg = STM32Gx_FLASH_SR; } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { sr_reg = STM32WB_FLASH_SR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + sr_reg = FLASH_H7_SR1; } else { ELOG("unsupported flash method, abort"); return(-1); @@ -973,6 +1010,8 @@ static inline unsigned int is_flash_busy(stlink_t *sl) { sr_busy_shift = STM32Gx_FLASH_SR_BSY; } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { sr_busy_shift = STM32WB_FLASH_SR_BSY; + } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + sr_busy_shift = FLASH_H7_SR_QW; } else { ELOG("unsupported flash method, abort"); return(-1); @@ -1064,25 +1103,48 @@ static inline void write_flash_ar2(stlink_t *sl, uint32_t n) { } static inline void write_flash_cr_psiz(stlink_t *sl, uint32_t n) { + uint32_t cr_reg, psize_shift; uint32_t x = read_flash_cr(sl); - x &= ~(0x03 << 8); - x |= (n << 8); + + if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + cr_reg = FLASH_H7_CR1; + psize_shift = FLASH_H7_CR_PSIZE; + } else { + cr_reg = FLASH_F4_CR; + psize_shift = 8; + } + + x &= ~(0x03 << psize_shift); + x |= (n << psize_shift); #if DEBUG_FLASH fprintf(stdout, "PSIZ:0x%x 0x%x\n", x, n); #endif - stlink_write_debug32(sl, FLASH_F4_CR, x); + stlink_write_debug32(sl, cr_reg, x); } - static inline void write_flash_cr_snb(stlink_t *sl, uint32_t n) { + uint32_t cr_reg, snb_mask, snb_shift, ser_shift; uint32_t x = read_flash_cr(sl); - x &= ~FLASH_F4_CR_SNB_MASK; - x |= (n << FLASH_F4_CR_SNB); - x |= (1 << FLASH_F4_CR_SER); + + if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + cr_reg = FLASH_H7_CR1; + snb_mask = FLASH_H7_CR_SNB_MASK; + snb_shift = FLASH_H7_CR_SNB; + ser_shift = FLASH_H7_CR_SER; + } else { + cr_reg = FLASH_F4_CR; + snb_mask = FLASH_F4_CR_SNB_MASK; + snb_shift = FLASH_F4_CR_SNB; + ser_shift = FLASH_F4_CR_SER; + } + + x &= ~snb_mask; + x |= (n << snb_shift); + x |= (1 << ser_shift); #if DEBUG_FLASH fprintf(stdout, "SNB:0x%x 0x%x\n", x, n); #endif - stlink_write_debug32(sl, FLASH_F4_CR, x); + stlink_write_debug32(sl, cr_reg, x); } static inline void write_flash_cr_bker_pnb(stlink_t *sl, uint32_t n) { @@ -2141,6 +2203,11 @@ uint32_t calculate_F7_sectornum(uint32_t flashaddr) { } +uint32_t calculate_H7_sectornum(uint32_t flashaddr) { + flashaddr &= ~STM32_FLASH_BASE; // sector holding the flash address + return(flashaddr / 0x20000); +} + // returns BKER:PNB for the given page address uint32_t calculate_L4_page(stlink_t *sl, uint32_t flashaddr) { uint32_t bker = 0; @@ -2214,7 +2281,8 @@ uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr) { int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { if (sl->flash_type == STLINK_FLASH_TYPE_F4 || sl->flash_type == STLINK_FLASH_TYPE_F7 || - sl->flash_type == STLINK_FLASH_TYPE_L4) { + sl->flash_type == STLINK_FLASH_TYPE_L4 || + sl->flash_type == STLINK_FLASH_TYPE_H7) { // wait for ongoing op to finish wait_flash_busy(sl); @@ -2239,6 +2307,13 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { // calculate the actual page from the address uint32_t sector = calculate_F7_sectornum(flashaddr); + fprintf(stderr, "EraseFlash - Sector:0x%x Size:0x%x ", + sector, stlink_calculate_pagesize(sl, flashaddr)); + write_flash_cr_snb(sl, sector); + } else if (sl->chip_id == STLINK_CHIPID_STM32_H74XXX) { + // calculate the actual page from the address + uint32_t sector = calculate_H7_sectornum(flashaddr); + fprintf(stderr, "EraseFlash - Sector:0x%x Size:0x%x ", sector, stlink_calculate_pagesize(sl, flashaddr)); write_flash_cr_snb(sl, sector); @@ -2854,6 +2929,31 @@ int stlink_write_flash( } fprintf(stdout, "\n"); + } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + ILOG("Starting Flash write for H7 core id\n"); + + unlock_flash_if(sl); // unlock the cr + set_flash_cr_pg(sl); // set programming mode + + for (off = 0; off < len;) { + // Program STM32H7x with 32-byte Flash words + size_t chunk = (len - off > 32) ? 32 : len - off; + memcpy(sl->q_buf, base + off, chunk); + stlink_write_mem32(sl, addr + (uint32_t)off, 32); + wait_flash_busy(sl); + + off += chunk; + + if (sl->verbose >= 1) { + // show progress + fprintf(stdout, "\r%u/%u bytes written", (unsigned int)off, (unsigned int)len); + fflush(stdout); + } + } + fprintf(stdout, "\n"); + + clear_flash_cr_pg(sl); + lock_flash(sl); } else { ELOG("unknown coreid, not sure how to write: %x\n", sl->core_id); return(-1); From bbc2b5417174418c597abc75755b12c11aee8f9a Mon Sep 17 00:00:00 2001 From: Timothy Lee Date: Mon, 19 Oct 2020 23:29:54 +1100 Subject: [PATCH 084/503] [feature] support STM32H7 option bytes --- inc/stm32.h | 1 + src/common.c | 95 +++++++++++++++++++++++++++++++++++++++++ src/stlink-lib/chipid.c | 4 +- 3 files changed, 99 insertions(+), 1 deletion(-) diff --git a/inc/stm32.h b/inc/stm32.h index 96836c9b7..1773e703b 100644 --- a/inc/stm32.h +++ b/inc/stm32.h @@ -21,5 +21,6 @@ #define STM32_L4_OPTION_BYTES_BASE ((uint32_t)0x1FFF7800) #define STM32_L1_OPTION_BYTES_BASE ((uint32_t)0x1FF80000) #define STM32_F7_OPTION_BYTES_BASE ((uint32_t)0x1FFF0000) +#define STM32_H7_OPTION_BYTES_BASE ((uint32_t)0x5200201C) #endif // STM32_H diff --git a/src/common.c b/src/common.c index 26275c175..a08db2733 100644 --- a/src/common.c +++ b/src/common.c @@ -313,10 +313,23 @@ #define FLASH_H7_SR_QW 2 +#define FLASH_H7_OPTCR_OPTLOCK 0 +#define FLASH_H7_OPTCR_OPTSTART 1 +#define FLASH_H7_OPTCR_MER 4 + +#define FLASH_H7_OPTSR_OPT_BUSY 0 +#define FLASH_H7_OPTSR_OPTCHANGEERR 30 + +#define FLASH_H7_OPTCCR_CLR_OPTCHANGEERR 30 + #define FLASH_H7_REGS_ADDR ((uint32_t)0x52002000) #define FLASH_H7_KEYR1 (FLASH_H7_REGS_ADDR + 0x04) +#define FLASH_H7_OPT_KEYR (FLASH_H7_REGS_ADDR + 0x08) #define FLASH_H7_CR1 (FLASH_H7_REGS_ADDR + 0x0c) #define FLASH_H7_SR1 (FLASH_H7_REGS_ADDR + 0x10) +#define FLASH_H7_OPTCR (FLASH_H7_REGS_ADDR + 0x18) +#define FLASH_H7_OPTSR_CUR (FLASH_H7_REGS_ADDR + 0x1c) +#define FLASH_H7_OPTCCR (FLASH_H7_REGS_ADDR + 0x24) #define L1_WRITE_BLOCK_SIZE 0x80 #define L0_WRITE_BLOCK_SIZE 0x40 @@ -603,6 +616,10 @@ static bool is_flash_option_locked(stlink_t *sl) { optcr_reg = STM32WB_FLASH_CR; optlock_shift = STM32WB_FLASH_CR_OPTLOCK; break; + case STLINK_FLASH_TYPE_H7: + optcr_reg = FLASH_H7_OPTCR; + optlock_shift = FLASH_H7_OPTCR_OPTLOCK; + break; default: ELOG("unsupported flash method, abort\n"); return -1; @@ -654,6 +671,10 @@ static int lock_flash_option(stlink_t *sl) { optcr_reg = STM32WB_FLASH_CR; optlock_shift = STM32WB_FLASH_CR_OPTLOCK; break; + case STLINK_FLASH_TYPE_H7: + optcr_reg = FLASH_H7_OPTCR; + optlock_shift = FLASH_H7_OPTCR_OPTLOCK; + break; default: ELOG("unsupported flash method, abort\n"); return -1; @@ -704,6 +725,9 @@ static int unlock_flash_option(stlink_t *sl) { case STLINK_FLASH_TYPE_WB: optkey_reg = STM32WB_FLASH_OPT_KEYR; break; + case STLINK_FLASH_TYPE_H7: + optkey_reg = FLASH_H7_OPT_KEYR; + break; default: ELOG("unsupported flash method, abort\n"); return(-1); @@ -3413,6 +3437,74 @@ static int stlink_write_option_bytes_f7(stlink_t *sl, uint8_t* base, stm32_addr_ return ret; } +/** + * Write STM32H7xx option bytes + * @param sl + * @param base option bytes to write + * @param addr of the memory mapped option bytes + * @param len number of bytes to write (must be multiple of 4) + * @return 0 on success, -ve on failure. + */ +static int stlink_write_option_bytes_h7( + stlink_t *sl, uint8_t* base, stm32_addr_t addr, uint32_t len) { + uint32_t val; + uint32_t data; + + // Wait until previous flash option has completed + wait_flash_busy(sl); + + // Clear previous error + stlink_write_debug32(sl, FLASH_H7_OPTCCR, 1 << FLASH_H7_OPTCCR_CLR_OPTCHANGEERR); + + while (len != 0) { + switch (addr) { + case FLASH_H7_REGS_ADDR + 0x20: // FLASH_OPTSR_PRG + case FLASH_H7_REGS_ADDR + 0x2c: // FLASH_PRAR_PRG1 + case FLASH_H7_REGS_ADDR + 0x34: // FLASH_SCAR_PRG1 + case FLASH_H7_REGS_ADDR + 0x3c: // FLASH_WPSN_PRG1 + case FLASH_H7_REGS_ADDR + 0x44: // FLASH_BOOT_PRG + /* Write to FLASH_xxx_PRG registers */ + write_uint32((unsigned char*)&data, *(uint32_t*)(base)); // write options bytes + + WLOG("Writing option bytes %#10x to %#10x\n", data, addr); + + /* Skip if the value in the CUR register is identical */ + stlink_read_debug32(sl, addr - 4, &val); + if (val == data) { + break; + } + + /* Write new option byte values and start modification */ + stlink_write_debug32(sl, addr, data); + stlink_read_debug32(sl, FLASH_H7_OPTCR, &val); + val |= (1 << FLASH_H7_OPTCR_OPTSTART); + stlink_write_debug32(sl, FLASH_H7_OPTCR, val); + + /* Wait for the option bytes modification to complete */ + do { + stlink_read_debug32(sl, FLASH_H7_OPTSR_CUR, &val); + } while ((val & (1 << FLASH_H7_OPTSR_OPT_BUSY)) != 0); + + /* Check for errors */ + if ((val & (1 << FLASH_H7_OPTSR_OPTCHANGEERR)) != 0) { + stlink_write_debug32(sl, FLASH_H7_OPTCCR, 1 << FLASH_H7_OPTCCR_CLR_OPTCHANGEERR); + return -1; + } + break; + + default: + /* Skip non-programmable registers */ + break; + } + + len -= 4; + addr += 4; + base += 4; + } + + return 0; +} + /** * Read option bytes * @param sl @@ -3735,6 +3827,9 @@ int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t* base, ui case STLINK_FLASH_TYPE_G4: ret = stlink_write_option_bytes_gx(sl, base, addr, len); break; + case STLINK_FLASH_TYPE_H7: + ret = stlink_write_option_bytes_h7(sl, base, addr, len); + break; default: ELOG("Option bytes writing is currently not implemented for connected chip\n"); break; diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index a9fb5af9d..c191fa919 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -623,7 +623,9 @@ static const struct stlink_chipid_params devices[] = { .flash_pagesize = 0x20000, // 128k sector (pg147) .sram_size = 0x20000, // 128k "DTCM" from Table 7 .bootrom_base = 0x1ff00000, // "System memory" starting address from Table 7 - .bootrom_size = 0x20000 // "System memory" byte size in hex from Table 7 + .bootrom_size = 0x20000, // "System memory" byte size in hex from Table 7 + .option_base = STM32_H7_OPTION_BYTES_BASE, + .option_size = 44, // FLASH_OPTSR_CUR to FLASH_BOOT_PRGR from Table 28 }, { // unknown From 781557dfba15d6539ccf85e2a385e4004af875a8 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sat, 24 Oct 2020 18:06:56 +0200 Subject: [PATCH 085/503] Removed outdated debian configuration Debian package build uses cmake environment. --- cmake/packaging/cpack_config.cmake | 2 +- debian/.gitignore | 10 -- debian/changelog | 74 --------------- debian/control | 44 --------- debian/copyright | 37 -------- debian/gbp.conf | 7 -- debian/libstlink-dev.install | 4 - debian/libstlink1.install | 1 - debian/libstlink1.symbols | 141 ----------------------------- debian/patches/guipath.patch | 11 --- debian/patches/series | 1 - debian/rules | 23 ----- debian/source/format | 1 - debian/source/options | 1 - debian/stlink-gui.install | 4 - debian/stlink-tools.install | 3 - debian/stlink-tools.manpages | 3 - debian/stlink.pc.in | 10 -- debian/watch | 3 - 19 files changed, 1 insertion(+), 379 deletions(-) delete mode 100644 debian/.gitignore delete mode 100644 debian/changelog delete mode 100644 debian/control delete mode 100644 debian/copyright delete mode 100644 debian/gbp.conf delete mode 100644 debian/libstlink-dev.install delete mode 100644 debian/libstlink1.install delete mode 100644 debian/libstlink1.symbols delete mode 100644 debian/patches/guipath.patch delete mode 100644 debian/patches/series delete mode 100755 debian/rules delete mode 100644 debian/source/format delete mode 100644 debian/source/options delete mode 100644 debian/stlink-gui.install delete mode 100644 debian/stlink-tools.install delete mode 100644 debian/stlink-tools.manpages delete mode 100644 debian/stlink.pc.in delete mode 100644 debian/watch diff --git a/cmake/packaging/cpack_config.cmake b/cmake/packaging/cpack_config.cmake index 469e743ca..acd5630fa 100644 --- a/cmake/packaging/cpack_config.cmake +++ b/cmake/packaging/cpack_config.cmake @@ -54,7 +54,7 @@ elseif (EXISTS "/etc/debian_version" AND NOT EXISTS WIN32) # Package-build is av # CPACK_DEBIAN_PACKAGE_ARCHITECTURE --> Default: Output of dpkg --print-architecture set(CPACK_DEBIAN_PACKAGE_DEPENDS "pkg-config, build-essential, debhelper (>=9), cmake (>= 3.4.2), libusb-1.0-0-dev (>= 1.0.20)") - set(CPACK_DEBIAN_PACKAGE_MAINTAINER "Luca Boccassi ") + set(CPACK_DEBIAN_PACKAGE_MAINTAINER "Nightwalker-87 ") # CPACK_DEBIAN_PACKAGE_DESCRIPTION --> Default: CPACK_DEBIAN_PACKAGE_DESCRIPTION (as it is set) # CPACK_DEBIAN_PACKAGE_SECTION --> Default: “devel” # CPACK_DEBIAN_ARCHIVE_TYPE --> Default: “gnutar” diff --git a/debian/.gitignore b/debian/.gitignore deleted file mode 100644 index 7624d1c9b..000000000 --- a/debian/.gitignore +++ /dev/null @@ -1,10 +0,0 @@ -.debhelper -files -debhelper-build-stamp -*.log -*.substvars -libstlink-dev -libstlink -stlink-gui -stlink-tools -tmp diff --git a/debian/changelog b/debian/changelog deleted file mode 100644 index c54850340..000000000 --- a/debian/changelog +++ /dev/null @@ -1,74 +0,0 @@ -stlink (1.6.1+ds-2) unstable; urgency=medium - - * Update d/copyright to remove GPL-2+ stanza about flashloaders - * Update upstream URLs for new Github org - * Patch CMake's hard-coded define of XML gui file location (Closes: - #963219) - - -- Luca Boccassi Sun, 21 Jun 2020 13:41:37 +0100 - -stlink (1.6.1+ds-1) unstable; urgency=medium - - * Merge tag 'v1.6.1' into debian - * Update Files-Excluded in d/copyright for new layout - * Fix d/watch intermediary file name - * Drop cross.patch, merged upstream in v1.6.1 - * Bump Build-Depends to cmake >= 3.4.2 - * Add new symbols from upstream version 1.6.1 - * Adjust install files, some files moved - * Remove unused variable from d/rules - * Generate pkgconfig file from d/rules, upstream doesn't do it - * Switch to debhelper-compat 12 - - -- Luca Boccassi Sat, 06 Jun 2020 14:44:54 +0100 - -stlink (1.6.0+ds-1) unstable; urgency=medium - - * Merge tag 'v1.6.0' into debian - * Bump Standards-Version to 4.5.0, no changes. - * Update libstlink1 symbols file for 1.6.0. - - -- Luca Boccassi Tue, 25 Feb 2020 22:08:33 +0000 - -stlink (1.5.1+ds-2) unstable; urgency=medium - - * Mark library packages as Multi-Arch: same. - * Apply cross.patch to fix cross-compiling the GUI. Thanks Helmut for - the patch! (Closes: #941320) - * Vcs-Git: add -b debian - * Set Rules-Requires-Root: no - * Bump Standards-Version to 4.4.0 - - -- Luca Boccassi Sun, 29 Sep 2019 12:50:58 +0100 - -stlink (1.5.1+ds-1) unstable; urgency=medium - - * Merge tag 'v1.5.1' into debian. See upstream changelog for info: - https://github.com/stlink-org/stlink/releases/tag/v1.5.1 - * Mark packages as linux-any, other systems not supported. - - -- Luca Boccassi Fri, 28 Sep 2018 10:26:39 +0100 - -stlink (1.5.0+ds-1) unstable; urgency=medium - - * Upload to unstable. (Closes: #869421) - - -- Luca Boccassi Fri, 16 Mar 2018 16:56:17 +0000 - -stlink (1.4.0) unstable; urgency=low - - -- Andrew 'Necromant' Andrianov Sat, 01 Jul 2017 00:00:00 +0000 - -stlink (1.3.1) unstable; urgency=low - - -- Andrew 'Necromant' Andrianov Sat, 25 Feb 2017 00:00:00 +0000 - -stlink (1.3.0) unstable; urgency=low - - -- Andrew 'Necromant' Andrianov Sat, 28 Jan 2017 00:00:00 +0000 - -stlink (1.2.1) unstable; urgency=low - - * Initial Debian-Packaged Release. - - -- Andrew 'Necromant' Andrianov Sat, 09 Jul 2016 23:16:07 +0300 diff --git a/debian/control b/debian/control deleted file mode 100644 index 598e0e89f..000000000 --- a/debian/control +++ /dev/null @@ -1,44 +0,0 @@ -Source: stlink -Priority: optional -Maintainer: Luca Boccassi -Build-Depends: debhelper-compat (= 12), cmake (>= 3.4.2), libusb-1.0-0-dev, libgtk-3-dev -Standards-Version: 4.5.0 -Rules-Requires-Root: no -Section: electronics -Homepage: https://github.com/stlink-org/stlink -Vcs-Git: https://github.com/bluca/stlink.git -b debian -Vcs-Browser: https://github.com/bluca/stlink - -Package: libstlink-dev -Section: libdevel -Architecture: linux-any -Multi-Arch: same -Depends: libstlink1 (= ${binary:Version}), ${misc:Depends} -Description: Open source STM32 MCU programming toolset. - . - This package contains the development files for stlink. - -Package: libstlink1 -Section: libs -Architecture: linux-any -Multi-Arch: same -Depends: ${shlibs:Depends}, ${misc:Depends} -Description: Open source STM32 MCU programming toolset. - . - This package contains the shared library for stlink. - -Package: stlink-tools -Architecture: linux-any -Depends: libstlink1 (= ${binary:Version}), ${shlibs:Depends}, ${misc:Depends} -Description: Open source STM32 MCU programming toolset. - . - This package contains commandline utilities for stlink, modprobe- and - udev-rules. - -Package: stlink-gui -Architecture: linux-any -Depends: libstlink1 (= ${binary:Version}), stlink-tools (= ${binary:Version}), - ${shlibs:Depends}, ${misc:Depends} -Description: Open source STM32 MCU programming toolset. - . - This package contains a GUI for stlink. diff --git a/debian/copyright b/debian/copyright deleted file mode 100644 index 8329cc250..000000000 --- a/debian/copyright +++ /dev/null @@ -1,37 +0,0 @@ -Format: https://www.debian.org/doc/packaging-manuals/copyright-format/1.0/ -Upstream-Name: stlink -Upstream-Contact: Luca Boccassi -Source: https://github.com/stlink-org/stlink -Files-Excluded: stlinkv1_macos_driver - -Files: * -Copyright: 2011-2020 stlink-org - Martin Capitanio [capnm] - Fabien Le Mentec [texane] - Jerry Jacobs [xor-gate] - [Nightwalker-87] - and many others... - An extended list of contributors can be found in "contributors.txt". -License: BSD-3-clause - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - . - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its - contributors may be used to endorse or promote products derived from - this software without specific prior written permission. - . - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. diff --git a/debian/gbp.conf b/debian/gbp.conf deleted file mode 100644 index 418e536e9..000000000 --- a/debian/gbp.conf +++ /dev/null @@ -1,7 +0,0 @@ -[buildpackage] -upstream-tag = %(version)s -debian-branch = debian - -[dch] -git-log = --first-parent -customizations = /usr/share/doc/git-buildpackage/examples/wrap_cl.py diff --git a/debian/libstlink-dev.install b/debian/libstlink-dev.install deleted file mode 100644 index 4e0e0d184..000000000 --- a/debian/libstlink-dev.install +++ /dev/null @@ -1,4 +0,0 @@ -usr/include/* -usr/lib/*/lib*.a -usr/lib/*/pkgconfig/* -usr/lib/*/lib*.so diff --git a/debian/libstlink1.install b/debian/libstlink1.install deleted file mode 100644 index 3ddde5841..000000000 --- a/debian/libstlink1.install +++ /dev/null @@ -1 +0,0 @@ -usr/lib/*/lib*.so.* diff --git a/debian/libstlink1.symbols b/debian/libstlink1.symbols deleted file mode 100644 index 159f27d0f..000000000 --- a/debian/libstlink1.symbols +++ /dev/null @@ -1,141 +0,0 @@ -libstlink.so.1 libstlink1 #MINVER# - Md5Calculate@Base 1.6.1 - Md5Finalise@Base 1.6.1 - Md5Initialise@Base 1.6.1 - Md5Update@Base 1.6.1 - _parse_version@Base 1.5.0 - _stlink_sg_close@Base 1.5.0 - _stlink_sg_core_id@Base 1.5.0 - _stlink_sg_current_mode@Base 1.5.0 - _stlink_sg_enter_jtag_mode@Base 1.5.0 - _stlink_sg_enter_swd_mode@Base 1.5.0 - _stlink_sg_exit_debug_mode@Base 1.5.0 - _stlink_sg_exit_dfu_mode@Base 1.5.0 - _stlink_sg_force_debug@Base 1.5.0 - _stlink_sg_jtag_reset@Base 1.5.0 - _stlink_sg_read_all_regs@Base 1.5.0 - _stlink_sg_read_debug32@Base 1.5.0 - _stlink_sg_read_mem32@Base 1.5.0 - _stlink_sg_read_reg@Base 1.5.0 - _stlink_sg_reset@Base 1.5.0 - _stlink_sg_run@Base 1.5.0 - _stlink_sg_status@Base 1.5.0 - _stlink_sg_step@Base 1.5.0 - _stlink_sg_version@Base 1.5.0 - _stlink_sg_write_debug32@Base 1.5.0 - _stlink_sg_write_mem32@Base 1.5.0 - _stlink_sg_write_mem8@Base 1.5.0 - _stlink_sg_write_reg@Base 1.5.0 - _stlink_usb_close@Base 1.5.0 - _stlink_usb_core_id@Base 1.5.0 - _stlink_usb_current_mode@Base 1.5.0 - _stlink_usb_enter_swd_mode@Base 1.5.0 - _stlink_usb_exit_debug_mode@Base 1.5.0 - _stlink_usb_exit_dfu_mode@Base 1.5.0 - _stlink_usb_force_debug@Base 1.5.0 - _stlink_usb_get_rw_status@Base 1.6.1 - _stlink_usb_jtag_reset@Base 1.5.0 - _stlink_usb_read_all_regs@Base 1.5.0 - _stlink_usb_read_all_unsupported_regs@Base 1.5.0 - _stlink_usb_read_debug32@Base 1.5.0 - _stlink_usb_read_mem32@Base 1.5.0 - _stlink_usb_read_reg@Base 1.5.0 - _stlink_usb_read_unsupported_reg@Base 1.5.0 - _stlink_usb_reset@Base 1.5.0 - _stlink_usb_run@Base 1.5.0 - _stlink_usb_set_swdclk@Base 1.5.0 - _stlink_usb_status@Base 1.5.0 - _stlink_usb_status_v2@Base 1.6.1 - _stlink_usb_step@Base 1.5.0 - _stlink_usb_target_voltage@Base 1.5.0 - _stlink_usb_version@Base 1.5.0 - _stlink_usb_write_debug32@Base 1.5.0 - _stlink_usb_write_mem32@Base 1.5.0 - _stlink_usb_write_mem8@Base 1.5.0 - _stlink_usb_write_reg@Base 1.5.0 - _stlink_usb_write_unsupported_reg@Base 1.5.0 - calculate_F4_sectornum@Base 1.5.0 - calculate_F7_sectornum@Base 1.5.0 - calculate_L4_page@Base 1.5.0 - is_bigendian@Base 1.5.0 - read_uint16@Base 1.5.0 - read_uint32@Base 1.5.0 - send_recv@Base 1.5.0 - send_usb_data_only@Base 1.5.0 - send_usb_mass_storage_command@Base 1.5.0 - stlink_calculate_pagesize@Base 1.5.0 - stlink_chip_id@Base 1.5.0 - stlink_chipid_get_params@Base 1.5.0 - stlink_close@Base 1.5.0 - stlink_clr_hw_bp@Base 1.5.0 - stlink_core_id@Base 1.5.0 - stlink_core_stat@Base 1.5.0 - stlink_cpu_id@Base 1.5.0 - stlink_current_mode@Base 1.5.0 - stlink_enter_swd_mode@Base 1.5.0 - stlink_erase_flash_mass@Base 1.5.0 - stlink_erase_flash_page@Base 1.5.0 - stlink_exit_debug_mode@Base 1.5.0 - stlink_exit_dfu_mode@Base 1.5.0 - stlink_fcheck_flash@Base 1.5.0 - stlink_flash_loader_init@Base 1.5.0 - stlink_flash_loader_run@Base 1.5.0 - stlink_flash_loader_write_to_sram@Base 1.5.0 - stlink_force_debug@Base 1.5.0 - stlink_fread@Base 1.5.0 - stlink_fwrite_flash@Base 1.5.0 - stlink_fwrite_option_bytes@Base 1.6.0 -#MISSING: 1.6.1# stlink_fwrite_option_bytes_32bit@Base 1.6.0 - stlink_fwrite_sram@Base 1.5.0 - stlink_get_erased_pattern@Base 1.5.0 - stlink_is_core_halted@Base 1.5.0 - stlink_jtag_reset@Base 1.5.0 - stlink_load_device_params@Base 1.5.0 - stlink_mwrite_flash@Base 1.5.0 - stlink_mwrite_sram@Base 1.5.0 - stlink_open_usb@Base 1.5.0 - stlink_parse_ihex@Base 1.5.0 - stlink_print_data@Base 1.5.0 - stlink_probe_usb@Base 1.5.0 - stlink_probe_usb_free@Base 1.5.0 - stlink_q@Base 1.5.0 - stlink_read_all_regs@Base 1.5.0 - stlink_read_all_unsupported_regs@Base 1.5.0 - stlink_read_debug32@Base 1.5.0 - stlink_read_mem32@Base 1.5.0 - stlink_read_option_bytes32@Base 1.6.1 - stlink_read_option_bytes_Gx@Base 1.6.1 - stlink_read_option_bytes_f2@Base 1.6.0 - stlink_read_option_bytes_f4@Base 1.6.0 - stlink_read_option_bytes_generic@Base 1.6.1 - stlink_read_reg@Base 1.5.0 - stlink_read_unsupported_reg@Base 1.5.0 - stlink_reset@Base 1.5.0 - stlink_run@Base 1.5.0 - stlink_run_at@Base 1.5.0 - stlink_set_hw_bp@Base 1.5.0 - stlink_set_swdclk@Base 1.5.0 - stlink_stat@Base 1.5.0 - stlink_status@Base 1.5.0 - stlink_step@Base 1.5.0 - stlink_target_voltage@Base 1.5.0 - stlink_v1_open@Base 1.5.0 - stlink_v1_open_inner@Base 1.5.0 - stlink_verify_write_flash@Base 1.5.0 - stlink_version@Base 1.5.0 - stlink_write_debug32@Base 1.5.0 - stlink_write_dreg@Base 1.5.0 - stlink_write_flash@Base 1.5.0 - stlink_write_mem32@Base 1.5.0 - stlink_write_mem8@Base 1.5.0 - stlink_write_option_bytes32@Base 1.6.1 - stlink_write_option_bytes@Base 1.6.0 - stlink_write_reg@Base 1.5.0 - stlink_write_unsupported_reg@Base 1.5.0 - stm32l1_write_half_pages@Base 1.5.0 - ugly_init@Base 1.5.0 - ugly_libusb_log_level@Base 1.6.1 - ugly_log@Base 1.5.0 - write_buffer_to_sram@Base 1.5.0 - write_uint16@Base 1.5.0 - write_uint32@Base 1.5.0 diff --git a/debian/patches/guipath.patch b/debian/patches/guipath.patch deleted file mode 100644 index d3effc92b..000000000 --- a/debian/patches/guipath.patch +++ /dev/null @@ -1,11 +0,0 @@ ---- a/src/stlink-gui/CMakeLists.txt -+++ b/src/stlink-gui/CMakeLists.txt -@@ -32,7 +32,7 @@ - add_executable(stlink-gui ${GUI_SOURCES}) - install(FILES stlink-gui.ui DESTINATION ${CMAKE_INSTALL_BINDIR}) - set_target_properties(stlink-gui PROPERTIES -- COMPILE_DEFINITIONS STLINK_UI_DIR="${CMAKE_INSTALL_PREFIX}/bin") -+ COMPILE_DEFINITIONS STLINK_UI_DIR="/usr/share/stlink") - target_link_libraries(stlink-gui ${STLINK_LIB_SHARED} ${SSP_LIB} ${GTK3_LDFLAGS}) - install(TARGETS stlink-gui DESTINATION ${CMAKE_INSTALL_BINDIR}) - diff --git a/debian/patches/series b/debian/patches/series deleted file mode 100644 index 1fdcf9977..000000000 --- a/debian/patches/series +++ /dev/null @@ -1 +0,0 @@ -guipath.patch diff --git a/debian/rules b/debian/rules deleted file mode 100755 index 512bd533f..000000000 --- a/debian/rules +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/make -f -# See debhelper(7) (uncomment to enable) -# output every command that modifies files on the build system. -#DH_VERBOSE = 1 - -# see EXAMPLES in dpkg-buildflags(1) and read /usr/share/dpkg/* -DPKG_EXPORT_BUILDFLAGS = 1 -include /usr/share/dpkg/default.mk - -# see FEATURE AREAS in dpkg-buildflags(1) -export DEB_BUILD_MAINT_OPTIONS = hardening=+all - -%: - dh $@ --buildsystem cmake - -override_dh_auto_configure: - dh_auto_configure -- \ - -DSTLINK_UDEV_RULES_DIR='/lib/udev/rules.d' - -override_dh_auto_install: - dh_auto_install - mkdir -p $(CURDIR)/debian/tmp/usr/lib/$(DEB_HOST_MULTIARCH)/pkgconfig - sed -e "s/@VERSION@/$(DEB_VERSION_UPSTREAM)/" -e "s/@DEB_HOST_MULTIARCH@/$(DEB_HOST_MULTIARCH)/" $(CURDIR)/debian/stlink.pc.in > $(CURDIR)/debian/tmp/usr/lib/$(DEB_HOST_MULTIARCH)/pkgconfig/stlink.pc diff --git a/debian/source/format b/debian/source/format deleted file mode 100644 index 163aaf8d8..000000000 --- a/debian/source/format +++ /dev/null @@ -1 +0,0 @@ -3.0 (quilt) diff --git a/debian/source/options b/debian/source/options deleted file mode 100644 index 506210d2c..000000000 --- a/debian/source/options +++ /dev/null @@ -1 +0,0 @@ -extend-diff-ignore=stlinkv1_macos_driver diff --git a/debian/stlink-gui.install b/debian/stlink-gui.install deleted file mode 100644 index 96c55213f..000000000 --- a/debian/stlink-gui.install +++ /dev/null @@ -1,4 +0,0 @@ -/usr/bin/stlink-gui -/usr/share/stlink/stlink-gui.ui -/usr/share/applications/stlink-gui.desktop -/usr/share/icons/hicolor/scalable/apps/stlink-gui.svg diff --git a/debian/stlink-tools.install b/debian/stlink-tools.install deleted file mode 100644 index ca875a0e6..000000000 --- a/debian/stlink-tools.install +++ /dev/null @@ -1,3 +0,0 @@ -/usr/bin/st-* -lib/udev/rules.d/*.rules -etc/modprobe.d/*.conf diff --git a/debian/stlink-tools.manpages b/debian/stlink-tools.manpages deleted file mode 100644 index 049509abe..000000000 --- a/debian/stlink-tools.manpages +++ /dev/null @@ -1,3 +0,0 @@ -usr/share/stlink/man/man1/st-flash.1 -usr/share/stlink/man/man1/st-info.1 -usr/share/stlink/man/man1/st-util.1 diff --git a/debian/stlink.pc.in b/debian/stlink.pc.in deleted file mode 100644 index 9f740ba09..000000000 --- a/debian/stlink.pc.in +++ /dev/null @@ -1,10 +0,0 @@ -prefix=/usr -includedir=${prefix}/include/stlink -libdir=${prefix}/lib/@DEB_HOST_MULTIARCH@ - -Name: stlink -Description: Open source STM32 MCU programming toolset -Version: @VERSION@ -Requires: libusb-1.0 -Libs: -L${libdir} -lstlink -Cflags: -I${includedir} diff --git a/debian/watch b/debian/watch deleted file mode 100644 index 6eb6b78d6..000000000 --- a/debian/watch +++ /dev/null @@ -1,3 +0,0 @@ -version=3 -opts=dversionmangle=s/\+ds$//,repacksuffix=+ds,filenamemangle=s/.+\/v?(\d\S+)\.tar\.gz/stlink-$1\.tar\.gz/ \ - https://github.com/stlink-org/stlink/tags .*/v?(\d\S+)\.tar\.gz From e43b434c8ac59885710cb4b2b05fb49d7c023ad4 Mon Sep 17 00:00:00 2001 From: Ant-ON Date: Tue, 27 Oct 2020 11:41:39 +0500 Subject: [PATCH 086/503] Small rewrote setting breakpoints in gdb-server for Cortex-M7 --- inc/stm32.h | 1 + src/common.c | 8 +++- src/st-util/gdb-server.c | 92 +++++++++++++--------------------------- src/stlink-lib/reg.h | 10 ++++- 4 files changed, 47 insertions(+), 64 deletions(-) diff --git a/inc/stm32.h b/inc/stm32.h index 1773e703b..768fabb87 100644 --- a/inc/stm32.h +++ b/inc/stm32.h @@ -10,6 +10,7 @@ /* Cortex core ids */ #define STM32VL_CORE_ID 0x1ba01477 #define STM32F7_CORE_ID 0x5ba02477 +#define STM32H7_CORE_ID 0x6ba02477 // STM32H7 JTAG ID Code (RM0433 pg3065) /* Constant STM32 memory map figures */ #define STM32_FLASH_BASE ((uint32_t)0x08000000) diff --git a/src/common.c b/src/common.c index a08db2733..c7f2883db 100644 --- a/src/common.c +++ b/src/common.c @@ -1252,7 +1252,13 @@ int stlink_core_id(stlink_t *sl) { int stlink_chip_id(stlink_t *sl, uint32_t *chip_id) { int ret; - ret = stlink_read_debug32(sl, 0xE0042000, chip_id); + if (sl->core_id == STM32H7_CORE_ID) { + // STM32H7 chipid in 0x5c001000 (RM0433 pg3189) + ret = stlink_read_debug32(sl, 0x5c001000, chip_id); + } else { + // default chipid address + ret = stlink_read_debug32(sl, 0xE0042000, chip_id); + } if (ret == -1) { return(ret); diff --git a/src/st-util/gdb-server.c b/src/st-util/gdb-server.c index 60c9c16d3..d2685cef6 100644 --- a/src/st-util/gdb-server.c +++ b/src/st-util/gdb-server.c @@ -575,21 +575,6 @@ char* make_memory_map(stlink_t *sl) { return(map); } -/* - * DWT_COMP0 0xE0001020 - * DWT_MASK0 0xE0001024 - * DWT_FUNCTION0 0xE0001028 - * DWT_COMP1 0xE0001030 - * DWT_MASK1 0xE0001034 - * DWT_FUNCTION1 0xE0001038 - * DWT_COMP2 0xE0001040 - * DWT_MASK2 0xE0001044 - * DWT_FUNCTION2 0xE0001048 - * DWT_COMP3 0xE0001050 - * DWT_MASK3 0xE0001054 - * DWT_FUNCTION3 0xE0001058 - */ - #define DATA_WATCH_NUM 4 enum watchfun { WATCHDISABLED = 0, WATCHREAD = 5, WATCHWRITE = 6, WATCHACCESS = 7 }; @@ -606,15 +591,15 @@ static void init_data_watchpoints(stlink_t *sl) { uint32_t data; DLOG("init watchpoints\n"); - stlink_read_debug32(sl, 0xE000EDFC, &data); + stlink_read_debug32(sl, STLINK_REG_CM3_DEMCR, &data); data |= 1 << 24; - // set trcena in debug command to turn on dwt unit - stlink_write_debug32(sl, 0xE000EDFC, data); + // set TRCENA in debug command to turn on DWT unit + stlink_write_debug32(sl, STLINK_REG_CM3_DEMCR, data); // make sure all watchpoints are cleared for (int i = 0; i < DATA_WATCH_NUM; i++) { data_watches[i].fun = WATCHDISABLED; - stlink_write_debug32(sl, 0xe0001028 + i * 16, 0); + stlink_write_debug32(sl, STLINK_REG_CM3_DWT_FUNn(i), 0); } } @@ -645,16 +630,16 @@ static int add_data_watchpoint(stlink_t *sl, enum watchfun wf, stm32_addr_t addr data_watches[i].mask = mask; // insert comparator address - stlink_write_debug32(sl, 0xE0001020 + i * 16, addr); + stlink_write_debug32(sl, STLINK_REG_CM3_DWT_COMPn(i), addr); // insert mask - stlink_write_debug32(sl, 0xE0001024 + i * 16, mask); + stlink_write_debug32(sl, STLINK_REG_CM3_DWT_MASKn(i), mask); // insert function - stlink_write_debug32(sl, 0xE0001028 + i * 16, wf); + stlink_write_debug32(sl, STLINK_REG_CM3_DWT_FUNn(i), wf); // just to make sure the matched bit is clear ! - stlink_read_debug32(sl, 0xE0001028 + i * 16, &dummy); + stlink_read_debug32(sl, STLINK_REG_CM3_DWT_FUNn(i), &dummy); return(0); } } @@ -671,7 +656,7 @@ static int delete_data_watchpoint(stlink_t *sl, stm32_addr_t addr) { DLOG("delete watchpoint %d addr %x\n", i, addr); data_watches[i].fun = WATCHDISABLED; - stlink_write_debug32(sl, 0xe0001028 + i * 16, 0); + stlink_write_debug32(sl, STLINK_REG_CM3_DWT_FUNn(i), 0); return(0); } @@ -705,9 +690,15 @@ static void init_code_breakpoints(stlink_t *sl) { ILOG("Found %i hw breakpoint registers\n", code_break_num); + if (sl->core_id == STM32F7_CORE_ID || sl->core_id == STM32H7_CORE_ID) { + // Cortex-M7 can have locked to write FP_* registers + // IHI0029D, p. 48, Lock Access Register + stlink_write_debug32(sl, STLINK_REG_CM7_FP_LAR, STLINK_REG_CM7_FP_LAR_KEY); + } + for (int i = 0; i < code_break_num; i++) { code_breaks[i].type = 0; - stlink_write_debug32(sl, STLINK_REG_CM3_FP_COMP0 + i * 4, 0); + stlink_write_debug32(sl, STLINK_REG_CM3_FP_COMPn(i), 0); } } @@ -719,69 +710,46 @@ static int has_breakpoint(stm32_addr_t addr) { } static int update_code_breakpoint(stlink_t *sl, stm32_addr_t addr, int set) { - stm32_addr_t fpb_addr; uint32_t mask; int type = (addr & 0x2) ? CODE_BREAK_HIGH : CODE_BREAK_LOW; + stm32_addr_t fpb_addr = addr & 0x1FFFFFFC; if (addr & 1) { ELOG("update_code_breakpoint: unaligned address %08x\n", addr); return(-1); } - if (sl->core_id == STM32F7_CORE_ID) { - fpb_addr = addr; - } else { - fpb_addr = addr & ~0x3; - } - int id = -1; - for (int i = 0; i < code_break_num; i++) if (fpb_addr == code_breaks[i].addr || (set && code_breaks[i].type == 0)) { id = i; break; } - if (id == -1) { - if (set) { - return(-1); - } // free slot not found - else { - return(0); - } // breakpoint is already removed - + if (set) + return(-1); // free slot not found + else + return(0); // breakpoint is already removed } struct code_hw_breakpoint* bp = &code_breaks[id]; - bp->addr = fpb_addr; - - if (sl->core_id == STM32F7_CORE_ID) { - if (set) { - bp->type = type; - } else { - bp->type = 0; - } - - mask = (bp->addr) | 1; - } else { - if (set) { - bp->type |= type; - } else { - bp->type &= ~type; - } - - mask = (bp->addr) | 1 | (bp->type << 30); - } + if (set) + bp->type |= type; + else + bp->type &= ~type; + + // DDI0403E, p. 759, FP_COMPn register description + mask = (bp->type << 30) | (bp->addr) | 1; if (bp->type == 0) { DLOG("clearing hw break %d\n", id); - stlink_write_debug32(sl, 0xe0002008 + id * 4, 0); + stlink_write_debug32(sl, STLINK_REG_CM3_FP_COMPn(id), 0); } else { DLOG("setting hw break %d at %08x (%d)\n", id, bp->addr, bp->type); DLOG("reg %08x \n", mask); - stlink_write_debug32(sl, 0xe0002008 + id * 4, mask); + stlink_write_debug32(sl, STLINK_REG_CM3_FP_COMPn(id), mask); } return(0); diff --git a/src/stlink-lib/reg.h b/src/stlink-lib/reg.h index dde77ef50..3a3682140 100644 --- a/src/stlink-lib/reg.h +++ b/src/stlink-lib/reg.h @@ -2,8 +2,16 @@ #define STLINK_REG_H_ #define STLINK_REG_CM3_CPUID 0xE000ED00 + #define STLINK_REG_CM3_FP_CTRL 0xE0002000 -#define STLINK_REG_CM3_FP_COMP0 0xE0002008 +#define STLINK_REG_CM3_FP_COMPn(n) (0xE0002008 + n*4) +#define STLINK_REG_CM7_FP_LAR 0xE0000FB0 +#define STLINK_REG_CM7_FP_LAR_KEY 0xC5ACCE55 + +#define STLINK_REG_CM3_DEMCR 0xE000EDFC +#define STLINK_REG_CM3_DWT_COMPn(n) (0xE0001020 + n*16) +#define STLINK_REG_CM3_DWT_MASKn(n) (0xE0001024 + n*16) +#define STLINK_REG_CM3_DWT_FUNn(n) (0xE0001028 + n*16) /* Cortex™-M3 Technical Reference Manual */ /* Debug Halting Control and Status Register */ From e5dcb5048c58bcbb95fee79e4775b7b447a5fc4f Mon Sep 17 00:00:00 2001 From: Timothy Lee Date: Tue, 27 Oct 2020 20:28:48 +1100 Subject: [PATCH 087/503] [feature] support STM32F4 option bytes --- inc/stm32.h | 1 + src/common.c | 1 + src/stlink-lib/chipid.c | 4 +++- 3 files changed, 5 insertions(+), 1 deletion(-) diff --git a/inc/stm32.h b/inc/stm32.h index 1773e703b..b81d3149d 100644 --- a/inc/stm32.h +++ b/inc/stm32.h @@ -20,6 +20,7 @@ #define STM32_F2_OPTION_BYTES_BASE ((uint32_t)0x1FFFC000) #define STM32_L4_OPTION_BYTES_BASE ((uint32_t)0x1FFF7800) #define STM32_L1_OPTION_BYTES_BASE ((uint32_t)0x1FF80000) +#define STM32_F4_OPTION_BYTES_BASE ((uint32_t)0x40023C14) #define STM32_F7_OPTION_BYTES_BASE ((uint32_t)0x1FFF0000) #define STM32_H7_OPTION_BYTES_BASE ((uint32_t)0x5200201C) diff --git a/src/common.c b/src/common.c index a08db2733..32c00ad3b 100644 --- a/src/common.c +++ b/src/common.c @@ -3680,6 +3680,7 @@ int stlink_read_option_bytes32(stlink_t *sl, uint32_t* option_byte) { switch (sl->chip_id) { case STLINK_CHIPID_STM32_F2: return stlink_read_option_bytes_f2(sl, option_byte); + case STLINK_CHIPID_STM32_F4: case STLINK_CHIPID_STM32_F446: return stlink_read_option_bytes_f4(sl, option_byte); case STLINK_CHIPID_STM32_F7XXXX: diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index c191fa919..a8d160445 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -77,7 +77,9 @@ static const struct stlink_chipid_params devices[] = { .flash_pagesize = 0x4000, .sram_size = 0x30000, .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7800 + .bootrom_size = 0x7800, + .option_base = STM32_F4_OPTION_BYTES_BASE, + .option_size = 4, }, { .chip_id = STLINK_CHIPID_STM32_F4_DSI, From 59f8b479f6e87181b4d3430ff5a57ce08f820291 Mon Sep 17 00:00:00 2001 From: Fabian Herb Date: Mon, 26 Oct 2020 16:11:49 +0000 Subject: [PATCH 088/503] st-util: Add specialized memory map for STM32H7 devices --- src/st-util/gdb-server.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/src/st-util/gdb-server.c b/src/st-util/gdb-server.c index 60c9c16d3..2e936a5de 100644 --- a/src/st-util/gdb-server.c +++ b/src/st-util/gdb-server.c @@ -504,6 +504,24 @@ static const char* const memory_map_template_F7 = " " // option byte area ""; +static const char* const memory_map_template_H7 = + "" + "" + "" + " " // ITCMRAM 64kB + " " // DTCMRAM 128kB + " " // RAM D1 512kB + " " // RAM D2 288kB + " " // RAM D3 64kB + " " + " 0x%x" + " " + " " // peripheral regs + " " // cortex regs + " " // bootrom + ""; + static const char* const memory_map_template_F4_DE = "" @@ -543,6 +561,10 @@ char* make_memory_map(stlink_t *sl) { } else if (sl->core_id == STM32F7_CORE_ID) { snprintf(map, sz, memory_map_template_F7, (unsigned int)sl->sram_size); + } else if (sl->chip_id == STLINK_CHIPID_STM32_H74XXX) { + snprintf(map, sz, memory_map_template_H7, + (unsigned int)sl->flash_size, + (unsigned int)sl->flash_pgsz); } else if (sl->chip_id == STLINK_CHIPID_STM32_F4_HD) { strcpy(map, memory_map_template_F4_HD); } else if (sl->chip_id == STLINK_CHIPID_STM32_F2) { From 31bea45e32d843b5b2d5bb2ea3bba3dbec73ac1b Mon Sep 17 00:00:00 2001 From: Ant-ON Date: Thu, 29 Oct 2020 13:30:16 +0500 Subject: [PATCH 089/503] Autodetect breakpoint style and cache support --- src/st-util/gdb-server.c | 75 ++++++++++++++++++++++------------------ src/stlink-lib/reg.h | 14 +++++++- 2 files changed, 55 insertions(+), 34 deletions(-) diff --git a/src/st-util/gdb-server.c b/src/st-util/gdb-server.c index d2685cef6..c832098f1 100644 --- a/src/st-util/gdb-server.c +++ b/src/st-util/gdb-server.c @@ -669,9 +669,13 @@ static int delete_data_watchpoint(stlink_t *sl, stm32_addr_t addr) { static int code_break_num; static int code_lit_num; +static int code_break_rev; #define CODE_BREAK_NUM_MAX 15 #define CODE_BREAK_LOW 0x01 #define CODE_BREAK_HIGH 0x02 +#define CODE_BREAK_REMAP 0x04 +#define CODE_BREAK_REV_V1 0x00 +#define CODE_BREAK_REV_V2 0x01 struct code_hw_breakpoint { stm32_addr_t addr; @@ -683,14 +687,16 @@ static struct code_hw_breakpoint code_breaks[CODE_BREAK_NUM_MAX]; static void init_code_breakpoints(stlink_t *sl) { unsigned int val; memset(sl->q_buf, 0, 4); - stlink_write_debug32(sl, STLINK_REG_CM3_FP_CTRL, 0x03 /* KEY | ENABLE4 */); + stlink_write_debug32(sl, STLINK_REG_CM3_FP_CTRL, 0x03 /* KEY | ENABLE */); stlink_read_debug32(sl, STLINK_REG_CM3_FP_CTRL, &val); code_break_num = ((val >> 4) & 0xf); code_lit_num = ((val >> 8) & 0xf); + code_break_rev = ((val >> 28) & 0xf); ILOG("Found %i hw breakpoint registers\n", code_break_num); - if (sl->core_id == STM32F7_CORE_ID || sl->core_id == STM32H7_CORE_ID) { + stlink_read_debug32(sl, STLINK_REG_CM3_CPUID, &val); + if (((val>>4) & 0xFFF) == 0xC27) { // Cortex-M7 can have locked to write FP_* registers // IHI0029D, p. 48, Lock Access Register stlink_write_debug32(sl, STLINK_REG_CM7_FP_LAR, STLINK_REG_CM7_FP_LAR_KEY); @@ -711,14 +717,22 @@ static int has_breakpoint(stm32_addr_t addr) { static int update_code_breakpoint(stlink_t *sl, stm32_addr_t addr, int set) { uint32_t mask; - int type = (addr & 0x2) ? CODE_BREAK_HIGH : CODE_BREAK_LOW; - stm32_addr_t fpb_addr = addr & 0x1FFFFFFC; + int type; + stm32_addr_t fpb_addr; if (addr & 1) { ELOG("update_code_breakpoint: unaligned address %08x\n", addr); return(-1); } + if (code_break_rev == CODE_BREAK_REV_V1) { + type = (addr & 0x2) ? CODE_BREAK_HIGH : CODE_BREAK_LOW; + fpb_addr = addr & 0x1FFFFFFC; + } else { + type = CODE_BREAK_REMAP; + fpb_addr = addr; + } + int id = -1; for (int i = 0; i < code_break_num; i++) if (fpb_addr == code_breaks[i].addr || (set && code_breaks[i].type == 0)) { @@ -741,7 +755,7 @@ static int update_code_breakpoint(stlink_t *sl, stm32_addr_t addr, int set) { bp->type &= ~type; // DDI0403E, p. 759, FP_COMPn register description - mask = (bp->type << 30) | (bp->addr) | 1; + mask = ((bp->type&0x03) << 30) | bp->addr | 1; if (bp->type == 0) { DLOG("clearing hw break %d\n", id); @@ -870,16 +884,6 @@ static int flash_go(stlink_t *sl) { return(error); } -#define CLIDR 0xE000ED78 -#define CTR 0xE000ED7C -#define CCSIDR 0xE000ED80 -#define CSSELR 0xE000ED84 -#define CCR 0xE000ED14 -#define CCR_DC (1 << 16) -#define CCR_IC (1 << 17) -#define DCCSW 0xE000EF6C -#define ICIALLU 0xE000EF50 - struct cache_level_desc { unsigned int nsets; unsigned int nways; @@ -888,6 +892,8 @@ struct cache_level_desc { }; struct cache_desc_t { + unsigned used; + // minimal line size in bytes unsigned int dminline; unsigned int iminline; @@ -914,7 +920,7 @@ static void read_cache_level_desc(stlink_t *sl, struct cache_level_desc *desc) { unsigned int ccsidr; unsigned int log2_nsets; - stlink_read_debug32(sl, CCSIDR, &ccsidr); + stlink_read_debug32(sl, STLINK_REG_CM7_CCSIDR, &ccsidr); desc->nsets = ((ccsidr >> 13) & 0x3fff) + 1; desc->nways = ((ccsidr >> 3) & 0x1ff) + 1; desc->log2_nways = ceil_log2 (desc->nways); @@ -930,18 +936,22 @@ static void init_cache (stlink_t *sl) { unsigned int ctr; int i; - // assume only F7 has a cache - if (sl->core_id != STM32F7_CORE_ID) { return; } - - stlink_read_debug32(sl, CLIDR, &clidr); - stlink_read_debug32(sl, CCR, &ccr); - stlink_read_debug32(sl, CTR, &ctr); + // Check have cache + stlink_read_debug32(sl, STLINK_REG_CM7_CTR, &ctr); + if ((ctr >> 29) != 0x04) { + cache_desc.used = 0; + return; + } else + cache_desc.used = 1; cache_desc.dminline = 4 << ((ctr >> 16) & 0x0f); cache_desc.iminline = 4 << (ctr & 0x0f); + + stlink_read_debug32(sl, STLINK_REG_CM7_CLIDR, &clidr); cache_desc.louu = (clidr >> 27) & 7; + stlink_read_debug32(sl, STLINK_REG_CM7_CCR, &ccr); ILOG("Chip clidr: %08x, I-Cache: %s, D-Cache: %s\n", - clidr, ccr & CCR_IC ? "on" : "off", ccr & CCR_DC ? "on" : "off"); + clidr, ccr & STLINK_REG_CM7_CCR_IC ? "on" : "off", ccr & STLINK_REG_CM7_CCR_DC ? "on" : "off"); ILOG(" cache: LoUU: %u, LoC: %u, LoUIS: %u\n", (clidr >> 27) & 7, (clidr >> 24) & 7, (clidr >> 21) & 7); ILOG(" cache: ctr: %08x, DminLine: %u bytes, IminLine: %u bytes\n", ctr, @@ -953,13 +963,13 @@ static void init_cache (stlink_t *sl) { cache_desc.icache[i].width = 0; if (ct == 2 || ct == 3 || ct == 4) { // data - stlink_write_debug32(sl, CSSELR, i << 1); + stlink_write_debug32(sl, STLINK_REG_CM7_CSSELR, i << 1); ILOG("D-Cache L%d: ", i); read_cache_level_desc(sl, &cache_desc.dcache[i]); } if (ct == 1 || ct == 3) { // instruction - stlink_write_debug32(sl, CSSELR, (i << 1) | 1); + stlink_write_debug32(sl, STLINK_REG_CM7_CSSELR, (i << 1) | 1); ILOG("I-Cache L%d: ", i); read_cache_level_desc(sl, &cache_desc.icache[i]); } @@ -969,7 +979,7 @@ static void init_cache (stlink_t *sl) { static void cache_flush(stlink_t *sl, unsigned ccr) { int level; - if (ccr & CCR_DC) { + if (ccr & STLINK_REG_CM7_CCR_DC) { for (level = cache_desc.louu - 1; level >= 0; level--) { struct cache_level_desc *desc = &cache_desc.dcache[level]; unsigned addr; @@ -981,15 +991,15 @@ static void cache_flush(stlink_t *sl, unsigned ccr) { unsigned int way; for (way = 0; way < desc->nways; way++) { - stlink_write_debug32(sl, DCCSW, addr | (way << way_sh)); + stlink_write_debug32(sl, STLINK_REG_CM7_DCCSW, addr | (way << way_sh)); } } } } // invalidate all I-cache to oPU - if (ccr & CCR_IC) { - stlink_write_debug32(sl, ICIALLU, 0); + if (ccr & STLINK_REG_CM7_CCR_IC) { + stlink_write_debug32(sl, STLINK_REG_CM7_ICIALLU, 0); } } @@ -1005,14 +1015,13 @@ static void cache_change(stm32_addr_t start, unsigned count) { static void cache_sync(stlink_t *sl) { unsigned ccr; - if (sl->core_id != STM32F7_CORE_ID) { return; } + if (!cache_desc.used) { return; } if (!cache_modified) { return; } cache_modified = 0; - stlink_read_debug32(sl, CCR, &ccr); - - if (ccr & (CCR_IC | CCR_DC)) { cache_flush(sl, ccr); } + stlink_read_debug32(sl, STLINK_REG_CM7_CCR, &ccr); + if (ccr & (STLINK_REG_CM7_CCR_IC | STLINK_REG_CM7_CCR_DC)) { cache_flush(sl, ccr); } } static size_t unhexify(const char *in, char *out, size_t out_count) { diff --git a/src/stlink-lib/reg.h b/src/stlink-lib/reg.h index 3a3682140..734107d6a 100644 --- a/src/stlink-lib/reg.h +++ b/src/stlink-lib/reg.h @@ -6,7 +6,7 @@ #define STLINK_REG_CM3_FP_CTRL 0xE0002000 #define STLINK_REG_CM3_FP_COMPn(n) (0xE0002008 + n*4) #define STLINK_REG_CM7_FP_LAR 0xE0000FB0 -#define STLINK_REG_CM7_FP_LAR_KEY 0xC5ACCE55 +#define STLINK_REG_CM7_FP_LAR_KEY 0xC5ACCE55 #define STLINK_REG_CM3_DEMCR 0xE000EDFC #define STLINK_REG_CM3_DWT_COMPn(n) (0xE0001020 + n*16) @@ -25,4 +25,16 @@ #define STLINK_REG_AIRCR_VECTKEY 0x05fa0000 #define STLINK_REG_AIRCR_SYSRESETREQ 0x00000004 +/* ARM Cortex-M7 Processor Technical Reference Manual */ +/* Cache Control and Status Register */ +#define STLINK_REG_CM7_CTR 0xE000ED7C +#define STLINK_REG_CM7_CLIDR 0xE000ED78 +#define STLINK_REG_CM7_CCR 0xE000ED14 +#define STLINK_REG_CM7_CCR_DC (1 << 16) +#define STLINK_REG_CM7_CCR_IC (1 << 17) +#define STLINK_REG_CM7_CSSELR 0xE000ED84 +#define STLINK_REG_CM7_DCCSW 0xE000EF6C +#define STLINK_REG_CM7_ICIALLU 0xE000EF50 +#define STLINK_REG_CM7_CCSIDR 0xE000ED80 + #endif // STLINK_REG_H_ From f503de605561a71bd4dafca59826d7847604ccd3 Mon Sep 17 00:00:00 2001 From: Luca Boccassi Date: Thu, 29 Oct 2020 18:06:33 +0000 Subject: [PATCH 090/503] Add cross.patch to fix cross-compilation. Thanks Helmut! Closes: #973339 --- debian/patches/cross.patch | 11 +++++++++++ debian/patches/series | 1 + 2 files changed, 12 insertions(+) create mode 100644 debian/patches/cross.patch diff --git a/debian/patches/cross.patch b/debian/patches/cross.patch new file mode 100644 index 000000000..8d927ba4b --- /dev/null +++ b/debian/patches/cross.patch @@ -0,0 +1,11 @@ +--- stlink-1.6.1+ds.orig/CMakeLists.txt ++++ stlink-1.6.1+ds/CMakeLists.txt +@@ -48,7 +48,7 @@ + find_package(libusb REQUIRED) + + ## Package configuration (pkg-config) on unix-based systems +-if (NOT WIN32 AND NOT CMAKE_CROSSCOMPILING) ++if (NOT WIN32) + #add_subdirectory(cmake/pkgconfig) + find_package(PkgConfig) + pkg_check_modules(GTK3 gtk+-3.0) diff --git a/debian/patches/series b/debian/patches/series index 1fdcf9977..b3c28e7e1 100644 --- a/debian/patches/series +++ b/debian/patches/series @@ -1 +1,2 @@ guipath.patch +cross.patch From a952c950a62038b231a8e303c03d1c34b0e13bcd Mon Sep 17 00:00:00 2001 From: Luca Boccassi Date: Thu, 29 Oct 2020 18:06:53 +0000 Subject: [PATCH 091/503] Update changelog for 1.6.1+ds-3 release --- debian/changelog | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/debian/changelog b/debian/changelog index f1265ee32..ac046a5f4 100644 --- a/debian/changelog +++ b/debian/changelog @@ -1,3 +1,10 @@ +stlink (1.6.1+ds-3) unstable; urgency=medium + + * Add cross.patch to fix cross-compilation. Thanks Helmut! (Closes: + #973339) + + -- Luca Boccassi Thu, 29 Oct 2020 18:06:39 +0000 + stlink (1.6.1+ds-2) unstable; urgency=medium * Update d/copyright to remove GPL-2+ stanza about flashloaders From 504858566be82af996566795c41684b701b52ce1 Mon Sep 17 00:00:00 2001 From: anton Date: Sun, 1 Nov 2020 20:42:21 +0500 Subject: [PATCH 092/503] Improv MCU reseting --- src/stlink-lib/reg.h | 1 + src/stlink-lib/usb.c | 43 ++++++++++++++++++++++++++++++++++++++----- 2 files changed, 39 insertions(+), 5 deletions(-) diff --git a/src/stlink-lib/reg.h b/src/stlink-lib/reg.h index 734107d6a..653852440 100644 --- a/src/stlink-lib/reg.h +++ b/src/stlink-lib/reg.h @@ -17,6 +17,7 @@ /* Debug Halting Control and Status Register */ #define STLINK_REG_DHCSR 0xe000edf0 #define STLINK_REG_DHCSR_DBGKEY 0xa05f0000 +#define STLINK_REG_DHCSR_S_RESET_ST 0x02000000 #define STLINK_REG_DCRSR 0xe000edf4 #define STLINK_REG_DCRDR 0xe000edf8 diff --git a/src/stlink-lib/usb.c b/src/stlink-lib/usb.c index 9726ddc4a..6b914d805 100644 --- a/src/stlink-lib/usb.c +++ b/src/stlink-lib/usb.c @@ -508,9 +508,14 @@ int _stlink_usb_reset(stlink_t * sl) { unsigned char* const data = sl->q_buf; unsigned char* const cmd = sl->c_buf; ssize_t size; - int rep_len = 2; - int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); + uint32_t dhcsr; + int ret, i, rep_len = 2; + // clear S_RESET_ST in DHCSR registr + stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); + + // send reset command + i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); cmd[i++] = STLINK_DEBUG_COMMAND; if (sl->version.jtag_api == STLINK_JTAG_API_V1) { @@ -526,9 +531,37 @@ int _stlink_usb_reset(stlink_t * sl) { return((int)size); } - // reset through AIRCR so that NRST does not need to be connected - return(stlink_write_debug32(sl, STLINK_REG_AIRCR, STLINK_REG_AIRCR_VECTKEY | - STLINK_REG_AIRCR_SYSRESETREQ)); + usleep(10000); + + dhcsr = 0; + ret = stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); + if ((dhcsr & STLINK_REG_DHCSR_S_RESET_ST) == 0) { + // reset not done yet + // try reset through AIRCR so that NRST does not need to be connected + + WLOG("NRST is not connected\n"); + DLOG("Using reset through SYSRESETREQ\n"); + ret = stlink_write_debug32(sl, STLINK_REG_AIRCR, STLINK_REG_AIRCR_VECTKEY | + STLINK_REG_AIRCR_SYSRESETREQ); + if (ret) + return(ret); + + usleep(10000); + } + + // waiting for a reset within 500ms + for (i=0; i<50; i++) { + // DDI0337E, p. 10-4, Debug Halting Control and Status Register + dhcsr = STLINK_REG_DHCSR_S_RESET_ST; + stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); + if ((dhcsr&STLINK_REG_DHCSR_S_RESET_ST) == 0) + break; + usleep(10000); + } + + if (i >= 50) + return(-1); + return(0); } int _stlink_usb_jtag_reset(stlink_t * sl, int value) { From 4d07eb363dc9ca68936fd828d62340d8a9b558e3 Mon Sep 17 00:00:00 2001 From: Ant-ON Date: Mon, 2 Nov 2020 21:52:13 +0500 Subject: [PATCH 093/503] Split flash write function to optimize gdb flash loading --- inc/stlink.h | 4 + src/common.c | 382 +++++++++++++++++++++------------------ src/st-util/gdb-server.c | 28 ++- 3 files changed, 234 insertions(+), 180 deletions(-) diff --git a/inc/stlink.h b/inc/stlink.h index 39f5f283c..e78b9569f 100644 --- a/inc/stlink.h +++ b/inc/stlink.h @@ -303,6 +303,10 @@ int stlink_write_option_control_register1_32(stlink_t *sl, uint32_t option_contr int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t len); int stlink_fwrite_option_bytes(stlink_t *sl, const char* path, stm32_addr_t addr); +int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl); +int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t addr, uint8_t* base, uint32_t len); +int stlink_flashloader_stop(stlink_t *sl); + #include #include #include diff --git a/src/common.c b/src/common.c index c7f2883db..71caeeaa8 100644 --- a/src/common.c +++ b/src/common.c @@ -2669,151 +2669,140 @@ int stm32l1_write_half_pages( return(0); } -int stlink_write_flash( - stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t len, uint8_t eraseonly) { - size_t off; - flash_loader_t fl; - ILOG("Attempting to write %d (%#x) bytes to stm32 address: %u (%#x)\n", len, len, addr, addr); - // check addr range is inside the flash - stlink_calculate_pagesize(sl, addr); - - if (addr < sl->flash_base) { - ELOG("addr too low %#x < %#x\n", addr, sl->flash_base); - return(-1); - } else if ((addr + len) < addr) { - ELOG("addr overruns\n"); - return(-1); - } else if ((addr + len) > (sl->flash_base + sl->flash_size)) { - ELOG("addr too high\n"); - return(-1); - } else if (addr & 1) { - ELOG("unaligned addr 0x%x\n", addr); - return(-1); - } else if (len & 1) { - WLOG("unaligned len 0x%x -- padding with zero\n", len); - len += 1; - } else if (addr & (sl->flash_pgsz - 1)) { - ELOG("addr not a multiple of current pagesize (%zd bytes), not supported, " - "check page start address and compare with flash module organisation " - "in related ST reference manual of your device.\n", sl->flash_pgsz); - return(-1); - } - - // make sure we've loaded the context with the chip details - stlink_core_id(sl); - - // Erase each page - int page_count = 0; - - for (off = 0; off < len; off += stlink_calculate_pagesize(sl, addr + (uint32_t)off)) { - // addr must be an addr inside the page - if (stlink_erase_flash_page(sl, addr + (uint32_t)off) == -1) { - ELOG("Failed to erase_flash_page(%#zx) == -1\n", addr + off); - return(-1); - } - - ILOG("Flash page at addr: 0x%08lx erased\n", (unsigned long)(addr + off)); - page_count++; - } - - ILOG("Finished erasing %d pages of %d (%#x) bytes\n", - page_count, sl->flash_pgsz, sl->flash_pgsz); - - if (eraseonly) { return(0); } - +int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { if ((sl->flash_type == STLINK_FLASH_TYPE_F4) || (sl->flash_type == STLINK_FLASH_TYPE_F7) || (sl->flash_type == STLINK_FLASH_TYPE_L4)) { - // TODO: check write operation - ILOG("Starting Flash write for F2/F4/F7/L4\n"); + // Flash loader initialisation - if (stlink_flash_loader_init(sl, &fl) == -1) { + if (stlink_flash_loader_init(sl, fl) == -1) { ELOG("stlink_flash_loader_init() == -1\n"); return(-1); } unlock_flash_if(sl); // first unlock the cr - // TODO: Check that Voltage range is 2.7 - 3.6 V - if ((sl->chip_id != STLINK_CHIPID_STM32_L4) && - (sl->chip_id != STLINK_CHIPID_STM32_L43X) && - (sl->chip_id != STLINK_CHIPID_STM32_L46X) && - (sl->chip_id != STLINK_CHIPID_STM32_L496X) && - (sl->chip_id != STLINK_CHIPID_STM32_L4RX)) { + int voltage; + if (sl->version.stlink_v == 1) { + WLOG("STLINK V1 cannot read voltage, use default voltage 3.2V\n"); + voltage = 3200; + } else { + voltage = stlink_target_voltage(sl); + } + + if (voltage == -1) { + ELOG("Failed to read Target voltage\n"); + return(voltage); + } - if ( sl->version.stlink_v == 1) { - printf("STLINK V1 cannot read voltage, defaulting to 32-bit " - "writes on F4 devices\n"); + if (sl->flash_type == STLINK_FLASH_TYPE_L4) { + // L4 does not have a byte-write mode + if (voltage < 1710) { + ELOG("Target voltage (%d mV) too low for flash writes!\n", voltage); + return(-1); + } + } else { + if (voltage > 2700) { + ILOG("enabling 32-bit flash writes\n"); write_flash_cr_psiz(sl, 2); } else { - // set parallelism to 32 bit - int voltage = stlink_target_voltage(sl); - - if (voltage == -1) { - printf("Failed to read Target voltage\n"); - return(voltage); - } else if (voltage > 2700) { - printf("enabling 32-bit flash writes\n"); - write_flash_cr_psiz(sl, 2); - } else { - printf("Target voltage (%d mV) too low for 32-bit flash, " - "using 8-bit flash writes\n", voltage); - write_flash_cr_psiz(sl, 0); - } + ILOG("Target voltage (%d mV) too low for 32-bit flash, " + "using 8-bit flash writes\n", voltage); + write_flash_cr_psiz(sl, 0); } + } + + // set programming mode + set_flash_cr_pg(sl); + } else if (sl->flash_type == STLINK_FLASH_TYPE_WB || + sl->flash_type == STLINK_FLASH_TYPE_G0 || + sl->flash_type == STLINK_FLASH_TYPE_G4) { + ILOG("Starting Flash write for WB/G0/G4\n"); + + wait_flash_busy(sl); + unlock_flash_if(sl); // unlock flash if necessary + set_flash_cr_pg(sl); // set PG 'allow programming' bit + } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { + ILOG("Starting Flash write for L0\n"); + + uint32_t val; + uint32_t flash_regs_base; + if (sl->chip_id == STLINK_CHIPID_STM32_L0 || + sl->chip_id == STLINK_CHIPID_STM32_L0_CAT5 || + sl->chip_id == STLINK_CHIPID_STM32_L0_CAT2 || + sl->chip_id == STLINK_CHIPID_STM32_L011) { + flash_regs_base = STM32L0_FLASH_REGS_ADDR; } else { - // L4 does not have a byte-write mode - int voltage = stlink_target_voltage(sl); + flash_regs_base = STM32L_FLASH_REGS_ADDR; + } - if (voltage == -1) { - printf("Failed to read Target voltage\n"); - return(voltage); - } else if (voltage < 1710) { - printf("Target voltage (%d mV) too low for flash writes!\n", voltage); - return(-1); - } + // disable pecr protection + stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, FLASH_L0_PEKEY1); + stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, FLASH_L0_PEKEY2); + + // check pecr.pelock is cleared + stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); + if (val & (1 << 0)) { + ELOG("pecr.pelock not clear\n"); + return(-1); } - // set programming mode - set_flash_cr_pg(sl); + // unlock program memory + stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, FLASH_L0_PRGKEY1); + stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, FLASH_L0_PRGKEY2); - size_t buf_size = (sl->sram_size > 0x8000) ? 0x8000 : 0x4000; + // check pecr.prglock is cleared + stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); + if (val & (1 << 1)) { + ELOG("pecr.prglock not clear\n"); + return(-1); + } + } else if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || + (sl->flash_type == STLINK_FLASH_TYPE_F1_XL)) { + ILOG("Starting Flash write for VL/F0/F3/F1_XL\n"); + + // flash loader initialisation + if (stlink_flash_loader_init(sl, fl) == -1) { + ELOG("stlink_flash_loader_init() == -1\n"); + return(-1); + } + } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + ILOG("Starting Flash write for H7\n"); + + unlock_flash_if(sl); // unlock the cr + set_flash_cr_pg(sl); // set programming mode + } else { + ELOG("unknown coreid, not sure how to write: %x\n", sl->core_id); + return(-1); + } + return(0); +} + +int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t addr, + uint8_t* base, uint32_t len) { + size_t off; + if ((sl->flash_type == STLINK_FLASH_TYPE_F4) || + (sl->flash_type == STLINK_FLASH_TYPE_F7) || + (sl->flash_type == STLINK_FLASH_TYPE_L4)) { + size_t buf_size = (sl->sram_size > 0x8000) ? 0x8000 : 0x4000; for (off = 0; off < len;) { size_t size = len - off > buf_size ? buf_size : len - off; - printf("size: %u\n", (unsigned int)size); - - if (stlink_flash_loader_run(sl, &fl, addr + (uint32_t)off, base + off, size) == -1) { + if (stlink_flash_loader_run(sl, fl, addr + (uint32_t)off, base + off, size) == -1) { ELOG("stlink_flash_loader_run(%#zx) failed! == -1\n", addr + off); return(-1); } off += size; } - - clear_flash_cr_pg(sl); - lock_flash(sl); - - // STM32F4END } else if (sl->flash_type == STLINK_FLASH_TYPE_WB || sl->flash_type == STLINK_FLASH_TYPE_G0 || sl->flash_type == STLINK_FLASH_TYPE_G4) { - fprintf(stdout, "Writing\r\n"); - fflush(stdout); - wait_flash_busy(sl); - unlock_flash_if(sl); // unlock flash if necessary - set_flash_cr_pg(sl); // set PG 'allow programming' bit - // write all words. - off = 0; - fprintf(stdout, "Starting %3u page write\r\n", (unsigned int)(len / sl->flash_pgsz)); - fflush(stdout); - - for ( ; off < len; off += sizeof(uint32_t)) { + DLOG("Starting %3u page write\r\n", (unsigned int)(len / sl->flash_pgsz)); + for (off = 0; off < len; off += sizeof(uint32_t)) { uint32_t data; - if (off > 254) { fprintf(stdout, "\r"); } - if ((off % sl->flash_pgsz) > (sl->flash_pgsz - 5)) { fprintf(stdout, "\r%3u/%3u pages written", (unsigned int)(off / sl->flash_pgsz), @@ -2825,18 +2814,14 @@ int stlink_write_flash( stlink_write_debug32(sl, addr + (uint32_t)off, data); wait_flash_busy(sl); // wait for 'busy' bit in FLASH_SR to clear } + fprintf(stdout, "\n"); // flash writes happen as 2 words at a time if ((off / sizeof(uint32_t)) % 2 != 0) { stlink_write_debug32(sl, addr + (uint32_t)off, 0); // write a single word of zeros wait_flash_busy(sl); // wait for 'busy' bit in FLASH_SR to clear } - - clear_flash_cr_pg(sl); // reset PG bit. - lock_flash(sl); } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { - // use fast word write - // TODO: half page uint32_t val; uint32_t flash_regs_base; uint32_t pagesize; @@ -2852,32 +2837,6 @@ int stlink_write_flash( pagesize = L1_WRITE_BLOCK_SIZE; } - // TODO: check write operation - - // disable pecr protection - stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, FLASH_L0_PEKEY1); - stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, FLASH_L0_PEKEY2); - - // check pecr.pelock is cleared - stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); - - if (val & (1 << 0)) { - fprintf(stderr, "pecr.pelock not clear\n"); - return(-1); - } - - // unlock program memory - stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, FLASH_L0_PRGKEY1); - stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, FLASH_L0_PRGKEY2); - - // check pecr.prglock is cleared - stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); - - if (val & (1 << 1)) { - fprintf(stderr, "pecr.prglock not clear\n"); - return(-1); - } - off = 0; if (len > pagesize) { @@ -2892,9 +2851,7 @@ int stlink_write_flash( // write remaining word in program memory for ( ; off < len; off += sizeof(uint32_t)) { uint32_t data; - - if (off > 254) { fprintf(stdout, "\r"); } - + if ((off % sl->flash_pgsz) > (sl->flash_pgsz - 5)) { fprintf(stdout, "\r%3u/%3u pages written", (unsigned int)(off / sl->flash_pgsz), @@ -2912,29 +2869,13 @@ int stlink_write_flash( // TODO: check redo write operation } - fprintf(stdout, "\n"); - // reset lock bits - stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); - val |= (1 << 0) | (1 << 1) | (1 << 2); - stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); } else if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || (sl->flash_type == STLINK_FLASH_TYPE_F1_XL)) { - ILOG("Starting Flash write for VL/F0/F3/F1_XL core id\n"); - - // flash loader initialisation - if (stlink_flash_loader_init(sl, &fl) == -1) { - ELOG("stlink_flash_loader_init() == -1\n"); - return(-1); - } - int write_block_count = 0; - for (off = 0; off < len; off += sl->flash_pgsz) { // adjust last write size - size_t size = sl->flash_pgsz; - - if ((off + sl->flash_pgsz) > len) { size = len - off; } + size_t size = len - off > sl->flash_pgsz ? sl->flash_pgsz : len - off; // unlock and set programming mode unlock_flash_if(sl); @@ -2943,7 +2884,7 @@ int stlink_write_flash( DLOG("Finished unlocking flash, running loader!\n"); - if (stlink_flash_loader_run(sl, &fl, addr + (uint32_t)off, base + off, size) == -1) { + if (stlink_flash_loader_run(sl, fl, addr + (uint32_t)off, base + off, size) == -1) { ELOG("stlink_flash_loader_run(%#zx) failed! == -1\n", addr + off); return(-1); } @@ -2952,19 +2893,15 @@ int stlink_write_flash( if (sl->verbose >= 1) { // show progress; writing procedure is slow and previous errors are misleading - fprintf(stdout, "\r%3u/%lu pages written", ++write_block_count, - (unsigned long)((len + sl->flash_pgsz - 1) / sl->flash_pgsz)); + fprintf(stdout, "\r%3u/%3u pages written", ++write_block_count, + (unsigned int)((len + sl->flash_pgsz - 1) / sl->flash_pgsz)); fflush(stdout); } } - - fprintf(stdout, "\n"); + if (sl->verbose >= 1) { + fprintf(stdout, "\n"); + } } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { - ILOG("Starting Flash write for H7 core id\n"); - - unlock_flash_if(sl); // unlock the cr - set_flash_cr_pg(sl); // set programming mode - for (off = 0; off < len;) { // Program STM32H7x with 32-byte Flash words size_t chunk = (len - off > 32) ? 32 : len - off; @@ -2980,15 +2917,110 @@ int stlink_write_flash( fflush(stdout); } } - fprintf(stdout, "\n"); + if (sl->verbose >= 1) { + fprintf(stdout, "\n"); + } + } else { + return(-1); + } + + return(0); +} + +int stlink_flashloader_stop(stlink_t *sl) { + if ((sl->flash_type == STLINK_FLASH_TYPE_F4) || + (sl->flash_type == STLINK_FLASH_TYPE_F7) || + (sl->flash_type == STLINK_FLASH_TYPE_L4) || + (sl->flash_type == STLINK_FLASH_TYPE_WB) || + (sl->flash_type == STLINK_FLASH_TYPE_G0) || + (sl->flash_type == STLINK_FLASH_TYPE_G4) || + (sl->flash_type == STLINK_FLASH_TYPE_H7)) { clear_flash_cr_pg(sl); lock_flash(sl); - } else { - ELOG("unknown coreid, not sure how to write: %x\n", sl->core_id); + } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { + uint32_t val; + uint32_t flash_regs_base; + if (sl->chip_id == STLINK_CHIPID_STM32_L0 || + sl->chip_id == STLINK_CHIPID_STM32_L0_CAT5 || + sl->chip_id == STLINK_CHIPID_STM32_L0_CAT2 || + sl->chip_id == STLINK_CHIPID_STM32_L011) { + flash_regs_base = STM32L0_FLASH_REGS_ADDR; + } else { + flash_regs_base = STM32L_FLASH_REGS_ADDR; + } + // reset lock bits + stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); + val |= (1 << 0) | (1 << 1) | (1 << 2); + stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); + } + + return(0); +} + +int stlink_write_flash( + stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t len, uint8_t eraseonly) { + size_t off; + int ret; + flash_loader_t fl; + ILOG("Attempting to write %d (%#x) bytes to stm32 address: %u (%#x)\n", len, len, addr, addr); + // check addr range is inside the flash + stlink_calculate_pagesize(sl, addr); + + if (addr < sl->flash_base) { + ELOG("addr too low %#x < %#x\n", addr, sl->flash_base); + return(-1); + } else if ((addr + len) < addr) { + ELOG("addr overruns\n"); + return(-1); + } else if ((addr + len) > (sl->flash_base + sl->flash_size)) { + ELOG("addr too high\n"); + return(-1); + } else if (addr & 1) { + ELOG("unaligned addr 0x%x\n", addr); return(-1); + } else if (len & 1) { + WLOG("unaligned len 0x%x -- padding with zero\n", len); + len += 1; + } else if (addr & (sl->flash_pgsz - 1)) { + ELOG("addr not a multiple of current pagesize (%zd bytes), not supported, " + "check page start address and compare with flash module organisation " + "in related ST reference manual of your device.\n", sl->flash_pgsz); + return(-1); + } + + // make sure we've loaded the context with the chip details + stlink_core_id(sl); + + // Erase each page + int page_count = 0; + + for (off = 0; off < len; off += stlink_calculate_pagesize(sl, addr + (uint32_t)off)) { + // addr must be an addr inside the page + if (stlink_erase_flash_page(sl, addr + (uint32_t)off) == -1) { + ELOG("Failed to erase_flash_page(%#zx) == -1\n", addr + off); + return(-1); + } + + ILOG("Flash page at addr: 0x%08lx erased\n", (unsigned long)(addr + off)); + page_count++; } + ILOG("Finished erasing %d pages of %d (%#x) bytes\n", + page_count, sl->flash_pgsz, sl->flash_pgsz); + + if (eraseonly) { return(0); } + + ret = stlink_flashloader_start(sl, &fl); + if (ret) + return ret; + ret = stlink_flashloader_write(sl, &fl, addr, base, len); + if (ret) + return ret; + ret = stlink_flashloader_stop(sl); + if (ret) + return ret; + return(stlink_verify_write_flash(sl, addr, base, len)); } diff --git a/src/st-util/gdb-server.c b/src/st-util/gdb-server.c index c832098f1..5e8a2549e 100644 --- a/src/st-util/gdb-server.c +++ b/src/st-util/gdb-server.c @@ -847,13 +847,31 @@ static int flash_populate(stm32_addr_t addr, uint8_t* data, unsigned length) { static int flash_go(stlink_t *sl) { int error = -1; - + int ret; + flash_loader_t fl; + // some kinds of clock settings do not allow writing to flash. stlink_reset(sl); stlink_force_debug(sl); for (struct flash_block* fb = flash_root; fb; fb = fb->next) { - DLOG("flash_do: block %08x -> %04x\n", fb->addr, fb->length); + ILOG("flash_erase: block %08x -> %04x\n", fb->addr, fb->length); + + for (stm32_addr_t page = fb->addr; page < fb->addr + fb->length; page += (uint32_t)FLASH_PAGE) { + // update FLASH_PAGE + stlink_calculate_pagesize(sl, page); + + ILOG("flash_erase: page %08x\n", page); + ret = stlink_erase_flash_page(sl, page); + if (ret < 0) { goto error; } + } + } + + ret = stlink_flashloader_start(sl, &fl); + if (ret < 0) { goto error; } + + for (struct flash_block* fb = flash_root; fb; fb = fb->next) { + ILOG("flash_do: block %08x -> %04x\n", fb->addr, fb->length); for (stm32_addr_t page = fb->addr; page < fb->addr + fb->length; page += (uint32_t)FLASH_PAGE) { unsigned length = fb->length - (page - fb->addr); @@ -861,14 +879,14 @@ static int flash_go(stlink_t *sl) { // update FLASH_PAGE stlink_calculate_pagesize(sl, page); - DLOG("flash_do: page %08x\n", page); + ILOG("flash_do: page %08x\n", page); unsigned len = (length > FLASH_PAGE) ? (unsigned int)FLASH_PAGE : length; - int ret = stlink_write_flash(sl, page, fb->data + (page - fb->addr), len, 0); - + ret = stlink_flashloader_write(sl, &fl, page, fb->data + (page - fb->addr), len); if (ret < 0) { goto error; } } } + stlink_flashloader_stop(sl); stlink_reset(sl); error = 0; From a7ea06d7d9b44e9033de68980b4ae2816b13a435 Mon Sep 17 00:00:00 2001 From: Ant-ON Date: Tue, 3 Nov 2020 10:23:07 +0500 Subject: [PATCH 094/503] Remove duplicate register definitions --- inc/stlink.h | 19 ------------------- src/stlink-lib/reg.h | 13 +++++++++++-- src/stlink-lib/usb.c | 8 ++++---- 3 files changed, 15 insertions(+), 25 deletions(-) diff --git a/inc/stlink.h b/inc/stlink.h index e78b9569f..c4466b10b 100644 --- a/inc/stlink.h +++ b/inc/stlink.h @@ -83,25 +83,6 @@ enum target_state { #define STLINK_V3_MAX_FREQ_NB 10 -/* Cortex Debug Control Block */ -#define DCB_DHCSR 0xE000EDF0 -#define DCB_DCRSR 0xE000EDF4 -#define DCB_DCRDR 0xE000EDF8 -#define DCB_DEMCR 0xE000EDFC - -/* DCB_DHCSR bit and field definitions */ -#define DBGKEY (0xA05F << 16) -#define C_DEBUGEN (1 << 0) -#define C_HALT (1 << 1) -#define C_STEP (1 << 2) -#define C_MASKINTS (1 << 3) -#define S_REGRDY (1 << 16) -#define S_HALT (1 << 17) -#define S_SLEEP (1 << 18) -#define S_LOCKUP (1 << 19) -#define S_RETIRE_ST (1 << 24) -#define S_RESET_ST (1 << 25) - /* Map the relevant features, quirks and workaround for specific firmware version of stlink */ #define STLINK_F_HAS_TRACE (1 << 0) #define STLINK_F_HAS_SWD_SET_FREQ (1 << 1) diff --git a/src/stlink-lib/reg.h b/src/stlink-lib/reg.h index 653852440..926480648 100644 --- a/src/stlink-lib/reg.h +++ b/src/stlink-lib/reg.h @@ -16,8 +16,17 @@ /* Cortex™-M3 Technical Reference Manual */ /* Debug Halting Control and Status Register */ #define STLINK_REG_DHCSR 0xe000edf0 -#define STLINK_REG_DHCSR_DBGKEY 0xa05f0000 -#define STLINK_REG_DHCSR_S_RESET_ST 0x02000000 +#define STLINK_REG_DHCSR_DBGKEY (0xA05F << 16) +#define STLINK_REG_DHCSR_C_DEBUGEN (1 << 0) +#define STLINK_REG_DHCSR_C_HALT (1 << 1) +#define STLINK_REG_DHCSR_C_STEP (1 << 2) +#define STLINK_REG_DHCSR_C_MASKINTS (1 << 3) +#define STLINK_REG_DHCSR_S_REGRDY (1 << 16) +#define STLINK_REG_DHCSR_S_HALT (1 << 17) +#define STLINK_REG_DHCSR_S_SLEEP (1 << 18) +#define STLINK_REG_DHCSR_S_LOCKUP (1 << 19) +#define STLINK_REG_DHCSR_S_RETIRE_ST (1 << 24) +#define STLINK_REG_DHCSR_S_RESET_ST (1 << 25) #define STLINK_REG_DCRSR 0xe000edf4 #define STLINK_REG_DCRDR 0xe000edf8 diff --git a/src/stlink-lib/usb.c b/src/stlink-lib/usb.c index 6b914d805..4e805a709 100644 --- a/src/stlink-lib/usb.c +++ b/src/stlink-lib/usb.c @@ -385,15 +385,15 @@ int _stlink_usb_status_v2(stlink_t *sl) { int result; uint32_t status = 0; - result = _stlink_usb_read_debug32(sl, DCB_DHCSR, &status); + result = _stlink_usb_read_debug32(sl, STLINK_REG_DHCSR, &status); DLOG("core status: %08X\n", status); if (result != 0) { sl->core_stat = TARGET_UNKNOWN; } else { - if (status & S_HALT) { + if (status & STLINK_REG_DHCSR_C_HALT) { sl->core_stat = TARGET_HALTED; - } else if (status & S_RESET_ST) { + } else if (status & STLINK_REG_DHCSR_S_RESET_ST) { sl->core_stat = TARGET_RESET; } else { sl->core_stat = TARGET_RUNNING; @@ -616,7 +616,7 @@ int _stlink_usb_run(stlink_t* sl) { int res; if (sl->version.jtag_api != STLINK_JTAG_API_V1) { - res = _stlink_usb_write_debug32(sl, DCB_DHCSR, DBGKEY | C_DEBUGEN); + res = _stlink_usb_write_debug32(sl, STLINK_REG_DHCSR, STLINK_REG_DHCSR_DBGKEY | STLINK_REG_DHCSR_C_DEBUGEN); return(res); } From 922eba585b47d7ce5814a83fd96409c98acd9e6b Mon Sep 17 00:00:00 2001 From: Ant-ON Date: Tue, 3 Nov 2020 12:19:47 +0500 Subject: [PATCH 095/503] Optimized timeout of the chip reset function --- CMakeLists.txt | 12 ++++++++++++ src/stlink-lib/helper.c | 13 +++++++++++++ src/stlink-lib/helper.h | 6 ++++++ src/stlink-lib/usb.c | 21 ++++++++++----------- src/win32/sys_time.c | 20 ++++++++++++++++++++ src/win32/sys_time.h | 30 ++++++++++++++++++++++++++++++ 6 files changed, 91 insertions(+), 11 deletions(-) create mode 100644 src/stlink-lib/helper.c create mode 100644 src/stlink-lib/helper.h create mode 100644 src/win32/sys_time.c create mode 100644 src/win32/sys_time.h diff --git a/CMakeLists.txt b/CMakeLists.txt index fae458dd7..4ab43271e 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -60,6 +60,11 @@ if (STLINK_HAVE_SYS_MMAN_H) add_definitions(-DSTLINK_HAVE_SYS_MMAN_H) endif() +CHECK_INCLUDE_FILE(sys/time.h STLINK_HAVE_SYS_TIME_H) +if (STLINK_HAVE_SYS_TIME_H) + add_definitions(-DSTLINK_HAVE_SYS_TIME_H) +endif() + CHECK_INCLUDE_FILE(unistd.h STLINK_HAVE_UNISTD_H) if (STLINK_HAVE_UNISTD_H) add_definitions(-DSTLINK_HAVE_UNISTD_H) @@ -104,6 +109,7 @@ set(STLINK_HEADERS src/stlink-lib/md5.h src/stlink-lib/sg.h src/stlink-lib/usb.h + src/stlink-lib/helper.h ) set(STLINK_SOURCE @@ -114,6 +120,7 @@ set(STLINK_SOURCE src/stlink-lib/md5.c src/stlink-lib/sg.c src/stlink-lib/usb.c + src/stlink-lib/helper.c ) if (WIN32) @@ -132,6 +139,11 @@ if (WIN32) set(STLINK_SOURCE "${STLINK_SOURCE};src/win32/mmap.c") set(STLINK_HEADERS "${STLINK_HEADERS};src/win32/mmap.h") endif() + + if (NOT STLINK_HAVE_SYS_TIME_H) + set(STLINK_SOURCE "${STLINK_SOURCE};src/win32/sys_time.c") + set(STLINK_HEADERS "${STLINK_HEADERS};src/win32/sys_time.h") + endif() endif () ## Include test execution for test-targets for target Debug diff --git a/src/stlink-lib/helper.c b/src/stlink-lib/helper.c new file mode 100644 index 000000000..50c55230b --- /dev/null +++ b/src/stlink-lib/helper.c @@ -0,0 +1,13 @@ +#include + +#ifdef STLINK_HAVE_SYS_TIME_H +#include +#else +#include +#endif + +unsigned time_ms() { + struct timeval tv; + gettimeofday(&tv, NULL); + return (unsigned)tv.tv_sec * 1000 + tv.tv_usec / 1000; +} diff --git a/src/stlink-lib/helper.h b/src/stlink-lib/helper.h new file mode 100644 index 000000000..defd0504b --- /dev/null +++ b/src/stlink-lib/helper.h @@ -0,0 +1,6 @@ +#ifndef SYS_HELPER_H +#define SYS_HELPER_H + +unsigned time_ms(); + +#endif SYS_HELPER_H diff --git a/src/stlink-lib/usb.c b/src/stlink-lib/usb.c index 4e805a709..b502ca2a6 100644 --- a/src/stlink-lib/usb.c +++ b/src/stlink-lib/usb.c @@ -17,6 +17,7 @@ #endif #include +#include #include "usb.h" enum SCSI_Generic_Direction {SG_DXFER_TO_DEV = 0, SG_DXFER_FROM_DEV = 0x80}; @@ -509,10 +510,10 @@ int _stlink_usb_reset(stlink_t * sl) { unsigned char* const cmd = sl->c_buf; ssize_t size; uint32_t dhcsr; - int ret, i, rep_len = 2; + int ret, timeout, i, rep_len = 2; // clear S_RESET_ST in DHCSR registr - stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); + _stlink_usb_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); // send reset command i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); @@ -534,14 +535,14 @@ int _stlink_usb_reset(stlink_t * sl) { usleep(10000); dhcsr = 0; - ret = stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); + ret = _stlink_usb_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); if ((dhcsr & STLINK_REG_DHCSR_S_RESET_ST) == 0) { // reset not done yet // try reset through AIRCR so that NRST does not need to be connected WLOG("NRST is not connected\n"); DLOG("Using reset through SYSRESETREQ\n"); - ret = stlink_write_debug32(sl, STLINK_REG_AIRCR, STLINK_REG_AIRCR_VECTKEY | + ret = _stlink_usb_write_debug32(sl, STLINK_REG_AIRCR, STLINK_REG_AIRCR_VECTKEY | STLINK_REG_AIRCR_SYSRESETREQ); if (ret) return(ret); @@ -550,18 +551,16 @@ int _stlink_usb_reset(stlink_t * sl) { } // waiting for a reset within 500ms - for (i=0; i<50; i++) { + timeout = time_ms() + 500; + while (time_ms() < timeout) { // DDI0337E, p. 10-4, Debug Halting Control and Status Register dhcsr = STLINK_REG_DHCSR_S_RESET_ST; - stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); + _stlink_usb_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); if ((dhcsr&STLINK_REG_DHCSR_S_RESET_ST) == 0) - break; - usleep(10000); + return(0); } - if (i >= 50) - return(-1); - return(0); + return(-1); } int _stlink_usb_jtag_reset(stlink_t * sl, int value) { diff --git a/src/win32/sys_time.c b/src/win32/sys_time.c new file mode 100644 index 000000000..ea7c25dda --- /dev/null +++ b/src/win32/sys_time.c @@ -0,0 +1,20 @@ +#include +#include + +#include "sys_time.h" + +/* Simple gettimeofday implementation without converting Windows time to Linux time */ +int gettimeofday(struct timeval *tv, struct timezone *tz) { + FILETIME ftime; + ULARGE_INTEGER ulint; + + GetSystemTimeAsFileTime(&ftime); + ulint.LowPart = ftime.dwLowDateTime; + ulint.HighPart = ftime.dwHighDateTime; + + tv->tv_sec = (long)(ulint.QuadPart / 10000000L); + tv->tv_usec = (long)(ulint.QuadPart % 10000000L); + + return 0; + (void)tz; +} diff --git a/src/win32/sys_time.h b/src/win32/sys_time.h new file mode 100644 index 000000000..87c3a42fd --- /dev/null +++ b/src/win32/sys_time.h @@ -0,0 +1,30 @@ +#ifndef STLINK_TIME_H +#define STLINK_TIME_H + +#ifdef STLINK_HAVE_SYS_TIME_H +#include +#else + +struct timeval { + long tv_sec; + long tv_usec; +}; + +struct timezone { + int tz_minuteswest; + int tz_dsttime; +}; + +#ifdef __cplusplus +extern "C" { +#endif + +int gettimeofday(struct timeval *tv, struct timezone *tz); + +#ifdef __cplusplus +} +#endif + +#endif /* STLINK_HAVE_SYS_TIME_H */ + +#endif /* STLINK_TIME_H */ From ddd39354b545f6176345cce8f2d520bd109dcbe7 Mon Sep 17 00:00:00 2001 From: Ant-ON Date: Tue, 3 Nov 2020 14:49:19 +0500 Subject: [PATCH 096/503] Trying to use a soft reset before starting debugging --- inc/stlink.h | 1 + src/common.c | 50 ++++++++++++++++++++++++++++++++++++---- src/st-util/gdb-server.c | 13 +++++++---- src/stlink-lib/reg.h | 2 ++ 4 files changed, 57 insertions(+), 9 deletions(-) diff --git a/inc/stlink.h b/inc/stlink.h index c4466b10b..2ec2db367 100644 --- a/inc/stlink.h +++ b/inc/stlink.h @@ -223,6 +223,7 @@ void stlink_close(stlink_t *sl); int stlink_core_id(stlink_t *sl); int stlink_reset(stlink_t *sl); int stlink_jtag_reset(stlink_t *sl, int value); +int stlink_soft_reset(stlink_t *sl, int halt_on_reset); int stlink_run(stlink_t *sl); int stlink_status(stlink_t *sl); int stlink_version(stlink_t *sl); diff --git a/src/common.c b/src/common.c index 71caeeaa8..ed3f7b222 100644 --- a/src/common.c +++ b/src/common.c @@ -1416,6 +1416,48 @@ int stlink_jtag_reset(stlink_t *sl, int value) { return(sl->backend->jtag_reset(sl, value)); } +int stlink_soft_reset(stlink_t *sl, int halt_on_reset) { + int ret; + uint32_t dhcsr, demcr; + + DLOG("*** stlink_soft_reset ***\n"); + + // halt core and enable debugging (if not already done) + // C_DEBUGEN is required to Halt on reset (DDI0337E, p. 10-6) + _stlink_usb_write_debug32(sl, STLINK_REG_DHCSR, STLINK_REG_DHCSR_DBGKEY | + STLINK_REG_DHCSR_C_HALT | STLINK_REG_DHCSR_C_DEBUGEN); + + // enable Halt on reset by set VC_CORERESET and TRCENA (DDI0337E, p. 10-10) + stlink_read_debug32(sl, STLINK_REG_CM3_DEMCR, &demcr); + if (halt_on_reset) { + demcr |= STLINK_REG_CM3_DEMCR_TRCENA | STLINK_REG_CM3_DEMCR_VC_CORERESET; + } else { + demcr &= ~STLINK_REG_CM3_DEMCR_VC_CORERESET; + } + stlink_write_debug32(sl, STLINK_REG_CM3_DEMCR, demcr); + + // clear S_RESET_ST in DHCSR register + stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); + + // soft reset (core reset) by SYSRESETREQ (DDI0337E, p. 8-23) + ret = stlink_write_debug32(sl, STLINK_REG_AIRCR, STLINK_REG_AIRCR_VECTKEY | + STLINK_REG_AIRCR_SYSRESETREQ); + if (ret) + return(ret); + + // waiting for a reset within 500ms + timeout = time_ms() + 500; + while (time_ms() < timeout) { + // DDI0337E, p. 10-4, Debug Halting Control and Status Register + dhcsr = STLINK_REG_DHCSR_S_RESET_ST; + stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); + if ((dhcsr&STLINK_REG_DHCSR_S_RESET_ST) == 0) + return(0); + } + + return(-1); +} + int stlink_run(stlink_t *sl) { DLOG("*** stlink_run ***\n"); return(sl->backend->run(sl)); @@ -2899,8 +2941,8 @@ int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t addr } } if (sl->verbose >= 1) { - fprintf(stdout, "\n"); - } + fprintf(stdout, "\n"); + } } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { for (off = 0; off < len;) { // Program STM32H7x with 32-byte Flash words @@ -2918,8 +2960,8 @@ int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t addr } } if (sl->verbose >= 1) { - fprintf(stdout, "\n"); - } + fprintf(stdout, "\n"); + } } else { return(-1); } diff --git a/src/st-util/gdb-server.c b/src/st-util/gdb-server.c index 5e8a2549e..4eca5819e 100644 --- a/src/st-util/gdb-server.c +++ b/src/st-util/gdb-server.c @@ -591,9 +591,9 @@ static void init_data_watchpoints(stlink_t *sl) { uint32_t data; DLOG("init watchpoints\n"); + // set TRCENA in debug command to turn on DWT unit stlink_read_debug32(sl, STLINK_REG_CM3_DEMCR, &data); - data |= 1 << 24; - // set TRCENA in debug command to turn on DWT unit + data |= STLINK_REG_CM3_DEMCR_TRCENA; stlink_write_debug32(sl, STLINK_REG_CM3_DEMCR, data); // make sure all watchpoints are cleared @@ -887,7 +887,7 @@ static int flash_go(stlink_t *sl) { } stlink_flashloader_stop(sl); - stlink_reset(sl); + //stlink_reset(sl); error = 0; error: @@ -1804,13 +1804,16 @@ int serve(stlink_t *sl, st_state_t *st) { case 'R': { // reset the core. - ret = stlink_reset(sl); - + ret = stlink_soft_reset(sl, 1 /* halt on reset */); if (ret) { DLOG("R packet : stlink_reset failed\n"); } init_code_breakpoints(sl); init_data_watchpoints(sl); + if (stlink_status(sl) == TARGET_HALTED) { + stlink_run(sl); + } + attached = 1; reply = strdup("OK"); diff --git a/src/stlink-lib/reg.h b/src/stlink-lib/reg.h index 926480648..d9323a042 100644 --- a/src/stlink-lib/reg.h +++ b/src/stlink-lib/reg.h @@ -9,6 +9,8 @@ #define STLINK_REG_CM7_FP_LAR_KEY 0xC5ACCE55 #define STLINK_REG_CM3_DEMCR 0xE000EDFC +#define STLINK_REG_CM3_DEMCR_TRCENA (1 << 24) +#define STLINK_REG_CM3_DEMCR_VC_CORERESET (1 << 0) #define STLINK_REG_CM3_DWT_COMPn(n) (0xE0001020 + n*16) #define STLINK_REG_CM3_DWT_MASKn(n) (0xE0001024 + n*16) #define STLINK_REG_CM3_DWT_FUNn(n) (0xE0001028 + n*16) From b401eaff9a144f973f44f5914a70fc82da36d39f Mon Sep 17 00:00:00 2001 From: Ant-ON Date: Thu, 5 Nov 2020 16:57:30 +0500 Subject: [PATCH 097/503] Improve soft reset with core halt --- src/common.c | 58 +++++++++++++++++++++++++++++----------- src/st-util/gdb-server.c | 22 +++++++-------- src/stlink-lib/helper.c | 2 ++ src/stlink-lib/helper.h | 2 +- src/stlink-lib/reg.h | 13 +++++++-- src/stlink-lib/usb.c | 14 ++++------ 6 files changed, 71 insertions(+), 40 deletions(-) diff --git a/src/common.c b/src/common.c index ed3f7b222..cdf0fa497 100644 --- a/src/common.c +++ b/src/common.c @@ -14,6 +14,7 @@ #include #include #include +#include #ifdef STLINK_HAVE_SYS_MMAN_H #include @@ -1418,44 +1419,71 @@ int stlink_jtag_reset(stlink_t *sl, int value) { int stlink_soft_reset(stlink_t *sl, int halt_on_reset) { int ret; - uint32_t dhcsr, demcr; + unsigned timeout; + uint32_t dhcsr, dfsr; - DLOG("*** stlink_soft_reset ***\n"); + ELOG("*** stlink_soft_reset %s***\n", halt_on_reset?"(halt) ":""); // halt core and enable debugging (if not already done) // C_DEBUGEN is required to Halt on reset (DDI0337E, p. 10-6) - _stlink_usb_write_debug32(sl, STLINK_REG_DHCSR, STLINK_REG_DHCSR_DBGKEY | + stlink_write_debug32(sl, STLINK_REG_DHCSR, STLINK_REG_DHCSR_DBGKEY | STLINK_REG_DHCSR_C_HALT | STLINK_REG_DHCSR_C_DEBUGEN); - + // enable Halt on reset by set VC_CORERESET and TRCENA (DDI0337E, p. 10-10) - stlink_read_debug32(sl, STLINK_REG_CM3_DEMCR, &demcr); if (halt_on_reset) { - demcr |= STLINK_REG_CM3_DEMCR_TRCENA | STLINK_REG_CM3_DEMCR_VC_CORERESET; + stlink_write_debug32(sl, STLINK_REG_CM3_DEMCR, STLINK_REG_CM3_DEMCR_TRCENA | + STLINK_REG_CM3_DEMCR_VC_HARDERR | STLINK_REG_CM3_DEMCR_VC_BUSERR | + STLINK_REG_CM3_DEMCR_VC_CORERESET); + + // clear VCATCH in the DFSR register + stlink_write_debug32(sl, STLINK_REG_DFSR, STLINK_REG_DFSR_VCATCH); } else { - demcr &= ~STLINK_REG_CM3_DEMCR_VC_CORERESET; + stlink_write_debug32(sl, STLINK_REG_CM3_DEMCR, STLINK_REG_CM3_DEMCR_TRCENA | + STLINK_REG_CM3_DEMCR_VC_HARDERR | STLINK_REG_CM3_DEMCR_VC_BUSERR); } - stlink_write_debug32(sl, STLINK_REG_CM3_DEMCR, demcr); - // clear S_RESET_ST in DHCSR register + // clear S_RESET_ST in the DHCSR register stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); - + // soft reset (core reset) by SYSRESETREQ (DDI0337E, p. 8-23) ret = stlink_write_debug32(sl, STLINK_REG_AIRCR, STLINK_REG_AIRCR_VECTKEY | STLINK_REG_AIRCR_SYSRESETREQ); - if (ret) + if (ret) { + ELOG("Soft reset failed: error write to AIRCR\n"); return(ret); + } // waiting for a reset within 500ms + // DDI0337E, p. 10-4, Debug Halting Control and Status Register timeout = time_ms() + 500; while (time_ms() < timeout) { // DDI0337E, p. 10-4, Debug Halting Control and Status Register dhcsr = STLINK_REG_DHCSR_S_RESET_ST; stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); - if ((dhcsr&STLINK_REG_DHCSR_S_RESET_ST) == 0) - return(0); + if ((dhcsr&STLINK_REG_DHCSR_S_RESET_ST) == 0) { + if (halt_on_reset) { + // waiting halt by the SYSRESETREQ exception + // DDI0403E, p. C1-699, Debug Fault Status Register + dfsr = 0; + stlink_read_debug32(sl, STLINK_REG_DFSR, &dfsr); + if ((dfsr&STLINK_REG_DFSR_VCATCH) == 0) { + continue; + } + } + timeout = 0; + break; + } } - return(-1); + // reset DFSR register. DFSR is power-on reset only (DDI0337H, p. 7-5) + stlink_write_debug32(sl, STLINK_REG_DFSR, STLINK_REG_DFSR_CLEAR); + + if (timeout) { + ELOG("Soft reset failed: timeout\n"); + return(-1); + } + + return(0); } int stlink_run(stlink_t *sl) { @@ -2735,7 +2763,7 @@ int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { if (voltage == -1) { ELOG("Failed to read Target voltage\n"); - return(voltage); + return(-1); } if (sl->flash_type == STLINK_FLASH_TYPE_L4) { diff --git a/src/st-util/gdb-server.c b/src/st-util/gdb-server.c index 4eca5819e..d69ac0626 100644 --- a/src/st-util/gdb-server.c +++ b/src/st-util/gdb-server.c @@ -591,7 +591,7 @@ static void init_data_watchpoints(stlink_t *sl) { uint32_t data; DLOG("init watchpoints\n"); - // set TRCENA in debug command to turn on DWT unit + // set TRCENA in debug command to turn on DWT unit stlink_read_debug32(sl, STLINK_REG_CM3_DEMCR, &data); data |= STLINK_REG_CM3_DEMCR_TRCENA; stlink_write_debug32(sl, STLINK_REG_CM3_DEMCR, data); @@ -849,7 +849,7 @@ static int flash_go(stlink_t *sl) { int error = -1; int ret; flash_loader_t fl; - + // some kinds of clock settings do not allow writing to flash. stlink_reset(sl); stlink_force_debug(sl); @@ -863,12 +863,12 @@ static int flash_go(stlink_t *sl) { ILOG("flash_erase: page %08x\n", page); ret = stlink_erase_flash_page(sl, page); - if (ret < 0) { goto error; } + if (ret) { goto error; } } } ret = stlink_flashloader_start(sl, &fl); - if (ret < 0) { goto error; } + if (ret) { goto error; } for (struct flash_block* fb = flash_root; fb; fb = fb->next) { ILOG("flash_do: block %08x -> %04x\n", fb->addr, fb->length); @@ -882,12 +882,12 @@ static int flash_go(stlink_t *sl) { ILOG("flash_do: page %08x\n", page); unsigned len = (length > FLASH_PAGE) ? (unsigned int)FLASH_PAGE : length; ret = stlink_flashloader_write(sl, &fl, page, fb->data + (page - fb->addr), len); - if (ret < 0) { goto error; } + if (ret) { goto error; } } } stlink_flashloader_stop(sl); - //stlink_reset(sl); + stlink_soft_reset(sl, 1 /* halt on reset */); error = 0; error: @@ -1390,8 +1390,8 @@ int serve(stlink_t *sl, st_state_t *st) { free(decoded); } else if (!strcmp(cmdName, "FlashDone")) { - if (flash_go(sl) < 0) { - reply = strdup("E00"); + if (flash_go(sl)) { + reply = strdup("E08"); } else { reply = strdup("OK"); } @@ -1804,16 +1804,12 @@ int serve(stlink_t *sl, st_state_t *st) { case 'R': { // reset the core. - ret = stlink_soft_reset(sl, 1 /* halt on reset */); + ret = stlink_reset(sl); if (ret) { DLOG("R packet : stlink_reset failed\n"); } init_code_breakpoints(sl); init_data_watchpoints(sl); - if (stlink_status(sl) == TARGET_HALTED) { - stlink_run(sl); - } - attached = 1; reply = strdup("OK"); diff --git a/src/stlink-lib/helper.c b/src/stlink-lib/helper.c index 50c55230b..8b2c8e8f7 100644 --- a/src/stlink-lib/helper.c +++ b/src/stlink-lib/helper.c @@ -1,5 +1,7 @@ #include +#include + #ifdef STLINK_HAVE_SYS_TIME_H #include #else diff --git a/src/stlink-lib/helper.h b/src/stlink-lib/helper.h index defd0504b..12c2ea2a7 100644 --- a/src/stlink-lib/helper.h +++ b/src/stlink-lib/helper.h @@ -3,4 +3,4 @@ unsigned time_ms(); -#endif SYS_HELPER_H +#endif /* SYS_HELPER_H */ diff --git a/src/stlink-lib/reg.h b/src/stlink-lib/reg.h index d9323a042..2e93dc5b1 100644 --- a/src/stlink-lib/reg.h +++ b/src/stlink-lib/reg.h @@ -10,6 +10,8 @@ #define STLINK_REG_CM3_DEMCR 0xE000EDFC #define STLINK_REG_CM3_DEMCR_TRCENA (1 << 24) +#define STLINK_REG_CM3_DEMCR_VC_HARDERR (1 << 10) +#define STLINK_REG_CM3_DEMCR_VC_BUSERR (1 << 8) #define STLINK_REG_CM3_DEMCR_VC_CORERESET (1 << 0) #define STLINK_REG_CM3_DWT_COMPn(n) (0xE0001020 + n*16) #define STLINK_REG_CM3_DWT_MASKn(n) (0xE0001024 + n*16) @@ -17,6 +19,12 @@ /* Cortex™-M3 Technical Reference Manual */ /* Debug Halting Control and Status Register */ +#define STLINK_REG_DFSR 0xE000ED30 +#define STLINK_REG_DFSR_HALT (1 << 0) +#define STLINK_REG_DFSR_BKPT (1 << 1) +#define STLINK_REG_DFSR_VCATCH (1 << 3) +#define STLINK_REG_DFSR_EXTERNAL (1 << 4) +#define STLINK_REG_DFSR_CLEAR 0x0000001F #define STLINK_REG_DHCSR 0xe000edf0 #define STLINK_REG_DHCSR_DBGKEY (0xA05F << 16) #define STLINK_REG_DHCSR_C_DEBUGEN (1 << 0) @@ -34,8 +42,9 @@ /* Application Interrupt and Reset Control Register */ #define STLINK_REG_AIRCR 0xe000ed0c -#define STLINK_REG_AIRCR_VECTKEY 0x05fa0000 -#define STLINK_REG_AIRCR_SYSRESETREQ 0x00000004 +#define STLINK_REG_AIRCR_VECTKEY 0x05fa0000 +#define STLINK_REG_AIRCR_SYSRESETREQ 0x00000004 +#define STLINK_REG_AIRCR_VECTRESET 0x00000001 /* ARM Cortex-M7 Processor Technical Reference Manual */ /* Cache Control and Status Register */ diff --git a/src/stlink-lib/usb.c b/src/stlink-lib/usb.c index b502ca2a6..7909a4e69 100644 --- a/src/stlink-lib/usb.c +++ b/src/stlink-lib/usb.c @@ -510,7 +510,8 @@ int _stlink_usb_reset(stlink_t * sl) { unsigned char* const cmd = sl->c_buf; ssize_t size; uint32_t dhcsr; - int ret, timeout, i, rep_len = 2; + unsigned timeout; + int i, rep_len = 2; // clear S_RESET_ST in DHCSR registr _stlink_usb_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); @@ -535,19 +536,14 @@ int _stlink_usb_reset(stlink_t * sl) { usleep(10000); dhcsr = 0; - ret = _stlink_usb_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); + _stlink_usb_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); if ((dhcsr & STLINK_REG_DHCSR_S_RESET_ST) == 0) { // reset not done yet // try reset through AIRCR so that NRST does not need to be connected - + WLOG("NRST is not connected\n"); DLOG("Using reset through SYSRESETREQ\n"); - ret = _stlink_usb_write_debug32(sl, STLINK_REG_AIRCR, STLINK_REG_AIRCR_VECTKEY | - STLINK_REG_AIRCR_SYSRESETREQ); - if (ret) - return(ret); - - usleep(10000); + return stlink_soft_reset(sl, 0); } // waiting for a reset within 500ms From 85f0e939111d7350bdd40746161da7ef656d5151 Mon Sep 17 00:00:00 2001 From: Ant-ON Date: Thu, 5 Nov 2020 17:00:48 +0500 Subject: [PATCH 098/503] Add switch to Thumb mode before starting flash loader --- src/stlink-lib/flash_loader.c | 26 ++++++++++++++++++++++---- 1 file changed, 22 insertions(+), 4 deletions(-) diff --git a/src/stlink-lib/flash_loader.c b/src/stlink-lib/flash_loader.c index 7de485ca3..c86aefbf7 100644 --- a/src/stlink-lib/flash_loader.c +++ b/src/stlink-lib/flash_loader.c @@ -316,6 +316,8 @@ int stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t targe int i = 0; size_t count = 0; uint32_t flash_base = 0; + const char *error = NULL; + uint32_t dhcsr, dfsr; DLOG("Running flash loader, write address:%#x, size: %u\n", target, (unsigned int)size); @@ -354,6 +356,13 @@ int stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t targe // only used on VL/F1_XL, but harmless for others stlink_write_reg(sl, fl->loader_addr, 15); // pc register + /* Make sure we are in Thumb mode */ + stlink_read_reg(sl, 16, &rr); + if ((rr.xpsr & (1 << 24)) == 0) { + ILOG("Go to Thumb mode\n"); + stlink_write_reg(sl, rr.xpsr | (1 << 24), 16); + } + /* Run loader */ stlink_run(sl); @@ -376,17 +385,26 @@ int stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t targe } if (i >= WAIT_ROUNDS) { - ELOG("flash loader run error\n"); - return(-1); + error = "Flash loader run error"; + goto error; } // check written byte count stlink_read_reg(sl, 2, &rr); if (rr.r[2] != 0) { - ELOG("write error, count == %u\n", rr.r[2]); - return(-1); + error = "Write error"; + goto error; } return(0); + +error: + dhcsr = dfsr = 0; + stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); + stlink_read_debug32(sl, STLINK_REG_DFSR, &dfsr); + stlink_read_all_regs(sl, &rr); + ELOG("%s (R2 0x%08X R15 0x%08X DHCSR 0x%08X DFSR 0x%08X)\n", error, rr.r[2], rr.r[15], dhcsr, dfsr); + + return(-1); } From 0135a0ea162e72a6d15de768140522078bb6bf81 Mon Sep 17 00:00:00 2001 From: Ant-ON Date: Thu, 5 Nov 2020 18:50:10 +0500 Subject: [PATCH 099/503] Expand and simplify stlink V2 + support --- src/stlink-lib/usb.c | 41 +++++++++++++++++++++++++++++------------ 1 file changed, 29 insertions(+), 12 deletions(-) diff --git a/src/stlink-lib/usb.c b/src/stlink-lib/usb.c index 7909a4e69..92ad4cbc5 100644 --- a/src/stlink-lib/usb.c +++ b/src/stlink-lib/usb.c @@ -262,7 +262,7 @@ int _stlink_usb_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data) { } int _stlink_usb_get_rw_status(stlink_t *sl) { - if (sl->version.jtag_api == STLINK_JTAG_API_V1) { return(-1); } + if (sl->version.jtag_api == STLINK_JTAG_API_V1) { return(0); } unsigned char* const rdata = sl->q_buf; struct stlink_libusb * const slu = sl->backend_data; @@ -355,15 +355,17 @@ int _stlink_usb_core_id(stlink_t * sl) { unsigned char* const cmd = sl->c_buf; unsigned char* const data = sl->q_buf; ssize_t size; - int rep_len = sl->version.jtag_api == STLINK_JTAG_API_V1 ? 4 : 12; + int offset, rep_len = sl->version.jtag_api == STLINK_JTAG_API_V1 ? 4 : 12; int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); cmd[i++] = STLINK_DEBUG_COMMAND; if (sl->version.jtag_api == STLINK_JTAG_API_V1) { cmd[i++] = STLINK_DEBUG_READCOREID; + offset = 0; } else { cmd[i++] = STLINK_DEBUG_APIV2_READ_IDCODES; + offset = 4; } size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); @@ -373,11 +375,7 @@ int _stlink_usb_core_id(stlink_t * sl) { return(-1); } - if (sl->version.jtag_api == STLINK_JTAG_API_V1) { - sl->core_id = read_uint32(data, 0); - } else { - sl->core_id = read_uint32(data, 4); - } + sl->core_id = read_uint32(data, offset); return(0); } @@ -440,6 +438,14 @@ int _stlink_usb_status(stlink_t * sl) { int _stlink_usb_force_debug(stlink_t *sl) { struct stlink_libusb *slu = sl->backend_data; + + int res; + + if (sl->version.jtag_api != STLINK_JTAG_API_V1) { + res = _stlink_usb_write_debug32(sl, STLINK_REG_DHCSR, STLINK_REG_DHCSR_DBGKEY | STLINK_REG_DHCSR_C_HALT | STLINK_REG_DHCSR_C_DEBUGEN); + return(res); + } + unsigned char* const data = sl->q_buf; unsigned char* const cmd = sl->c_buf; ssize_t size; @@ -583,6 +589,17 @@ int _stlink_usb_jtag_reset(stlink_t * sl, int value) { int _stlink_usb_step(stlink_t* sl) { struct stlink_libusb * const slu = sl->backend_data; + + if (sl->version.jtag_api != STLINK_JTAG_API_V1) { + // emulates the JTAG v1 API by using DHCSR + _stlink_usb_write_debug32(sl, STLINK_REG_DHCSR, STLINK_REG_DHCSR_DBGKEY | STLINK_REG_DHCSR_C_HALT | + STLINK_REG_DHCSR_C_MASKINTS | STLINK_REG_DHCSR_C_DEBUGEN); + _stlink_usb_write_debug32(sl, STLINK_REG_DHCSR, STLINK_REG_DHCSR_DBGKEY | STLINK_REG_DHCSR_C_STEP | + STLINK_REG_DHCSR_C_MASKINTS | STLINK_REG_DHCSR_C_DEBUGEN); + return _stlink_usb_write_debug32(sl, STLINK_REG_DHCSR, STLINK_REG_DHCSR_DBGKEY | STLINK_REG_DHCSR_C_HALT | + STLINK_REG_DHCSR_C_DEBUGEN); + } + unsigned char* const data = sl->q_buf; unsigned char* const cmd = sl->c_buf; ssize_t size; @@ -792,11 +809,11 @@ int _stlink_usb_read_all_regs(stlink_t *sl, struct stlink_reg *regp) { if (sl->verbose < 2) { return(0); } - DLOG("xpsr = 0x%08x\n", read_uint32(sl->q_buf, reg_offset + 64)); - DLOG("main_sp = 0x%08x\n", read_uint32(sl->q_buf, reg_offset + 68)); - DLOG("process_sp = 0x%08x\n", read_uint32(sl->q_buf, reg_offset + 72)); - DLOG("rw = 0x%08x\n", read_uint32(sl->q_buf, reg_offset + 76)); - DLOG("rw2 = 0x%08x\n", read_uint32(sl->q_buf, reg_offset + 80)); + DLOG("xpsr = 0x%08x\n", regp->xpsr); + DLOG("main_sp = 0x%08x\n", regp->main_sp); + DLOG("process_sp = 0x%08x\n", regp->process_sp); + DLOG("rw = 0x%08x\n", regp->rw); + DLOG("rw2 = 0x%08x\n", regp->rw2); return(0); } From f3c824c83e10548b89513b12f55f113452259a97 Mon Sep 17 00:00:00 2001 From: Ant-ON Date: Thu, 5 Nov 2020 18:54:03 +0500 Subject: [PATCH 100/503] More robust fw flash by gdb --- src/common.c | 2 +- src/st-util/gdb-server.c | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/src/common.c b/src/common.c index cdf0fa497..89f27aa66 100644 --- a/src/common.c +++ b/src/common.c @@ -1422,7 +1422,7 @@ int stlink_soft_reset(stlink_t *sl, int halt_on_reset) { unsigned timeout; uint32_t dhcsr, dfsr; - ELOG("*** stlink_soft_reset %s***\n", halt_on_reset?"(halt) ":""); + DLOG("*** stlink_soft_reset %s***\n", halt_on_reset?"(halt) ":""); // halt core and enable debugging (if not already done) // C_DEBUGEN is required to Halt on reset (DDI0337E, p. 10-6) diff --git a/src/st-util/gdb-server.c b/src/st-util/gdb-server.c index d69ac0626..63ba68fcf 100644 --- a/src/st-util/gdb-server.c +++ b/src/st-util/gdb-server.c @@ -853,6 +853,8 @@ static int flash_go(stlink_t *sl) { // some kinds of clock settings do not allow writing to flash. stlink_reset(sl); stlink_force_debug(sl); + // delay to ensure that STM32 HSI clock and others have started up fully + usleep(10000); for (struct flash_block* fb = flash_root; fb; fb = fb->next) { ILOG("flash_erase: block %08x -> %04x\n", fb->addr, fb->length); From 43019fcde99b8e745a767b8e2c307d5868c09878 Mon Sep 17 00:00:00 2001 From: Ant-ON Date: Thu, 5 Nov 2020 19:34:22 +0500 Subject: [PATCH 101/503] Fix change SWD frequency of stlink v3 --- doc/dev/developer.txt | 2 +- inc/backend.h | 2 +- inc/stlink.h | 2 +- src/common.c | 4 +-- src/stlink-lib/usb.c | 68 +++++++++++++++++-------------------------- 5 files changed, 31 insertions(+), 47 deletions(-) diff --git a/doc/dev/developer.txt b/doc/dev/developer.txt index 32afd4352..9c4da22f7 100644 --- a/doc/dev/developer.txt +++ b/doc/dev/developer.txt @@ -300,7 +300,7 @@ Return: -1 for error. 0 for success. int stlink_current_mode(stlink_t *sl); int stlink_force_debug(stlink_t *sl); int stlink_target_voltage(stlink_t *sl); - int stlink_set_swdclk(stlink_t *sl, uint16_t divisor); + int stlink_set_swdclk(stlink_t *sl, int freq_khz); int stlink_erase_flash_mass(stlink_t* sl); int stlink_write_flash(stlink_t* sl, stm32_addr_t address, uint8_t* data, uint32_t length, uint8_t eraseonly); diff --git a/inc/backend.h b/inc/backend.h index f852da05d..d60708031 100644 --- a/inc/backend.h +++ b/inc/backend.h @@ -28,7 +28,7 @@ int (*current_mode) (stlink_t * stl); int (*force_debug) (stlink_t *sl); int32_t (*target_voltage) (stlink_t *sl); - int (*set_swdclk) (stlink_t * stl, uint16_t divisor); + int (*set_swdclk) (stlink_t * stl, int freq_khz); } stlink_backend_t; #endif // STLINK_BACKEND_H_ diff --git a/inc/stlink.h b/inc/stlink.h index 2ec2db367..7fce9d3dc 100644 --- a/inc/stlink.h +++ b/inc/stlink.h @@ -242,7 +242,7 @@ int stlink_step(stlink_t *sl); int stlink_current_mode(stlink_t *sl); int stlink_force_debug(stlink_t *sl); int stlink_target_voltage(stlink_t *sl); -int stlink_set_swdclk(stlink_t *sl, uint16_t divisor); +int stlink_set_swdclk(stlink_t *sl, int freq_khz); int stlink_erase_flash_mass(stlink_t* sl); int stlink_write_flash(stlink_t* sl, stm32_addr_t address, uint8_t* data, uint32_t length, uint8_t eraseonly); diff --git a/src/common.c b/src/common.c index 89f27aa66..7321b39a4 100644 --- a/src/common.c +++ b/src/common.c @@ -1491,9 +1491,9 @@ int stlink_run(stlink_t *sl) { return(sl->backend->run(sl)); } -int stlink_set_swdclk(stlink_t *sl, uint16_t divisor) { +int stlink_set_swdclk(stlink_t *sl, int freq_khz) { DLOG("*** set_swdclk ***\n"); - return(sl->backend->set_swdclk(sl, divisor)); + return(sl->backend->set_swdclk(sl, freq_khz)); } int stlink_status(stlink_t *sl) { diff --git a/src/stlink-lib/usb.c b/src/stlink-lib/usb.c index 92ad4cbc5..f5a91abf4 100644 --- a/src/stlink-lib/usb.c +++ b/src/stlink-lib/usb.c @@ -651,7 +651,7 @@ int _stlink_usb_run(stlink_t* sl) { return(0); } -int _stlink_usb_set_swdclk(stlink_t* sl, uint16_t clk_divisor) { +int _stlink_usb_set_swdclk(stlink_t* sl, int clk_freq) { struct stlink_libusb * const slu = sl->backend_data; unsigned char* const data = sl->q_buf; unsigned char* const cmd = sl->c_buf; @@ -661,6 +661,28 @@ int _stlink_usb_set_swdclk(stlink_t* sl, uint16_t clk_divisor) { // clock speed only supported by stlink/v2 and for firmware >= 22 if (sl->version.stlink_v == 2 && sl->version.jtag_v >= 22) { + uint16_t clk_divisor; + if (clk_freq) { + const uint32_t map[] = {5, 15, 25, 50, 100, 125, 240, 480, 950, 1200, 1800, 4000}; + int speed_index = _stlink_match_speed_map(map, STLINK_ARRAY_SIZE(map), clk_freq); + switch (map[speed_index]) { + case 5: clk_divisor = STLINK_SWDCLK_5KHZ_DIVISOR; break; + case 15: clk_divisor = STLINK_SWDCLK_15KHZ_DIVISOR; break; + case 25: clk_divisor = STLINK_SWDCLK_25KHZ_DIVISOR; break; + case 50: clk_divisor = STLINK_SWDCLK_50KHZ_DIVISOR; break; + case 100: clk_divisor = STLINK_SWDCLK_100KHZ_DIVISOR; break; + case 125: clk_divisor = STLINK_SWDCLK_125KHZ_DIVISOR; break; + case 240: clk_divisor = STLINK_SWDCLK_240KHZ_DIVISOR; break; + case 480: clk_divisor = STLINK_SWDCLK_480KHZ_DIVISOR; break; + case 950: clk_divisor = STLINK_SWDCLK_950KHZ_DIVISOR; break; + case 1200: clk_divisor = STLINK_SWDCLK_1P2MHZ_DIVISOR; break; + default: + case 1800: clk_divisor = STLINK_SWDCLK_1P8MHZ_DIVISOR; break; + case 4000: clk_divisor = STLINK_SWDCLK_4MHZ_DIVISOR; break; + } + } else + clk_divisor = STLINK_SWDCLK_1P8MHZ_DIVISOR; + i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); cmd[i++] = STLINK_DEBUG_COMMAND; @@ -691,7 +713,6 @@ int _stlink_usb_set_swdclk(stlink_t* sl, uint16_t clk_divisor) { } int speeds_size = data[8]; - if (speeds_size > STLINK_V3_MAX_FREQ_NB) { speeds_size = STLINK_V3_MAX_FREQ_NB; } @@ -701,7 +722,8 @@ int _stlink_usb_set_swdclk(stlink_t* sl, uint16_t clk_divisor) { // Set to zero all the next entries for (i = speeds_size; i < STLINK_V3_MAX_FREQ_NB; i++) map[i] = 0; - speed_index = _stlink_match_speed_map(map, STLINK_ARRAY_SIZE(map), 1800); + if (!clk_freq) clk_freq = 1800; // set default frequency + speed_index = _stlink_match_speed_map(map, STLINK_ARRAY_SIZE(map), clk_freq); i = fill_command(sl, SG_DXFER_FROM_DEV, 16); @@ -1228,45 +1250,7 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, int reset, char serial[STL // should be done at this speed too // set the stlink clock speed (default is 1800kHz) DLOG("JTAG/SWD freq set to %d\n", freq); - - switch (freq) { - case 5: - stlink_set_swdclk(sl, STLINK_SWDCLK_5KHZ_DIVISOR); - break; - case 15: - stlink_set_swdclk(sl, STLINK_SWDCLK_15KHZ_DIVISOR); - break; - case 25: - stlink_set_swdclk(sl, STLINK_SWDCLK_25KHZ_DIVISOR); - break; - case 50: - stlink_set_swdclk(sl, STLINK_SWDCLK_50KHZ_DIVISOR); - break; - case 100: - stlink_set_swdclk(sl, STLINK_SWDCLK_100KHZ_DIVISOR); - break; - case 125: - stlink_set_swdclk(sl, STLINK_SWDCLK_125KHZ_DIVISOR); - break; - case 240: - stlink_set_swdclk(sl, STLINK_SWDCLK_240KHZ_DIVISOR); - break; - case 480: - stlink_set_swdclk(sl, STLINK_SWDCLK_480KHZ_DIVISOR); - break; - case 950: - stlink_set_swdclk(sl, STLINK_SWDCLK_950KHZ_DIVISOR); - break; - case 1200: - stlink_set_swdclk(sl, STLINK_SWDCLK_1P2MHZ_DIVISOR); - break; - case 0: case 1800: - stlink_set_swdclk(sl, STLINK_SWDCLK_1P8MHZ_DIVISOR); - break; - case 4000: - stlink_set_swdclk(sl, STLINK_SWDCLK_4MHZ_DIVISOR); - break; - } + stlink_set_swdclk(sl, freq); if (reset == 2) { stlink_jtag_reset(sl, 0); From 2acfa8b8f2211d5d53e3e39fa79c90c56dd54409 Mon Sep 17 00:00:00 2001 From: Ant-ON Date: Thu, 5 Nov 2020 20:42:32 +0500 Subject: [PATCH 102/503] Add debug message of current CPU mode --- src/common.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/common.c b/src/common.c index 7321b39a4..8eb3370ef 100644 --- a/src/common.c +++ b/src/common.c @@ -1487,7 +1487,12 @@ int stlink_soft_reset(stlink_t *sl, int halt_on_reset) { } int stlink_run(stlink_t *sl) { + struct stlink_reg rr; DLOG("*** stlink_run ***\n"); + + stlink_read_reg(sl, 16, &rr); + DLOG("Run in %s mode\n", (rr.xpsr & (1 << 24))?"ARM":"THUMB"); + return(sl->backend->run(sl)); } From 4e58872913acd4bcbef5ac9b63514cb04bba4727 Mon Sep 17 00:00:00 2001 From: Ant-ON Date: Fri, 6 Nov 2020 16:17:54 +0500 Subject: [PATCH 103/503] Add printing st-link version to st-info --- src/common.c | 2 +- src/st-info/info.c | 30 +++++++++++++++++++++++------- 2 files changed, 24 insertions(+), 8 deletions(-) diff --git a/src/common.c b/src/common.c index 8eb3370ef..d04d10049 100644 --- a/src/common.c +++ b/src/common.c @@ -1487,7 +1487,7 @@ int stlink_soft_reset(stlink_t *sl, int halt_on_reset) { } int stlink_run(stlink_t *sl) { - struct stlink_reg rr; + struct stlink_reg rr; DLOG("*** stlink_run ***\n"); stlink_read_reg(sl, 16, &rr); diff --git a/src/st-info/info.c b/src/st-info/info.c index 2343140de..4f2fae1eb 100644 --- a/src/st-info/info.c +++ b/src/st-info/info.c @@ -35,23 +35,36 @@ static void stlink_print_serial(stlink_t *sl, bool openocd) { printf("\n"); } +static void stlink_print_version(stlink_t *sl) { + // Implementation of version printing is minimalistic + // but contains all available information from sl->version + printf("V%d", sl->version.stlink_v); + if (sl->version.jtag_v > 0) + printf("J%d", sl->version.jtag_v); + if (sl->version.swim_v > 0) + printf("S%d", sl->version.swim_v); + printf("\n"); +} + static void stlink_print_info(stlink_t *sl) { const struct stlink_chipid_params *params = NULL; if (!sl) { return; } - printf(" serial: "); + printf(" version: "); + stlink_print_version(sl); + printf(" serial: "); stlink_print_serial(sl, false); - printf(" hla-serial: "); + printf(" hla-serial: "); stlink_print_serial(sl, true); - printf(" flash: %u (pagesize: %u)\n", + printf(" flash: %u (pagesize: %u)\n", (uint32_t)sl->flash_size, (uint32_t)sl->flash_pgsz); - printf(" sram: %u\n", (uint32_t)sl->sram_size); - printf(" chipid: 0x%.4x\n", sl->chip_id); + printf(" sram: %u\n", (uint32_t)sl->sram_size); + printf(" chipid: 0x%.4x\n", sl->chip_id); params = stlink_chipid_get_params(sl->chip_id); - if (params) { printf(" descr: %s\n", params->description); } + if (params) { printf(" descr: %s\n", params->description); } } static void stlink_probe(void) { @@ -62,7 +75,10 @@ static void stlink_probe(void) { printf("Found %u stlink programmers\n", (unsigned int)size); - for (size_t n = 0; n < size; n++) { stlink_print_info(stdevs[n]); } + for (size_t n = 0; n < size; n++) { + if (size>1) printf("%lu.\n", n+1); + stlink_print_info(stdevs[n]); + } stlink_probe_usb_free(&stdevs, size); } From 277eee7aec00493151d940a12d697651e8977d66 Mon Sep 17 00:00:00 2001 From: Ant-ON Date: Sat, 7 Nov 2020 13:50:14 +0500 Subject: [PATCH 104/503] Move check of current instruction mode to stlink_run --- src/common.c | 8 +++++++- src/stlink-lib/flash_loader.c | 7 ------- 2 files changed, 7 insertions(+), 8 deletions(-) diff --git a/src/common.c b/src/common.c index d04d10049..e3c4fdd2e 100644 --- a/src/common.c +++ b/src/common.c @@ -1490,8 +1490,14 @@ int stlink_run(stlink_t *sl) { struct stlink_reg rr; DLOG("*** stlink_run ***\n"); + /* Make sure we are in Thumb mode + * Cortex-M chips don't support ARM mode instructions + * xPSR may be incorrect if the vector table has invalid data */ stlink_read_reg(sl, 16, &rr); - DLOG("Run in %s mode\n", (rr.xpsr & (1 << 24))?"ARM":"THUMB"); + if ((rr.xpsr & (1 << 24)) == 0) { + ILOG("Go to Thumb mode\n"); + stlink_write_reg(sl, rr.xpsr | (1 << 24), 16); + } return(sl->backend->run(sl)); } diff --git a/src/stlink-lib/flash_loader.c b/src/stlink-lib/flash_loader.c index c86aefbf7..b7726e875 100644 --- a/src/stlink-lib/flash_loader.c +++ b/src/stlink-lib/flash_loader.c @@ -356,13 +356,6 @@ int stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t targe // only used on VL/F1_XL, but harmless for others stlink_write_reg(sl, fl->loader_addr, 15); // pc register - /* Make sure we are in Thumb mode */ - stlink_read_reg(sl, 16, &rr); - if ((rr.xpsr & (1 << 24)) == 0) { - ILOG("Go to Thumb mode\n"); - stlink_write_reg(sl, rr.xpsr | (1 << 24), 16); - } - /* Run loader */ stlink_run(sl); From 54000d67acefd86df4bdb0594dee940dd04763fa Mon Sep 17 00:00:00 2001 From: Ant-ON Date: Mon, 9 Nov 2020 13:41:51 +0500 Subject: [PATCH 105/503] H7 add support dual bank, mass erase and new chips --- inc/stm32.h | 2 + src/common.c | 400 ++++++++++++++++++++-------------------- src/stlink-lib/chipid.c | 31 +++- src/stlink-lib/chipid.h | 2 + 4 files changed, 239 insertions(+), 196 deletions(-) diff --git a/inc/stm32.h b/inc/stm32.h index 768fabb87..1ea0d1f04 100644 --- a/inc/stm32.h +++ b/inc/stm32.h @@ -14,6 +14,8 @@ /* Constant STM32 memory map figures */ #define STM32_FLASH_BASE ((uint32_t)0x08000000) +#define STM32_F1_FLASH_BANK2_BASE ((uint32_t)0x08080000) +#define STM32_H7_FLASH_BANK2_BASE ((uint32_t)0x08100000) #define STM32_SRAM_BASE ((uint32_t)0x20000000) #define STM32_G0_OPTION_BYTES_BASE ((uint32_t)0x1FFF7800) #define STM32_G4_OPTION_BYTES_BASE ((uint32_t)0x1FFFF800) diff --git a/src/common.c b/src/common.c index e3c4fdd2e..0ac2d1153 100644 --- a/src/common.c +++ b/src/common.c @@ -30,6 +30,9 @@ #define __attribute__(x) #endif +#define BANK_1 0 +#define BANK_2 1 + /* stm32f FPEC flash controller interface, pm0063 manual */ // TODO - all of this needs to be abstracted out.... // STM32F05x is identical, based on RM0091 (DM00031936, Doc ID 018940 Rev 2, August 2012) @@ -50,7 +53,6 @@ #define FLASH_SR2 (FLASH_REGS_ADDR + 0x4c) #define FLASH_CR2 (FLASH_REGS_ADDR + 0x50) #define FLASH_AR2 (FLASH_REGS_ADDR + 0x54) -#define FLASH_BANK2_START_ADDR 0x08080000 // For STM32F05x, the RDPTR_KEY may be wrong, but as it is not used anywhere... #define FLASH_RDPTR_KEY 0x00a5 @@ -307,12 +309,17 @@ #define FLASH_H7_CR_LOCK 0 #define FLASH_H7_CR_PG 1 #define FLASH_H7_CR_SER 2 +#define FLASH_H7_CR_BER 3 #define FLASH_H7_CR_PSIZE 4 -#define FLASH_H7_CR_START 7 +#define FLASH_H7_CR_START(chipid) (chipid==STLINK_CHIPID_STM32_H7AX?5:7) #define FLASH_H7_CR_SNB 8 #define FLASH_H7_CR_SNB_MASK 0x700 #define FLASH_H7_SR_QW 2 +#define FLASH_H7_SR_WRPERR 17 +#define FLASH_H7_SR_PGSERR 18 +#define FLASH_H7_SR_STRBERR 19 +#define FLASH_H7_SR_ERROR_MASK ((1 << FLASH_H7_SR_PGSERR) | (1 << FLASH_H7_SR_STRBERR) | (1 << FLASH_H7_SR_WRPERR)) #define FLASH_H7_OPTCR_OPTLOCK 0 #define FLASH_H7_OPTCR_OPTSTART 1 @@ -325,10 +332,17 @@ #define FLASH_H7_REGS_ADDR ((uint32_t)0x52002000) #define FLASH_H7_KEYR1 (FLASH_H7_REGS_ADDR + 0x04) +#define FLASH_H7_KEYR2 (FLASH_H7_REGS_ADDR + 0x104) #define FLASH_H7_OPT_KEYR (FLASH_H7_REGS_ADDR + 0x08) +#define FLASH_H7_OPT_KEYR2 (FLASH_H7_REGS_ADDR + 0x108) #define FLASH_H7_CR1 (FLASH_H7_REGS_ADDR + 0x0c) +#define FLASH_H7_CR2 (FLASH_H7_REGS_ADDR + 0x10c) #define FLASH_H7_SR1 (FLASH_H7_REGS_ADDR + 0x10) +#define FLASH_H7_SR2 (FLASH_H7_REGS_ADDR + 0x110) +#define FLASH_H7_CCR1 (FLASH_H7_REGS_ADDR + 0x14) +#define FLASH_H7_CCR2 (FLASH_H7_REGS_ADDR + 0x114) #define FLASH_H7_OPTCR (FLASH_H7_REGS_ADDR + 0x18) +#define FLASH_H7_OPTCR2 (FLASH_H7_REGS_ADDR + 0x118) #define FLASH_H7_OPTSR_CUR (FLASH_H7_REGS_ADDR + 0x1c) #define FLASH_H7_OPTCCR (FLASH_H7_REGS_ADDR + 0x24) @@ -397,7 +411,7 @@ static uint32_t __attribute__((unused)) read_flash_rdp(stlink_t *sl) { return(rdp & 0xff); } -static inline uint32_t read_flash_cr(stlink_t *sl) { +static inline uint32_t read_flash_cr(stlink_t *sl, unsigned bank) { uint32_t reg, res; if (sl->flash_type == STLINK_FLASH_TYPE_F4) { @@ -412,9 +426,9 @@ static inline uint32_t read_flash_cr(stlink_t *sl) { } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { reg = STM32WB_FLASH_CR; } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { - reg = FLASH_H7_CR1; + reg = (bank == BANK_1)?FLASH_H7_CR1:FLASH_H7_CR2; } else { - reg = FLASH_CR; + reg = (bank == BANK_1)?FLASH_CR:FLASH_CR2; } stlink_read_debug32(sl, reg, &res); @@ -425,15 +439,6 @@ static inline uint32_t read_flash_cr(stlink_t *sl) { return(res); } -static inline uint32_t read_flash_cr2(stlink_t *sl) { - uint32_t res; - stlink_read_debug32(sl, FLASH_CR2, &res); -#if DEBUG_FLASH - fprintf(stdout, "CR2:0x%x\n", res); -#endif - return(res); -} - static inline unsigned int is_flash_locked(stlink_t *sl) { /* return non zero for true */ uint32_t cr_lock_shift; @@ -476,7 +481,7 @@ static inline unsigned int is_flash_locked(stlink_t *sl) { } static void unlock_flash(stlink_t *sl) { - uint32_t key_reg; + uint32_t key_reg, key2_reg = 0; uint32_t flash_key1 = FLASH_KEY1; uint32_t flash_key2 = FLASH_KEY2; /* The unlock sequence consists of 2 write cycles where 2 key values are written @@ -484,9 +489,11 @@ static void unlock_flash(stlink_t *sl) { * An invalid sequence results in a definitive lock of the FPEC block until next reset. */ - if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || - (sl->flash_type == STLINK_FLASH_TYPE_F1_XL)) { + if (sl->flash_type == STLINK_FLASH_TYPE_F0) { key_reg = FLASH_KEYR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL) { + key_reg = FLASH_KEYR; + key2_reg = FLASH_KEYR2; } else if (sl->flash_type == STLINK_FLASH_TYPE_F4) { key_reg = FLASH_F4_KEYR; } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { @@ -504,6 +511,9 @@ static void unlock_flash(stlink_t *sl) { key_reg = STM32WB_FLASH_KEYR; } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { key_reg = FLASH_H7_KEYR1; + if (sl->has_dual_bank) { + key2_reg = FLASH_H7_KEYR2; + } } else { ELOG("unsupported flash method, abort\n"); return; @@ -512,9 +522,9 @@ static void unlock_flash(stlink_t *sl) { stlink_write_debug32(sl, key_reg, flash_key1); stlink_write_debug32(sl, key_reg, flash_key2); - if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL) { - stlink_write_debug32(sl, FLASH_KEYR2, flash_key1); - stlink_write_debug32(sl, FLASH_KEYR2, flash_key2); + if (key2_reg) { + stlink_write_debug32(sl, key2_reg, flash_key1); + stlink_write_debug32(sl, key2_reg, flash_key2); } } @@ -534,13 +544,16 @@ static int unlock_flash_if(stlink_t *sl) { } static void lock_flash(stlink_t *sl) { - uint32_t cr_lock_shift, cr_reg, n; + uint32_t cr_lock_shift, cr_reg, n, cr2_reg = 0; uint32_t cr_mask = 0xffffffffu; - if (sl->flash_type == STLINK_FLASH_TYPE_F0 || - sl->flash_type == STLINK_FLASH_TYPE_F1_XL) { + if (sl->flash_type == STLINK_FLASH_TYPE_F0) { cr_reg = FLASH_CR; cr_lock_shift = FLASH_CR_LOCK; + } else if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL) { + cr_reg = FLASH_CR; + cr2_reg = FLASH_CR2; + cr_lock_shift = FLASH_CR_LOCK; } else if (sl->flash_type == STLINK_FLASH_TYPE_F4) { cr_reg = FLASH_F4_CR; cr_lock_shift = FLASH_F4_CR_LOCK; @@ -562,6 +575,9 @@ static void lock_flash(stlink_t *sl) { cr_lock_shift = STM32WB_FLASH_CR_LOCK; } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { cr_reg = FLASH_H7_CR1; + if (sl->has_dual_bank) { + cr2_reg = FLASH_H7_CR2; + } cr_lock_shift = FLASH_H7_CR_LOCK; cr_mask = ~(1u << FLASH_H7_CR_SER); } else { @@ -574,9 +590,9 @@ static void lock_flash(stlink_t *sl) { n |= (1u << cr_lock_shift); stlink_write_debug32(sl, cr_reg, n); - if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL) { - n = read_flash_cr2(sl) | (1u << cr_lock_shift); - stlink_write_debug32(sl, FLASH_CR2, n); + if (cr2_reg) { + n = read_flash_cr(sl, BANK_2) | (1u << cr_lock_shift); + stlink_write_debug32(sl, cr2_reg, n); } } @@ -637,7 +653,7 @@ static bool is_flash_option_locked(stlink_t *sl) { } static int lock_flash_option(stlink_t *sl) { - uint32_t optlock_shift, optcr_reg, n; + uint32_t optlock_shift, optcr_reg, n, optcr2_reg = 0; int active_bit_level = 1; switch (sl->flash_type) { @@ -675,6 +691,8 @@ static int lock_flash_option(stlink_t *sl) { case STLINK_FLASH_TYPE_H7: optcr_reg = FLASH_H7_OPTCR; optlock_shift = FLASH_H7_OPTCR_OPTLOCK; + if (sl->has_dual_bank) + optcr2_reg = FLASH_H7_OPTCR2; break; default: ELOG("unsupported flash method, abort\n"); @@ -690,11 +708,24 @@ static int lock_flash_option(stlink_t *sl) { } stlink_write_debug32(sl, optcr_reg, n); + + if (optcr2_reg) { + stlink_read_debug32(sl, optcr2_reg, &n); + + if (active_bit_level == 0) { + n &= ~(1u << optlock_shift); + } else { + n |= (1u << optlock_shift); + } + + stlink_write_debug32(sl, optcr2_reg, n); + } + return(0); } static int unlock_flash_option(stlink_t *sl) { - uint32_t optkey_reg; + uint32_t optkey_reg, optkey2_reg = 0; uint32_t optkey1 = FLASH_OPTKEY1; uint32_t optkey2 = FLASH_OPTKEY2; @@ -728,6 +759,8 @@ static int unlock_flash_option(stlink_t *sl) { break; case STLINK_FLASH_TYPE_H7: optkey_reg = FLASH_H7_OPT_KEYR; + if (sl->has_dual_bank) + optkey2_reg = FLASH_H7_OPT_KEYR2; break; default: ELOG("unsupported flash method, abort\n"); @@ -736,6 +769,12 @@ static int unlock_flash_option(stlink_t *sl) { stlink_write_debug32(sl, optkey_reg, optkey1); stlink_write_debug32(sl, optkey_reg, optkey2); + + if (optkey2_reg) { + stlink_write_debug32(sl, optkey2_reg, optkey1); + stlink_write_debug32(sl, optkey2_reg, optkey2); + } + return(0); } @@ -756,10 +795,10 @@ static int unlock_flash_option_if(stlink_t *sl) { return(0); } -static void set_flash_cr_pg(stlink_t *sl) { +static void set_flash_cr_pg(stlink_t *sl, unsigned bank) { uint32_t cr_reg, x; - x = read_flash_cr(sl); + x = read_flash_cr(sl, bank); if (sl->flash_type == STLINK_FLASH_TYPE_F4) { cr_reg = FLASH_F4_CR; @@ -779,7 +818,7 @@ static void set_flash_cr_pg(stlink_t *sl) { cr_reg = STM32WB_FLASH_CR; x |= (1 << FLASH_CR_PG); } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { - cr_reg = FLASH_H7_CR1; + cr_reg = (bank == BANK_1)?FLASH_H7_CR1:FLASH_H7_CR2; x |= (1 << FLASH_H7_CR_PG); } else { cr_reg = FLASH_CR; @@ -789,8 +828,9 @@ static void set_flash_cr_pg(stlink_t *sl) { stlink_write_debug32(sl, cr_reg, x); } -static void clear_flash_cr_pg(stlink_t *sl) { +static void clear_flash_cr_pg(stlink_t *sl, unsigned bank) { uint32_t cr_reg, n; + uint32_t bit = FLASH_CR_PG; if (sl->flash_type == STLINK_FLASH_TYPE_F4) { cr_reg = FLASH_F4_CR; @@ -803,15 +843,18 @@ static void clear_flash_cr_pg(stlink_t *sl) { cr_reg = STM32Gx_FLASH_CR; } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { cr_reg = STM32WB_FLASH_CR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + cr_reg = (bank == BANK_1)?FLASH_H7_CR1:FLASH_H7_CR2; + bit = FLASH_H7_CR_PG; } else { cr_reg = FLASH_CR; } - n = read_flash_cr(sl) & ~(1 << FLASH_CR_PG); + n = read_flash_cr(sl, bank) & ~(1 << bit); stlink_write_debug32(sl, cr_reg, n); } -static void set_flash_cr_per(stlink_t *sl) { +static void set_flash_cr_per(stlink_t *sl, unsigned bank) { uint32_t cr_reg, val; if (sl->flash_type == STLINK_FLASH_TYPE_G0 || @@ -820,7 +863,7 @@ static void set_flash_cr_per(stlink_t *sl) { } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { cr_reg = STM32WB_FLASH_CR; } else { - cr_reg = FLASH_CR; + cr_reg = (bank==BANK_1)?FLASH_CR:FLASH_CR2; } stlink_read_debug32(sl, cr_reg, &val); @@ -828,12 +871,7 @@ static void set_flash_cr_per(stlink_t *sl) { stlink_write_debug32(sl, cr_reg, val); } -static void set_flash_cr2_per(stlink_t *sl) { - const uint32_t n = (1 << FLASH_CR_PER); - stlink_write_debug32(sl, FLASH_CR2, n); -} - -static void clear_flash_cr_per(stlink_t *sl) { +static void clear_flash_cr_per(stlink_t *sl, unsigned bank) { uint32_t cr_reg; if (sl->flash_type == STLINK_FLASH_TYPE_G0 || @@ -842,14 +880,14 @@ static void clear_flash_cr_per(stlink_t *sl) { } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { cr_reg = STM32WB_FLASH_CR; } else { - cr_reg = FLASH_CR; + cr_reg = (bank==BANK_1)?FLASH_CR:FLASH_CR2; } - const uint32_t n = read_flash_cr(sl) & ~(1 << FLASH_CR_PER); + const uint32_t n = read_flash_cr(sl, bank) & ~(1 << FLASH_CR_PER); stlink_write_debug32(sl, cr_reg, n); } -static void set_flash_cr_mer(stlink_t *sl, bool v) { +static void set_flash_cr_mer(stlink_t *sl, bool v, unsigned bank) { uint32_t val, cr_reg, cr_mer, cr_pg; if (sl->flash_type == STLINK_FLASH_TYPE_F4) { @@ -878,8 +916,12 @@ static void set_flash_cr_mer(stlink_t *sl, bool v) { cr_reg = STM32WB_FLASH_CR; cr_mer = (1 << FLASH_CR_MER); cr_pg = (1 << FLASH_CR_PG); + } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + cr_reg = (bank==BANK_1)?FLASH_H7_CR1:FLASH_H7_CR2; + cr_mer = (1 << FLASH_H7_CR_BER); + cr_pg = (1 << FLASH_H7_CR_PG); } else { - cr_reg = FLASH_CR; + cr_reg = (bank==BANK_1)?FLASH_CR:FLASH_CR2; cr_mer = (1 << FLASH_CR_MER); cr_pg = (1 << FLASH_CR_PG); } @@ -901,46 +943,7 @@ static void set_flash_cr_mer(stlink_t *sl, bool v) { stlink_write_debug32(sl, cr_reg, val); } -static void set_flash_cr2_mer(stlink_t *sl, bool v) { - const uint32_t cr_pg = (1 << FLASH_CR_PER); - const uint32_t cr_mer = (1 << FLASH_CR_MER); - uint32_t val; - - stlink_read_debug32(sl, FLASH_CR2, &val); - val &= ~cr_pg; - - if (v) { - val |= cr_mer; - } else { - val &= ~cr_mer; - } - - stlink_write_debug32(sl, FLASH_CR2, val); -} - -static void __attribute__((unused)) clear_flash_cr_mer(stlink_t *sl) { - uint32_t val, cr_reg, cr_mer; - - if (sl->flash_type == STLINK_FLASH_TYPE_F4) { - cr_reg = FLASH_F4_CR; - cr_mer = 1 << FLASH_CR_MER; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { - cr_reg = FLASH_F7_CR; - cr_mer = 1 << FLASH_CR_MER; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { - cr_reg = STM32L4_FLASH_CR; - cr_mer = (1 << STM32L4_FLASH_CR_MER1) | (1 << STM32L4_FLASH_CR_MER2); - } else { - cr_reg = FLASH_CR; - cr_mer = (1 << FLASH_CR_MER); - } - - stlink_read_debug32(sl, cr_reg, &val); - val &= ~cr_mer; - stlink_write_debug32(sl, cr_reg, val); -} - -static void set_flash_cr_strt(stlink_t *sl) { +static void set_flash_cr_strt(stlink_t *sl, unsigned bank) { uint32_t val, cr_reg, cr_strt; if (sl->flash_type == STLINK_FLASH_TYPE_F4) { @@ -960,10 +963,10 @@ static void set_flash_cr_strt(stlink_t *sl) { cr_reg = STM32WB_FLASH_CR; cr_strt = (1 << STM32WB_FLASH_CR_STRT); } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { - cr_reg = FLASH_H7_CR1; - cr_strt = 1 << FLASH_H7_CR_START; + cr_reg = (bank==BANK_1)?FLASH_H7_CR1:FLASH_H7_CR2; + cr_strt = 1 << FLASH_H7_CR_START(sl->chip_id); } else { - cr_reg = FLASH_CR; + cr_reg = (bank==BANK_1)?FLASH_CR:FLASH_CR2; cr_strt = (1 << FLASH_CR_STRT); } @@ -972,20 +975,12 @@ static void set_flash_cr_strt(stlink_t *sl) { stlink_write_debug32(sl, cr_reg, val); } -static void set_flash_cr2_strt(stlink_t *sl) { - uint32_t val; - - stlink_read_debug32(sl, FLASH_CR2, &val); - val |= 1 << FLASH_CR_STRT; - stlink_write_debug32(sl, FLASH_CR2, val); -} - -static inline uint32_t read_flash_sr(stlink_t *sl) { +static inline uint32_t read_flash_sr(stlink_t *sl, unsigned bank) { uint32_t res, sr_reg; if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || (sl->flash_type == STLINK_FLASH_TYPE_F1_XL)) { - sr_reg = FLASH_SR; + sr_reg = (bank==BANK_1)?FLASH_SR:FLASH_SR2; } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { sr_reg = get_stm32l0_flash_base(sl) + FLASH_SR_OFF; } else if (sl->flash_type == STLINK_FLASH_TYPE_F4) { @@ -1000,7 +995,7 @@ static inline uint32_t read_flash_sr(stlink_t *sl) { } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { sr_reg = STM32WB_FLASH_SR; } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { - sr_reg = FLASH_H7_SR1; + sr_reg = (bank==BANK_1)?FLASH_H7_SR1:FLASH_H7_SR2; } else { ELOG("unsupported flash method, abort"); return(-1); @@ -1010,12 +1005,6 @@ static inline uint32_t read_flash_sr(stlink_t *sl) { return(res); } -static inline uint32_t read_flash_sr2(stlink_t *sl) { - uint32_t res; - stlink_read_debug32(sl, FLASH_SR2, &res); - return(res); -} - static inline unsigned int is_flash_busy(stlink_t *sl) { uint32_t sr_busy_shift; unsigned int res; @@ -1042,10 +1031,11 @@ static inline unsigned int is_flash_busy(stlink_t *sl) { return(-1); } - res = read_flash_sr(sl) & (1 << sr_busy_shift); + res = read_flash_sr(sl, BANK_1) & (1 << sr_busy_shift); - if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL) { - res |= read_flash_sr2(sl) & (1 << sr_busy_shift); + if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL || + (sl->flash_type == STLINK_FLASH_TYPE_H7 && sl->has_dual_bank)) { + res |= read_flash_sr(sl, BANK_2) & (1 << sr_busy_shift); } return(res); @@ -1081,17 +1071,31 @@ static int check_flash_error(stlink_t *sl) switch (sl->flash_type) { case STLINK_FLASH_TYPE_F0: - res = read_flash_sr(sl) & FLASH_SR_ERROR_MASK; + res = read_flash_sr(sl, BANK_1) & FLASH_SR_ERROR_MASK; break; case STLINK_FLASH_TYPE_F7: - res = read_flash_sr(sl) & FLASH_F7_SR_ERROR_MASK; + res = read_flash_sr(sl, BANK_1) & FLASH_F7_SR_ERROR_MASK; break; case STLINK_FLASH_TYPE_G0: case STLINK_FLASH_TYPE_G4: - res = read_flash_sr(sl) & STM32Gx_FLASH_SR_ERROR_MASK; + res = read_flash_sr(sl, BANK_1) & STM32Gx_FLASH_SR_ERROR_MASK; break; case STLINK_FLASH_TYPE_L0: - res = read_flash_sr(sl) & STM32L0_FLASH_SR_ERROR_MASK; + res = read_flash_sr(sl, BANK_1) & STM32L0_FLASH_SR_ERROR_MASK; + break; + case STLINK_FLASH_TYPE_H7: + res = read_flash_sr(sl, BANK_1) & FLASH_H7_SR_ERROR_MASK; + if (sl->has_dual_bank) { + res |= read_flash_sr(sl, BANK_2) & FLASH_H7_SR_ERROR_MASK; + } + if (res) { + // Clear errors + stlink_write_debug32(sl, FLASH_H7_CCR1, res); + if (sl->has_dual_bank) { + stlink_write_debug32(sl, FLASH_H7_CCR2, res); + } + } + break; default: break; } @@ -1104,35 +1108,16 @@ static int check_flash_error(stlink_t *sl) return(0); } -static inline unsigned int is_flash_eop(stlink_t *sl) { - return(read_flash_sr(sl) & (1 << FLASH_SR_EOP)); -} - -static void __attribute__((unused)) clear_flash_sr_eop(stlink_t *sl) { - const uint32_t n = read_flash_sr(sl) & ~(1 << FLASH_SR_EOP); - stlink_write_debug32(sl, FLASH_SR, n); -} - -static void __attribute__((unused)) wait_flash_eop(stlink_t *sl) { - // TODO: add some delays here - while (is_flash_eop(sl) == 0) - ; -} - -static inline void write_flash_ar(stlink_t *sl, uint32_t n) { - stlink_write_debug32(sl, FLASH_AR, n); -} - -static inline void write_flash_ar2(stlink_t *sl, uint32_t n) { - stlink_write_debug32(sl, FLASH_AR2, n); +static inline void write_flash_ar(stlink_t *sl, uint32_t n, unsigned bank) { + stlink_write_debug32(sl, (bank==BANK_1)?FLASH_AR:FLASH_AR2, n); } -static inline void write_flash_cr_psiz(stlink_t *sl, uint32_t n) { +static inline void write_flash_cr_psiz(stlink_t *sl, uint32_t n, unsigned bank) { uint32_t cr_reg, psize_shift; - uint32_t x = read_flash_cr(sl); + uint32_t x = read_flash_cr(sl, bank); if (sl->flash_type == STLINK_FLASH_TYPE_H7) { - cr_reg = FLASH_H7_CR1; + cr_reg = (bank==BANK_1)?FLASH_H7_CR1:FLASH_H7_CR2; psize_shift = FLASH_H7_CR_PSIZE; } else { cr_reg = FLASH_F4_CR; @@ -1147,12 +1132,12 @@ static inline void write_flash_cr_psiz(stlink_t *sl, uint32_t n) { stlink_write_debug32(sl, cr_reg, x); } -static inline void write_flash_cr_snb(stlink_t *sl, uint32_t n) { +static inline void write_flash_cr_snb(stlink_t *sl, uint32_t n, unsigned bank) { uint32_t cr_reg, snb_mask, snb_shift, ser_shift; - uint32_t x = read_flash_cr(sl); + uint32_t x = read_flash_cr(sl, bank); if (sl->flash_type == STLINK_FLASH_TYPE_H7) { - cr_reg = FLASH_H7_CR1; + cr_reg = (bank==BANK_1)?FLASH_H7_CR1:FLASH_H7_CR2; snb_mask = FLASH_H7_CR_SNB_MASK; snb_shift = FLASH_H7_CR_SNB; ser_shift = FLASH_H7_CR_SER; @@ -1174,7 +1159,7 @@ static inline void write_flash_cr_snb(stlink_t *sl, uint32_t n) { static inline void write_flash_cr_bker_pnb(stlink_t *sl, uint32_t n) { stlink_write_debug32(sl, STM32L4_FLASH_SR, 0xFFFFFFFF & ~(1 << STM32L4_FLASH_SR_BSY)); - uint32_t x = read_flash_cr(sl); + uint32_t x = read_flash_cr(sl, BANK_1); x &= ~STM32L4_FLASH_CR_OPBITS; x &= ~STM32L4_FLASH_CR_PAGEMASK; x &= ~(1 << STM32L4_FLASH_CR_MER1); @@ -1391,6 +1376,11 @@ int stlink_load_device_params(stlink_t *sl) { if (!(flash_optr & (1 << STM32G4_FLASH_OPTR_DBANK))) { sl->flash_pgsz <<= 1; } } + // H7 devices with small flash has one bank + if (sl->has_dual_bank && sl->flash_type == STLINK_FLASH_TYPE_H7) { + sl->has_dual_bank = (flash_size/sl->flash_pgsz) > 1; + } + #if 0 // Old code -- REW ILOG("Device connected is: %s, id %#x\n", params->description, chip_id); @@ -2314,9 +2304,9 @@ uint32_t calculate_F7_sectornum(uint32_t flashaddr) { } -uint32_t calculate_H7_sectornum(uint32_t flashaddr) { - flashaddr &= ~STM32_FLASH_BASE; // sector holding the flash address - return(flashaddr / 0x20000); +uint32_t calculate_H7_sectornum(stlink_t *sl, uint32_t flashaddr, unsigned bank) { + flashaddr &= ~((bank==BANK_1)?STM32_FLASH_BASE:STM32_H7_FLASH_BANK2_BASE); // sector holding the flash address + return(flashaddr / sl->flash_pgsz); } // returns BKER:PNB for the given page address @@ -2392,8 +2382,7 @@ uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr) { int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { if (sl->flash_type == STLINK_FLASH_TYPE_F4 || sl->flash_type == STLINK_FLASH_TYPE_F7 || - sl->flash_type == STLINK_FLASH_TYPE_L4 || - sl->flash_type == STLINK_FLASH_TYPE_H7) { + sl->flash_type == STLINK_FLASH_TYPE_L4) { // wait for ongoing op to finish wait_flash_busy(sl); @@ -2420,14 +2409,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { fprintf(stderr, "EraseFlash - Sector:0x%x Size:0x%x ", sector, stlink_calculate_pagesize(sl, flashaddr)); - write_flash_cr_snb(sl, sector); - } else if (sl->chip_id == STLINK_CHIPID_STM32_H74XXX) { - // calculate the actual page from the address - uint32_t sector = calculate_H7_sectornum(flashaddr); - - fprintf(stderr, "EraseFlash - Sector:0x%x Size:0x%x ", - sector, stlink_calculate_pagesize(sl, flashaddr)); - write_flash_cr_snb(sl, sector); + write_flash_cr_snb(sl, sector, BANK_1); } else { // calculate the actual page from the address uint32_t sector = calculate_F4_sectornum(flashaddr); @@ -2439,14 +2421,14 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { // follow the values for the first bank on 2mb devices... if (sector >= 12) { sector += 4; } - write_flash_cr_snb(sl, sector); + write_flash_cr_snb(sl, sector, BANK_1); } - set_flash_cr_strt(sl); // start erase operation + set_flash_cr_strt(sl, BANK_1); // start erase operation wait_flash_busy(sl); // wait for completion lock_flash(sl); // TODO: fails to program if this is in #if DEBUG_FLASH - fprintf(stdout, "Erase Final CR:0x%x\n", read_flash_cr(sl)); + fprintf(stdout, "Erase Final CR:0x%x\n", read_flash_cr(sl, BANK_1)); #endif } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { @@ -2526,7 +2508,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { uint32_t val; wait_flash_busy(sl); // wait for any ongoing Flash operation to finish unlock_flash_if(sl); - set_flash_cr_per(sl); // set the 'enable Flash erase' bit + set_flash_cr_per(sl, BANK_1); // set the 'enable Flash erase' bit // set the page to erase if (sl->flash_type == STLINK_FLASH_TYPE_WB) { @@ -2554,27 +2536,29 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { stlink_write_debug32(sl, STM32Gx_FLASH_CR, val); } - set_flash_cr_strt(sl); // set the 'start operation' bit + set_flash_cr_strt(sl, BANK_1); // set the 'start operation' bit wait_flash_busy(sl); // wait for the 'busy' bit to clear - clear_flash_cr_per(sl); // clear the 'enable page erase' bit + clear_flash_cr_per(sl, BANK_1); // clear the 'enable page erase' bit lock_flash(sl); - } else if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || - ((sl->flash_type == STLINK_FLASH_TYPE_F1_XL) && (flashaddr < FLASH_BANK2_START_ADDR))) { + } else if (sl->flash_type == STLINK_FLASH_TYPE_F0 || + sl->flash_type == STLINK_FLASH_TYPE_F1_XL) { + unsigned bank = (flashaddr < STM32_F1_FLASH_BANK2_BASE)?BANK_1:BANK_2; wait_flash_busy(sl); unlock_flash_if(sl); - clear_flash_cr_pg(sl); // clear the pg bit - set_flash_cr_per(sl); // set the page erase bit - write_flash_ar(sl, flashaddr); // select the page to erase - set_flash_cr_strt(sl); // start erase operation, reset by hw with busy bit + clear_flash_cr_pg(sl, bank); // clear the pg bit + set_flash_cr_per(sl, bank); // set the page erase bit + write_flash_ar(sl, flashaddr, bank); // select the page to erase + set_flash_cr_strt(sl, bank); // start erase operation, reset by hw with busy bit wait_flash_busy(sl); lock_flash(sl); - } else if ((sl->flash_type == STLINK_FLASH_TYPE_F1_XL) && (flashaddr >= FLASH_BANK2_START_ADDR)) { - wait_flash_busy(sl); - unlock_flash_if(sl); - set_flash_cr2_per(sl); // set the page erase bit - write_flash_ar2(sl, flashaddr); // select the page to erase - set_flash_cr2_strt(sl); // start erase operation, reset by hw with busy bit - wait_flash_busy(sl); + } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + unsigned bank = (flashaddr < STM32_H7_FLASH_BANK2_BASE)?BANK_1:BANK_2; + wait_flash_busy(sl); // wait for ongoing op to finish + unlock_flash_if(sl); // unlock if locked + uint32_t sector = calculate_H7_sectornum(sl, flashaddr, bank);// calculate the actual page from the address + write_flash_cr_snb(sl, sector, bank); // select the page to erase + set_flash_cr_strt(sl, bank); // start erase operation + wait_flash_busy(sl); // wait for completion lock_flash(sl); } else { WLOG("unknown coreid %x, page erase failed\n", sl->core_id); @@ -2586,7 +2570,9 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { } int stlink_erase_flash_mass(stlink_t *sl) { - // TODO: User MER bit to mass-erase G0, G4, WB series. + int err = 0; + + // TODO: User MER bit to mass-erase WB series. if (sl->flash_type == STLINK_FLASH_TYPE_L0 || sl->flash_type == STLINK_FLASH_TYPE_WB) { // erase each page @@ -2609,28 +2595,39 @@ int stlink_erase_flash_mass(stlink_t *sl) { } else { wait_flash_busy(sl); unlock_flash_if(sl); - set_flash_cr_mer(sl, 1); // set the mass erase bit - set_flash_cr_strt(sl); // start erase operation, reset by hw with busy bit - if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL) { - set_flash_cr2_mer(sl, 1); // set the mass erase bit in bank 2 - set_flash_cr2_strt(sl); // start erase operation in bank 2 + if (sl->flash_type == STLINK_FLASH_TYPE_H7 && sl->chip_id != STLINK_CHIPID_STM32_H7AX) { + // set parallelism + write_flash_cr_psiz(sl, 3 /*64it*/, BANK_1); + if (sl->has_dual_bank) { + write_flash_cr_psiz(sl, 3 /*64bit*/, BANK_2); + } + } + + set_flash_cr_mer(sl, 1, BANK_1); // set the mass erase bit + set_flash_cr_strt(sl, BANK_1); // start erase operation, reset by hw with busy bit + + if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL || + (sl->flash_type == STLINK_FLASH_TYPE_H7 && sl->has_dual_bank)) { + set_flash_cr_mer(sl, 1, BANK_2); // set the mass erase bit in bank 2 + set_flash_cr_strt(sl, BANK_2); // start erase operation in bank 2 } wait_flash_busy_progress(sl); - check_flash_error(sl); + err = check_flash_error(sl); lock_flash(sl); - set_flash_cr_mer(sl, 0); // reset the mass erase bit - - if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL) { - set_flash_cr2_mer(sl, 0); // reset the mass erase bit in bank 2 + // reset the mass erase bit + set_flash_cr_mer(sl, 0, BANK_1); + if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL || + (sl->flash_type == STLINK_FLASH_TYPE_H7 && sl->has_dual_bank)) { + set_flash_cr_mer(sl, 0, BANK_2); } // TODO: verify the erased memory } - return(0); + return(err); } int stlink_fcheck_flash(stlink_t *sl, const char* path, stm32_addr_t addr) { @@ -2786,16 +2783,16 @@ int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { } else { if (voltage > 2700) { ILOG("enabling 32-bit flash writes\n"); - write_flash_cr_psiz(sl, 2); + write_flash_cr_psiz(sl, 2, BANK_1); } else { ILOG("Target voltage (%d mV) too low for 32-bit flash, " "using 8-bit flash writes\n", voltage); - write_flash_cr_psiz(sl, 0); + write_flash_cr_psiz(sl, 0, BANK_1); } } // set programming mode - set_flash_cr_pg(sl); + set_flash_cr_pg(sl, BANK_1); } else if (sl->flash_type == STLINK_FLASH_TYPE_WB || sl->flash_type == STLINK_FLASH_TYPE_G0 || sl->flash_type == STLINK_FLASH_TYPE_G4) { @@ -2803,7 +2800,7 @@ int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { wait_flash_busy(sl); unlock_flash_if(sl); // unlock flash if necessary - set_flash_cr_pg(sl); // set PG 'allow programming' bit + set_flash_cr_pg(sl, BANK_1); // set PG 'allow programming' bit } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { ILOG("Starting Flash write for L0\n"); @@ -2852,7 +2849,17 @@ int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { ILOG("Starting Flash write for H7\n"); unlock_flash_if(sl); // unlock the cr - set_flash_cr_pg(sl); // set programming mode + set_flash_cr_pg(sl, BANK_1); // set programming mode + if (sl->has_dual_bank) { + set_flash_cr_pg(sl, BANK_2); + } + if (sl->chip_id != STLINK_CHIPID_STM32_H7AX) { + // set parallelism + write_flash_cr_psiz(sl, 3 /*64it*/, BANK_1); + if (sl->has_dual_bank) { + write_flash_cr_psiz(sl, 3 /*64bit*/, BANK_2); + } + } } else { ELOG("unknown coreid, not sure how to write: %x\n", sl->core_id); return(-1); @@ -2961,7 +2968,7 @@ int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t addr // unlock and set programming mode unlock_flash_if(sl); - if (sl->flash_type != STLINK_FLASH_TYPE_F1_XL) { set_flash_cr_pg(sl); } + if (sl->flash_type != STLINK_FLASH_TYPE_F1_XL) { set_flash_cr_pg(sl, BANK_1); } DLOG("Finished unlocking flash, running loader!\n"); @@ -2984,10 +2991,10 @@ int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t addr } } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { for (off = 0; off < len;) { - // Program STM32H7x with 32-byte Flash words - size_t chunk = (len - off > 32) ? 32 : len - off; + // Program STM32H7x with 64-byte Flash words + size_t chunk = (len - off > 64) ? 64 : len - off; memcpy(sl->q_buf, base + off, chunk); - stlink_write_mem32(sl, addr + (uint32_t)off, 32); + stlink_write_mem32(sl, addr + (uint32_t)off, 64); wait_flash_busy(sl); off += chunk; @@ -3009,7 +3016,7 @@ int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t addr } int stlink_flashloader_stop(stlink_t *sl) { - if ((sl->flash_type == STLINK_FLASH_TYPE_F4) || + if ((sl->flash_type == STLINK_FLASH_TYPE_F4) || (sl->flash_type == STLINK_FLASH_TYPE_F7) || (sl->flash_type == STLINK_FLASH_TYPE_L4) || (sl->flash_type == STLINK_FLASH_TYPE_WB) || @@ -3017,7 +3024,10 @@ int stlink_flashloader_stop(stlink_t *sl) { (sl->flash_type == STLINK_FLASH_TYPE_G4) || (sl->flash_type == STLINK_FLASH_TYPE_H7)) { - clear_flash_cr_pg(sl); + clear_flash_cr_pg(sl, BANK_1); + if (sl->flash_type == STLINK_FLASH_TYPE_H7 && sl->has_dual_bank) { + clear_flash_cr_pg(sl, BANK_2); + } lock_flash(sl); } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { uint32_t val; diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index c191fa919..5cf2ddd1c 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -617,8 +617,9 @@ static const struct stlink_chipid_params devices[] = { { // STM32H742/743/753 (from RM0433) .chip_id = STLINK_CHIPID_STM32_H74XXX, - .description = "H742/743/753", + .description = "H74x/H75x", .flash_type = STLINK_FLASH_TYPE_H7, + .has_dual_bank = true, .flash_size_reg = 0x1ff1e880, // "Flash size register" (pg3272) .flash_pagesize = 0x20000, // 128k sector (pg147) .sram_size = 0x20000, // 128k "DTCM" from Table 7 @@ -627,6 +628,34 @@ static const struct stlink_chipid_params devices[] = { .option_base = STM32_H7_OPTION_BYTES_BASE, .option_size = 44, // FLASH_OPTSR_CUR to FLASH_BOOT_PRGR from Table 28 }, + { + // STM32H7A3/7B3 (from RM0455) + .chip_id = STLINK_CHIPID_STM32_H7AX, + .description = "H7Ax/H7Bx", + .flash_type = STLINK_FLASH_TYPE_H7, + .has_dual_bank = true, + .flash_size_reg = 0x08FFF80C, // "Flash size register" (p.2949) + .flash_pagesize = 0x2000, // 8k sector (p.146) + .sram_size = 0x20000, // 128k "DTCM" (Figure 1) + .bootrom_base = 0x1FF00000, // "System memory" starting address (Table 12-14) + .bootrom_size = 0x20000, // "System memory" byte size in hex splitted to two banks (Table 12-14) + .option_base = STM32_H7_OPTION_BYTES_BASE, + .option_size = 44, + }, + { + // STM32H72x/H73x (from RM0468) + .chip_id = STLINK_CHIPID_STM32_H72X, + .description = "H72x/H73x", + .flash_type = STLINK_FLASH_TYPE_H7, + .flash_size_reg = 0x1FF1E880, // "Flash size register" (p.3286) + .flash_pagesize = 0x20000, // 128k sector (p.152) + .sram_size = 0x20000, // 128k "DTCM" (Figure 1) + .bootrom_base = 0x1FF00000, // "System memory" starting address (Table 6) + .bootrom_size = 0x20000, // "System memory" byte size in hex (Table 6) + .option_base = STM32_H7_OPTION_BYTES_BASE, + .option_size = 44, + }, + { // unknown .chip_id = STLINK_CHIPID_UNKNOWN, diff --git a/src/stlink-lib/chipid.h b/src/stlink-lib/chipid.h index f717022ca..a342df2dc 100644 --- a/src/stlink-lib/chipid.h +++ b/src/stlink-lib/chipid.h @@ -64,6 +64,8 @@ enum stlink_stm32_chipids { STLINK_CHIPID_STM32_G4_CAT2 = 0x468, /* See: RM 0440 s46.6.1 "MCU device ID code" */ STLINK_CHIPID_STM32_G4_CAT3 = 0x469, STLINK_CHIPID_STM32_L4RX = 0x470, /* ID found on the STM32L4R9I-DISCO board */ + STLINK_CHIPID_STM32_H7AX = 0x480, /* RM0455, p. 2863 */ + STLINK_CHIPID_STM32_H72X = 0x483, /* RM0468, p. 3199 */ STLINK_CHIPID_STM32_WB55 = 0x495 }; From d902fba40aa3db82c4b144849a5ea427492cb06e Mon Sep 17 00:00:00 2001 From: Ant-ON Date: Wed, 11 Nov 2020 19:57:57 +0500 Subject: [PATCH 106/503] Fix printf format --- src/st-info/info.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/st-info/info.c b/src/st-info/info.c index 4f2fae1eb..2e1ce0e96 100644 --- a/src/st-info/info.c +++ b/src/st-info/info.c @@ -38,11 +38,11 @@ static void stlink_print_serial(stlink_t *sl, bool openocd) { static void stlink_print_version(stlink_t *sl) { // Implementation of version printing is minimalistic // but contains all available information from sl->version - printf("V%d", sl->version.stlink_v); + printf("V%u", sl->version.stlink_v); if (sl->version.jtag_v > 0) - printf("J%d", sl->version.jtag_v); + printf("J%u", sl->version.jtag_v); if (sl->version.swim_v > 0) - printf("S%d", sl->version.swim_v); + printf("S%u", sl->version.swim_v); printf("\n"); } From 79b225945b93a6306f374eb9438d78136d3fea8f Mon Sep 17 00:00:00 2001 From: Oleksiy Slyshyk Date: Thu, 12 Nov 2020 22:39:49 +0200 Subject: [PATCH 107/503] link for WIN32 & APPLE with stlink-static --- CMakeLists.txt | 12 ++++++------ tests/CMakeLists.txt | 12 +++++++++--- 2 files changed, 15 insertions(+), 9 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index fae458dd7..824c3671e 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -155,11 +155,7 @@ execute_process(COMMAND bash -c "export LD_LIBRARY_PATH=${CMAKE_INSTALL_LIBDIR}" ### # Set library name -if (NOT WIN32) - set(STLINK_LIB_SHARED ${PROJECT_NAME}) -else (WIN32) - set(STLINK_LIB_SHARED ${PROJECT_NAME}-shared) -endif () +set(STLINK_LIB_SHARED ${PROJECT_NAME}-shared) add_library(${STLINK_LIB_SHARED} SHARED ${STLINK_HEADERS} ${STLINK_SOURCE}) @@ -195,6 +191,10 @@ install(TARGETS ${STLINK_LIB_SHARED} DESTINATION ${STLINK_LIBRARY_PATH}) # Set library name set(STLINK_LIB_STATIC ${PROJECT_NAME}-static) +set(STLINK_LIB_STATIC_OUTPUT_NAME ${PROJECT_NAME}) +if (MSVC) + set(STLINK_LIB_STATIC_OUTPUT_NAME ${PROJECT_NAME}-static) +endif() add_library(${STLINK_LIB_STATIC} STATIC ${STLINK_HEADERS} ${STLINK_SOURCE}) @@ -206,7 +206,7 @@ message(STATUS "VERSION: ${STLINK_STATIC_VERSION}") set_target_properties(${STLINK_LIB_STATIC} PROPERTIES SOVERSION ${PROJECT_VERSION_MAJOR} VERSION ${STLINK_STATIC_VERSION} - OUTPUT_NAME ${PROJECT_NAME} + OUTPUT_NAME ${STLINK_LIB_STATIC_OUTPUT_NAME} ) # Link static library diff --git a/tests/CMakeLists.txt b/tests/CMakeLists.txt index a3011fc7e..0f23214d6 100644 --- a/tests/CMakeLists.txt +++ b/tests/CMakeLists.txt @@ -4,13 +4,19 @@ set(TESTEXEC usb sg) +set(TEST_DEPENDENCY ${STLINK_LIB_SHARED}) +if (WIN32 OR APPLE) + set(TEST_DEPENDENCY ${STLINK_LIB_STATIC}) +endif() + foreach (test ${TESTEXEC}) add_executable(test-${test} ${test}.c) - add_dependencies(test-${test} ${STLINK_LIB_SHARED}) - target_link_libraries(test-${test} ${STLINK_LIB_SHARED} ${SSP_LIB}) + add_dependencies(test-${test} ${TEST_DEPENDENCY}) + target_link_libraries(test-${test} ${TEST_DEPENDENCY} ${SSP_LIB}) add_test(test-${test} ${CMAKE_BINARY_DIR}/bin/test-${test}) endforeach () add_executable(test-flash flash.c "${CMAKE_SOURCE_DIR}/src/st-flash/flash_opts.c") -target_link_libraries(test-flash ${STLINK_LIB_SHARED} ${SSP_LIB}) +add_dependencies(test-flash ${TEST_DEPENDENCY}) +target_link_libraries(test-flash ${TEST_DEPENDENCY} ${SSP_LIB}) add_test(test-flash ${CMAKE_BINARY_DIR}/bin/test-flash) From 27d3144fce97ecf8ece522b96ad5c60eb8dc446d Mon Sep 17 00:00:00 2001 From: John Hall Date: Wed, 25 Nov 2020 10:51:20 -0800 Subject: [PATCH 108/503] Adding framework for st-trace. --- .gitignore | 1 + CMakeLists.txt | 5 ++ src/st-trace/trace.c | 143 +++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 149 insertions(+) create mode 100644 src/st-trace/trace.c diff --git a/.gitignore b/.gitignore index 9fbe0139c..8b1dc465d 100644 --- a/.gitignore +++ b/.gitignore @@ -4,3 +4,4 @@ build-mingw obj-* *.user* .cmake/ +*.swp diff --git a/CMakeLists.txt b/CMakeLists.txt index 824c3671e..08a889660 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -231,6 +231,7 @@ install(TARGETS ${STLINK_LIB_STATIC} ARCHIVE DESTINATION ${STLINK_LIBRARY_PATH}) set(ST-FLASH_SOURCES src/st-flash/flash.c src/st-flash/flash_opts.c) set(ST-INFO_SOURCES src/st-info/info.c) set(ST-UTIL_SOURCES src/st-util/gdb-remote.c src/st-util/gdb-server.c src/st-util/semihosting.c) +set(ST-TRACE_SOURCES src/st-trace/trace.c) if (MSVC) # Add getopt to sources @@ -241,20 +242,24 @@ endif () add_executable(st-flash ${ST-FLASH_SOURCES}) add_executable(st-info ${ST-INFO_SOURCES}) add_executable(st-util ${ST-UTIL_SOURCES}) +add_executable(st-trace ${ST-TRACE_SOURCES}) if (WIN32 OR APPLE) target_link_libraries(st-flash ${STLINK_LIB_STATIC} ${SSP_LIB}) target_link_libraries(st-info ${STLINK_LIB_STATIC} ${SSP_LIB}) target_link_libraries(st-util ${STLINK_LIB_STATIC} ${SSP_LIB}) + target_link_libraries(st-trace ${STLINK_LIB_STATIC} ${SSP_LIB}) else () target_link_libraries(st-flash ${STLINK_LIB_SHARED} ${SSP_LIB}) target_link_libraries(st-info ${STLINK_LIB_SHARED} ${SSP_LIB}) target_link_libraries(st-util ${STLINK_LIB_SHARED} ${SSP_LIB}) + target_link_libraries(st-trace ${STLINK_LIB_SHARED} ${SSP_LIB}) endif () install(TARGETS st-flash DESTINATION ${CMAKE_INSTALL_BINDIR}) install(TARGETS st-info DESTINATION ${CMAKE_INSTALL_BINDIR}) install(TARGETS st-util DESTINATION ${CMAKE_INSTALL_BINDIR}) +install(TARGETS st-trace DESTINATION ${CMAKE_INSTALL_BINDIR}) ### diff --git a/src/st-trace/trace.c b/src/st-trace/trace.c new file mode 100644 index 000000000..d7ece29d4 --- /dev/null +++ b/src/st-trace/trace.c @@ -0,0 +1,143 @@ +#include +#include +#include +#include +#include +#include + +#include +#include + + +#define DEFAULT_LOGGING_LEVEL 50 +#define DEBUG_LOGGING_LEVEL 100 + +#define APP_RESULT_SUCCESS 0 +#define APP_RESULT_INVALID_PARAMS 1 + + +struct _st_settings_t +{ + bool show_help; + bool show_version; + int logging_level; + int core_frequency_mhz; + bool reset_board; + char* serial_number; + bool wait_sync; +}; +typedef struct _st_settings_t st_settings_t; + + +static void usage(void) { + puts("st-trace - usage:"); + puts(" -h, --help Print this help"); + puts(" -V, --version Print this version"); + puts(" -vXX, --verbose=XX Specify a specific verbosity level (0..99)"); + puts(" -v, --verbose Specify a generally verbose logging"); + puts(" -cXX, --clock=XX Specify the core frequency in MHz"); + puts(" -n, --no-reset Do not reset board on connection"); + puts(" -sXX, --serial=XX Use a specific serial number"); + puts(" -a, --no-sync Do not wait for a sync packet"); +} + +bool parse_options(int argc, char** argv, st_settings_t *settings) { + + static struct option long_options[] = { + {"help", no_argument, NULL, 'h'}, + {"version", no_argument, NULL, 'V'}, + {"verbose", optional_argument, NULL, 'v'}, + {"clock", required_argument, NULL, 'c'}, + {"no-reset", no_argument, NULL, 'n'}, + {"serial", required_argument, NULL, 's'}, + {"no-sync", no_argument, NULL, 'a'}, + {0, 0, 0, 0}, + }; + int option_index = 0; + int c; + + settings->show_help = false; + settings->show_version = false; + settings->logging_level = DEFAULT_LOGGING_LEVEL; + settings->core_frequency_mhz = 0; + settings->reset_board = true; + settings->serial_number = NULL; + settings->wait_sync = true; + + while ((c = getopt_long(argc, argv, "hVv::c:ns:a", long_options, &option_index)) != -1) { + switch (c) { + case 'h': + settings->show_help = true; + break; + case 'V': + settings->show_version = true; + break; + case 'v': + if (optarg) { + settings->logging_level = atoi(optarg); + } else { + settings->logging_level = DEBUG_LOGGING_LEVEL; + } + break; + case 'c': + settings->core_frequency_mhz = atoi(optarg); + break; + case 'n': + settings->reset_board = false; + break; + case 's': + settings->serial_number = optarg; + break; + case 'a': + settings->wait_sync = false; + break; + case '?': + return false; + break; + default: + printf("ERROR: Unknown command line option: '%c' (0x%02x)\n", c, c); + return false; + } + } + + if (optind < argc) { + while (optind < argc) { + printf("ERROR: Unknown command line argument: '%s'\n", argv[optind++]); + } + return false; + } + + return true; +} + +int main(int argc, char** argv) +{ + st_settings_t settings; + + if (!parse_options(argc, argv, &settings)) { + usage(); + return APP_RESULT_INVALID_PARAMS; + } + + /* if (settings.logging_level >= UDEBUG) */ + printf("show_help = %s\n", settings.show_help ? "true" : "false"); + printf("show_version = %s\n", settings.show_version ? "true" : "false"); + printf("logging_level = %d\n", settings.logging_level); + printf("core_frequency = %d MHz\n", settings.core_frequency_mhz); + printf("reset_board = %s\n", settings.reset_board ? "true" : "false"); + printf("serial_number = %s\n", settings.serial_number ? settings.serial_number : "any"); + printf("wait_sync = %s\n", settings.wait_sync ? "true" : "false"); + + if (settings.show_help) { + usage(); + return APP_RESULT_SUCCESS; + } + + if (settings.show_version) { + printf("v%s\n", STLINK_VERSION); + return APP_RESULT_SUCCESS; + } + + return APP_RESULT_SUCCESS; +} + From 0f411da1d75620e5b005643afaf7110cf25b2d70 Mon Sep 17 00:00:00 2001 From: John Hall Date: Wed, 25 Nov 2020 23:49:42 +0000 Subject: [PATCH 109/503] Getting to build on raspberry pi. Adding calls to identify st-links. --- raspberrypi-build.sh | 20 +++++++++++ src/st-trace/trace.c | 80 +++++++++++++++++++++++++++++++++----------- 2 files changed, 81 insertions(+), 19 deletions(-) create mode 100755 raspberrypi-build.sh diff --git a/raspberrypi-build.sh b/raspberrypi-build.sh new file mode 100755 index 000000000..7f77dab45 --- /dev/null +++ b/raspberrypi-build.sh @@ -0,0 +1,20 @@ +#!/bin/bash + +mkdir -p build/raspberry +mkdir -p build/raspberry/inc +mkdir -p build/raspberry/bin + +cat << EOF > build/raspberry/inc/version.h +#ifndef STLINK_VERSION_H_ +#define STLINK_VERSION_H_ + +#define STLINK_VERSION "1.6.1-116-g27d3-pi-dirty" +#define STLINK_VERSION_MAJOR 1 +#define STLINK_VERSION_MINOR 6 +#define STLINK_VERSION_PATCH 1 + +#endif // STLINK_VERSION_H_ +EOF + +gcc -std=gnu99 -Iinc -Isrc/stlink-lib/ -I/usr/include/libusb-1.0/ -Ibuild/raspberry/inc -DLIBUSB_API_VERSION=MINIMAL_API_VERSION -DSTLINK_HAVE_SYS_MMAN_H src/*.c src/stlink-lib/*.c src/st-trace/*.c -lusb-1.0 -o build/raspberry/bin/st-trace + diff --git a/src/st-trace/trace.c b/src/st-trace/trace.c index d7ece29d4..03f1ac43d 100644 --- a/src/st-trace/trace.c +++ b/src/st-trace/trace.c @@ -12,8 +12,9 @@ #define DEFAULT_LOGGING_LEVEL 50 #define DEBUG_LOGGING_LEVEL 100 -#define APP_RESULT_SUCCESS 0 -#define APP_RESULT_INVALID_PARAMS 1 +#define APP_RESULT_SUCCESS 0 +#define APP_RESULT_INVALID_PARAMS 1 +#define APP_RESULT_STLINK_NOT_FOUND 2 struct _st_settings_t @@ -30,15 +31,15 @@ typedef struct _st_settings_t st_settings_t; static void usage(void) { - puts("st-trace - usage:"); - puts(" -h, --help Print this help"); - puts(" -V, --version Print this version"); - puts(" -vXX, --verbose=XX Specify a specific verbosity level (0..99)"); - puts(" -v, --verbose Specify a generally verbose logging"); - puts(" -cXX, --clock=XX Specify the core frequency in MHz"); - puts(" -n, --no-reset Do not reset board on connection"); - puts(" -sXX, --serial=XX Use a specific serial number"); - puts(" -a, --no-sync Do not wait for a sync packet"); + puts("st-trace - usage:"); + puts(" -h, --help Print this help"); + puts(" -V, --version Print this version"); + puts(" -vXX, --verbose=XX Specify a specific verbosity level (0..99)"); + puts(" -v, --verbose Specify a generally verbose logging"); + puts(" -cXX, --clock=XX Specify the core frequency in MHz"); + puts(" -n, --no-reset Do not reset board on connection"); + puts(" -sXX, --serial=XX Use a specific serial number"); + puts(" -a, --no-sync Do not wait for a sync packet"); } bool parse_options(int argc, char** argv, st_settings_t *settings) { @@ -110,6 +111,33 @@ bool parse_options(int argc, char** argv, st_settings_t *settings) { return true; } +static bool FindStLink(const st_settings_t* settings, stlink_t* link) { + stlink_t **stdevs; + size_t size; + bool result = false; + + size = stlink_probe_usb(&stdevs); + if (settings->logging_level >= UDEBUG) { + printf("Found %u stlink programmers\n", (unsigned int)size); + } + + if (!settings->serial_number && size > 0) { + *link = *stdevs[0]; + result = true; + } else { + for (size_t n = 0; n < size; n++) { + if (strncmp(stdevs[n]->serial, settings->serial_number, stdevs[n]->serial_size) == 0) { + *link = *stdevs[n]; + result = true; + } + } + } + + stlink_probe_usb_free(&stdevs, size); + + return result; +} + int main(int argc, char** argv) { st_settings_t settings; @@ -119,14 +147,15 @@ int main(int argc, char** argv) return APP_RESULT_INVALID_PARAMS; } - /* if (settings.logging_level >= UDEBUG) */ - printf("show_help = %s\n", settings.show_help ? "true" : "false"); - printf("show_version = %s\n", settings.show_version ? "true" : "false"); - printf("logging_level = %d\n", settings.logging_level); - printf("core_frequency = %d MHz\n", settings.core_frequency_mhz); - printf("reset_board = %s\n", settings.reset_board ? "true" : "false"); - printf("serial_number = %s\n", settings.serial_number ? settings.serial_number : "any"); - printf("wait_sync = %s\n", settings.wait_sync ? "true" : "false"); + if (settings.logging_level >= UDEBUG) { + printf("show_help = %s\n", settings.show_help ? "true" : "false"); + printf("show_version = %s\n", settings.show_version ? "true" : "false"); + printf("logging_level = %d\n", settings.logging_level); + printf("core_frequency = %d MHz\n", settings.core_frequency_mhz); + printf("reset_board = %s\n", settings.reset_board ? "true" : "false"); + printf("serial_number = %s\n", settings.serial_number ? settings.serial_number : "any"); + printf("wait_sync = %s\n", settings.wait_sync ? "true" : "false"); + } if (settings.show_help) { usage(); @@ -137,6 +166,19 @@ int main(int argc, char** argv) printf("v%s\n", STLINK_VERSION); return APP_RESULT_SUCCESS; } + + stlink_t link; + if (!FindStLink(&settings, &link)) { + if (settings.serial_number) { + printf("ERROR: Unable to locate st-link '%s'\n", settings.serial_number); + } else { + printf("ERROR: Unable to locate st-link\n"); + } + return APP_RESULT_STLINK_NOT_FOUND; + } + + + return APP_RESULT_SUCCESS; } From 5ad3bb9846c58086c9758aa5e1816b551473c422 Mon Sep 17 00:00:00 2001 From: John Hall Date: Wed, 25 Nov 2020 16:15:51 -0800 Subject: [PATCH 110/503] Separating out method to check if stlink is usable. Adding a log macro. Adding logs with stlink list. --- src/st-trace/trace.c | 33 ++++++++++++++++++++++----------- 1 file changed, 22 insertions(+), 11 deletions(-) diff --git a/src/st-trace/trace.c b/src/st-trace/trace.c index 03f1ac43d..2fec00c8d 100644 --- a/src/st-trace/trace.c +++ b/src/st-trace/trace.c @@ -16,6 +16,8 @@ #define APP_RESULT_INVALID_PARAMS 1 #define APP_RESULT_STLINK_NOT_FOUND 2 +#define LOG(SETTINGS, LEVEL, ARGS...) if (settings->logging_level >= LEVEL) printf(ARGS) + struct _st_settings_t { @@ -111,25 +113,34 @@ bool parse_options(int argc, char** argv, st_settings_t *settings) { return true; } +static bool CompareStlink(const st_settings_t* settings, const stlink_t* link) { + if (!settings->serial_number) { + return true; + } + + if (strncmp(link->serial, settings->serial_number, link->serial_size) == 0) { + return true; + } + + return false; +} + static bool FindStLink(const st_settings_t* settings, stlink_t* link) { stlink_t **stdevs; size_t size; bool result = false; size = stlink_probe_usb(&stdevs); - if (settings->logging_level >= UDEBUG) { - printf("Found %u stlink programmers\n", (unsigned int)size); - } + LOG(settings, UDEBUG, "Found %u stlink programmers\n", (unsigned int)size); - if (!settings->serial_number && size > 0) { - *link = *stdevs[0]; - result = true; - } else { - for (size_t n = 0; n < size; n++) { - if (strncmp(stdevs[n]->serial, settings->serial_number, stdevs[n]->serial_size) == 0) { - *link = *stdevs[n]; - result = true; + for (size_t n = 0; n < size; n++) { + if (CompareStlink(settings, stdevs[n])) { + LOG(settings, UDEBUG, "Matching stlink '%*s'\n", stdevs[n]->serial_size, stdevs[n]->serial); + if (result) { + LOG(settings, UWARN, "WARNING: Multiple matching stlinks\n"); } + *link = *stdevs[n]; + result = true; } } From 4aed3205a8d014091662925329dcd4b46db0be6d Mon Sep 17 00:00:00 2001 From: John Hall Date: Thu, 26 Nov 2020 05:52:37 +0000 Subject: [PATCH 111/503] Fixed that serial numbers are stored as binary values. --- src/st-trace/trace.c | 27 +++++++++++++++++++++------ 1 file changed, 21 insertions(+), 6 deletions(-) diff --git a/src/st-trace/trace.c b/src/st-trace/trace.c index 2fec00c8d..19ea1def2 100644 --- a/src/st-trace/trace.c +++ b/src/st-trace/trace.c @@ -113,12 +113,26 @@ bool parse_options(int argc, char** argv, st_settings_t *settings) { return true; } +static const char* GetSerialString(const stlink_t* link) { + const char kHexChars[16] = "0123456789abcdef"; + static char serial[2 * sizeof(link->serial) + 1]; + + size_t cursor = 0; + for (size_t n = 0; n < link->serial_size; n++) { + serial[cursor++] = kHexChars[(link->serial[n] >> 4) & 0x0f]; + serial[cursor++] = kHexChars[(link->serial[n] >> 0) & 0x0f]; + } + serial[cursor++] = 0; + + return serial; +} + static bool CompareStlink(const st_settings_t* settings, const stlink_t* link) { if (!settings->serial_number) { return true; } - if (strncmp(link->serial, settings->serial_number, link->serial_size) == 0) { + if (strncmp(GetSerialString(link), settings->serial_number, strlen(settings->serial_number)) == 0) { return true; } @@ -131,16 +145,17 @@ static bool FindStLink(const st_settings_t* settings, stlink_t* link) { bool result = false; size = stlink_probe_usb(&stdevs); - LOG(settings, UDEBUG, "Found %u stlink programmers\n", (unsigned int)size); + LOG(settings, UDEBUG, "Found %u stlink programmer(s)\n", (unsigned int)size); for (size_t n = 0; n < size; n++) { if (CompareStlink(settings, stdevs[n])) { - LOG(settings, UDEBUG, "Matching stlink '%*s'\n", stdevs[n]->serial_size, stdevs[n]->serial); + LOG(settings, UDEBUG, "Matching stlink '%s'\n", GetSerialString(stdevs[n])); if (result) { - LOG(settings, UWARN, "WARNING: Multiple matching stlinks\n"); + LOG(settings, UWARN, "WARNING: Multiple matching stlink programmers. Using '%s'\n", GetSerialString(link)); + } else { + *link = *stdevs[n]; + result = true; } - *link = *stdevs[n]; - result = true; } } From f5cc12ce331ec2ecd41b8838f279332bf1ebcc96 Mon Sep 17 00:00:00 2001 From: John Hall Date: Thu, 26 Nov 2020 05:59:27 +0000 Subject: [PATCH 112/503] Cleaning up logging a bit. --- src/st-trace/trace.c | 28 +++++++++++----------------- 1 file changed, 11 insertions(+), 17 deletions(-) diff --git a/src/st-trace/trace.c b/src/st-trace/trace.c index 19ea1def2..8f02a06f1 100644 --- a/src/st-trace/trace.c +++ b/src/st-trace/trace.c @@ -16,7 +16,7 @@ #define APP_RESULT_INVALID_PARAMS 1 #define APP_RESULT_STLINK_NOT_FOUND 2 -#define LOG(SETTINGS, LEVEL, ARGS...) if (settings->logging_level >= LEVEL) printf(ARGS) +#define LOG(SETTINGS, LEVEL, ARGS...) if ((SETTINGS)->logging_level >= (LEVEL)) printf(ARGS) struct _st_settings_t @@ -98,14 +98,14 @@ bool parse_options(int argc, char** argv, st_settings_t *settings) { return false; break; default: - printf("ERROR: Unknown command line option: '%c' (0x%02x)\n", c, c); + LOG(settings, UERROR, "ERROR: Unknown command line option: '%c' (0x%02x)\n", c, c); return false; } } if (optind < argc) { while (optind < argc) { - printf("ERROR: Unknown command line argument: '%s'\n", argv[optind++]); + LOG(settings, UERROR, "ERROR: Unknown command line argument: '%s'\n", argv[optind++]); } return false; } @@ -173,15 +173,13 @@ int main(int argc, char** argv) return APP_RESULT_INVALID_PARAMS; } - if (settings.logging_level >= UDEBUG) { - printf("show_help = %s\n", settings.show_help ? "true" : "false"); - printf("show_version = %s\n", settings.show_version ? "true" : "false"); - printf("logging_level = %d\n", settings.logging_level); - printf("core_frequency = %d MHz\n", settings.core_frequency_mhz); - printf("reset_board = %s\n", settings.reset_board ? "true" : "false"); - printf("serial_number = %s\n", settings.serial_number ? settings.serial_number : "any"); - printf("wait_sync = %s\n", settings.wait_sync ? "true" : "false"); - } + LOG(&settings, UDEBUG, "show_help = %s\n", settings.show_help ? "true" : "false"); + LOG(&settings, UDEBUG, "show_version = %s\n", settings.show_version ? "true" : "false"); + LOG(&settings, UDEBUG, "logging_level = %d\n", settings.logging_level); + LOG(&settings, UDEBUG, "core_frequency = %d MHz\n", settings.core_frequency_mhz); + LOG(&settings, UDEBUG, "reset_board = %s\n", settings.reset_board ? "true" : "false"); + LOG(&settings, UDEBUG, "serial_number = %s\n", settings.serial_number ? settings.serial_number : "any"); + LOG(&settings, UDEBUG, "wait_sync = %s\n", settings.wait_sync ? "true" : "false"); if (settings.show_help) { usage(); @@ -195,11 +193,7 @@ int main(int argc, char** argv) stlink_t link; if (!FindStLink(&settings, &link)) { - if (settings.serial_number) { - printf("ERROR: Unable to locate st-link '%s'\n", settings.serial_number); - } else { - printf("ERROR: Unable to locate st-link\n"); - } + LOG(&settings, UERROR, "ERROR: Unable to locate st-link\n"); return APP_RESULT_STLINK_NOT_FOUND; } From be8d86f6333da1dba6b94e2f22bc9788965177de Mon Sep 17 00:00:00 2001 From: John Hall Date: Thu, 26 Nov 2020 06:46:42 +0000 Subject: [PATCH 113/503] Fixing to use built in logging. --- src/st-trace/trace.c | 30 +++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/src/st-trace/trace.c b/src/st-trace/trace.c index 8f02a06f1..0f651b0d8 100644 --- a/src/st-trace/trace.c +++ b/src/st-trace/trace.c @@ -16,8 +16,6 @@ #define APP_RESULT_INVALID_PARAMS 1 #define APP_RESULT_STLINK_NOT_FOUND 2 -#define LOG(SETTINGS, LEVEL, ARGS...) if ((SETTINGS)->logging_level >= (LEVEL)) printf(ARGS) - struct _st_settings_t { @@ -66,6 +64,7 @@ bool parse_options(int argc, char** argv, st_settings_t *settings) { settings->reset_board = true; settings->serial_number = NULL; settings->wait_sync = true; + ugly_init(settings->logging_level); while ((c = getopt_long(argc, argv, "hVv::c:ns:a", long_options, &option_index)) != -1) { switch (c) { @@ -81,6 +80,7 @@ bool parse_options(int argc, char** argv, st_settings_t *settings) { } else { settings->logging_level = DEBUG_LOGGING_LEVEL; } + ugly_init(settings->logging_level); break; case 'c': settings->core_frequency_mhz = atoi(optarg); @@ -98,14 +98,14 @@ bool parse_options(int argc, char** argv, st_settings_t *settings) { return false; break; default: - LOG(settings, UERROR, "ERROR: Unknown command line option: '%c' (0x%02x)\n", c, c); + ELOG("Unknown command line option: '%c' (0x%02x)\n", c, c); return false; } } if (optind < argc) { while (optind < argc) { - LOG(settings, UERROR, "ERROR: Unknown command line argument: '%s'\n", argv[optind++]); + ELOG("Unknown command line argument: '%s'\n", argv[optind++]); } return false; } @@ -145,13 +145,13 @@ static bool FindStLink(const st_settings_t* settings, stlink_t* link) { bool result = false; size = stlink_probe_usb(&stdevs); - LOG(settings, UDEBUG, "Found %u stlink programmer(s)\n", (unsigned int)size); + DLOG("Found %u stlink programmer(s)\n", (unsigned int)size); for (size_t n = 0; n < size; n++) { if (CompareStlink(settings, stdevs[n])) { - LOG(settings, UDEBUG, "Matching stlink '%s'\n", GetSerialString(stdevs[n])); + DLOG("Matching stlink '%s'\n", GetSerialString(stdevs[n])); if (result) { - LOG(settings, UWARN, "WARNING: Multiple matching stlink programmers. Using '%s'\n", GetSerialString(link)); + WLOG("Multiple matching stlink programmers. Using '%s'\n", GetSerialString(link)); } else { *link = *stdevs[n]; result = true; @@ -173,13 +173,13 @@ int main(int argc, char** argv) return APP_RESULT_INVALID_PARAMS; } - LOG(&settings, UDEBUG, "show_help = %s\n", settings.show_help ? "true" : "false"); - LOG(&settings, UDEBUG, "show_version = %s\n", settings.show_version ? "true" : "false"); - LOG(&settings, UDEBUG, "logging_level = %d\n", settings.logging_level); - LOG(&settings, UDEBUG, "core_frequency = %d MHz\n", settings.core_frequency_mhz); - LOG(&settings, UDEBUG, "reset_board = %s\n", settings.reset_board ? "true" : "false"); - LOG(&settings, UDEBUG, "serial_number = %s\n", settings.serial_number ? settings.serial_number : "any"); - LOG(&settings, UDEBUG, "wait_sync = %s\n", settings.wait_sync ? "true" : "false"); + DLOG("show_help = %s\n", settings.show_help ? "true" : "false"); + DLOG("show_version = %s\n", settings.show_version ? "true" : "false"); + DLOG("logging_level = %d\n", settings.logging_level); + DLOG("core_frequency = %d MHz\n", settings.core_frequency_mhz); + DLOG("reset_board = %s\n", settings.reset_board ? "true" : "false"); + DLOG("serial_number = %s\n", settings.serial_number ? settings.serial_number : "any"); + DLOG("wait_sync = %s\n", settings.wait_sync ? "true" : "false"); if (settings.show_help) { usage(); @@ -193,7 +193,7 @@ int main(int argc, char** argv) stlink_t link; if (!FindStLink(&settings, &link)) { - LOG(&settings, UERROR, "ERROR: Unable to locate st-link\n"); + ELOG("Unable to locate st-link\n"); return APP_RESULT_STLINK_NOT_FOUND; } From 2fd0ab86144c894979fd3271f898902696fd80e4 Mon Sep 17 00:00:00 2001 From: John Hall Date: Thu, 26 Nov 2020 16:28:43 +0000 Subject: [PATCH 114/503] Library already supported specifying which stlink to use. --- src/st-trace/trace.c | 68 ++++++++++---------------------------------- 1 file changed, 15 insertions(+), 53 deletions(-) diff --git a/src/st-trace/trace.c b/src/st-trace/trace.c index 0f651b0d8..0427d5760 100644 --- a/src/st-trace/trace.c +++ b/src/st-trace/trace.c @@ -113,60 +113,25 @@ bool parse_options(int argc, char** argv, st_settings_t *settings) { return true; } -static const char* GetSerialString(const stlink_t* link) { - const char kHexChars[16] = "0123456789abcdef"; - static char serial[2 * sizeof(link->serial) + 1]; - - size_t cursor = 0; - for (size_t n = 0; n < link->serial_size; n++) { - serial[cursor++] = kHexChars[(link->serial[n] >> 4) & 0x0f]; - serial[cursor++] = kHexChars[(link->serial[n] >> 0) & 0x0f]; - } - serial[cursor++] = 0; - - return serial; -} - -static bool CompareStlink(const st_settings_t* settings, const stlink_t* link) { - if (!settings->serial_number) { - return true; - } - - if (strncmp(GetSerialString(link), settings->serial_number, strlen(settings->serial_number)) == 0) { - return true; - } - - return false; -} - -static bool FindStLink(const st_settings_t* settings, stlink_t* link) { - stlink_t **stdevs; - size_t size; - bool result = false; - - size = stlink_probe_usb(&stdevs); - DLOG("Found %u stlink programmer(s)\n", (unsigned int)size); - - for (size_t n = 0; n < size; n++) { - if (CompareStlink(settings, stdevs[n])) { - DLOG("Matching stlink '%s'\n", GetSerialString(stdevs[n])); - if (result) { - WLOG("Multiple matching stlink programmers. Using '%s'\n", GetSerialString(link)); - } else { - *link = *stdevs[n]; - result = true; - } +static stlink_t* StLinkConnect(const st_settings_t* settings) { + if (settings->serial_number) { + char serial_number[STLINK_SERIAL_MAX_SIZE] = { 0 }; + size_t length = 0; + for (uint32_t n = 0; n < strlen(settings->serial_number) && length < STLINK_SERIAL_MAX_SIZE; n += 2) { + char buffer[3] = { 0 }; + memcpy(buffer, settings->serial_number + n, 2); + serial_number[length++] = (uint8_t)strtol(buffer, NULL, 16); } + return stlink_open_usb(settings->logging_level, false, serial_number, 0); + } else { + return stlink_open_usb(settings->logging_level, false, NULL, 0); } - - stlink_probe_usb_free(&stdevs, size); - - return result; } int main(int argc, char** argv) { st_settings_t settings; + stlink_t* link = NULL; if (!parse_options(argc, argv, &settings)) { usage(); @@ -191,15 +156,12 @@ int main(int argc, char** argv) return APP_RESULT_SUCCESS; } - stlink_t link; - if (!FindStLink(&settings, &link)) { + link = StLinkConnect(&settings); + if (!link) { ELOG("Unable to locate st-link\n"); return APP_RESULT_STLINK_NOT_FOUND; } - - - - + return APP_RESULT_SUCCESS; } From 380444a6fd8f4394374cb433f0e1b21f9807bebd Mon Sep 17 00:00:00 2001 From: John Hall Date: Fri, 27 Nov 2020 16:16:16 +0000 Subject: [PATCH 115/503] In progress. Added defines for trace debug commands. Added initial start trace method. --- src/st-trace/trace.c | 158 ++++++++++++++++++++++++++++++++++++-- src/stlink-lib/commands.h | 3 + 2 files changed, 154 insertions(+), 7 deletions(-) diff --git a/src/st-trace/trace.c b/src/st-trace/trace.c index 0427d5760..2f9bcc2ff 100644 --- a/src/st-trace/trace.c +++ b/src/st-trace/trace.c @@ -12,9 +12,12 @@ #define DEFAULT_LOGGING_LEVEL 50 #define DEBUG_LOGGING_LEVEL 100 -#define APP_RESULT_SUCCESS 0 -#define APP_RESULT_INVALID_PARAMS 1 -#define APP_RESULT_STLINK_NOT_FOUND 2 +#define APP_RESULT_SUCCESS 0 +#define APP_RESULT_INVALID_PARAMS 1 +#define APP_RESULT_STLINK_NOT_FOUND 2 +#define APP_RESULT_STLINK_MISSING_DEVICE 3 +#define APP_RESULT_STLINK_UNSUPPORTED_DEVICE 4 +#define APP_RESULT_STLINK_STATE_ERROR 5 struct _st_settings_t @@ -128,10 +131,122 @@ static stlink_t* StLinkConnect(const st_settings_t* settings) { } } +// TODO: Move this to device table. +static bool IsDeviceTraceSupported(int chip_id) { + switch (chip_id) { + case STLINK_CHIPID_STM32_F4: + case STLINK_CHIPID_STM32_F4_DSI: + case STLINK_CHIPID_STM32_F4_HD: + case STLINK_CHIPID_STM32_F4_LP: + case STLINK_CHIPID_STM32_F411RE: + case STLINK_CHIPID_STM32_F4_DE: + case STLINK_CHIPID_STM32_F446: + case STLINK_CHIPID_STM32_F410: + case STLINK_CHIPID_STM32_F3: + case STLINK_CHIPID_STM32_F37x: + case STLINK_CHIPID_STM32_F412: + case STLINK_CHIPID_STM32_F413: + case STLINK_CHIPID_STM32_F3_SMALL: + case STLINK_CHIPID_STM32_F334: + case STLINK_CHIPID_STM32_F303_HIGH: + return true; + default: + return false; + } +} + +static bool EnableTrace(stlink_t* stlink, int core_frequency_mhz, bool reset_board) { + struct stlink_read_reg regp = {}; + + if (stlink_force_debug(stlink)) { + return false; + } + + if (reset_board && stlink_reset(stlink)) { + return false; + } + + // The remainder of the items in this function were taken directly from https://github.com/avrhack/stlink-trace/blob/master/stlink-trace.c#L386 + + // Set DHCSR to C_HALT and C_DEBUGEN + stlink_write_debug32(stlink, 0xE000EDF0, 0xA05F0003); + + // Set TRCENA flag to enable global DWT and ITM + stlink_write_debug32(stlink, 0xE000EDFC, 0x01000000); + + // Set FP_CTRL to enable write + stlink_write_debug32(stlink, 0xE0002000, 0x00000002); + + // Set DWT_FUNCTION0 to DWT_FUNCTION3 to disable sampling + stlink_write_debug32(stlink, 0xE0001028, 0x00000000); + stlink_write_debug32(stlink, 0xE0001038, 0x00000000); + stlink_write_debug32(stlink, 0xE0001048, 0x00000000); + stlink_write_debug32(stlink, 0xE0001058, 0x00000000); + + // Clear DWT_CTRL and other registers + stlink_write_debug32(stlink, 0xE0001000, 0x00000000); + stlink_write_debug32(stlink, 0xE0001004, 0x00000000); + stlink_write_debug32(stlink, 0xE0001008, 0x00000000); + stlink_write_debug32(stlink, 0xE000100C, 0x00000000); + stlink_write_debug32(stlink, 0xE0001010, 0x00000000); + stlink_write_debug32(stlink, 0xE0001014, 0x00000000); + stlink_write_debug32(stlink, 0xE0001018, 0x00000000); + + // We should be checking these regisers. + stlink_read_reg(stlink, 15, ®p); // Read program counter + stlink_read_reg(stlink, 16, ®p); // Read xpsr register + + // Set DBGMCU_CR to enable asynchronous transmission + stlink_write_debug32(stlink, 0xE0042004, 0x00000027); + + + // STLINK_DEBUG_APIV2_START_TRACE_RX + // ???? + unsigned char txBuffer3[] = {STLINK_DEBUG_COMMAND, 0x40, 0x00, 0x10, 0x80, 0x84, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; + unsigned char rxBuffer3[100]; + SendAndReceive(&txBuffer3[0], 16, &rxBuffer3[0], 64); + + + + // Set TPIU_CSPSR to enable trace port width of 2 + stlink_write_debug32(stlink, 0xE0040004, 0x00000001); + + if (core_frequency_mhz) + // Set TPIU_ACPR clock divisor + stlink_write_debug32(stlink, 0xE0040010, core_frequency_mhz / 2 - 1); + + // Set TPIU_SPPR to Asynchronous SWO (NRZ) + stlink_write_debug32(stlink, 0xE00400F0, 0x00000002); + + // Set TPIU_FFCR continuous formatting) + stlink_write_debug32(stlink, 0xE0040304, 0x00000100); + + // Unlock the ITM registers for write + stlink_write_debug32(stlink, 0xE0000FB0, 0xC5ACCE55); + + // Set sync counter + stlink_write_debug32(stlink, 0xE0000E90, 0x00000400); + + // Set ITM_TCR flags : ITMENA,TSENA ATB=0 + stlink_write_debug32(stlink, 0xE0000E80, 0x00010003); + + // Enable all trace ports in ITM_TER + stlink_write_debug32(stlink, 0xE0000E00, 0xFFFFFFFF); + + // Enable unprivileged access to trace ports 31:0 in ITM_TPR + stlink_write_debug32(stlink, 0xE0000E40, 0x0000000F); + + // Set DWT_CTRL flags) + stlink_write_debug32(stlink, 0xE0000E40, 0x400003FE); // Keil one + + // Enable tracing (DEMCR - TRCENA bit) + stlink_write_debug32(stlink, 0xE000EDFC, 0x01000000); +} + int main(int argc, char** argv) { st_settings_t settings; - stlink_t* link = NULL; + stlink_t* stlink = NULL; if (!parse_options(argc, argv, &settings)) { usage(); @@ -156,12 +271,41 @@ int main(int argc, char** argv) return APP_RESULT_SUCCESS; } - link = StLinkConnect(&settings); - if (!link) { + stlink = StLinkConnect(&settings); + if (!stlink) { ELOG("Unable to locate st-link\n"); return APP_RESULT_STLINK_NOT_FOUND; } - + + if (stlink->chip_id == STLINK_CHIPID_UNKNOWN) { + ELOG("st-link not connected\n"); + return APP_RESULT_STLINK_MISSING_DEVICE; + } + + // TODO: Check if trace is supported by stlink. + + if (!IsDeviceTraceSupported(stlink->chip_id)) { + const struct stlink_chipid_params *params = stlink_chipid_get_params(stlink->chip_id); + ELOG("We do not support SWO output for device '%s'", params->description); + return APP_RESULT_STLINK_UNSUPPORTED_DEVICE; + } + + if (!EnableTrace(stlink, settings.core_frequency_mhz, settings.reset_board)) { + ELOG("Unable to enable trace mode\n"); + return APP_RESULT_STLINK_STATE_ERROR; + } + + if (stlink_run(stlink)) { + ELOG("Unable to run device\n"); + return APP_RESULT_STLINK_STATE_ERROR; + } + + + // Read SWO output + + + stlink_close(stlink); + return APP_RESULT_SUCCESS; } diff --git a/src/stlink-lib/commands.h b/src/stlink-lib/commands.h index 0925e8e67..dac82b8e6 100644 --- a/src/stlink-lib/commands.h +++ b/src/stlink-lib/commands.h @@ -30,6 +30,9 @@ enum stlink_debug_commands { STLINK_DEBUG_APIV2_READALLREGS = 0x3A, STLINK_DEBUG_APIV2_GETLASTRWSTATUS = 0x3B, STLINK_DEBUG_APIV2_GETLASTRWSTATUS2 = 0x3E, + STLINK_DEBUG_APIV2_START_TRACE_RX = 0x40, + STLINK_DEBUG_APIV2_STOP_TRACE_RX = 0x41, + STLINK_DEBUG_APIV2_GET_TRACE_NB = 0x42, STLINK_DEBUG_ENTER_SWD = 0xa3 }; From 568b0d130a5f61e511b1063bcea68f2e0ad18c1c Mon Sep 17 00:00:00 2001 From: John Hall Date: Fri, 27 Nov 2020 09:37:50 -0800 Subject: [PATCH 116/503] Adding backend code to start/stop tracing and to read the incoming data. --- inc/backend.h | 4 +++ inc/stlink.h | 7 ++++ src/common.c | 16 +++++++++ src/st-trace/trace.c | 14 +++----- src/stlink-lib/sg.c | 5 ++- src/stlink-lib/usb.c | 83 +++++++++++++++++++++++++++++++++++++++++++- src/stlink-lib/usb.h | 1 + 7 files changed, 119 insertions(+), 11 deletions(-) diff --git a/inc/backend.h b/inc/backend.h index f852da05d..470702fde 100644 --- a/inc/backend.h +++ b/inc/backend.h @@ -29,6 +29,10 @@ int (*force_debug) (stlink_t *sl); int32_t (*target_voltage) (stlink_t *sl); int (*set_swdclk) (stlink_t * stl, uint16_t divisor); + int (*trace_enable) (stlink_t * sl); + int (*trace_disable) (stlink_t * sl); + int (*trace_read) (stlink_t * sl, uint8_t* buf, size_t size); + } stlink_backend_t; #endif // STLINK_BACKEND_H_ diff --git a/inc/stlink.h b/inc/stlink.h index 39f5f283c..e7aefbded 100644 --- a/inc/stlink.h +++ b/inc/stlink.h @@ -83,6 +83,9 @@ enum target_state { #define STLINK_V3_MAX_FREQ_NB 10 +#define STLINK_TRACE_BUF_LEN 4096 +#define STLINK_TRACE_FREQUENCY 2000000 + /* Cortex Debug Control Block */ #define DCB_DHCSR 0xE000EDF0 #define DCB_DCRSR 0xE000EDF4 @@ -261,6 +264,9 @@ int stlink_current_mode(stlink_t *sl); int stlink_force_debug(stlink_t *sl); int stlink_target_voltage(stlink_t *sl); int stlink_set_swdclk(stlink_t *sl, uint16_t divisor); +int stlink_trace_enable(stlink_t* sl); +int stlink_trace_disable(stlink_t* sl); +int stlink_trace_read(stlink_t* sl, uint8_t* buf, size_t size); int stlink_erase_flash_mass(stlink_t* sl); int stlink_write_flash(stlink_t* sl, stm32_addr_t address, uint8_t* data, uint32_t length, uint8_t eraseonly); @@ -303,6 +309,7 @@ int stlink_write_option_control_register1_32(stlink_t *sl, uint32_t option_contr int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t len); int stlink_fwrite_option_bytes(stlink_t *sl, const char* path, stm32_addr_t addr); + #include #include #include diff --git a/src/common.c b/src/common.c index 32c00ad3b..e340ecc71 100644 --- a/src/common.c +++ b/src/common.c @@ -1677,6 +1677,21 @@ int stlink_current_mode(stlink_t *sl) { return(STLINK_DEV_UNKNOWN_MODE); } +int stlink_trace_enable(stlink_t* sl) { + DLOG("*** stlink_trace_enable ***\n"); + return(sl->backend->trace_enable(sl)); +} + +int stlink_trace_disable(stlink_t* sl) { + DLOG("*** stlink_trace_disable ***\n"); + return(sl->backend->trace_disable(sl)); +} + +int stlink_trace_read(stlink_t* sl, uint8_t* buf, size_t size) { + DLOG("*** stlink_trace_read ***\n"); + return(sl->backend->trace_read(sl, buf, size)); +} + // End of delegates.... Common code below here... @@ -4070,3 +4085,4 @@ int stlink_fwrite_option_bytes(stlink_t *sl, const char* path, stm32_addr_t addr return(err); } + diff --git a/src/st-trace/trace.c b/src/st-trace/trace.c index 2f9bcc2ff..0bbec903e 100644 --- a/src/st-trace/trace.c +++ b/src/st-trace/trace.c @@ -156,7 +156,6 @@ static bool IsDeviceTraceSupported(int chip_id) { } static bool EnableTrace(stlink_t* stlink, int core_frequency_mhz, bool reset_board) { - struct stlink_read_reg regp = {}; if (stlink_force_debug(stlink)) { return false; @@ -193,20 +192,15 @@ static bool EnableTrace(stlink_t* stlink, int core_frequency_mhz, bool reset_boa stlink_write_debug32(stlink, 0xE0001018, 0x00000000); // We should be checking these regisers. + struct stlink_reg regp = {}; stlink_read_reg(stlink, 15, ®p); // Read program counter stlink_read_reg(stlink, 16, ®p); // Read xpsr register // Set DBGMCU_CR to enable asynchronous transmission stlink_write_debug32(stlink, 0xE0042004, 0x00000027); - - // STLINK_DEBUG_APIV2_START_TRACE_RX - // ???? - unsigned char txBuffer3[] = {STLINK_DEBUG_COMMAND, 0x40, 0x00, 0x10, 0x80, 0x84, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; - unsigned char rxBuffer3[100]; - SendAndReceive(&txBuffer3[0], 16, &rxBuffer3[0], 64); - - + // Actually start tracing. + stlink_trace_enable(stlink); // Set TPIU_CSPSR to enable trace port width of 2 stlink_write_debug32(stlink, 0xE0040004, 0x00000001); @@ -241,6 +235,8 @@ static bool EnableTrace(stlink_t* stlink, int core_frequency_mhz, bool reset_boa // Enable tracing (DEMCR - TRCENA bit) stlink_write_debug32(stlink, 0xE000EDFC, 0x01000000); + + return true; } int main(int argc, char** argv) diff --git a/src/stlink-lib/sg.c b/src/stlink-lib/sg.c index 5cc27b1fe..f66864c44 100644 --- a/src/stlink-lib/sg.c +++ b/src/stlink-lib/sg.c @@ -944,7 +944,10 @@ static stlink_backend_t _stlink_sg_backend = { _stlink_sg_current_mode, _stlink_sg_force_debug, NULL, // target_voltage - NULL // set_swdclk + NULL, // set_swdclk + NULL, // trace_enable + NULL, // trace_disable + NULL, // trace_read }; static stlink_t* stlink_open(const int verbose) { diff --git a/src/stlink-lib/usb.c b/src/stlink-lib/usb.c index 9726ddc4a..a7ebab0f3 100644 --- a/src/stlink-lib/usb.c +++ b/src/stlink-lib/usb.c @@ -972,6 +972,82 @@ int _stlink_usb_write_reg(stlink_t *sl, uint32_t reg, int idx) { return(0); } +int _stlink_usb_enable_trace(stlink_t* sl) { + struct stlink_libusb * const slu = sl->backend_data; + unsigned char* const cmd = sl->c_buf; + ssize_t size; + + int i = fill_command(sl, SG_DXFER_FROM_DEV, 0); + cmd[i++] = STLINK_DEBUG_COMMAND; + cmd[i++] = STLINK_DEBUG_APIV2_START_TRACE_RX; + write_uint16(&cmd[i + 0], STLINK_TRACE_BUF_LEN); + write_uint32(&cmd[i + 2], STLINK_TRACE_FREQUENCY); + + size = send_only(slu, 1, cmd, slu->cmd_len); + + if (size == -1) { + printf("[!] send_only STLINK_DEBUG_APIV2_START_TRACE_RX\n"); + return((int)size); + } + + return(0); +} + +int _stlink_usb_disable_trace(stlink_t* sl) { + struct stlink_libusb * const slu = sl->backend_data; + unsigned char* const cmd = sl->c_buf; + ssize_t size; + + int i = fill_command(sl, SG_DXFER_FROM_DEV, 0); + cmd[i++] = STLINK_DEBUG_COMMAND; + cmd[i++] = STLINK_DEBUG_APIV2_STOP_TRACE_RX; + + size = send_only(slu, 1, cmd, slu->cmd_len); + + if (size == -1) { + printf("[!] send_only STLINK_DEBUG_APIV2_STOP_TRACE_RX\n"); + return((int)size); + } + + return(0); +} + +int _stlink_usb_read_trace(stlink_t* sl, uint8_t* buf, size_t size) { + struct stlink_libusb * const slu = sl->backend_data; + unsigned char* const data = sl->q_buf; + unsigned char* const cmd = sl->c_buf; + uint32_t rep_len = 2; + int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); + + cmd[i++] = STLINK_DEBUG_COMMAND; + cmd[i++] = STLINK_DEBUG_APIV2_GET_TRACE_NB; + ssize_t send_size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); + + if (send_size == -1) { + printf("[!] send_recv STLINK_DEBUG_APIV2_GET_TRACE_NB\n"); + return((int)send_size); + } + + stlink_print_data(sl); + size_t trace_count = read_uint16(sl->q_buf, 0); + DLOG("trace_count = 0x%08x\n", trace_count); + + if (trace_count > size) { + ELOG("read_trace insufficient buffer length\n"); + return -1; + } + + int res = 0; + int t = libusb_bulk_transfer(slu->usb_handle, slu->ep_trace, buf, trace_count, &res, 3000); + + if (t) { + ELOG("read_trace read error\n"); + return(-1); + } + + return trace_count; +} + static stlink_backend_t _stlink_usb_backend = { _stlink_usb_close, _stlink_usb_exit_debug_mode, @@ -999,7 +1075,10 @@ static stlink_backend_t _stlink_usb_backend = { _stlink_usb_current_mode, _stlink_usb_force_debug, _stlink_usb_target_voltage, - _stlink_usb_set_swdclk + _stlink_usb_set_swdclk, + _stlink_usb_enable_trace, + _stlink_usb_disable_trace, + _stlink_usb_read_trace }; stlink_t *stlink_open_usb(enum ugly_loglevel verbose, int reset, char serial[STLINK_SERIAL_MAX_SIZE], int freq) { @@ -1161,8 +1240,10 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, int reset, char serial[STL desc.idProduct == STLINK_USB_PID_STLINK_V3S_PID || desc.idProduct == STLINK_USB_PID_STLINK_V3_2VCP_PID) { slu->ep_req = 1 /* ep req */ | LIBUSB_ENDPOINT_OUT; + slu->ep_trace = 2 | LIBUSB_ENDPOINT_IN; } else { slu->ep_req = 2 /* ep req */ | LIBUSB_ENDPOINT_OUT; + slu->ep_trace = 3 | LIBUSB_ENDPOINT_IN; } slu->sg_transfer_idx = 0; diff --git a/src/stlink-lib/usb.h b/src/stlink-lib/usb.h index d11f17381..717a82f6d 100644 --- a/src/stlink-lib/usb.h +++ b/src/stlink-lib/usb.h @@ -53,6 +53,7 @@ struct stlink_libusb { libusb_device_handle* usb_handle; unsigned int ep_req; unsigned int ep_rep; + unsigned int ep_trace; int protocoll; unsigned int sg_transfer_idx; unsigned int cmd_len; From 2900571f95cfaf7880b9bba0008e56fb07bea09a Mon Sep 17 00:00:00 2001 From: John Hall Date: Sat, 28 Nov 2020 17:02:49 +0000 Subject: [PATCH 117/503] In progress. --- src/st-trace/trace.c | 57 ++++++++++++++++++++++++-------------------- src/stlink-lib/usb.c | 4 ++-- 2 files changed, 33 insertions(+), 28 deletions(-) diff --git a/src/st-trace/trace.c b/src/st-trace/trace.c index 0bbec903e..2918fd61e 100644 --- a/src/st-trace/trace.c +++ b/src/st-trace/trace.c @@ -155,6 +155,11 @@ static bool IsDeviceTraceSupported(int chip_id) { } } +static void Write32(stlink_t* stlink, uint32_t address, uint32_t data) { + write_uint32(stlink->q_buf, data); + stlink_write_mem32(stlink, address, 4); +} + static bool EnableTrace(stlink_t* stlink, int core_frequency_mhz, bool reset_board) { if (stlink_force_debug(stlink)) { @@ -168,28 +173,28 @@ static bool EnableTrace(stlink_t* stlink, int core_frequency_mhz, bool reset_boa // The remainder of the items in this function were taken directly from https://github.com/avrhack/stlink-trace/blob/master/stlink-trace.c#L386 // Set DHCSR to C_HALT and C_DEBUGEN - stlink_write_debug32(stlink, 0xE000EDF0, 0xA05F0003); + Write32(stlink, 0xE000EDF0, 0xA05F0003); // Set TRCENA flag to enable global DWT and ITM - stlink_write_debug32(stlink, 0xE000EDFC, 0x01000000); + Write32(stlink, 0xE000EDFC, 0x01000000); // Set FP_CTRL to enable write - stlink_write_debug32(stlink, 0xE0002000, 0x00000002); + Write32(stlink, 0xE0002000, 0x00000002); // Set DWT_FUNCTION0 to DWT_FUNCTION3 to disable sampling - stlink_write_debug32(stlink, 0xE0001028, 0x00000000); - stlink_write_debug32(stlink, 0xE0001038, 0x00000000); - stlink_write_debug32(stlink, 0xE0001048, 0x00000000); - stlink_write_debug32(stlink, 0xE0001058, 0x00000000); + Write32(stlink, 0xE0001028, 0x00000000); + Write32(stlink, 0xE0001038, 0x00000000); + Write32(stlink, 0xE0001048, 0x00000000); + Write32(stlink, 0xE0001058, 0x00000000); // Clear DWT_CTRL and other registers - stlink_write_debug32(stlink, 0xE0001000, 0x00000000); - stlink_write_debug32(stlink, 0xE0001004, 0x00000000); - stlink_write_debug32(stlink, 0xE0001008, 0x00000000); - stlink_write_debug32(stlink, 0xE000100C, 0x00000000); - stlink_write_debug32(stlink, 0xE0001010, 0x00000000); - stlink_write_debug32(stlink, 0xE0001014, 0x00000000); - stlink_write_debug32(stlink, 0xE0001018, 0x00000000); + Write32(stlink, 0xE0001000, 0x00000000); + Write32(stlink, 0xE0001004, 0x00000000); + Write32(stlink, 0xE0001008, 0x00000000); + Write32(stlink, 0xE000100C, 0x00000000); + Write32(stlink, 0xE0001010, 0x00000000); + Write32(stlink, 0xE0001014, 0x00000000); + Write32(stlink, 0xE0001018, 0x00000000); // We should be checking these regisers. struct stlink_reg regp = {}; @@ -197,44 +202,44 @@ static bool EnableTrace(stlink_t* stlink, int core_frequency_mhz, bool reset_boa stlink_read_reg(stlink, 16, ®p); // Read xpsr register // Set DBGMCU_CR to enable asynchronous transmission - stlink_write_debug32(stlink, 0xE0042004, 0x00000027); + Write32(stlink, 0xE0042004, 0x00000027); // Actually start tracing. stlink_trace_enable(stlink); // Set TPIU_CSPSR to enable trace port width of 2 - stlink_write_debug32(stlink, 0xE0040004, 0x00000001); + Write32(stlink, 0xE0040004, 0x00000001); if (core_frequency_mhz) // Set TPIU_ACPR clock divisor - stlink_write_debug32(stlink, 0xE0040010, core_frequency_mhz / 2 - 1); + Write32(stlink, 0xE0040010, core_frequency_mhz / 2 - 1); // Set TPIU_SPPR to Asynchronous SWO (NRZ) - stlink_write_debug32(stlink, 0xE00400F0, 0x00000002); + Write32(stlink, 0xE00400F0, 0x00000002); // Set TPIU_FFCR continuous formatting) - stlink_write_debug32(stlink, 0xE0040304, 0x00000100); + Write32(stlink, 0xE0040304, 0x00000100); // Unlock the ITM registers for write - stlink_write_debug32(stlink, 0xE0000FB0, 0xC5ACCE55); + Write32(stlink, 0xE0000FB0, 0xC5ACCE55); // Set sync counter - stlink_write_debug32(stlink, 0xE0000E90, 0x00000400); + Write32(stlink, 0xE0000E90, 0x00000400); // Set ITM_TCR flags : ITMENA,TSENA ATB=0 - stlink_write_debug32(stlink, 0xE0000E80, 0x00010003); + Write32(stlink, 0xE0000E80, 0x00010003); // Enable all trace ports in ITM_TER - stlink_write_debug32(stlink, 0xE0000E00, 0xFFFFFFFF); + Write32(stlink, 0xE0000E00, 0xFFFFFFFF); // Enable unprivileged access to trace ports 31:0 in ITM_TPR - stlink_write_debug32(stlink, 0xE0000E40, 0x0000000F); + Write32(stlink, 0xE0000E40, 0x0000000F); // Set DWT_CTRL flags) - stlink_write_debug32(stlink, 0xE0000E40, 0x400003FE); // Keil one + Write32(stlink, 0xE0000E40, 0x400003FE); // Keil one // Enable tracing (DEMCR - TRCENA bit) - stlink_write_debug32(stlink, 0xE000EDFC, 0x01000000); + Write32(stlink, 0xE000EDFC, 0x01000000); return true; } diff --git a/src/stlink-lib/usb.c b/src/stlink-lib/usb.c index a7ebab0f3..a5d2c3678 100644 --- a/src/stlink-lib/usb.c +++ b/src/stlink-lib/usb.c @@ -977,7 +977,7 @@ int _stlink_usb_enable_trace(stlink_t* sl) { unsigned char* const cmd = sl->c_buf; ssize_t size; - int i = fill_command(sl, SG_DXFER_FROM_DEV, 0); + int i = fill_command(sl, SG_DXFER_TO_DEV, 0); cmd[i++] = STLINK_DEBUG_COMMAND; cmd[i++] = STLINK_DEBUG_APIV2_START_TRACE_RX; write_uint16(&cmd[i + 0], STLINK_TRACE_BUF_LEN); @@ -998,7 +998,7 @@ int _stlink_usb_disable_trace(stlink_t* sl) { unsigned char* const cmd = sl->c_buf; ssize_t size; - int i = fill_command(sl, SG_DXFER_FROM_DEV, 0); + int i = fill_command(sl, SG_DXFER_TO_DEV, 0); cmd[i++] = STLINK_DEBUG_COMMAND; cmd[i++] = STLINK_DEBUG_APIV2_STOP_TRACE_RX; From 737894cbe080da25c20b451298cfaadf8b0fc0fa Mon Sep 17 00:00:00 2001 From: John Hall Date: Sat, 28 Nov 2020 20:58:54 -0800 Subject: [PATCH 118/503] Got basic trace data transfer working. Still needs to decode the data stream. --- raspberrypi-build.sh | 20 -------- src/st-trace/trace.c | 114 ++++++++++++++++++++++++++----------------- src/stlink-lib/usb.c | 35 +++++++++---- 3 files changed, 93 insertions(+), 76 deletions(-) delete mode 100755 raspberrypi-build.sh diff --git a/raspberrypi-build.sh b/raspberrypi-build.sh deleted file mode 100755 index 7f77dab45..000000000 --- a/raspberrypi-build.sh +++ /dev/null @@ -1,20 +0,0 @@ -#!/bin/bash - -mkdir -p build/raspberry -mkdir -p build/raspberry/inc -mkdir -p build/raspberry/bin - -cat << EOF > build/raspberry/inc/version.h -#ifndef STLINK_VERSION_H_ -#define STLINK_VERSION_H_ - -#define STLINK_VERSION "1.6.1-116-g27d3-pi-dirty" -#define STLINK_VERSION_MAJOR 1 -#define STLINK_VERSION_MINOR 6 -#define STLINK_VERSION_PATCH 1 - -#endif // STLINK_VERSION_H_ -EOF - -gcc -std=gnu99 -Iinc -Isrc/stlink-lib/ -I/usr/include/libusb-1.0/ -Ibuild/raspberry/inc -DLIBUSB_API_VERSION=MINIMAL_API_VERSION -DSTLINK_HAVE_SYS_MMAN_H src/*.c src/stlink-lib/*.c src/st-trace/*.c -lusb-1.0 -o build/raspberry/bin/st-trace - diff --git a/src/st-trace/trace.c b/src/st-trace/trace.c index 2918fd61e..9146dd2bc 100644 --- a/src/st-trace/trace.c +++ b/src/st-trace/trace.c @@ -4,6 +4,9 @@ #include #include #include +#include +#include +#include #include #include @@ -20,6 +23,9 @@ #define APP_RESULT_STLINK_STATE_ERROR 5 +static bool g_done = false; + + struct _st_settings_t { bool show_help; @@ -45,6 +51,10 @@ static void usage(void) { puts(" -a, --no-sync Do not wait for a sync packet"); } +static void cleanup() { + g_done = true; +} + bool parse_options(int argc, char** argv, st_settings_t *settings) { static struct option long_options[] = { @@ -161,6 +171,7 @@ static void Write32(stlink_t* stlink, uint32_t address, uint32_t data) { } static bool EnableTrace(stlink_t* stlink, int core_frequency_mhz, bool reset_board) { + struct stlink_reg regp = {}; if (stlink_force_debug(stlink)) { return false; @@ -172,23 +183,14 @@ static bool EnableTrace(stlink_t* stlink, int core_frequency_mhz, bool reset_boa // The remainder of the items in this function were taken directly from https://github.com/avrhack/stlink-trace/blob/master/stlink-trace.c#L386 - // Set DHCSR to C_HALT and C_DEBUGEN - Write32(stlink, 0xE000EDF0, 0xA05F0003); - - // Set TRCENA flag to enable global DWT and ITM - Write32(stlink, 0xE000EDFC, 0x01000000); - - // Set FP_CTRL to enable write - Write32(stlink, 0xE0002000, 0x00000002); - - // Set DWT_FUNCTION0 to DWT_FUNCTION3 to disable sampling - Write32(stlink, 0xE0001028, 0x00000000); + Write32(stlink, 0xE000EDF0, 0xA05F0003); // Set DHCSR to C_HALT and C_DEBUGEN + Write32(stlink, 0xE000EDFC, 0x01000000); // Set TRCENA flag to enable global DWT and ITM + Write32(stlink, 0xE0002000, 0x00000002); // Set FP_CTRL to enable write + Write32(stlink, 0xE0001028, 0x00000000); // Set DWT_FUNCTION0 to DWT_FUNCTION3 to disable sampling Write32(stlink, 0xE0001038, 0x00000000); Write32(stlink, 0xE0001048, 0x00000000); Write32(stlink, 0xE0001058, 0x00000000); - - // Clear DWT_CTRL and other registers - Write32(stlink, 0xE0001000, 0x00000000); + Write32(stlink, 0xE0001000, 0x00000000); // Clear DWT_CTRL and other registers Write32(stlink, 0xE0001004, 0x00000000); Write32(stlink, 0xE0001008, 0x00000000); Write32(stlink, 0xE000100C, 0x00000000); @@ -196,50 +198,60 @@ static bool EnableTrace(stlink_t* stlink, int core_frequency_mhz, bool reset_boa Write32(stlink, 0xE0001014, 0x00000000); Write32(stlink, 0xE0001018, 0x00000000); - // We should be checking these regisers. - struct stlink_reg regp = {}; stlink_read_reg(stlink, 15, ®p); // Read program counter stlink_read_reg(stlink, 16, ®p); // Read xpsr register - // Set DBGMCU_CR to enable asynchronous transmission - Write32(stlink, 0xE0042004, 0x00000027); + Write32(stlink, 0xE0042004, 0x00000027); // Set DBGMCU_CR to enable asynchronous transmission // Actually start tracing. - stlink_trace_enable(stlink); - - // Set TPIU_CSPSR to enable trace port width of 2 - Write32(stlink, 0xE0040004, 0x00000001); + if (stlink_trace_enable(stlink)) { + return false; + } - if (core_frequency_mhz) - // Set TPIU_ACPR clock divisor - Write32(stlink, 0xE0040010, core_frequency_mhz / 2 - 1); + Write32(stlink, 0xE0040004, 0x00000001); // Set TPIU_CSPSR to enable trace port width of 2 - // Set TPIU_SPPR to Asynchronous SWO (NRZ) - Write32(stlink, 0xE00400F0, 0x00000002); + if (core_frequency_mhz) { + uint32_t clock_divisor = core_frequency_mhz / 2 - 1; + Write32(stlink, 0xE0040010, clock_divisor); // Set TPIU_ACPR clock divisor + } - // Set TPIU_FFCR continuous formatting) - Write32(stlink, 0xE0040304, 0x00000100); + Write32(stlink, 0xE00400F0, 0x00000002); // Set TPIU_SPPR to Asynchronous SWO (NRZ) + Write32(stlink, 0xE0040304, 0x00000100); // Set TPIU_FFCR continuous formatting) + Write32(stlink, 0xE0000FB0, 0xC5ACCE55); // Unlock the ITM registers for write + Write32(stlink, 0xE0000E90, 0x00000400); // Set sync counter + Write32(stlink, 0xE0000E80, 0x00010003); // Set ITM_TCR flags : ITMENA,TSENA ATB=0 + Write32(stlink, 0xE0000E00, 0xFFFFFFFF); // Enable all trace ports in ITM_TER + Write32(stlink, 0xE0000E40, 0x0000000F); // Enable unprivileged access to trace ports 31:0 in ITM_TPR + Write32(stlink, 0xE0000E40, 0x400003FE); // Set DWT_CTRL flags) + Write32(stlink, 0xE000EDFC, 0x01000000); // Enable tracing (DEMCR - TRCENA bit) - // Unlock the ITM registers for write - Write32(stlink, 0xE0000FB0, 0xC5ACCE55); + return true; +} - // Set sync counter - Write32(stlink, 0xE0000E90, 0x00000400); +static bool ReadTrace(stlink_t* stlink) { + uint8_t buffer[STLINK_TRACE_BUF_LEN]; + int length = stlink_trace_read(stlink, buffer, sizeof(buffer)); - // Set ITM_TCR flags : ITMENA,TSENA ATB=0 - Write32(stlink, 0xE0000E80, 0x00010003); + if (length < 0) { + ELOG("Error reading trace (%d)\n", length); + return false; + } - // Enable all trace ports in ITM_TER - Write32(stlink, 0xE0000E00, 0xFFFFFFFF); + if (length == 0) { + usleep(1000); + return true; + } - // Enable unprivileged access to trace ports 31:0 in ITM_TPR - Write32(stlink, 0xE0000E40, 0x0000000F); + DLOG("Trace Length: %d\n", length); - // Set DWT_CTRL flags) - Write32(stlink, 0xE0000E40, 0x400003FE); // Keil one + printf("Data: "); + for (int i = 0; i < length; i++) + printf("%02x ", buffer[i]); + printf(" '"); + for (int i = 0; i < length; i++) + printf("%c", isprint(buffer[i]) ? buffer[i] : '?'); + printf("'\n"); - // Enable tracing (DEMCR - TRCENA bit) - Write32(stlink, 0xE000EDFC, 0x01000000); return true; } @@ -249,6 +261,10 @@ int main(int argc, char** argv) st_settings_t settings; stlink_t* stlink = NULL; + signal(SIGINT, &cleanup); + signal(SIGTERM, &cleanup); + signal(SIGSEGV, &cleanup); + if (!parse_options(argc, argv, &settings)) { usage(); return APP_RESULT_INVALID_PARAMS; @@ -278,6 +294,8 @@ int main(int argc, char** argv) return APP_RESULT_STLINK_NOT_FOUND; } + stlink->verbose = settings.logging_level; + if (stlink->chip_id == STLINK_CHIPID_UNKNOWN) { ELOG("st-link not connected\n"); return APP_RESULT_STLINK_MISSING_DEVICE; @@ -295,16 +313,20 @@ int main(int argc, char** argv) ELOG("Unable to enable trace mode\n"); return APP_RESULT_STLINK_STATE_ERROR; } - + if (stlink_run(stlink)) { ELOG("Unable to run device\n"); return APP_RESULT_STLINK_STATE_ERROR; } + ILOG("Reading SWO Data\n"); - // Read SWO output - + while (!g_done) { + if (!ReadTrace(stlink)) + g_done = true; + } + stlink_trace_disable(stlink); stlink_close(stlink); return APP_RESULT_SUCCESS; diff --git a/src/stlink-lib/usb.c b/src/stlink-lib/usb.c index a5d2c3678..4d8d78a65 100644 --- a/src/stlink-lib/usb.c +++ b/src/stlink-lib/usb.c @@ -974,41 +974,51 @@ int _stlink_usb_write_reg(stlink_t *sl, uint32_t reg, int idx) { int _stlink_usb_enable_trace(stlink_t* sl) { struct stlink_libusb * const slu = sl->backend_data; + unsigned char* const data = sl->q_buf; unsigned char* const cmd = sl->c_buf; ssize_t size; + uint32_t rep_len = 2; - int i = fill_command(sl, SG_DXFER_TO_DEV, 0); + int i = fill_command(sl, SG_DXFER_TO_DEV, rep_len); cmd[i++] = STLINK_DEBUG_COMMAND; cmd[i++] = STLINK_DEBUG_APIV2_START_TRACE_RX; write_uint16(&cmd[i + 0], STLINK_TRACE_BUF_LEN); write_uint32(&cmd[i + 2], STLINK_TRACE_FREQUENCY); - size = send_only(slu, 1, cmd, slu->cmd_len); + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); if (size == -1) { printf("[!] send_only STLINK_DEBUG_APIV2_START_TRACE_RX\n"); return((int)size); } + sl->q_len = (int)size; + stlink_print_data(sl); + return(0); } int _stlink_usb_disable_trace(stlink_t* sl) { struct stlink_libusb * const slu = sl->backend_data; + unsigned char* const data = sl->q_buf; unsigned char* const cmd = sl->c_buf; ssize_t size; + uint32_t rep_len = 2; - int i = fill_command(sl, SG_DXFER_TO_DEV, 0); + int i = fill_command(sl, SG_DXFER_TO_DEV, rep_len); cmd[i++] = STLINK_DEBUG_COMMAND; cmd[i++] = STLINK_DEBUG_APIV2_STOP_TRACE_RX; - size = send_only(slu, 1, cmd, slu->cmd_len); + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); if (size == -1) { printf("[!] send_only STLINK_DEBUG_APIV2_STOP_TRACE_RX\n"); return((int)size); } + sl->q_len = (int)size; + stlink_print_data(sl); + return(0); } @@ -1027,8 +1037,11 @@ int _stlink_usb_read_trace(stlink_t* sl, uint8_t* buf, size_t size) { printf("[!] send_recv STLINK_DEBUG_APIV2_GET_TRACE_NB\n"); return((int)send_size); } + if (send_size != 2) { + printf("[!] send_recv STLINK_DEBUG_APIV2_GET_TRACE_NB %d\n", (int)send_size); + return -1; + } - stlink_print_data(sl); size_t trace_count = read_uint16(sl->q_buf, 0); DLOG("trace_count = 0x%08x\n", trace_count); @@ -1037,12 +1050,14 @@ int _stlink_usb_read_trace(stlink_t* sl, uint8_t* buf, size_t size) { return -1; } - int res = 0; - int t = libusb_bulk_transfer(slu->usb_handle, slu->ep_trace, buf, trace_count, &res, 3000); + if (trace_count != 0) { + int res = 0; + int t = libusb_bulk_transfer(slu->usb_handle, slu->ep_trace, buf, trace_count, &res, 3000); - if (t) { - ELOG("read_trace read error\n"); - return(-1); + if (t) { + ELOG("read_trace read error\n"); + return(-1); + } } return trace_count; From 9c86d53341e2dd1a8b168d79bc53ccf45008638a Mon Sep 17 00:00:00 2001 From: John Hall Date: Sat, 28 Nov 2020 23:47:29 -0800 Subject: [PATCH 119/503] Added a state machine to parse trace output. Improved comments. --- src/st-trace/trace.c | 134 +++++++++++++++++++++++++++++++++---------- 1 file changed, 103 insertions(+), 31 deletions(-) diff --git a/src/st-trace/trace.c b/src/st-trace/trace.c index 9146dd2bc..ccb1a4828 100644 --- a/src/st-trace/trace.c +++ b/src/st-trace/trace.c @@ -15,30 +15,63 @@ #define DEFAULT_LOGGING_LEVEL 50 #define DEBUG_LOGGING_LEVEL 100 -#define APP_RESULT_SUCCESS 0 -#define APP_RESULT_INVALID_PARAMS 1 -#define APP_RESULT_STLINK_NOT_FOUND 2 -#define APP_RESULT_STLINK_MISSING_DEVICE 3 -#define APP_RESULT_STLINK_UNSUPPORTED_DEVICE 4 -#define APP_RESULT_STLINK_STATE_ERROR 5 - - +#define APP_RESULT_SUCCESS 0 +#define APP_RESULT_INVALID_PARAMS 1 +#define APP_RESULT_STLINK_NOT_FOUND 2 +#define APP_RESULT_STLINK_MISSING_DEVICE 3 +#define APP_RESULT_STLINK_UNSUPPORTED_DEVICE 4 +#define APP_RESULT_STLINK_STATE_ERROR 5 + +// See https://developer.arm.com/documentation/ddi0403/ed/ +#define TRACE_OP_IS_OVERFLOW(c) ((c) == 0x70) +#define TRACE_OP_IS_LOCAL_TIME(c) (((c) & 0x0f) == 0x00 && ((c) & 0x70) != 0x00) +#define TRACE_OP_IS_EXTENSION(c) (((c) & 0x0b) == 0x08) +#define TRACE_OP_IS_GLOBAL_TIME(c) (((c) & 0xdf) == 0x94) +#define TRACE_OP_IS_SOURCE(c) (((c) & 0x03) != 0x00) +#define TRACE_OP_IS_SW_SOURCE(c) (((c) & 0x03) != 0x00 && ((c) & 0x04) == 0x00) +#define TRACE_OP_IS_HW_SOURCE(c) (((c) & 0x03) != 0x00 && ((c) & 0x04) == 0x04) +#define TRACE_OP_IS_TARGET_SOURCE(c) ((c) == 0x01) + +#define TRACE_OP_GET_CONTINUATION(c) ((c) & 0x80) +#define TRACE_OP_GET_SOURCE_SIZE(c) ((c) & 0x03) +#define TRACE_OP_GET_SW_SOURCE_ADDR(c) ((c) >> 3) + + +// We use a global flag to allow communicating to the main thread from the signal handler. static bool g_done = false; -struct _st_settings_t -{ +struct _st_settings_t { bool show_help; bool show_version; int logging_level; int core_frequency_mhz; bool reset_board; char* serial_number; - bool wait_sync; }; typedef struct _st_settings_t st_settings_t; +// We use a simple state machine to parse the trace data. +enum _trace_step { + TRACE_STEP_IDLE, + TRACE_STEP_TARGET_SOURCE, + TRACE_STEP_SKIP_FRAME, + TRACE_STEP_SKIP_4, + TRACE_STEP_SKIP_3, + TRACE_STEP_SKIP_2, + TRACE_STEP_SKIP_1, +}; +typedef enum _trace_step trace_step; + +struct _st_trace_state_t { + trace_step step; + bool overflow; + bool error; +}; +typedef struct _st_trace_state_t st_trace_state_t; + + static void usage(void) { puts("st-trace - usage:"); puts(" -h, --help Print this help"); @@ -48,7 +81,6 @@ static void usage(void) { puts(" -cXX, --clock=XX Specify the core frequency in MHz"); puts(" -n, --no-reset Do not reset board on connection"); puts(" -sXX, --serial=XX Use a specific serial number"); - puts(" -a, --no-sync Do not wait for a sync packet"); } static void cleanup() { @@ -64,7 +96,6 @@ bool parse_options(int argc, char** argv, st_settings_t *settings) { {"clock", required_argument, NULL, 'c'}, {"no-reset", no_argument, NULL, 'n'}, {"serial", required_argument, NULL, 's'}, - {"no-sync", no_argument, NULL, 'a'}, {0, 0, 0, 0}, }; int option_index = 0; @@ -76,10 +107,9 @@ bool parse_options(int argc, char** argv, st_settings_t *settings) { settings->core_frequency_mhz = 0; settings->reset_board = true; settings->serial_number = NULL; - settings->wait_sync = true; ugly_init(settings->logging_level); - while ((c = getopt_long(argc, argv, "hVv::c:ns:a", long_options, &option_index)) != -1) { + while ((c = getopt_long(argc, argv, "hVv::c:ns:", long_options, &option_index)) != -1) { switch (c) { case 'h': settings->show_help = true; @@ -104,9 +134,6 @@ bool parse_options(int argc, char** argv, st_settings_t *settings) { case 's': settings->serial_number = optarg; break; - case 'a': - settings->wait_sync = false; - break; case '?': return false; break; @@ -128,6 +155,7 @@ bool parse_options(int argc, char** argv, st_settings_t *settings) { static stlink_t* StLinkConnect(const st_settings_t* settings) { if (settings->serial_number) { + // Convert our serial number string to a binary value. char serial_number[STLINK_SERIAL_MAX_SIZE] = { 0 }; size_t length = 0; for (uint32_t n = 0; n < strlen(settings->serial_number) && length < STLINK_SERIAL_MAX_SIZE; n += 2) { @@ -135,13 +163,16 @@ static stlink_t* StLinkConnect(const st_settings_t* settings) { memcpy(buffer, settings->serial_number + n, 2); serial_number[length++] = (uint8_t)strtol(buffer, NULL, 16); } + + // Open this specific stlink. return stlink_open_usb(settings->logging_level, false, serial_number, 0); } else { + // Otherwise, open any stlink. return stlink_open_usb(settings->logging_level, false, NULL, 0); } } -// TODO: Move this to device table. +// TODO: Consider moving this to the device table. static bool IsDeviceTraceSupported(int chip_id) { switch (chip_id) { case STLINK_CHIPID_STM32_F4: @@ -228,7 +259,7 @@ static bool EnableTrace(stlink_t* stlink, int core_frequency_mhz, bool reset_boa return true; } -static bool ReadTrace(stlink_t* stlink) { +static bool ReadTrace(stlink_t* stlink, st_trace_state_t* state) { uint8_t buffer[STLINK_TRACE_BUF_LEN]; int length = stlink_trace_read(stlink, buffer, sizeof(buffer)); @@ -244,14 +275,55 @@ static bool ReadTrace(stlink_t* stlink) { DLOG("Trace Length: %d\n", length); - printf("Data: "); - for (int i = 0; i < length; i++) - printf("%02x ", buffer[i]); - printf(" '"); - for (int i = 0; i < length; i++) - printf("%c", isprint(buffer[i]) ? buffer[i] : '?'); - printf("'\n"); - + for (int i = 0; i < length; i++) { + uint8_t c = buffer[i]; + + // Parse the input using a state machine. + switch (state->step) + { + case TRACE_STEP_IDLE: + if (TRACE_OP_IS_TARGET_SOURCE(c)) { + state->step = TRACE_STEP_TARGET_SOURCE; + } else if (TRACE_OP_IS_SOURCE(c)) { + const trace_step kSourceSkip[] = { TRACE_STEP_IDLE, TRACE_STEP_SKIP_1, TRACE_STEP_SKIP_2, TRACE_STEP_SKIP_4 }; + const char* type = TRACE_OP_IS_SW_SOURCE(c) ? "sw" : "hw"; + uint8_t addr = TRACE_OP_GET_SW_SOURCE_ADDR(c); + uint8_t size = TRACE_OP_GET_SOURCE_SIZE(c); + WLOG("Unsupported %s source 0x%x size %d", type, addr, size); + state->step = kSourceSkip[size]; + } else if (TRACE_OP_IS_LOCAL_TIME(c) || TRACE_OP_IS_EXTENSION(c) || TRACE_OP_IS_GLOBAL_TIME(c)) { + if (TRACE_OP_GET_CONTINUATION(c)) + state->step = TRACE_STEP_SKIP_FRAME; + } else if (TRACE_OP_IS_OVERFLOW(c)) { + state->overflow = true; + } else { + WLOG("Unknown opcode 0x%02x\n", c); + if (TRACE_OP_GET_CONTINUATION(c)) + state->step = TRACE_STEP_SKIP_FRAME; + } + break; + case TRACE_STEP_TARGET_SOURCE: + putchar(c); + state->step = TRACE_STEP_IDLE; + break; + case TRACE_STEP_SKIP_FRAME: + if (TRACE_OP_GET_CONTINUATION(c) == 0) + state->step = TRACE_STEP_IDLE; + break; + case TRACE_STEP_SKIP_4: + state->step = TRACE_STEP_SKIP_3; + break; + case TRACE_STEP_SKIP_3: + state->step = TRACE_STEP_SKIP_2; + break; + case TRACE_STEP_SKIP_2: + state->step = TRACE_STEP_SKIP_1; + break; + case TRACE_STEP_SKIP_1: + state->step = TRACE_STEP_IDLE; + break; + } + } return true; } @@ -276,7 +348,6 @@ int main(int argc, char** argv) DLOG("core_frequency = %d MHz\n", settings.core_frequency_mhz); DLOG("reset_board = %s\n", settings.reset_board ? "true" : "false"); DLOG("serial_number = %s\n", settings.serial_number ? settings.serial_number : "any"); - DLOG("wait_sync = %s\n", settings.wait_sync ? "true" : "false"); if (settings.show_help) { usage(); @@ -319,10 +390,11 @@ int main(int argc, char** argv) return APP_RESULT_STLINK_STATE_ERROR; } - ILOG("Reading SWO Data\n"); + ILOG("Reading.\n"); + st_trace_state_t state = {}; while (!g_done) { - if (!ReadTrace(stlink)) + if (!ReadTrace(stlink, &state)) g_done = true; } From 8793f3ceef06a394c6ea8120dbe58ddd28b42ba4 Mon Sep 17 00:00:00 2001 From: John Hall Date: Sun, 29 Nov 2020 00:25:00 -0800 Subject: [PATCH 120/503] Tabs to spaces --- src/st-trace/trace.c | 670 +++++++++++++++++++++---------------------- 1 file changed, 335 insertions(+), 335 deletions(-) diff --git a/src/st-trace/trace.c b/src/st-trace/trace.c index ccb1a4828..bb516ebf0 100644 --- a/src/st-trace/trace.c +++ b/src/st-trace/trace.c @@ -15,26 +15,26 @@ #define DEFAULT_LOGGING_LEVEL 50 #define DEBUG_LOGGING_LEVEL 100 -#define APP_RESULT_SUCCESS 0 -#define APP_RESULT_INVALID_PARAMS 1 -#define APP_RESULT_STLINK_NOT_FOUND 2 -#define APP_RESULT_STLINK_MISSING_DEVICE 3 -#define APP_RESULT_STLINK_UNSUPPORTED_DEVICE 4 -#define APP_RESULT_STLINK_STATE_ERROR 5 +#define APP_RESULT_SUCCESS 0 +#define APP_RESULT_INVALID_PARAMS 1 +#define APP_RESULT_STLINK_NOT_FOUND 2 +#define APP_RESULT_STLINK_MISSING_DEVICE 3 +#define APP_RESULT_STLINK_UNSUPPORTED_DEVICE 4 +#define APP_RESULT_STLINK_STATE_ERROR 5 // See https://developer.arm.com/documentation/ddi0403/ed/ -#define TRACE_OP_IS_OVERFLOW(c) ((c) == 0x70) -#define TRACE_OP_IS_LOCAL_TIME(c) (((c) & 0x0f) == 0x00 && ((c) & 0x70) != 0x00) -#define TRACE_OP_IS_EXTENSION(c) (((c) & 0x0b) == 0x08) -#define TRACE_OP_IS_GLOBAL_TIME(c) (((c) & 0xdf) == 0x94) -#define TRACE_OP_IS_SOURCE(c) (((c) & 0x03) != 0x00) -#define TRACE_OP_IS_SW_SOURCE(c) (((c) & 0x03) != 0x00 && ((c) & 0x04) == 0x00) -#define TRACE_OP_IS_HW_SOURCE(c) (((c) & 0x03) != 0x00 && ((c) & 0x04) == 0x04) -#define TRACE_OP_IS_TARGET_SOURCE(c) ((c) == 0x01) +#define TRACE_OP_IS_OVERFLOW(c) ((c) == 0x70) +#define TRACE_OP_IS_LOCAL_TIME(c) (((c) & 0x0f) == 0x00 && ((c) & 0x70) != 0x00) +#define TRACE_OP_IS_EXTENSION(c) (((c) & 0x0b) == 0x08) +#define TRACE_OP_IS_GLOBAL_TIME(c) (((c) & 0xdf) == 0x94) +#define TRACE_OP_IS_SOURCE(c) (((c) & 0x03) != 0x00) +#define TRACE_OP_IS_SW_SOURCE(c) (((c) & 0x03) != 0x00 && ((c) & 0x04) == 0x00) +#define TRACE_OP_IS_HW_SOURCE(c) (((c) & 0x03) != 0x00 && ((c) & 0x04) == 0x04) +#define TRACE_OP_IS_TARGET_SOURCE(c) ((c) == 0x01) -#define TRACE_OP_GET_CONTINUATION(c) ((c) & 0x80) -#define TRACE_OP_GET_SOURCE_SIZE(c) ((c) & 0x03) -#define TRACE_OP_GET_SW_SOURCE_ADDR(c) ((c) >> 3) +#define TRACE_OP_GET_CONTINUATION(c) ((c) & 0x80) +#define TRACE_OP_GET_SOURCE_SIZE(c) ((c) & 0x03) +#define TRACE_OP_GET_SW_SOURCE_ADDR(c) ((c) >> 3) // We use a global flag to allow communicating to the main thread from the signal handler. @@ -42,365 +42,365 @@ static bool g_done = false; struct _st_settings_t { - bool show_help; - bool show_version; - int logging_level; - int core_frequency_mhz; - bool reset_board; - char* serial_number; + bool show_help; + bool show_version; + int logging_level; + int core_frequency_mhz; + bool reset_board; + char* serial_number; }; typedef struct _st_settings_t st_settings_t; // We use a simple state machine to parse the trace data. enum _trace_step { - TRACE_STEP_IDLE, - TRACE_STEP_TARGET_SOURCE, - TRACE_STEP_SKIP_FRAME, - TRACE_STEP_SKIP_4, - TRACE_STEP_SKIP_3, - TRACE_STEP_SKIP_2, - TRACE_STEP_SKIP_1, + TRACE_STEP_IDLE, + TRACE_STEP_TARGET_SOURCE, + TRACE_STEP_SKIP_FRAME, + TRACE_STEP_SKIP_4, + TRACE_STEP_SKIP_3, + TRACE_STEP_SKIP_2, + TRACE_STEP_SKIP_1, }; typedef enum _trace_step trace_step; struct _st_trace_state_t { - trace_step step; - bool overflow; - bool error; + trace_step step; + bool overflow; + bool error; }; typedef struct _st_trace_state_t st_trace_state_t; static void usage(void) { - puts("st-trace - usage:"); - puts(" -h, --help Print this help"); - puts(" -V, --version Print this version"); - puts(" -vXX, --verbose=XX Specify a specific verbosity level (0..99)"); - puts(" -v, --verbose Specify a generally verbose logging"); - puts(" -cXX, --clock=XX Specify the core frequency in MHz"); - puts(" -n, --no-reset Do not reset board on connection"); - puts(" -sXX, --serial=XX Use a specific serial number"); + puts("st-trace - usage:"); + puts(" -h, --help Print this help"); + puts(" -V, --version Print this version"); + puts(" -vXX, --verbose=XX Specify a specific verbosity level (0..99)"); + puts(" -v, --verbose Specify a generally verbose logging"); + puts(" -cXX, --clock=XX Specify the core frequency in MHz"); + puts(" -n, --no-reset Do not reset board on connection"); + puts(" -sXX, --serial=XX Use a specific serial number"); } static void cleanup() { - g_done = true; + g_done = true; } bool parse_options(int argc, char** argv, st_settings_t *settings) { - static struct option long_options[] = { - {"help", no_argument, NULL, 'h'}, - {"version", no_argument, NULL, 'V'}, - {"verbose", optional_argument, NULL, 'v'}, - {"clock", required_argument, NULL, 'c'}, - {"no-reset", no_argument, NULL, 'n'}, - {"serial", required_argument, NULL, 's'}, - {0, 0, 0, 0}, - }; - int option_index = 0; - int c; - - settings->show_help = false; - settings->show_version = false; - settings->logging_level = DEFAULT_LOGGING_LEVEL; - settings->core_frequency_mhz = 0; - settings->reset_board = true; - settings->serial_number = NULL; - ugly_init(settings->logging_level); - - while ((c = getopt_long(argc, argv, "hVv::c:ns:", long_options, &option_index)) != -1) { - switch (c) { - case 'h': - settings->show_help = true; - break; - case 'V': - settings->show_version = true; - break; - case 'v': - if (optarg) { - settings->logging_level = atoi(optarg); - } else { - settings->logging_level = DEBUG_LOGGING_LEVEL; - } - ugly_init(settings->logging_level); - break; - case 'c': - settings->core_frequency_mhz = atoi(optarg); - break; - case 'n': - settings->reset_board = false; - break; - case 's': - settings->serial_number = optarg; - break; - case '?': - return false; - break; - default: - ELOG("Unknown command line option: '%c' (0x%02x)\n", c, c); - return false; - } - } - - if (optind < argc) { - while (optind < argc) { - ELOG("Unknown command line argument: '%s'\n", argv[optind++]); - } - return false; - } - - return true; + static struct option long_options[] = { + {"help", no_argument, NULL, 'h'}, + {"version", no_argument, NULL, 'V'}, + {"verbose", optional_argument, NULL, 'v'}, + {"clock", required_argument, NULL, 'c'}, + {"no-reset", no_argument, NULL, 'n'}, + {"serial", required_argument, NULL, 's'}, + {0, 0, 0, 0}, + }; + int option_index = 0; + int c; + + settings->show_help = false; + settings->show_version = false; + settings->logging_level = DEFAULT_LOGGING_LEVEL; + settings->core_frequency_mhz = 0; + settings->reset_board = true; + settings->serial_number = NULL; + ugly_init(settings->logging_level); + + while ((c = getopt_long(argc, argv, "hVv::c:ns:", long_options, &option_index)) != -1) { + switch (c) { + case 'h': + settings->show_help = true; + break; + case 'V': + settings->show_version = true; + break; + case 'v': + if (optarg) { + settings->logging_level = atoi(optarg); + } else { + settings->logging_level = DEBUG_LOGGING_LEVEL; + } + ugly_init(settings->logging_level); + break; + case 'c': + settings->core_frequency_mhz = atoi(optarg); + break; + case 'n': + settings->reset_board = false; + break; + case 's': + settings->serial_number = optarg; + break; + case '?': + return false; + break; + default: + ELOG("Unknown command line option: '%c' (0x%02x)\n", c, c); + return false; + } + } + + if (optind < argc) { + while (optind < argc) { + ELOG("Unknown command line argument: '%s'\n", argv[optind++]); + } + return false; + } + + return true; } static stlink_t* StLinkConnect(const st_settings_t* settings) { - if (settings->serial_number) { - // Convert our serial number string to a binary value. - char serial_number[STLINK_SERIAL_MAX_SIZE] = { 0 }; - size_t length = 0; - for (uint32_t n = 0; n < strlen(settings->serial_number) && length < STLINK_SERIAL_MAX_SIZE; n += 2) { - char buffer[3] = { 0 }; - memcpy(buffer, settings->serial_number + n, 2); - serial_number[length++] = (uint8_t)strtol(buffer, NULL, 16); - } - - // Open this specific stlink. - return stlink_open_usb(settings->logging_level, false, serial_number, 0); - } else { - // Otherwise, open any stlink. - return stlink_open_usb(settings->logging_level, false, NULL, 0); - } + if (settings->serial_number) { + // Convert our serial number string to a binary value. + char serial_number[STLINK_SERIAL_MAX_SIZE] = { 0 }; + size_t length = 0; + for (uint32_t n = 0; n < strlen(settings->serial_number) && length < STLINK_SERIAL_MAX_SIZE; n += 2) { + char buffer[3] = { 0 }; + memcpy(buffer, settings->serial_number + n, 2); + serial_number[length++] = (uint8_t)strtol(buffer, NULL, 16); + } + + // Open this specific stlink. + return stlink_open_usb(settings->logging_level, false, serial_number, 0); + } else { + // Otherwise, open any stlink. + return stlink_open_usb(settings->logging_level, false, NULL, 0); + } } // TODO: Consider moving this to the device table. static bool IsDeviceTraceSupported(int chip_id) { - switch (chip_id) { - case STLINK_CHIPID_STM32_F4: - case STLINK_CHIPID_STM32_F4_DSI: - case STLINK_CHIPID_STM32_F4_HD: - case STLINK_CHIPID_STM32_F4_LP: - case STLINK_CHIPID_STM32_F411RE: - case STLINK_CHIPID_STM32_F4_DE: - case STLINK_CHIPID_STM32_F446: - case STLINK_CHIPID_STM32_F410: - case STLINK_CHIPID_STM32_F3: - case STLINK_CHIPID_STM32_F37x: - case STLINK_CHIPID_STM32_F412: - case STLINK_CHIPID_STM32_F413: - case STLINK_CHIPID_STM32_F3_SMALL: - case STLINK_CHIPID_STM32_F334: - case STLINK_CHIPID_STM32_F303_HIGH: - return true; - default: - return false; - } + switch (chip_id) { + case STLINK_CHIPID_STM32_F4: + case STLINK_CHIPID_STM32_F4_DSI: + case STLINK_CHIPID_STM32_F4_HD: + case STLINK_CHIPID_STM32_F4_LP: + case STLINK_CHIPID_STM32_F411RE: + case STLINK_CHIPID_STM32_F4_DE: + case STLINK_CHIPID_STM32_F446: + case STLINK_CHIPID_STM32_F410: + case STLINK_CHIPID_STM32_F3: + case STLINK_CHIPID_STM32_F37x: + case STLINK_CHIPID_STM32_F412: + case STLINK_CHIPID_STM32_F413: + case STLINK_CHIPID_STM32_F3_SMALL: + case STLINK_CHIPID_STM32_F334: + case STLINK_CHIPID_STM32_F303_HIGH: + return true; + default: + return false; + } } static void Write32(stlink_t* stlink, uint32_t address, uint32_t data) { - write_uint32(stlink->q_buf, data); - stlink_write_mem32(stlink, address, 4); + write_uint32(stlink->q_buf, data); + stlink_write_mem32(stlink, address, 4); } static bool EnableTrace(stlink_t* stlink, int core_frequency_mhz, bool reset_board) { - struct stlink_reg regp = {}; - - if (stlink_force_debug(stlink)) { - return false; - } - - if (reset_board && stlink_reset(stlink)) { - return false; - } - - // The remainder of the items in this function were taken directly from https://github.com/avrhack/stlink-trace/blob/master/stlink-trace.c#L386 - - Write32(stlink, 0xE000EDF0, 0xA05F0003); // Set DHCSR to C_HALT and C_DEBUGEN - Write32(stlink, 0xE000EDFC, 0x01000000); // Set TRCENA flag to enable global DWT and ITM - Write32(stlink, 0xE0002000, 0x00000002); // Set FP_CTRL to enable write - Write32(stlink, 0xE0001028, 0x00000000); // Set DWT_FUNCTION0 to DWT_FUNCTION3 to disable sampling - Write32(stlink, 0xE0001038, 0x00000000); - Write32(stlink, 0xE0001048, 0x00000000); - Write32(stlink, 0xE0001058, 0x00000000); - Write32(stlink, 0xE0001000, 0x00000000); // Clear DWT_CTRL and other registers - Write32(stlink, 0xE0001004, 0x00000000); - Write32(stlink, 0xE0001008, 0x00000000); - Write32(stlink, 0xE000100C, 0x00000000); - Write32(stlink, 0xE0001010, 0x00000000); - Write32(stlink, 0xE0001014, 0x00000000); - Write32(stlink, 0xE0001018, 0x00000000); - - stlink_read_reg(stlink, 15, ®p); // Read program counter - stlink_read_reg(stlink, 16, ®p); // Read xpsr register - - Write32(stlink, 0xE0042004, 0x00000027); // Set DBGMCU_CR to enable asynchronous transmission - - // Actually start tracing. - if (stlink_trace_enable(stlink)) { - return false; - } - - Write32(stlink, 0xE0040004, 0x00000001); // Set TPIU_CSPSR to enable trace port width of 2 - - if (core_frequency_mhz) { - uint32_t clock_divisor = core_frequency_mhz / 2 - 1; - Write32(stlink, 0xE0040010, clock_divisor); // Set TPIU_ACPR clock divisor - } - - Write32(stlink, 0xE00400F0, 0x00000002); // Set TPIU_SPPR to Asynchronous SWO (NRZ) - Write32(stlink, 0xE0040304, 0x00000100); // Set TPIU_FFCR continuous formatting) - Write32(stlink, 0xE0000FB0, 0xC5ACCE55); // Unlock the ITM registers for write - Write32(stlink, 0xE0000E90, 0x00000400); // Set sync counter - Write32(stlink, 0xE0000E80, 0x00010003); // Set ITM_TCR flags : ITMENA,TSENA ATB=0 - Write32(stlink, 0xE0000E00, 0xFFFFFFFF); // Enable all trace ports in ITM_TER - Write32(stlink, 0xE0000E40, 0x0000000F); // Enable unprivileged access to trace ports 31:0 in ITM_TPR - Write32(stlink, 0xE0000E40, 0x400003FE); // Set DWT_CTRL flags) - Write32(stlink, 0xE000EDFC, 0x01000000); // Enable tracing (DEMCR - TRCENA bit) - - return true; + struct stlink_reg regp = {}; + + if (stlink_force_debug(stlink)) { + return false; + } + + if (reset_board && stlink_reset(stlink)) { + return false; + } + + // The order and values to set were taken from https://github.com/avrhack/stlink-trace/blob/master/stlink-trace.c#L386 + + Write32(stlink, 0xE000EDF0, 0xA05F0003); // Set DHCSR to C_HALT and C_DEBUGEN + Write32(stlink, 0xE000EDFC, 0x01000000); // Set TRCENA flag to enable global DWT and ITM + Write32(stlink, 0xE0002000, 0x00000002); // Set FP_CTRL to enable write + Write32(stlink, 0xE0001028, 0x00000000); // Set DWT_FUNCTION0 to DWT_FUNCTION3 to disable sampling + Write32(stlink, 0xE0001038, 0x00000000); + Write32(stlink, 0xE0001048, 0x00000000); + Write32(stlink, 0xE0001058, 0x00000000); + Write32(stlink, 0xE0001000, 0x00000000); // Clear DWT_CTRL and other registers + Write32(stlink, 0xE0001004, 0x00000000); + Write32(stlink, 0xE0001008, 0x00000000); + Write32(stlink, 0xE000100C, 0x00000000); + Write32(stlink, 0xE0001010, 0x00000000); + Write32(stlink, 0xE0001014, 0x00000000); + Write32(stlink, 0xE0001018, 0x00000000); + + stlink_read_reg(stlink, 15, ®p); // Read program counter + stlink_read_reg(stlink, 16, ®p); // Read xpsr register + + Write32(stlink, 0xE0042004, 0x00000027); // Set DBGMCU_CR to enable asynchronous transmission + + // Actually start tracing. + if (stlink_trace_enable(stlink)) { + return false; + } + + Write32(stlink, 0xE0040004, 0x00000001); // Set TPIU_CSPSR to enable trace port width of 2 + + if (core_frequency_mhz) { + uint32_t clock_divisor = core_frequency_mhz / 2 - 1; + Write32(stlink, 0xE0040010, clock_divisor); // Set TPIU_ACPR clock divisor + } + + Write32(stlink, 0xE00400F0, 0x00000002); // Set TPIU_SPPR to Asynchronous SWO (NRZ) + Write32(stlink, 0xE0040304, 0x00000100); // Set TPIU_FFCR continuous formatting) + Write32(stlink, 0xE0000FB0, 0xC5ACCE55); // Unlock the ITM registers for write + Write32(stlink, 0xE0000E90, 0x00000400); // Set sync counter + Write32(stlink, 0xE0000E80, 0x00010003); // Set ITM_TCR flags : ITMENA,TSENA ATB=0 + Write32(stlink, 0xE0000E00, 0xFFFFFFFF); // Enable all trace ports in ITM_TER + Write32(stlink, 0xE0000E40, 0x0000000F); // Enable unprivileged access to trace ports 31:0 in ITM_TPR + Write32(stlink, 0xE0000E40, 0x400003FE); // Set DWT_CTRL flags) + Write32(stlink, 0xE000EDFC, 0x01000000); // Enable tracing (DEMCR - TRCENA bit) + + return true; } static bool ReadTrace(stlink_t* stlink, st_trace_state_t* state) { - uint8_t buffer[STLINK_TRACE_BUF_LEN]; - int length = stlink_trace_read(stlink, buffer, sizeof(buffer)); - - if (length < 0) { - ELOG("Error reading trace (%d)\n", length); - return false; - } - - if (length == 0) { - usleep(1000); - return true; - } - - DLOG("Trace Length: %d\n", length); - - for (int i = 0; i < length; i++) { - uint8_t c = buffer[i]; - - // Parse the input using a state machine. - switch (state->step) - { - case TRACE_STEP_IDLE: - if (TRACE_OP_IS_TARGET_SOURCE(c)) { - state->step = TRACE_STEP_TARGET_SOURCE; - } else if (TRACE_OP_IS_SOURCE(c)) { - const trace_step kSourceSkip[] = { TRACE_STEP_IDLE, TRACE_STEP_SKIP_1, TRACE_STEP_SKIP_2, TRACE_STEP_SKIP_4 }; - const char* type = TRACE_OP_IS_SW_SOURCE(c) ? "sw" : "hw"; - uint8_t addr = TRACE_OP_GET_SW_SOURCE_ADDR(c); - uint8_t size = TRACE_OP_GET_SOURCE_SIZE(c); - WLOG("Unsupported %s source 0x%x size %d", type, addr, size); - state->step = kSourceSkip[size]; - } else if (TRACE_OP_IS_LOCAL_TIME(c) || TRACE_OP_IS_EXTENSION(c) || TRACE_OP_IS_GLOBAL_TIME(c)) { - if (TRACE_OP_GET_CONTINUATION(c)) - state->step = TRACE_STEP_SKIP_FRAME; - } else if (TRACE_OP_IS_OVERFLOW(c)) { - state->overflow = true; - } else { - WLOG("Unknown opcode 0x%02x\n", c); - if (TRACE_OP_GET_CONTINUATION(c)) - state->step = TRACE_STEP_SKIP_FRAME; - } - break; - case TRACE_STEP_TARGET_SOURCE: - putchar(c); - state->step = TRACE_STEP_IDLE; - break; - case TRACE_STEP_SKIP_FRAME: - if (TRACE_OP_GET_CONTINUATION(c) == 0) - state->step = TRACE_STEP_IDLE; - break; - case TRACE_STEP_SKIP_4: - state->step = TRACE_STEP_SKIP_3; - break; - case TRACE_STEP_SKIP_3: - state->step = TRACE_STEP_SKIP_2; - break; - case TRACE_STEP_SKIP_2: - state->step = TRACE_STEP_SKIP_1; - break; - case TRACE_STEP_SKIP_1: - state->step = TRACE_STEP_IDLE; - break; - } - } - - return true; + uint8_t buffer[STLINK_TRACE_BUF_LEN]; + int length = stlink_trace_read(stlink, buffer, sizeof(buffer)); + + if (length < 0) { + ELOG("Error reading trace (%d)\n", length); + return false; + } + + if (length == 0) { + usleep(1000); + return true; + } + + DLOG("Trace Length: %d\n", length); + + for (int i = 0; i < length; i++) { + uint8_t c = buffer[i]; + + // Parse the input using a state machine. + switch (state->step) + { + case TRACE_STEP_IDLE: + if (TRACE_OP_IS_TARGET_SOURCE(c)) { + state->step = TRACE_STEP_TARGET_SOURCE; + } else if (TRACE_OP_IS_SOURCE(c)) { + const trace_step kSourceSkip[] = { TRACE_STEP_IDLE, TRACE_STEP_SKIP_1, TRACE_STEP_SKIP_2, TRACE_STEP_SKIP_4 }; + const char* type = TRACE_OP_IS_SW_SOURCE(c) ? "sw" : "hw"; + uint8_t addr = TRACE_OP_GET_SW_SOURCE_ADDR(c); + uint8_t size = TRACE_OP_GET_SOURCE_SIZE(c); + WLOG("Unsupported %s source 0x%x size %d", type, addr, size); + state->step = kSourceSkip[size]; + } else if (TRACE_OP_IS_LOCAL_TIME(c) || TRACE_OP_IS_EXTENSION(c) || TRACE_OP_IS_GLOBAL_TIME(c)) { + if (TRACE_OP_GET_CONTINUATION(c)) + state->step = TRACE_STEP_SKIP_FRAME; + } else if (TRACE_OP_IS_OVERFLOW(c)) { + state->overflow = true; + } else { + WLOG("Unknown opcode 0x%02x\n", c); + if (TRACE_OP_GET_CONTINUATION(c)) + state->step = TRACE_STEP_SKIP_FRAME; + } + break; + case TRACE_STEP_TARGET_SOURCE: + putchar(c); + state->step = TRACE_STEP_IDLE; + break; + case TRACE_STEP_SKIP_FRAME: + if (TRACE_OP_GET_CONTINUATION(c) == 0) + state->step = TRACE_STEP_IDLE; + break; + case TRACE_STEP_SKIP_4: + state->step = TRACE_STEP_SKIP_3; + break; + case TRACE_STEP_SKIP_3: + state->step = TRACE_STEP_SKIP_2; + break; + case TRACE_STEP_SKIP_2: + state->step = TRACE_STEP_SKIP_1; + break; + case TRACE_STEP_SKIP_1: + state->step = TRACE_STEP_IDLE; + break; + } + } + + return true; } int main(int argc, char** argv) { - st_settings_t settings; - stlink_t* stlink = NULL; - - signal(SIGINT, &cleanup); - signal(SIGTERM, &cleanup); - signal(SIGSEGV, &cleanup); - - if (!parse_options(argc, argv, &settings)) { - usage(); - return APP_RESULT_INVALID_PARAMS; - } - - DLOG("show_help = %s\n", settings.show_help ? "true" : "false"); - DLOG("show_version = %s\n", settings.show_version ? "true" : "false"); - DLOG("logging_level = %d\n", settings.logging_level); - DLOG("core_frequency = %d MHz\n", settings.core_frequency_mhz); - DLOG("reset_board = %s\n", settings.reset_board ? "true" : "false"); - DLOG("serial_number = %s\n", settings.serial_number ? settings.serial_number : "any"); - - if (settings.show_help) { - usage(); - return APP_RESULT_SUCCESS; - } - - if (settings.show_version) { - printf("v%s\n", STLINK_VERSION); - return APP_RESULT_SUCCESS; - } - - stlink = StLinkConnect(&settings); - if (!stlink) { - ELOG("Unable to locate st-link\n"); - return APP_RESULT_STLINK_NOT_FOUND; - } - - stlink->verbose = settings.logging_level; - - if (stlink->chip_id == STLINK_CHIPID_UNKNOWN) { - ELOG("st-link not connected\n"); - return APP_RESULT_STLINK_MISSING_DEVICE; - } - - // TODO: Check if trace is supported by stlink. - - if (!IsDeviceTraceSupported(stlink->chip_id)) { - const struct stlink_chipid_params *params = stlink_chipid_get_params(stlink->chip_id); - ELOG("We do not support SWO output for device '%s'", params->description); - return APP_RESULT_STLINK_UNSUPPORTED_DEVICE; - } - - if (!EnableTrace(stlink, settings.core_frequency_mhz, settings.reset_board)) { - ELOG("Unable to enable trace mode\n"); - return APP_RESULT_STLINK_STATE_ERROR; - } - - if (stlink_run(stlink)) { - ELOG("Unable to run device\n"); - return APP_RESULT_STLINK_STATE_ERROR; - } - - ILOG("Reading.\n"); - - st_trace_state_t state = {}; - while (!g_done) { - if (!ReadTrace(stlink, &state)) - g_done = true; - } - - stlink_trace_disable(stlink); - stlink_close(stlink); - - return APP_RESULT_SUCCESS; + st_settings_t settings; + stlink_t* stlink = NULL; + + signal(SIGINT, &cleanup); + signal(SIGTERM, &cleanup); + signal(SIGSEGV, &cleanup); + + if (!parse_options(argc, argv, &settings)) { + usage(); + return APP_RESULT_INVALID_PARAMS; + } + + DLOG("show_help = %s\n", settings.show_help ? "true" : "false"); + DLOG("show_version = %s\n", settings.show_version ? "true" : "false"); + DLOG("logging_level = %d\n", settings.logging_level); + DLOG("core_frequency = %d MHz\n", settings.core_frequency_mhz); + DLOG("reset_board = %s\n", settings.reset_board ? "true" : "false"); + DLOG("serial_number = %s\n", settings.serial_number ? settings.serial_number : "any"); + + if (settings.show_help) { + usage(); + return APP_RESULT_SUCCESS; + } + + if (settings.show_version) { + printf("v%s\n", STLINK_VERSION); + return APP_RESULT_SUCCESS; + } + + stlink = StLinkConnect(&settings); + if (!stlink) { + ELOG("Unable to locate st-link\n"); + return APP_RESULT_STLINK_NOT_FOUND; + } + + stlink->verbose = settings.logging_level; + + if (stlink->chip_id == STLINK_CHIPID_UNKNOWN) { + ELOG("st-link not connected\n"); + return APP_RESULT_STLINK_MISSING_DEVICE; + } + + // TODO: Check if trace is supported by stlink. + + if (!IsDeviceTraceSupported(stlink->chip_id)) { + const struct stlink_chipid_params *params = stlink_chipid_get_params(stlink->chip_id); + ELOG("We do not support SWO output for device '%s'", params->description); + return APP_RESULT_STLINK_UNSUPPORTED_DEVICE; + } + + if (!EnableTrace(stlink, settings.core_frequency_mhz, settings.reset_board)) { + ELOG("Unable to enable trace mode\n"); + return APP_RESULT_STLINK_STATE_ERROR; + } + + if (stlink_run(stlink)) { + ELOG("Unable to run device\n"); + return APP_RESULT_STLINK_STATE_ERROR; + } + + ILOG("Reading.\n"); + + st_trace_state_t state = {}; + while (!g_done) { + if (!ReadTrace(stlink, &state)) + g_done = true; + } + + stlink_trace_disable(stlink); + stlink_close(stlink); + + return APP_RESULT_SUCCESS; } From 3531e34636f75cc094c995416c2a5b09daf67763 Mon Sep 17 00:00:00 2001 From: John Hall Date: Mon, 30 Nov 2020 09:08:59 -0800 Subject: [PATCH 121/503] Code cleanup. --- src/common.c | 1 - src/st-trace/trace.c | 145 ++++++++++++++++++++++++------------------- src/stlink-lib/usb.c | 1 - 3 files changed, 80 insertions(+), 67 deletions(-) diff --git a/src/common.c b/src/common.c index e340ecc71..78cda9318 100644 --- a/src/common.c +++ b/src/common.c @@ -1688,7 +1688,6 @@ int stlink_trace_disable(stlink_t* sl) { } int stlink_trace_read(stlink_t* sl, uint8_t* buf, size_t size) { - DLOG("*** stlink_trace_read ***\n"); return(sl->backend->trace_read(sl, buf, size)); } diff --git a/src/st-trace/trace.c b/src/st-trace/trace.c index bb516ebf0..148876c7a 100644 --- a/src/st-trace/trace.c +++ b/src/st-trace/trace.c @@ -24,6 +24,7 @@ // See https://developer.arm.com/documentation/ddi0403/ed/ #define TRACE_OP_IS_OVERFLOW(c) ((c) == 0x70) +#define TRACE_OP_IS_SYNC(c) ((c) == 0x00) #define TRACE_OP_IS_LOCAL_TIME(c) (((c) & 0x0f) == 0x00 && ((c) & 0x70) != 0x00) #define TRACE_OP_IS_EXTENSION(c) (((c) & 0x0b) == 0x08) #define TRACE_OP_IS_GLOBAL_TIME(c) (((c) & 0xdf) == 0x94) @@ -53,23 +54,23 @@ typedef struct _st_settings_t st_settings_t; // We use a simple state machine to parse the trace data. -enum _trace_step { - TRACE_STEP_IDLE, - TRACE_STEP_TARGET_SOURCE, - TRACE_STEP_SKIP_FRAME, - TRACE_STEP_SKIP_4, - TRACE_STEP_SKIP_3, - TRACE_STEP_SKIP_2, - TRACE_STEP_SKIP_1, +enum _trace_state { + TRACE_STATE_IDLE, + TRACE_STATE_TARGET_SOURCE, + TRACE_STATE_SKIP_FRAME, + TRACE_STATE_SKIP_4, + TRACE_STATE_SKIP_3, + TRACE_STATE_SKIP_2, + TRACE_STATE_SKIP_1, }; -typedef enum _trace_step trace_step; +typedef enum _trace_state trace_state; -struct _st_trace_state_t { - trace_step step; +struct _st_trace_t { + trace_state state; bool overflow; bool error; }; -typedef struct _st_trace_state_t st_trace_state_t; +typedef struct _st_trace_t st_trace_t; static void usage(void) { @@ -242,8 +243,9 @@ static bool EnableTrace(stlink_t* stlink, int core_frequency_mhz, bool reset_boa Write32(stlink, 0xE0040004, 0x00000001); // Set TPIU_CSPSR to enable trace port width of 2 if (core_frequency_mhz) { - uint32_t clock_divisor = core_frequency_mhz / 2 - 1; + uint32_t clock_divisor = core_frequency_mhz * 1000000 / STLINK_TRACE_FREQUENCY - 1; Write32(stlink, 0xE0040010, clock_divisor); // Set TPIU_ACPR clock divisor + } else { } Write32(stlink, 0xE00400F0, 0x00000002); // Set TPIU_SPPR to Asynchronous SWO (NRZ) @@ -259,7 +261,67 @@ static bool EnableTrace(stlink_t* stlink, int core_frequency_mhz, bool reset_boa return true; } -static bool ReadTrace(stlink_t* stlink, st_trace_state_t* state) { +static void UpdateTrace(st_trace_t* trace, uint8_t c) { + // Parse the input using a state machine. + switch (trace->state) + { + case TRACE_STATE_IDLE: + if (TRACE_OP_IS_TARGET_SOURCE(c)) { + trace->state = TRACE_STATE_TARGET_SOURCE; + } else if (TRACE_OP_IS_SOURCE(c)) { + const trace_state kSourceSkip[] = { TRACE_STATE_IDLE, TRACE_STATE_SKIP_1, TRACE_STATE_SKIP_2, TRACE_STATE_SKIP_4 }; + const char* type = TRACE_OP_IS_SW_SOURCE(c) ? "sw" : "hw"; + uint8_t addr = TRACE_OP_GET_SW_SOURCE_ADDR(c); + uint8_t size = TRACE_OP_GET_SOURCE_SIZE(c); + if (TRACE_OP_IS_SW_SOURCE(c)) + WLOG("Unsupported %s source 0x%x size %d\n", type, addr, size); + trace->state = kSourceSkip[size]; + } else if (TRACE_OP_IS_LOCAL_TIME(c) || TRACE_OP_IS_EXTENSION(c) || TRACE_OP_IS_GLOBAL_TIME(c)) { + if (TRACE_OP_GET_CONTINUATION(c)) + trace->state = TRACE_STATE_SKIP_FRAME; + } else if (TRACE_OP_IS_SYNC(c)) { + } else if (TRACE_OP_IS_OVERFLOW(c)) { + trace->overflow = true; + } else { + WLOG("Unknown opcode 0x%02x\n", c); + if (TRACE_OP_GET_CONTINUATION(c)) + trace->state = TRACE_STATE_SKIP_FRAME; + } + break; + + case TRACE_STATE_TARGET_SOURCE: + putchar(c); + trace->state = TRACE_STATE_IDLE; + break; + + case TRACE_STATE_SKIP_FRAME: + if (TRACE_OP_GET_CONTINUATION(c) == 0) + trace->state = TRACE_STATE_IDLE; + break; + + case TRACE_STATE_SKIP_4: + trace->state = TRACE_STATE_SKIP_3; + break; + + case TRACE_STATE_SKIP_3: + trace->state = TRACE_STATE_SKIP_2; + break; + + case TRACE_STATE_SKIP_2: + trace->state = TRACE_STATE_SKIP_1; + break; + + case TRACE_STATE_SKIP_1: + trace->state = TRACE_STATE_IDLE; + break; + + default: + ELOG("Invalid state %d", trace->state); + trace->state = TRACE_STATE_IDLE; + } +} + +static bool ReadTrace(stlink_t* stlink, st_trace_t* trace) { uint8_t buffer[STLINK_TRACE_BUF_LEN]; int length = stlink_trace_read(stlink, buffer, sizeof(buffer)); @@ -274,55 +336,8 @@ static bool ReadTrace(stlink_t* stlink, st_trace_state_t* state) { } DLOG("Trace Length: %d\n", length); - for (int i = 0; i < length; i++) { - uint8_t c = buffer[i]; - - // Parse the input using a state machine. - switch (state->step) - { - case TRACE_STEP_IDLE: - if (TRACE_OP_IS_TARGET_SOURCE(c)) { - state->step = TRACE_STEP_TARGET_SOURCE; - } else if (TRACE_OP_IS_SOURCE(c)) { - const trace_step kSourceSkip[] = { TRACE_STEP_IDLE, TRACE_STEP_SKIP_1, TRACE_STEP_SKIP_2, TRACE_STEP_SKIP_4 }; - const char* type = TRACE_OP_IS_SW_SOURCE(c) ? "sw" : "hw"; - uint8_t addr = TRACE_OP_GET_SW_SOURCE_ADDR(c); - uint8_t size = TRACE_OP_GET_SOURCE_SIZE(c); - WLOG("Unsupported %s source 0x%x size %d", type, addr, size); - state->step = kSourceSkip[size]; - } else if (TRACE_OP_IS_LOCAL_TIME(c) || TRACE_OP_IS_EXTENSION(c) || TRACE_OP_IS_GLOBAL_TIME(c)) { - if (TRACE_OP_GET_CONTINUATION(c)) - state->step = TRACE_STEP_SKIP_FRAME; - } else if (TRACE_OP_IS_OVERFLOW(c)) { - state->overflow = true; - } else { - WLOG("Unknown opcode 0x%02x\n", c); - if (TRACE_OP_GET_CONTINUATION(c)) - state->step = TRACE_STEP_SKIP_FRAME; - } - break; - case TRACE_STEP_TARGET_SOURCE: - putchar(c); - state->step = TRACE_STEP_IDLE; - break; - case TRACE_STEP_SKIP_FRAME: - if (TRACE_OP_GET_CONTINUATION(c) == 0) - state->step = TRACE_STEP_IDLE; - break; - case TRACE_STEP_SKIP_4: - state->step = TRACE_STEP_SKIP_3; - break; - case TRACE_STEP_SKIP_3: - state->step = TRACE_STEP_SKIP_2; - break; - case TRACE_STEP_SKIP_2: - state->step = TRACE_STEP_SKIP_1; - break; - case TRACE_STEP_SKIP_1: - state->step = TRACE_STEP_IDLE; - break; - } + UpdateTrace(trace, buffer[i]); } return true; @@ -376,7 +391,7 @@ int main(int argc, char** argv) if (!IsDeviceTraceSupported(stlink->chip_id)) { const struct stlink_chipid_params *params = stlink_chipid_get_params(stlink->chip_id); - ELOG("We do not support SWO output for device '%s'", params->description); + ELOG("We do not support SWO output for device '%s'\n", params->description); return APP_RESULT_STLINK_UNSUPPORTED_DEVICE; } @@ -392,9 +407,9 @@ int main(int argc, char** argv) ILOG("Reading.\n"); - st_trace_state_t state = {}; + st_trace_t trace = {}; while (!g_done) { - if (!ReadTrace(stlink, &state)) + if (!ReadTrace(stlink, &trace)) g_done = true; } diff --git a/src/stlink-lib/usb.c b/src/stlink-lib/usb.c index 4d8d78a65..db187acc5 100644 --- a/src/stlink-lib/usb.c +++ b/src/stlink-lib/usb.c @@ -1043,7 +1043,6 @@ int _stlink_usb_read_trace(stlink_t* sl, uint8_t* buf, size_t size) { } size_t trace_count = read_uint16(sl->q_buf, 0); - DLOG("trace_count = 0x%08x\n", trace_count); if (trace_count > size) { ELOG("read_trace insufficient buffer length\n"); From 0b3f39fb13ea386105a9a8bb94256fef173073f6 Mon Sep 17 00:00:00 2001 From: John Hall Date: Mon, 30 Nov 2020 10:21:19 -0800 Subject: [PATCH 122/503] Checked that the trace port is configured. Added log messages to share the configuration and to tell the user what to do if it is not configured. --- src/st-trace/trace.c | 23 ++++++++++++++++++++--- 1 file changed, 20 insertions(+), 3 deletions(-) diff --git a/src/st-trace/trace.c b/src/st-trace/trace.c index 148876c7a..aa8fb50c4 100644 --- a/src/st-trace/trace.c +++ b/src/st-trace/trace.c @@ -199,7 +199,16 @@ static bool IsDeviceTraceSupported(int chip_id) { static void Write32(stlink_t* stlink, uint32_t address, uint32_t data) { write_uint32(stlink->q_buf, data); - stlink_write_mem32(stlink, address, 4); + if (stlink_write_mem32(stlink, address, 4)) { + ELOG("Unable to set address 0x%08x to 0x%08x\n", address, data); + } +} + +static uint32_t Read32(stlink_t* stlink, uint32_t address) { + if (stlink_read_mem32(stlink, address, 4)) { + ELOG("Unable to read from address 0x%08x\n", address); + } + return read_uint32(stlink->q_buf, 0); } static bool EnableTrace(stlink_t* stlink, int core_frequency_mhz, bool reset_board) { @@ -243,9 +252,17 @@ static bool EnableTrace(stlink_t* stlink, int core_frequency_mhz, bool reset_boa Write32(stlink, 0xE0040004, 0x00000001); // Set TPIU_CSPSR to enable trace port width of 2 if (core_frequency_mhz) { - uint32_t clock_divisor = core_frequency_mhz * 1000000 / STLINK_TRACE_FREQUENCY - 1; - Write32(stlink, 0xE0040010, clock_divisor); // Set TPIU_ACPR clock divisor + uint32_t prescaler = core_frequency_mhz * 1000000 / STLINK_TRACE_FREQUENCY - 1; + Write32(stlink, 0xE0040010, prescaler); // Set TPIU_ACPR clock divisor + } + uint32_t prescaler = Read32(stlink, 0xE0040010); + if (prescaler) { + uint32_t system_clock_speed = (prescaler + 1) * STLINK_TRACE_FREQUENCY; + ILOG("Trace Port Interface configured to expect a %d MHz system clock.\n", (system_clock_speed + 500000) / 1000000); } else { + WLOG("Trace Port Interface not configured. Specify the system clock with a --clock=XX command\n"); + WLOG("line option or set it in your device's clock initialization routine, such as with:\n"); + WLOG(" TPI->ACPR = HAL_RCC_GetHCLKFreq() / 2000000 - 1;\n"); } Write32(stlink, 0xE00400F0, 0x00000002); // Set TPIU_SPPR to Asynchronous SWO (NRZ) From acbb78d1f4674b5dfd2464c1ed2e5322a27d5370 Mon Sep 17 00:00:00 2001 From: John Hall Date: Mon, 30 Nov 2020 10:51:28 -0800 Subject: [PATCH 123/503] Checking that stlink supports tracing. --- src/common.c | 5 +++++ src/st-trace/trace.c | 28 ++++++++++++++++------------ 2 files changed, 21 insertions(+), 12 deletions(-) diff --git a/src/common.c b/src/common.c index 78cda9318..bda2ccf87 100644 --- a/src/common.c +++ b/src/common.c @@ -1465,6 +1465,10 @@ void _parse_version(stlink_t *sl, stlink_version_t *slv) { if (sl->version.jtag_v >= 15) { sl->version.flags |= STLINK_F_HAS_GETLASTRWSTATUS2; } + + if (sl->version.jtag_v >= 13) { + sl->version.flags |= STLINK_F_HAS_TRACE; + } } } else { // V3 uses different version format, for reference see OpenOCD source @@ -1478,6 +1482,7 @@ void _parse_version(stlink_t *sl, stlink_version_t *slv) { slv->jtag_api = STLINK_JTAG_API_V3; /* preferred API to get last R/W status */ sl->version.flags |= STLINK_F_HAS_GETLASTRWSTATUS2; + sl->version.flags |= STLINK_F_HAS_TRACE; } return; diff --git a/src/st-trace/trace.c b/src/st-trace/trace.c index aa8fb50c4..2646dead5 100644 --- a/src/st-trace/trace.c +++ b/src/st-trace/trace.c @@ -20,9 +20,10 @@ #define APP_RESULT_STLINK_NOT_FOUND 2 #define APP_RESULT_STLINK_MISSING_DEVICE 3 #define APP_RESULT_STLINK_UNSUPPORTED_DEVICE 4 -#define APP_RESULT_STLINK_STATE_ERROR 5 +#define APP_RESULT_STLINK_UNSUPPORTED_LINK 5 +#define APP_RESULT_STLINK_STATE_ERROR 6 -// See https://developer.arm.com/documentation/ddi0403/ed/ +// See D4.2 of https://developer.arm.com/documentation/ddi0403/ed/ #define TRACE_OP_IS_OVERFLOW(c) ((c) == 0x70) #define TRACE_OP_IS_SYNC(c) ((c) == 0x00) #define TRACE_OP_IS_LOCAL_TIME(c) (((c) & 0x0f) == 0x00 && ((c) & 0x70) != 0x00) @@ -32,7 +33,6 @@ #define TRACE_OP_IS_SW_SOURCE(c) (((c) & 0x03) != 0x00 && ((c) & 0x04) == 0x00) #define TRACE_OP_IS_HW_SOURCE(c) (((c) & 0x03) != 0x00 && ((c) & 0x04) == 0x04) #define TRACE_OP_IS_TARGET_SOURCE(c) ((c) == 0x01) - #define TRACE_OP_GET_CONTINUATION(c) ((c) & 0x80) #define TRACE_OP_GET_SOURCE_SIZE(c) ((c) & 0x03) #define TRACE_OP_GET_SW_SOURCE_ADDR(c) ((c) >> 3) @@ -293,7 +293,10 @@ static void UpdateTrace(st_trace_t* trace, uint8_t c) { if (TRACE_OP_IS_SW_SOURCE(c)) WLOG("Unsupported %s source 0x%x size %d\n", type, addr, size); trace->state = kSourceSkip[size]; - } else if (TRACE_OP_IS_LOCAL_TIME(c) || TRACE_OP_IS_EXTENSION(c) || TRACE_OP_IS_GLOBAL_TIME(c)) { + } else if (TRACE_OP_IS_LOCAL_TIME(c) || TRACE_OP_IS_GLOBAL_TIME(c)) { + if (TRACE_OP_GET_CONTINUATION(c)) + trace->state = TRACE_STATE_SKIP_FRAME; + } else if (TRACE_OP_IS_EXTENSION(c)) { if (TRACE_OP_GET_CONTINUATION(c)) trace->state = TRACE_STATE_SKIP_FRAME; } else if (TRACE_OP_IS_SYNC(c)) { @@ -393,18 +396,21 @@ int main(int argc, char** argv) stlink = StLinkConnect(&settings); if (!stlink) { - ELOG("Unable to locate st-link\n"); + ELOG("Unable to locate an stlink\n"); return APP_RESULT_STLINK_NOT_FOUND; } stlink->verbose = settings.logging_level; if (stlink->chip_id == STLINK_CHIPID_UNKNOWN) { - ELOG("st-link not connected\n"); + ELOG("Your stlink is not connected to a device\n"); return APP_RESULT_STLINK_MISSING_DEVICE; } - // TODO: Check if trace is supported by stlink. + if (!(stlink->version.flags & STLINK_F_HAS_TRACE)) { + ELOG("Your stlink does not support tracing\n"); + return APP_RESULT_STLINK_UNSUPPORTED_LINK; + } if (!IsDeviceTraceSupported(stlink->chip_id)) { const struct stlink_chipid_params *params = stlink_chipid_get_params(stlink->chip_id); @@ -422,12 +428,10 @@ int main(int argc, char** argv) return APP_RESULT_STLINK_STATE_ERROR; } - ILOG("Reading.\n"); - + ILOG("Reading Trace\n"); st_trace_t trace = {}; - while (!g_done) { - if (!ReadTrace(stlink, &trace)) - g_done = true; + while (!g_done && ReadTrace(stlink, &trace)) { + // TODO: Check that things are roughly working. } stlink_trace_disable(stlink); From 722224e5f282dd0ee727fbf7787d7ccd745f3a01 Mon Sep 17 00:00:00 2001 From: John Hall Date: Mon, 30 Nov 2020 11:10:59 -0800 Subject: [PATCH 124/503] Adding a force flag to ignore errors. --- src/st-trace/trace.c | 61 +++++++++++++++++++++++++++++++------------- 1 file changed, 43 insertions(+), 18 deletions(-) diff --git a/src/st-trace/trace.c b/src/st-trace/trace.c index 2646dead5..ef34d62e0 100644 --- a/src/st-trace/trace.c +++ b/src/st-trace/trace.c @@ -48,6 +48,7 @@ struct _st_settings_t { int logging_level; int core_frequency_mhz; bool reset_board; + bool force; char* serial_number; }; typedef struct _st_settings_t st_settings_t; @@ -82,6 +83,7 @@ static void usage(void) { puts(" -cXX, --clock=XX Specify the core frequency in MHz"); puts(" -n, --no-reset Do not reset board on connection"); puts(" -sXX, --serial=XX Use a specific serial number"); + puts(" -f, --force Ignore some errors"); } static void cleanup() { @@ -97,20 +99,23 @@ bool parse_options(int argc, char** argv, st_settings_t *settings) { {"clock", required_argument, NULL, 'c'}, {"no-reset", no_argument, NULL, 'n'}, {"serial", required_argument, NULL, 's'}, + {"force", no_argument, NULL, 'f'}, {0, 0, 0, 0}, }; int option_index = 0; int c; + bool error = false; settings->show_help = false; settings->show_version = false; settings->logging_level = DEFAULT_LOGGING_LEVEL; settings->core_frequency_mhz = 0; settings->reset_board = true; + settings->force = false; settings->serial_number = NULL; ugly_init(settings->logging_level); - while ((c = getopt_long(argc, argv, "hVv::c:ns:", long_options, &option_index)) != -1) { + while ((c = getopt_long(argc, argv, "hVv::c:ns:f", long_options, &option_index)) != -1) { switch (c) { case 'h': settings->show_help = true; @@ -132,15 +137,19 @@ bool parse_options(int argc, char** argv, st_settings_t *settings) { case 'n': settings->reset_board = false; break; + case 'f': + settings->force = true; + break; case 's': settings->serial_number = optarg; break; case '?': - return false; + error = true; break; default: ELOG("Unknown command line option: '%c' (0x%02x)\n", c, c); - return false; + error = true; + break; } } @@ -148,9 +157,12 @@ bool parse_options(int argc, char** argv, st_settings_t *settings) { while (optind < argc) { ELOG("Unknown command line argument: '%s'\n", argv[optind++]); } - return false; + error = true; } + if (error && !settings->force) + return false; + return true; } @@ -211,15 +223,19 @@ static uint32_t Read32(stlink_t* stlink, uint32_t address) { return read_uint32(stlink->q_buf, 0); } -static bool EnableTrace(stlink_t* stlink, int core_frequency_mhz, bool reset_board) { +static bool EnableTrace(stlink_t* stlink, const st_settings_t* settings) { struct stlink_reg regp = {}; if (stlink_force_debug(stlink)) { - return false; + ELOG("Unable to debug device\n"); + if (!settings->force) + return false; } - if (reset_board && stlink_reset(stlink)) { - return false; + if (settings->reset_board && stlink_reset(stlink)) { + ELOG("Unable to reset device\n"); + if (!settings->force) + return false; } // The order and values to set were taken from https://github.com/avrhack/stlink-trace/blob/master/stlink-trace.c#L386 @@ -246,13 +262,15 @@ static bool EnableTrace(stlink_t* stlink, int core_frequency_mhz, bool reset_boa // Actually start tracing. if (stlink_trace_enable(stlink)) { - return false; + ELOG("Unable to trace device\n"); + if (!settings->force) + return false; } Write32(stlink, 0xE0040004, 0x00000001); // Set TPIU_CSPSR to enable trace port width of 2 - if (core_frequency_mhz) { - uint32_t prescaler = core_frequency_mhz * 1000000 / STLINK_TRACE_FREQUENCY - 1; + if (settings->core_frequency_mhz) { + uint32_t prescaler = settings->core_frequency_mhz * 1000000 / STLINK_TRACE_FREQUENCY - 1; Write32(stlink, 0xE0040010, prescaler); // Set TPIU_ACPR clock divisor } uint32_t prescaler = Read32(stlink, 0xE0040010); @@ -304,6 +322,7 @@ static void UpdateTrace(st_trace_t* trace, uint8_t c) { trace->overflow = true; } else { WLOG("Unknown opcode 0x%02x\n", c); + trace->error = true; if (TRACE_OP_GET_CONTINUATION(c)) trace->state = TRACE_STATE_SKIP_FRAME; } @@ -336,7 +355,7 @@ static void UpdateTrace(st_trace_t* trace, uint8_t c) { break; default: - ELOG("Invalid state %d", trace->state); + ELOG("Invalid state %d. This should never happen\n", trace->state); trace->state = TRACE_STATE_IDLE; } } @@ -382,6 +401,7 @@ int main(int argc, char** argv) DLOG("logging_level = %d\n", settings.logging_level); DLOG("core_frequency = %d MHz\n", settings.core_frequency_mhz); DLOG("reset_board = %s\n", settings.reset_board ? "true" : "false"); + DLOG("force = %s\n", settings.force ? "true" : "false"); DLOG("serial_number = %s\n", settings.serial_number ? settings.serial_number : "any"); if (settings.show_help) { @@ -404,28 +424,33 @@ int main(int argc, char** argv) if (stlink->chip_id == STLINK_CHIPID_UNKNOWN) { ELOG("Your stlink is not connected to a device\n"); - return APP_RESULT_STLINK_MISSING_DEVICE; + if (!settings.force) + return APP_RESULT_STLINK_MISSING_DEVICE; } if (!(stlink->version.flags & STLINK_F_HAS_TRACE)) { ELOG("Your stlink does not support tracing\n"); - return APP_RESULT_STLINK_UNSUPPORTED_LINK; + if (!settings.force) + return APP_RESULT_STLINK_UNSUPPORTED_LINK; } if (!IsDeviceTraceSupported(stlink->chip_id)) { const struct stlink_chipid_params *params = stlink_chipid_get_params(stlink->chip_id); ELOG("We do not support SWO output for device '%s'\n", params->description); - return APP_RESULT_STLINK_UNSUPPORTED_DEVICE; + if (!settings.force) + return APP_RESULT_STLINK_UNSUPPORTED_DEVICE; } - if (!EnableTrace(stlink, settings.core_frequency_mhz, settings.reset_board)) { + if (!EnableTrace(stlink, &settings)) { ELOG("Unable to enable trace mode\n"); - return APP_RESULT_STLINK_STATE_ERROR; + if (!settings.force) + return APP_RESULT_STLINK_STATE_ERROR; } if (stlink_run(stlink)) { ELOG("Unable to run device\n"); - return APP_RESULT_STLINK_STATE_ERROR; + if (!settings.force) + return APP_RESULT_STLINK_STATE_ERROR; } ILOG("Reading Trace\n"); From 3188fb48d1cbd745f437c3bd55af3a8599c0484f Mon Sep 17 00:00:00 2001 From: John Hall Date: Mon, 30 Nov 2020 19:39:43 -0800 Subject: [PATCH 125/503] Updating to use register names to make code more readable. --- inc/stlink.h | 3 ++ src/st-trace/trace.c | 124 ++++++++++++++++++++++++++++++------------- 2 files changed, 89 insertions(+), 38 deletions(-) diff --git a/inc/stlink.h b/inc/stlink.h index e7aefbded..1c9f6b09a 100644 --- a/inc/stlink.h +++ b/inc/stlink.h @@ -105,6 +105,9 @@ enum target_state { #define S_RETIRE_ST (1 << 24) #define S_RESET_ST (1 << 25) +/* DCB_DEMCR field definitions */ +#define DEMCR_TRCENA (1 << 24) + /* Map the relevant features, quirks and workaround for specific firmware version of stlink */ #define STLINK_F_HAS_TRACE (1 << 0) #define STLINK_F_HAS_SWD_SET_FREQ (1 << 1) diff --git a/src/st-trace/trace.c b/src/st-trace/trace.c index ef34d62e0..877bd4e35 100644 --- a/src/st-trace/trace.c +++ b/src/st-trace/trace.c @@ -38,6 +38,64 @@ #define TRACE_OP_GET_SW_SOURCE_ADDR(c) ((c) >> 3) +// Instrumentation Trace Macrocell (ITM) Registers +#define ITM_TER 0xE0000E00 // ITM Trace Enable Register +#define ITM_TPR 0xE0000E40 // ITM Trace Privilege Register +#define ITM_TCR 0xE0000E80 // ITM Trace Control Register +#define ITM_TCC 0xE0000E90 // ITM Trace Cycle Count +#define ITM_LAR 0xE0000FB0 // ITM Lock Access Register + +// ITM field definitions +#define ITM_TER_PORTS_ALL (0xFFFFFFFF) +#define ITM_TPR_PORTS_ALL (0x0F) +#define ITM_TCR_TRACE_BUS_ID_1 (0x01 << 16) +#define ITM_TCR_SWO_ENA (1 << 4) +#define ITM_TCR_DWT_ENA (1 << 3) +#define ITM_TCR_SYNC_ENA (1 << 2) +#define ITM_TCR_TS_ENA (1 << 1) +#define ITM_TCR_ITM_ENA (1 << 0) +#define ITM_LAR_KEY 0xC5ACCE55 + +// Data Watchpoint and Trace (DWT) Registers +#define DWT_CTRL 0xE0001000 // DWT Control Register +#define DWT_FUNCTION0 0xE0001028 // DWT Function Register 0 +#define DWT_FUNCTION1 0xE0001038 // DWT Function Register 1 +#define DWT_FUNCTION2 0xE0001048 // DWT Function Register 2 +#define DWT_FUNCTION3 0xE0001058 // DWT Function Register 3 + +// DWT field definitions +#define DWT_CTRL_NUM_COMP (1 << 28) +#define DWT_CTRL_CYC_TAP (1 << 9) +#define DWT_CTRL_POST_INIT (1 << 5) +#define DWT_CTRL_POST_PRESET (1 << 1) +#define DWT_CTRL_CYCCNT_ENA (1 << 0) + +// Trace Port Interface (TPI) Registers +#define TPI_CSPSR 0xE0040004 // TPI Current Parallel Port Size Register +#define TPI_ACPR 0xE0040010 // TPI Asynchronous Clock Prescaler Register +#define TPI_SPPR 0xE00400F0 // TPI Selected Pin Protocol Register +#define TPI_FFCR 0xE0040304 // TPI Formatter and Flush Control Register + +// TPI field definitions +#define TPI_TPI_CSPSR_PORT_SIZE_1 (0x01 << 0) +#define TPI_SPPR_SWO_MANCHESTER (0x01 << 0) +#define TPI_SPPR_SWO_NRZ (0x02 << 0) +#define TPI_FFCR_EN_F_CONT (0x01 << 1) +#define TPI_FFCR_F_ON_MAN (0x01 << 6) +#define TPI_FFCR_TRIG_IN (0x01 << 8) + +// Other Registers +#define FP_CTRL 0xE0002000 // Flash Patch Control Register [WHY DO WE NEED THIS?] +#define DBGMCU_CR 0xE0042004 // Debug MCU Configuration Register + +// Other register field definitions +#define FP_CTRL_KEY (1 << 1) +#define DBGMCU_CR_DBG_SLEEP (1 << 0) +#define DBGMCU_CR_DBG_STOP (1 << 1) +#define DBGMCU_CR_DBG_STANDBY (1 << 2) +#define DBGMCU_CR_TRACE_IOEN (1 << 5) +#define DBGMCU_CR_TRACE_MODE_ASYNC (0x00 << 6) + // We use a global flag to allow communicating to the main thread from the signal handler. static bool g_done = false; @@ -185,8 +243,8 @@ static stlink_t* StLinkConnect(const st_settings_t* settings) { } } -// TODO: Consider moving this to the device table. static bool IsDeviceTraceSupported(int chip_id) { + // TODO: Consider moving this to a flag in the device table. switch (chip_id) { case STLINK_CHIPID_STM32_F4: case STLINK_CHIPID_STM32_F4_DSI: @@ -224,7 +282,6 @@ static uint32_t Read32(stlink_t* stlink, uint32_t address) { } static bool EnableTrace(stlink_t* stlink, const st_settings_t* settings) { - struct stlink_reg regp = {}; if (stlink_force_debug(stlink)) { ELOG("Unable to debug device\n"); @@ -238,42 +295,31 @@ static bool EnableTrace(stlink_t* stlink, const st_settings_t* settings) { return false; } - // The order and values to set were taken from https://github.com/avrhack/stlink-trace/blob/master/stlink-trace.c#L386 - - Write32(stlink, 0xE000EDF0, 0xA05F0003); // Set DHCSR to C_HALT and C_DEBUGEN - Write32(stlink, 0xE000EDFC, 0x01000000); // Set TRCENA flag to enable global DWT and ITM - Write32(stlink, 0xE0002000, 0x00000002); // Set FP_CTRL to enable write - Write32(stlink, 0xE0001028, 0x00000000); // Set DWT_FUNCTION0 to DWT_FUNCTION3 to disable sampling - Write32(stlink, 0xE0001038, 0x00000000); - Write32(stlink, 0xE0001048, 0x00000000); - Write32(stlink, 0xE0001058, 0x00000000); - Write32(stlink, 0xE0001000, 0x00000000); // Clear DWT_CTRL and other registers - Write32(stlink, 0xE0001004, 0x00000000); - Write32(stlink, 0xE0001008, 0x00000000); - Write32(stlink, 0xE000100C, 0x00000000); - Write32(stlink, 0xE0001010, 0x00000000); - Write32(stlink, 0xE0001014, 0x00000000); - Write32(stlink, 0xE0001018, 0x00000000); - - stlink_read_reg(stlink, 15, ®p); // Read program counter - stlink_read_reg(stlink, 16, ®p); // Read xpsr register - - Write32(stlink, 0xE0042004, 0x00000027); // Set DBGMCU_CR to enable asynchronous transmission - - // Actually start tracing. + Write32(stlink, DCB_DHCSR, DBGKEY | C_DEBUGEN | C_HALT); // Debug and halt the CPU + Write32(stlink, DCB_DEMCR, DEMCR_TRCENA); // Enable tracing + Write32(stlink, FP_CTRL, FP_CTRL_KEY); // Disable flash patch unit. + Write32(stlink, DWT_FUNCTION0, 0); // Disable sampling units + Write32(stlink, DWT_FUNCTION1, 0); + Write32(stlink, DWT_FUNCTION2, 0); + Write32(stlink, DWT_FUNCTION3, 0); + Write32(stlink, DWT_CTRL, 0); // Disable other watchpoint and trace features + Write32(stlink, DBGMCU_CR, DBGMCU_CR_DBG_SLEEP | DBGMCU_CR_DBG_STOP | + DBGMCU_CR_DBG_STANDBY | DBGMCU_CR_TRACE_IOEN | + DBGMCU_CR_TRACE_MODE_ASYNC); // Enable async tracing + if (stlink_trace_enable(stlink)) { - ELOG("Unable to trace device\n"); + ELOG("Unable to turn on tracing in stlink\n"); if (!settings->force) return false; } - Write32(stlink, 0xE0040004, 0x00000001); // Set TPIU_CSPSR to enable trace port width of 2 + Write32(stlink, TPI_CSPSR, TPI_TPI_CSPSR_PORT_SIZE_1); if (settings->core_frequency_mhz) { uint32_t prescaler = settings->core_frequency_mhz * 1000000 / STLINK_TRACE_FREQUENCY - 1; - Write32(stlink, 0xE0040010, prescaler); // Set TPIU_ACPR clock divisor + Write32(stlink, TPI_ACPR, prescaler); // Set TPIU_ACPR clock divisor } - uint32_t prescaler = Read32(stlink, 0xE0040010); + uint32_t prescaler = Read32(stlink, TPI_ACPR); if (prescaler) { uint32_t system_clock_speed = (prescaler + 1) * STLINK_TRACE_FREQUENCY; ILOG("Trace Port Interface configured to expect a %d MHz system clock.\n", (system_clock_speed + 500000) / 1000000); @@ -283,15 +329,17 @@ static bool EnableTrace(stlink_t* stlink, const st_settings_t* settings) { WLOG(" TPI->ACPR = HAL_RCC_GetHCLKFreq() / 2000000 - 1;\n"); } - Write32(stlink, 0xE00400F0, 0x00000002); // Set TPIU_SPPR to Asynchronous SWO (NRZ) - Write32(stlink, 0xE0040304, 0x00000100); // Set TPIU_FFCR continuous formatting) - Write32(stlink, 0xE0000FB0, 0xC5ACCE55); // Unlock the ITM registers for write - Write32(stlink, 0xE0000E90, 0x00000400); // Set sync counter - Write32(stlink, 0xE0000E80, 0x00010003); // Set ITM_TCR flags : ITMENA,TSENA ATB=0 - Write32(stlink, 0xE0000E00, 0xFFFFFFFF); // Enable all trace ports in ITM_TER - Write32(stlink, 0xE0000E40, 0x0000000F); // Enable unprivileged access to trace ports 31:0 in ITM_TPR - Write32(stlink, 0xE0000E40, 0x400003FE); // Set DWT_CTRL flags) - Write32(stlink, 0xE000EDFC, 0x01000000); // Enable tracing (DEMCR - TRCENA bit) + Write32(stlink, TPI_FFCR, TPI_FFCR_TRIG_IN | TPI_FFCR_EN_F_CONT); + Write32(stlink, TPI_SPPR, TPI_SPPR_SWO_NRZ); + Write32(stlink, ITM_LAR, ITM_LAR_KEY); // Unlocks the following registers. + Write32(stlink, ITM_TCC, 0x00000400); // Set sync counter + Write32(stlink, ITM_TCR, ITM_TCR_TRACE_BUS_ID_1 | ITM_TCR_TS_ENA | ITM_TCR_ITM_ENA); + Write32(stlink, ITM_TER, ITM_TER_PORTS_ALL); + Write32(stlink, ITM_TPR, ITM_TPR_PORTS_ALL); + Write32(stlink, DWT_CTRL, 4 * DWT_CTRL_NUM_COMP | DWT_CTRL_CYC_TAP | + 0xF * DWT_CTRL_POST_INIT | 0xF * DWT_CTRL_POST_PRESET | + DWT_CTRL_CYCCNT_ENA); + Write32(stlink, DCB_DEMCR, DEMCR_TRCENA); // Enable tracing (again...?) return true; } From 074f061b667a2bdae8eeb26d786f88ac2920fb94 Mon Sep 17 00:00:00 2001 From: John Hall Date: Mon, 30 Nov 2020 19:43:36 -0800 Subject: [PATCH 126/503] Verified sleep timer is about right. --- src/st-trace/trace.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/st-trace/trace.c b/src/st-trace/trace.c index 877bd4e35..5cafc85ec 100644 --- a/src/st-trace/trace.c +++ b/src/st-trace/trace.c @@ -141,7 +141,7 @@ static void usage(void) { puts(" -cXX, --clock=XX Specify the core frequency in MHz"); puts(" -n, --no-reset Do not reset board on connection"); puts(" -sXX, --serial=XX Use a specific serial number"); - puts(" -f, --force Ignore some errors"); + puts(" -f, --force Ignore most initialization errors"); } static void cleanup() { @@ -418,7 +418,7 @@ static bool ReadTrace(stlink_t* stlink, st_trace_t* trace) { } if (length == 0) { - usleep(1000); + usleep(1000); // Our buffer could fill in around 2ms, so sleep half that. return true; } From f51f06535eb9979456eb553a1c7724f96116e7ba Mon Sep 17 00:00:00 2001 From: John Hall Date: Mon, 30 Nov 2020 21:00:29 -0800 Subject: [PATCH 127/503] Added a check that looks at connection results after 10 seconds and displays a diagnositic message if it looks like we are not configured correctly. --- src/st-trace/trace.c | 99 ++++++++++++++++++++++++++++++++------------ 1 file changed, 73 insertions(+), 26 deletions(-) diff --git a/src/st-trace/trace.c b/src/st-trace/trace.c index 5cafc85ec..b2837dbbe 100644 --- a/src/st-trace/trace.c +++ b/src/st-trace/trace.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include @@ -25,7 +26,6 @@ // See D4.2 of https://developer.arm.com/documentation/ddi0403/ed/ #define TRACE_OP_IS_OVERFLOW(c) ((c) == 0x70) -#define TRACE_OP_IS_SYNC(c) ((c) == 0x00) #define TRACE_OP_IS_LOCAL_TIME(c) (((c) & 0x0f) == 0x00 && ((c) & 0x70) != 0x00) #define TRACE_OP_IS_EXTENSION(c) (((c) & 0x0b) == 0x08) #define TRACE_OP_IS_GLOBAL_TIME(c) (((c) & 0xdf) == 0x94) @@ -100,7 +100,7 @@ static bool g_done = false; -struct _st_settings_t { +typedef struct { bool show_help; bool show_version; int logging_level; @@ -108,12 +108,11 @@ struct _st_settings_t { bool reset_board; bool force; char* serial_number; -}; -typedef struct _st_settings_t st_settings_t; +} st_settings_t; // We use a simple state machine to parse the trace data. -enum _trace_state { +typedef enum { TRACE_STATE_IDLE, TRACE_STATE_TARGET_SOURCE, TRACE_STATE_SKIP_FRAME, @@ -121,15 +120,22 @@ enum _trace_state { TRACE_STATE_SKIP_3, TRACE_STATE_SKIP_2, TRACE_STATE_SKIP_1, -}; -typedef enum _trace_state trace_state; +} trace_state; + +typedef struct { + time_t start_time; + bool configuration_checked; -struct _st_trace_t { trace_state state; - bool overflow; - bool error; -}; -typedef struct _st_trace_t st_trace_t; + + uint32_t count_raw_bytes; + uint32_t count_target_data; + uint32_t count_time_packets; + uint32_t count_overflow; + uint32_t count_error; + + uint8_t unknown_opcodes[256 / 8]; +} st_trace_t; static void usage(void) { @@ -295,14 +301,14 @@ static bool EnableTrace(stlink_t* stlink, const st_settings_t* settings) { return false; } - Write32(stlink, DCB_DHCSR, DBGKEY | C_DEBUGEN | C_HALT); // Debug and halt the CPU - Write32(stlink, DCB_DEMCR, DEMCR_TRCENA); // Enable tracing - Write32(stlink, FP_CTRL, FP_CTRL_KEY); // Disable flash patch unit. - Write32(stlink, DWT_FUNCTION0, 0); // Disable sampling units + Write32(stlink, DCB_DHCSR, DBGKEY | C_DEBUGEN | C_HALT); + Write32(stlink, DCB_DEMCR, DEMCR_TRCENA); + Write32(stlink, FP_CTRL, FP_CTRL_KEY); + Write32(stlink, DWT_FUNCTION0, 0); Write32(stlink, DWT_FUNCTION1, 0); Write32(stlink, DWT_FUNCTION2, 0); Write32(stlink, DWT_FUNCTION3, 0); - Write32(stlink, DWT_CTRL, 0); // Disable other watchpoint and trace features + Write32(stlink, DWT_CTRL, 0); Write32(stlink, DBGMCU_CR, DBGMCU_CR_DBG_SLEEP | DBGMCU_CR_DBG_STOP | DBGMCU_CR_DBG_STANDBY | DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_ASYNC); // Enable async tracing @@ -322,7 +328,8 @@ static bool EnableTrace(stlink_t* stlink, const st_settings_t* settings) { uint32_t prescaler = Read32(stlink, TPI_ACPR); if (prescaler) { uint32_t system_clock_speed = (prescaler + 1) * STLINK_TRACE_FREQUENCY; - ILOG("Trace Port Interface configured to expect a %d MHz system clock.\n", (system_clock_speed + 500000) / 1000000); + uint32_t system_clock_speed_mhz = (system_clock_speed + 500000) / 1000000; + ILOG("Trace Port Interface configured to expect a %d MHz system clock.\n", system_clock_speed_mhz); } else { WLOG("Trace Port Interface not configured. Specify the system clock with a --clock=XX command\n"); WLOG("line option or set it in your device's clock initialization routine, such as with:\n"); @@ -331,7 +338,7 @@ static bool EnableTrace(stlink_t* stlink, const st_settings_t* settings) { Write32(stlink, TPI_FFCR, TPI_FFCR_TRIG_IN | TPI_FFCR_EN_F_CONT); Write32(stlink, TPI_SPPR, TPI_SPPR_SWO_NRZ); - Write32(stlink, ITM_LAR, ITM_LAR_KEY); // Unlocks the following registers. + Write32(stlink, ITM_LAR, ITM_LAR_KEY); Write32(stlink, ITM_TCC, 0x00000400); // Set sync counter Write32(stlink, ITM_TCR, ITM_TCR_TRACE_BUS_ID_1 | ITM_TCR_TS_ENA | ITM_TCR_ITM_ENA); Write32(stlink, ITM_TER, ITM_TER_PORTS_ALL); @@ -339,13 +346,14 @@ static bool EnableTrace(stlink_t* stlink, const st_settings_t* settings) { Write32(stlink, DWT_CTRL, 4 * DWT_CTRL_NUM_COMP | DWT_CTRL_CYC_TAP | 0xF * DWT_CTRL_POST_INIT | 0xF * DWT_CTRL_POST_PRESET | DWT_CTRL_CYCCNT_ENA); - Write32(stlink, DCB_DEMCR, DEMCR_TRCENA); // Enable tracing (again...?) + Write32(stlink, DCB_DEMCR, DEMCR_TRCENA); return true; } static void UpdateTrace(st_trace_t* trace, uint8_t c) { // Parse the input using a state machine. + trace->count_raw_bytes++; switch (trace->state) { case TRACE_STATE_IDLE: @@ -360,17 +368,19 @@ static void UpdateTrace(st_trace_t* trace, uint8_t c) { WLOG("Unsupported %s source 0x%x size %d\n", type, addr, size); trace->state = kSourceSkip[size]; } else if (TRACE_OP_IS_LOCAL_TIME(c) || TRACE_OP_IS_GLOBAL_TIME(c)) { + trace->count_time_packets++; if (TRACE_OP_GET_CONTINUATION(c)) trace->state = TRACE_STATE_SKIP_FRAME; } else if (TRACE_OP_IS_EXTENSION(c)) { if (TRACE_OP_GET_CONTINUATION(c)) trace->state = TRACE_STATE_SKIP_FRAME; - } else if (TRACE_OP_IS_SYNC(c)) { } else if (TRACE_OP_IS_OVERFLOW(c)) { - trace->overflow = true; + trace->count_overflow++; } else { - WLOG("Unknown opcode 0x%02x\n", c); - trace->error = true; + if (!(trace->unknown_opcodes[c / 8] & (1 << c % 8))) + WLOG("Unknown opcode 0x%02x\n", c); + trace->unknown_opcodes[c / 8] |= (1 << c % 8); + trace->count_error++; if (TRACE_OP_GET_CONTINUATION(c)) trace->state = TRACE_STATE_SKIP_FRAME; } @@ -378,6 +388,7 @@ static void UpdateTrace(st_trace_t* trace, uint8_t c) { case TRACE_STATE_TARGET_SOURCE: putchar(c); + trace->count_target_data++; trace->state = TRACE_STATE_IDLE; break; @@ -422,7 +433,6 @@ static bool ReadTrace(stlink_t* stlink, st_trace_t* trace) { return true; } - DLOG("Trace Length: %d\n", length); for (int i = 0; i < length; i++) { UpdateTrace(trace, buffer[i]); } @@ -430,6 +440,42 @@ static bool ReadTrace(stlink_t* stlink, st_trace_t* trace) { return true; } +static void CheckForConfigurationError(stlink_t* stlink, st_trace_t* trace) { + uint32_t elapsed_time_s = time(NULL) - trace->start_time; + if (trace->configuration_checked || elapsed_time_s < 10) { + return; + } + trace->configuration_checked = true; + + // Simple huristic to determine if we are configured poorly. + if (trace->count_raw_bytes < 100 || trace->count_error > 1 || trace->count_time_packets < 10) { + // Output Diagnostic Information + WLOG("****\n"); + WLOG("We do not appear to be retrieving data from the stlink correctly.\n"); + WLOG("Raw Bytes: %d\n", trace->count_raw_bytes); + WLOG("Target Data: %d\n", trace->count_target_data); + WLOG("Time Packets: %d\n", trace->count_time_packets); + WLOG("Overlow Count: %d\n", trace->count_overflow); + WLOG("Errors: %d\n", trace->count_error); + for (uint32_t i = 0; i <= 0xFF; i++) + if (trace->unknown_opcodes[i / 8] & (1 << i % 8)) + WLOG("Unknown Opcode 0x%02x\n", i); + uint32_t prescaler = Read32(stlink, TPI_ACPR); + if (prescaler) { + uint32_t system_clock_speed = (prescaler + 1) * STLINK_TRACE_FREQUENCY; + uint32_t system_clock_speed_mhz = (system_clock_speed + 500000) / 1000000; + WLOG("Trace Port Interface configured to expect a %d MHz system clock.\n", system_clock_speed_mhz); + } else { + WLOG("Trace Port Interface not configured. Specify the system clock with a --clock=XX command\n"); + WLOG("line option or set it in your device's clock initialization routine, such as with:\n"); + WLOG(" TPI->ACPR = HAL_RCC_GetHCLKFreq() / 2000000 - 1;\n"); + } + // TODO: Include clock configuration information here. + // TODO: Include TRACE/DEBUG register values here. + WLOG("****\n"); + } +} + int main(int argc, char** argv) { st_settings_t settings; @@ -503,8 +549,9 @@ int main(int argc, char** argv) ILOG("Reading Trace\n"); st_trace_t trace = {}; + trace.start_time = time(NULL); while (!g_done && ReadTrace(stlink, &trace)) { - // TODO: Check that things are roughly working. + CheckForConfigurationError(stlink, &trace); } stlink_trace_disable(stlink); From b8c459fd4bff00ef8bc7718d7b80cb3d706f15ba Mon Sep 17 00:00:00 2001 From: John Hall Date: Mon, 30 Nov 2020 21:27:29 -0800 Subject: [PATCH 128/503] Avoiding duplicating logs for unknown sources. --- src/st-trace/trace.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/src/st-trace/trace.c b/src/st-trace/trace.c index b2837dbbe..70e80b49b 100644 --- a/src/st-trace/trace.c +++ b/src/st-trace/trace.c @@ -135,6 +135,7 @@ typedef struct { uint32_t count_error; uint8_t unknown_opcodes[256 / 8]; + uint32_t unknown_sources; } st_trace_t; @@ -364,8 +365,11 @@ static void UpdateTrace(st_trace_t* trace, uint8_t c) { const char* type = TRACE_OP_IS_SW_SOURCE(c) ? "sw" : "hw"; uint8_t addr = TRACE_OP_GET_SW_SOURCE_ADDR(c); uint8_t size = TRACE_OP_GET_SOURCE_SIZE(c); - if (TRACE_OP_IS_SW_SOURCE(c)) - WLOG("Unsupported %s source 0x%x size %d\n", type, addr, size); + if (TRACE_OP_IS_SW_SOURCE(c)) { + if (!(trace->unknown_sources & (1 << addr))) + WLOG("Unsupported %s source 0x%x size %d\n", type, addr, size); + trace->unknown_sources |= (1 << addr); + } trace->state = kSourceSkip[size]; } else if (TRACE_OP_IS_LOCAL_TIME(c) || TRACE_OP_IS_GLOBAL_TIME(c)) { trace->count_time_packets++; @@ -460,6 +464,9 @@ static void CheckForConfigurationError(stlink_t* stlink, st_trace_t* trace) { for (uint32_t i = 0; i <= 0xFF; i++) if (trace->unknown_opcodes[i / 8] & (1 << i % 8)) WLOG("Unknown Opcode 0x%02x\n", i); + for (uint32_t i = 0; i < 32; i++) + if (trace->unknown_sources & (1 << i)) + WLOG("Unknown Source %d\n", i); uint32_t prescaler = Read32(stlink, TPI_ACPR); if (prescaler) { uint32_t system_clock_speed = (prescaler + 1) * STLINK_TRACE_FREQUENCY; From 7ceb09dc65a3aee96d84287fc7d4a8fa35a02fe4 Mon Sep 17 00:00:00 2001 From: John Hall Date: Mon, 30 Nov 2020 21:44:26 -0800 Subject: [PATCH 129/503] Avoiding reading register from check method as this seems to halt the process. --- src/st-trace/trace.c | 20 ++++++-------------- 1 file changed, 6 insertions(+), 14 deletions(-) diff --git a/src/st-trace/trace.c b/src/st-trace/trace.c index 70e80b49b..2ff90c8d9 100644 --- a/src/st-trace/trace.c +++ b/src/st-trace/trace.c @@ -444,7 +444,7 @@ static bool ReadTrace(stlink_t* stlink, st_trace_t* trace) { return true; } -static void CheckForConfigurationError(stlink_t* stlink, st_trace_t* trace) { +static void CheckForConfigurationError(st_trace_t* trace) { uint32_t elapsed_time_s = time(NULL) - trace->start_time; if (trace->configuration_checked || elapsed_time_s < 10) { return; @@ -467,18 +467,9 @@ static void CheckForConfigurationError(stlink_t* stlink, st_trace_t* trace) { for (uint32_t i = 0; i < 32; i++) if (trace->unknown_sources & (1 << i)) WLOG("Unknown Source %d\n", i); - uint32_t prescaler = Read32(stlink, TPI_ACPR); - if (prescaler) { - uint32_t system_clock_speed = (prescaler + 1) * STLINK_TRACE_FREQUENCY; - uint32_t system_clock_speed_mhz = (system_clock_speed + 500000) / 1000000; - WLOG("Trace Port Interface configured to expect a %d MHz system clock.\n", system_clock_speed_mhz); - } else { - WLOG("Trace Port Interface not configured. Specify the system clock with a --clock=XX command\n"); - WLOG("line option or set it in your device's clock initialization routine, such as with:\n"); - WLOG(" TPI->ACPR = HAL_RCC_GetHCLKFreq() / 2000000 - 1;\n"); - } - // TODO: Include clock configuration information here. - // TODO: Include TRACE/DEBUG register values here. + WLOG("Check that the clock frequency is set correctly. Either with the --clock=XX\n"); + WLOG("command line option, or by adding the following to your device's clock initialization:\n"); + WLOG(" TPI->ACPR = HAL_RCC_GetHCLKFreq() / 2000000 - 1;\n"); WLOG("****\n"); } } @@ -491,6 +482,7 @@ int main(int argc, char** argv) signal(SIGINT, &cleanup); signal(SIGTERM, &cleanup); signal(SIGSEGV, &cleanup); + signal(SIGPIPE, &cleanup); if (!parse_options(argc, argv, &settings)) { usage(); @@ -558,7 +550,7 @@ int main(int argc, char** argv) st_trace_t trace = {}; trace.start_time = time(NULL); while (!g_done && ReadTrace(stlink, &trace)) { - CheckForConfigurationError(stlink, &trace); + CheckForConfigurationError(&trace); } stlink_trace_disable(stlink); From 2e4c81e2a3552cc7a5db1657b5794507d4b68403 Mon Sep 17 00:00:00 2001 From: John Hall Date: Mon, 30 Nov 2020 22:30:54 -0800 Subject: [PATCH 130/503] Was using continouous triggering wrong. --- src/st-trace/trace.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/src/st-trace/trace.c b/src/st-trace/trace.c index 2ff90c8d9..b4c509063 100644 --- a/src/st-trace/trace.c +++ b/src/st-trace/trace.c @@ -80,8 +80,6 @@ #define TPI_TPI_CSPSR_PORT_SIZE_1 (0x01 << 0) #define TPI_SPPR_SWO_MANCHESTER (0x01 << 0) #define TPI_SPPR_SWO_NRZ (0x02 << 0) -#define TPI_FFCR_EN_F_CONT (0x01 << 1) -#define TPI_FFCR_F_ON_MAN (0x01 << 6) #define TPI_FFCR_TRIG_IN (0x01 << 8) // Other Registers @@ -337,7 +335,7 @@ static bool EnableTrace(stlink_t* stlink, const st_settings_t* settings) { WLOG(" TPI->ACPR = HAL_RCC_GetHCLKFreq() / 2000000 - 1;\n"); } - Write32(stlink, TPI_FFCR, TPI_FFCR_TRIG_IN | TPI_FFCR_EN_F_CONT); + Write32(stlink, TPI_FFCR, TPI_FFCR_TRIG_IN); Write32(stlink, TPI_SPPR, TPI_SPPR_SWO_NRZ); Write32(stlink, ITM_LAR, ITM_LAR_KEY); Write32(stlink, ITM_TCC, 0x00000400); // Set sync counter From b88b19287b41e98ece35072ffa94e45a47b13fec Mon Sep 17 00:00:00 2001 From: John Hall Date: Mon, 30 Nov 2020 22:41:47 -0800 Subject: [PATCH 131/503] Flushing stdout after every newline. This is needed for things to run correctly in some scripts. --- src/st-trace/trace.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/st-trace/trace.c b/src/st-trace/trace.c index b4c509063..a50bef4ef 100644 --- a/src/st-trace/trace.c +++ b/src/st-trace/trace.c @@ -390,6 +390,8 @@ static void UpdateTrace(st_trace_t* trace, uint8_t c) { case TRACE_STATE_TARGET_SOURCE: putchar(c); + if (c == '\n') + fflush(stdout); trace->count_target_data++; trace->state = TRACE_STATE_IDLE; break; From c2356fabac30a0daac176dd0f472d48e7a74ac77 Mon Sep 17 00:00:00 2001 From: John Hall Date: Tue, 1 Dec 2020 09:22:07 -0800 Subject: [PATCH 132/503] Cleaning up code before code review. --- src/st-trace/trace.c | 138 ++++++++++++++++++++++--------------------- 1 file changed, 71 insertions(+), 67 deletions(-) diff --git a/src/st-trace/trace.c b/src/st-trace/trace.c index a50bef4ef..08775c226 100644 --- a/src/st-trace/trace.c +++ b/src/st-trace/trace.c @@ -38,6 +38,8 @@ #define TRACE_OP_GET_SW_SOURCE_ADDR(c) ((c) >> 3) +// TODO: Ideally all register and field definitions would be in a common header file. + // Instrumentation Trace Macrocell (ITM) Registers #define ITM_TER 0xE0000E00 // ITM Trace Enable Register #define ITM_TPR 0xE0000E40 // ITM Trace Privilege Register @@ -83,7 +85,7 @@ #define TPI_FFCR_TRIG_IN (0x01 << 8) // Other Registers -#define FP_CTRL 0xE0002000 // Flash Patch Control Register [WHY DO WE NEED THIS?] +#define FP_CTRL 0xE0002000 // Flash Patch Control Register #define DBGMCU_CR 0xE0042004 // Debug MCU Configuration Register // Other register field definitions @@ -94,8 +96,9 @@ #define DBGMCU_CR_TRACE_IOEN (1 << 5) #define DBGMCU_CR_TRACE_MODE_ASYNC (0x00 << 6) + // We use a global flag to allow communicating to the main thread from the signal handler. -static bool g_done = false; +static bool g_abort_trace = false; typedef struct { @@ -149,8 +152,8 @@ static void usage(void) { puts(" -f, --force Ignore most initialization errors"); } -static void cleanup() { - g_done = true; +static void abort_trace() { + g_abort_trace = true; } bool parse_options(int argc, char** argv, st_settings_t *settings) { @@ -229,19 +232,21 @@ bool parse_options(int argc, char** argv, st_settings_t *settings) { return true; } +static void ConvertSerialNumberTextToBinary(const char* text, char binary_out[STLINK_SERIAL_MAX_SIZE]) { + size_t length = 0; + for (uint32_t n = 0; n < strlen(text) && length < STLINK_SERIAL_MAX_SIZE; n += 2) { + char buffer[3] = { 0 }; + memcpy(buffer, text + n, 2); + binary_out[length++] = (uint8_t)strtol(buffer, NULL, 16); + } +} + static stlink_t* StLinkConnect(const st_settings_t* settings) { if (settings->serial_number) { - // Convert our serial number string to a binary value. - char serial_number[STLINK_SERIAL_MAX_SIZE] = { 0 }; - size_t length = 0; - for (uint32_t n = 0; n < strlen(settings->serial_number) && length < STLINK_SERIAL_MAX_SIZE; n += 2) { - char buffer[3] = { 0 }; - memcpy(buffer, settings->serial_number + n, 2); - serial_number[length++] = (uint8_t)strtol(buffer, NULL, 16); - } - // Open this specific stlink. - return stlink_open_usb(settings->logging_level, false, serial_number, 0); + char binary_serial_number[STLINK_SERIAL_MAX_SIZE] = { 0 }; + ConvertSerialNumberTextToBinary(settings->serial_number, binary_serial_number); + return stlink_open_usb(settings->logging_level, false, binary_serial_number, 0); } else { // Otherwise, open any stlink. return stlink_open_usb(settings->logging_level, false, NULL, 0); @@ -350,76 +355,75 @@ static bool EnableTrace(stlink_t* stlink, const st_settings_t* settings) { return true; } -static void UpdateTrace(st_trace_t* trace, uint8_t c) { - // Parse the input using a state machine. +static trace_state UpdateTraceIdle(st_trace_t* trace, uint8_t c) { + if (TRACE_OP_IS_TARGET_SOURCE(c)) { + return TRACE_STATE_TARGET_SOURCE; + } + if (TRACE_OP_IS_SOURCE(c)) { + uint8_t size = TRACE_OP_GET_SOURCE_SIZE(c); + if (TRACE_OP_IS_SW_SOURCE(c)) { + uint8_t addr = TRACE_OP_GET_SW_SOURCE_ADDR(c); + if (!(trace->unknown_sources & (1 << addr))) + WLOG("Unsupported source 0x%x size %d\n", addr, size); + trace->unknown_sources |= (1 << addr); + } + if (size == 1) return TRACE_STATE_SKIP_1; + if (size == 2) return TRACE_STATE_SKIP_2; + if (size == 3) return TRACE_STATE_SKIP_4; + } + if (TRACE_OP_IS_LOCAL_TIME(c) || TRACE_OP_IS_GLOBAL_TIME(c)) { + trace->count_time_packets++; + return TRACE_OP_GET_CONTINUATION(c) ? TRACE_STATE_SKIP_FRAME : TRACE_STATE_IDLE; + } + if (TRACE_OP_IS_EXTENSION(c)) { + return TRACE_OP_GET_CONTINUATION(c) ? TRACE_STATE_SKIP_FRAME : TRACE_STATE_IDLE; + } + if (TRACE_OP_IS_OVERFLOW(c)) { + trace->count_overflow++; + } + + if (!(trace->unknown_opcodes[c / 8] & (1 << c % 8))) + WLOG("Unknown opcode 0x%02x\n", c); + trace->unknown_opcodes[c / 8] |= (1 << c % 8); + + trace->count_error++; + return TRACE_OP_GET_CONTINUATION(c) ? TRACE_STATE_SKIP_FRAME : TRACE_STATE_IDLE; +} + +static trace_state UpdateTrace(st_trace_t* trace, uint8_t c) { trace->count_raw_bytes++; + + // Parse the input using a state machine. switch (trace->state) { case TRACE_STATE_IDLE: - if (TRACE_OP_IS_TARGET_SOURCE(c)) { - trace->state = TRACE_STATE_TARGET_SOURCE; - } else if (TRACE_OP_IS_SOURCE(c)) { - const trace_state kSourceSkip[] = { TRACE_STATE_IDLE, TRACE_STATE_SKIP_1, TRACE_STATE_SKIP_2, TRACE_STATE_SKIP_4 }; - const char* type = TRACE_OP_IS_SW_SOURCE(c) ? "sw" : "hw"; - uint8_t addr = TRACE_OP_GET_SW_SOURCE_ADDR(c); - uint8_t size = TRACE_OP_GET_SOURCE_SIZE(c); - if (TRACE_OP_IS_SW_SOURCE(c)) { - if (!(trace->unknown_sources & (1 << addr))) - WLOG("Unsupported %s source 0x%x size %d\n", type, addr, size); - trace->unknown_sources |= (1 << addr); - } - trace->state = kSourceSkip[size]; - } else if (TRACE_OP_IS_LOCAL_TIME(c) || TRACE_OP_IS_GLOBAL_TIME(c)) { - trace->count_time_packets++; - if (TRACE_OP_GET_CONTINUATION(c)) - trace->state = TRACE_STATE_SKIP_FRAME; - } else if (TRACE_OP_IS_EXTENSION(c)) { - if (TRACE_OP_GET_CONTINUATION(c)) - trace->state = TRACE_STATE_SKIP_FRAME; - } else if (TRACE_OP_IS_OVERFLOW(c)) { - trace->count_overflow++; - } else { - if (!(trace->unknown_opcodes[c / 8] & (1 << c % 8))) - WLOG("Unknown opcode 0x%02x\n", c); - trace->unknown_opcodes[c / 8] |= (1 << c % 8); - trace->count_error++; - if (TRACE_OP_GET_CONTINUATION(c)) - trace->state = TRACE_STATE_SKIP_FRAME; - } - break; + return UpdateTraceIdle(trace, c); case TRACE_STATE_TARGET_SOURCE: putchar(c); if (c == '\n') fflush(stdout); trace->count_target_data++; - trace->state = TRACE_STATE_IDLE; - break; + return TRACE_STATE_IDLE; case TRACE_STATE_SKIP_FRAME: - if (TRACE_OP_GET_CONTINUATION(c) == 0) - trace->state = TRACE_STATE_IDLE; - break; + return TRACE_OP_GET_CONTINUATION(c) ? TRACE_STATE_SKIP_FRAME : TRACE_STATE_IDLE; case TRACE_STATE_SKIP_4: - trace->state = TRACE_STATE_SKIP_3; - break; + return TRACE_STATE_SKIP_3; case TRACE_STATE_SKIP_3: - trace->state = TRACE_STATE_SKIP_2; - break; + return TRACE_STATE_SKIP_2; case TRACE_STATE_SKIP_2: - trace->state = TRACE_STATE_SKIP_1; - break; + return TRACE_STATE_SKIP_1; case TRACE_STATE_SKIP_1: - trace->state = TRACE_STATE_IDLE; - break; + return TRACE_STATE_IDLE; default: ELOG("Invalid state %d. This should never happen\n", trace->state); - trace->state = TRACE_STATE_IDLE; + return TRACE_STATE_IDLE; } } @@ -438,7 +442,7 @@ static bool ReadTrace(stlink_t* stlink, st_trace_t* trace) { } for (int i = 0; i < length; i++) { - UpdateTrace(trace, buffer[i]); + trace->state = UpdateTrace(trace, buffer[i]); } return true; @@ -479,10 +483,10 @@ int main(int argc, char** argv) st_settings_t settings; stlink_t* stlink = NULL; - signal(SIGINT, &cleanup); - signal(SIGTERM, &cleanup); - signal(SIGSEGV, &cleanup); - signal(SIGPIPE, &cleanup); + signal(SIGINT, &abort_trace); + signal(SIGTERM, &abort_trace); + signal(SIGSEGV, &abort_trace); + signal(SIGPIPE, &abort_trace); if (!parse_options(argc, argv, &settings)) { usage(); @@ -549,7 +553,7 @@ int main(int argc, char** argv) ILOG("Reading Trace\n"); st_trace_t trace = {}; trace.start_time = time(NULL); - while (!g_done && ReadTrace(stlink, &trace)) { + while (!g_abort_trace && ReadTrace(stlink, &trace)) { CheckForConfigurationError(&trace); } From 793088f4389acf6a3883a3667d7e5fb9cb9a3d76 Mon Sep 17 00:00:00 2001 From: John Hall Date: Tue, 1 Dec 2020 10:25:55 -0800 Subject: [PATCH 133/503] Updating to use chip flags instead of multiple boolean values. --- inc/stlink.h | 2 +- src/common.c | 4 ++-- src/stlink-lib/chipid.c | 2 +- src/stlink-lib/chipid.h | 5 ++++- 4 files changed, 8 insertions(+), 5 deletions(-) diff --git a/inc/stlink.h b/inc/stlink.h index 1c9f6b09a..c369a133a 100644 --- a/inc/stlink.h +++ b/inc/stlink.h @@ -217,7 +217,7 @@ struct _stlink { enum stlink_flash_type flash_type; // stlink_chipid_params.flash_type, set by stlink_load_device_params(), values: STLINK_FLASH_TYPE_xxx - bool has_dual_bank; + uint32_t chip_flags; stm32_addr_t flash_base; // STM32_FLASH_BASE, set by stlink_load_device_params() size_t flash_size; // calculated by stlink_load_device_params() diff --git a/src/common.c b/src/common.c index bda2ccf87..0325c85f9 100644 --- a/src/common.c +++ b/src/common.c @@ -868,7 +868,7 @@ static void set_flash_cr_mer(stlink_t *sl, bool v) { cr_reg = STM32Gx_FLASH_CR; cr_mer = (1 << STM32Gx_FLASH_CR_MER1); - if (sl->has_dual_bank) { + if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { cr_mer |= (1 << STM32Gx_FLASH_CR_MER2); } @@ -1363,7 +1363,7 @@ int stlink_load_device_params(stlink_t *sl) { } sl->flash_type = params->flash_type; - sl->has_dual_bank = params->has_dual_bank; + sl->chip_flags = params->flags; sl->flash_pgsz = params->flash_pagesize; sl->sram_size = params->sram_size; sl->sys_base = params->bootrom_base; diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index a8d160445..ca35c887e 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -593,7 +593,7 @@ static const struct stlink_chipid_params devices[] = { .chip_id = STLINK_CHIPID_STM32_G4_CAT3, .description = "G4 Category-3", .flash_type = STLINK_FLASH_TYPE_G4, - .has_dual_bank = true, + .flags = CHIP_F_HAS_DUAL_BANK, .flash_size_reg = 0x1FFF75E0, // Section 47.2 .flash_pagesize = 0x800, // 2k (sec 3.3.1) // SRAM1 is 80k at 0x20000000 diff --git a/src/stlink-lib/chipid.h b/src/stlink-lib/chipid.h index f717022ca..1573b182e 100644 --- a/src/stlink-lib/chipid.h +++ b/src/stlink-lib/chipid.h @@ -67,12 +67,15 @@ enum stlink_stm32_chipids { STLINK_CHIPID_STM32_WB55 = 0x495 }; +#define CHIP_F_HAS_DUAL_BANK (1 << 0) +#define CHIP_F_HAS_SWO_TRACING (1 << 1) + /** Chipid parameters */ struct stlink_chipid_params { uint32_t chip_id; char *description; enum stlink_flash_type flash_type; - bool has_dual_bank; + uint32_t flags; uint32_t flash_size_reg; uint32_t flash_pagesize; uint32_t sram_size; From 660dee303cd1d1dcab8bea5684d31a99dacb414c Mon Sep 17 00:00:00 2001 From: John Hall Date: Tue, 1 Dec 2020 10:41:40 -0800 Subject: [PATCH 134/503] Moved chip trace support into chipid where it belongs. --- src/st-trace/trace.c | 26 +--------- src/stlink-lib/chipid.c | 104 +++++++++++++++++++++++++++------------- 2 files changed, 73 insertions(+), 57 deletions(-) diff --git a/src/st-trace/trace.c b/src/st-trace/trace.c index 08775c226..b8a9f88cb 100644 --- a/src/st-trace/trace.c +++ b/src/st-trace/trace.c @@ -253,30 +253,6 @@ static stlink_t* StLinkConnect(const st_settings_t* settings) { } } -static bool IsDeviceTraceSupported(int chip_id) { - // TODO: Consider moving this to a flag in the device table. - switch (chip_id) { - case STLINK_CHIPID_STM32_F4: - case STLINK_CHIPID_STM32_F4_DSI: - case STLINK_CHIPID_STM32_F4_HD: - case STLINK_CHIPID_STM32_F4_LP: - case STLINK_CHIPID_STM32_F411RE: - case STLINK_CHIPID_STM32_F4_DE: - case STLINK_CHIPID_STM32_F446: - case STLINK_CHIPID_STM32_F410: - case STLINK_CHIPID_STM32_F3: - case STLINK_CHIPID_STM32_F37x: - case STLINK_CHIPID_STM32_F412: - case STLINK_CHIPID_STM32_F413: - case STLINK_CHIPID_STM32_F3_SMALL: - case STLINK_CHIPID_STM32_F334: - case STLINK_CHIPID_STM32_F303_HIGH: - return true; - default: - return false; - } -} - static void Write32(stlink_t* stlink, uint32_t address, uint32_t data) { write_uint32(stlink->q_buf, data); if (stlink_write_mem32(stlink, address, 4)) { @@ -531,7 +507,7 @@ int main(int argc, char** argv) return APP_RESULT_STLINK_UNSUPPORTED_LINK; } - if (!IsDeviceTraceSupported(stlink->chip_id)) { + if (!(stlink->chip_flags & CHIP_F_HAS_SWO_TRACING)) { const struct stlink_chipid_params *params = stlink_chipid_get_params(stlink->chip_id); ELOG("We do not support SWO output for device '%s'\n", params->description); if (!settings.force) diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index ca35c887e..d136384f9 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -13,7 +13,8 @@ static const struct stlink_chipid_params devices[] = { .bootrom_base = 0x00200000, // ! "System memory" starting address from .bootrom_size = 0xEDC0, // ! @todo "System memory" byte size in hex from .option_base = STM32_F7_OPTION_BYTES_BASE, // Used for reading back the option bytes, writing uses FLASH_F7_OPTCR and FLASH_F7_OPTCR1 - .option_size = 0x20 + .option_size = 0x20, + .flags = CHIP_F_HAS_SWO_TRACING, }, { // RM0385 and DS10916 document was used to find these paramaters @@ -24,7 +25,8 @@ static const struct stlink_chipid_params devices[] = { .flash_pagesize = 0x800, // No flash pages .sram_size = 0x50000, // "SRAM" byte size in hex from DS Fig 18 .bootrom_base = 0x00100000, // "System memory" starting address from DS Fig 18 - .bootrom_size = 0xEDC0 // "System memory" byte size in hex from DS Fig 18 + .bootrom_size = 0xEDC0, // "System memory" byte size in hex from DS Fig 18 + .flags = CHIP_F_HAS_SWO_TRACING, }, { // RM0431 and DS document was used to find these paramaters @@ -35,7 +37,8 @@ static const struct stlink_chipid_params devices[] = { .flash_pagesize = 0x800, // No flash pages .sram_size = 0x40000, // "SRAM" byte size in hex from DS Fig 24 .bootrom_base = 0x00100000, // "System memory" starting address from DS Fig 24 - .bootrom_size = 0xEDC0 // "System memory" byte size in hex from DS Fig 24 + .bootrom_size = 0xEDC0, // "System memory" byte size in hex from DS Fig 24 + .flags = CHIP_F_HAS_SWO_TRACING, }, { // table 2, PM0063 .chip_id = STLINK_CHIPID_STM32_F1_MEDIUM, @@ -45,7 +48,8 @@ static const struct stlink_chipid_params devices[] = { .flash_pagesize = 0x400, .sram_size = 0x5000, .bootrom_base = 0x1ffff000, - .bootrom_size = 0x800 + .bootrom_size = 0x800, + .flags = CHIP_F_HAS_SWO_TRACING, }, { // table 1, PM0059 .chip_id = STLINK_CHIPID_STM32_F2, @@ -58,6 +62,7 @@ static const struct stlink_chipid_params devices[] = { .bootrom_size = 0x7800, .option_base = 0x1FFFC000, .option_size = 4, + .flags = CHIP_F_HAS_SWO_TRACING, }, { // PM0063 .chip_id = STLINK_CHIPID_STM32_F1_LOW, @@ -67,7 +72,8 @@ static const struct stlink_chipid_params devices[] = { .flash_pagesize = 0x400, .sram_size = 0x2800, .bootrom_base = 0x1ffff000, - .bootrom_size = 0x800 + .bootrom_size = 0x800, + .flags = CHIP_F_HAS_SWO_TRACING, }, { .chip_id = STLINK_CHIPID_STM32_F4, @@ -80,6 +86,7 @@ static const struct stlink_chipid_params devices[] = { .bootrom_size = 0x7800, .option_base = STM32_F4_OPTION_BYTES_BASE, .option_size = 4, + .flags = CHIP_F_HAS_SWO_TRACING, }, { .chip_id = STLINK_CHIPID_STM32_F4_DSI, @@ -89,7 +96,8 @@ static const struct stlink_chipid_params devices[] = { .flash_pagesize = 0x4000, .sram_size = 0x40000, .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7800 + .bootrom_size = 0x7800, + .flags = CHIP_F_HAS_SWO_TRACING, }, { .chip_id = STLINK_CHIPID_STM32_F4_HD, @@ -99,7 +107,8 @@ static const struct stlink_chipid_params devices[] = { .flash_pagesize = 0x4000, .sram_size = 0x40000, .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7800 + .bootrom_size = 0x7800, + .flags = CHIP_F_HAS_SWO_TRACING, }, { .chip_id = STLINK_CHIPID_STM32_F4_LP, @@ -109,7 +118,8 @@ static const struct stlink_chipid_params devices[] = { .flash_pagesize = 0x4000, .sram_size = 0x10000, .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7800 + .bootrom_size = 0x7800, + .flags = CHIP_F_HAS_SWO_TRACING, }, { .chip_id = STLINK_CHIPID_STM32_F411RE, @@ -119,7 +129,8 @@ static const struct stlink_chipid_params devices[] = { .flash_pagesize = 0x4000, .sram_size = 0x20000, .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7800 + .bootrom_size = 0x7800, + .flags = CHIP_F_HAS_SWO_TRACING, }, { .chip_id = STLINK_CHIPID_STM32_F4_DE, @@ -129,7 +140,8 @@ static const struct stlink_chipid_params devices[] = { .flash_pagesize = 0x4000, .sram_size = 0x18000, .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7800 + .bootrom_size = 0x7800, + .flags = CHIP_F_HAS_SWO_TRACING, }, { .chip_id = STLINK_CHIPID_STM32_F1_HIGH, @@ -139,7 +151,8 @@ static const struct stlink_chipid_params devices[] = { .flash_pagesize = 0x800, .sram_size = 0x10000, .bootrom_base = 0x1ffff000, - .bootrom_size = 0x800 + .bootrom_size = 0x800, + .flags = CHIP_F_HAS_SWO_TRACING, }, { // This ignores the EEPROM! (and uses the page erase size, @@ -151,7 +164,8 @@ static const struct stlink_chipid_params devices[] = { .flash_pagesize = 0x100, .sram_size = 0x4000, .bootrom_base = 0x1ff00000, - .bootrom_size = 0x1000 + .bootrom_size = 0x1000, + .flags = CHIP_F_HAS_SWO_TRACING, }, { .chip_id = STLINK_CHIPID_STM32_L1_CAT2, @@ -161,7 +175,8 @@ static const struct stlink_chipid_params devices[] = { .flash_pagesize = 0x100, .sram_size = 0x8000, .bootrom_base = 0x1ff00000, - .bootrom_size = 0x1000 + .bootrom_size = 0x1000, + .flags = CHIP_F_HAS_SWO_TRACING, }, { .chip_id = STLINK_CHIPID_STM32_L1_MEDIUM_PLUS, @@ -171,7 +186,8 @@ static const struct stlink_chipid_params devices[] = { .flash_pagesize = 0x100, .sram_size = 0x8000, // not completely clear if there are some with 48k .bootrom_base = 0x1ff00000, - .bootrom_size = 0x1000 + .bootrom_size = 0x1000, + .flags = CHIP_F_HAS_SWO_TRACING, }, { .chip_id = STLINK_CHIPID_STM32_L1_HIGH, @@ -184,6 +200,7 @@ static const struct stlink_chipid_params devices[] = { .bootrom_size = 0x1000, .option_base = STM32_L1_OPTION_BYTES_BASE, .option_size = 8, + .flags = CHIP_F_HAS_SWO_TRACING, }, { .chip_id = STLINK_CHIPID_STM32_L152_RE, @@ -193,7 +210,8 @@ static const struct stlink_chipid_params devices[] = { .flash_pagesize = 0x100, .sram_size = 0x14000, // not completely clear if there are some with 32k .bootrom_base = 0x1ff00000, - .bootrom_size = 0x1000 + .bootrom_size = 0x1000, + .flags = CHIP_F_HAS_SWO_TRACING, }, { .chip_id = STLINK_CHIPID_STM32_F1_CONN, @@ -203,7 +221,8 @@ static const struct stlink_chipid_params devices[] = { .flash_pagesize = 0x800, .sram_size = 0x10000, .bootrom_base = 0x1fffb000, - .bootrom_size = 0x4800 + .bootrom_size = 0x4800, + .flags = CHIP_F_HAS_SWO_TRACING, }, { // Low and Medium density VL have same chipid. RM0041 25.6.1 .chip_id = STLINK_CHIPID_STM32_F1_VL_MEDIUM_LOW, @@ -213,7 +232,8 @@ static const struct stlink_chipid_params devices[] = { .flash_pagesize = 0x400, .sram_size = 0x2000, // 0x1000 for low density devices .bootrom_base = 0x1ffff000, - .bootrom_size = 0x800 + .bootrom_size = 0x800, + .flags = CHIP_F_HAS_SWO_TRACING, }, { // STM32F446x family. Support based on DM00135183.pdf (RM0390) document. @@ -227,6 +247,7 @@ static const struct stlink_chipid_params devices[] = { .bootrom_size = 0x7800, .option_base = 0x1FFFC000, .option_size = 4, + .flags = CHIP_F_HAS_SWO_TRACING, }, { // STM32F410 MCUs. Support based on DM00180366.pdf (RM0401) document. @@ -237,7 +258,8 @@ static const struct stlink_chipid_params devices[] = { .flash_pagesize = 0x4000, .sram_size = 0x8000, .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7800 + .bootrom_size = 0x7800, + .flags = CHIP_F_HAS_SWO_TRACING, }, { // This is STK32F303VCT6 device from STM32 F3 Discovery board. @@ -249,7 +271,8 @@ static const struct stlink_chipid_params devices[] = { .flash_pagesize = 0x800, .sram_size = 0xa000, .bootrom_base = 0x1ffff000, - .bootrom_size = 0x800 + .bootrom_size = 0x800, + .flags = CHIP_F_HAS_SWO_TRACING, }, { // This is STK32F373VCT6 device from STM32 F373 eval board @@ -261,7 +284,8 @@ static const struct stlink_chipid_params devices[] = { .flash_pagesize = 0x800, .sram_size = 0xa000, .bootrom_base = 0x1ffff000, - .bootrom_size = 0x800 + .bootrom_size = 0x800, + .flags = CHIP_F_HAS_SWO_TRACING, }, { .chip_id = STLINK_CHIPID_STM32_F1_VL_HIGH, @@ -271,7 +295,8 @@ static const struct stlink_chipid_params devices[] = { .flash_pagesize = 0x800, .sram_size = 0x8000, .bootrom_base = 0x1ffff000, - .bootrom_size = 0x800 + .bootrom_size = 0x800, + .flags = CHIP_F_HAS_SWO_TRACING, }, { .chip_id = STLINK_CHIPID_STM32_F1_XL, @@ -281,7 +306,8 @@ static const struct stlink_chipid_params devices[] = { .flash_pagesize = 0x800, .sram_size = 0x18000, .bootrom_base = 0x1fffe000, - .bootrom_size = 0x1800 + .bootrom_size = 0x1800, + .flags = CHIP_F_HAS_SWO_TRACING, }, { // Use this as an example for mapping future chips: @@ -317,7 +343,8 @@ static const struct stlink_chipid_params devices[] = { .flash_pagesize = 0x4000, // Table 5. Flash module organization ? .sram_size = 0x40000, // "SRAM" byte size in hex from Table 4 .bootrom_base = 0x1FFF0000, // "System memory" starting address from Table 4 - .bootrom_size = 0x7800 // "System memory" byte size in hex from Table 4 + .bootrom_size = 0x7800, // "System memory" byte size in hex from Table 4 + .flags = CHIP_F_HAS_SWO_TRACING, }, { // RM0430 DocID029473 Rev 2 document was used to find these parameters @@ -329,7 +356,8 @@ static const struct stlink_chipid_params devices[] = { .flash_pagesize = 0x4000, // Table 5. Flash module organization (variable sector sizes, but 0x4000 is smallest) .sram_size = 0x50000, // "SRAM" byte size in hex from Figure 2 (Table 4 only says 0x40000) .bootrom_base = 0x1FFF0000, // "System memory" starting address from Table 4 - .bootrom_size = 0x7800 // "System memory" byte size in hex from Table 4 + .bootrom_size = 0x7800, // "System memory" byte size in hex from Table 4 + .flags = CHIP_F_HAS_SWO_TRACING, }, { .chip_id = STLINK_CHIPID_STM32_F09X, @@ -374,7 +402,8 @@ static const struct stlink_chipid_params devices[] = { .flash_pagesize = 0x800, .sram_size = 0xa000, .bootrom_base = 0x1fffd800, - .bootrom_size = 0x2000 + .bootrom_size = 0x2000, + .flags = CHIP_F_HAS_SWO_TRACING, }, { // STM32L0x @@ -428,7 +457,8 @@ static const struct stlink_chipid_params devices[] = { .flash_pagesize = 0x800, .sram_size = 0x3000, .bootrom_base = 0x1fffd800, - .bootrom_size = 0x2000 + .bootrom_size = 0x2000, + .flags = CHIP_F_HAS_SWO_TRACING, }, { // This is STK32F303RET6 device from STM32 F3 Nucelo board. @@ -440,7 +470,8 @@ static const struct stlink_chipid_params devices[] = { .flash_pagesize = 0x800, // 4.2.1 Flash memory organization .sram_size = 0x10000, // 3.3 Embedded SRAM .bootrom_base = 0x1fffd800, // 3.3.2 / Table 4 System Memory - .bootrom_size = 0x2000 + .bootrom_size = 0x2000, + .flags = CHIP_F_HAS_SWO_TRACING, }, { // STM32L4x6 @@ -459,6 +490,7 @@ static const struct stlink_chipid_params devices[] = { .bootrom_size = 0x7000, // 28k (per bank), same source as base .option_base = STM32_L4_OPTION_BYTES_BASE, .option_size = 4, + .flags = CHIP_F_HAS_SWO_TRACING, }, { // STM32L4RX @@ -470,7 +502,8 @@ static const struct stlink_chipid_params devices[] = { .flash_pagesize = 0x1000, // 4k, section 3.3, pg 97 .sram_size = 0xa0000, // 192k (SRAM1) + 64k SRAM2 + 384k SRAM3 = 640k, or 0xA0000 .bootrom_base = 0x1fff0000, // 3.3.1, pg 99 - .bootrom_size = 0x7000 // 28k (per bank), same source as base (pg 99) + .bootrom_size = 0x7000, // 28k (per bank), same source as base (pg 99) + .flags = CHIP_F_HAS_SWO_TRACING, }, { // STLINK_CHIPID_STM32_L41X @@ -484,7 +517,8 @@ static const struct stlink_chipid_params devices[] = { // SRAM2 is 8k at 0x10000000 and 0x20008000 (DS12469, sec 3.5, page 18) .sram_size = 0xa000, // 40k (DS12469, sec 3.5, page 18) .bootrom_base = 0x1fff0000, // System Memory (RM0394, sec 3.3.1, table 8) - .bootrom_size = 0x7000 // 28k, same source as base + .bootrom_size = 0x7000, // 28k, same source as base + .flags = CHIP_F_HAS_SWO_TRACING, }, { // STLINK_CHIPID_STM32_L43X @@ -503,6 +537,7 @@ static const struct stlink_chipid_params devices[] = { .bootrom_size = 0x7000, // 28k (per bank), same source as base .option_base = STM32_L4_OPTION_BYTES_BASE, .option_size = 4, + .flags = CHIP_F_HAS_SWO_TRACING, }, { // STLINK_CHIPID_STM32_L496X @@ -519,6 +554,7 @@ static const struct stlink_chipid_params devices[] = { .bootrom_size = 0x7000, // 28k (per bank), same source as base .option_base = STM32_L4_OPTION_BYTES_BASE, .option_size = 4, + .flags = CHIP_F_HAS_SWO_TRACING, }, { // STLINK_CHIPID_STM32_L46X @@ -533,7 +569,8 @@ static const struct stlink_chipid_params devices[] = { // SRAM2 is 32k mapped at 0x10000000 (sec 2.4.2, table 3-4, page 68, also fig 2 on page 63) .sram_size = 0x20000, .bootrom_base = 0x1fff0000, // Tables 6, pages 71-72 (Bank 1 system memory, also fig 2 on page 63) - .bootrom_size = 0x7000 // 28k (per bank), same source as base + .bootrom_size = 0x7000, // 28k (per bank), same source as base + .flags = CHIP_F_HAS_SWO_TRACING, }, { // STM32L011 @@ -587,13 +624,13 @@ static const struct stlink_chipid_params devices[] = { .bootrom_size = 0x7000, // 28k (table 2) .option_base = STM32_G4_OPTION_BYTES_BASE, .option_size = 4, + .flags = CHIP_F_HAS_SWO_TRACING, }, { // STM32G471/473/474/483/484 (from RM0440) .chip_id = STLINK_CHIPID_STM32_G4_CAT3, .description = "G4 Category-3", .flash_type = STLINK_FLASH_TYPE_G4, - .flags = CHIP_F_HAS_DUAL_BANK, .flash_size_reg = 0x1FFF75E0, // Section 47.2 .flash_pagesize = 0x800, // 2k (sec 3.3.1) // SRAM1 is 80k at 0x20000000 @@ -604,6 +641,7 @@ static const struct stlink_chipid_params devices[] = { .bootrom_size = 0x7000, // 28k (table 2) .option_base = STM32_G4_OPTION_BYTES_BASE, .option_size = 4, + .flags = CHIP_F_HAS_DUAL_BANK | CHIP_F_HAS_SWO_TRACING, }, { // STM32WB55 (from RM0434) @@ -628,6 +666,7 @@ static const struct stlink_chipid_params devices[] = { .bootrom_size = 0x20000, // "System memory" byte size in hex from Table 7 .option_base = STM32_H7_OPTION_BYTES_BASE, .option_size = 44, // FLASH_OPTSR_CUR to FLASH_BOOT_PRGR from Table 28 + .flags = CHIP_F_HAS_SWO_TRACING, }, { // unknown @@ -638,7 +677,8 @@ static const struct stlink_chipid_params devices[] = { .flash_pagesize = 0x0, .sram_size = 0x0, .bootrom_base = 0x0, - .bootrom_size = 0x0 + .bootrom_size = 0x0, + .flags = 0, }, }; From ce7f0a157c1b66216c03977bd1e55291033b1d97 Mon Sep 17 00:00:00 2001 From: John Hall Date: Tue, 1 Dec 2020 10:56:40 -0800 Subject: [PATCH 135/503] One last cleanup before I feel this code is ready to submit for CR. --- src/st-trace/trace.c | 21 +++++++++++++-------- 1 file changed, 13 insertions(+), 8 deletions(-) diff --git a/src/st-trace/trace.c b/src/st-trace/trace.c index b8a9f88cb..379c4cec1 100644 --- a/src/st-trace/trace.c +++ b/src/st-trace/trace.c @@ -97,10 +97,6 @@ #define DBGMCU_CR_TRACE_MODE_ASYNC (0x00 << 6) -// We use a global flag to allow communicating to the main thread from the signal handler. -static bool g_abort_trace = false; - - typedef struct { bool show_help; bool show_version; @@ -140,6 +136,13 @@ typedef struct { } st_trace_t; +// We use a global flag to allow communicating to the main thread from the signal handler. +static bool g_abort_trace = false; + +static void abort_trace() { + g_abort_trace = true; +} + static void usage(void) { puts("st-trace - usage:"); puts(" -h, --help Print this help"); @@ -152,10 +155,6 @@ static void usage(void) { puts(" -f, --force Ignore most initialization errors"); } -static void abort_trace() { - g_abort_trace = true; -} - bool parse_options(int argc, char** argv, st_settings_t *settings) { static struct option long_options[] = { @@ -332,9 +331,12 @@ static bool EnableTrace(stlink_t* stlink, const st_settings_t* settings) { } static trace_state UpdateTraceIdle(st_trace_t* trace, uint8_t c) { + // Handle a trace byte when we are in the idle state. + if (TRACE_OP_IS_TARGET_SOURCE(c)) { return TRACE_STATE_TARGET_SOURCE; } + if (TRACE_OP_IS_SOURCE(c)) { uint8_t size = TRACE_OP_GET_SOURCE_SIZE(c); if (TRACE_OP_IS_SW_SOURCE(c)) { @@ -347,13 +349,16 @@ static trace_state UpdateTraceIdle(st_trace_t* trace, uint8_t c) { if (size == 2) return TRACE_STATE_SKIP_2; if (size == 3) return TRACE_STATE_SKIP_4; } + if (TRACE_OP_IS_LOCAL_TIME(c) || TRACE_OP_IS_GLOBAL_TIME(c)) { trace->count_time_packets++; return TRACE_OP_GET_CONTINUATION(c) ? TRACE_STATE_SKIP_FRAME : TRACE_STATE_IDLE; } + if (TRACE_OP_IS_EXTENSION(c)) { return TRACE_OP_GET_CONTINUATION(c) ? TRACE_STATE_SKIP_FRAME : TRACE_STATE_IDLE; } + if (TRACE_OP_IS_OVERFLOW(c)) { trace->count_overflow++; } From 4f762501c2c333aacc3e143fd0549bbe16c442e4 Mon Sep 17 00:00:00 2001 From: John Hall Date: Tue, 1 Dec 2020 12:08:29 -0800 Subject: [PATCH 136/503] Using debug instead of write. Fixing buffer semantics. --- inc/stlink.h | 2 +- src/st-trace/trace.c | 83 +++++++++++++++++++------------------------- src/stlink-lib/usb.c | 6 ++-- 3 files changed, 40 insertions(+), 51 deletions(-) diff --git a/inc/stlink.h b/inc/stlink.h index c369a133a..d40fdbb71 100644 --- a/inc/stlink.h +++ b/inc/stlink.h @@ -83,7 +83,7 @@ enum target_state { #define STLINK_V3_MAX_FREQ_NB 10 -#define STLINK_TRACE_BUF_LEN 4096 +#define STLINK_TRACE_BUF_LEN 2048 #define STLINK_TRACE_FREQUENCY 2000000 /* Cortex Debug Control Block */ diff --git a/src/st-trace/trace.c b/src/st-trace/trace.c index 379c4cec1..868334e49 100644 --- a/src/st-trace/trace.c +++ b/src/st-trace/trace.c @@ -252,20 +252,6 @@ static stlink_t* StLinkConnect(const st_settings_t* settings) { } } -static void Write32(stlink_t* stlink, uint32_t address, uint32_t data) { - write_uint32(stlink->q_buf, data); - if (stlink_write_mem32(stlink, address, 4)) { - ELOG("Unable to set address 0x%08x to 0x%08x\n", address, data); - } -} - -static uint32_t Read32(stlink_t* stlink, uint32_t address) { - if (stlink_read_mem32(stlink, address, 4)) { - ELOG("Unable to read from address 0x%08x\n", address); - } - return read_uint32(stlink->q_buf, 0); -} - static bool EnableTrace(stlink_t* stlink, const st_settings_t* settings) { if (stlink_force_debug(stlink)) { @@ -274,23 +260,23 @@ static bool EnableTrace(stlink_t* stlink, const st_settings_t* settings) { return false; } - if (settings->reset_board && stlink_reset(stlink)) { + if (settings->reset_board && stlink_jtag_reset(stlink, 2)) { ELOG("Unable to reset device\n"); if (!settings->force) return false; } - Write32(stlink, DCB_DHCSR, DBGKEY | C_DEBUGEN | C_HALT); - Write32(stlink, DCB_DEMCR, DEMCR_TRCENA); - Write32(stlink, FP_CTRL, FP_CTRL_KEY); - Write32(stlink, DWT_FUNCTION0, 0); - Write32(stlink, DWT_FUNCTION1, 0); - Write32(stlink, DWT_FUNCTION2, 0); - Write32(stlink, DWT_FUNCTION3, 0); - Write32(stlink, DWT_CTRL, 0); - Write32(stlink, DBGMCU_CR, DBGMCU_CR_DBG_SLEEP | DBGMCU_CR_DBG_STOP | - DBGMCU_CR_DBG_STANDBY | DBGMCU_CR_TRACE_IOEN | - DBGMCU_CR_TRACE_MODE_ASYNC); // Enable async tracing + stlink_write_debug32(stlink, DCB_DHCSR, DBGKEY | C_DEBUGEN | C_HALT); + stlink_write_debug32(stlink, DCB_DEMCR, DEMCR_TRCENA); + stlink_write_debug32(stlink, FP_CTRL, FP_CTRL_KEY); + stlink_write_debug32(stlink, DWT_FUNCTION0, 0); + stlink_write_debug32(stlink, DWT_FUNCTION1, 0); + stlink_write_debug32(stlink, DWT_FUNCTION2, 0); + stlink_write_debug32(stlink, DWT_FUNCTION3, 0); + stlink_write_debug32(stlink, DWT_CTRL, 0); + stlink_write_debug32(stlink, DBGMCU_CR, DBGMCU_CR_DBG_SLEEP | DBGMCU_CR_DBG_STOP | + DBGMCU_CR_DBG_STANDBY | DBGMCU_CR_TRACE_IOEN | + DBGMCU_CR_TRACE_MODE_ASYNC); // Enable async tracing if (stlink_trace_enable(stlink)) { ELOG("Unable to turn on tracing in stlink\n"); @@ -298,13 +284,26 @@ static bool EnableTrace(stlink_t* stlink, const st_settings_t* settings) { return false; } - Write32(stlink, TPI_CSPSR, TPI_TPI_CSPSR_PORT_SIZE_1); + stlink_write_debug32(stlink, TPI_CSPSR, TPI_TPI_CSPSR_PORT_SIZE_1); if (settings->core_frequency_mhz) { uint32_t prescaler = settings->core_frequency_mhz * 1000000 / STLINK_TRACE_FREQUENCY - 1; - Write32(stlink, TPI_ACPR, prescaler); // Set TPIU_ACPR clock divisor - } - uint32_t prescaler = Read32(stlink, TPI_ACPR); + stlink_write_debug32(stlink, TPI_ACPR, prescaler); // Set TPIU_ACPR clock divisor + } + stlink_write_debug32(stlink, TPI_FFCR, TPI_FFCR_TRIG_IN); + stlink_write_debug32(stlink, TPI_SPPR, TPI_SPPR_SWO_NRZ); + stlink_write_debug32(stlink, ITM_LAR, ITM_LAR_KEY); + stlink_write_debug32(stlink, ITM_TCC, 0x00000400); // Set sync counter + stlink_write_debug32(stlink, ITM_TCR, ITM_TCR_TRACE_BUS_ID_1 | ITM_TCR_TS_ENA | ITM_TCR_ITM_ENA); + stlink_write_debug32(stlink, ITM_TER, ITM_TER_PORTS_ALL); + stlink_write_debug32(stlink, ITM_TPR, ITM_TPR_PORTS_ALL); + stlink_write_debug32(stlink, DWT_CTRL, 4 * DWT_CTRL_NUM_COMP | DWT_CTRL_CYC_TAP | + 0xF * DWT_CTRL_POST_INIT | 0xF * DWT_CTRL_POST_PRESET | + DWT_CTRL_CYCCNT_ENA); + stlink_write_debug32(stlink, DCB_DEMCR, DEMCR_TRCENA); + + uint32_t prescaler; + stlink_read_debug32(stlink, TPI_ACPR, &prescaler); if (prescaler) { uint32_t system_clock_speed = (prescaler + 1) * STLINK_TRACE_FREQUENCY; uint32_t system_clock_speed_mhz = (system_clock_speed + 500000) / 1000000; @@ -312,21 +311,9 @@ static bool EnableTrace(stlink_t* stlink, const st_settings_t* settings) { } else { WLOG("Trace Port Interface not configured. Specify the system clock with a --clock=XX command\n"); WLOG("line option or set it in your device's clock initialization routine, such as with:\n"); - WLOG(" TPI->ACPR = HAL_RCC_GetHCLKFreq() / 2000000 - 1;\n"); + WLOG(" TPI->ACPR = HAL_RCC_GetHCLKFreq() / %d - 1;\n", STLINK_TRACE_FREQUENCY); } - Write32(stlink, TPI_FFCR, TPI_FFCR_TRIG_IN); - Write32(stlink, TPI_SPPR, TPI_SPPR_SWO_NRZ); - Write32(stlink, ITM_LAR, ITM_LAR_KEY); - Write32(stlink, ITM_TCC, 0x00000400); // Set sync counter - Write32(stlink, ITM_TCR, ITM_TCR_TRACE_BUS_ID_1 | ITM_TCR_TS_ENA | ITM_TCR_ITM_ENA); - Write32(stlink, ITM_TER, ITM_TER_PORTS_ALL); - Write32(stlink, ITM_TPR, ITM_TPR_PORTS_ALL); - Write32(stlink, DWT_CTRL, 4 * DWT_CTRL_NUM_COMP | DWT_CTRL_CYC_TAP | - 0xF * DWT_CTRL_POST_INIT | 0xF * DWT_CTRL_POST_PRESET | - DWT_CTRL_CYCCNT_ENA); - Write32(stlink, DCB_DEMCR, DEMCR_TRCENA); - return true; } @@ -417,8 +404,9 @@ static bool ReadTrace(stlink_t* stlink, st_trace_t* trace) { return false; } + DLOG("Trace Length %d\n", length); if (length == 0) { - usleep(1000); // Our buffer could fill in around 2ms, so sleep half that. + // usleep(100); return true; } @@ -525,15 +513,16 @@ int main(int argc, char** argv) return APP_RESULT_STLINK_STATE_ERROR; } + ILOG("Reading Trace\n"); + st_trace_t trace = {}; + trace.start_time = time(NULL); + if (stlink_run(stlink)) { ELOG("Unable to run device\n"); if (!settings.force) return APP_RESULT_STLINK_STATE_ERROR; } - ILOG("Reading Trace\n"); - st_trace_t trace = {}; - trace.start_time = time(NULL); while (!g_abort_trace && ReadTrace(stlink, &trace)) { CheckForConfigurationError(&trace); } diff --git a/src/stlink-lib/usb.c b/src/stlink-lib/usb.c index db187acc5..5b84bb36a 100644 --- a/src/stlink-lib/usb.c +++ b/src/stlink-lib/usb.c @@ -982,7 +982,7 @@ int _stlink_usb_enable_trace(stlink_t* sl) { int i = fill_command(sl, SG_DXFER_TO_DEV, rep_len); cmd[i++] = STLINK_DEBUG_COMMAND; cmd[i++] = STLINK_DEBUG_APIV2_START_TRACE_RX; - write_uint16(&cmd[i + 0], STLINK_TRACE_BUF_LEN); + write_uint16(&cmd[i + 0], 2 * STLINK_TRACE_BUF_LEN); write_uint32(&cmd[i + 2], STLINK_TRACE_FREQUENCY); size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); @@ -1053,8 +1053,8 @@ int _stlink_usb_read_trace(stlink_t* sl, uint8_t* buf, size_t size) { int res = 0; int t = libusb_bulk_transfer(slu->usb_handle, slu->ep_trace, buf, trace_count, &res, 3000); - if (t) { - ELOG("read_trace read error\n"); + if (t || res != trace_count) { + ELOG("read_trace read error %d\n", t); return(-1); } } From aaaae8a61c3bbe4753c85cbff4830fcade9bd462 Mon Sep 17 00:00:00 2001 From: John Hall Date: Tue, 1 Dec 2020 13:05:19 -0800 Subject: [PATCH 137/503] Minor change didn't compile. --- src/stlink-lib/usb.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/stlink-lib/usb.c b/src/stlink-lib/usb.c index 5b84bb36a..97b616532 100644 --- a/src/stlink-lib/usb.c +++ b/src/stlink-lib/usb.c @@ -1053,7 +1053,7 @@ int _stlink_usb_read_trace(stlink_t* sl, uint8_t* buf, size_t size) { int res = 0; int t = libusb_bulk_transfer(slu->usb_handle, slu->ep_trace, buf, trace_count, &res, 3000); - if (t || res != trace_count) { + if (t || res != (int)trace_count) { ELOG("read_trace read error %d\n", t); return(-1); } From ac104ebabea7ad796eff2e6ebe88f22d113aeafe Mon Sep 17 00:00:00 2001 From: John Hall Date: Tue, 1 Dec 2020 13:47:04 -0800 Subject: [PATCH 138/503] Allowed configuring trace frequency. --- inc/backend.h | 2 +- inc/stlink.h | 9 ++++-- src/common.c | 6 ++-- src/st-trace/trace.c | 67 +++++++++++++++++++++++++++++--------------- src/stlink-lib/usb.c | 4 +-- 5 files changed, 57 insertions(+), 31 deletions(-) diff --git a/inc/backend.h b/inc/backend.h index 470702fde..70b3b739f 100644 --- a/inc/backend.h +++ b/inc/backend.h @@ -29,7 +29,7 @@ int (*force_debug) (stlink_t *sl); int32_t (*target_voltage) (stlink_t *sl); int (*set_swdclk) (stlink_t * stl, uint16_t divisor); - int (*trace_enable) (stlink_t * sl); + int (*trace_enable) (stlink_t * sl, uint32_t frequency); int (*trace_disable) (stlink_t * sl); int (*trace_read) (stlink_t * sl, uint8_t* buf, size_t size); diff --git a/inc/stlink.h b/inc/stlink.h index d40fdbb71..653b48e44 100644 --- a/inc/stlink.h +++ b/inc/stlink.h @@ -83,8 +83,10 @@ enum target_state { #define STLINK_V3_MAX_FREQ_NB 10 -#define STLINK_TRACE_BUF_LEN 2048 -#define STLINK_TRACE_FREQUENCY 2000000 +#define STLINK_TRACE_BUF_LEN 2048 +#define STLINK_V2_MAX_TRACE_FREQUENCY 2000000 +#define STLINK_V3_MAX_TRACE_FREQUENCY 24000000 +#define STLINK_DEFAULT_TRACE_FREQUENCY 2000000 /* Cortex Debug Control Block */ #define DCB_DHCSR 0xE000EDF0 @@ -214,6 +216,7 @@ struct _stlink { char serial[STLINK_SERIAL_MAX_SIZE]; int serial_size; int freq; // set by stlink_open_usb(), values: STLINK_SWDCLK_xxx_DIVISOR + uint32_t max_trace_freq; // set by stlink_open_usb() enum stlink_flash_type flash_type; // stlink_chipid_params.flash_type, set by stlink_load_device_params(), values: STLINK_FLASH_TYPE_xxx @@ -267,7 +270,7 @@ int stlink_current_mode(stlink_t *sl); int stlink_force_debug(stlink_t *sl); int stlink_target_voltage(stlink_t *sl); int stlink_set_swdclk(stlink_t *sl, uint16_t divisor); -int stlink_trace_enable(stlink_t* sl); +int stlink_trace_enable(stlink_t* sl, uint32_t frequency); int stlink_trace_disable(stlink_t* sl); int stlink_trace_read(stlink_t* sl, uint8_t* buf, size_t size); diff --git a/src/common.c b/src/common.c index 0325c85f9..ac78db089 100644 --- a/src/common.c +++ b/src/common.c @@ -1468,6 +1468,7 @@ void _parse_version(stlink_t *sl, stlink_version_t *slv) { if (sl->version.jtag_v >= 13) { sl->version.flags |= STLINK_F_HAS_TRACE; + sl->max_trace_freq = STLINK_V2_MAX_TRACE_FREQUENCY; } } } else { @@ -1483,6 +1484,7 @@ void _parse_version(stlink_t *sl, stlink_version_t *slv) { /* preferred API to get last R/W status */ sl->version.flags |= STLINK_F_HAS_GETLASTRWSTATUS2; sl->version.flags |= STLINK_F_HAS_TRACE; + sl->max_trace_freq = STLINK_V3_MAX_TRACE_FREQUENCY; } return; @@ -1682,9 +1684,9 @@ int stlink_current_mode(stlink_t *sl) { return(STLINK_DEV_UNKNOWN_MODE); } -int stlink_trace_enable(stlink_t* sl) { +int stlink_trace_enable(stlink_t* sl, uint32_t frequency) { DLOG("*** stlink_trace_enable ***\n"); - return(sl->backend->trace_enable(sl)); + return(sl->backend->trace_enable(sl, frequency)); } int stlink_trace_disable(stlink_t* sl) { diff --git a/src/st-trace/trace.c b/src/st-trace/trace.c index 868334e49..fe4e20fdc 100644 --- a/src/st-trace/trace.c +++ b/src/st-trace/trace.c @@ -22,7 +22,8 @@ #define APP_RESULT_STLINK_MISSING_DEVICE 3 #define APP_RESULT_STLINK_UNSUPPORTED_DEVICE 4 #define APP_RESULT_STLINK_UNSUPPORTED_LINK 5 -#define APP_RESULT_STLINK_STATE_ERROR 6 +#define APP_RESULT_UNSUPPORTED_TRACE_FREQUENCY 6 +#define APP_RESULT_STLINK_STATE_ERROR 7 // See D4.2 of https://developer.arm.com/documentation/ddi0403/ed/ #define TRACE_OP_IS_OVERFLOW(c) ((c) == 0x70) @@ -98,13 +99,14 @@ typedef struct { - bool show_help; - bool show_version; - int logging_level; - int core_frequency_mhz; - bool reset_board; - bool force; - char* serial_number; + bool show_help; + bool show_version; + int logging_level; + uint32_t core_frequency; + uint32_t trace_frequency; + bool reset_board; + bool force; + char* serial_number; } st_settings_t; @@ -150,6 +152,7 @@ static void usage(void) { puts(" -vXX, --verbose=XX Specify a specific verbosity level (0..99)"); puts(" -v, --verbose Specify a generally verbose logging"); puts(" -cXX, --clock=XX Specify the core frequency in MHz"); + puts(" -tXX, --trace=XX Specify the trace frequency in Hz"); puts(" -n, --no-reset Do not reset board on connection"); puts(" -sXX, --serial=XX Use a specific serial number"); puts(" -f, --force Ignore most initialization errors"); @@ -162,6 +165,7 @@ bool parse_options(int argc, char** argv, st_settings_t *settings) { {"version", no_argument, NULL, 'V'}, {"verbose", optional_argument, NULL, 'v'}, {"clock", required_argument, NULL, 'c'}, + {"trace", required_argument, NULL, 't'}, {"no-reset", no_argument, NULL, 'n'}, {"serial", required_argument, NULL, 's'}, {"force", no_argument, NULL, 'f'}, @@ -174,7 +178,8 @@ bool parse_options(int argc, char** argv, st_settings_t *settings) { settings->show_help = false; settings->show_version = false; settings->logging_level = DEFAULT_LOGGING_LEVEL; - settings->core_frequency_mhz = 0; + settings->core_frequency = 0; + settings->trace_frequency = 0; settings->reset_board = true; settings->force = false; settings->serial_number = NULL; @@ -197,7 +202,10 @@ bool parse_options(int argc, char** argv, st_settings_t *settings) { ugly_init(settings->logging_level); break; case 'c': - settings->core_frequency_mhz = atoi(optarg); + settings->core_frequency = atoi(optarg) * 1000000; + break; + case 't': + settings->trace_frequency = atoi(optarg); break; case 'n': settings->reset_board = false; @@ -252,7 +260,7 @@ static stlink_t* StLinkConnect(const st_settings_t* settings) { } } -static bool EnableTrace(stlink_t* stlink, const st_settings_t* settings) { +static bool EnableTrace(stlink_t* stlink, const st_settings_t* settings, uint32_t trace_frequency) { if (stlink_force_debug(stlink)) { ELOG("Unable to debug device\n"); @@ -278,7 +286,8 @@ static bool EnableTrace(stlink_t* stlink, const st_settings_t* settings) { DBGMCU_CR_DBG_STANDBY | DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_ASYNC); // Enable async tracing - if (stlink_trace_enable(stlink)) { + DLOG("Setting trace frequency to %d Hz.\n", trace_frequency); + if (stlink_trace_enable(stlink, trace_frequency)) { ELOG("Unable to turn on tracing in stlink\n"); if (!settings->force) return false; @@ -286,8 +295,8 @@ static bool EnableTrace(stlink_t* stlink, const st_settings_t* settings) { stlink_write_debug32(stlink, TPI_CSPSR, TPI_TPI_CSPSR_PORT_SIZE_1); - if (settings->core_frequency_mhz) { - uint32_t prescaler = settings->core_frequency_mhz * 1000000 / STLINK_TRACE_FREQUENCY - 1; + if (settings->core_frequency) { + uint32_t prescaler = settings->core_frequency / trace_frequency - 1; stlink_write_debug32(stlink, TPI_ACPR, prescaler); // Set TPIU_ACPR clock divisor } stlink_write_debug32(stlink, TPI_FFCR, TPI_FFCR_TRIG_IN); @@ -305,13 +314,13 @@ static bool EnableTrace(stlink_t* stlink, const st_settings_t* settings) { uint32_t prescaler; stlink_read_debug32(stlink, TPI_ACPR, &prescaler); if (prescaler) { - uint32_t system_clock_speed = (prescaler + 1) * STLINK_TRACE_FREQUENCY; + uint32_t system_clock_speed = (prescaler + 1) * trace_frequency; uint32_t system_clock_speed_mhz = (system_clock_speed + 500000) / 1000000; ILOG("Trace Port Interface configured to expect a %d MHz system clock.\n", system_clock_speed_mhz); } else { WLOG("Trace Port Interface not configured. Specify the system clock with a --clock=XX command\n"); WLOG("line option or set it in your device's clock initialization routine, such as with:\n"); - WLOG(" TPI->ACPR = HAL_RCC_GetHCLKFreq() / %d - 1;\n", STLINK_TRACE_FREQUENCY); + WLOG(" TPI->ACPR = HAL_RCC_GetHCLKFreq() / %d - 1;\n", trace_frequency); } return true; @@ -404,12 +413,14 @@ static bool ReadTrace(stlink_t* stlink, st_trace_t* trace) { return false; } - DLOG("Trace Length %d\n", length); if (length == 0) { - // usleep(100); + usleep(100); return true; } + if (length == sizeof(buffer)) { + } + for (int i = 0; i < length; i++) { trace->state = UpdateTrace(trace, buffer[i]); } @@ -417,7 +428,7 @@ static bool ReadTrace(stlink_t* stlink, st_trace_t* trace) { return true; } -static void CheckForConfigurationError(st_trace_t* trace) { +static void CheckForConfigurationError(st_trace_t* trace, uint32_t trace_frequency) { uint32_t elapsed_time_s = time(NULL) - trace->start_time; if (trace->configuration_checked || elapsed_time_s < 10) { return; @@ -442,7 +453,7 @@ static void CheckForConfigurationError(st_trace_t* trace) { WLOG("Unknown Source %d\n", i); WLOG("Check that the clock frequency is set correctly. Either with the --clock=XX\n"); WLOG("command line option, or by adding the following to your device's clock initialization:\n"); - WLOG(" TPI->ACPR = HAL_RCC_GetHCLKFreq() / 2000000 - 1;\n"); + WLOG(" TPI->ACPR = HAL_RCC_GetHCLKFreq() / %d - 1;\n", trace_frequency); WLOG("****\n"); } } @@ -465,7 +476,8 @@ int main(int argc, char** argv) DLOG("show_help = %s\n", settings.show_help ? "true" : "false"); DLOG("show_version = %s\n", settings.show_version ? "true" : "false"); DLOG("logging_level = %d\n", settings.logging_level); - DLOG("core_frequency = %d MHz\n", settings.core_frequency_mhz); + DLOG("core_frequency = %d Hz\n", settings.core_frequency); + DLOG("trace_frequency = %d Hz\n", settings.trace_frequency); DLOG("reset_board = %s\n", settings.reset_board ? "true" : "false"); DLOG("force = %s\n", settings.force ? "true" : "false"); DLOG("serial_number = %s\n", settings.serial_number ? settings.serial_number : "any"); @@ -507,7 +519,16 @@ int main(int argc, char** argv) return APP_RESULT_STLINK_UNSUPPORTED_DEVICE; } - if (!EnableTrace(stlink, &settings)) { + uint32_t trace_frequency = settings.trace_frequency; + if (!trace_frequency) + trace_frequency = STLINK_DEFAULT_TRACE_FREQUENCY; + if (trace_frequency > stlink->max_trace_freq) { + ELOG("Invalid trace frequency %d (max %d)\n", trace_frequency, stlink->max_trace_freq); + if (!settings.force) + return APP_RESULT_UNSUPPORTED_TRACE_FREQUENCY; + } + + if (!EnableTrace(stlink, &settings, trace_frequency)) { ELOG("Unable to enable trace mode\n"); if (!settings.force) return APP_RESULT_STLINK_STATE_ERROR; @@ -524,7 +545,7 @@ int main(int argc, char** argv) } while (!g_abort_trace && ReadTrace(stlink, &trace)) { - CheckForConfigurationError(&trace); + CheckForConfigurationError(&trace, trace_frequency); } stlink_trace_disable(stlink); diff --git a/src/stlink-lib/usb.c b/src/stlink-lib/usb.c index 97b616532..db11968a6 100644 --- a/src/stlink-lib/usb.c +++ b/src/stlink-lib/usb.c @@ -972,7 +972,7 @@ int _stlink_usb_write_reg(stlink_t *sl, uint32_t reg, int idx) { return(0); } -int _stlink_usb_enable_trace(stlink_t* sl) { +int _stlink_usb_enable_trace(stlink_t* sl, uint32_t frequency) { struct stlink_libusb * const slu = sl->backend_data; unsigned char* const data = sl->q_buf; unsigned char* const cmd = sl->c_buf; @@ -983,7 +983,7 @@ int _stlink_usb_enable_trace(stlink_t* sl) { cmd[i++] = STLINK_DEBUG_COMMAND; cmd[i++] = STLINK_DEBUG_APIV2_START_TRACE_RX; write_uint16(&cmd[i + 0], 2 * STLINK_TRACE_BUF_LEN); - write_uint32(&cmd[i + 2], STLINK_TRACE_FREQUENCY); + write_uint32(&cmd[i + 2], frequency); size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); From a331da4df3e539c39820a4404b3a2f4ee591df84 Mon Sep 17 00:00:00 2001 From: John Hall Date: Tue, 1 Dec 2020 15:54:40 -0800 Subject: [PATCH 139/503] Improving diagnostics, especially for sw buffer overruns. --- src/st-trace/trace.c | 88 +++++++++++++++++++++++++++++++------------- 1 file changed, 62 insertions(+), 26 deletions(-) diff --git a/src/st-trace/trace.c b/src/st-trace/trace.c index fe4e20fdc..f82a804c6 100644 --- a/src/st-trace/trace.c +++ b/src/st-trace/trace.c @@ -130,7 +130,8 @@ typedef struct { uint32_t count_raw_bytes; uint32_t count_target_data; uint32_t count_time_packets; - uint32_t count_overflow; + uint32_t count_hw_overflow; + uint32_t count_sw_overflow; uint32_t count_error; uint8_t unknown_opcodes[256 / 8]; @@ -356,7 +357,7 @@ static trace_state UpdateTraceIdle(st_trace_t* trace, uint8_t c) { } if (TRACE_OP_IS_OVERFLOW(c)) { - trace->count_overflow++; + trace->count_hw_overflow++; } if (!(trace->unknown_opcodes[c / 8] & (1 << c % 8))) @@ -419,6 +420,10 @@ static bool ReadTrace(stlink_t* stlink, st_trace_t* trace) { } if (length == sizeof(buffer)) { + if (trace->count_sw_overflow++) + DLOG("Buffer overflow.\n"); + else + WLOG("Buffer overflow. Try using a slower trace frequency.\n"); } for (int i = 0; i < length; i++) { @@ -428,7 +433,8 @@ static bool ReadTrace(stlink_t* stlink, st_trace_t* trace) { return true; } -static void CheckForConfigurationError(st_trace_t* trace, uint32_t trace_frequency) { +static void CheckForConfigurationError(stlink_t* stlink, st_trace_t* trace, uint32_t trace_frequency) { + // Only check configuration one time after the first 10 seconds of running. uint32_t elapsed_time_s = time(NULL) - trace->start_time; if (trace->configuration_checked || elapsed_time_s < 10) { return; @@ -436,38 +442,68 @@ static void CheckForConfigurationError(st_trace_t* trace, uint32_t trace_frequen trace->configuration_checked = true; // Simple huristic to determine if we are configured poorly. - if (trace->count_raw_bytes < 100 || trace->count_error > 1 || trace->count_time_packets < 10) { - // Output Diagnostic Information - WLOG("****\n"); - WLOG("We do not appear to be retrieving data from the stlink correctly.\n"); - WLOG("Raw Bytes: %d\n", trace->count_raw_bytes); - WLOG("Target Data: %d\n", trace->count_target_data); - WLOG("Time Packets: %d\n", trace->count_time_packets); - WLOG("Overlow Count: %d\n", trace->count_overflow); - WLOG("Errors: %d\n", trace->count_error); - for (uint32_t i = 0; i <= 0xFF; i++) - if (trace->unknown_opcodes[i / 8] & (1 << i % 8)) - WLOG("Unknown Opcode 0x%02x\n", i); - for (uint32_t i = 0; i < 32; i++) - if (trace->unknown_sources & (1 << i)) - WLOG("Unknown Source %d\n", i); - WLOG("Check that the clock frequency is set correctly. Either with the --clock=XX\n"); - WLOG("command line option, or by adding the following to your device's clock initialization:\n"); + bool error_no_data = (trace->count_raw_bytes < 100); + bool error_bad_data = (trace->count_error > 1 || trace->count_time_packets < 10 || trace->unknown_sources > 0); + bool error_dropped_data = (trace->count_sw_overflow > 0); + + if (!error_no_data && !error_bad_data && !error_dropped_data) + return; + + WLOG("****\n"); + WLOG("We do not appear to be retrieving data from the stlink correctly.\n"); + + if (error_dropped_data) { + WLOG("Try setting a slower trace frequency with the --trace=%d command line option.\n", trace_frequency / 2); + } + + if (error_no_data || error_bad_data) { + uint32_t prescaler; + stlink_read_debug32(stlink, TPI_ACPR, &prescaler); + if (prescaler) { + uint32_t system_clock_speed = (prescaler + 1) * trace_frequency; + uint32_t system_clock_speed_mhz = (system_clock_speed + 500000) / 1000000; + WLOG("Verify the system clock is running at %d MHz.\n", system_clock_speed_mhz); + } + WLOG("Try specifying the system clock with the --clock=XX command line option.\n"); + WLOG("Try setting the trace speed in your device's clock initialization routine:\n"); WLOG(" TPI->ACPR = HAL_RCC_GetHCLKFreq() / %d - 1;\n", trace_frequency); - WLOG("****\n"); } + + WLOG("Diagnostic Information:\n"); + WLOG("Raw Bytes: %d\n", trace->count_raw_bytes); + WLOG("Target Data: %d\n", trace->count_target_data); + WLOG("Time Packets: %d\n", trace->count_time_packets); + WLOG("Hardware Overflow Count: %d\n", trace->count_hw_overflow); + WLOG("Software Overflow Count: %d\n", trace->count_sw_overflow); + WLOG("Errors: %d\n", trace->count_error); + + char buffer[1024]; + memset(buffer, 0, sizeof(buffer)); + uint32_t offset = 0; + for (uint32_t i = 0; i <= 0xFF; i++) + if (trace->unknown_opcodes[i / 8] & (1 << i % 8)) + offset += snprintf(buffer + offset, sizeof(buffer) - offset, "%02x, ", i); + WLOG("Unknown Opcodes: %s\n", buffer); + + memset(buffer, 0, sizeof(buffer)); + offset = 0; + for (uint32_t i = 0; i < 32; i++) + if (trace->unknown_sources & (1 << i)) + offset += snprintf(buffer + offset, sizeof(buffer) - offset, "%d, ", i); + WLOG("Unknown Sources: %s\n", buffer); + + WLOG("Chip ID: 0x%04x\n", stlink->chip_id); + WLOG("****\n"); } int main(int argc, char** argv) { - st_settings_t settings; - stlink_t* stlink = NULL; - signal(SIGINT, &abort_trace); signal(SIGTERM, &abort_trace); signal(SIGSEGV, &abort_trace); signal(SIGPIPE, &abort_trace); + st_settings_t settings; if (!parse_options(argc, argv, &settings)) { usage(); return APP_RESULT_INVALID_PARAMS; @@ -492,7 +528,7 @@ int main(int argc, char** argv) return APP_RESULT_SUCCESS; } - stlink = StLinkConnect(&settings); + stlink_t* stlink = StLinkConnect(&settings); if (!stlink) { ELOG("Unable to locate an stlink\n"); return APP_RESULT_STLINK_NOT_FOUND; @@ -545,7 +581,7 @@ int main(int argc, char** argv) } while (!g_abort_trace && ReadTrace(stlink, &trace)) { - CheckForConfigurationError(&trace, trace_frequency); + CheckForConfigurationError(stlink, &trace, trace_frequency); } stlink_trace_disable(stlink); From 57f1bc791112ce2cacb3481484747b6332b537fa Mon Sep 17 00:00:00 2001 From: John Hall Date: Tue, 1 Dec 2020 16:28:10 -0800 Subject: [PATCH 140/503] Making sure TPI async prescalar is within the available range. Trying to recover from buffer overruns where we may land in the middle of trace output. --- src/st-trace/trace.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/src/st-trace/trace.c b/src/st-trace/trace.c index f82a804c6..8368cee34 100644 --- a/src/st-trace/trace.c +++ b/src/st-trace/trace.c @@ -84,6 +84,7 @@ #define TPI_SPPR_SWO_MANCHESTER (0x01 << 0) #define TPI_SPPR_SWO_NRZ (0x02 << 0) #define TPI_FFCR_TRIG_IN (0x01 << 8) +#define TPI_ACPR_MAX (0x1FFF) // Other Registers #define FP_CTRL 0xE0002000 // Flash Patch Control Register @@ -112,6 +113,7 @@ typedef struct { // We use a simple state machine to parse the trace data. typedef enum { + TRACE_STATE_UNKNOWN, TRACE_STATE_IDLE, TRACE_STATE_TARGET_SOURCE, TRACE_STATE_SKIP_FRAME, @@ -298,6 +300,11 @@ static bool EnableTrace(stlink_t* stlink, const st_settings_t* settings, uint32_ if (settings->core_frequency) { uint32_t prescaler = settings->core_frequency / trace_frequency - 1; + if (prescaler > TPI_ACPR_MAX) { + ELOG("Trace frequency prescaler %d out of range. Try setting a faster trace frequency.\n", prescaler); + if (!settings->force) + return false; + } stlink_write_debug32(stlink, TPI_ACPR, prescaler); // Set TPIU_ACPR clock divisor } stlink_write_debug32(stlink, TPI_FFCR, TPI_FFCR_TRIG_IN); @@ -372,6 +379,12 @@ static trace_state UpdateTrace(st_trace_t* trace, uint8_t c) { trace->count_raw_bytes++; // Parse the input using a state machine. + + if (trace->state == TRACE_STATE_UNKNOWN) { + if (TRACE_OP_IS_TARGET_SOURCE(c) || TRACE_OP_IS_LOCAL_TIME(c) || TRACE_OP_IS_GLOBAL_TIME(c)) + trace->state = TRACE_STATE_IDLE; + } + switch (trace->state) { case TRACE_STATE_IDLE: @@ -399,6 +412,9 @@ static trace_state UpdateTrace(st_trace_t* trace, uint8_t c) { case TRACE_STATE_SKIP_1: return TRACE_STATE_IDLE; + case TRACE_STATE_UNKNOWN: + return TRACE_STATE_UNKNOWN; + default: ELOG("Invalid state %d. This should never happen\n", trace->state); return TRACE_STATE_IDLE; @@ -424,6 +440,7 @@ static bool ReadTrace(stlink_t* stlink, st_trace_t* trace) { DLOG("Buffer overflow.\n"); else WLOG("Buffer overflow. Try using a slower trace frequency.\n"); + trace->state = TRACE_STATE_UNKNOWN; } for (int i = 0; i < length; i++) { From 305b7a4f2b3723af690931b11ac8e81167d14230 Mon Sep 17 00:00:00 2001 From: John Hall Date: Tue, 1 Dec 2020 16:35:40 -0800 Subject: [PATCH 141/503] Inproving huristic to handle cases where there is lots of valid data coming in that is starving out the time trace ops. --- src/st-trace/trace.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/src/st-trace/trace.c b/src/st-trace/trace.c index 8368cee34..1356ceca0 100644 --- a/src/st-trace/trace.c +++ b/src/st-trace/trace.c @@ -289,7 +289,6 @@ static bool EnableTrace(stlink_t* stlink, const st_settings_t* settings, uint32_ DBGMCU_CR_DBG_STANDBY | DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_ASYNC); // Enable async tracing - DLOG("Setting trace frequency to %d Hz.\n", trace_frequency); if (stlink_trace_enable(stlink, trace_frequency)) { ELOG("Unable to turn on tracing in stlink\n"); if (!settings->force) @@ -330,6 +329,7 @@ static bool EnableTrace(stlink_t* stlink, const st_settings_t* settings, uint32_ WLOG("line option or set it in your device's clock initialization routine, such as with:\n"); WLOG(" TPI->ACPR = HAL_RCC_GetHCLKFreq() / %d - 1;\n", trace_frequency); } + ILOG("Trace frequency set to %d Hz.\n", trace_frequency); return true; } @@ -460,10 +460,11 @@ static void CheckForConfigurationError(stlink_t* stlink, st_trace_t* trace, uint // Simple huristic to determine if we are configured poorly. bool error_no_data = (trace->count_raw_bytes < 100); - bool error_bad_data = (trace->count_error > 1 || trace->count_time_packets < 10 || trace->unknown_sources > 0); + bool error_low_data = (trace->count_time_packets < 10 && trace->count_target_data < 1000); + bool error_bad_data = (trace->count_error > 1 || trace->unknown_sources > 0); bool error_dropped_data = (trace->count_sw_overflow > 0); - if (!error_no_data && !error_bad_data && !error_dropped_data) + if (!error_no_data && !error_low_data && !error_bad_data && !error_dropped_data) return; WLOG("****\n"); @@ -473,7 +474,7 @@ static void CheckForConfigurationError(stlink_t* stlink, st_trace_t* trace, uint WLOG("Try setting a slower trace frequency with the --trace=%d command line option.\n", trace_frequency / 2); } - if (error_no_data || error_bad_data) { + if (error_no_data || error_low_data || error_bad_data) { uint32_t prescaler; stlink_read_debug32(stlink, TPI_ACPR, &prescaler); if (prescaler) { From fdeb1729d68aa1949f856dc539a444c8c7a1bb06 Mon Sep 17 00:00:00 2001 From: John Hall Date: Wed, 2 Dec 2020 09:52:12 -0800 Subject: [PATCH 142/503] When a USB error occurs, chip-id does not appear to be initialized. --- src/common.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/common.c b/src/common.c index ac78db089..20d71df32 100644 --- a/src/common.c +++ b/src/common.c @@ -1305,7 +1305,7 @@ int stlink_load_device_params(stlink_t *sl) { DLOG("Loading device parameters....\n"); const struct stlink_chipid_params *params = NULL; stlink_core_id(sl); - uint32_t chip_id; + uint32_t chip_id = 0; uint32_t flash_size; stlink_chip_id(sl, &chip_id); From 1bbdd74c4b1b5ca7fe0bbfe367677503e20dc82d Mon Sep 17 00:00:00 2001 From: Ant-ON Date: Sat, 5 Dec 2020 11:16:39 +0500 Subject: [PATCH 143/503] Fix the indentation --- CMakeLists.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index 4ab43271e..b125803b8 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -109,7 +109,7 @@ set(STLINK_HEADERS src/stlink-lib/md5.h src/stlink-lib/sg.h src/stlink-lib/usb.h - src/stlink-lib/helper.h + src/stlink-lib/helper.h ) set(STLINK_SOURCE From 20e1d531153093842c6c37fec5dd4564e92934cd Mon Sep 17 00:00:00 2001 From: Ant-ON Date: Sat, 5 Dec 2020 15:16:14 +0500 Subject: [PATCH 144/503] Fix the indentation --- CMakeLists.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index b125803b8..c8ab40257 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -120,7 +120,7 @@ set(STLINK_SOURCE src/stlink-lib/md5.c src/stlink-lib/sg.c src/stlink-lib/usb.c - src/stlink-lib/helper.c + src/stlink-lib/helper.c ) if (WIN32) From d6c9f8bd1103b1ad9f603e9b38ff7a73e3598c1b Mon Sep 17 00:00:00 2001 From: Oleksiy Slyshyk Date: Sat, 5 Dec 2020 13:28:36 +0200 Subject: [PATCH 145/503] fix printf format srting --- src/st-info/info.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/st-info/info.c b/src/st-info/info.c index 2e1ce0e96..0fc4d4d8a 100644 --- a/src/st-info/info.c +++ b/src/st-info/info.c @@ -76,7 +76,7 @@ static void stlink_probe(void) { printf("Found %u stlink programmers\n", (unsigned int)size); for (size_t n = 0; n < size; n++) { - if (size>1) printf("%lu.\n", n+1); + if (size > 1) printf("%u.\n", (unsigned int)n+1); stlink_print_info(stdevs[n]); } From 28c94453485a42290f0830219a1ab3a4f224111c Mon Sep 17 00:00:00 2001 From: Oleksiy Slyshyk Date: Sat, 5 Dec 2020 14:10:24 +0200 Subject: [PATCH 146/503] fix gettimeofday for msvc --- src/win32/sys_time.c | 31 ++++++++++++++++++++++--------- src/win32/sys_time.h | 5 +---- 2 files changed, 23 insertions(+), 13 deletions(-) diff --git a/src/win32/sys_time.c b/src/win32/sys_time.c index ea7c25dda..08da60b85 100644 --- a/src/win32/sys_time.c +++ b/src/win32/sys_time.c @@ -1,20 +1,33 @@ -#include -#include - #include "sys_time.h" +#ifndef STLINK_HAVE_SYS_TIME_H + +#include + /* Simple gettimeofday implementation without converting Windows time to Linux time */ int gettimeofday(struct timeval *tv, struct timezone *tz) { FILETIME ftime; ULARGE_INTEGER ulint; + static int tzflag = 0; + + if(NULL != tv) { + GetSystemTimeAsFileTime(&ftime); + ulint.LowPart = ftime.dwLowDateTime; + ulint.HighPart = ftime.dwHighDateTime; - GetSystemTimeAsFileTime(&ftime); - ulint.LowPart = ftime.dwLowDateTime; - ulint.HighPart = ftime.dwHighDateTime; + tv->tv_sec = (long)(ulint.QuadPart / 10000000L); + tv->tv_usec = (long)(ulint.QuadPart % 10000000L); + } - tv->tv_sec = (long)(ulint.QuadPart / 10000000L); - tv->tv_usec = (long)(ulint.QuadPart % 10000000L); + if(NULL != tz) { + if (!tzflag) { + _tzset(); + tzflag++; + } + tz->tz_minuteswest = _timezone / 60; + tz->tz_dsttime = _daylight; + } return 0; - (void)tz; } +#endif //STLINK_HAVE_SYS_TIME_H diff --git a/src/win32/sys_time.h b/src/win32/sys_time.h index 87c3a42fd..39f97f739 100644 --- a/src/win32/sys_time.h +++ b/src/win32/sys_time.h @@ -5,10 +5,7 @@ #include #else -struct timeval { - long tv_sec; - long tv_usec; -}; +#include struct timezone { int tz_minuteswest; From fc9e7915fc9b783a5e0467d473645ca81ea3c97f Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sat, 5 Dec 2020 13:35:23 +0100 Subject: [PATCH 147/503] General Project Update - Corrected identation in reg.h - Updated README.md - Updated CHANGELOG.md - Updated list of contributors --- CHANGELOG.md | 16 +++++++- README.md | 19 ++------- contributors.txt | 8 ++-- doc/devices_boards.md | 2 +- src/stlink-lib/reg.h | 90 +++++++++++++++++++++---------------------- 5 files changed, 67 insertions(+), 68 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index d9dc64a11..4c178a4e4 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -8,7 +8,16 @@ Release date: (TBD) Features: +* Added support for STM32H742/743/753 ([#671](https://github.com/stlink-org/stlink/pull/671), [#793](https://github.com/stlink-org/stlink/pull/793), [#823](https://github.com/stlink-org/stlink/pull/823), [#998](https://github.com/stlink-org/stlink/pull/998), [#1052](https://github.com/stlink-org/stlink/pull/1052)) +* Added preliminary support for STM32L5x2 ([#904](https://github.com/stlink-org/stlink/pull/904), [#999](https://github.com/stlink-org/stlink/pull/999)) * Option bytes on the STM32F767 ZIT6 Nucleo-144 ([#968](https://github.com/stlink-org/stlink/pull/968), [#997](https://github.com/stlink-org/stlink/pull/997)) +* Use SetConsoleCtrlHandler for Windows ([#1021](https://github.com/stlink-org/stlink/pull/1021)) +* Increase STM32L0 option_size to 20 ([#1046](https://github.com/stlink-org/stlink/pull/1046)) +* st-util: Add specialized memory map for STM32H7 devices ([#1060](https://github.com/stlink-org/stlink/pull/1060)) +* Support for STM32F4 option bytes ([#1062](https://github.com/stlink-org/stlink/pull/1062)) +* Link for WIN32 & APPLE with stlink-static ([#1069](https://github.com/stlink-org/stlink/pull/1069)) +* Extended support for STM32H7 ([#1059](https://github.com/stlink-org/stlink/pull/1059), [#1063](https://github.com/stlink-org/stlink/pull/1063), [#1071](https://github.com/stlink-org/stlink/pull/1071)) +* ITM functionality for ST-Link V2 and STM32Fxx chipsets ([#136](https://github.com/stlink-org/stlink/pull/136), [#179](https://github.com/stlink-org/stlink/pull/179), [#815](https://github.com/stlink-org/stlink/pull/815), [#1072](https://github.com/stlink-org/stlink/pull/1072)) Updates & changes: @@ -16,6 +25,7 @@ Updates & changes: * [refactoring] General maintenance ([#864](https://github.com/stlink-org/stlink/pull/864), [#976](https://github.com/stlink-org/stlink/pull/976), [#978](https://github.com/stlink-org/stlink/pull/978)) * Imported debian pkg-settings ([#986](https://github.com/stlink-org/stlink/pull/986)) * Add support for FreeBSD's libusb reimplementation ([#992](https://github.com/stlink-org/stlink/pull/992), [#993](https://github.com/stlink-org/stlink/pull/993)) +* [doc] Added example for output of 'st-info --probe' ([#1007](https://github.com/stlink-org/stlink/pull/1007), [#1049](https://github.com/stlink-org/stlink/pull/1049)) Fixes: @@ -26,8 +36,10 @@ Fixes: * Fix for static linking of libssp ([#973](https://github.com/stlink-org/stlink/pull/973), [#974](https://github.com/stlink-org/stlink/pull/974)) * Fixed connect under reset for st-flash and st-util ([#983](https://github.com/stlink-org/stlink/pull/983)) * Fix for mmap() size_t overflow in st-flash ([#988](https://github.com/stlink-org/stlink/pull/988), [#989](https://github.com/stlink-org/stlink/pull/989)) -* [regression] stlink-gui installation issue on Ubuntu-18.04 ([#1006](https://github.com/stlink-org/stlink/pull/1006)) -* st-util: wrong register values passed to gdb (st-link v2) ([#1026](https://github.com/stlink-org/stlink/pull/1026), [#1027](https://github.com/stlink-org/stlink/pull/1027)) +* [regression] stlink-gui installation issue on Ubuntu-18.04 ([#1001](https://github.com/stlink-org/stlink/pull/1001), [#1004](https://github.com/stlink-org/stlink/pull/1004), [#1006](https://github.com/stlink-org/stlink/pull/1006)) +* st-util: wrong register values passed to gdb (st-link v2) ([#1002](https://github.com/stlink-org/stlink/pull/1002), [#1011](https://github.com/stlink-org/stlink/pull/1011), [#1026](https://github.com/stlink-org/stlink/pull/1026), [#1027](https://github.com/stlink-org/stlink/pull/1027)) +* [doc] Fixed wrong path for rules.d folder ([#1020](https://github.com/stlink-org/stlink/pull/1020)) +* Use vl flashloader for all STM32F1 series ([#1041](https://github.com/stlink-org/stlink/pull/1041), [#1044](https://github.com/stlink-org/stlink/pull/1044)) v1.6.1 diff --git a/README.md b/README.md index 5be842156..350c36e34 100644 --- a/README.md +++ b/README.md @@ -23,7 +23,7 @@ The stlink library and tools are licensed under the **[BSD-3 License](LICENSE.md STLink is an open source toolset to program and debug STM32 devices and boards manufactured by STMicroelectronics. It supports several so called STLINK programmer boards (and clones thereof) which use a microcontroller chip to translate commands from USB to JTAG/SWD. There are four generations available on the market which are _all_ supported by this toolset: -* **STLINK/v1** _(obsolete as of 21-11-2019, continued support by this toolset)_ +* **STLINK/v1** _[obsolete as of 21-11-2019, continued support by this toolset] *)_ - transport layer: SCSI passthru commands over USB - stand-alone programmer and present on STM32VL Discovery boards * **STLINK/v2** @@ -36,6 +36,8 @@ It supports several so called STLINK programmer boards (and clones thereof) whic - transport layer: raw USB commands - stand-alone programmer +_*)_ **Note: Support on macOS is limited to 10.13 - 10.15. Any later versions are no longer compatible with the STLINK/v1 due to technical reasons.** + On the user level there is no difference in handling or operation between these different revisions. The STlink toolset includes: @@ -112,18 +114,3 @@ When there is no executable available for your platform or you need the latest ( * Please start new forks from the develop branch, as pull requests will go into this branch as well. Please also refer to our [Contribution Guidelines](CONTRIBUTING.md). - - -# Current state of the project -## Known missing features - -Some features are currently missing from the `stlink-org/stlink` toolset. -Here we would appreciate any help and would love to welcome new contributors who want to get involved: - -* Instrumentation Trace Macro (ITM) Cell ([#136](https://github.com/stlink-org/stlink/issues/136)) -* OTP & EEPROM area programming ([#202](https://github.com/stlink-org/stlink/issues/202), [#333](https://github.com/stlink-org/stlink/issues/333), [#686](https://github.com/stlink-org/stlink/issues/686)) -* Protection bits area reading ([#346](https://github.com/stlink-org/stlink/issues/346)) -* Writing external memory connected to an STM32 controller (e.g Quad SPI NOR flash) ([#412](https://github.com/stlink-org/stlink/issues/412)) -* MCU hotplug ([#449](https://github.com/stlink-org/stlink/issues/449)) -* Writing options bytes (region) ([#458](https://github.com/stlink-org/stlink/issues/458)) -* Enhanced support for STLINKv3 programmer ([#820](https://github.com/stlink-org/stlink/issues/820)) diff --git a/contributors.txt b/contributors.txt index cc9403456..65b53aed1 100644 --- a/contributors.txt +++ b/contributors.txt @@ -7,6 +7,7 @@ Andrea Mucignat Andrew Andrianov [necromant] Andrey Yurovsky Andy Isaacson +Anton [Ant-ON] Áron Radics A. Sheaff Björn Hauffe @@ -35,7 +36,7 @@ Denis Osterland Dmitry Bravikov [bravikov] Efe Can İçöz Ethan Zonca -Fabien Chouteau +Fabien Chouteau [Fabien-Chouteau] Florian Hars Friedrich Beckmann Gabriel Górski [Glaeqen] @@ -63,6 +64,7 @@ Jim Paris Jiří Netolický Jerry Nosky [jnosky] Jochen Wilhelmy [Jochen0x90h] +Joel Bodenmann [Tectu] Johannes Taelman Jonas Danielsson Jonas Norling @@ -71,7 +73,6 @@ Karl Palsson [karlp] Kevlar Harness Kyle Manna Lari Lehtomäki -Lutz Freitag [nerdmaennchen] Martin Nowak Matteo Collina Max Chen @@ -80,7 +81,6 @@ Maxime Vincent Michael Pratt [prattmic] Michael Sparmann Mike Szczys -Miklós Márton [martonmiklos] Magnus Lundin [mlu] mux Ned Konz @@ -111,7 +111,7 @@ Simon Wright Stany Marcel Stefan Misik Sven Wegener -Joel Bodenmann [Tectu] +Timothy Lee [timothytylee] Tuomo Kaikkonen Theodore A. Roth Thomas Gärtner diff --git a/doc/devices_boards.md b/doc/devices_boards.md index 8291f7532..4402839c5 100644 --- a/doc/devices_boards.md +++ b/doc/devices_boards.md @@ -50,7 +50,7 @@ Tested boards [incl. STLink programmers]: | 0x418 | STM32F105xx/107xx | x8 xB xC | | | | | F105
F107 | | 0x420 | Medium density value | x8 xB | F100 | | | | | | 0x428 | High density Value | xC xD xE | F100 | | | | | -| 0x430 | XL-Density | xF XG | | F101 | | F103 | | +| 0x430 | XL-Density | xF xG | | F101 | | F103 | | Tested boards [incl. STLink programmers]: * STM32VL-Discovery (STM32F100RBT6) with STLink-v1 [v1, v2] diff --git a/src/stlink-lib/reg.h b/src/stlink-lib/reg.h index 2e93dc5b1..fdea175d3 100644 --- a/src/stlink-lib/reg.h +++ b/src/stlink-lib/reg.h @@ -1,61 +1,61 @@ #ifndef STLINK_REG_H_ #define STLINK_REG_H_ -#define STLINK_REG_CM3_CPUID 0xE000ED00 +#define STLINK_REG_CM3_CPUID 0xE000ED00 -#define STLINK_REG_CM3_FP_CTRL 0xE0002000 -#define STLINK_REG_CM3_FP_COMPn(n) (0xE0002008 + n*4) -#define STLINK_REG_CM7_FP_LAR 0xE0000FB0 +#define STLINK_REG_CM3_FP_CTRL 0xE0002000 +#define STLINK_REG_CM3_FP_COMPn(n) (0xE0002008 + n*4) +#define STLINK_REG_CM7_FP_LAR 0xE0000FB0 #define STLINK_REG_CM7_FP_LAR_KEY 0xC5ACCE55 -#define STLINK_REG_CM3_DEMCR 0xE000EDFC -#define STLINK_REG_CM3_DEMCR_TRCENA (1 << 24) -#define STLINK_REG_CM3_DEMCR_VC_HARDERR (1 << 10) -#define STLINK_REG_CM3_DEMCR_VC_BUSERR (1 << 8) -#define STLINK_REG_CM3_DEMCR_VC_CORERESET (1 << 0) -#define STLINK_REG_CM3_DWT_COMPn(n) (0xE0001020 + n*16) -#define STLINK_REG_CM3_DWT_MASKn(n) (0xE0001024 + n*16) -#define STLINK_REG_CM3_DWT_FUNn(n) (0xE0001028 + n*16) +#define STLINK_REG_CM3_DEMCR 0xE000EDFC +#define STLINK_REG_CM3_DEMCR_TRCENA (1 << 24) +#define STLINK_REG_CM3_DEMCR_VC_HARDERR (1 << 10) +#define STLINK_REG_CM3_DEMCR_VC_BUSERR (1 << 8) +#define STLINK_REG_CM3_DEMCR_VC_CORERESET (1 << 0) +#define STLINK_REG_CM3_DWT_COMPn(n) (0xE0001020 + n*16) +#define STLINK_REG_CM3_DWT_MASKn(n) (0xE0001024 + n*16) +#define STLINK_REG_CM3_DWT_FUNn(n) (0xE0001028 + n*16) /* Cortex™-M3 Technical Reference Manual */ /* Debug Halting Control and Status Register */ -#define STLINK_REG_DFSR 0xE000ED30 -#define STLINK_REG_DFSR_HALT (1 << 0) -#define STLINK_REG_DFSR_BKPT (1 << 1) -#define STLINK_REG_DFSR_VCATCH (1 << 3) -#define STLINK_REG_DFSR_EXTERNAL (1 << 4) -#define STLINK_REG_DFSR_CLEAR 0x0000001F -#define STLINK_REG_DHCSR 0xe000edf0 -#define STLINK_REG_DHCSR_DBGKEY (0xA05F << 16) -#define STLINK_REG_DHCSR_C_DEBUGEN (1 << 0) -#define STLINK_REG_DHCSR_C_HALT (1 << 1) -#define STLINK_REG_DHCSR_C_STEP (1 << 2) -#define STLINK_REG_DHCSR_C_MASKINTS (1 << 3) -#define STLINK_REG_DHCSR_S_REGRDY (1 << 16) -#define STLINK_REG_DHCSR_S_HALT (1 << 17) -#define STLINK_REG_DHCSR_S_SLEEP (1 << 18) -#define STLINK_REG_DHCSR_S_LOCKUP (1 << 19) -#define STLINK_REG_DHCSR_S_RETIRE_ST (1 << 24) -#define STLINK_REG_DHCSR_S_RESET_ST (1 << 25) -#define STLINK_REG_DCRSR 0xe000edf4 -#define STLINK_REG_DCRDR 0xe000edf8 +#define STLINK_REG_DFSR 0xE000ED30 +#define STLINK_REG_DFSR_HALT (1 << 0) +#define STLINK_REG_DFSR_BKPT (1 << 1) +#define STLINK_REG_DFSR_VCATCH (1 << 3) +#define STLINK_REG_DFSR_EXTERNAL (1 << 4) +#define STLINK_REG_DFSR_CLEAR 0x0000001F +#define STLINK_REG_DHCSR 0xe000edf0 +#define STLINK_REG_DHCSR_DBGKEY (0xA05F << 16) +#define STLINK_REG_DHCSR_C_DEBUGEN (1 << 0) +#define STLINK_REG_DHCSR_C_HALT (1 << 1) +#define STLINK_REG_DHCSR_C_STEP (1 << 2) +#define STLINK_REG_DHCSR_C_MASKINTS (1 << 3) +#define STLINK_REG_DHCSR_S_REGRDY (1 << 16) +#define STLINK_REG_DHCSR_S_HALT (1 << 17) +#define STLINK_REG_DHCSR_S_SLEEP (1 << 18) +#define STLINK_REG_DHCSR_S_LOCKUP (1 << 19) +#define STLINK_REG_DHCSR_S_RETIRE_ST (1 << 24) +#define STLINK_REG_DHCSR_S_RESET_ST (1 << 25) +#define STLINK_REG_DCRSR 0xe000edf4 +#define STLINK_REG_DCRDR 0xe000edf8 /* Application Interrupt and Reset Control Register */ -#define STLINK_REG_AIRCR 0xe000ed0c -#define STLINK_REG_AIRCR_VECTKEY 0x05fa0000 -#define STLINK_REG_AIRCR_SYSRESETREQ 0x00000004 -#define STLINK_REG_AIRCR_VECTRESET 0x00000001 +#define STLINK_REG_AIRCR 0xe000ed0c +#define STLINK_REG_AIRCR_VECTKEY 0x05fa0000 +#define STLINK_REG_AIRCR_SYSRESETREQ 0x00000004 +#define STLINK_REG_AIRCR_VECTRESET 0x00000001 /* ARM Cortex-M7 Processor Technical Reference Manual */ /* Cache Control and Status Register */ -#define STLINK_REG_CM7_CTR 0xE000ED7C -#define STLINK_REG_CM7_CLIDR 0xE000ED78 -#define STLINK_REG_CM7_CCR 0xE000ED14 -#define STLINK_REG_CM7_CCR_DC (1 << 16) -#define STLINK_REG_CM7_CCR_IC (1 << 17) -#define STLINK_REG_CM7_CSSELR 0xE000ED84 -#define STLINK_REG_CM7_DCCSW 0xE000EF6C -#define STLINK_REG_CM7_ICIALLU 0xE000EF50 -#define STLINK_REG_CM7_CCSIDR 0xE000ED80 +#define STLINK_REG_CM7_CTR 0xE000ED7C +#define STLINK_REG_CM7_CLIDR 0xE000ED78 +#define STLINK_REG_CM7_CCR 0xE000ED14 +#define STLINK_REG_CM7_CCR_DC (1 << 16) +#define STLINK_REG_CM7_CCR_IC (1 << 17) +#define STLINK_REG_CM7_CSSELR 0xE000ED84 +#define STLINK_REG_CM7_DCCSW 0xE000EF6C +#define STLINK_REG_CM7_ICIALLU 0xE000EF50 +#define STLINK_REG_CM7_CCSIDR 0xE000ED80 #endif // STLINK_REG_H_ From 373eee2cfebc410efc86b42524f84dc0dd536081 Mon Sep 17 00:00:00 2001 From: John Hall Date: Sat, 5 Dec 2020 10:25:14 -0800 Subject: [PATCH 148/503] Adding back has_dual_bank. Replacing flags field with has_swo_tracing. --- inc/backend.h | 2 +- inc/stlink.h | 6 ++- src/common.c | 5 ++- src/st-trace/trace.c | 2 +- src/stlink-lib/chipid.c | 99 +++++++++++++++++++++-------------------- src/stlink-lib/chipid.h | 5 +-- 6 files changed, 62 insertions(+), 57 deletions(-) diff --git a/inc/backend.h b/inc/backend.h index 6a0232849..ebd438127 100644 --- a/inc/backend.h +++ b/inc/backend.h @@ -28,7 +28,7 @@ int (*current_mode) (stlink_t * stl); int (*force_debug) (stlink_t *sl); int32_t (*target_voltage) (stlink_t *sl); - int (*set_swdclk) (stlink_t * stl, uint16_t divisor); + int (*set_swdclk) (stlink_t * stl, int freq_khz); int (*trace_enable) (stlink_t * sl, uint32_t frequency); int (*trace_disable) (stlink_t * sl); int (*trace_read) (stlink_t * sl, uint8_t* buf, size_t size); diff --git a/inc/stlink.h b/inc/stlink.h index 163d5d4b9..17c0bc6f4 100644 --- a/inc/stlink.h +++ b/inc/stlink.h @@ -220,7 +220,7 @@ struct _stlink { enum stlink_flash_type flash_type; // stlink_chipid_params.flash_type, set by stlink_load_device_params(), values: STLINK_FLASH_TYPE_xxx - uint32_t chip_flags; + bool has_dual_bank; stm32_addr_t flash_base; // STM32_FLASH_BASE, set by stlink_load_device_params() size_t flash_size; // calculated by stlink_load_device_params() @@ -234,6 +234,8 @@ struct _stlink { stm32_addr_t option_base; size_t option_size; + bool has_swo_tracing; + // bootloader // sys_base and sys_size are not used by the tools, but are only there to download the bootloader code // (see tests/sg.c) @@ -270,7 +272,7 @@ int stlink_step(stlink_t *sl); int stlink_current_mode(stlink_t *sl); int stlink_force_debug(stlink_t *sl); int stlink_target_voltage(stlink_t *sl); -int stlink_set_swdclk(stlink_t *sl, uint16_t divisor); +int stlink_set_swdclk(stlink_t *sl, int freq_khz); int stlink_trace_enable(stlink_t* sl, uint32_t frequency); int stlink_trace_disable(stlink_t* sl); int stlink_trace_read(stlink_t* sl, uint8_t* buf, size_t size); diff --git a/src/common.c b/src/common.c index 5e1e61e25..f2d68daf4 100644 --- a/src/common.c +++ b/src/common.c @@ -907,7 +907,7 @@ static void set_flash_cr_mer(stlink_t *sl, bool v, unsigned bank) { cr_reg = STM32Gx_FLASH_CR; cr_mer = (1 << STM32Gx_FLASH_CR_MER1); - if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { + if (sl->has_dual_bank) { cr_mer |= (1 << STM32Gx_FLASH_CR_MER2); } @@ -1355,13 +1355,14 @@ int stlink_load_device_params(stlink_t *sl) { } sl->flash_type = params->flash_type; - sl->chip_flags = params->flags; + sl->has_dual_bank = params->has_dual_bank; sl->flash_pgsz = params->flash_pagesize; sl->sram_size = params->sram_size; sl->sys_base = params->bootrom_base; sl->sys_size = params->bootrom_size; sl->option_base = params->option_base; sl->option_size = params->option_size; + sl->has_swo_tracing = params->has_swo_tracing; // medium and low devices have the same chipid. ram size depends on flash size. // STM32F100xx datasheet Doc ID 16455 Table 2 diff --git a/src/st-trace/trace.c b/src/st-trace/trace.c index 1356ceca0..6a5ccb91d 100644 --- a/src/st-trace/trace.c +++ b/src/st-trace/trace.c @@ -566,7 +566,7 @@ int main(int argc, char** argv) return APP_RESULT_STLINK_UNSUPPORTED_LINK; } - if (!(stlink->chip_flags & CHIP_F_HAS_SWO_TRACING)) { + if (!stlink->has_swo_tracing) { const struct stlink_chipid_params *params = stlink_chipid_get_params(stlink->chip_id); ELOG("We do not support SWO output for device '%s'\n", params->description); if (!settings.force) diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index 1a0c305c7..cb9276c93 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -14,7 +14,7 @@ static const struct stlink_chipid_params devices[] = { .bootrom_size = 0xEDC0, // ! @todo "System memory" byte size in hex from .option_base = STM32_F7_OPTION_BYTES_BASE, // Used for reading back the option bytes, writing uses FLASH_F7_OPTCR and FLASH_F7_OPTCR1 .option_size = 0x20, - .flags = CHIP_F_HAS_SWO_TRACING, + .has_swo_tracing = true, }, { // RM0385 and DS10916 document was used to find these paramaters @@ -26,7 +26,7 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0x50000, // "SRAM" byte size in hex from DS Fig 18 .bootrom_base = 0x00100000, // "System memory" starting address from DS Fig 18 .bootrom_size = 0xEDC0, // "System memory" byte size in hex from DS Fig 18 - .flags = CHIP_F_HAS_SWO_TRACING, + .has_swo_tracing = true, }, { // RM0431 and DS document was used to find these paramaters @@ -38,7 +38,7 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0x40000, // "SRAM" byte size in hex from DS Fig 24 .bootrom_base = 0x00100000, // "System memory" starting address from DS Fig 24 .bootrom_size = 0xEDC0, // "System memory" byte size in hex from DS Fig 24 - .flags = CHIP_F_HAS_SWO_TRACING, + .has_swo_tracing = true, }, { // table 2, PM0063 .chip_id = STLINK_CHIPID_STM32_F1_MEDIUM, @@ -49,7 +49,7 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0x5000, .bootrom_base = 0x1ffff000, .bootrom_size = 0x800, - .flags = CHIP_F_HAS_SWO_TRACING, + .has_swo_tracing = true, }, { // table 1, PM0059 .chip_id = STLINK_CHIPID_STM32_F2, @@ -62,7 +62,7 @@ static const struct stlink_chipid_params devices[] = { .bootrom_size = 0x7800, .option_base = 0x1FFFC000, .option_size = 4, - .flags = CHIP_F_HAS_SWO_TRACING, + .has_swo_tracing = true, }, { // PM0063 .chip_id = STLINK_CHIPID_STM32_F1_LOW, @@ -73,7 +73,7 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0x2800, .bootrom_base = 0x1ffff000, .bootrom_size = 0x800, - .flags = CHIP_F_HAS_SWO_TRACING, + .has_swo_tracing = true, }, { .chip_id = STLINK_CHIPID_STM32_F4, @@ -86,7 +86,7 @@ static const struct stlink_chipid_params devices[] = { .bootrom_size = 0x7800, .option_base = STM32_F4_OPTION_BYTES_BASE, .option_size = 4, - .flags = CHIP_F_HAS_SWO_TRACING, + .has_swo_tracing = true, }, { .chip_id = STLINK_CHIPID_STM32_F4_DSI, @@ -97,7 +97,7 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0x40000, .bootrom_base = 0x1fff0000, .bootrom_size = 0x7800, - .flags = CHIP_F_HAS_SWO_TRACING, + .has_swo_tracing = true, }, { .chip_id = STLINK_CHIPID_STM32_F4_HD, @@ -108,7 +108,7 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0x40000, .bootrom_base = 0x1fff0000, .bootrom_size = 0x7800, - .flags = CHIP_F_HAS_SWO_TRACING, + .has_swo_tracing = true, }, { .chip_id = STLINK_CHIPID_STM32_F4_LP, @@ -119,7 +119,7 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0x10000, .bootrom_base = 0x1fff0000, .bootrom_size = 0x7800, - .flags = CHIP_F_HAS_SWO_TRACING, + .has_swo_tracing = true, }, { .chip_id = STLINK_CHIPID_STM32_F411RE, @@ -130,7 +130,7 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0x20000, .bootrom_base = 0x1fff0000, .bootrom_size = 0x7800, - .flags = CHIP_F_HAS_SWO_TRACING, + .has_swo_tracing = true, }, { .chip_id = STLINK_CHIPID_STM32_F4_DE, @@ -141,7 +141,7 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0x18000, .bootrom_base = 0x1fff0000, .bootrom_size = 0x7800, - .flags = CHIP_F_HAS_SWO_TRACING, + .has_swo_tracing = true, }, { .chip_id = STLINK_CHIPID_STM32_F1_HIGH, @@ -152,7 +152,7 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0x10000, .bootrom_base = 0x1ffff000, .bootrom_size = 0x800, - .flags = CHIP_F_HAS_SWO_TRACING, + .has_swo_tracing = true, }, { // This ignores the EEPROM! (and uses the page erase size, @@ -165,7 +165,7 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0x4000, .bootrom_base = 0x1ff00000, .bootrom_size = 0x1000, - .flags = CHIP_F_HAS_SWO_TRACING, + .has_swo_tracing = true, }, { .chip_id = STLINK_CHIPID_STM32_L1_CAT2, @@ -176,7 +176,7 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0x8000, .bootrom_base = 0x1ff00000, .bootrom_size = 0x1000, - .flags = CHIP_F_HAS_SWO_TRACING, + .has_swo_tracing = true, }, { .chip_id = STLINK_CHIPID_STM32_L1_MEDIUM_PLUS, @@ -187,7 +187,7 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0x8000, // not completely clear if there are some with 48k .bootrom_base = 0x1ff00000, .bootrom_size = 0x1000, - .flags = CHIP_F_HAS_SWO_TRACING, + .has_swo_tracing = true, }, { .chip_id = STLINK_CHIPID_STM32_L1_HIGH, @@ -200,7 +200,7 @@ static const struct stlink_chipid_params devices[] = { .bootrom_size = 0x1000, .option_base = STM32_L1_OPTION_BYTES_BASE, .option_size = 8, - .flags = CHIP_F_HAS_SWO_TRACING, + .has_swo_tracing = true, }, { .chip_id = STLINK_CHIPID_STM32_L152_RE, @@ -211,7 +211,7 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0x14000, // not completely clear if there are some with 32k .bootrom_base = 0x1ff00000, .bootrom_size = 0x1000, - .flags = CHIP_F_HAS_SWO_TRACING, + .has_swo_tracing = true, }, { .chip_id = STLINK_CHIPID_STM32_F1_CONN, @@ -222,7 +222,7 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0x10000, .bootrom_base = 0x1fffb000, .bootrom_size = 0x4800, - .flags = CHIP_F_HAS_SWO_TRACING, + .has_swo_tracing = true, }, { // Low and Medium density VL have same chipid. RM0041 25.6.1 .chip_id = STLINK_CHIPID_STM32_F1_VL_MEDIUM_LOW, @@ -233,7 +233,7 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0x2000, // 0x1000 for low density devices .bootrom_base = 0x1ffff000, .bootrom_size = 0x800, - .flags = CHIP_F_HAS_SWO_TRACING, + .has_swo_tracing = true, }, { // STM32F446x family. Support based on DM00135183.pdf (RM0390) document. @@ -247,7 +247,7 @@ static const struct stlink_chipid_params devices[] = { .bootrom_size = 0x7800, .option_base = 0x1FFFC000, .option_size = 4, - .flags = CHIP_F_HAS_SWO_TRACING, + .has_swo_tracing = true, }, { // STM32F410 MCUs. Support based on DM00180366.pdf (RM0401) document. @@ -259,7 +259,7 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0x8000, .bootrom_base = 0x1fff0000, .bootrom_size = 0x7800, - .flags = CHIP_F_HAS_SWO_TRACING, + .has_swo_tracing = true, }, { // This is STK32F303VCT6 device from STM32 F3 Discovery board. @@ -272,7 +272,7 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0xa000, .bootrom_base = 0x1ffff000, .bootrom_size = 0x800, - .flags = CHIP_F_HAS_SWO_TRACING, + .has_swo_tracing = true, }, { // This is STK32F373VCT6 device from STM32 F373 eval board @@ -285,7 +285,7 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0xa000, .bootrom_base = 0x1ffff000, .bootrom_size = 0x800, - .flags = CHIP_F_HAS_SWO_TRACING, + .has_swo_tracing = true, }, { .chip_id = STLINK_CHIPID_STM32_F1_VL_HIGH, @@ -296,7 +296,7 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0x8000, .bootrom_base = 0x1ffff000, .bootrom_size = 0x800, - .flags = CHIP_F_HAS_SWO_TRACING, + .has_swo_tracing = true, }, { .chip_id = STLINK_CHIPID_STM32_F1_XL, @@ -307,7 +307,7 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0x18000, .bootrom_base = 0x1fffe000, .bootrom_size = 0x1800, - .flags = CHIP_F_HAS_SWO_TRACING, + .has_swo_tracing = true, }, { // Use this as an example for mapping future chips: @@ -319,7 +319,7 @@ static const struct stlink_chipid_params devices[] = { .flash_pagesize = 0x800, // Page sizes listed in Table 4 .sram_size = 0x4000, // "SRAM" byte size in hex from Table 2 .bootrom_base = 0x1fffC800, // "System memory" starting address from Table 2 - .bootrom_size = 0x3000 // "System memory" byte size in hex from Table 2 + .bootrom_size = 0x3000, // "System memory" byte size in hex from Table 2 }, { // Use this as an example for mapping future chips: @@ -331,7 +331,7 @@ static const struct stlink_chipid_params devices[] = { .flash_pagesize = 0x400, // Page sizes listed in Table 4 .sram_size = 0x2000, // "SRAM" byte size in hex from Table 2 .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2 - .bootrom_size = 0xC00 // "System memory" byte size in hex from Table 2 + .bootrom_size = 0xC00, // "System memory" byte size in hex from Table 2 }, { // RM0402 document was used to find these parameters @@ -344,7 +344,7 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0x40000, // "SRAM" byte size in hex from Table 4 .bootrom_base = 0x1FFF0000, // "System memory" starting address from Table 4 .bootrom_size = 0x7800, // "System memory" byte size in hex from Table 4 - .flags = CHIP_F_HAS_SWO_TRACING, + .has_swo_tracing = true, }, { // RM0430 DocID029473 Rev 2 document was used to find these parameters @@ -357,7 +357,7 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0x50000, // "SRAM" byte size in hex from Figure 2 (Table 4 only says 0x40000) .bootrom_base = 0x1FFF0000, // "System memory" starting address from Table 4 .bootrom_size = 0x7800, // "System memory" byte size in hex from Table 4 - .flags = CHIP_F_HAS_SWO_TRACING, + .has_swo_tracing = true, }, { .chip_id = STLINK_CHIPID_STM32_F09X, @@ -367,7 +367,7 @@ static const struct stlink_chipid_params devices[] = { .flash_pagesize = 0x800, // Page sizes listed in Table 4 (pg 56) .sram_size = 0x8000, // "SRAM" byte size in hex from Table 2 (pg 50) .bootrom_base = 0x1fffd800, // "System memory" starting address from Table 2 - .bootrom_size = 0x2000 // "System memory" byte size in hex from Table 2 + .bootrom_size = 0x2000, // "System memory" byte size in hex from Table 2 }, { // Use this as an example for mapping future chips: @@ -379,7 +379,7 @@ static const struct stlink_chipid_params devices[] = { .flash_pagesize = 0x400, // Page sizes listed in Table 4 .sram_size = 0x1800, // "SRAM" byte size in hex from Table 2 .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2 - .bootrom_size = 0xC00 // "System memory" byte size in hex from Table 2 + .bootrom_size = 0xC00, // "System memory" byte size in hex from Table 2 }, { // Use this as an example for mapping future chips: @@ -391,7 +391,7 @@ static const struct stlink_chipid_params devices[] = { .flash_pagesize = 0x400, // Page sizes listed in Table 4 .sram_size = 0x1000, // "SRAM" byte size in hex from Table 2 .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2 - .bootrom_size = 0xC00 // "System memory" byte size in hex from Table 2 + .bootrom_size = 0xC00, // "System memory" byte size in hex from Table 2 }, { // STM32F30x @@ -403,7 +403,7 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0xa000, .bootrom_base = 0x1fffd800, .bootrom_size = 0x2000, - .flags = CHIP_F_HAS_SWO_TRACING, + .has_swo_tracing = true, }, { // STM32L0x @@ -458,7 +458,7 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0x3000, .bootrom_base = 0x1fffd800, .bootrom_size = 0x2000, - .flags = CHIP_F_HAS_SWO_TRACING, + .has_swo_tracing = true, }, { // This is STK32F303RET6 device from STM32 F3 Nucelo board. @@ -471,7 +471,7 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0x10000, // 3.3 Embedded SRAM .bootrom_base = 0x1fffd800, // 3.3.2 / Table 4 System Memory .bootrom_size = 0x2000, - .flags = CHIP_F_HAS_SWO_TRACING, + .has_swo_tracing = true, }, { // STM32L4x6 @@ -490,7 +490,7 @@ static const struct stlink_chipid_params devices[] = { .bootrom_size = 0x7000, // 28k (per bank), same source as base .option_base = STM32_L4_OPTION_BYTES_BASE, .option_size = 4, - .flags = CHIP_F_HAS_SWO_TRACING, + .has_swo_tracing = true, }, { // STM32L4RX @@ -503,7 +503,7 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0xa0000, // 192k (SRAM1) + 64k SRAM2 + 384k SRAM3 = 640k, or 0xA0000 .bootrom_base = 0x1fff0000, // 3.3.1, pg 99 .bootrom_size = 0x7000, // 28k (per bank), same source as base (pg 99) - .flags = CHIP_F_HAS_SWO_TRACING, + .has_swo_tracing = true, }, { // STLINK_CHIPID_STM32_L41X @@ -518,7 +518,7 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0xa000, // 40k (DS12469, sec 3.5, page 18) .bootrom_base = 0x1fff0000, // System Memory (RM0394, sec 3.3.1, table 8) .bootrom_size = 0x7000, // 28k, same source as base - .flags = CHIP_F_HAS_SWO_TRACING, + .has_swo_tracing = true, }, { // STLINK_CHIPID_STM32_L43X @@ -537,7 +537,7 @@ static const struct stlink_chipid_params devices[] = { .bootrom_size = 0x7000, // 28k (per bank), same source as base .option_base = STM32_L4_OPTION_BYTES_BASE, .option_size = 4, - .flags = CHIP_F_HAS_SWO_TRACING, + .has_swo_tracing = true, }, { // STLINK_CHIPID_STM32_L496X @@ -554,7 +554,7 @@ static const struct stlink_chipid_params devices[] = { .bootrom_size = 0x7000, // 28k (per bank), same source as base .option_base = STM32_L4_OPTION_BYTES_BASE, .option_size = 4, - .flags = CHIP_F_HAS_SWO_TRACING, + .has_swo_tracing = true, }, { // STLINK_CHIPID_STM32_L46X @@ -570,7 +570,7 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0x20000, .bootrom_base = 0x1fff0000, // Tables 6, pages 71-72 (Bank 1 system memory, also fig 2 on page 63) .bootrom_size = 0x7000, // 28k (per bank), same source as base - .flags = CHIP_F_HAS_SWO_TRACING, + .has_swo_tracing = true, }, { // STM32L011 @@ -581,7 +581,7 @@ static const struct stlink_chipid_params devices[] = { .flash_pagesize = 0x80, .sram_size = 0x2000, .bootrom_base = 0x1ff00000, - .bootrom_size = 0x2000 + .bootrom_size = 0x2000, }, { // STM32G030/031/041 (from RM0454 & RM0444) @@ -624,13 +624,14 @@ static const struct stlink_chipid_params devices[] = { .bootrom_size = 0x7000, // 28k (table 2) .option_base = STM32_G4_OPTION_BYTES_BASE, .option_size = 4, - .flags = CHIP_F_HAS_SWO_TRACING, + .has_swo_tracing = true, }, { // STM32G471/473/474/483/484 (from RM0440) .chip_id = STLINK_CHIPID_STM32_G4_CAT3, .description = "G4 Category-3", .flash_type = STLINK_FLASH_TYPE_G4, + .has_dual_bank = true, .flash_size_reg = 0x1FFF75E0, // Section 47.2 .flash_pagesize = 0x800, // 2k (sec 3.3.1) // SRAM1 is 80k at 0x20000000 @@ -641,7 +642,7 @@ static const struct stlink_chipid_params devices[] = { .bootrom_size = 0x7000, // 28k (table 2) .option_base = STM32_G4_OPTION_BYTES_BASE, .option_size = 4, - .flags = CHIP_F_HAS_DUAL_BANK | CHIP_F_HAS_SWO_TRACING, + .has_swo_tracing = true, }, { // STM32WB55 (from RM0434) @@ -652,7 +653,8 @@ static const struct stlink_chipid_params devices[] = { .flash_pagesize = 0x1000, // 4k .sram_size = 0x40000, .bootrom_base = 0x1fff0000, // see the memory map - .bootrom_size = 0x7000 + .bootrom_size = 0x7000, + .has_swo_tracing = true, }, { // STM32H742/743/753 (from RM0433) @@ -667,7 +669,7 @@ static const struct stlink_chipid_params devices[] = { .bootrom_size = 0x20000, // "System memory" byte size in hex from Table 7 .option_base = STM32_H7_OPTION_BYTES_BASE, .option_size = 44, // FLASH_OPTSR_CUR to FLASH_BOOT_PRGR from Table 28 - .flags = CHIP_F_HAS_SWO_TRACING, + .has_swo_tracing = true, }, { // STM32H7A3/7B3 (from RM0455) @@ -682,6 +684,7 @@ static const struct stlink_chipid_params devices[] = { .bootrom_size = 0x20000, // "System memory" byte size in hex splitted to two banks (Table 12-14) .option_base = STM32_H7_OPTION_BYTES_BASE, .option_size = 44, + .has_swo_tracing = true, }, { // STM32H72x/H73x (from RM0468) @@ -695,6 +698,7 @@ static const struct stlink_chipid_params devices[] = { .bootrom_size = 0x20000, // "System memory" byte size in hex (Table 6) .option_base = STM32_H7_OPTION_BYTES_BASE, .option_size = 44, + .has_swo_tracing = true, }, { @@ -707,7 +711,6 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0x0, .bootrom_base = 0x0, .bootrom_size = 0x0, - .flags = 0, }, }; diff --git a/src/stlink-lib/chipid.h b/src/stlink-lib/chipid.h index 1b54fe140..aab22759c 100644 --- a/src/stlink-lib/chipid.h +++ b/src/stlink-lib/chipid.h @@ -69,15 +69,13 @@ enum stlink_stm32_chipids { STLINK_CHIPID_STM32_WB55 = 0x495 }; -#define CHIP_F_HAS_DUAL_BANK (1 << 0) -#define CHIP_F_HAS_SWO_TRACING (1 << 1) /** Chipid parameters */ struct stlink_chipid_params { uint32_t chip_id; char *description; enum stlink_flash_type flash_type; - uint32_t flags; + bool has_dual_bank; uint32_t flash_size_reg; uint32_t flash_pagesize; uint32_t sram_size; @@ -85,6 +83,7 @@ struct stlink_chipid_params { uint32_t bootrom_size; uint32_t option_base; uint32_t option_size; + bool has_swo_tracing; }; const struct stlink_chipid_params *stlink_chipid_get_params(uint32_t chipid); From 5d1f3198a4530ca87e6dc61e21fb259b0e6f8417 Mon Sep 17 00:00:00 2001 From: Ant-ON Date: Sun, 6 Dec 2020 14:09:59 +0500 Subject: [PATCH 149/503] Fix warning of narrowing issues --- src/stlink-lib/helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/stlink-lib/helper.c b/src/stlink-lib/helper.c index 8b2c8e8f7..32d9b6c8d 100644 --- a/src/stlink-lib/helper.c +++ b/src/stlink-lib/helper.c @@ -11,5 +11,5 @@ unsigned time_ms() { struct timeval tv; gettimeofday(&tv, NULL); - return (unsigned)tv.tv_sec * 1000 + tv.tv_usec / 1000; + return (unsigned)(tv.tv_sec * 1000 + tv.tv_usec / 1000); } From 3e9e2bb38a00e7dae1cc97c613a91d2e680cd589 Mon Sep 17 00:00:00 2001 From: John Hall Date: Sun, 6 Dec 2020 11:01:02 -0800 Subject: [PATCH 150/503] Adding back flag. --- inc/stlink.h | 6 +-- src/common.c | 2 +- src/st-trace/trace.c | 2 +- src/stlink-lib/chipid.c | 86 ++++++++++++++++++++--------------------- src/stlink-lib/chipid.h | 5 ++- 5 files changed, 52 insertions(+), 49 deletions(-) diff --git a/inc/stlink.h b/inc/stlink.h index 17c0bc6f4..b4fff334f 100644 --- a/inc/stlink.h +++ b/inc/stlink.h @@ -22,7 +22,7 @@ extern "C" { /* Max data transfer size */ // 6kB = max mem32_read block, 8kB sram -// #define Q_BUF_LEN 96 +// #define Q_BUF_LEN 96 #define Q_BUF_LEN (1024 * 100) // STLINK_DEBUG_RESETSYS, etc: @@ -234,8 +234,6 @@ struct _stlink { stm32_addr_t option_base; size_t option_size; - bool has_swo_tracing; - // bootloader // sys_base and sys_size are not used by the tools, but are only there to download the bootloader code // (see tests/sg.c) @@ -243,6 +241,8 @@ struct _stlink { size_t sys_size; // stlink_chipid_params.bootrom_size, set by stlink_load_device_params() struct stlink_version_ version; + + uint32_t chip_flags; // stlink_chipid_params.flags, set by stlink_load_device_params(), values: CHIP_F_xxx }; int stlink_enter_swd_mode(stlink_t *sl); diff --git a/src/common.c b/src/common.c index f2d68daf4..a9e907c60 100644 --- a/src/common.c +++ b/src/common.c @@ -1362,7 +1362,7 @@ int stlink_load_device_params(stlink_t *sl) { sl->sys_size = params->bootrom_size; sl->option_base = params->option_base; sl->option_size = params->option_size; - sl->has_swo_tracing = params->has_swo_tracing; + sl->chip_flags = params->flags; // medium and low devices have the same chipid. ram size depends on flash size. // STM32F100xx datasheet Doc ID 16455 Table 2 diff --git a/src/st-trace/trace.c b/src/st-trace/trace.c index 6a5ccb91d..1356ceca0 100644 --- a/src/st-trace/trace.c +++ b/src/st-trace/trace.c @@ -566,7 +566,7 @@ int main(int argc, char** argv) return APP_RESULT_STLINK_UNSUPPORTED_LINK; } - if (!stlink->has_swo_tracing) { + if (!(stlink->chip_flags & CHIP_F_HAS_SWO_TRACING)) { const struct stlink_chipid_params *params = stlink_chipid_get_params(stlink->chip_id); ELOG("We do not support SWO output for device '%s'\n", params->description); if (!settings.force) diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index cb9276c93..dc3218261 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -14,7 +14,7 @@ static const struct stlink_chipid_params devices[] = { .bootrom_size = 0xEDC0, // ! @todo "System memory" byte size in hex from .option_base = STM32_F7_OPTION_BYTES_BASE, // Used for reading back the option bytes, writing uses FLASH_F7_OPTCR and FLASH_F7_OPTCR1 .option_size = 0x20, - .has_swo_tracing = true, + .flags = CHIP_F_HAS_SWO_TRACING, }, { // RM0385 and DS10916 document was used to find these paramaters @@ -26,7 +26,7 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0x50000, // "SRAM" byte size in hex from DS Fig 18 .bootrom_base = 0x00100000, // "System memory" starting address from DS Fig 18 .bootrom_size = 0xEDC0, // "System memory" byte size in hex from DS Fig 18 - .has_swo_tracing = true, + .flags = CHIP_F_HAS_SWO_TRACING, }, { // RM0431 and DS document was used to find these paramaters @@ -38,7 +38,7 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0x40000, // "SRAM" byte size in hex from DS Fig 24 .bootrom_base = 0x00100000, // "System memory" starting address from DS Fig 24 .bootrom_size = 0xEDC0, // "System memory" byte size in hex from DS Fig 24 - .has_swo_tracing = true, + .flags = CHIP_F_HAS_SWO_TRACING, }, { // table 2, PM0063 .chip_id = STLINK_CHIPID_STM32_F1_MEDIUM, @@ -49,7 +49,7 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0x5000, .bootrom_base = 0x1ffff000, .bootrom_size = 0x800, - .has_swo_tracing = true, + .flags = CHIP_F_HAS_SWO_TRACING, }, { // table 1, PM0059 .chip_id = STLINK_CHIPID_STM32_F2, @@ -62,7 +62,7 @@ static const struct stlink_chipid_params devices[] = { .bootrom_size = 0x7800, .option_base = 0x1FFFC000, .option_size = 4, - .has_swo_tracing = true, + .flags = CHIP_F_HAS_SWO_TRACING, }, { // PM0063 .chip_id = STLINK_CHIPID_STM32_F1_LOW, @@ -73,7 +73,7 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0x2800, .bootrom_base = 0x1ffff000, .bootrom_size = 0x800, - .has_swo_tracing = true, + .flags = CHIP_F_HAS_SWO_TRACING, }, { .chip_id = STLINK_CHIPID_STM32_F4, @@ -86,7 +86,7 @@ static const struct stlink_chipid_params devices[] = { .bootrom_size = 0x7800, .option_base = STM32_F4_OPTION_BYTES_BASE, .option_size = 4, - .has_swo_tracing = true, + .flags = CHIP_F_HAS_SWO_TRACING, }, { .chip_id = STLINK_CHIPID_STM32_F4_DSI, @@ -97,7 +97,7 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0x40000, .bootrom_base = 0x1fff0000, .bootrom_size = 0x7800, - .has_swo_tracing = true, + .flags = CHIP_F_HAS_SWO_TRACING, }, { .chip_id = STLINK_CHIPID_STM32_F4_HD, @@ -108,7 +108,7 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0x40000, .bootrom_base = 0x1fff0000, .bootrom_size = 0x7800, - .has_swo_tracing = true, + .flags = CHIP_F_HAS_SWO_TRACING, }, { .chip_id = STLINK_CHIPID_STM32_F4_LP, @@ -119,7 +119,7 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0x10000, .bootrom_base = 0x1fff0000, .bootrom_size = 0x7800, - .has_swo_tracing = true, + .flags = CHIP_F_HAS_SWO_TRACING, }, { .chip_id = STLINK_CHIPID_STM32_F411RE, @@ -130,7 +130,7 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0x20000, .bootrom_base = 0x1fff0000, .bootrom_size = 0x7800, - .has_swo_tracing = true, + .flags = CHIP_F_HAS_SWO_TRACING, }, { .chip_id = STLINK_CHIPID_STM32_F4_DE, @@ -141,7 +141,7 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0x18000, .bootrom_base = 0x1fff0000, .bootrom_size = 0x7800, - .has_swo_tracing = true, + .flags = CHIP_F_HAS_SWO_TRACING, }, { .chip_id = STLINK_CHIPID_STM32_F1_HIGH, @@ -152,7 +152,7 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0x10000, .bootrom_base = 0x1ffff000, .bootrom_size = 0x800, - .has_swo_tracing = true, + .flags = CHIP_F_HAS_SWO_TRACING, }, { // This ignores the EEPROM! (and uses the page erase size, @@ -165,7 +165,7 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0x4000, .bootrom_base = 0x1ff00000, .bootrom_size = 0x1000, - .has_swo_tracing = true, + .flags = CHIP_F_HAS_SWO_TRACING, }, { .chip_id = STLINK_CHIPID_STM32_L1_CAT2, @@ -176,7 +176,7 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0x8000, .bootrom_base = 0x1ff00000, .bootrom_size = 0x1000, - .has_swo_tracing = true, + .flags = CHIP_F_HAS_SWO_TRACING, }, { .chip_id = STLINK_CHIPID_STM32_L1_MEDIUM_PLUS, @@ -187,7 +187,7 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0x8000, // not completely clear if there are some with 48k .bootrom_base = 0x1ff00000, .bootrom_size = 0x1000, - .has_swo_tracing = true, + .flags = CHIP_F_HAS_SWO_TRACING, }, { .chip_id = STLINK_CHIPID_STM32_L1_HIGH, @@ -200,7 +200,7 @@ static const struct stlink_chipid_params devices[] = { .bootrom_size = 0x1000, .option_base = STM32_L1_OPTION_BYTES_BASE, .option_size = 8, - .has_swo_tracing = true, + .flags = CHIP_F_HAS_SWO_TRACING, }, { .chip_id = STLINK_CHIPID_STM32_L152_RE, @@ -211,7 +211,7 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0x14000, // not completely clear if there are some with 32k .bootrom_base = 0x1ff00000, .bootrom_size = 0x1000, - .has_swo_tracing = true, + .flags = CHIP_F_HAS_SWO_TRACING, }, { .chip_id = STLINK_CHIPID_STM32_F1_CONN, @@ -222,7 +222,7 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0x10000, .bootrom_base = 0x1fffb000, .bootrom_size = 0x4800, - .has_swo_tracing = true, + .flags = CHIP_F_HAS_SWO_TRACING, }, { // Low and Medium density VL have same chipid. RM0041 25.6.1 .chip_id = STLINK_CHIPID_STM32_F1_VL_MEDIUM_LOW, @@ -233,7 +233,7 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0x2000, // 0x1000 for low density devices .bootrom_base = 0x1ffff000, .bootrom_size = 0x800, - .has_swo_tracing = true, + .flags = CHIP_F_HAS_SWO_TRACING, }, { // STM32F446x family. Support based on DM00135183.pdf (RM0390) document. @@ -247,7 +247,7 @@ static const struct stlink_chipid_params devices[] = { .bootrom_size = 0x7800, .option_base = 0x1FFFC000, .option_size = 4, - .has_swo_tracing = true, + .flags = CHIP_F_HAS_SWO_TRACING, }, { // STM32F410 MCUs. Support based on DM00180366.pdf (RM0401) document. @@ -259,7 +259,7 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0x8000, .bootrom_base = 0x1fff0000, .bootrom_size = 0x7800, - .has_swo_tracing = true, + .flags = CHIP_F_HAS_SWO_TRACING, }, { // This is STK32F303VCT6 device from STM32 F3 Discovery board. @@ -272,7 +272,7 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0xa000, .bootrom_base = 0x1ffff000, .bootrom_size = 0x800, - .has_swo_tracing = true, + .flags = CHIP_F_HAS_SWO_TRACING, }, { // This is STK32F373VCT6 device from STM32 F373 eval board @@ -285,7 +285,7 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0xa000, .bootrom_base = 0x1ffff000, .bootrom_size = 0x800, - .has_swo_tracing = true, + .flags = CHIP_F_HAS_SWO_TRACING, }, { .chip_id = STLINK_CHIPID_STM32_F1_VL_HIGH, @@ -296,7 +296,7 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0x8000, .bootrom_base = 0x1ffff000, .bootrom_size = 0x800, - .has_swo_tracing = true, + .flags = CHIP_F_HAS_SWO_TRACING, }, { .chip_id = STLINK_CHIPID_STM32_F1_XL, @@ -307,7 +307,7 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0x18000, .bootrom_base = 0x1fffe000, .bootrom_size = 0x1800, - .has_swo_tracing = true, + .flags = CHIP_F_HAS_SWO_TRACING, }, { // Use this as an example for mapping future chips: @@ -344,7 +344,7 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0x40000, // "SRAM" byte size in hex from Table 4 .bootrom_base = 0x1FFF0000, // "System memory" starting address from Table 4 .bootrom_size = 0x7800, // "System memory" byte size in hex from Table 4 - .has_swo_tracing = true, + .flags = CHIP_F_HAS_SWO_TRACING, }, { // RM0430 DocID029473 Rev 2 document was used to find these parameters @@ -357,7 +357,7 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0x50000, // "SRAM" byte size in hex from Figure 2 (Table 4 only says 0x40000) .bootrom_base = 0x1FFF0000, // "System memory" starting address from Table 4 .bootrom_size = 0x7800, // "System memory" byte size in hex from Table 4 - .has_swo_tracing = true, + .flags = CHIP_F_HAS_SWO_TRACING, }, { .chip_id = STLINK_CHIPID_STM32_F09X, @@ -403,7 +403,7 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0xa000, .bootrom_base = 0x1fffd800, .bootrom_size = 0x2000, - .has_swo_tracing = true, + .flags = CHIP_F_HAS_SWO_TRACING, }, { // STM32L0x @@ -458,7 +458,7 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0x3000, .bootrom_base = 0x1fffd800, .bootrom_size = 0x2000, - .has_swo_tracing = true, + .flags = CHIP_F_HAS_SWO_TRACING, }, { // This is STK32F303RET6 device from STM32 F3 Nucelo board. @@ -471,7 +471,7 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0x10000, // 3.3 Embedded SRAM .bootrom_base = 0x1fffd800, // 3.3.2 / Table 4 System Memory .bootrom_size = 0x2000, - .has_swo_tracing = true, + .flags = CHIP_F_HAS_SWO_TRACING, }, { // STM32L4x6 @@ -490,7 +490,7 @@ static const struct stlink_chipid_params devices[] = { .bootrom_size = 0x7000, // 28k (per bank), same source as base .option_base = STM32_L4_OPTION_BYTES_BASE, .option_size = 4, - .has_swo_tracing = true, + .flags = CHIP_F_HAS_SWO_TRACING, }, { // STM32L4RX @@ -503,7 +503,7 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0xa0000, // 192k (SRAM1) + 64k SRAM2 + 384k SRAM3 = 640k, or 0xA0000 .bootrom_base = 0x1fff0000, // 3.3.1, pg 99 .bootrom_size = 0x7000, // 28k (per bank), same source as base (pg 99) - .has_swo_tracing = true, + .flags = CHIP_F_HAS_SWO_TRACING, }, { // STLINK_CHIPID_STM32_L41X @@ -518,7 +518,7 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0xa000, // 40k (DS12469, sec 3.5, page 18) .bootrom_base = 0x1fff0000, // System Memory (RM0394, sec 3.3.1, table 8) .bootrom_size = 0x7000, // 28k, same source as base - .has_swo_tracing = true, + .flags = CHIP_F_HAS_SWO_TRACING, }, { // STLINK_CHIPID_STM32_L43X @@ -537,7 +537,7 @@ static const struct stlink_chipid_params devices[] = { .bootrom_size = 0x7000, // 28k (per bank), same source as base .option_base = STM32_L4_OPTION_BYTES_BASE, .option_size = 4, - .has_swo_tracing = true, + .flags = CHIP_F_HAS_SWO_TRACING, }, { // STLINK_CHIPID_STM32_L496X @@ -554,7 +554,7 @@ static const struct stlink_chipid_params devices[] = { .bootrom_size = 0x7000, // 28k (per bank), same source as base .option_base = STM32_L4_OPTION_BYTES_BASE, .option_size = 4, - .has_swo_tracing = true, + .flags = CHIP_F_HAS_SWO_TRACING, }, { // STLINK_CHIPID_STM32_L46X @@ -570,7 +570,7 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0x20000, .bootrom_base = 0x1fff0000, // Tables 6, pages 71-72 (Bank 1 system memory, also fig 2 on page 63) .bootrom_size = 0x7000, // 28k (per bank), same source as base - .has_swo_tracing = true, + .flags = CHIP_F_HAS_SWO_TRACING, }, { // STM32L011 @@ -624,7 +624,7 @@ static const struct stlink_chipid_params devices[] = { .bootrom_size = 0x7000, // 28k (table 2) .option_base = STM32_G4_OPTION_BYTES_BASE, .option_size = 4, - .has_swo_tracing = true, + .flags = CHIP_F_HAS_SWO_TRACING, }, { // STM32G471/473/474/483/484 (from RM0440) @@ -642,7 +642,7 @@ static const struct stlink_chipid_params devices[] = { .bootrom_size = 0x7000, // 28k (table 2) .option_base = STM32_G4_OPTION_BYTES_BASE, .option_size = 4, - .has_swo_tracing = true, + .flags = CHIP_F_HAS_SWO_TRACING, }, { // STM32WB55 (from RM0434) @@ -654,7 +654,7 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0x40000, .bootrom_base = 0x1fff0000, // see the memory map .bootrom_size = 0x7000, - .has_swo_tracing = true, + .flags = CHIP_F_HAS_SWO_TRACING, }, { // STM32H742/743/753 (from RM0433) @@ -669,7 +669,7 @@ static const struct stlink_chipid_params devices[] = { .bootrom_size = 0x20000, // "System memory" byte size in hex from Table 7 .option_base = STM32_H7_OPTION_BYTES_BASE, .option_size = 44, // FLASH_OPTSR_CUR to FLASH_BOOT_PRGR from Table 28 - .has_swo_tracing = true, + .flags = CHIP_F_HAS_SWO_TRACING, }, { // STM32H7A3/7B3 (from RM0455) @@ -684,7 +684,7 @@ static const struct stlink_chipid_params devices[] = { .bootrom_size = 0x20000, // "System memory" byte size in hex splitted to two banks (Table 12-14) .option_base = STM32_H7_OPTION_BYTES_BASE, .option_size = 44, - .has_swo_tracing = true, + .flags = CHIP_F_HAS_SWO_TRACING, }, { // STM32H72x/H73x (from RM0468) @@ -698,7 +698,7 @@ static const struct stlink_chipid_params devices[] = { .bootrom_size = 0x20000, // "System memory" byte size in hex (Table 6) .option_base = STM32_H7_OPTION_BYTES_BASE, .option_size = 44, - .has_swo_tracing = true, + .flags = CHIP_F_HAS_SWO_TRACING, }, { diff --git a/src/stlink-lib/chipid.h b/src/stlink-lib/chipid.h index aab22759c..5fee49f87 100644 --- a/src/stlink-lib/chipid.h +++ b/src/stlink-lib/chipid.h @@ -70,6 +70,9 @@ enum stlink_stm32_chipids { }; +#define CHIP_F_HAS_SWO_TRACING (1 << 0) + + /** Chipid parameters */ struct stlink_chipid_params { uint32_t chip_id; @@ -83,7 +86,7 @@ struct stlink_chipid_params { uint32_t bootrom_size; uint32_t option_base; uint32_t option_size; - bool has_swo_tracing; + uint32_t flags; }; const struct stlink_chipid_params *stlink_chipid_get_params(uint32_t chipid); From 67bf3906ef509e40c8ad909489701390cab2b89d Mon Sep 17 00:00:00 2001 From: John Hall Date: Sun, 6 Dec 2020 15:56:40 -0800 Subject: [PATCH 151/503] Fixing funcation naming convention. --- src/st-trace/trace.c | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/src/st-trace/trace.c b/src/st-trace/trace.c index 1356ceca0..450e7c598 100644 --- a/src/st-trace/trace.c +++ b/src/st-trace/trace.c @@ -242,7 +242,7 @@ bool parse_options(int argc, char** argv, st_settings_t *settings) { return true; } -static void ConvertSerialNumberTextToBinary(const char* text, char binary_out[STLINK_SERIAL_MAX_SIZE]) { +static void convert_serial_number_text_to_binary(const char* text, char binary_out[STLINK_SERIAL_MAX_SIZE]) { size_t length = 0; for (uint32_t n = 0; n < strlen(text) && length < STLINK_SERIAL_MAX_SIZE; n += 2) { char buffer[3] = { 0 }; @@ -251,11 +251,11 @@ static void ConvertSerialNumberTextToBinary(const char* text, char binary_out[ST } } -static stlink_t* StLinkConnect(const st_settings_t* settings) { +static stlink_t* stlink_connect(const st_settings_t* settings) { if (settings->serial_number) { // Open this specific stlink. char binary_serial_number[STLINK_SERIAL_MAX_SIZE] = { 0 }; - ConvertSerialNumberTextToBinary(settings->serial_number, binary_serial_number); + convert_serial_number_text_to_binary(settings->serial_number, binary_serial_number); return stlink_open_usb(settings->logging_level, false, binary_serial_number, 0); } else { // Otherwise, open any stlink. @@ -263,7 +263,7 @@ static stlink_t* StLinkConnect(const st_settings_t* settings) { } } -static bool EnableTrace(stlink_t* stlink, const st_settings_t* settings, uint32_t trace_frequency) { +static bool enable_trace(stlink_t* stlink, const st_settings_t* settings, uint32_t trace_frequency) { if (stlink_force_debug(stlink)) { ELOG("Unable to debug device\n"); @@ -334,7 +334,7 @@ static bool EnableTrace(stlink_t* stlink, const st_settings_t* settings, uint32_ return true; } -static trace_state UpdateTraceIdle(st_trace_t* trace, uint8_t c) { +static trace_state update_trace_idle(st_trace_t* trace, uint8_t c) { // Handle a trace byte when we are in the idle state. if (TRACE_OP_IS_TARGET_SOURCE(c)) { @@ -375,7 +375,7 @@ static trace_state UpdateTraceIdle(st_trace_t* trace, uint8_t c) { return TRACE_OP_GET_CONTINUATION(c) ? TRACE_STATE_SKIP_FRAME : TRACE_STATE_IDLE; } -static trace_state UpdateTrace(st_trace_t* trace, uint8_t c) { +static trace_state update_trace(st_trace_t* trace, uint8_t c) { trace->count_raw_bytes++; // Parse the input using a state machine. @@ -388,7 +388,7 @@ static trace_state UpdateTrace(st_trace_t* trace, uint8_t c) { switch (trace->state) { case TRACE_STATE_IDLE: - return UpdateTraceIdle(trace, c); + return update_trace_idle(trace, c); case TRACE_STATE_TARGET_SOURCE: putchar(c); @@ -421,7 +421,7 @@ static trace_state UpdateTrace(st_trace_t* trace, uint8_t c) { } } -static bool ReadTrace(stlink_t* stlink, st_trace_t* trace) { +static bool read_trace(stlink_t* stlink, st_trace_t* trace) { uint8_t buffer[STLINK_TRACE_BUF_LEN]; int length = stlink_trace_read(stlink, buffer, sizeof(buffer)); @@ -444,13 +444,13 @@ static bool ReadTrace(stlink_t* stlink, st_trace_t* trace) { } for (int i = 0; i < length; i++) { - trace->state = UpdateTrace(trace, buffer[i]); + trace->state = update_trace(trace, buffer[i]); } return true; } -static void CheckForConfigurationError(stlink_t* stlink, st_trace_t* trace, uint32_t trace_frequency) { +static void check_for_configuration_error(stlink_t* stlink, st_trace_t* trace, uint32_t trace_frequency) { // Only check configuration one time after the first 10 seconds of running. uint32_t elapsed_time_s = time(NULL) - trace->start_time; if (trace->configuration_checked || elapsed_time_s < 10) { @@ -546,7 +546,7 @@ int main(int argc, char** argv) return APP_RESULT_SUCCESS; } - stlink_t* stlink = StLinkConnect(&settings); + stlink_t* stlink = stlink_connect(&settings); if (!stlink) { ELOG("Unable to locate an stlink\n"); return APP_RESULT_STLINK_NOT_FOUND; @@ -582,7 +582,7 @@ int main(int argc, char** argv) return APP_RESULT_UNSUPPORTED_TRACE_FREQUENCY; } - if (!EnableTrace(stlink, &settings, trace_frequency)) { + if (!enable_trace(stlink, &settings, trace_frequency)) { ELOG("Unable to enable trace mode\n"); if (!settings.force) return APP_RESULT_STLINK_STATE_ERROR; @@ -598,8 +598,8 @@ int main(int argc, char** argv) return APP_RESULT_STLINK_STATE_ERROR; } - while (!g_abort_trace && ReadTrace(stlink, &trace)) { - CheckForConfigurationError(stlink, &trace, trace_frequency); + while (!g_abort_trace && read_trace(stlink, &trace)) { + check_for_configuration_error(stlink, &trace, trace_frequency); } stlink_trace_disable(stlink); From 7db0477d8f3da330d429da5ea12fde7cd4a09b7e Mon Sep 17 00:00:00 2001 From: John Hall Date: Sun, 6 Dec 2020 16:01:41 -0800 Subject: [PATCH 152/503] Adding windows signal handler type behavior. --- src/st-trace/trace.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/src/st-trace/trace.c b/src/st-trace/trace.c index 450e7c598..63003df58 100644 --- a/src/st-trace/trace.c +++ b/src/st-trace/trace.c @@ -148,6 +148,13 @@ static void abort_trace() { g_abort_trace = true; } +#if defined(_WIN32) +BOOL WINAPI CtrlHandler(DWORD fdwCtrlType) { + abort_trace(); + return FALSE; +} +#endif + static void usage(void) { puts("st-trace - usage:"); puts(" -h, --help Print this help"); @@ -516,10 +523,15 @@ static void check_for_configuration_error(stlink_t* stlink, st_trace_t* trace, u int main(int argc, char** argv) { +#if defined(_WIN32) + SetConsoleCtrlHandler((PHANDLER_ROUTINE)abort_trace, TRUE); +#else signal(SIGINT, &abort_trace); signal(SIGTERM, &abort_trace); signal(SIGSEGV, &abort_trace); signal(SIGPIPE, &abort_trace); +#endif + st_settings_t settings; if (!parse_options(argc, argv, &settings)) { From dc9726cd06bfbe695993951d78943b064560a8bb Mon Sep 17 00:00:00 2001 From: John Hall Date: Mon, 7 Dec 2020 09:02:00 -0800 Subject: [PATCH 153/503] Set abort routine wrong in windows. Found in code review. --- src/st-trace/trace.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/st-trace/trace.c b/src/st-trace/trace.c index 63003df58..a01f0c522 100644 --- a/src/st-trace/trace.c +++ b/src/st-trace/trace.c @@ -524,7 +524,7 @@ static void check_for_configuration_error(stlink_t* stlink, st_trace_t* trace, u int main(int argc, char** argv) { #if defined(_WIN32) - SetConsoleCtrlHandler((PHANDLER_ROUTINE)abort_trace, TRUE); + SetConsoleCtrlHandler((PHANDLER_ROUTINE)CtrlHandler, TRUE); #else signal(SIGINT, &abort_trace); signal(SIGTERM, &abort_trace); From d1a9fd85e097ce0f03699b3b163fcc96c35e4d57 Mon Sep 17 00:00:00 2001 From: John Hall Date: Mon, 7 Dec 2020 10:12:23 -0800 Subject: [PATCH 154/503] Moved register definitions to common reg.h file. --- inc/stlink.h | 22 -------- src/st-trace/trace.c | 126 +++++++++++++------------------------------ src/stlink-lib/reg.h | 52 +++++++++++++++++- 3 files changed, 89 insertions(+), 111 deletions(-) diff --git a/inc/stlink.h b/inc/stlink.h index b4fff334f..ef61fd1ba 100644 --- a/inc/stlink.h +++ b/inc/stlink.h @@ -88,28 +88,6 @@ enum target_state { #define STLINK_V3_MAX_TRACE_FREQUENCY 24000000 #define STLINK_DEFAULT_TRACE_FREQUENCY 2000000 -/* Cortex Debug Control Block */ -#define DCB_DHCSR 0xE000EDF0 -#define DCB_DCRSR 0xE000EDF4 -#define DCB_DCRDR 0xE000EDF8 -#define DCB_DEMCR 0xE000EDFC - -/* DCB_DHCSR bit and field definitions */ -#define DBGKEY (0xA05F << 16) -#define C_DEBUGEN (1 << 0) -#define C_HALT (1 << 1) -#define C_STEP (1 << 2) -#define C_MASKINTS (1 << 3) -#define S_REGRDY (1 << 16) -#define S_HALT (1 << 17) -#define S_SLEEP (1 << 18) -#define S_LOCKUP (1 << 19) -#define S_RETIRE_ST (1 << 24) -#define S_RESET_ST (1 << 25) - -/* DCB_DEMCR field definitions */ -#define DEMCR_TRCENA (1 << 24) - /* Map the relevant features, quirks and workaround for specific firmware version of stlink */ #define STLINK_F_HAS_TRACE (1 << 0) #define STLINK_F_HAS_SWD_SET_FREQ (1 << 1) diff --git a/src/st-trace/trace.c b/src/st-trace/trace.c index a01f0c522..7f586c7c2 100644 --- a/src/st-trace/trace.c +++ b/src/st-trace/trace.c @@ -10,6 +10,7 @@ #include #include +#include #include @@ -39,66 +40,6 @@ #define TRACE_OP_GET_SW_SOURCE_ADDR(c) ((c) >> 3) -// TODO: Ideally all register and field definitions would be in a common header file. - -// Instrumentation Trace Macrocell (ITM) Registers -#define ITM_TER 0xE0000E00 // ITM Trace Enable Register -#define ITM_TPR 0xE0000E40 // ITM Trace Privilege Register -#define ITM_TCR 0xE0000E80 // ITM Trace Control Register -#define ITM_TCC 0xE0000E90 // ITM Trace Cycle Count -#define ITM_LAR 0xE0000FB0 // ITM Lock Access Register - -// ITM field definitions -#define ITM_TER_PORTS_ALL (0xFFFFFFFF) -#define ITM_TPR_PORTS_ALL (0x0F) -#define ITM_TCR_TRACE_BUS_ID_1 (0x01 << 16) -#define ITM_TCR_SWO_ENA (1 << 4) -#define ITM_TCR_DWT_ENA (1 << 3) -#define ITM_TCR_SYNC_ENA (1 << 2) -#define ITM_TCR_TS_ENA (1 << 1) -#define ITM_TCR_ITM_ENA (1 << 0) -#define ITM_LAR_KEY 0xC5ACCE55 - -// Data Watchpoint and Trace (DWT) Registers -#define DWT_CTRL 0xE0001000 // DWT Control Register -#define DWT_FUNCTION0 0xE0001028 // DWT Function Register 0 -#define DWT_FUNCTION1 0xE0001038 // DWT Function Register 1 -#define DWT_FUNCTION2 0xE0001048 // DWT Function Register 2 -#define DWT_FUNCTION3 0xE0001058 // DWT Function Register 3 - -// DWT field definitions -#define DWT_CTRL_NUM_COMP (1 << 28) -#define DWT_CTRL_CYC_TAP (1 << 9) -#define DWT_CTRL_POST_INIT (1 << 5) -#define DWT_CTRL_POST_PRESET (1 << 1) -#define DWT_CTRL_CYCCNT_ENA (1 << 0) - -// Trace Port Interface (TPI) Registers -#define TPI_CSPSR 0xE0040004 // TPI Current Parallel Port Size Register -#define TPI_ACPR 0xE0040010 // TPI Asynchronous Clock Prescaler Register -#define TPI_SPPR 0xE00400F0 // TPI Selected Pin Protocol Register -#define TPI_FFCR 0xE0040304 // TPI Formatter and Flush Control Register - -// TPI field definitions -#define TPI_TPI_CSPSR_PORT_SIZE_1 (0x01 << 0) -#define TPI_SPPR_SWO_MANCHESTER (0x01 << 0) -#define TPI_SPPR_SWO_NRZ (0x02 << 0) -#define TPI_FFCR_TRIG_IN (0x01 << 8) -#define TPI_ACPR_MAX (0x1FFF) - -// Other Registers -#define FP_CTRL 0xE0002000 // Flash Patch Control Register -#define DBGMCU_CR 0xE0042004 // Debug MCU Configuration Register - -// Other register field definitions -#define FP_CTRL_KEY (1 << 1) -#define DBGMCU_CR_DBG_SLEEP (1 << 0) -#define DBGMCU_CR_DBG_STOP (1 << 1) -#define DBGMCU_CR_DBG_STANDBY (1 << 2) -#define DBGMCU_CR_TRACE_IOEN (1 << 5) -#define DBGMCU_CR_TRACE_MODE_ASYNC (0x00 << 6) - - typedef struct { bool show_help; bool show_version; @@ -284,17 +225,22 @@ static bool enable_trace(stlink_t* stlink, const st_settings_t* settings, uint32 return false; } - stlink_write_debug32(stlink, DCB_DHCSR, DBGKEY | C_DEBUGEN | C_HALT); - stlink_write_debug32(stlink, DCB_DEMCR, DEMCR_TRCENA); - stlink_write_debug32(stlink, FP_CTRL, FP_CTRL_KEY); - stlink_write_debug32(stlink, DWT_FUNCTION0, 0); - stlink_write_debug32(stlink, DWT_FUNCTION1, 0); - stlink_write_debug32(stlink, DWT_FUNCTION2, 0); - stlink_write_debug32(stlink, DWT_FUNCTION3, 0); - stlink_write_debug32(stlink, DWT_CTRL, 0); - stlink_write_debug32(stlink, DBGMCU_CR, DBGMCU_CR_DBG_SLEEP | DBGMCU_CR_DBG_STOP | - DBGMCU_CR_DBG_STANDBY | DBGMCU_CR_TRACE_IOEN | - DBGMCU_CR_TRACE_MODE_ASYNC); // Enable async tracing + + stlink_write_debug32(stlink, STLINK_REG_DHCSR, STLINK_REG_DHCSR_DBGKEY | + STLINK_REG_DHCSR_C_DEBUGEN | + STLINK_REG_DHCSR_C_HALT); + stlink_write_debug32(stlink, STLINK_REG_DEMCR, STLINK_REG_DEMCR_TRCENA); + stlink_write_debug32(stlink, STLINK_REG_CM3_FP_CTRL, STLINK_REG_CM3_FP_CTRL_KEY); + stlink_write_debug32(stlink, STLINK_REG_DWT_FUNCTION0, 0); + stlink_write_debug32(stlink, STLINK_REG_DWT_FUNCTION1, 0); + stlink_write_debug32(stlink, STLINK_REG_DWT_FUNCTION2, 0); + stlink_write_debug32(stlink, STLINK_REG_DWT_FUNCTION3, 0); + stlink_write_debug32(stlink, STLINK_REG_DWT_CTRL, 0); + stlink_write_debug32(stlink, STLINK_REG_DBGMCU_CR, STLINK_REG_DBGMCU_CR_DBG_SLEEP | + STLINK_REG_DBGMCU_CR_DBG_STOP | + STLINK_REG_DBGMCU_CR_DBG_STANDBY | + STLINK_REG_DBGMCU_CR_TRACE_IOEN | + STLINK_REG_DBGMCU_CR_TRACE_MODE_ASYNC); if (stlink_trace_enable(stlink, trace_frequency)) { ELOG("Unable to turn on tracing in stlink\n"); @@ -302,31 +248,35 @@ static bool enable_trace(stlink_t* stlink, const st_settings_t* settings, uint32 return false; } - stlink_write_debug32(stlink, TPI_CSPSR, TPI_TPI_CSPSR_PORT_SIZE_1); + stlink_write_debug32(stlink, STLINK_REG_TPI_CSPSR, STLINK_REG_TPI_CSPSR_PORT_SIZE_1); if (settings->core_frequency) { uint32_t prescaler = settings->core_frequency / trace_frequency - 1; - if (prescaler > TPI_ACPR_MAX) { + if (prescaler > STLINK_REG_TPI_ACPR_MAX) { ELOG("Trace frequency prescaler %d out of range. Try setting a faster trace frequency.\n", prescaler); if (!settings->force) return false; } - stlink_write_debug32(stlink, TPI_ACPR, prescaler); // Set TPIU_ACPR clock divisor - } - stlink_write_debug32(stlink, TPI_FFCR, TPI_FFCR_TRIG_IN); - stlink_write_debug32(stlink, TPI_SPPR, TPI_SPPR_SWO_NRZ); - stlink_write_debug32(stlink, ITM_LAR, ITM_LAR_KEY); - stlink_write_debug32(stlink, ITM_TCC, 0x00000400); // Set sync counter - stlink_write_debug32(stlink, ITM_TCR, ITM_TCR_TRACE_BUS_ID_1 | ITM_TCR_TS_ENA | ITM_TCR_ITM_ENA); - stlink_write_debug32(stlink, ITM_TER, ITM_TER_PORTS_ALL); - stlink_write_debug32(stlink, ITM_TPR, ITM_TPR_PORTS_ALL); - stlink_write_debug32(stlink, DWT_CTRL, 4 * DWT_CTRL_NUM_COMP | DWT_CTRL_CYC_TAP | - 0xF * DWT_CTRL_POST_INIT | 0xF * DWT_CTRL_POST_PRESET | - DWT_CTRL_CYCCNT_ENA); - stlink_write_debug32(stlink, DCB_DEMCR, DEMCR_TRCENA); + stlink_write_debug32(stlink, STLINK_REG_TPI_ACPR, prescaler); // Set TPIU_ACPR clock divisor + } + stlink_write_debug32(stlink, STLINK_REG_TPI_FFCR, STLINK_REG_TPI_FFCR_TRIG_IN); + stlink_write_debug32(stlink, STLINK_REG_TPI_SPPR, STLINK_REG_TPI_SPPR_SWO_NRZ); + stlink_write_debug32(stlink, STLINK_REG_ITM_LAR, STLINK_REG_ITM_LAR_KEY); + stlink_write_debug32(stlink, STLINK_REG_ITM_TCC, 0x00000400); // Set sync counter + stlink_write_debug32(stlink, STLINK_REG_ITM_TCR, STLINK_REG_ITM_TCR_TRACE_BUS_ID_1 | + STLINK_REG_ITM_TCR_TS_ENA | + STLINK_REG_ITM_TCR_ITM_ENA); + stlink_write_debug32(stlink, STLINK_REG_ITM_TER, STLINK_REG_ITM_TER_PORTS_ALL); + stlink_write_debug32(stlink, STLINK_REG_ITM_TPR, STLINK_REG_ITM_TPR_PORTS_ALL); + stlink_write_debug32(stlink, STLINK_REG_DWT_CTRL, 4 * STLINK_REG_DWT_CTRL_NUM_COMP | + STLINK_REG_DWT_CTRL_CYC_TAP | + 0xF * STLINK_REG_DWT_CTRL_POST_INIT | + 0xF * STLINK_REG_DWT_CTRL_POST_PRESET | + STLINK_REG_DWT_CTRL_CYCCNT_ENA); + stlink_write_debug32(stlink, STLINK_REG_DEMCR, STLINK_REG_DEMCR_TRCENA); uint32_t prescaler; - stlink_read_debug32(stlink, TPI_ACPR, &prescaler); + stlink_read_debug32(stlink, STLINK_REG_TPI_ACPR_MAX, &prescaler); if (prescaler) { uint32_t system_clock_speed = (prescaler + 1) * trace_frequency; uint32_t system_clock_speed_mhz = (system_clock_speed + 500000) / 1000000; @@ -483,7 +433,7 @@ static void check_for_configuration_error(stlink_t* stlink, st_trace_t* trace, u if (error_no_data || error_low_data || error_bad_data) { uint32_t prescaler; - stlink_read_debug32(stlink, TPI_ACPR, &prescaler); + stlink_read_debug32(stlink, STLINK_REG_TPI_ACPR, &prescaler); if (prescaler) { uint32_t system_clock_speed = (prescaler + 1) * trace_frequency; uint32_t system_clock_speed_mhz = (system_clock_speed + 500000) / 1000000; diff --git a/src/stlink-lib/reg.h b/src/stlink-lib/reg.h index fdea175d3..6d2c9f1af 100644 --- a/src/stlink-lib/reg.h +++ b/src/stlink-lib/reg.h @@ -3,8 +3,9 @@ #define STLINK_REG_CM3_CPUID 0xE000ED00 -#define STLINK_REG_CM3_FP_CTRL 0xE0002000 +#define STLINK_REG_CM3_FP_CTRL 0xE0002000 // Flash Patch Control Register #define STLINK_REG_CM3_FP_COMPn(n) (0xE0002008 + n*4) +#define STLINK_REG_CM3_FP_CTRL_KEY (1 << 1) #define STLINK_REG_CM7_FP_LAR 0xE0000FB0 #define STLINK_REG_CM7_FP_LAR_KEY 0xC5ACCE55 @@ -39,6 +40,55 @@ #define STLINK_REG_DHCSR_S_RESET_ST (1 << 25) #define STLINK_REG_DCRSR 0xe000edf4 #define STLINK_REG_DCRDR 0xe000edf8 +#define STLINK_REG_DEMCR 0xe000edfc +#define STLINK_REG_DEMCR_TRCENA (1 << 24) + +/* MCU Debug Component Registers */ +#define STLINK_REG_DBGMCU_CR 0xE0042004 // Debug MCU Configuration Register +#define STLINK_REG_DBGMCU_CR_DBG_SLEEP (1 << 0) +#define STLINK_REG_DBGMCU_CR_DBG_STOP (1 << 1) +#define STLINK_REG_DBGMCU_CR_DBG_STANDBY (1 << 2) +#define STLINK_REG_DBGMCU_CR_TRACE_IOEN (1 << 5) +#define STLINK_REG_DBGMCU_CR_TRACE_MODE_ASYNC (0x00 << 6) + +/* Data Watchpoint and Trace (DWT) Registers */ +#define STLINK_REG_DWT_CTRL 0xE0001000 // DWT Control Register +#define STLINK_REG_DWT_CTRL_NUM_COMP (1 << 28) +#define STLINK_REG_DWT_CTRL_CYC_TAP (1 << 9) +#define STLINK_REG_DWT_CTRL_POST_INIT (1 << 5) +#define STLINK_REG_DWT_CTRL_POST_PRESET (1 << 1) +#define STLINK_REG_DWT_CTRL_CYCCNT_ENA (1 << 0) +#define STLINK_REG_DWT_FUNCTION0 0xE0001028 // DWT Function Register 0 +#define STLINK_REG_DWT_FUNCTION1 0xE0001038 // DWT Function Register 1 +#define STLINK_REG_DWT_FUNCTION2 0xE0001048 // DWT Function Register 2 +#define STLINK_REG_DWT_FUNCTION3 0xE0001058 // DWT Function Register 3 + +/* Instrumentation Trace Macrocell (ITM) Registers */ +#define STLINK_REG_ITM_TER 0xE0000E00 // ITM Trace Enable Register +#define STLINK_REG_ITM_TER_PORTS_ALL (0xFFFFFFFF) +#define STLINK_REG_ITM_TPR 0xE0000E40 // ITM Trace Privilege Register +#define STLINK_REG_ITM_TPR_PORTS_ALL (0x0F) +#define STLINK_REG_ITM_TCR 0xE0000E80 // ITM Trace Control Register +#define STLINK_REG_ITM_TCR_TRACE_BUS_ID_1 (0x01 << 16) +#define STLINK_REG_ITM_TCR_SWO_ENA (1 << 4) +#define STLINK_REG_ITM_TCR_DWT_ENA (1 << 3) +#define STLINK_REG_ITM_TCR_SYNC_ENA (1 << 2) +#define STLINK_REG_ITM_TCR_TS_ENA (1 << 1) +#define STLINK_REG_ITM_TCR_ITM_ENA (1 << 0) +#define STLINK_REG_ITM_TCC 0xE0000E90 // ITM Trace Cycle Count +#define STLINK_REG_ITM_LAR 0xE0000FB0 // ITM Lock Access Register +#define STLINK_REG_ITM_LAR_KEY 0xC5ACCE55 + +/* Trace Port Interface (TPI) Registers */ +#define STLINK_REG_TPI_CSPSR 0xE0040004 // TPI Current Parallel Port Size Reg +#define STLINK_REG_TPI_CSPSR_PORT_SIZE_1 (0x01 << 0) +#define STLINK_REG_TPI_ACPR 0xE0040010 // TPI Async Clock Prescaler Register +#define STLINK_REG_TPI_ACPR_MAX (0x1FFF) +#define STLINK_REG_TPI_SPPR 0xE00400F0 // TPI Selected Pin Protocol Register +#define STLINK_REG_TPI_SPPR_SWO_MANCHESTER (0x01 << 0) +#define STLINK_REG_TPI_SPPR_SWO_NRZ (0x02 << 0) +#define STLINK_REG_TPI_FFCR 0xE0040304 // TPI Formatter and Flush Control Register +#define STLINK_REG_TPI_FFCR_TRIG_IN (0x01 << 8) /* Application Interrupt and Reset Control Register */ #define STLINK_REG_AIRCR 0xe000ed0c From 08a8474e3dea10a12a9f9b21885b8cdee0bb4a7a Mon Sep 17 00:00:00 2001 From: John Hall Date: Mon, 7 Dec 2020 10:52:23 -0800 Subject: [PATCH 155/503] Removing unused variable warning. --- src/st-trace/trace.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/st-trace/trace.c b/src/st-trace/trace.c index 7f586c7c2..7b31900a2 100644 --- a/src/st-trace/trace.c +++ b/src/st-trace/trace.c @@ -91,6 +91,7 @@ static void abort_trace() { #if defined(_WIN32) BOOL WINAPI CtrlHandler(DWORD fdwCtrlType) { + (void)fdwCtrlType; abort_trace(); return FALSE; } From d5c63c3b111381d6d58d47f8f05ccc485fa1c494 Mon Sep 17 00:00:00 2001 From: John Hall Date: Mon, 7 Dec 2020 11:06:59 -0800 Subject: [PATCH 156/503] Moving has_dual_bank into the flags field. --- inc/stlink.h | 1 - src/common.c | 34 +++++++++++++++++----------------- src/stlink-lib/chipid.c | 9 +++------ src/stlink-lib/chipid.h | 4 ++-- 4 files changed, 22 insertions(+), 26 deletions(-) diff --git a/inc/stlink.h b/inc/stlink.h index ef61fd1ba..d66cd74fb 100644 --- a/inc/stlink.h +++ b/inc/stlink.h @@ -198,7 +198,6 @@ struct _stlink { enum stlink_flash_type flash_type; // stlink_chipid_params.flash_type, set by stlink_load_device_params(), values: STLINK_FLASH_TYPE_xxx - bool has_dual_bank; stm32_addr_t flash_base; // STM32_FLASH_BASE, set by stlink_load_device_params() size_t flash_size; // calculated by stlink_load_device_params() diff --git a/src/common.c b/src/common.c index a9e907c60..ec9f19b4a 100644 --- a/src/common.c +++ b/src/common.c @@ -511,7 +511,7 @@ static void unlock_flash(stlink_t *sl) { key_reg = STM32WB_FLASH_KEYR; } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { key_reg = FLASH_H7_KEYR1; - if (sl->has_dual_bank) { + if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { key2_reg = FLASH_H7_KEYR2; } } else { @@ -575,7 +575,7 @@ static void lock_flash(stlink_t *sl) { cr_lock_shift = STM32WB_FLASH_CR_LOCK; } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { cr_reg = FLASH_H7_CR1; - if (sl->has_dual_bank) { + if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { cr2_reg = FLASH_H7_CR2; } cr_lock_shift = FLASH_H7_CR_LOCK; @@ -691,7 +691,7 @@ static int lock_flash_option(stlink_t *sl) { case STLINK_FLASH_TYPE_H7: optcr_reg = FLASH_H7_OPTCR; optlock_shift = FLASH_H7_OPTCR_OPTLOCK; - if (sl->has_dual_bank) + if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) optcr2_reg = FLASH_H7_OPTCR2; break; default: @@ -759,7 +759,7 @@ static int unlock_flash_option(stlink_t *sl) { break; case STLINK_FLASH_TYPE_H7: optkey_reg = FLASH_H7_OPT_KEYR; - if (sl->has_dual_bank) + if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) optkey2_reg = FLASH_H7_OPT_KEYR2; break; default: @@ -907,7 +907,7 @@ static void set_flash_cr_mer(stlink_t *sl, bool v, unsigned bank) { cr_reg = STM32Gx_FLASH_CR; cr_mer = (1 << STM32Gx_FLASH_CR_MER1); - if (sl->has_dual_bank) { + if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { cr_mer |= (1 << STM32Gx_FLASH_CR_MER2); } @@ -1034,7 +1034,7 @@ static inline unsigned int is_flash_busy(stlink_t *sl) { res = read_flash_sr(sl, BANK_1) & (1 << sr_busy_shift); if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL || - (sl->flash_type == STLINK_FLASH_TYPE_H7 && sl->has_dual_bank)) { + (sl->flash_type == STLINK_FLASH_TYPE_H7 && sl->chip_flags & CHIP_F_HAS_DUAL_BANK)) { res |= read_flash_sr(sl, BANK_2) & (1 << sr_busy_shift); } @@ -1085,13 +1085,13 @@ static int check_flash_error(stlink_t *sl) break; case STLINK_FLASH_TYPE_H7: res = read_flash_sr(sl, BANK_1) & FLASH_H7_SR_ERROR_MASK; - if (sl->has_dual_bank) { + if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { res |= read_flash_sr(sl, BANK_2) & FLASH_H7_SR_ERROR_MASK; } if (res) { // Clear errors stlink_write_debug32(sl, FLASH_H7_CCR1, res); - if (sl->has_dual_bank) { + if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { stlink_write_debug32(sl, FLASH_H7_CCR2, res); } } @@ -1355,7 +1355,6 @@ int stlink_load_device_params(stlink_t *sl) { } sl->flash_type = params->flash_type; - sl->has_dual_bank = params->has_dual_bank; sl->flash_pgsz = params->flash_pagesize; sl->sram_size = params->sram_size; sl->sys_base = params->bootrom_base; @@ -1378,8 +1377,9 @@ int stlink_load_device_params(stlink_t *sl) { } // H7 devices with small flash has one bank - if (sl->has_dual_bank && sl->flash_type == STLINK_FLASH_TYPE_H7) { - sl->has_dual_bank = (flash_size/sl->flash_pgsz) > 1; + if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK && sl->flash_type == STLINK_FLASH_TYPE_H7) { + if ((flash_size/sl->flash_pgsz) <= 1) + sl->chip_flags &= ~CHIP_F_HAS_DUAL_BANK; } #if 0 @@ -2621,7 +2621,7 @@ int stlink_erase_flash_mass(stlink_t *sl) { if (sl->flash_type == STLINK_FLASH_TYPE_H7 && sl->chip_id != STLINK_CHIPID_STM32_H7AX) { // set parallelism write_flash_cr_psiz(sl, 3 /*64it*/, BANK_1); - if (sl->has_dual_bank) { + if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { write_flash_cr_psiz(sl, 3 /*64bit*/, BANK_2); } } @@ -2630,7 +2630,7 @@ int stlink_erase_flash_mass(stlink_t *sl) { set_flash_cr_strt(sl, BANK_1); // start erase operation, reset by hw with busy bit if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL || - (sl->flash_type == STLINK_FLASH_TYPE_H7 && sl->has_dual_bank)) { + (sl->flash_type == STLINK_FLASH_TYPE_H7 && sl->chip_flags & CHIP_F_HAS_DUAL_BANK)) { set_flash_cr_mer(sl, 1, BANK_2); // set the mass erase bit in bank 2 set_flash_cr_strt(sl, BANK_2); // start erase operation in bank 2 } @@ -2642,7 +2642,7 @@ int stlink_erase_flash_mass(stlink_t *sl) { // reset the mass erase bit set_flash_cr_mer(sl, 0, BANK_1); if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL || - (sl->flash_type == STLINK_FLASH_TYPE_H7 && sl->has_dual_bank)) { + (sl->flash_type == STLINK_FLASH_TYPE_H7 && sl->chip_flags & CHIP_F_HAS_DUAL_BANK)) { set_flash_cr_mer(sl, 0, BANK_2); } @@ -2872,13 +2872,13 @@ int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { unlock_flash_if(sl); // unlock the cr set_flash_cr_pg(sl, BANK_1); // set programming mode - if (sl->has_dual_bank) { + if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { set_flash_cr_pg(sl, BANK_2); } if (sl->chip_id != STLINK_CHIPID_STM32_H7AX) { // set parallelism write_flash_cr_psiz(sl, 3 /*64it*/, BANK_1); - if (sl->has_dual_bank) { + if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { write_flash_cr_psiz(sl, 3 /*64bit*/, BANK_2); } } @@ -3047,7 +3047,7 @@ int stlink_flashloader_stop(stlink_t *sl) { (sl->flash_type == STLINK_FLASH_TYPE_H7)) { clear_flash_cr_pg(sl, BANK_1); - if (sl->flash_type == STLINK_FLASH_TYPE_H7 && sl->has_dual_bank) { + if (sl->flash_type == STLINK_FLASH_TYPE_H7 && sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { clear_flash_cr_pg(sl, BANK_2); } lock_flash(sl); diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index dc3218261..425cc17d5 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -631,7 +631,6 @@ static const struct stlink_chipid_params devices[] = { .chip_id = STLINK_CHIPID_STM32_G4_CAT3, .description = "G4 Category-3", .flash_type = STLINK_FLASH_TYPE_G4, - .has_dual_bank = true, .flash_size_reg = 0x1FFF75E0, // Section 47.2 .flash_pagesize = 0x800, // 2k (sec 3.3.1) // SRAM1 is 80k at 0x20000000 @@ -642,7 +641,7 @@ static const struct stlink_chipid_params devices[] = { .bootrom_size = 0x7000, // 28k (table 2) .option_base = STM32_G4_OPTION_BYTES_BASE, .option_size = 4, - .flags = CHIP_F_HAS_SWO_TRACING, + .flags = CHIP_F_HAS_DUAL_BANK | CHIP_F_HAS_SWO_TRACING, }, { // STM32WB55 (from RM0434) @@ -661,7 +660,6 @@ static const struct stlink_chipid_params devices[] = { .chip_id = STLINK_CHIPID_STM32_H74XXX, .description = "H74x/H75x", .flash_type = STLINK_FLASH_TYPE_H7, - .has_dual_bank = true, .flash_size_reg = 0x1ff1e880, // "Flash size register" (pg3272) .flash_pagesize = 0x20000, // 128k sector (pg147) .sram_size = 0x20000, // 128k "DTCM" from Table 7 @@ -669,14 +667,13 @@ static const struct stlink_chipid_params devices[] = { .bootrom_size = 0x20000, // "System memory" byte size in hex from Table 7 .option_base = STM32_H7_OPTION_BYTES_BASE, .option_size = 44, // FLASH_OPTSR_CUR to FLASH_BOOT_PRGR from Table 28 - .flags = CHIP_F_HAS_SWO_TRACING, + .flags = CHIP_F_HAS_DUAL_BANK | CHIP_F_HAS_SWO_TRACING, }, { // STM32H7A3/7B3 (from RM0455) .chip_id = STLINK_CHIPID_STM32_H7AX, .description = "H7Ax/H7Bx", .flash_type = STLINK_FLASH_TYPE_H7, - .has_dual_bank = true, .flash_size_reg = 0x08FFF80C, // "Flash size register" (p.2949) .flash_pagesize = 0x2000, // 8k sector (p.146) .sram_size = 0x20000, // 128k "DTCM" (Figure 1) @@ -684,7 +681,7 @@ static const struct stlink_chipid_params devices[] = { .bootrom_size = 0x20000, // "System memory" byte size in hex splitted to two banks (Table 12-14) .option_base = STM32_H7_OPTION_BYTES_BASE, .option_size = 44, - .flags = CHIP_F_HAS_SWO_TRACING, + .flags = CHIP_F_HAS_DUAL_BANK | CHIP_F_HAS_SWO_TRACING, }, { // STM32H72x/H73x (from RM0468) diff --git a/src/stlink-lib/chipid.h b/src/stlink-lib/chipid.h index 5fee49f87..f790e7899 100644 --- a/src/stlink-lib/chipid.h +++ b/src/stlink-lib/chipid.h @@ -70,7 +70,8 @@ enum stlink_stm32_chipids { }; -#define CHIP_F_HAS_SWO_TRACING (1 << 0) +#define CHIP_F_HAS_DUAL_BANK (1 << 0) +#define CHIP_F_HAS_SWO_TRACING (1 << 1) /** Chipid parameters */ @@ -78,7 +79,6 @@ struct stlink_chipid_params { uint32_t chip_id; char *description; enum stlink_flash_type flash_type; - bool has_dual_bank; uint32_t flash_size_reg; uint32_t flash_pagesize; uint32_t sram_size; From cbd2633e64b93644eeec2fefdd10729d1fa02ff2 Mon Sep 17 00:00:00 2001 From: John Hall Date: Mon, 7 Dec 2020 11:10:19 -0800 Subject: [PATCH 157/503] Fixing binary compatibility with the stlink structure. --- inc/stlink.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/inc/stlink.h b/inc/stlink.h index d66cd74fb..9b5e56594 100644 --- a/inc/stlink.h +++ b/inc/stlink.h @@ -194,7 +194,6 @@ struct _stlink { char serial[STLINK_SERIAL_MAX_SIZE]; int serial_size; int freq; // set by stlink_open_usb(), values: STLINK_SWDCLK_xxx_DIVISOR - uint32_t max_trace_freq; // set by stlink_open_usb() enum stlink_flash_type flash_type; // stlink_chipid_params.flash_type, set by stlink_load_device_params(), values: STLINK_FLASH_TYPE_xxx @@ -220,6 +219,8 @@ struct _stlink { struct stlink_version_ version; uint32_t chip_flags; // stlink_chipid_params.flags, set by stlink_load_device_params(), values: CHIP_F_xxx + + uint32_t max_trace_freq; // set by stlink_open_usb() }; int stlink_enter_swd_mode(stlink_t *sl); From 4cf8b79099ca28cf97be76b5fdf60e2e83bd06d2 Mon Sep 17 00:00:00 2001 From: John Hall Date: Wed, 9 Dec 2020 14:03:18 -0800 Subject: [PATCH 158/503] Fixing build on clang. --- src/st-trace/trace.c | 2 +- src/stlink-lib/helper.c | 2 +- src/stlink-lib/usb.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/st-trace/trace.c b/src/st-trace/trace.c index 7b31900a2..549a1a385 100644 --- a/src/st-trace/trace.c +++ b/src/st-trace/trace.c @@ -410,7 +410,7 @@ static bool read_trace(stlink_t* stlink, st_trace_t* trace) { static void check_for_configuration_error(stlink_t* stlink, st_trace_t* trace, uint32_t trace_frequency) { // Only check configuration one time after the first 10 seconds of running. - uint32_t elapsed_time_s = time(NULL) - trace->start_time; + time_t elapsed_time_s = time(NULL) - trace->start_time; if (trace->configuration_checked || elapsed_time_s < 10) { return; } diff --git a/src/stlink-lib/helper.c b/src/stlink-lib/helper.c index 8b2c8e8f7..32d9b6c8d 100644 --- a/src/stlink-lib/helper.c +++ b/src/stlink-lib/helper.c @@ -11,5 +11,5 @@ unsigned time_ms() { struct timeval tv; gettimeofday(&tv, NULL); - return (unsigned)tv.tv_sec * 1000 + tv.tv_usec / 1000; + return (unsigned)(tv.tv_sec * 1000 + tv.tv_usec / 1000); } diff --git a/src/stlink-lib/usb.c b/src/stlink-lib/usb.c index ec0720a03..caf31e280 100644 --- a/src/stlink-lib/usb.c +++ b/src/stlink-lib/usb.c @@ -1109,7 +1109,7 @@ int _stlink_usb_read_trace(stlink_t* sl, uint8_t* buf, size_t size) { return -1; } - size_t trace_count = read_uint16(sl->q_buf, 0); + uint16_t trace_count = read_uint16(sl->q_buf, 0); if (trace_count > size) { ELOG("read_trace insufficient buffer length\n"); From 95e9c36a85cefa9ca5cfa033dd9a9fe238a2f40d Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 13 Dec 2020 00:04:11 +0100 Subject: [PATCH 159/503] General Project Update - Mention support for VS Code (Closes #1057) - Compilation with GCC 11 fails (Closes #1077) - Updated list of contributors - Updated CHANGELOG.md --- CHANGELOG.md | 2 ++ README.md | 11 ++++++----- contributors.txt | 1 + src/st-util/gdb-server.c | 2 +- 4 files changed, 10 insertions(+), 6 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index 4c178a4e4..eed8b8546 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -40,6 +40,8 @@ Fixes: * st-util: wrong register values passed to gdb (st-link v2) ([#1002](https://github.com/stlink-org/stlink/pull/1002), [#1011](https://github.com/stlink-org/stlink/pull/1011), [#1026](https://github.com/stlink-org/stlink/pull/1026), [#1027](https://github.com/stlink-org/stlink/pull/1027)) * [doc] Fixed wrong path for rules.d folder ([#1020](https://github.com/stlink-org/stlink/pull/1020)) * Use vl flashloader for all STM32F1 series ([#1041](https://github.com/stlink-org/stlink/pull/1041), [#1044](https://github.com/stlink-org/stlink/pull/1044)) +* Fixed gettimeofday for MSVC ([#1074](https://github.com/stlink-org/stlink/pull/1074)) +* Fixed compilation with GCC 11 ([#1077](https://github.com/stlink-org/stlink/pull/1077)) v1.6.1 diff --git a/README.md b/README.md index 350c36e34..6bb99b892 100644 --- a/README.md +++ b/README.md @@ -42,11 +42,11 @@ On the user level there is no difference in handling or operation between these The STlink toolset includes: -* a communication library (libstlink.a), -* a programmer and chip information tool (st-info), -* a flash manipulation tool (st-flash), -* a GDB server (st-util) and -* a GUI-Interface (stlink-gui) _[optional]_ +* `libstlink` - a communication library +* `st-info` - a programmer and chip information tool +* `st-flash` - a flash manipulation tool +* `st-util` - a GDB server (supported in Visual Studio Code / VSCodium via the [Cortex-Debug](https://github.com/Marus/cortex-debug) plugin +* `stlink-gui` - a GUI-Interface [optional]_ ## Supported operating systems and hardware combinations @@ -58,6 +58,7 @@ Supported operating systems are listed in [version_support.md](doc/version_suppo The `stlink` toolset continues to maintain backwards compatibility with the **STLINK/v1** programmer.
Please note that on macOS this support is limited to versions 10.13 - 10.15. + ## Tutorial & HOWTO Our [tutorial](doc/tutorial.md) may help you along with some advanced tasks and additional info. diff --git a/contributors.txt b/contributors.txt index 65b53aed1..57801b9ab 100644 --- a/contributors.txt +++ b/contributors.txt @@ -64,6 +64,7 @@ Jim Paris Jiří Netolický Jerry Nosky [jnosky] Jochen Wilhelmy [Jochen0x90h] +John Hall [simplerobot] Joel Bodenmann [Tectu] Johannes Taelman Jonas Danielsson diff --git a/src/st-util/gdb-server.c b/src/st-util/gdb-server.c index c47a3a9f3..4177cef11 100644 --- a/src/st-util/gdb-server.c +++ b/src/st-util/gdb-server.c @@ -43,7 +43,7 @@ static stlink_t *connected_stlink = NULL; static bool semihosting = false; static bool serial_specified = false; -static char serialnumber[28] = {0}; +static char serialnumber[STLINK_SERIAL_MAX_SIZE] = {0}; #if defined(_WIN32) #define close_socket win32_close_socket From a66557a102d48e69feb0a9746e8e42c4baf31fe2 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 13 Dec 2020 16:58:48 +0100 Subject: [PATCH 160/503] [doc] STM32F103 fake chips (Closes #1024) --- doc/tutorial.md | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/doc/tutorial.md b/doc/tutorial.md index 7b8b1d461..1d20c68ee 100644 --- a/doc/tutorial.md +++ b/doc/tutorial.md @@ -78,6 +78,28 @@ to ensure that the rules actually take effect. Using the trigger command means t If the VID:PID of your device doesn't match those in any of the 3 files, then you may need to create a custom rule file to match your VID:PID. +### b) NOTE: Chinese Fake-Chips CKS32F103C8T6 or CS32F103C8T6 being marked as "STM32F103C8T6" + +In contrast to "Clone chips" which identify themselves as such by their official marking (manufacturer, model, etc.), so called "Fake chips" do not. +Instead counterfeiters try to copy the outer appearance of the original and thus are very hard to detect. +Possible malfunction then may lead to various effects and issues during operation also in in connection with this toolset. + +As of December 2019 several so called "Bluepill-Boards" with a STM32F103C8T6 appeared on the market that do not hold the original part. +In this known example one finds the counterfeited "STM32F103C8T6" MCUs to identify themselves with chip-id `0x2ba01477` instead of `0x1ba01477`. + +In the following you find some hints on how to identify your chip and track down fraud: + +* [How to Detect STM32 Fakes](https://www.cnx-software.com/2020/03/22/how-to-detect-stm32-fakes/) +* [Confirmation by STMicroelectronics](https://www.mikrocontroller.net/attachment/442839/couterfeit_STM.png) (Marking: 991KA 93 MYS 807) + +However it appears that not all counterfeited parts cause problems during operation, but some are known to not even being able to execute a basic "blinky" example binary. Further there can be problems that may not even show up or affect you directly, but somewhen later in time (or maybe never). +This demonstrates there is no guarantee for a proper working chip with equal functionality compared to the original. + +Please keep this in mind and be sceptical when facing problems with this type of boards. +Check your hardware and try to identify what you have in front of you before assuming a bug in the `stlink` toolset. + +Please let us know, if you come across any further websites or tutorials that help to identify STM32 fake chips so we can list them here to help others. + ------ ( Content below is currently unrevised and may be outdated as of Apr 2020. ) From 0b7b1f3b03814a6d09d389697cc420a9de335a3c Mon Sep 17 00:00:00 2001 From: Oleksiy Slyshyk Date: Sat, 19 Dec 2020 14:41:26 +0200 Subject: [PATCH 161/503] fix msvc build --- CMakeLists.txt | 1 + src/st-trace/trace.c | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index f5c450e93..064aa06d5 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -249,6 +249,7 @@ if (MSVC) # Add getopt to sources include_directories(src/win32/getopt) set(ST-UTIL_SOURCES "${ST-UTIL_SOURCES};src/win32/getopt/getopt.c") + set(ST-TRACE_SOURCES "${ST-TRACE_SOURCES};src/win32/getopt/getopt.c") endif () add_executable(st-flash ${ST-FLASH_SOURCES}) diff --git a/src/st-trace/trace.c b/src/st-trace/trace.c index 549a1a385..e737e4d4a 100644 --- a/src/st-trace/trace.c +++ b/src/st-trace/trace.c @@ -552,7 +552,7 @@ int main(int argc, char** argv) } ILOG("Reading Trace\n"); - st_trace_t trace = {}; + st_trace_t trace = {0}; trace.start_time = time(NULL); if (stlink_run(stlink)) { From ffbecc4800c2053cf172cdeffa3c9772cb3d9636 Mon Sep 17 00:00:00 2001 From: Oleksiy Slyshyk Date: Sat, 19 Dec 2020 15:33:03 +0200 Subject: [PATCH 162/503] use memset for init struct --- src/st-trace/trace.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/st-trace/trace.c b/src/st-trace/trace.c index e737e4d4a..ee35a5923 100644 --- a/src/st-trace/trace.c +++ b/src/st-trace/trace.c @@ -552,7 +552,8 @@ int main(int argc, char** argv) } ILOG("Reading Trace\n"); - st_trace_t trace = {0}; + st_trace_t trace; + memset(&trace, 0, sizeof(trace)); trace.start_time = time(NULL); if (stlink_run(stlink)) { From e8c1e8a120cafa0a773ef6b93a3617087f322650 Mon Sep 17 00:00:00 2001 From: Luuk van Dijk Date: Sun, 20 Dec 2020 22:53:00 +0100 Subject: [PATCH 163/503] correctly handle endianness without reference to host platform --- src/common.c | 72 ++++++++++++---------------------------------------- 1 file changed, 16 insertions(+), 56 deletions(-) diff --git a/src/common.c b/src/common.c index ec9f19b4a..aaa2462a1 100644 --- a/src/common.c +++ b/src/common.c @@ -349,49 +349,32 @@ #define L1_WRITE_BLOCK_SIZE 0x80 #define L0_WRITE_BLOCK_SIZE 0x40 + +// Endianness +// https://commandcenter.blogspot.com/2012/04/byte-order-fallacy.html +// These functions encode and decode little endian uint16 and uint32 values. + void write_uint32(unsigned char* buf, uint32_t ui) { - if (!is_bigendian()) { // le -> le (don't swap) - buf[0] = ((unsigned char*)&ui)[0]; - buf[1] = ((unsigned char*)&ui)[1]; - buf[2] = ((unsigned char*)&ui)[2]; - buf[3] = ((unsigned char*)&ui)[3]; - } else { - buf[0] = ((unsigned char*)&ui)[3]; - buf[1] = ((unsigned char*)&ui)[2]; - buf[2] = ((unsigned char*)&ui)[1]; - buf[3] = ((unsigned char*)&ui)[0]; - } + buf[0] = ui; + buf[1] = ui >> 8; + buf[2] = ui >> 16; + buf[3] = ui >> 24; } void write_uint16(unsigned char* buf, uint16_t ui) { - if (!is_bigendian()) { // le -> le (don't swap) - buf[0] = ((unsigned char*)&ui)[0]; - buf[1] = ((unsigned char*)&ui)[1]; - } else { - buf[0] = ((unsigned char*)&ui)[1]; - buf[1] = ((unsigned char*)&ui)[0]; - } + buf[0] = ui ; + buf[1] = ui >> 8; } uint32_t read_uint32(const unsigned char *c, const int pt) { - uint32_t ui; - char *p = (char *)&ui; - - if (!is_bigendian()) { // le -> le (don't swap) - p[0] = c[pt + 0]; - p[1] = c[pt + 1]; - p[2] = c[pt + 2]; - p[3] = c[pt + 3]; - } else { - p[0] = c[pt + 3]; - p[1] = c[pt + 2]; - p[2] = c[pt + 1]; - p[3] = c[pt + 0]; - } + return ((uint32_t)c[pt]) | ((uint32_t)c[pt+1] << 8) | ((uint32_t)c[pt+2] << 16) | ((uint32_t)c[pt+3] << 24) ; +} - return(ui); +uint16_t read_uint16(const unsigned char *c, const int pt) { + return ((uint16_t)c[pt]) | ((uint16_t)c[pt+1] << 8); } + static uint32_t get_stm32l0_flash_base(stlink_t *sl) { switch (sl->chip_id) { @@ -1779,30 +1762,7 @@ int stlink_trace_read(stlink_t* sl, uint8_t* buf, size_t size) { // End of delegates.... Common code below here... -// Endianness -// http://www.ibm.com/developerworks/aix/library/au-endianc/index.html -// const int i = 1; -// #define is_bigendian() ( (*(char*)&i) == 0 ) - -unsigned int is_bigendian(void) { - static volatile const unsigned int i = 1; - return(*(volatile const char*)&i == 0); -} - -uint16_t read_uint16(const unsigned char *c, const int pt) { - uint32_t ui; - char *p = (char *)&ui; - if (!is_bigendian()) { // le -> le (don't swap) - p[0] = c[pt + 0]; - p[1] = c[pt + 1]; - } else { - p[0] = c[pt + 1]; - p[1] = c[pt + 0]; - } - - return(ui); -} // same as above with entrypoint. From ddac731929b0c879a9a6dc9e17811abc88b682c3 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Fri, 25 Dec 2020 23:33:20 +0100 Subject: [PATCH 164/503] Minor formatting fixes --- CHANGELOG.md | 4 ++-- README.md | 6 +++--- src/st-trace/trace.c | 1 - src/stlink-lib/chipid.c | 2 +- 4 files changed, 6 insertions(+), 7 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index eed8b8546..ad13e46aa 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -317,13 +317,13 @@ Major changes and added features: * Added intel hex file reading for `st-flash` ([#110](https://github.com/stlink-org/stlink/pull/110), [#157](https://github.com/stlink-org/stlink/pull/157), [#457](https://github.com/stlink-org/stlink/pull/547), [#459](https://github.com/stlink-org/stlink/pull/549)) * Added support for ARM semihosting to `st-util` ([#147](https://github.com/stlink-org/stlink/pull/147), [#227](https://github.com/stlink-org/stlink/pull/227), [#454](https://github.com/stlink-org/stlink/pull/454), [#455](https://github.com/stlink-org/stlink/pull/455)) * Added manpages (generated with pandoc from Markdown) ([#208](https://github.com/stlink-org/stlink/pull/208), [#464](https://github.com/stlink-org/stlink/pull/464), [#466](https://github.com/stlink-org/stlink/pull/466), [#467](https://github.com/stlink-org/stlink/pull/467)) -* Removal of undocumented `st-term` utility, which is now replaced by `st-util` ARM semihosting feature ([#228](https://github.com/stlink-org/stlink/pull/228), ([#507](https://github.com/stlink-org/stlink/pull/507), commit [#3fd0f09](https://github.com/stlink-org/stlink/commit/3fd0f099782506532198473b24f643a3f68d5ff9)) +* Removal of undocumented `st-term` utility, which is now replaced by `st-util` ARM semihosting feature ([#228](https://github.com/stlink-org/stlink/pull/228), [#507](https://github.com/stlink-org/stlink/pull/507), commit [#3fd0f09](https://github.com/stlink-org/stlink/commit/3fd0f099782506532198473b24f643a3f68d5ff9)) * Support serial numbers argument for `st-util` and `st-flash` to probe and control multiple connected programmers ([#318](https://github.com/stlink-org/stlink/pull/318), [#398](https://github.com/stlink-org/stlink/pull/398), [#541](https://github.com/stlink-org/stlink/pull/541)) * Merge st-probe tool into st-info ([#398](https://github.com/stlink-org/stlink/pull/398)) * Added support for native debian packaging ([#444](https://github.com/stlink-org/stlink/pull/444), [#472](https://github.com/stlink-org/stlink/pull/472), [#473](https://github.com/stlink-org/stlink/pull/473), [#482](https://github.com/stlink-org/stlink/pull/482), [#483](https://github.com/stlink-org/stlink/pull/483), [#484](https://github.com/stlink-org/stlink/pull/484), [#485](https://github.com/stlink-org/stlink/pull/485)) * Rewritten commandline parsing for `st-flash` ([#459](https://github.com/stlink-org/stlink/pull/459)) * Added `--reset` command to `st-flash` ([#505](https://github.com/stlink-org/stlink/pull/505)) -* st-util should detect when USB commands fail ([#525](https://github.com/stlink-org/stlink/pull/525), ([#527](https://github.com/stlink-org/stlink/pull/527), ([#528](https://github.com/stlink-org/stlink/pull/528)) +* st-util should detect when USB commands fail ([#525](https://github.com/stlink-org/stlink/pull/525), [#527](https://github.com/stlink-org/stlink/pull/527), [#528](https://github.com/stlink-org/stlink/pull/528)) Chip support added for: diff --git a/README.md b/README.md index 6bb99b892..d401f2c5d 100644 --- a/README.md +++ b/README.md @@ -42,11 +42,11 @@ On the user level there is no difference in handling or operation between these The STlink toolset includes: -* `libstlink` - a communication library * `st-info` - a programmer and chip information tool * `st-flash` - a flash manipulation tool -* `st-util` - a GDB server (supported in Visual Studio Code / VSCodium via the [Cortex-Debug](https://github.com/Marus/cortex-debug) plugin -* `stlink-gui` - a GUI-Interface [optional]_ +* `st-util` - a GDB server (supported in Visual Studio Code / VSCodium via the [Cortex-Debug](https://github.com/Marus/cortex-debug) plugin) +* `stlink-lib` - a communication library +* `stlink-gui` - a GUI-Interface _[optional]_ ## Supported operating systems and hardware combinations diff --git a/src/st-trace/trace.c b/src/st-trace/trace.c index ee35a5923..71ba6b360 100644 --- a/src/st-trace/trace.c +++ b/src/st-trace/trace.c @@ -571,4 +571,3 @@ int main(int argc, char** argv) return APP_RESULT_SUCCESS; } - diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index 425cc17d5..221234bbb 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -11,7 +11,7 @@ static const struct stlink_chipid_params devices[] = { .flash_pagesize = 0x800, // No flash pages .sram_size = 0x80000, // "SRAM" byte size in hex from .bootrom_base = 0x00200000, // ! "System memory" starting address from - .bootrom_size = 0xEDC0, // ! @todo "System memory" byte size in hex from + .bootrom_size = 0xEDC0, // ! @todo "System memory" byte size in hex from .option_base = STM32_F7_OPTION_BYTES_BASE, // Used for reading back the option bytes, writing uses FLASH_F7_OPTCR and FLASH_F7_OPTCR1 .option_size = 0x20, .flags = CHIP_F_HAS_SWO_TRACING, From 4bfaab0ea993fe86da9f2aef612036adcf8ef58d Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Mon, 4 Jan 2021 00:53:24 +0100 Subject: [PATCH 165/503] Removed support for STLINK/v1 on macOS 10.13 --- README.md | 2 +- stlinkv1_macos_driver/install.sh | 5 +- .../Contents/Info.plist | 82 ------------- .../Contents/MacOS/stlink_shield_10_13 | Bin 33840 -> 0 bytes .../stlink_shield_10_13.kext/Contents/PkgInfo | 1 - .../Contents/_CodeSignature/CodeResources | 115 ------------------ .../Contents/Info.plist | 2 +- .../Contents/MacOS/stlink_shield_10_14 | Bin 33840 -> 33840 bytes .../Contents/Info.plist | 2 +- .../Contents/MacOS/stlink_shield_10_15 | Bin 33840 -> 33840 bytes .../stlink_shield.xcodeproj/project.pbxproj | 95 +-------------- .../contents.xcworkspacedata | 2 +- .../UserInterfaceState.xcuserstate | Bin 185319 -> 187405 bytes .../WorkspaceSettings.xcsettings | 6 +- .../xcschemes/stlink_shield_10.13.xcscheme | 67 ---------- .../xcschemes/xcschememanagement.plist | 34 +----- 16 files changed, 17 insertions(+), 396 deletions(-) delete mode 100644 stlinkv1_macos_driver/stlink_shield_10_13.kext/Contents/Info.plist delete mode 100644 stlinkv1_macos_driver/stlink_shield_10_13.kext/Contents/MacOS/stlink_shield_10_13 delete mode 100644 stlinkv1_macos_driver/stlink_shield_10_13.kext/Contents/PkgInfo delete mode 100644 stlinkv1_macos_driver/stlink_shield_10_13.kext/Contents/_CodeSignature/CodeResources delete mode 100644 stlinkv1_macos_driver/stlink_shield_xcode/stlink_shield.xcodeproj/xcshareddata/xcschemes/stlink_shield_10.13.xcscheme diff --git a/README.md b/README.md index d401f2c5d..3799f46d2 100644 --- a/README.md +++ b/README.md @@ -36,7 +36,7 @@ It supports several so called STLINK programmer boards (and clones thereof) whic - transport layer: raw USB commands - stand-alone programmer -_*)_ **Note: Support on macOS is limited to 10.13 - 10.15. Any later versions are no longer compatible with the STLINK/v1 due to technical reasons.** +_*)_ **Note: Support on macOS is limited to 10.14 - 10.15. Any later versions are no longer compatible with the STLINK/v1 due to technical reasons.** On the user level there is no difference in handling or operation between these different revisions. diff --git a/stlinkv1_macos_driver/install.sh b/stlinkv1_macos_driver/install.sh index 19e9f141d..5716281a1 100644 --- a/stlinkv1_macos_driver/install.sh +++ b/stlinkv1_macos_driver/install.sh @@ -2,15 +2,12 @@ ISMACOS=$(sw_vers -productVersion) case $ISMACOS in -10.13*) - KEXT="stlink_shield_10_13.kext" - ;; 10.14*) KEXT="stlink_shield_10_14.kext" ;; 10.15*) KEXT="stlink_shield_10_15.kext" - ;; + ;; *) echo "OS X version not supported." exit 1 diff --git a/stlinkv1_macos_driver/stlink_shield_10_13.kext/Contents/Info.plist b/stlinkv1_macos_driver/stlink_shield_10_13.kext/Contents/Info.plist deleted file mode 100644 index fc759b362..000000000 --- a/stlinkv1_macos_driver/stlink_shield_10_13.kext/Contents/Info.plist +++ /dev/null @@ -1,82 +0,0 @@ - - - - - BuildMachineOSBuild - 18G4032 - CFBundleDevelopmentRegion - English - CFBundleIdentifier - com.libusb.stlink-shield - CFBundleInfoDictionaryVersion - 6.0 - CFBundlePackageType - KEXT - CFBundleSignature - ???? - CFBundleSupportedPlatforms - - MacOSX - - CFBundleVersion - 1.0.0 - DTCompiler - com.apple.compilers.llvm.clang.1_0 - DTPlatformBuild - 11C504 - DTPlatformVersion - GM - DTSDKBuild - 19B90 - DTSDKName - macosx10.15 - DTXcode - 1130 - DTXcodeBuild - 11C504 - IOKitPersonalities - - DeviceDriver - - CFBundleIdentifier - com.apple.kpi.iokit - IOClass - IOService - IOProviderClass - IOUSBDevice - bcdDevice - 256 - idProduct - 14148 - idVendor - 1155 - - InterfaceDriver - - CFBundleIdentifier - com.apple.kpi.iokit - IOClass - IOService - IOProviderClass - IOUSBInterface - bConfigurationValue - 1 - bInterfaceNumber - 0 - idProduct - 14148 - idVendor - 1155 - - - LSMinimumSystemVersion - 10.13 - OSBundleLibraries - - com.apple.iokit.IOUSBFamily - 1.8 - com.apple.kpi.libkern - 11.2.0 - - - diff --git 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1000 - - ^Resources/.*\.lproj/locversion.plist$ - - omit - - weight - 1100 - - ^Resources/Base\.lproj/ - - weight - 1010 - - ^version.plist$ - - - rules2 - - .*\.dSYM($|/) - - weight - 11 - - ^(.*/)?\.DS_Store$ - - omit - - weight - 2000 - - ^(Frameworks|SharedFrameworks|PlugIns|Plug-ins|XPCServices|Helpers|MacOS|Library/(Automator|Spotlight|LoginItems))/ - - nested - - weight - 10 - - ^.* - - ^Info\.plist$ - - omit - - weight - 20 - - ^PkgInfo$ - - omit - - weight - 20 - - ^Resources/ - - weight - 20 - - ^Resources/.*\.lproj/ - - optional - - weight - 1000 - - ^Resources/.*\.lproj/locversion.plist$ - - omit - - weight - 1100 - - ^Resources/Base\.lproj/ - - weight - 1010 - - ^[^/]+$ - - nested - - weight - 10 - - ^embedded\.provisionprofile$ - - weight - 20 - - ^version\.plist$ - - weight - 20 - - - - diff --git a/stlinkv1_macos_driver/stlink_shield_10_14.kext/Contents/Info.plist b/stlinkv1_macos_driver/stlink_shield_10_14.kext/Contents/Info.plist index d43deca2b..fd424ea93 100644 --- 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UseAppPreferences + UseTargetSettings + BuildSystemType + Latest CustomBuildIntermediatesPath Build/Intermediates.noindex CustomBuildLocationType @@ -13,7 +15,7 @@ DerivedDataLocationStyle Default IssueFilterStyle - ShowActiveSchemeOnly + ShowAll LiveSourceIssuesEnabled SharedBuildFolderName diff --git a/stlinkv1_macos_driver/stlink_shield_xcode/stlink_shield.xcodeproj/xcshareddata/xcschemes/stlink_shield_10.13.xcscheme b/stlinkv1_macos_driver/stlink_shield_xcode/stlink_shield.xcodeproj/xcshareddata/xcschemes/stlink_shield_10.13.xcscheme deleted file mode 100644 index d98dd9b97..000000000 --- a/stlinkv1_macos_driver/stlink_shield_xcode/stlink_shield.xcodeproj/xcshareddata/xcschemes/stlink_shield_10.13.xcscheme +++ /dev/null @@ -1,67 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/stlinkv1_macos_driver/stlink_shield_xcode/stlink_shield.xcodeproj/xcuserdata/vm-user.xcuserdatad/xcschemes/xcschememanagement.plist b/stlinkv1_macos_driver/stlink_shield_xcode/stlink_shield.xcodeproj/xcuserdata/vm-user.xcuserdatad/xcschemes/xcschememanagement.plist index d23112ec9..c9d1a75b6 100644 --- a/stlinkv1_macos_driver/stlink_shield_xcode/stlink_shield.xcodeproj/xcuserdata/vm-user.xcuserdatad/xcschemes/xcschememanagement.plist +++ b/stlinkv1_macos_driver/stlink_shield_xcode/stlink_shield.xcodeproj/xcuserdata/vm-user.xcuserdatad/xcschemes/xcschememanagement.plist @@ -4,45 +4,15 @@ SchemeUserState - stlink_shield 10.7.xcscheme_^#shared#^_ - - orderHint - 2 - - stlink_shield copy copy.xcscheme_^#shared#^_ - - orderHint - 3 - - stlink_shield copy.xcscheme_^#shared#^_ - - orderHint - 2 - - stlink_shield.xcscheme_^#shared#^_ - - orderHint - 1 - - stlink_shield_10.13.xcscheme_^#shared#^_ - - orderHint - 0 - - stlink_shield_10.14 copy.xcscheme_^#shared#^_ - - orderHint - 4 - stlink_shield_10.14.xcscheme_^#shared#^_ orderHint - 1 + 0 stlink_shield_10.15.xcscheme_^#shared#^_ orderHint - 2 + 1 SuppressBuildableAutocreation From 9fd7e63ec2bcb79ba70521a4918bdf3bfe492adc Mon Sep 17 00:00:00 2001 From: Sebastiaan de Schaetzen Date: Thu, 14 Jan 2021 11:45:49 +0100 Subject: [PATCH 166/503] flash_loader: increase wait rounds for slow boards --- src/stlink-lib/flash_loader.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/stlink-lib/flash_loader.c b/src/stlink-lib/flash_loader.c index b7726e875..b55953406 100644 --- a/src/stlink-lib/flash_loader.c +++ b/src/stlink-lib/flash_loader.c @@ -368,7 +368,7 @@ int stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t targe * the OS uses, the wait until the error message is reduced to the same order of magnitude * as what was intended. -- REW. */ -#define WAIT_ROUNDS 30 +#define WAIT_ROUNDS 40 // wait until done (reaches breakpoint) for (i = 0; i < WAIT_ROUNDS; i++) { From 1b29c6529d8723f35afd92dd108988f996d5dcde Mon Sep 17 00:00:00 2001 From: Oleksiy Slyshyk Date: Sat, 20 Feb 2021 20:26:39 +0200 Subject: [PATCH 167/503] check format string for log messages --- src/common.c | 64 +++++++++++++++++++-------------------- src/st-util/semihosting.c | 6 ++-- src/stlink-lib/logging.h | 16 +++++++--- src/stlink-lib/sg.c | 4 +-- src/stlink-lib/usb.c | 2 +- 5 files changed, 49 insertions(+), 43 deletions(-) diff --git a/src/common.c b/src/common.c index aaa2462a1..99049196d 100644 --- a/src/common.c +++ b/src/common.c @@ -1373,9 +1373,9 @@ int stlink_load_device_params(stlink_t *sl) { sl->sram_size, sl->sram_size / 1024, sl->flash_size, sl->flash_size / 1024, (unsigned int)sl->flash_pgsz); #else - ILOG("%s: %zd KiB SRAM, %zd KiB flash in at least %zd %s pages.\n", - params->description, sl->sram_size / 1024, sl->flash_size / 1024, - (sl->flash_pgsz < 1024) ? sl->flash_pgsz : sl->flash_pgsz / 1024, + ILOG("%s: %u KiB SRAM, %u KiB flash in at least %u %s pages.\n", + params->description, (unsigned)(sl->sram_size / 1024), (unsigned)(sl->flash_size / 1024), + (sl->flash_pgsz < 1024) ? (unsigned)(sl->flash_pgsz) : (unsigned)(sl->flash_pgsz / 1024), (sl->flash_pgsz < 1024) ? "byte" : "KiB"); #endif return(0); @@ -1398,7 +1398,7 @@ int stlink_soft_reset(stlink_t *sl, int halt_on_reset) { DLOG("*** stlink_soft_reset %s***\n", halt_on_reset?"(halt) ":""); - // halt core and enable debugging (if not already done) + // halt core and enable debugging (if not already done) // C_DEBUGEN is required to Halt on reset (DDI0337E, p. 10-6) stlink_write_debug32(sl, STLINK_REG_DHCSR, STLINK_REG_DHCSR_DBGKEY | STLINK_REG_DHCSR_C_HALT | STLINK_REG_DHCSR_C_DEBUGEN); @@ -1585,7 +1585,7 @@ int stlink_target_voltage(stlink_t *sl) { voltage = sl->backend->target_voltage(sl); if (voltage != -1) { - DLOG("target voltage = %ldmV\n", voltage); + DLOG("target voltage = %imV\n", voltage); } else { DLOG("error reading target voltage\n"); } @@ -2201,8 +2201,8 @@ static bool stlink_fread_ihex_finalize(struct stlink_fread_ihex_worker_arg* the_ int stlink_fread(stlink_t* sl, const char* path, bool is_ihex, stm32_addr_t addr, size_t size) { // read size bytes from addr to file - ILOG("read from address %#010x size %d\n", addr, size); - + ILOG("read from address %#010x size %u\n", addr, (unsigned)size); + int error; int fd = open(path, O_RDWR | O_TRUNC | O_CREAT | O_BINARY, 00700); @@ -2565,7 +2565,7 @@ int stlink_erase_flash_mass(stlink_t *sl) { stm32_addr_t addr = (stm32_addr_t)sl->flash_base + i * (stm32_addr_t)sl->flash_pgsz; if (stlink_erase_flash_page(sl, addr) == -1) { - WLOG("Failed to erase_flash_page(%#zx) == -1\n", addr); + WLOG("Failed to erase_flash_page(%#x) == -1\n", addr); return(-1); } @@ -2701,7 +2701,7 @@ int stm32l1_write_half_pages( for (count = 0; count < num_half_pages; count++) { if (stlink_flash_loader_run( sl, &fl, addr + count * pagesize, base + count * pagesize, pagesize) == -1) { - WLOG("l1_stlink_flash_loader_run(%#zx) failed! == -1\n", addr + count * pagesize); + WLOG("l1_stlink_flash_loader_run(%#x) failed! == -1\n", addr + count * pagesize); stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); val &= ~((1 << FLASH_L1_FPRG) | (1 << FLASH_L1_PROG)); stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); @@ -2734,7 +2734,7 @@ int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { (sl->flash_type == STLINK_FLASH_TYPE_F7) || (sl->flash_type == STLINK_FLASH_TYPE_L4)) { ILOG("Starting Flash write for F2/F4/F7/L4\n"); - + // Flash loader initialisation if (stlink_flash_loader_init(sl, fl) == -1) { ELOG("stlink_flash_loader_init() == -1\n"); @@ -2750,7 +2750,7 @@ int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { } else { voltage = stlink_target_voltage(sl); } - + if (voltage == -1) { ELOG("Failed to read Target voltage\n"); return(-1); @@ -2771,7 +2771,7 @@ int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { "using 8-bit flash writes\n", voltage); write_flash_cr_psiz(sl, 0, BANK_1); } - } + } // set programming mode set_flash_cr_pg(sl, BANK_1); @@ -2850,7 +2850,7 @@ int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { return(0); } -int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t addr, +int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t addr, uint8_t* base, uint32_t len) { size_t off; if ((sl->flash_type == STLINK_FLASH_TYPE_F4) || @@ -2860,7 +2860,7 @@ int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t addr for (off = 0; off < len;) { size_t size = len - off > buf_size ? buf_size : len - off; if (stlink_flash_loader_run(sl, fl, addr + (uint32_t)off, base + off, size) == -1) { - ELOG("stlink_flash_loader_run(%#zx) failed! == -1\n", addr + off); + ELOG("stlink_flash_loader_run(%#x) failed! == -1\n", (unsigned)(addr + off)); return(-1); } @@ -2921,7 +2921,7 @@ int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t addr // write remaining word in program memory for ( ; off < len; off += sizeof(uint32_t)) { uint32_t data; - + if ((off % sl->flash_pgsz) > (sl->flash_pgsz - 5)) { fprintf(stdout, "\r%3u/%3u pages written", (unsigned int)(off / sl->flash_pgsz), @@ -2955,7 +2955,7 @@ int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t addr DLOG("Finished unlocking flash, running loader!\n"); if (stlink_flash_loader_run(sl, fl, addr + (uint32_t)off, base + off, size) == -1) { - ELOG("stlink_flash_loader_run(%#zx) failed! == -1\n", addr + off); + ELOG("stlink_flash_loader_run(%#x) failed! == -1\n", (unsigned)(addr + off)); return(-1); } @@ -3003,7 +3003,7 @@ int stlink_flashloader_stop(stlink_t *sl) { (sl->flash_type == STLINK_FLASH_TYPE_L4) || (sl->flash_type == STLINK_FLASH_TYPE_WB) || (sl->flash_type == STLINK_FLASH_TYPE_G0) || - (sl->flash_type == STLINK_FLASH_TYPE_G4) || + (sl->flash_type == STLINK_FLASH_TYPE_G4) || (sl->flash_type == STLINK_FLASH_TYPE_H7)) { clear_flash_cr_pg(sl, BANK_1); @@ -3056,9 +3056,9 @@ int stlink_write_flash( WLOG("unaligned len 0x%x -- padding with zero\n", len); len += 1; } else if (addr & (sl->flash_pgsz - 1)) { - ELOG("addr not a multiple of current pagesize (%zd bytes), not supported, " + ELOG("addr not a multiple of current pagesize (%u bytes), not supported, " "check page start address and compare with flash module organisation " - "in related ST reference manual of your device.\n", sl->flash_pgsz); + "in related ST reference manual of your device.\n", (unsigned)(sl->flash_pgsz)); return(-1); } @@ -3071,7 +3071,7 @@ int stlink_write_flash( for (off = 0; off < len; off += stlink_calculate_pagesize(sl, addr + (uint32_t)off)) { // addr must be an addr inside the page if (stlink_erase_flash_page(sl, addr + (uint32_t)off) == -1) { - ELOG("Failed to erase_flash_page(%#zx) == -1\n", addr + off); + ELOG("Failed to erase_flash_page(%#x) == -1\n", (unsigned)(addr + off)); return(-1); } @@ -3079,8 +3079,8 @@ int stlink_write_flash( page_count++; } - ILOG("Finished erasing %d pages of %d (%#x) bytes\n", - page_count, sl->flash_pgsz, sl->flash_pgsz); + ILOG("Finished erasing %d pages of %u (%#x) bytes\n", + page_count, (unsigned)(sl->flash_pgsz), (unsigned)(sl->flash_pgsz)); if (eraseonly) { return(0); } @@ -3092,7 +3092,7 @@ int stlink_write_flash( return ret; ret = stlink_flashloader_stop(sl); if (ret) - return ret; + return ret; return(stlink_verify_write_flash(sl, addr, base, len)); } @@ -3145,7 +3145,7 @@ int stlink_parse_ihex(const char* path, uint8_t erased_pattern, uint8_t * * mem, data = calloc(*size, 1); // use calloc to get NULL if out of memory if (!data) { - ELOG("Cannot allocate %d bytes\n", *size); + ELOG("Cannot allocate %u bytes\n", (unsigned)(*size)); res = -1; break; } @@ -3520,7 +3520,7 @@ static int stlink_write_option_bytes_f7(stlink_t *sl, uint8_t* base, stm32_addr_ addr = FLASH_F7_OPTCR; ILOG("No address provided, using %#10x\n", addr); } - + if ( addr == FLASH_F7_OPTCR ) { /* write option byte, ensuring we dont lock opt, and set strt bit */ stlink_write_debug32(sl, FLASH_F7_OPTCR, (option_byte & ~(1 << FLASH_F7_OPTCR_LOCK)) | (1 << FLASH_F7_OPTCR_START)); @@ -3542,7 +3542,7 @@ static int stlink_write_option_bytes_f7(stlink_t *sl, uint8_t* base, stm32_addr_ ret = check_flash_error(sl); if (!ret) ILOG("Wrote %d option bytes %#010x to %#010x!\n", len, *(uint32_t*) base, addr); - + /* option bytes are reloaded at reset only, no obl. */ return ret; @@ -3899,7 +3899,7 @@ int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t* base, ui return(-1); } - + if ((addr < sl->option_base) || addr > sl->option_base + sl->option_size) { ELOG("Option bytes start address out of Option bytes range\n"); return(-1); @@ -3972,7 +3972,7 @@ static int stlink_write_option_control_register_f7(stlink_t *sl, uint32_t option ILOG("Asked to write option control register 1 %#10x to %#010x.\n", option_control_register, FLASH_F7_OPTCR); //write_uint32((unsigned char*) &option_byte, *(uint32_t*) (base)); //ILOG("Write %d option bytes %#010x to %#010x!\n", len, option_byte, addr); - + /* write option byte, ensuring we dont lock opt, and set strt bit */ stlink_write_debug32(sl, FLASH_F7_OPTCR, (option_control_register & ~(1 << FLASH_F7_OPTCR_LOCK)) | (1 << FLASH_F7_OPTCR_START)); @@ -3981,7 +3981,7 @@ static int stlink_write_option_control_register_f7(stlink_t *sl, uint32_t option ret = check_flash_error(sl); if (!ret) ILOG("Wrote option bytes %#010x to %#010x!\n", option_control_register, FLASH_F7_OPTCR1); - + return ret; } @@ -3997,11 +3997,11 @@ static int stlink_write_option_control_register1_f7(stlink_t *sl, uint32_t optio ILOG("Asked to write option control register 1 %#010x to %#010x.\n", option_control_register1, FLASH_F7_OPTCR1); //write_uint32((unsigned char*) &option_byte, *(uint32_t*) (base)); //ILOG("Write %d option bytes %#010x to %#010x!\n", len, option_byte, addr); - + /* write option byte, ensuring we dont lock opt, and set strt bit */ uint32_t current_control_register_value; stlink_read_debug32(sl, FLASH_F7_OPTCR, ¤t_control_register_value); - + /* write option byte */ stlink_write_debug32(sl, FLASH_F7_OPTCR1, option_control_register1); stlink_write_debug32(sl, FLASH_F7_OPTCR, (current_control_register_value & ~(1 << FLASH_F7_OPTCR_LOCK)) | (1 << FLASH_F7_OPTCR_START)); @@ -4011,7 +4011,7 @@ static int stlink_write_option_control_register1_f7(stlink_t *sl, uint32_t optio ret = check_flash_error(sl); if (!ret) ILOG("Wrote option bytes %#010x to %#010x!\n", option_control_register1, FLASH_F7_OPTCR1); - + return ret; } diff --git a/src/st-util/semihosting.c b/src/st-util/semihosting.c index 821dcdbbb..32169c812 100644 --- a/src/st-util/semihosting.c +++ b/src/st-util/semihosting.c @@ -256,7 +256,7 @@ int do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { return(-1); } - DLOG("Semihosting: write(%d, target_addr:0x%08x, %zu)\n", fd, buffer_address, + DLOG("Semihosting: write(%d, target_addr:0x%08x, %u)\n", fd, buffer_address, buffer_len); *ret = (uint32_t)write(fd, buffer, buffer_len); @@ -305,7 +305,7 @@ int do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { return(-1); } - DLOG("Semihosting: read(%d, target_addr:0x%08x, %zu)\n", fd, buffer_address, + DLOG("Semihosting: read(%d, target_addr:0x%08x, %u)\n", fd, buffer_address, buffer_len); read_result = read(fd, buffer, buffer_len); @@ -399,7 +399,7 @@ int do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { fd = (int)args[0]; offset = (off_t)args[1]; - DLOG("Semihosting: lseek(%d, %d, SEEK_SET)\n", fd, offset); + DLOG("Semihosting: lseek(%d, %d, SEEK_SET)\n", fd, (int)offset); *ret = (uint32_t)lseek(fd, offset, SEEK_SET); saved_errno = errno; diff --git a/src/stlink-lib/logging.h b/src/stlink-lib/logging.h index 78562b0d9..7f3994492 100644 --- a/src/stlink-lib/logging.h +++ b/src/stlink-lib/logging.h @@ -16,8 +16,14 @@ enum ugly_loglevel { UERROR = 20 }; +#if defined(__GNUC__) +#define PRINTF_ARRT __attribute__ ((format (printf, 3, 4))) +#else +#define PRINTF_ARRT +#endif + int ugly_init(int maximum_threshold); -int ugly_log(int level, const char *tag, const char *format, ...); +int ugly_log(int level, const char *tag, const char *format, ...) PRINTF_ARRT; int ugly_libusb_log_level(enum ugly_loglevel v); #define UGLY_LOG_FILE (strstr(__FILE__, "/") != NULL ? \ @@ -27,13 +33,13 @@ int ugly_libusb_log_level(enum ugly_loglevel v); // TODO: we need to write this in a more generic way, for now this should compile // on visual studio (See http://stackoverflow.com/a/8673872/1836746) #define DLOG_HELPER(format, ...) ugly_log(UDEBUG, UGLY_LOG_FILE, format, __VA_ARGS__) -#define DLOG(...) DLOG_HELPER(__VA_ARGS__, "") +#define DLOG(...) ugly_log(UDEBUG, UGLY_LOG_FILE, __VA_ARGS__) #define ILOG_HELPER(format, ...) ugly_log(UINFO, UGLY_LOG_FILE, format, __VA_ARGS__) -#define ILOG(...) ILOG_HELPER(__VA_ARGS__, "") +#define ILOG(...) ugly_log(UINFO, UGLY_LOG_FILE, __VA_ARGS__) #define WLOG_HELPER(format, ...) ugly_log(UWARN, UGLY_LOG_FILE, format, __VA_ARGS__) -#define WLOG(...) WLOG_HELPER(__VA_ARGS__, "") +#define WLOG(...) ugly_log(UWARN, UGLY_LOG_FILE, __VA_ARGS__) #define ELOG_HELPER(format, ...) ugly_log(UERROR, UGLY_LOG_FILE, format, __VA_ARGS__) -#define ELOG(...) ELOG_HELPER(__VA_ARGS__, "") +#define ELOG(...) ugly_log(UERROR, UGLY_LOG_FILE, __VA_ARGS__) #ifdef __cplusplus } diff --git a/src/stlink-lib/sg.c b/src/stlink-lib/sg.c index f66864c44..840466e75 100644 --- a/src/stlink-lib/sg.c +++ b/src/stlink-lib/sg.c @@ -161,7 +161,7 @@ static int dump_CDB_command(uint8_t *cdb, uint8_t cdb_len) { } sprintf(dbugp, "]\n"); - DLOG(dbugblah); + DLOG("%s",dbugblah); return(0); } @@ -274,7 +274,7 @@ static void get_sense(libusb_device_handle *handle, uint8_t endpoint_in, uint8_t } if (transferred != sizeof(sense)) { - WLOG("received unexpected amount of sense: %d != %d\n", transferred, sizeof(sense)); + WLOG("received unexpected amount of sense: %d != %u\n", transferred, (unsigned)sizeof(sense)); } uint32_t received_tag; diff --git a/src/stlink-lib/usb.c b/src/stlink-lib/usb.c index caf31e280..0168834ca 100644 --- a/src/stlink-lib/usb.c +++ b/src/stlink-lib/usb.c @@ -1442,7 +1442,7 @@ static size_t stlink_probe_usb_devs(libusb_device **devs, stlink_t **sldevs[]) { if (ret < 0) { if (ret == LIBUSB_ERROR_ACCESS) { - ELOG("Could not open USB device %#06x:%#06x, access error.\n", desc.idVendor, desc.idProduct, ret); + ELOG("Could not open USB device %#06x:%#06x, access error.\n", desc.idVendor, desc.idProduct); } else { ELOG("Failed to open USB device %#06x:%#06x, libusb error: %d)\n", desc.idVendor, desc.idProduct, ret); } From d0416149e0761f3a541b0719f76be327bec26337 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sat, 6 Mar 2021 17:36:26 +0100 Subject: [PATCH 168/503] General Project Update - Updated ISSUE_TEMPLATES - Updated .gitignore --- .github/ISSUE_TEMPLATE/bug-report.md | 12 ++++++------ .github/ISSUE_TEMPLATE/feature-request.md | 14 +++++++------- .gitignore | 5 ++++- 3 files changed, 17 insertions(+), 14 deletions(-) diff --git a/.github/ISSUE_TEMPLATE/bug-report.md b/.github/ISSUE_TEMPLATE/bug-report.md index fc30f3993..d76943d1e 100644 --- a/.github/ISSUE_TEMPLATE/bug-report.md +++ b/.github/ISSUE_TEMPLATE/bug-report.md @@ -11,13 +11,13 @@ Thank you for giving feedback to the stlink project. - [ ] I made serious effort to avoid creating duplicate or nearly similar issue -In order to allow developers and other contributors to isolate and target your respective issue, please take some time to fill out each of the following items appropriate to your specific problem: +In order to allow developers and other contributors to isolate and target your respective issue, please take some time to select the check boxes below and edit each item individually appropriate to your specific problem. -- Programmer/board type: [enter here] (e.g Stlink /v1, /v2, /v2-clone, /v2-1) -- Operating system and version: [enter here] (e.g Linux, Mac OS X, Windows) -- **Stlink tools version** and/or git commit hash: [enter here] (e.g v1.1.0/git-c722056) -- Stlink commandline tool name: [enter here] (e.g `st-info`, `st-flash`, `st-util`) -- Target chip (and board if applicable): [enter here] (e.g STM32F402VG) +- [ ] Programmer/board type: (e.g ST-Link/v1, ST-Link/v2, ST-Link/v2-onboard, ST-Link/v3) +- [ ] Operating system: (e.g Linux, Mac OS X, Windows (with specific version)) +- [ ] Stlink tools version and/or git commit hash: (e.g v1.1.0/git-c722056) +- [ ] Stlink commandline tool name: (e.g `st-info`, `st-flash`, `st-util`) +- [ ] Target chip (and optional board): (e.g STM32F402VG (STM32Fxxx Discovery)) Futher we kindly ask you to describe the detected problem as detailed as possible and to add debug output if available, by using the following template: diff --git a/.github/ISSUE_TEMPLATE/feature-request.md b/.github/ISSUE_TEMPLATE/feature-request.md index 133b895b2..c6e236ce1 100644 --- a/.github/ISSUE_TEMPLATE/feature-request.md +++ b/.github/ISSUE_TEMPLATE/feature-request.md @@ -11,15 +11,15 @@ Thank you for giving feedback to the stlink project. - [ ] I made serious effort to avoid creating duplicate or nearly similar issue -In order to allow developers and other contributors to isolate and target your respective issue, please take some time to fill out the check boxes below by setting a 'x' into the checkboxes ( [x] ) and edit each item appropriate to your specific problem. +In order to allow developers and other contributors to isolate and target your respective issue, please take some time to select the check boxes below and edit each item individually appropriate to your specific request. -- [ ] Programmer/board type: e.g Stlink/v1, Stlink/v2, Stlink/v2-onboard -- [ ] Operating system: e.g Linux, Mac OS X, Windows (with specific version) -- [ ] Stlink tools version and/or git commit hash: e.g v1.1.0/git-c722056 -- [ ] Stlink commandline tool name: e.g `st-info`, `st-flash`, `st-util` -- [ ] Target chip (and optional board): e.g STM32F402VG (STM32Fxxx Discovery) +- [ ] Programmer/board type: (e.g ST-Link/v1, ST-Link/v2, ST-Link/v2-onboard, ST-Link/v3) +- [ ] Operating system: (e.g Linux, Mac OS X, Windows (with specific version)) +- [ ] Stlink tools version and/or git commit hash: (e.g v1.1.0/git-c722056) +- [ ] Stlink commandline tool name: (e.g `st-info`, `st-flash`, `st-util`) +- [ ] Target chip (and optional board): (e.g STM32F402VG (STM32Fxxx Discovery)) -Futher we kindly ask you to describe the detected problem as detailled as possible and to add debug output if available, by using the following template: +Futher we kindly ask you to describe the detected problem as detailed as possible and to add debug output if available, by using the following template: Commandline-Output: diff --git a/.gitignore b/.gitignore index 09b9b33de..e753cbe42 100644 --- a/.gitignore +++ b/.gitignore @@ -1,5 +1,8 @@ build build-mingw +.cmake/ +.vscode/ +.project + obj-* *.user* -.project From 29be2cf26a0f9dce79f544d48f30b5dfa0568b98 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Mon, 8 Mar 2021 23:24:45 +0100 Subject: [PATCH 169/503] General Project Update - Updated CHANGELOG.md - Minor formatting & spelling fix - Minor corrections --- CHANGELOG.md | 1 + doc/devices_boards.md | 2 +- doc/flashloaders.md | 2 +- doc/version_support.md | 2 +- 4 files changed, 4 insertions(+), 3 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index ad13e46aa..d304ab616 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -128,6 +128,7 @@ Fixes: * [regression] Fixed sign-compare (size != rep_len) in usb.c ([#772](https://github.com/stlink-org/stlink/pull/772), [#869](https://github.com/stlink-org/stlink/pull/869), [#872](https://github.com/stlink-org/stlink/pull/872), [#891](https://github.com/stlink-org/stlink/pull/891)) * Fixed dead loop after an unexpected unplug ([#780](https://github.com/stlink-org/stlink/pull/780), [#812](https://github.com/stlink-org/stlink/pull/812), [#913](https://github.com/stlink-org/stlink/pull/913)) * Avoid re-define of O_BINARY on Windows ([#788](https://github.com/stlink-org/stlink/pull/788)) +* Fixed stlink lock-up when not connected to a device via JTAG / SWD ([#835](https://github.com/stlink-org/stlink/pull/835), [#943](https://github.com/stlink-org/stlink/pull/943)) * Fixed st-flash manpage read example ([#858](https://github.com/stlink-org/stlink/pull/858)) * Fixed stlink support with no mass storage ([#861](https://github.com/stlink-org/stlink/pull/861)) * Make Version.cmake more error-resistant ([#872](https://github.com/stlink-org/stlink/pull/872)) diff --git a/doc/devices_boards.md b/doc/devices_boards.md index 4402839c5..97094b972 100644 --- a/doc/devices_boards.md +++ b/doc/devices_boards.md @@ -53,7 +53,7 @@ Tested boards [incl. STLink programmers]: | 0x430 | XL-Density | xF xG | | F101 | | F103 | | Tested boards [incl. STLink programmers]: -* STM32VL-Discovery (STM32F100RBT6) with STLink-v1 [v1, v2] +* STM32VL-Discovery (STM32F100RBT6) with STLink-v1 [v1], [v2] * STM32F103-Bluepill: C8Tx & R8xx [v2] * Nucleo-F103RB [v2-1] * HY-STM32 (STM32F103VETx) [v1, v2] diff --git a/doc/flashloaders.md b/doc/flashloaders.md index 6a7cb3504..b1208b6f5 100644 --- a/doc/flashloaders.md +++ b/doc/flashloaders.md @@ -6,7 +6,7 @@ The on-chip FLASH of STM32 needs to be written once a byte/half word/word/double As SRAM is usually less in size than FLASH, `stlink` only flashes one page (may be less if SRAM is insufficient) at a time. The whole flashing process may consist of server launches of flashloaders. -## The flahsing process +## The flashing process 1. `st-flash` loads compiled binary of corresponding flashloader to SRAM by calling `stlink_flash_loader_init` in `src/flash_loader.c` 2. `st-flash` erases corresponding flash page by calling `stlink_erase_flash_page` in `common.c`. diff --git a/doc/version_support.md b/doc/version_support.md index 43c201101..afa2d2bd7 100644 --- a/doc/version_support.md +++ b/doc/version_support.md @@ -21,7 +21,7 @@ Thus no user interaction regarding libusb is necessary. | homebrew | 1.0.23 | 3.17.0 | 3.24.18
gtk+3 | 10.12 (Sierra)- 10.15 (Catalina) | | MacPorts | 1.0.23 | 3.17.0 | 3.24.18
gtk3 | 10.6 (Snow Leopard) - 10.15 (Catalina) | -NOTE: In order to use a STLINK/v1 programmer on macOS, versions 10.13, 10.14 or 10.15 are required. +NOTE: In order to use a STLINK/v1 programmer on macOS, versions 10.14 or 10.15 are required. ### Linux-/Unix-based: From 70f68e1c62d61c970b937b44eb438f2f49b15dc4 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Wed, 10 Mar 2021 16:06:51 +0100 Subject: [PATCH 170/503] Updated travis CI build settings. --- .travis.yml | 285 +++++++++++++++++++++++++++++----------------------- 1 file changed, 157 insertions(+), 128 deletions(-) diff --git a/.travis.yml b/.travis.yml index 17db35765..27fbec5f8 100644 --- a/.travis.yml +++ b/.travis.yml @@ -1,140 +1,169 @@ language: c jobs: - include: - ### 64-bit builds on AMD64 ### - - os: linux - dist: bionic - env: BADGE=linux - compiler: gcc-5 - addons: - apt: - sources: ['ubuntu-toolchain-r-test'] - packages: ['gcc-5', 'libusb-1.0.0-dev', 'libgtk-3-dev', 'rpm'] - - os: linux - dist: bionic - env: BADGE=linux - compiler: gcc-9 - addons: - apt: - sources: ['ubuntu-toolchain-r-test'] - packages: ['gcc-9', 'libusb-1.0.0-dev', 'libgtk-3-dev', 'rpm'] - - os: linux - dist: xenial - env: BADGE=linux - compiler: clang-3.7 - addons: - apt: - sources: ['ubuntu-toolchain-r-test', 'llvm-toolchain-xenial-3.7'] - packages: ['clang-3.7', 'libusb-1.0.0-dev', 'libgtk-3-dev', 'rpm'] - - os: linux - dist: bionic - env: BADGE=linux - compiler: clang-6.0 - addons: - apt: - sources: ['ubuntu-toolchain-r-test', 'llvm-toolchain-bionic-6.0'] - packages: ['clang-6.0', 'libusb-1.0.0-dev', 'libgtk-3-dev', 'rpm'] - - os: linux - dist: bionic - env: BADGE=linux - compiler: clang-9 - addons: - apt: - sources: ['ubuntu-toolchain-r-test'] - packages: ['clang-9', 'libusb-1.0.0-dev', 'libgtk-3-dev', 'rpm'] + include: + ### 64-bit builds on AMD64 ### + - os: linux + dist: bionic + env: BADGE=linux + compiler: gcc-5 + addons: + apt: + sources: ["ubuntu-toolchain-r-test"] + packages: ["gcc-5", "libusb-1.0.0-dev", "libgtk-3-dev", "rpm"] + - os: linux + dist: bionic + env: BADGE=linux + compiler: gcc-9 + addons: + apt: + sources: ["ubuntu-toolchain-r-test"] + packages: ["gcc-9", "libusb-1.0.0-dev", "libgtk-3-dev", "rpm"] + - os: linux + dist: focal + env: BADGE=linux + compiler: gcc-10 + addons: + apt: + sources: ["ubuntu-toolchain-r-test"] + packages: ["gcc-10", "libusb-1.0.0-dev", "libgtk-3-dev", "rpm"] + - os: linux + dist: xenial + env: BADGE=linux + compiler: clang-3.7 + addons: + apt: + sources: ["ubuntu-toolchain-r-test", "llvm-toolchain-xenial-3.7"] + packages: ["clang-3.7", "libusb-1.0.0-dev", "libgtk-3-dev", "rpm"] + - os: linux + dist: bionic + env: BADGE=linux + compiler: clang-6.0 + addons: + apt: + sources: ["ubuntu-toolchain-r-test", "llvm-toolchain-bionic-6.0"] + packages: ["clang-6.0", "libusb-1.0.0-dev", "libgtk-3-dev", "rpm"] + - os: linux + dist: bionic + env: BADGE=linux + compiler: clang-9 + addons: + apt: + sources: ["ubuntu-toolchain-r-test"] + packages: ["clang-9", "libusb-1.0.0-dev", "libgtk-3-dev", "rpm"] + - os: linux + dist: focal + env: BADGE=linux + compiler: clang-10 + addons: + apt: + sources: ["ubuntu-toolchain-r-test"] + packages: ["clang-10", "libusb-1.0.0-dev", "libgtk-3-dev", "rpm"] - - os: linux - dist: bionic - env: BADGE=linux-mingw - name: linux-mingw - compiler: gcc-9 - addons: - apt: - sources: ['ubuntu-toolchain-r-test'] - packages: ['gcc-9', 'libusb-1.0.0-dev', 'libgtk-3-dev', 'rpm', 'mingw-w64'] + - os: linux + dist: bionic + env: BADGE=linux-mingw + name: linux-mingw + compiler: gcc-9 + addons: + apt: + sources: ["ubuntu-toolchain-r-test"] + packages: + ["gcc-9", "libusb-1.0.0-dev", "libgtk-3-dev", "rpm", "mingw-w64"] - ### 32-bit builds on AMD64 ### - - os: linux - dist: bionic - env: BADGE=linux - compiler: gcc-5 - addons: - apt: - sources: ['ubuntu-toolchain-r-test'] - packages: ['gcc-5', 'libusb-1.0.0-dev', 'libgtk-3-dev', 'rpm'] - before_install: - - CFLAGS="$CFLAGS -m32"; CXXFLAGS="$CXXFLAGS -m32"; LDFLAGS="$LDFLAGS -m32"; - - os: linux - dist: bionic - env: BADGE=linux - compiler: gcc-9 - addons: - apt: - sources: ['ubuntu-toolchain-r-test'] - packages: ['gcc-9', 'libusb-1.0.0-dev', 'libgtk-3-dev', 'rpm'] - before_install: - - CFLAGS="$CFLAGS -m32"; CXXFLAGS="$CXXFLAGS -m32"; LDFLAGS="$LDFLAGS -m32"; - - os: linux - dist: xenial - env: BADGE=linux - compiler: clang-3.7 - addons: - apt: - sources: ['ubuntu-toolchain-r-test', 'llvm-toolchain-xenial-3.7'] - packages: ['clang-3.7', 'libusb-1.0.0-dev', 'libgtk-3-dev', 'rpm'] - before_install: - - CFLAGS="$CFLAGS -m32"; CXXFLAGS="$CXXFLAGS -m32"; LDFLAGS="$LDFLAGS -m32"; - - os: linux - dist: bionic - env: BADGE=linux - compiler: clang-6.0 - addons: - apt: - sources: ['ubuntu-toolchain-r-test', 'llvm-toolchain-bionic-6.0'] - packages: ['clang-6.0', 'libusb-1.0.0-dev', 'libgtk-3-dev', 'rpm'] - before_install: - - CFLAGS="$CFLAGS -m32"; CXXFLAGS="$CXXFLAGS -m32"; LDFLAGS="$LDFLAGS -m32"; - - os: linux - dist: bionic - env: BADGE=linux - compiler: clang-9 - addons: - apt: - sources: ['ubuntu-toolchain-r-test'] - packages: ['clang-9', 'libusb-1.0.0-dev', 'libgtk-3-dev', 'rpm'] - before_install: - - CFLAGS="$CFLAGS -m32"; CXXFLAGS="$CXXFLAGS -m32"; LDFLAGS="$LDFLAGS -m32"; + ### 32-bit builds on AMD64 ### + - os: linux + dist: bionic + env: BADGE=linux + compiler: gcc-5 + addons: + apt: + sources: ["ubuntu-toolchain-r-test"] + packages: ["gcc-5", "libusb-1.0.0-dev", "libgtk-3-dev", "rpm"] + before_install: + - CFLAGS="$CFLAGS -m32"; CXXFLAGS="$CXXFLAGS -m32"; LDFLAGS="$LDFLAGS -m32"; + - os: linux + dist: bionic + env: BADGE=linux + compiler: gcc-9 + addons: + apt: + sources: ["ubuntu-toolchain-r-test"] + packages: ["gcc-9", "libusb-1.0.0-dev", "libgtk-3-dev", "rpm"] + before_install: + - CFLAGS="$CFLAGS -m32"; CXXFLAGS="$CXXFLAGS -m32"; LDFLAGS="$LDFLAGS -m32"; + - os: linux + dist: focal + env: BADGE=linux + compiler: gcc-10 + addons: + apt: + sources: ["ubuntu-toolchain-r-test"] + packages: ["gcc-10", "libusb-1.0.0-dev", "libgtk-3-dev", "rpm"] + before_install: + - CFLAGS="$CFLAGS -m32"; CXXFLAGS="$CXXFLAGS -m32"; LDFLAGS="$LDFLAGS -m32"; + - os: linux + dist: xenial + env: BADGE=linux + compiler: clang-3.7 + addons: + apt: + sources: ["ubuntu-toolchain-r-test", "llvm-toolchain-xenial-3.7"] + packages: ["clang-3.7", "libusb-1.0.0-dev", "libgtk-3-dev", "rpm"] + before_install: + - CFLAGS="$CFLAGS -m32"; CXXFLAGS="$CXXFLAGS -m32"; LDFLAGS="$LDFLAGS -m32"; + - os: linux + dist: bionic + env: BADGE=linux + compiler: clang-6.0 + addons: + apt: + sources: ["ubuntu-toolchain-r-test", "llvm-toolchain-bionic-6.0"] + packages: ["clang-6.0", "libusb-1.0.0-dev", "libgtk-3-dev", "rpm"] + before_install: + - CFLAGS="$CFLAGS -m32"; CXXFLAGS="$CXXFLAGS -m32"; LDFLAGS="$LDFLAGS -m32"; + - os: linux + dist: bionic + env: BADGE=linux + compiler: clang-9 + addons: + apt: + sources: ["ubuntu-toolchain-r-test"] + packages: ["clang-9", "libusb-1.0.0-dev", "libgtk-3-dev", "rpm"] + before_install: + - os: linux + dist: focal + env: BADGE=linux + compiler: clang-10 + addons: + apt: + sources: ["ubuntu-toolchain-r-test"] + packages: ["clang-10", "libusb-1.0.0-dev", "libgtk-3-dev", "rpm"] + before_install: + - CFLAGS="$CFLAGS -m32"; CXXFLAGS="$CXXFLAGS -m32"; LDFLAGS="$LDFLAGS -m32"; - - ### macOS ### - - os: osx - env: BADGE=osx - compiler: gcc - addons: - homebrew: - packages: - - gcc - - libusb - - gtk+3 - - os: osx - env: BADGE=osx - compiler: clang - addons: - homebrew: - packages: - - clang - - libusb - - gtk+3 - - ### Windows ### -# - os: windows -# env: BADGE=windows -# compiler: gcc + ### macOS ### + - os: osx + env: BADGE=osx + compiler: gcc + addons: + homebrew: + packages: + - gcc + - libusb + - gtk+3 + - os: osx + env: BADGE=osx + compiler: clang + addons: + homebrew: + packages: + - clang + - libusb + - gtk+3 script: - git fetch --tags - printenv - cmake --version - if [[ "$TRAVIS_OS_NAME" == "linux" ]] || [[ "$TRAVIS_OS_NAME" == "osx" ]]; then ./.travis.sh; fi -# - if [[ "$TRAVIS_OS_NAME" == "windows" ]]; then cmd.exe /C 'mingw64-build.bat'; fi From 8429ac078a783ee6d75db6bd8741eba732959c54 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Wed, 10 Mar 2021 16:09:10 +0100 Subject: [PATCH 171/503] Update and correction for compiling instructions --- doc/compiling.md | 57 ++++++++++++++++++++++-------------------------- 1 file changed, 26 insertions(+), 31 deletions(-) diff --git a/doc/compiling.md b/doc/compiling.md index d8cb62ebb..07193f357 100644 --- a/doc/compiling.md +++ b/doc/compiling.md @@ -108,54 +108,50 @@ or execute (Debian-based systems only): `apt-get install gcc build-essential cma ### Building +#### Installation: + 1. Change into the project source directory: `cd stlink` 2. Run `make clean` -- required by some linux variants. 3. Run `make release` to create the _Release_ target -4. Run `make debug` to create the _Debug_ target (_optional_)
+4. Run `make install` to full install the package with complete system integration +5. Run `make debug` to create the _Debug_ target (_optional_)
The debug target is only necessary in order to modify the sources and to run under a debugger. +6. Run `make package`to build a Debian Package. The generated packages can be found in the subdirectory `./build/dist`. -The top level Makefile is just a handy wrapper for: +As an option you may also install to an individual user-defined folder e.g `$HOME` with `make install DESTDIR=$HOME`. -##### MinGW64: -```sh -$ mkdir build && cd build -$ cmake -DCMAKE_BUILD_TYPE=release -DCMAKE_TOOLCHAIN_FILE=./cmake/linux-mingw64.cmake -S .. -$ make -``` +#### Removal: -##### MinGW32: +1. Run `make uninstall` to perform a clean uninstall of the package from the system. +2. Run `make clean` to clean the build-folder within the project source and remove all compiled and linked files and libraries. -```sh -$ mkdir build && cd build -$ cmake -DCMAKE_BUILD_TYPE=release -DCMAKE_TOOLCHAIN_FILE=./cmake/linux-mingw32.cmake -S .. -$ make -``` - -As an alternative you may also install -- to a user folder e.g `$HOME` with `cd build/Release && make install DESTDIR=$HOME` -- or system wide with `cd build/Release && sudo make install`. -When installing system-wide, the dynamic library cache needs to be updated with the command `ldconfig`. +### Cross-Building for Windows +Install the following packages from your package repository: -### Build a Debian Package +* `mingw-w64` +* `mingw-w64-common` +* `mingw-w64-i686-dev` +* `mingw-w64-x86-64-dev` -To build the debian package you need the following extra packages: `devscripts debhelper`. +After following the steps for installation above, proceed with from the build dircetory itself: ```sh -$ git archive --prefix=$(git describe)/ HEAD | bzip2 --stdout > ../libstlink_$(sed -En -e "s/.*\((.*)\).*/\1/" -e "1,1 p" debian/changelog).orig.tar.bz2 -$ debuild -uc -us +$ sudo sh ./cmake/packaging/windows/generate_binaries.sh ``` +The generated zip-packages can be found in the subdirectory `./build/dist`. + -### Set permissions with udev +### Set device access permissions and the role of udev By default most distributions don't allow access to USB devices. -Therefore make sure you install udev files which are necessary to run the tools without root permissions.
-udev rules create devices nodes and set the group of these to `stlink`. +In this context udev rules, which create devices nodes, are necessary to run the tools without root permissions. +To achieve this you need to ensure that the group `plugdev` exists and the user who is trying to access these devices is a member of this group. -The rules are located in the subdirectory `config/udev/rules.d` within the sourcefolder and are automatically installed along with `sudo make install` on linux. +Within the sourcefolder of the project, these rules are located in the subdirectory `config/udev/rules.d` and are automatically installed along with `sudo make install` on linux. Afterwards it may be necessary to reload the udev rules: ```sh @@ -164,13 +160,12 @@ $ sudo udevadm control --reload-rules $ sudo udevadm trigger ``` -Udev will now create device node files `/dev/stlinkv2_XX`, `/dev/stlinkv1_XX`.
-You need to ensure that the group `stlink` exists and the user who is trying to access these devices is a member of this group. +udev will now create device node files, e.g. `/dev/stlinkv3_XX`, `/dev/stlinkv2_XX`, `/dev/stlinkv1_XX`. -### Note on the use of STLink-v1 programmers (legacy): +### Special note on the use of STLink/V1 programmers (legacy): -As the STLINKv1's SCSI emulation is somehow broken, the best advice possibly is to tell your operating system to completely ignore it.
+As the STLINKV1's SCSI emulation is somehow broken, the best advice possibly is to tell your operating system to completely ignore it.
Choose one of the following options _before_ connecting the device to your computer: * `modprobe -r usb-storage && modprobe usb-storage quirks=483:3744:i` From dc6310b469132b2d4210de5fa266571c81df3d82 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Wed, 10 Mar 2021 16:45:57 +0100 Subject: [PATCH 172/503] Updated travis CI build settings - covered active Ubuntu LTS version trees - gcc: 5 / 6 / 10 - clang: 8 / 10 --- .travis.yml | 51 ++++++++++++++++++--------------------------------- 1 file changed, 18 insertions(+), 33 deletions(-) diff --git a/.travis.yml b/.travis.yml index 27fbec5f8..4437b3148 100644 --- a/.travis.yml +++ b/.travis.yml @@ -4,7 +4,7 @@ jobs: include: ### 64-bit builds on AMD64 ### - os: linux - dist: bionic + dist: xenial env: BADGE=linux compiler: gcc-5 addons: @@ -14,11 +14,11 @@ jobs: - os: linux dist: bionic env: BADGE=linux - compiler: gcc-9 + compiler: gcc-6 addons: apt: sources: ["ubuntu-toolchain-r-test"] - packages: ["gcc-9", "libusb-1.0.0-dev", "libgtk-3-dev", "rpm"] + packages: ["gcc-6", "libusb-1.0.0-dev", "libgtk-3-dev", "rpm"] - os: linux dist: focal env: BADGE=linux @@ -30,27 +30,19 @@ jobs: - os: linux dist: xenial env: BADGE=linux - compiler: clang-3.7 + compiler: clang-8 addons: apt: sources: ["ubuntu-toolchain-r-test", "llvm-toolchain-xenial-3.7"] - packages: ["clang-3.7", "libusb-1.0.0-dev", "libgtk-3-dev", "rpm"] - - os: linux - dist: bionic - env: BADGE=linux - compiler: clang-6.0 - addons: - apt: - sources: ["ubuntu-toolchain-r-test", "llvm-toolchain-bionic-6.0"] - packages: ["clang-6.0", "libusb-1.0.0-dev", "libgtk-3-dev", "rpm"] + packages: ["clang-8", "libusb-1.0.0-dev", "libgtk-3-dev", "rpm"] - os: linux dist: bionic env: BADGE=linux - compiler: clang-9 + compiler: clang-10 addons: apt: sources: ["ubuntu-toolchain-r-test"] - packages: ["clang-9", "libusb-1.0.0-dev", "libgtk-3-dev", "rpm"] + packages: ["clang-10", "libusb-1.0.0-dev", "libgtk-3-dev", "rpm"] - os: linux dist: focal env: BADGE=linux @@ -60,20 +52,21 @@ jobs: sources: ["ubuntu-toolchain-r-test"] packages: ["clang-10", "libusb-1.0.0-dev", "libgtk-3-dev", "rpm"] + ### cross build on AMD64 ### - os: linux - dist: bionic + dist: focal env: BADGE=linux-mingw name: linux-mingw - compiler: gcc-9 + compiler: gcc-10 addons: apt: sources: ["ubuntu-toolchain-r-test"] packages: - ["gcc-9", "libusb-1.0.0-dev", "libgtk-3-dev", "rpm", "mingw-w64"] + ["gcc-10", "libusb-1.0.0-dev", "libgtk-3-dev", "rpm", "mingw-w64"] ### 32-bit builds on AMD64 ### - os: linux - dist: bionic + dist: xenial env: BADGE=linux compiler: gcc-5 addons: @@ -85,11 +78,11 @@ jobs: - os: linux dist: bionic env: BADGE=linux - compiler: gcc-9 + compiler: gcc-6 addons: apt: sources: ["ubuntu-toolchain-r-test"] - packages: ["gcc-9", "libusb-1.0.0-dev", "libgtk-3-dev", "rpm"] + packages: ["gcc-6", "libusb-1.0.0-dev", "libgtk-3-dev", "rpm"] before_install: - CFLAGS="$CFLAGS -m32"; CXXFLAGS="$CXXFLAGS -m32"; LDFLAGS="$LDFLAGS -m32"; - os: linux @@ -105,31 +98,23 @@ jobs: - os: linux dist: xenial env: BADGE=linux - compiler: clang-3.7 + compiler: clang-8 addons: apt: sources: ["ubuntu-toolchain-r-test", "llvm-toolchain-xenial-3.7"] - packages: ["clang-3.7", "libusb-1.0.0-dev", "libgtk-3-dev", "rpm"] + packages: ["clang-8", "libusb-1.0.0-dev", "libgtk-3-dev", "rpm"] before_install: - CFLAGS="$CFLAGS -m32"; CXXFLAGS="$CXXFLAGS -m32"; LDFLAGS="$LDFLAGS -m32"; - os: linux dist: bionic env: BADGE=linux - compiler: clang-6.0 + compiler: clang-10 addons: apt: sources: ["ubuntu-toolchain-r-test", "llvm-toolchain-bionic-6.0"] - packages: ["clang-6.0", "libusb-1.0.0-dev", "libgtk-3-dev", "rpm"] + packages: ["clang-10", "libusb-1.0.0-dev", "libgtk-3-dev", "rpm"] before_install: - CFLAGS="$CFLAGS -m32"; CXXFLAGS="$CXXFLAGS -m32"; LDFLAGS="$LDFLAGS -m32"; - - os: linux - dist: bionic - env: BADGE=linux - compiler: clang-9 - addons: - apt: - sources: ["ubuntu-toolchain-r-test"] - packages: ["clang-9", "libusb-1.0.0-dev", "libgtk-3-dev", "rpm"] before_install: - os: linux dist: focal From 8f9c5430cbf70192a4b3072b2ba690800cc0d306 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Wed, 10 Mar 2021 23:57:10 +0100 Subject: [PATCH 173/503] Updated changelog --- CHANGELOG.md | 600 +++++++++++++++++++++++++-------------------------- 1 file changed, 292 insertions(+), 308 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index d304ab616..c4adaf2ba 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -1,51 +1,49 @@ -stlink ChangeLog -================ +# stlink ChangeLog -v1.6.2 -====== +# v1.6.2 Release date: (TBD) Features: -* Added support for STM32H742/743/753 ([#671](https://github.com/stlink-org/stlink/pull/671), [#793](https://github.com/stlink-org/stlink/pull/793), [#823](https://github.com/stlink-org/stlink/pull/823), [#998](https://github.com/stlink-org/stlink/pull/998), [#1052](https://github.com/stlink-org/stlink/pull/1052)) -* Added preliminary support for STM32L5x2 ([#904](https://github.com/stlink-org/stlink/pull/904), [#999](https://github.com/stlink-org/stlink/pull/999)) -* Option bytes on the STM32F767 ZIT6 Nucleo-144 ([#968](https://github.com/stlink-org/stlink/pull/968), [#997](https://github.com/stlink-org/stlink/pull/997)) -* Use SetConsoleCtrlHandler for Windows ([#1021](https://github.com/stlink-org/stlink/pull/1021)) -* Increase STM32L0 option_size to 20 ([#1046](https://github.com/stlink-org/stlink/pull/1046)) -* st-util: Add specialized memory map for STM32H7 devices ([#1060](https://github.com/stlink-org/stlink/pull/1060)) -* Support for STM32F4 option bytes ([#1062](https://github.com/stlink-org/stlink/pull/1062)) -* Link for WIN32 & APPLE with stlink-static ([#1069](https://github.com/stlink-org/stlink/pull/1069)) -* Extended support for STM32H7 ([#1059](https://github.com/stlink-org/stlink/pull/1059), [#1063](https://github.com/stlink-org/stlink/pull/1063), [#1071](https://github.com/stlink-org/stlink/pull/1071)) -* ITM functionality for ST-Link V2 and STM32Fxx chipsets ([#136](https://github.com/stlink-org/stlink/pull/136), [#179](https://github.com/stlink-org/stlink/pull/179), [#815](https://github.com/stlink-org/stlink/pull/815), [#1072](https://github.com/stlink-org/stlink/pull/1072)) +- Added support for STM32H742/743/753 ([#671](https://github.com/stlink-org/stlink/pull/671), [#793](https://github.com/stlink-org/stlink/pull/793), [#823](https://github.com/stlink-org/stlink/pull/823), [#998](https://github.com/stlink-org/stlink/pull/998), [#1052](https://github.com/stlink-org/stlink/pull/1052)) +- Added preliminary support for STM32L5x2 ([#904](https://github.com/stlink-org/stlink/pull/904), [#999](https://github.com/stlink-org/stlink/pull/999)) +- Option bytes on the STM32F767 ZIT6 Nucleo-144 ([#968](https://github.com/stlink-org/stlink/pull/968), [#997](https://github.com/stlink-org/stlink/pull/997)) +- Use SetConsoleCtrlHandler for Windows ([#1021](https://github.com/stlink-org/stlink/pull/1021)) +- Increase STM32L0 `option_size` to 20 ([#1046](https://github.com/stlink-org/stlink/pull/1046)) +- `st-util`: Add specialized memory map for STM32H7 devices ([#1060](https://github.com/stlink-org/stlink/pull/1060)) +- Support for STM32F4 option bytes ([#1062](https://github.com/stlink-org/stlink/pull/1062)) +- Link for WIN32 & APPLE with stlink-static ([#1069](https://github.com/stlink-org/stlink/pull/1069)) +- Extended support for STM32H7 ([#1059](https://github.com/stlink-org/stlink/pull/1059), [#1063](https://github.com/stlink-org/stlink/pull/1063), [#1071](https://github.com/stlink-org/stlink/pull/1071)) +- ITM functionality for STLink/V2 and STM32Fxx chipsets ([#136](https://github.com/stlink-org/stlink/pull/136), [#179](https://github.com/stlink-org/stlink/pull/179), [#815](https://github.com/stlink-org/stlink/pull/815), [#1072](https://github.com/stlink-org/stlink/pull/1072)) Updates & changes: -* [doc] st-flash --reset parameter (one solution for #356) ([#642](https://github.com/stlink-org/stlink/pull/642)) -* [refactoring] General maintenance ([#864](https://github.com/stlink-org/stlink/pull/864), [#976](https://github.com/stlink-org/stlink/pull/976), [#978](https://github.com/stlink-org/stlink/pull/978)) -* Imported debian pkg-settings ([#986](https://github.com/stlink-org/stlink/pull/986)) -* Add support for FreeBSD's libusb reimplementation ([#992](https://github.com/stlink-org/stlink/pull/992), [#993](https://github.com/stlink-org/stlink/pull/993)) -* [doc] Added example for output of 'st-info --probe' ([#1007](https://github.com/stlink-org/stlink/pull/1007), [#1049](https://github.com/stlink-org/stlink/pull/1049)) +- [doc] `st-flash --reset` parameter (one solution for #356) ([#642](https://github.com/stlink-org/stlink/pull/642)) +- [refactoring] General maintenance ([#864](https://github.com/stlink-org/stlink/pull/864), [#976](https://github.com/stlink-org/stlink/pull/976), [#978](https://github.com/stlink-org/stlink/pull/978)) +- Imported debian pkg-settings ([#986](https://github.com/stlink-org/stlink/pull/986)) +- Add support for FreeBSD's `libusb` reimplementation ([#992](https://github.com/stlink-org/stlink/pull/992), [#993](https://github.com/stlink-org/stlink/pull/993)) +- [doc] Added example for output of `st-info --probe` ([#1007](https://github.com/stlink-org/stlink/pull/1007), [#1049](https://github.com/stlink-org/stlink/pull/1049)) Fixes: -* [regression] Changed timeout on flash write ([#787](https://github.com/stlink-org/stlink/pull/787), [#981](https://github.com/stlink-org/stlink/pull/981), [#987](https://github.com/stlink-org/stlink/pull/987)) -* cmake compile failure with external CMAKE_MODULE_PATH set ([#962](https://github.com/stlink-org/stlink/pull/962)) -* doc/man: Fixed installation directory ([#970](https://github.com/stlink-org/stlink/pull/970)) -* Fixed installation path for desktop-file and icons ([#972](https://github.com/stlink-org/stlink/pull/972)) -* Fix for static linking of libssp ([#973](https://github.com/stlink-org/stlink/pull/973), [#974](https://github.com/stlink-org/stlink/pull/974)) -* Fixed connect under reset for st-flash and st-util ([#983](https://github.com/stlink-org/stlink/pull/983)) -* Fix for mmap() size_t overflow in st-flash ([#988](https://github.com/stlink-org/stlink/pull/988), [#989](https://github.com/stlink-org/stlink/pull/989)) -* [regression] stlink-gui installation issue on Ubuntu-18.04 ([#1001](https://github.com/stlink-org/stlink/pull/1001), [#1004](https://github.com/stlink-org/stlink/pull/1004), [#1006](https://github.com/stlink-org/stlink/pull/1006)) -* st-util: wrong register values passed to gdb (st-link v2) ([#1002](https://github.com/stlink-org/stlink/pull/1002), [#1011](https://github.com/stlink-org/stlink/pull/1011), [#1026](https://github.com/stlink-org/stlink/pull/1026), [#1027](https://github.com/stlink-org/stlink/pull/1027)) -* [doc] Fixed wrong path for rules.d folder ([#1020](https://github.com/stlink-org/stlink/pull/1020)) -* Use vl flashloader for all STM32F1 series ([#1041](https://github.com/stlink-org/stlink/pull/1041), [#1044](https://github.com/stlink-org/stlink/pull/1044)) -* Fixed gettimeofday for MSVC ([#1074](https://github.com/stlink-org/stlink/pull/1074)) -* Fixed compilation with GCC 11 ([#1077](https://github.com/stlink-org/stlink/pull/1077)) - - -v1.6.1 -====== +- [regression] Changed timeout on flash write ([#787](https://github.com/stlink-org/stlink/pull/787), [#981](https://github.com/stlink-org/stlink/pull/981), [#987](https://github.com/stlink-org/stlink/pull/987)) +- cmake compile failure with external `CMAKE_MODULE_PATH` set ([#962](https://github.com/stlink-org/stlink/pull/962)) +- doc/man: Fixed installation directory ([#970](https://github.com/stlink-org/stlink/pull/970)) +- Fixed installation path for desktop-file and icons ([#972](https://github.com/stlink-org/stlink/pull/972)) +- Fix for static linking of `libssp` ([#973](https://github.com/stlink-org/stlink/pull/973), [#974](https://github.com/stlink-org/stlink/pull/974)) +- [regression] Fixed wrong formatting for library install path ([#978](https://github.com/stlink-org/stlink/pull/978), [#1089](https://github.com/stlink-org/stlink/pull/1089)) +- Fixed installation of header files needed for compiling with `libstlink.so.1.6.1` ([#982](https://github.com/stlink-org/stlink/pull/982)) +- Fixed `connect under reset` for `st-flash` and `st-util` ([#983](https://github.com/stlink-org/stlink/pull/983)) +- Fix for `mmap() size_t overflow` in `st-flash` ([#988](https://github.com/stlink-org/stlink/pull/988), [#989](https://github.com/stlink-org/stlink/pull/989)) +- [regression] `stlink-gui` installation issue on Ubuntu-18.04 ([#1001](https://github.com/stlink-org/stlink/pull/1001), [#1004](https://github.com/stlink-org/stlink/pull/1004), [#1006](https://github.com/stlink-org/stlink/pull/1006)) +- `st-util`: wrong register values passed to `gdb` (STLink/V2) ([#1002](https://github.com/stlink-org/stlink/pull/1002), [#1011](https://github.com/stlink-org/stlink/pull/1011), [#1026](https://github.com/stlink-org/stlink/pull/1026), [#1027](https://github.com/stlink-org/stlink/pull/1027)) +- [doc] Fixed wrong path for `rules.d` folder ([#1020](https://github.com/stlink-org/stlink/pull/1020)) +- Use vl flashloader for all STM32F1 series ([#1041](https://github.com/stlink-org/stlink/pull/1041), [#1044](https://github.com/stlink-org/stlink/pull/1044)) +- Fixed `gettimeofday` for MSVC ([#1074](https://github.com/stlink-org/stlink/pull/1074)) +- Fixed compilation with GCC 11 ([#1077](https://github.com/stlink-org/stlink/pull/1077)) + +# v1.6.1 Release date: 2020-06-01 @@ -53,364 +51,350 @@ This release drops support for some older operating systems. Check project READM Features: -* Basic compatibility for STLink-v3 programmer ([#271](https://github.com/stlink-org/stlink/pull/271), [#863](https://github.com/stlink-org/stlink/pull/863), [#954](https://github.com/stlink-org/stlink/pull/954)) +- Basic compatibility for STLink/V3 programmer ([#271](https://github.com/stlink-org/stlink/pull/271), [#863](https://github.com/stlink-org/stlink/pull/863), [#954](https://github.com/stlink-org/stlink/pull/954)) - Added support for JTAG command API v2 & distinguish protocol versions v1 and v2 - - Compatibility with the STLink-v3 firmware which dropped support for the previous API v1 - - As of firmware version J11 the ST-LINK-V1 programmer supports API v2 commands as well -* Display programmer serial when no target is connected ([#432](https://github.com/stlink-org/stlink/pull/432), [#933](https://github.com/stlink-org/stlink/pull/933), [#943](https://github.com/stlink-org/stlink/pull/943)) -* Added connect under reset to stlink_open_usb( ) ([#577](https://github.com/stlink-org/stlink/pull/577), [#963](https://github.com/stlink-org/stlink/pull/963)) -* Support for STM32L1, SM32L4 option bytes write ([#596](https://github.com/stlink-org/stlink/pull/596), [#844](https://github.com/stlink-org/stlink/pull/844), [#847](https://github.com/stlink-org/stlink/pull/847)) -* Added CMAKEFLAGS and install target ([#804](https://github.com/stlink-org/stlink/pull/804), [#935](https://github.com/stlink-org/stlink/pull/935)) -* Support for STM32G4 ([#822](https://github.com/stlink-org/stlink/pull/822)) -* Added aliased SRAM2 region in the L496 memory map ([#824](https://github.com/stlink-org/stlink/pull/824)) -* Improved support for STM32G0 ([#825](https://github.com/stlink-org/stlink/pull/825), [#850](https://github.com/stlink-org/stlink/pull/850), [#856](https://github.com/stlink-org/stlink/pull/856), [#857](https://github.com/stlink-org/stlink/pull/857)) -* Added postinst script with 'depmod -a' for 'make package' ([#845](https://github.com/stlink-org/stlink/pull/845), [#931](https://github.com/stlink-org/stlink/pull/931)) -* Calculate checksums for flash operations ([#862](https://github.com/stlink-org/stlink/pull/862), [#924](https://github.com/stlink-org/stlink/pull/924)) -* Adjust the JTAG/SWD frequency via cmdline option ([#893](https://github.com/stlink-org/stlink/pull/893), [#953](https://github.com/stlink-org/stlink/pull/953)) -* Added usb PID and udev rules for STlink v2.1 found on Nucleo-L432KC and Nucleo-L552ze boards ([#900](https://github.com/stlink-org/stlink/pull/900)) -* STM32G0/G4 improvements ([#910](https://github.com/stlink-org/stlink/pull/910)) + - Compatibility with the STLink/V3 firmware which dropped support for the previous API v1 + - As of firmware version J11 the STLink/V1 programmer supports API v2 commands as well +- Display programmer serial when no target is connected ([#432](https://github.com/stlink-org/stlink/pull/432), [#933](https://github.com/stlink-org/stlink/pull/933), [#943](https://github.com/stlink-org/stlink/pull/943)) +- Added `connect under reset` to `stlink_open_usb( )` ([#577](https://github.com/stlink-org/stlink/pull/577), [#963](https://github.com/stlink-org/stlink/pull/963)) +- Support for STM32L1, SM32L4 option bytes write ([#596](https://github.com/stlink-org/stlink/pull/596), [#844](https://github.com/stlink-org/stlink/pull/844), [#847](https://github.com/stlink-org/stlink/pull/847)) +- Added `CMAKEFLAGS` and install target ([#804](https://github.com/stlink-org/stlink/pull/804), [#935](https://github.com/stlink-org/stlink/pull/935)) +- Support for STM32G4 ([#822](https://github.com/stlink-org/stlink/pull/822)) +- Added aliased SRAM2 region in the L496 memory map ([#824](https://github.com/stlink-org/stlink/pull/824)) +- Improved support for STM32G0 ([#825](https://github.com/stlink-org/stlink/pull/825), [#850](https://github.com/stlink-org/stlink/pull/850), [#856](https://github.com/stlink-org/stlink/pull/856), [#857](https://github.com/stlink-org/stlink/pull/857)) +- Added postinst script with `depmod -a` for `make package` ([#845](https://github.com/stlink-org/stlink/pull/845), [#931](https://github.com/stlink-org/stlink/pull/931)) +- Calculate checksums for flash operations ([#862](https://github.com/stlink-org/stlink/pull/862), [#924](https://github.com/stlink-org/stlink/pull/924)) +- Adjust the JTAG/SWD frequency via cmdline option ([#893](https://github.com/stlink-org/stlink/pull/893), [#953](https://github.com/stlink-org/stlink/pull/953)) +- Added usb PID and udev rules for STLink/V2.1 found on Nucleo-L432KC and Nucleo-L552ze boards ([#900](https://github.com/stlink-org/stlink/pull/900)) +- STM32G0/G4 improvements ([#910](https://github.com/stlink-org/stlink/pull/910)) - Enable mass erase with a flash programming check - Handle G4 Cat3 devices with configurable dual bank flash by using a helper Updates & changes: -* [doc] Updated compiling instructions ([#113](https://github.com/stlink-org/stlink/pull/113), commit [#10ae529](https://github.com/stlink-org/stlink/commit/10ae5294cd03aacfc07312010f026d3cb12ea56c)) -* Defined libusb version compatibility for supported systems via LIBUSB_API_VERSION ([#211](https://github.com/stlink-org/stlink/pull/211), [#782](https://github.com/stlink-org/stlink/pull/782), [#895](https://github.com/stlink-org/stlink/pull/895)) -* Improved argument parsing for CLI tools ([#378](https://github.com/stlink-org/stlink/pull/378), [#922](https://github.com/stlink-org/stlink/pull/922)) -* [doc] Updated tutorial: macOS ST-Link-v1 detection ([#574](https://github.com/stlink-org/stlink/pull/574), [#587](https://github.com/stlink-org/stlink/pull/587)) -* Enhanced error log with file path for map_file() ([#650](https://github.com/stlink-org/stlink/pull/650), [#879](https://github.com/stlink-org/stlink/pull/879), [#921](https://github.com/stlink-org/stlink/pull/921)) -* Enhanced output for error msg "addr not a multiple of pagesize, not supported" ([#663](https://github.com/stlink-org/stlink/pull/663), [#945](https://github.com/stlink-org/stlink/pull/945)) -* Updated STLink-v1 driver for macOS ([#735](https://github.com/stlink-org/stlink/pull/735), [#964](https://github.com/stlink-org/stlink/pull/964)) -* Package distribution: Provide Windows binaries via Debian-based cross-build ([#738](https://github.com/stlink-org/stlink/pull/738), [#795](https://github.com/stlink-org/stlink/pull/795), [#798](https://github.com/stlink-org/stlink/pull/798), [#870](https://github.com/stlink-org/stlink/pull/870), [#955](https://github.com/stlink-org/stlink/pull/955)) +- [doc] Updated compiling instructions ([#113](https://github.com/stlink-org/stlink/pull/113), commit [#10ae529](https://github.com/stlink-org/stlink/commit/10ae5294cd03aacfc07312010f026d3cb12ea56c)) +- Defined `libusb` version compatibility for supported systems via `LIBUSB_API_VERSION` ([#211](https://github.com/stlink-org/stlink/pull/211), [#782](https://github.com/stlink-org/stlink/pull/782), [#895](https://github.com/stlink-org/stlink/pull/895)) +- Improved argument parsing for CLI tools ([#378](https://github.com/stlink-org/stlink/pull/378), [#922](https://github.com/stlink-org/stlink/pull/922)) +- [doc] Updated tutorial: macOS STLink/V1 detection ([#574](https://github.com/stlink-org/stlink/pull/574), [#587](https://github.com/stlink-org/stlink/pull/587)) +- Enhanced error log with file path for `map_file()` ([#650](https://github.com/stlink-org/stlink/pull/650), [#879](https://github.com/stlink-org/stlink/pull/879), [#921](https://github.com/stlink-org/stlink/pull/921)) +- Enhanced output for error msg `addr not a multiple of pagesize, not supported` ([#663](https://github.com/stlink-org/stlink/pull/663), [#945](https://github.com/stlink-org/stlink/pull/945)) +- Updated STLink/V1 driver for macOS ([#735](https://github.com/stlink-org/stlink/pull/735), [#964](https://github.com/stlink-org/stlink/pull/964)) +- Package distribution: Provide Windows binaries via Debian-based cross-build ([#738](https://github.com/stlink-org/stlink/pull/738), [#795](https://github.com/stlink-org/stlink/pull/795), [#798](https://github.com/stlink-org/stlink/pull/798), [#870](https://github.com/stlink-org/stlink/pull/870), [#955](https://github.com/stlink-org/stlink/pull/955)) - [refactoring] Update, corrections & cleanup for build settings (see #955 for details) - - New cpack package-config for DEB and RPM build - - Update for travis build configuration: builds for clang -m32, clang-9, MinGW-cross on linux + - New `cpack` package-config for DEB and RPM build + - Update for travis build configuration: builds for `clang -m32`, `clang-9`, MinGW-cross on linux - Updated steps for release preparation - Project contributors now listed in separate file - - Test files & gui now use shared stlink-library -* [doc] Verify correct udev configuration for device access ([#764](https://github.com/stlink-org/stlink/pull/764)) -* Added more error info to WLOGs during probe ([#883](https://github.com/stlink-org/stlink/pull/883)) -* [doc] Added missing documentation for stlink-gui ([#884](https://github.com/stlink-org/stlink/pull/884)) -* Added check for libssp during compilation ([#885](https://github.com/stlink-org/stlink/pull/885)) -* Silenced unnecessary messages ([#886](https://github.com/stlink-org/stlink/pull/886)) -* [doc] Defined libusb & cmake version compatibility ([#896](https://github.com/stlink-org/stlink/pull/896), [#897](https://github.com/stlink-org/stlink/pull/897), [#899](https://github.com/stlink-org/stlink/pull/899), commit [#27aa888](https://github.com/stlink-org/stlink/commit/27aa88821197d3ffe82baff4e971c3488ec39899)) -* Update for STM32G471/473/474/483/484 devices ([#901](https://github.com/stlink-org/stlink/pull/901)) -* [doc] st-flash --flash=n[k][m] command line option to override device model ([#902](https://github.com/stlink-org/stlink/pull/902)) -* [refactoring] Improved cmake build process ([#912](https://github.com/stlink-org/stlink/pull/912)) - - Set up a libusb log level accordingly to verbosity ([#894](https://github.com/stlink-org/stlink/pull/894) - - [compatibility] Updated libusb to v1.0.23 ([#895](https://github.com/stlink-org/stlink/pull/895) - - Updated compiling doc & version support ([#896](https://github.com/stlink-org/stlink/pull/896), [#897](https://github.com/stlink-org/stlink/pull/897), [#899](https://github.com/stlink-org/stlink/pull/899)) + - Test files & gui now use shared `stlink-library` +- [doc] Verify correct udev configuration for device access ([#764](https://github.com/stlink-org/stlink/pull/764)) +- Added more error info to `WLOGs` during probe ([#883](https://github.com/stlink-org/stlink/pull/883)) +- [doc] Added missing documentation for stlink-gui ([#884](https://github.com/stlink-org/stlink/pull/884)) +- Added check for `libssp` during compilation ([#885](https://github.com/stlink-org/stlink/pull/885)) +- Silenced unnecessary messages ([#886](https://github.com/stlink-org/stlink/pull/886)) +- [doc] Defined `libusb` & `cmake` version compatibility ([#896](https://github.com/stlink-org/stlink/pull/896), [#897](https://github.com/stlink-org/stlink/pull/897), [#899](https://github.com/stlink-org/stlink/pull/899), commit [#27aa888](https://github.com/stlink-org/stlink/commit/27aa88821197d3ffe82baff4e971c3488ec39899)) +- Update for STM32G471/473/474/483/484 devices ([#901](https://github.com/stlink-org/stlink/pull/901)) +- [doc] `st-flash --flash=n[k][m]` command line option to override device model ([#902](https://github.com/stlink-org/stlink/pull/902)) +- [refactoring] Improved cmake build process ([#912](https://github.com/stlink-org/stlink/pull/912)) + - Set up a `libusb` log level accordingly to verbosity ([#894](https://github.com/stlink-org/stlink/pull/894) + - [compatibility] Updated `libusb` to v1.0.23 ([#895](https://github.com/stlink-org/stlink/pull/895, [#1089](https://github.com/stlink-org/stlink/pull/1089)) + - Updated compiling doc & version support ([#896](https://github.com/stlink-org/stlink/pull/896), [#897](https://github.com/stlink-org/stlink/pull/897), [#899](https://github.com/stlink-org/stlink/pull/899)) - Version requirements & pkg-maintainer - Fixed install paths in build script - - Updated C-flag -std=gnu99 to gnu11) - - Added cmake uninstall target ([#619](https://github.com/stlink-org/stlink/pull/619), [#907](https://github.com/stlink-org/stlink/pull/907)) - - Integrated module GNUInstallDirs.cmake ([#557](https://github.com/stlink-org/stlink/pull/557)) + - Updated C-flag `-std=gnu99` to `gnu11`) + - Added `cmake` uninstall target ([#619](https://github.com/stlink-org/stlink/pull/619), [#907](https://github.com/stlink-org/stlink/pull/907)) + - Integrated module `GNUInstallDirs.cmake` ([#557](https://github.com/stlink-org/stlink/pull/557)) - [doc] Defined version compatibility and installation instructions for macOS - - [refactoring] libusb detection - - Deprecated old appveyor-mingw script -* [refactoring] BSD-License-compliant rewrite of flashloader source files ([#915](https://github.com/stlink-org/stlink/pull/915), [#932](https://github.com/stlink-org/stlink/pull/932)) -* [refactoring] Overall option code rework ([#927](https://github.com/stlink-org/stlink/pull/927)) -* [refactoring] Build settings / GUI-Build on UNIX-based systems if GTK3 is detected ([#929](https://github.com/stlink-org/stlink/pull/929)) -* [refactoring] Reconfiguration of package build process ([#931](https://github.com/stlink-org/stlink/pull/931), [#936](https://github.com/stlink-org/stlink/pull/936), [#940](https://github.com/stlink-org/stlink/pull/940), commit [#9b19f92](https://github.com/stlink-org/stlink/commit/9b19f9225460472af9d98959b7217d0a840ee972)) -* [refactoring] st-util: Removed now useless v1/v2 STLink version stuff ([#934](https://github.com/stlink-org/stlink/pull/934)) -* [refactoring] Cleanup for option bytes and flash settings ([#941](https://github.com/stlink-org/stlink/pull/941)) -* Added compilation guideline for MSVC toolchain ([#942](https://github.com/stlink-org/stlink/pull/942)) -* [refactoring] Cleanup of cmake build process ([#944](https://github.com/stlink-org/stlink/pull/944), [#946](https://github.com/stlink-org/stlink/pull/946), [#947](https://github.com/stlink-org/stlink/pull/947)) - - libusb package extraction no longer requires 7zip as an external unarchiver + - [refactoring] `libusb` detection + - Deprecated old `appveyor-mingw` script +- [refactoring] BSD-License-compliant rewrite of flashloader source files ([#915](https://github.com/stlink-org/stlink/pull/915), [#932](https://github.com/stlink-org/stlink/pull/932)) +- [refactoring] Overall option code rework ([#927](https://github.com/stlink-org/stlink/pull/927)) +- [refactoring] Build settings / GUI-Build on UNIX-based systems if `GTK3` is detected ([#929](https://github.com/stlink-org/stlink/pull/929)) +- [refactoring] Reconfiguration of package build process ([#931](https://github.com/stlink-org/stlink/pull/931), [#936](https://github.com/stlink-org/stlink/pull/936), [#940](https://github.com/stlink-org/stlink/pull/940), commit [#9b19f92](https://github.com/stlink-org/stlink/commit/9b19f9225460472af9d98959b7217d0a840ee972)) +- [refactoring] `st-util`: Removed now useless v1/v2 STLink version stuff ([#934](https://github.com/stlink-org/stlink/pull/934)) +- [refactoring] Cleanup for option bytes and flash settings ([#941](https://github.com/stlink-org/stlink/pull/941)) +- Added compilation guideline for MSVC toolchain ([#942](https://github.com/stlink-org/stlink/pull/942)) +- [refactoring] Cleanup of `cmake` build process ([#944](https://github.com/stlink-org/stlink/pull/944), [#946](https://github.com/stlink-org/stlink/pull/946), [#947](https://github.com/stlink-org/stlink/pull/947)) + - `libusb` package extraction no longer requires `7zip` as an external unarchiver Fixes: -* Fixed wait-loop for flash_loader_run() ([#290](https://github.com/stlink-org/stlink/pull/290)) -* Better argument parsing for CLI tools: stlink_open_usb can address v1, v2, v3 ([#378](https://github.com/stlink-org/stlink/pull/378), [#922](https://github.com/stlink-org/stlink/pull/922)) -* Clear the PG bit before setting the PER bit ([#579](https://github.com/stlink-org/stlink/pull/579), [#876](https://github.com/stlink-org/stlink/pull/876)) -* Fixed compilation issues with int length on 32-bit platforms ([#629](https://github.com/stlink-org/stlink/pull/629), [#908](https://github.com/stlink-org/stlink/pull/908)) -* Fixed st-info --probe mechanism ([#679](https://github.com/stlink-org/stlink/pull/679), [#918](https://github.com/stlink-org/stlink/pull/918)) -* [regression] Fixed sign-compare (size != rep_len) in usb.c ([#772](https://github.com/stlink-org/stlink/pull/772), [#869](https://github.com/stlink-org/stlink/pull/869), [#872](https://github.com/stlink-org/stlink/pull/872), [#891](https://github.com/stlink-org/stlink/pull/891)) -* Fixed dead loop after an unexpected unplug ([#780](https://github.com/stlink-org/stlink/pull/780), [#812](https://github.com/stlink-org/stlink/pull/812), [#913](https://github.com/stlink-org/stlink/pull/913)) -* Avoid re-define of O_BINARY on Windows ([#788](https://github.com/stlink-org/stlink/pull/788)) -* Fixed stlink lock-up when not connected to a device via JTAG / SWD ([#835](https://github.com/stlink-org/stlink/pull/835), [#943](https://github.com/stlink-org/stlink/pull/943)) -* Fixed st-flash manpage read example ([#858](https://github.com/stlink-org/stlink/pull/858)) -* Fixed stlink support with no mass storage ([#861](https://github.com/stlink-org/stlink/pull/861)) -* Make Version.cmake more error-resistant ([#872](https://github.com/stlink-org/stlink/pull/872)) -* Error return in failed probe ([#887](https://github.com/stlink-org/stlink/pull/887), [#890](https://github.com/stlink-org/stlink/pull/890)) -* Fixed broken build on 32-bit systems ([#919](https://github.com/stlink-org/stlink/pull/919), [#920](https://github.com/stlink-org/stlink/pull/920)) -* st-flash: Minor usage fix and make cmdline parsing more user friendly ([#925](https://github.com/stlink-org/stlink/pull/925)) -* [regression] Restored functionality of make test builds ([#926](https://github.com/stlink-org/stlink/pull/926), [#929](https://github.com/stlink-org/stlink/pull/929)) -* Fixed compilation error due to uninitialized cpuid ([#937](https://github.com/stlink-org/stlink/pull/937), [#938](https://github.com/stlink-org/stlink/pull/938)) -* Fixes for STM32F0 flashloader ([#958](https://github.com/stlink-org/stlink/pull/958), [#959](https://github.com/stlink-org/stlink/pull/959)) -* Set static link for libssp (stack-smashing protection) ([#960](https://github.com/stlink-org/stlink/pull/960), [#961](https://github.com/stlink-org/stlink/pull/961)) -* Fixed udev rules installing to wrong directory ([#966](https://github.com/stlink-org/stlink/pull/966)) -* Fixed formatting for options display in st-flash & st-info (commits [#c783d0e](https://github.com/stlink-org/stlink/commit/c783d0e777ccc83a7a8be26a4f4d3414e0478560) and [#562cd24](https://github.com/stlink-org/stlink/commit/562cd2496e696dbd22950925866aac662d81ee5f)) - - -v1.6.0 -====== +- Fixed wait-loop for `flash_loader_run()` ([#290](https://github.com/stlink-org/stlink/pull/290)) +- Better argument parsing for CLI tools: `stlink_open_usb` can address v1, v2, v3 ([#378](https://github.com/stlink-org/stlink/pull/378), [#922](https://github.com/stlink-org/stlink/pull/922)) +- Clear the PG bit before setting the `PER` bit ([#579](https://github.com/stlink-org/stlink/pull/579), [#876](https://github.com/stlink-org/stlink/pull/876)) +- Fixed compilation issues with int length on 32-bit platforms ([#629](https://github.com/stlink-org/stlink/pull/629), [#908](https://github.com/stlink-org/stlink/pull/908)) +- Fixed `st-info --probe` mechanism ([#679](https://github.com/stlink-org/stlink/pull/679), [#918](https://github.com/stlink-org/stlink/pull/918)) +- [regression] Fixed sign-compare (`size != rep_len`) in `usb.c` ([#772](https://github.com/stlink-org/stlink/pull/772), [#869](https://github.com/stlink-org/stlink/pull/869), [#872](https://github.com/stlink-org/stlink/pull/872), [#891](https://github.com/stlink-org/stlink/pull/891)) +- Fixed dead loop after an unexpected unplug ([#780](https://github.com/stlink-org/stlink/pull/780), [#812](https://github.com/stlink-org/stlink/pull/812), [#913](https://github.com/stlink-org/stlink/pull/913)) +- Avoid re-define of `O_BINARY` on Windows ([#788](https://github.com/stlink-org/stlink/pull/788)) +- Fixed stlink lock-up when not connected to a device via JTAG / SWD ([#835](https://github.com/stlink-org/stlink/pull/835), [#943](https://github.com/stlink-org/stlink/pull/943)) +- Fixed `st-flash` manpage read example ([#858](https://github.com/stlink-org/stlink/pull/858)) +- Fixed stlink support with no mass storage ([#861](https://github.com/stlink-org/stlink/pull/861)) +- Make `version.cmake` more error-resistant ([#872](https://github.com/stlink-org/stlink/pull/872)) +- Error return in failed probe ([#887](https://github.com/stlink-org/stlink/pull/887), [#890](https://github.com/stlink-org/stlink/pull/890)) +- Fixed broken build on 32-bit systems ([#919](https://github.com/stlink-org/stlink/pull/919), [#920](https://github.com/stlink-org/stlink/pull/920)) +- `st-flash`: Minor usage fix and make cmdline parsing more user friendly ([#925](https://github.com/stlink-org/stlink/pull/925)) +- [regression] Restored functionality of make test builds ([#926](https://github.com/stlink-org/stlink/pull/926), [#929](https://github.com/stlink-org/stlink/pull/929)) +- Fixed compilation error due to uninitialized cpuid ([#937](https://github.com/stlink-org/stlink/pull/937), [#938](https://github.com/stlink-org/stlink/pull/938)) +- Fixes for STM32F0 flashloader ([#958](https://github.com/stlink-org/stlink/pull/958), [#959](https://github.com/stlink-org/stlink/pull/959)) +- Set static link for `libssp` (stack-smashing protection) ([#960](https://github.com/stlink-org/stlink/pull/960), [#961](https://github.com/stlink-org/stlink/pull/961)) +- Fixed udev rules installing to wrong directory ([#966](https://github.com/stlink-org/stlink/pull/966)) +- Fixed formatting for options display in `st-flash` & `st-info` (commits [#c783d0e](https://github.com/stlink-org/stlink/commit/c783d0e777ccc83a7a8be26a4f4d3414e0478560) and [#562cd24](https://github.com/stlink-org/stlink/commit/562cd2496e696dbd22950925866aac662d81ee5f)) + +# v1.6.0 Release date: 2020-02-20 Major changes and added features: -* Initial support for STM32L41X ([#754](https://github.com/stlink-org/stlink/pull/754), [#799](https://github.com/stlink-org/stlink/pull/799)) -* Verified support for CKS32F103C8T6 and related CKS devices with Core-ID 0x2ba01477 ([#756](https://github.com/stlink-org/stlink/pull/756), [#757](https://github.com/stlink-org/stlink/pull/757), [#805](https://github.com/stlink-org/stlink/pull/805), [#834](https://github.com/stlink-org/stlink/pull/834), Regression-Fixes: [#761](https://github.com/stlink-org/stlink/pull/761), [#766](https://github.com/stlink-org/stlink/pull/766)) -* Added preliminary support for some STM32G0 chips ([#759](https://github.com/stlink-org/stlink/pull/759), [#760](https://github.com/stlink-org/stlink/pull/760), [#797](https://github.com/stlink-org/stlink/pull/797)) -* Added support for mass erasing second bank on STM32F10x_XL ([#767](https://github.com/stlink-org/stlink/pull/767), [#768](https://github.com/stlink-org/stlink/pull/768)) -* Added call to clear PG bit after writing to flash ([#773](https://github.com/stlink-org/stlink/pull/773)) -* Added support to write option bytes for the STM32G0 ([#778](https://github.com/stlink-org/stlink/pull/778)) -* Added support for STM32WB55 chips ([#786](https://github.com/stlink-org/stlink/pull/786), [#810](https://github.com/stlink-org/stlink/pull/810), [#816](https://github.com/stlink-org/stlink/pull/816)) -* Added STLink V3SET VID:PIDs to the udev rules ([#789](https://github.com/stlink-org/stlink/pull/789)) -* Support for "STM32+Audio" v2-1 firmware ([#790](https://github.com/stlink-org/stlink/pull/790)) -* Build for Windows under Debian/Ubuntu ([#802](https://github.com/stlink-org/stlink/pull/802)) -* Allow for 64 bytes serials ([#809](https://github.com/stlink-org/stlink/pull/809)) -* Added full support for STLINK CHIP ID L4RX ([#814](https://github.com/stlink-org/stlink/pull/814), [#839](https://github.com/stlink-org/stlink/pull/839)) -* Added support for the STLink-v2.1 when flashed with no mass storage (PID 0x3752) ([#819](https://github.com/stlink-org/stlink/pull/819), [#861](https://github.com/stlink-org/stlink/pull/861)) -* Added support for writing option bytes on STM32L0xx ([#830](https://github.com/stlink-org/stlink/pull/830)) -* Added support to read and write option bytes for STM32F2 series ([#836](https://github.com/stlink-org/stlink/pull/836), [#837](https://github.com/stlink-org/stlink/pull/837)) -* Added support to read and write option bytes for STM32F446 ([#843](https://github.com/stlink-org/stlink/pull/843)) +- Initial support for STM32L41X ([#754](https://github.com/stlink-org/stlink/pull/754), [#799](https://github.com/stlink-org/stlink/pull/799)) +- Verified support for CKS32F103C8T6 and related CKS devices with Core-ID 0x2ba01477 ([#756](https://github.com/stlink-org/stlink/pull/756), [#757](https://github.com/stlink-org/stlink/pull/757), [#805](https://github.com/stlink-org/stlink/pull/805), [#834](https://github.com/stlink-org/stlink/pull/834), Regression-Fixes: [#761](https://github.com/stlink-org/stlink/pull/761), [#766](https://github.com/stlink-org/stlink/pull/766)) +- Added preliminary support for some STM32G0 chips ([#759](https://github.com/stlink-org/stlink/pull/759), [#760](https://github.com/stlink-org/stlink/pull/760), [#797](https://github.com/stlink-org/stlink/pull/797)) +- Added support for mass erasing second bank on `STM32F10x_XL` ([#767](https://github.com/stlink-org/stlink/pull/767), [#768](https://github.com/stlink-org/stlink/pull/768)) +- Added call to clear `PG` bit after writing to flash ([#773](https://github.com/stlink-org/stlink/pull/773)) +- Added support to write option bytes for the STM32G0 ([#778](https://github.com/stlink-org/stlink/pull/778)) +- Added support for STM32WB55 chips ([#786](https://github.com/stlink-org/stlink/pull/786), [#810](https://github.com/stlink-org/stlink/pull/810), [#816](https://github.com/stlink-org/stlink/pull/816)) +- Added `STLink V3SET` VID:PIDs to the udev rules ([#789](https://github.com/stlink-org/stlink/pull/789)) +- Support for `STM32+Audio` v2-1 firmware ([#790](https://github.com/stlink-org/stlink/pull/790)) +- Build for Windows under Debian/Ubuntu ([#802](https://github.com/stlink-org/stlink/pull/802)) +- Allow for 64 bytes serials ([#809](https://github.com/stlink-org/stlink/pull/809)) +- Added full support for STLINK CHIP ID L4RX ([#814](https://github.com/stlink-org/stlink/pull/814), [#839](https://github.com/stlink-org/stlink/pull/839)) +- Added support for the STLink/V2.1 when flashed with no mass storage (PID 0x3752) ([#819](https://github.com/stlink-org/stlink/pull/819), [#861](https://github.com/stlink-org/stlink/pull/861)) +- Added support for writing option bytes on STM32L0xx ([#830](https://github.com/stlink-org/stlink/pull/830)) +- Added support to read and write option bytes for STM32F2 series ([#836](https://github.com/stlink-org/stlink/pull/836), [#837](https://github.com/stlink-org/stlink/pull/837)) +- Added support to read and write option bytes for STM32F446 ([#843](https://github.com/stlink-org/stlink/pull/843)) Updates and fixes: -* Fixed "unkown chip id", piped output and st-util -v ([#107](https://github.com/stlink-org/stlink/pull/107), [#665](https://github.com/stlink-org/stlink/pull/665), [#763](https://github.com/stlink-org/stlink/pull/763)) -* Fixed an issue with versioning stuck at 1.4.0 for versions cloned with git ([#563](https://github.com/stlink-org/stlink/pull/563), [#762](https://github.com/stlink-org/stlink/pull/762), [#772](https://github.com/stlink-org/stlink/pull/772)) -* Updated STM32F3xx chip ID that covers a few different devices ([#685](https://github.com/stlink-org/stlink/pull/685), [#758](https://github.com/stlink-org/stlink/pull/758)) -* Made udev rules and modprobe conf installation optional ([#741](https://github.com/stlink-org/stlink/pull/741)) -* Fixed case when __FILE__ don't contain "/" nor "\\" ([#745](https://github.com/stlink-org/stlink/pull/745)) -* Fixed double dash issue in doc/man ([#746](https://github.com/stlink-org/stlink/pull/746), [#747](https://github.com/stlink-org/stlink/pull/747)) -* Compiling documentation: package is called libusb-1.0-0-dev on Debian ([#748](https://github.com/stlink-org/stlink/pull/748)) -* Only do bank calculation on STM32L4 devices with dual banked flash / Added chip-ID 0x464 for STM32L41xxx/L42xxx devices ([#751](https://github.com/stlink-org/stlink/pull/751)) -* Added O_BINARY option to open file ([#753](https://github.com/stlink-org/stlink/pull/753)) -* Fixed versioning when compiling from the checked out git-repo ([#762](https://github.com/stlink-org/stlink/pull/762), [#772](https://github.com/stlink-org/stlink/pull/772)) -* win32: move usleep definition to unistd.h ([#765](https://github.com/stlink-org/stlink/pull/765)) -* Fixed relative path to the UI files needed by stlink-gui-local (GUI) ([#770](https://github.com/stlink-org/stlink/pull/770), [#771](https://github.com/stlink-org/stlink/pull/771)) -* Added howto for sending NRST signal through GDB ([#774](https://github.com/stlink-org/stlink/pull/774), [#776](https://github.com/stlink-org/stlink/pull/776), [#779](https://github.com/stlink-org/stlink/pull/779)) -* Fixed package name "devscripts" in doc/compiling.md ([#775](https://github.com/stlink-org/stlink/pull/775)) -* Fixed few potential memory/resource leaks ([#803](https://github.com/stlink-org/stlink/pull/803), [#831](https://github.com/stlink-org/stlink/pull/831)) -* Updated Linux source repositories in README.md: Debian and Ubuntu ([#821](https://github.com/stlink-org/stlink/pull/821), [#835](https://github.com/stlink-org/stlink/pull/835), [#859](https://github.com/stlink-org/stlink/pull/859)) -* Do not issue JTAG reset on stlink-v1 ([#828](https://github.com/stlink-org/stlink/pull/828)) -* Fixed flash size of STM32 Discovery vl ([#829](https://github.com/stlink-org/stlink/pull/829)) -* Updated documentation on software structure ([#851](https://github.com/stlink-org/stlink/pull/851)) +- Fixed `unkown chip id`, piped output and `st-util -v` ([#107](https://github.com/stlink-org/stlink/pull/107), [#665](https://github.com/stlink-org/stlink/pull/665), [#763](https://github.com/stlink-org/stlink/pull/763)) +- Fixed an issue with versioning stuck at 1.4.0 for versions cloned with git ([#563](https://github.com/stlink-org/stlink/pull/563), [#762](https://github.com/stlink-org/stlink/pull/762), [#772](https://github.com/stlink-org/stlink/pull/772)) +- Updated STM32F3xx chip ID that covers a few different devices ([#685](https://github.com/stlink-org/stlink/pull/685), [#758](https://github.com/stlink-org/stlink/pull/758)) +- Made udev rules and modprobe conf installation optional ([#741](https://github.com/stlink-org/stlink/pull/741)) +- Fixed case when `__FILE__` doesn't contain either `/` nor `\\` ([#745](https://github.com/stlink-org/stlink/pull/745)) +- Fixed double dash issue in doc/man ([#746](https://github.com/stlink-org/stlink/pull/746), [#747](https://github.com/stlink-org/stlink/pull/747)) +- Compiling documentation: package is called `libusb-1.0-0-dev` on Debian ([#748](https://github.com/stlink-org/stlink/pull/748)) +- Only do bank calculation on STM32L4 devices with dual banked flash / Added chip-ID 0x464 for STM32L41xxx/L42xxx devices ([#751](https://github.com/stlink-org/stlink/pull/751)) +- Added `O_BINARY` option to open file ([#753](https://github.com/stlink-org/stlink/pull/753)) +- Fixed versioning when compiling from the checked out git-repo ([#762](https://github.com/stlink-org/stlink/pull/762), [#772](https://github.com/stlink-org/stlink/pull/772)) +- win32: move usleep definition to `unistd.h` ([#765](https://github.com/stlink-org/stlink/pull/765)) +- Fixed relative path to the UI files needed by `stlink-gui-local` (GUI) ([#770](https://github.com/stlink-org/stlink/pull/770), [#771](https://github.com/stlink-org/stlink/pull/771)) +- Added howto for sending `NRST` signal through GDB ([#774](https://github.com/stlink-org/stlink/pull/774), [#776](https://github.com/stlink-org/stlink/pull/776), [#779](https://github.com/stlink-org/stlink/pull/779)) +- Fixed package name `devscripts` in doc/compiling.md ([#775](https://github.com/stlink-org/stlink/pull/775)) +- Fixed few potential memory/resource leaks ([#803](https://github.com/stlink-org/stlink/pull/803), [#831](https://github.com/stlink-org/stlink/pull/831)) +- Updated Linux source repositories in README.md: Debian and Ubuntu ([#821](https://github.com/stlink-org/stlink/pull/821), [#835](https://github.com/stlink-org/stlink/pull/835), [#859](https://github.com/stlink-org/stlink/pull/859)) +- Do not issue JTAG reset on STLink/V1 ([#828](https://github.com/stlink-org/stlink/pull/828)) +- Fixed flash size of STM32 Discovery VL ([#829](https://github.com/stlink-org/stlink/pull/829)) +- Updated documentation on software structure ([#851](https://github.com/stlink-org/stlink/pull/851)) General project updates: -* Updated README.md, CHANGELOG.md and issue templates (Nightwalker-87) -* Fixed travis build config file (Nightwalker-87) -* Added CODE_OF_CONDUCT (Nightwalker-87) -* Archived page from github project wiki to doc/wiki_old.md (Nightwalker-87) +- Updated `README.md`, `CHANGELOG.md` and issue templates (Nightwalker-87) +- Fixed travis build config file (Nightwalker-87) +- Added `CODE_OF_CONDUCT` (Nightwalker-87) +- Archived page from github project wiki to doc/wiki_old.md (Nightwalker-87) - -v1.5.1 -====== +# v1.5.1 Release date: 2018-09-13 Major changes and added features: -* Added reset through AIRCR ([#540](https://github.com/stlink-org/stlink/pull/540), [#712](https://github.com/stlink-org/stlink/pull/712)) -* Added creation of icons for .desktop file ([#684](https://github.com/stlink-org/stlink/pull/684), [#708](https://github.com/stlink-org/stlink/pull/708)) -* Added desktop file for linux ([#688](https://github.com/stlink-org/stlink/pull/688)) -* Added button to export STM32 flash memory to a file ([#691](https://github.com/stlink-org/stlink/pull/691)) -* Updated libusb to 1.0.22 ([#695](https://github.com/stlink-org/stlink/pull/695)) - (related Bugs: [#438](https://github.com/stlink-org/stlink/pull/438), [#632](https://github.com/stlink-org/stlink/pull/632)) -* Added icons for STLink GUI ([#697](https://github.com/stlink-org/stlink/pull/697)) -* Added support for STM32L4R9 target ([#694](https://github.com/stlink-org/stlink/pull/694), [#699](https://github.com/stlink-org/stlink/pull/699)) -* Added memory map for STM32F411RE target ([#709](https://github.com/stlink-org/stlink/pull/709)) -* Implemented intel hex support for GTK GUI ([#713](https://github.com/stlink-org/stlink/pull/713), [#718](https://github.com/stlink-org/stlink/pull/718)) +- Added reset through `AIRCR` ([#540](https://github.com/stlink-org/stlink/pull/540), [#712](https://github.com/stlink-org/stlink/pull/712)) +- Added creation of icons for `.desktop` file ([#684](https://github.com/stlink-org/stlink/pull/684), [#708](https://github.com/stlink-org/stlink/pull/708)) +- Added desktop file for linux ([#688](https://github.com/stlink-org/stlink/pull/688)) +- Added button to export STM32 flash memory to a file ([#691](https://github.com/stlink-org/stlink/pull/691)) +- Updated `libusb` to 1.0.22 ([#695](https://github.com/stlink-org/stlink/pull/695)) - (related Bugs: [#438](https://github.com/stlink-org/stlink/pull/438), [#632](https://github.com/stlink-org/stlink/pull/632)) +- Added icons for stlink GUI ([#697](https://github.com/stlink-org/stlink/pull/697)) +- Added support for STM32L4R9 target ([#694](https://github.com/stlink-org/stlink/pull/694), [#699](https://github.com/stlink-org/stlink/pull/699)) +- Added memory map for STM32F411RE target ([#709](https://github.com/stlink-org/stlink/pull/709)) +- Implemented intel hex support for `GTK` GUI ([#713](https://github.com/stlink-org/stlink/pull/713), [#718](https://github.com/stlink-org/stlink/pull/718)) Updates and fixes: -* Fixed missing flash_loader for STM32L0x ([#269](https://github.com/stlink-org/stlink/pull/269), [#274](https://github.com/stlink-org/stlink/pull/274), [#654](https://github.com/stlink-org/stlink/pull/654), [#675](https://github.com/stlink-org/stlink/pull/675)) -* Fix for stlink library calls exit() or _exit() ([#634](https://github.com/stlink-org/stlink/pull/634), [#696](https://github.com/stlink-org/stlink/pull/696)) -* Added semihosting parameter documentation in doc/man ([#674](https://github.com/stlink-org/stlink/pull/674)) -* Fixed reference to non-exisiting st-term tool in doc/man ([#676](https://github.com/stlink-org/stlink/pull/676)) -* Fixed serial number size mismatch with stlink_open_usb() ([#680](https://github.com/stlink-org/stlink/pull/680)) -* Debian packaging, CMake and README.md fixes ([#682](https://github.com/stlink-org/stlink/pull/682), [#683](https://github.com/stlink-org/stlink/pull/683)) -* Disabled static library installation by default ([#702](https://github.com/stlink-org/stlink/pull/702)) -* Fix for libusb deprecation ([#703](https://github.com/stlink-org/stlink/pull/703), [#704](https://github.com/stlink-org/stlink/pull/704)) -* Renamed STLINK_CHIPID_STM32_L4R9 to STLINK_CHIPID_STM32_L4RX ([#706](https://github.com/stlink-org/stlink/pull/706)) -* [regression] stlink installation under Linux (Debian 9) is broken since #695 ([#700](https://github.com/stlink-org/stlink/pull/700), [#701](https://github.com/stlink-org/stlink/pull/701), [#707](https://github.com/stlink-org/stlink/pull/707)) -* Fixed flash memory map for STM32F72xxx target ([#711](https://github.com/stlink-org/stlink/pull/711)) -* Proper flash page size calculation for STM32F412xx target ([#721](https://github.com/stlink-org/stlink/pull/721)) -* Return correct value on EOF for Semihosting SYS_READ ([#726](https://github.com/stlink-org/stlink/pull/726), [#727](https://github.com/stlink-org/stlink/pull/727), [#728](https://github.com/stlink-org/stlink/pull/728), [#729](https://github.com/stlink-org/stlink/pull/729), [#730](https://github.com/stlink-org/stlink/pull/730), [#731](https://github.com/stlink-org/stlink/pull/731), [#732](https://github.com/stlink-org/stlink/pull/732)) -* FreeBSD defines LIBUSB_API_VERSION instead of LIBUSBX_API_VERSION ([#733](https://github.com/stlink-org/stlink/pull/733)) - - -v1.5.0 -====== +- Fixed missing flash_loader for STM32L0x ([#269](https://github.com/stlink-org/stlink/pull/269), [#274](https://github.com/stlink-org/stlink/pull/274), [#654](https://github.com/stlink-org/stlink/pull/654), [#675](https://github.com/stlink-org/stlink/pull/675)) +- Fix for stlink library calls `exit()` or `_exit()` ([#634](https://github.com/stlink-org/stlink/pull/634), [#696](https://github.com/stlink-org/stlink/pull/696)) +- Added semihosting parameter documentation in doc/man ([#674](https://github.com/stlink-org/stlink/pull/674)) +- Fixed reference to non-exisiting `st-term` tool in doc/man ([#676](https://github.com/stlink-org/stlink/pull/676)) +- Fixed serial number size mismatch with `stlink_open_usb()` ([#680](https://github.com/stlink-org/stlink/pull/680)) +- Debian packaging, `cmake` and `README.md` fixes ([#682](https://github.com/stlink-org/stlink/pull/682), [#683](https://github.com/stlink-org/stlink/pull/683)) +- Disabled static library installation by default ([#702](https://github.com/stlink-org/stlink/pull/702)) +- Fix for `libusb` deprecation ([#703](https://github.com/stlink-org/stlink/pull/703), [#704](https://github.com/stlink-org/stlink/pull/704)) +- Renamed `STLINK_CHIPID_STM32_L4R9` to `STLINK_CHIPID_STM32_L4RX` ([#706](https://github.com/stlink-org/stlink/pull/706)) +- [regression] stlink installation under Linux (Debian 9) is broken since #695 ([#700](https://github.com/stlink-org/stlink/pull/700), [#701](https://github.com/stlink-org/stlink/pull/701), [#707](https://github.com/stlink-org/stlink/pull/707)) +- Fixed flash memory map for STM32F72xxx target ([#711](https://github.com/stlink-org/stlink/pull/711)) +- Proper flash page size calculation for STM32F412xx target ([#721](https://github.com/stlink-org/stlink/pull/721)) +- Return correct value on `EOF` for semihosting `SYS_READ` ([#726](https://github.com/stlink-org/stlink/pull/726), [#727](https://github.com/stlink-org/stlink/pull/727), [#728](https://github.com/stlink-org/stlink/pull/728), [#729](https://github.com/stlink-org/stlink/pull/729), [#730](https://github.com/stlink-org/stlink/pull/730), [#731](https://github.com/stlink-org/stlink/pull/731), [#732](https://github.com/stlink-org/stlink/pull/732)) +- FreeBSD defines `LIBUSB_API_VERSION` instead of `LIBUSBX_API_VERSION` ([#733](https://github.com/stlink-org/stlink/pull/733)) + +# v1.5.0 Release date: 2018-02-16 Major changes and added features: -* Added support of STM32L496xx/4A6xx devices ([#615](https://github.com/stlink-org/stlink/pull/615), [#657](https://github.com/stlink-org/stlink/pull/657)) -* Added unknown chip dummy to obtain the serial of the ST-link by a call to st-info --probe ([#641](https://github.com/stlink-org/stlink/pull/641)) -* Added support for STM32F72xx (chip-ID: 0x452) devices (commit [#1969148](https://github.com/stlink-org/stlink/commit/19691485359afef1a256964afcbb8dcf4b733209)) +- Added support of STM32L496xx/4A6xx devices ([#615](https://github.com/stlink-org/stlink/pull/615), [#657](https://github.com/stlink-org/stlink/pull/657)) +- Added unknown chip dummy to obtain the serial of the STlink by a call to `st-info --probe` ([#641](https://github.com/stlink-org/stlink/pull/641)) +- Added support for STM32F72xx (chip-ID: 0x452) devices (commit [#1969148](https://github.com/stlink-org/stlink/commit/19691485359afef1a256964afcbb8dcf4b733209)) Updates and fixes: -* Fixed verification of flash error for STM32L496x device ([#617](https://github.com/stlink-org/stlink/pull/617), [#618](https://github.com/stlink-org/stlink/pull/618)) -* Updated Linux source repositories in README.md: Gentoo, Fedora and RedHat/CentOS ([#622](https://github.com/stlink-org/stlink/pull/622), [#635](https://github.com/stlink-org/stlink/pull/635)) -* Updated changelog in debian package ([#630](https://github.com/stlink-org/stlink/pull/630)) -* Added LIB_INSTALL_DIR to correct libs install on 64-bit systems ([#633](https://github.com/stlink-org/stlink/pull/633), [#636](https://github.com/stlink-org/stlink/pull/636)) -* Fixed write for microcontroller with RAM size less or equal to 32K ([#637](https://github.com/stlink-org/stlink/pull/637)) -* Fixed memory map for STM32L496xx boards ([#639](https://github.com/stlink-org/stlink/pull/639)) -* Fixed __FILE__ base name extraction ([#624](https://github.com/stlink-org/stlink/pull/624), [#628](https://github.com/stlink-org/stlink/pull/628), [#648](https://github.com/stlink-org/stlink/pull/648)) -* Added debian/triggers to run ldconfig ([#664](https://github.com/stlink-org/stlink/pull/664)) -* Fixed build on Fedora with GCC 8 ([#666](https://github.com/stlink-org/stlink/pull/666), [#667](https://github.com/stlink-org/stlink/pull/667), [#668](https://github.com/stlink-org/stlink/pull/668)) - +- Fixed verification of flash error for STM32L496x device ([#617](https://github.com/stlink-org/stlink/pull/617), [#618](https://github.com/stlink-org/stlink/pull/618)) +- Updated Linux source repositories in README.md: Gentoo, Fedora and RedHat/CentOS ([#622](https://github.com/stlink-org/stlink/pull/622), [#635](https://github.com/stlink-org/stlink/pull/635)) +- Updated changelog in debian package ([#630](https://github.com/stlink-org/stlink/pull/630)) +- Added `LIB_INSTALL_DIR` to correct libs install on 64-bit systems ([#633](https://github.com/stlink-org/stlink/pull/633), [#636](https://github.com/stlink-org/stlink/pull/636)) +- Fixed write for microcontroller with RAM size less or equal to 32K ([#637](https://github.com/stlink-org/stlink/pull/637)) +- Fixed memory map for STM32L496xx boards ([#639](https://github.com/stlink-org/stlink/pull/639)) +- Fixed `__FILE__` base name extraction ([#624](https://github.com/stlink-org/stlink/pull/624), [#628](https://github.com/stlink-org/stlink/pull/628), [#648](https://github.com/stlink-org/stlink/pull/648)) +- Added debian/triggers to run `ldconfig` ([#664](https://github.com/stlink-org/stlink/pull/664)) +- Fixed build on Fedora with GCC 8 ([#666](https://github.com/stlink-org/stlink/pull/666), [#667](https://github.com/stlink-org/stlink/pull/667), [#668](https://github.com/stlink-org/stlink/pull/668)) -v1.4.0 -====== +# v1.4.0 Release date: 2017-07-01 Major changes and added features: -* Allow building of debian package with CPack ([#554](https://github.com/stlink-org/stlink/pull/554), commit [#5b69f25](https://github.com/stlink-org/stlink/commit/5b69f25198a1a8f34e2ee48d1ad20f79447e3d55)) -* Added support for STM32L011 target ([#564](https://github.com/stlink-org/stlink/pull/564), [#565](https://github.com/stlink-org/stlink/pull/565), [#572](https://github.com/stlink-org/stlink/pull/572)) -* Added support for flashing second bank on STM32F10x_XL ([#592](https://github.com/stlink-org/stlink/pull/592)) -* Initial support to compile with Microsoft Visual Studio 2017 ([#602](https://github.com/stlink-org/stlink/pull/602)) -* Added support for STM32L452 target ([#603](https://github.com/stlink-org/stlink/pull/603), [#608](https://github.com/stlink-org/stlink/pull/608)) +- Allow building of debian package with CPack ([#554](https://github.com/stlink-org/stlink/pull/554), commit [#5b69f25](https://github.com/stlink-org/stlink/commit/5b69f25198a1a8f34e2ee48d1ad20f79447e3d55)) +- Added support for STM32L011 target ([#564](https://github.com/stlink-org/stlink/pull/564), [#565](https://github.com/stlink-org/stlink/pull/565), [#572](https://github.com/stlink-org/stlink/pull/572)) +- Added support for flashing second bank on STM32F10x_XL ([#592](https://github.com/stlink-org/stlink/pull/592)) +- Initial support to compile with Microsoft Visual Studio 2017 ([#602](https://github.com/stlink-org/stlink/pull/602)) +- Added support for STM32L452 target ([#603](https://github.com/stlink-org/stlink/pull/603), [#608](https://github.com/stlink-org/stlink/pull/608)) Updates and fixes: -* Fixed gdb-server: STM32L0xx has no FP_CTRL register for breakpoints ([#273](https://github.com/stlink-org/stlink/pull/273)) -* Added --flash=n[k][m] command line option to override device model ([#305](https://github.com/stlink-org/stlink/pull/305), [#516](https://github.com/stlink-org/stlink/pull/516), [#576](https://github.com/stlink-org/stlink/pull/576)) -* Updated libusb to 1.0.21 for Windows ([#562](https://github.com/stlink-org/stlink/pull/562)) -* Fixed low-voltage flashing on STM32F7 devices ([#566](https://github.com/stlink-org/stlink/pull/566), [#567](https://github.com/stlink-org/stlink/pull/567)) -* Fixed building with mingw64 ([#569](https://github.com/stlink-org/stlink/pull/569), [#573](https://github.com/stlink-org/stlink/pull/573), [#578](https://github.com/stlink-org/stlink/pull/578), [#582](https://github.com/stlink-org/stlink/pull/582), [#584](https://github.com/stlink-org/stlink/pull/584), [#610](https://github.com/stlink-org/stlink/pull/610), [#846](https://github.com/stlink-org/stlink/pull/846)) -* Fixed possible memory leak ([#570](https://github.com/stlink-org/stlink/pull/570), [#571](https://github.com/stlink-org/stlink/pull/571)) -* Fixed installation path for shared objects ([#581](https://github.com/stlink-org/stlink/pull/581)) -* Fixed a few -Wformat warnings ([#582](https://github.com/stlink-org/stlink/pull/582)) -* Removed unused defines in mimgw.h ([#583](https://github.com/stlink-org/stlink/pull/583)) -* Skip GTK detection when cross-compiling ([#588](https://github.com/stlink-org/stlink/pull/588)) -* Fixed compilation with GCC 7 ([#590](https://github.com/stlink-org/stlink/pull/590), [#591](https://github.com/stlink-org/stlink/pull/591)) -* Fixed flashing to 'f0 device' targets ([#594](https://github.com/stlink-org/stlink/pull/594), [#595](https://github.com/stlink-org/stlink/pull/595)) -* Fixed wrong counting when flashing ([#605](https://github.com/stlink-org/stlink/pull/605)) - - -v1.3.1 -====== +- Fixed gdb-server: STM32L0xx has no `FP_CTRL` register for breakpoints ([#273](https://github.com/stlink-org/stlink/pull/273)) +- Added `--flash=n[k][m]` command line option to override device model ([#305](https://github.com/stlink-org/stlink/pull/305), [#516](https://github.com/stlink-org/stlink/pull/516), [#576](https://github.com/stlink-org/stlink/pull/576)) +- Updated `libusb` to 1.0.21 for Windows ([#562](https://github.com/stlink-org/stlink/pull/562)) +- Fixed low-voltage flashing on STM32F7 devices ([#566](https://github.com/stlink-org/stlink/pull/566), [#567](https://github.com/stlink-org/stlink/pull/567)) +- Fixed building with mingw64 ([#569](https://github.com/stlink-org/stlink/pull/569), [#573](https://github.com/stlink-org/stlink/pull/573), [#578](https://github.com/stlink-org/stlink/pull/578), [#582](https://github.com/stlink-org/stlink/pull/582), [#584](https://github.com/stlink-org/stlink/pull/584), [#610](https://github.com/stlink-org/stlink/pull/610), [#846](https://github.com/stlink-org/stlink/pull/846)) +- Fixed possible memory leak ([#570](https://github.com/stlink-org/stlink/pull/570), [#571](https://github.com/stlink-org/stlink/pull/571)) +- Fixed installation path for shared objects ([#581](https://github.com/stlink-org/stlink/pull/581)) +- Fixed a few `-Wformat` warnings ([#582](https://github.com/stlink-org/stlink/pull/582)) +- Removed unused defines in `mingw.h` ([#583](https://github.com/stlink-org/stlink/pull/583)) +- Skip `GTK` detection when cross-compiling ([#588](https://github.com/stlink-org/stlink/pull/588)) +- Fixed compilation with GCC 7 ([#590](https://github.com/stlink-org/stlink/pull/590), [#591](https://github.com/stlink-org/stlink/pull/591)) +- Fixed flashing to `F0 device` targets ([#594](https://github.com/stlink-org/stlink/pull/594), [#595](https://github.com/stlink-org/stlink/pull/595)) +- Fixed wrong counting when flashing ([#605](https://github.com/stlink-org/stlink/pull/605)) + +# v1.3.1 Release date: 2017-02-25 Major changes and added features: -* Added support for Semihosting `SYS_READC` ([#546](https://github.com/stlink-org/stlink/pull/546)) -* Added support for STM32F413 ([#549](https://github.com/stlink-org/stlink/pull/549), [#550](https://github.com/stlink-org/stlink/pull/550), [#758](https://github.com/stlink-org/stlink/pull/758)) -* Added preliminary support for STM32L011 to see it after probe (chip-ID 0x457) ([#558](https://github.com/stlink-org/stlink/pull/558), [#598](https://github.com/stlink-org/stlink/pull/598)) +- Added support for Semihosting `SYS_READC` ([#546](https://github.com/stlink-org/stlink/pull/546)) +- Added support for STM32F413 ([#549](https://github.com/stlink-org/stlink/pull/549), [#550](https://github.com/stlink-org/stlink/pull/550), [#758](https://github.com/stlink-org/stlink/pull/758)) +- Added preliminary support for STM32L011 to see it after probe (chip-ID 0x457) ([#558](https://github.com/stlink-org/stlink/pull/558), [#598](https://github.com/stlink-org/stlink/pull/598)) Updates and fixes: -* cmake/CPackConfig.cmake: Fixup OSX zip filename -* Updated source repositories in README.md: Windows, macOS, Alpine Linux -* Compilation fixes ([#547](https://github.com/stlink-org/stlink/pull/547), [#551](https://github.com/stlink-org/stlink/pull/551), [#552](https://github.com/stlink-org/stlink/pull/552)) -* Stripped full paths to source files in log ([#548](https://github.com/stlink-org/stlink/pull/548)) -* Fixed incorrect release folder name in docs ([#560](https://github.com/stlink-org/stlink/pull/560)) -* Fixed compilation when path includes spaces ([#561](https://github.com/stlink-org/stlink/pull/561)) - +- `cmake/CPackConfig.cmake`: Fixup OSX zip filename +- Updated source repositories in README.md: Windows, macOS, Alpine Linux +- Compilation fixes ([#547](https://github.com/stlink-org/stlink/pull/547), [#551](https://github.com/stlink-org/stlink/pull/551), [#552](https://github.com/stlink-org/stlink/pull/552)) +- Stripped full paths to source files in log ([#548](https://github.com/stlink-org/stlink/pull/548)) +- Fixed incorrect release folder name in docs ([#560](https://github.com/stlink-org/stlink/pull/560)) +- Fixed compilation when path includes spaces ([#561](https://github.com/stlink-org/stlink/pull/561)) -v1.3.0 -====== +# v1.3.0 Release date: 2017-01-28 Major changes and added features: -* Deprecation of autotools (autoconf, automake) and fixed build with MinGW ([#83](https://github.com/stlink-org/stlink/pull/83), [#431](https://github.com/stlink-org/stlink/pull/431), [#434](https://github.com/stlink-org/stlink/pull/434), [#465](https://github.com/stlink-org/stlink/pull/465)) -* Added intel hex file reading for `st-flash` ([#110](https://github.com/stlink-org/stlink/pull/110), [#157](https://github.com/stlink-org/stlink/pull/157), [#457](https://github.com/stlink-org/stlink/pull/547), [#459](https://github.com/stlink-org/stlink/pull/549)) -* Added support for ARM semihosting to `st-util` ([#147](https://github.com/stlink-org/stlink/pull/147), [#227](https://github.com/stlink-org/stlink/pull/227), [#454](https://github.com/stlink-org/stlink/pull/454), [#455](https://github.com/stlink-org/stlink/pull/455)) -* Added manpages (generated with pandoc from Markdown) ([#208](https://github.com/stlink-org/stlink/pull/208), [#464](https://github.com/stlink-org/stlink/pull/464), [#466](https://github.com/stlink-org/stlink/pull/466), [#467](https://github.com/stlink-org/stlink/pull/467)) -* Removal of undocumented `st-term` utility, which is now replaced by `st-util` ARM semihosting feature ([#228](https://github.com/stlink-org/stlink/pull/228), [#507](https://github.com/stlink-org/stlink/pull/507), commit [#3fd0f09](https://github.com/stlink-org/stlink/commit/3fd0f099782506532198473b24f643a3f68d5ff9)) -* Support serial numbers argument for `st-util` and `st-flash` to probe and control multiple connected programmers ([#318](https://github.com/stlink-org/stlink/pull/318), [#398](https://github.com/stlink-org/stlink/pull/398), [#541](https://github.com/stlink-org/stlink/pull/541)) -* Merge st-probe tool into st-info ([#398](https://github.com/stlink-org/stlink/pull/398)) -* Added support for native debian packaging ([#444](https://github.com/stlink-org/stlink/pull/444), [#472](https://github.com/stlink-org/stlink/pull/472), [#473](https://github.com/stlink-org/stlink/pull/473), [#482](https://github.com/stlink-org/stlink/pull/482), [#483](https://github.com/stlink-org/stlink/pull/483), [#484](https://github.com/stlink-org/stlink/pull/484), [#485](https://github.com/stlink-org/stlink/pull/485)) -* Rewritten commandline parsing for `st-flash` ([#459](https://github.com/stlink-org/stlink/pull/459)) -* Added `--reset` command to `st-flash` ([#505](https://github.com/stlink-org/stlink/pull/505)) -* st-util should detect when USB commands fail ([#525](https://github.com/stlink-org/stlink/pull/525), [#527](https://github.com/stlink-org/stlink/pull/527), [#528](https://github.com/stlink-org/stlink/pull/528)) +- Deprecation of autotools (`autoconf`, `automake`) and fixed build with MinGW ([#83](https://github.com/stlink-org/stlink/pull/83), [#431](https://github.com/stlink-org/stlink/pull/431), [#434](https://github.com/stlink-org/stlink/pull/434), [#465](https://github.com/stlink-org/stlink/pull/465)) +- Added intel hex file reading for `st-flash` ([#110](https://github.com/stlink-org/stlink/pull/110), [#157](https://github.com/stlink-org/stlink/pull/157), [#457](https://github.com/stlink-org/stlink/pull/547), [#459](https://github.com/stlink-org/stlink/pull/549)) +- Added support for ARM semihosting to `st-util` ([#147](https://github.com/stlink-org/stlink/pull/147), [#227](https://github.com/stlink-org/stlink/pull/227), [#454](https://github.com/stlink-org/stlink/pull/454), [#455](https://github.com/stlink-org/stlink/pull/455)) +- Added manpages (generated with `pandoc` from Markdown) ([#208](https://github.com/stlink-org/stlink/pull/208), [#464](https://github.com/stlink-org/stlink/pull/464), [#466](https://github.com/stlink-org/stlink/pull/466), [#467](https://github.com/stlink-org/stlink/pull/467)) +- Removal of undocumented `st-term` utility, which is now replaced by `st-util` ARM semihosting feature ([#228](https://github.com/stlink-org/stlink/pull/228), [#507](https://github.com/stlink-org/stlink/pull/507), commit [#3fd0f09](https://github.com/stlink-org/stlink/commit/3fd0f099782506532198473b24f643a3f68d5ff9)) +- Support serial numbers argument for `st-util` and `st-flash` to probe and control multiple connected programmers ([#318](https://github.com/stlink-org/stlink/pull/318), [#398](https://github.com/stlink-org/stlink/pull/398), [#541](https://github.com/stlink-org/stlink/pull/541)) +- Merge `st-probe` tool into `st-info` ([#398](https://github.com/stlink-org/stlink/pull/398)) +- Added support for native debian packaging ([#444](https://github.com/stlink-org/stlink/pull/444), [#472](https://github.com/stlink-org/stlink/pull/472), [#473](https://github.com/stlink-org/stlink/pull/473), [#482](https://github.com/stlink-org/stlink/pull/482), [#483](https://github.com/stlink-org/stlink/pull/483), [#484](https://github.com/stlink-org/stlink/pull/484), [#485](https://github.com/stlink-org/stlink/pull/485)) +- Rewritten commandline parsing for `st-flash` ([#459](https://github.com/stlink-org/stlink/pull/459)) +- Added `--reset` command to `st-flash` ([#505](https://github.com/stlink-org/stlink/pull/505)) +- st-util should detect when USB commands fail ([#525](https://github.com/stlink-org/stlink/pull/525), [#527](https://github.com/stlink-org/stlink/pull/527), [#528](https://github.com/stlink-org/stlink/pull/528)) Chip support added for: -* STM32F401XE: Added memory map for device ([#460](https://github.com/stlink-org/stlink/pull/460)) -* STM32F410RBTx ([#418](https://github.com/stlink-org/stlink/pull/418)) -* STM32F412 ([#537](https://github.com/stlink-org/stlink/pull/537), [#538](https://github.com/stlink-org/stlink/pull/538)) -* STM32F7xx ([#324](https://github.com/stlink-org/stlink/pull/324), [#326](https://github.com/stlink-org/stlink/pull/326), [#327](https://github.com/stlink-org/stlink/pull/327), [#337](https://github.com/stlink-org/stlink/pull/337)) -* STM32F7x7x ([#433](https://github.com/stlink-org/stlink/pull/433), [#435](https://github.com/stlink-org/stlink/pull/435), [#436](https://github.com/stlink-org/stlink/pull/436), [#509](https://github.com/stlink-org/stlink/pull/509)) -* STM32L0xx Cat2 devices (chip-ID: 0x425) ([#414](https://github.com/stlink-org/stlink/pull/414)) -* STM32L0xx Cat5 devices (chip-ID: 0x447) ([#387](https://github.com/stlink-org/stlink/pull/387), [#406](https://github.com/stlink-org/stlink/pull/406)) -* STM32L4xx ([#321](https://github.com/stlink-org/stlink/pull/321)) -* STM32L432 ([#500](https://github.com/stlink-org/stlink/pull/500), [#501](https://github.com/stlink-org/stlink/pull/501)) +- STM32F401XE: Added memory map for device ([#460](https://github.com/stlink-org/stlink/pull/460)) +- STM32F410RBTx ([#418](https://github.com/stlink-org/stlink/pull/418)) +- STM32F412 ([#537](https://github.com/stlink-org/stlink/pull/537), [#538](https://github.com/stlink-org/stlink/pull/538)) +- STM32F7xx ([#324](https://github.com/stlink-org/stlink/pull/324), [#326](https://github.com/stlink-org/stlink/pull/326), [#327](https://github.com/stlink-org/stlink/pull/327), [#337](https://github.com/stlink-org/stlink/pull/337)) +- STM32F7x7x ([#433](https://github.com/stlink-org/stlink/pull/433), [#435](https://github.com/stlink-org/stlink/pull/435), [#436](https://github.com/stlink-org/stlink/pull/436), [#509](https://github.com/stlink-org/stlink/pull/509)) +- STM32L0xx Cat2 devices (chip-ID: 0x425) ([#414](https://github.com/stlink-org/stlink/pull/414)) +- STM32L0xx Cat5 devices (chip-ID: 0x447) ([#387](https://github.com/stlink-org/stlink/pull/387), [#406](https://github.com/stlink-org/stlink/pull/406)) +- STM32L4xx ([#321](https://github.com/stlink-org/stlink/pull/321)) +- STM32L432 ([#500](https://github.com/stlink-org/stlink/pull/500), [#501](https://github.com/stlink-org/stlink/pull/501)) Updates and fixes: -* Fixed "unaligned addr or size" when trying to write a program in RAM ([#323](https://github.com/stlink-org/stlink/pull/323)) -* Fixed flashing on STM32_F3_SMALL ([#325](https://github.com/stlink-org/stlink/pull/325)) -* Fixed STM32L-problem with flash loader ([#390](https://github.com/stlink-org/stlink/pull/390), [#407](https://github.com/stlink-org/stlink/pull/407), [#408](https://github.com/stlink-org/stlink/pull/408)) -* Don't read the target voltage on startup, because it crashes STM32F100 ([#423](https://github.com/stlink-org/stlink/pull/423), [#424](https://github.com/stlink-org/stlink/pull/424)) -* Added a useful error message instead of "[!] send_recv" ([#425](https://github.com/stlink-org/stlink/pull/425), [#426](https://github.com/stlink-org/stlink/pull/426)) -* Do a JTAG reset prior to reading CPU information when processor is in deep sleep ([#428](https://github.com/stlink-org/stlink/pull/428), [#430](https://github.com/stlink-org/stlink/pull/430), [#451](https://github.com/stlink-org/stlink/pull/451)) -* Fixed STM32F030 erase error ([#442](https://github.com/stlink-org/stlink/pull/442)) -* Fixed memory map for STM32F7xx ([#453](https://github.com/stlink-org/stlink/pull/453), [#456](https://github.com/stlink-org/stlink/pull/456)) -* Redesign of `st-flash` commandline options parsing ([#459](https://github.com/stlink-org/stlink/pull/459)) -* Set SWDCLK and fixed jtag_reset bug ([#462](https://github.com/stlink-org/stlink/pull/462), [#475](https://github.com/stlink-org/stlink/pull/475), [#534](https://github.com/stlink-org/stlink/pull/534)) -* doc/compiling.md: Add note about installation and ldconfig ([#478](https://github.com/stlink-org/stlink/pull/478), commit [#be66bbf](https://github.com/stlink-org/stlink/commit/be66bbf200c718904514b044ba84d64a36456218)) -* Fixed Release target to generate the man-pages with pandoc ([#479](https://github.com/stlink-org/stlink/pull/479)) -* Fixed Cygwin build ([#487](https://github.com/stlink-org/stlink/pull/487), ([#506](https://github.com/stlink-org/stlink/pull/506)) -* Reset flash mass erase (MER) bit after mass erase for safety ([#489](https://github.com/stlink-org/stlink/pull/489)) -* Wrong extract command in FindLibUSB.cmake ([#510](https://github.com/stlink-org/stlink/pull/510), [#511](https://github.com/stlink-org/stlink/pull/511)) -* Fixed compilation error on Ubuntu 16.10 ([#514](https://github.com/stlink-org/stlink/pull/514), [#525](https://github.com/stlink-org/stlink/pull/525)) - - -v1.2.0 -====== +- Fixed `unaligned addr or size` when trying to write a program in RAM ([#323](https://github.com/stlink-org/stlink/pull/323)) +- Fixed flashing on `STM32_F3_SMALL` ([#325](https://github.com/stlink-org/stlink/pull/325)) +- Fixed STM32L-problem with flash loader ([#390](https://github.com/stlink-org/stlink/pull/390), [#407](https://github.com/stlink-org/stlink/pull/407), [#408](https://github.com/stlink-org/stlink/pull/408)) +- Don't read the target voltage on startup, because it crashes STM32F100 ([#423](https://github.com/stlink-org/stlink/pull/423), [#424](https://github.com/stlink-org/stlink/pull/424)) +- Added a useful error message instead of `[!] send_recv` ([#425](https://github.com/stlink-org/stlink/pull/425), [#426](https://github.com/stlink-org/stlink/pull/426)) +- Do a JTAG reset prior to reading CPU information when processor is in deep sleep ([#428](https://github.com/stlink-org/stlink/pull/428), [#430](https://github.com/stlink-org/stlink/pull/430), [#451](https://github.com/stlink-org/stlink/pull/451)) +- Fixed STM32F030 erase error ([#442](https://github.com/stlink-org/stlink/pull/442)) +- Fixed memory map for STM32F7xx ([#453](https://github.com/stlink-org/stlink/pull/453), [#456](https://github.com/stlink-org/stlink/pull/456)) +- Redesign of `st-flash` commandline options parsing ([#459](https://github.com/stlink-org/stlink/pull/459)) +- Set `SWDCLK` and fixed `jtag_reset` bug ([#462](https://github.com/stlink-org/stlink/pull/462), [#475](https://github.com/stlink-org/stlink/pull/475), [#534](https://github.com/stlink-org/stlink/pull/534)) +- doc/compiling.md: Add note about installation and `ldconfig` ([#478](https://github.com/stlink-org/stlink/pull/478), commit [#be66bbf](https://github.com/stlink-org/stlink/commit/be66bbf200c718904514b044ba84d64a36456218)) +- Fixed Release target to generate the man-pages with `pandoc` ([#479](https://github.com/stlink-org/stlink/pull/479)) +- Fixed Cygwin build ([#487](https://github.com/stlink-org/stlink/pull/487), ([#506](https://github.com/stlink-org/stlink/pull/506)) +- Reset flash mass erase (MER) bit after mass erase for safety ([#489](https://github.com/stlink-org/stlink/pull/489)) +- Wrong extract command in `FindLibUSB.cmake` ([#510](https://github.com/stlink-org/stlink/pull/510), [#511](https://github.com/stlink-org/stlink/pull/511)) +- Fixed compilation error on Ubuntu 16.10 ([#514](https://github.com/stlink-org/stlink/pull/514), [#525](https://github.com/stlink-org/stlink/pull/525)) + +# v1.2.0 Release date: 2016-05-16 Features added: -* Added multiple stlink probing (`st-info --probe`, `st-info --hla-serial`) with printing serial in hex and OpenOCD `hla_serial` format (Jerry Jacobs) -* Added stlink usb probe API functions (Jerry Jacobs) -* Added parameter to specify one stlink v2 of many (Georg von Zengen) +- Added multiple stlink probing (`st-info --probe`, `st-info --hla-serial`) with printing serial in hex and OpenOCD `hla_serial` format (Jerry Jacobs) +- Added stlink usb probe API functions (Jerry Jacobs) +- Added parameter to specify one stlink v2 of many (Georg von Zengen) Updates and fixes: -* Refactoring/fixes of flash loader (Maxime Coquelin) -* Synchronized cache for STM32F7 (Tristan Gingold) -* Allow flashing of STM32L4 down to 1.71 V (Greg Meiste) -* Fix on STM32L4 to clear flash mass erase flags on CR (Bruno Dal Bo) -* Proper writing of page 0 of second bank for stm32l476xe (Tobias Badertscher) -* Trace the read data in stlink_read_debug32 and not the address of the variable (Tobias Badertscher) -* Mac OS X El Capitan platform support confirmation (Nikolay) -* Do not send a NUL at end of packets to gdb (Tristan Gingold) -* Correctly compute flash write size for partial pages (Dave Vandervies) -* _stlink_usb_reset use hardreset (mlundinse) -* Make sure MCU is halted before running RAM based flashloaders (mlundinse) -* Could not flash STM32_F3_SMALL (Max Chen) -* STM32F4 8-bit support for 1.8v operation (Andy Isaacson) -* Fixed STM32F2xx memory map (Nicolas Schodet) -* Memory map for STM32F42xxx and STM32F43xxx devices (Craig Lilley) -* Stm32l0x flash loader (Robin Kreis) -* Fixed segfault when programmer is already busy and NULL pointers are in the list ([#256](https://github.com/stlink-org/stlink/pull/256), [#394](https://github.com/stlink-org/stlink/pull/394)) -* Send F4 memory-map and features for STM32F429 ([#188](https://github.com/stlink-org/stlink/pull/188), [#196](https://github.com/stlink-org/stlink/pull/196), [#250](https://github.com/stlink-org/stlink/pull/250), [#251](https://github.com/stlink-org/stlink/pull/251)) (Release v1.1.0) -* Added AHB3 Peripherals definition for STM32F4 ([#218](https://github.com/stlink-org/stlink/pull/218), [#288](https://github.com/stlink-org/stlink/pull/288)) (Release v1.1.0) -* Corrected flash size register address for STM32F2 devices ([#278](https://github.com/stlink-org/stlink/pull/278)) (Release v1.0.0) +- Refactoring/fixes of flash loader (Maxime Coquelin) +- Synchronized cache for STM32F7 (Tristan Gingold) +- Allow flashing of STM32L4 down to 1.71 V (Greg Meiste) +- Fix on STM32L4 to clear flash mass erase flags on CR (Bruno Dal Bo) +- Proper writing of page 0 of second bank for STM32L476xe (Tobias Badertscher) +- Trace the read data in `stlink_read_debug32` and not the address of the variable (Tobias Badertscher) +- Mac OS X El Capitan platform support confirmation (Nikolay) +- Do not send a `NULL` at end of packets to `gdb` (Tristan Gingold) +- Correctly compute flash write size for partial pages (Dave Vandervies) +- `_stlink_usb_reset` use hardreset (mlundinse) +- Make sure MCU is halted before running RAM based flashloaders (mlundinse) +- Could not flash `STM32_F3_SMALL` (Max Chen) +- STM32F4 8-bit support for 1.8v operation (Andy Isaacson) +- Fixed STM32F2xx memory map (Nicolas Schodet) +- Memory map for STM32F42xxx and STM32F43xxx devices (Craig Lilley) +- Stm32l0x flash loader (Robin Kreis) +- Fixed segfault when programmer is already busy and `NULL` pointers are in the list ([#256](https://github.com/stlink-org/stlink/pull/256), [#394](https://github.com/stlink-org/stlink/pull/394)) +- Send F4 memory-map and features for STM32F429 ([#188](https://github.com/stlink-org/stlink/pull/188), [#196](https://github.com/stlink-org/stlink/pull/196), [#250](https://github.com/stlink-org/stlink/pull/250), [#251](https://github.com/stlink-org/stlink/pull/251)) (Release v1.1.0) +- Added AHB3 Peripherals definition for STM32F4 ([#218](https://github.com/stlink-org/stlink/pull/218), [#288](https://github.com/stlink-org/stlink/pull/288)) (Release v1.1.0) +- Corrected flash size register address for STM32F2 devices ([#278](https://github.com/stlink-org/stlink/pull/278)) (Release v1.0.0) Chip support added for: -* STM32L053R8 (Jean-Luc Béchennec) -* STM32F7 Support (mlundinse) -* Added STM32L4 to CHIPID #defines and devices[], flash driver and loader (Dave Vandervies) -* Basic support for STM32F446 (Pavel Kirienko) -* STM32F303 High Density -* STM32F469/STM32F479 ([#345](https://github.com/stlink-org/stlink/pull/345), [#555](https://github.com/stlink-org/stlink/pull/555)) (Release v1.2.0) -* STM32L1xx Cat.2 devices (Nicolas Schodet) -* STM32L1xx (chip-ID 0x427) ([#152](https://github.com/stlink-org/stlink/pull/152), [#163](https://github.com/stlink-org/stlink/pull/163), [#165](https://github.com/stlink-org/stlink/pull/165)) (Release v1.0.0) -* Added SIGINT handler for stlink cleanup ([#31](https://github.com/stlink-org/stlink/pull/31), [#135](https://github.com/stlink-org/stlink/pull/135)) (Release v1.0.0) +- STM32L053R8 (Jean-Luc Béchennec) +- STM32F7 Support (mlundinse) +- Added STM32L4 to CHIPID #defines and devices[], flash driver and loader (Dave Vandervies) +- Basic support for STM32F446 (Pavel Kirienko) +- STM32F303 High Density +- STM32F469/STM32F479 ([#345](https://github.com/stlink-org/stlink/pull/345), [#555](https://github.com/stlink-org/stlink/pull/555)) (Release v1.2.0) +- STM32L1xx Cat.2 devices (Nicolas Schodet) +- STM32L1xx (chip-ID 0x427) ([#152](https://github.com/stlink-org/stlink/pull/152), [#163](https://github.com/stlink-org/stlink/pull/163), [#165](https://github.com/stlink-org/stlink/pull/165)) (Release v1.0.0) +- Added `SIGINT` handler for stlink cleanup ([#31](https://github.com/stlink-org/stlink/pull/31), [#135](https://github.com/stlink-org/stlink/pull/135)) (Release v1.0.0) Board support added for: -* Nucleo-F303RE (Kyle Manna) -* Nucleo-F411RE (texane) +- Nucleo-F303RE (Kyle Manna) +- Nucleo-F411RE (texane) Build system: -* Travis: Initial support for Travis continues integration on Linux & Mac OS X (Jerry Jacobs) -* CMake: Document in README.md and add extra strict compiler flags (Jerry Jacobs) -* CMake: First stab at a cmake build (Josh Bialkowski) +- Travis: Initial support for Travis continues integration on Linux & Mac OS X (Jerry Jacobs) +- CMake: Document in README.md and add extra strict compiler flags (Jerry Jacobs) +- CMake: First stab at a `cmake` build (Josh Bialkowski) From 03793d42b6078344a9ef8ad55f1d5d0fc19e486e Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Thu, 11 Mar 2021 00:52:03 +0100 Subject: [PATCH 174/503] [doc] Added note on gdb 'run' command (Closes #267) --- doc/tutorial.md | 70 +++++++++++++++++++++++-------------------------- 1 file changed, 33 insertions(+), 37 deletions(-) diff --git a/doc/tutorial.md b/doc/tutorial.md index 1d20c68ee..f13c4c6f1 100644 --- a/doc/tutorial.md +++ b/doc/tutorial.md @@ -1,35 +1,37 @@ -stlink Tools Tutorial -===================== +# stlink Tools Tutorial ## Available tools and options -| Option | Tool | Description | Available
since | -| --- | --- | --- | --- | -| --flash=n[k][m] | st-flash | One can specify `--flash=128k` for example, to override the default value of 64k
for the STM32F103C8T6 to assume 128k of flash being present. This option accepts
decimal (128k), octal 0200k, or hex 0x80k values. Leaving the multiplier out is
equally valid, e.g.: `--flash=0x20000`. The size may be followed by an optional "k"
or "m" to multiply the given value by 1k (1024) or 1M respectively. | v1.4.0 | -| --freq=n[k][m] | st-flash,
st-util | The frequency of the SWD/JTAG interface can be specified, to override the default
1800 kHz configuration. This option solely accepts decimal values (5K or 1.8M) with
the unit `Hz` being left out. Valid frequencies are `5K, 15K, 25K, 50K, 100K,`
`125K, 240K, 480K, 950K, 1200K(1.2M), 1800K(1.8M), 4000K(4M)`. | v1.6.1 | -| --opt | st-flash | Optimisation can be enabled in order to skip flashing empty (0x00 or 0xff) bytes at
the end of binary file. This may cause some garbage data left after a flash operation.
This option was enabled by default in earlier releases. | v1.6.1 | -| --reset | st-flash | Trigger a reset both before and after flashing. | v1.0.0 | -| --version | st-info,
st-flash,
st-util | Print version information. | | -| --help | st-flash,
st-util | Print list of available commands. _(To be added to this table.)_ | | +| Option | Tool | Description | Available
since | +| --------------- | ------------------------------------ | ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | -------------------- | +| --flash=n[k][m] | st-flash | One can specify `--flash=128k` for example, to override the default value of 64k
for the STM32F103C8T6 to assume 128k of flash being present. This option accepts
decimal (128k), octal 0200k, or hex 0x80k values. Leaving the multiplier out is
equally valid, e.g.: `--flash=0x20000`. The size may be followed by an optional "k"
or "m" to multiply the given value by 1k (1024) or 1M respectively. | v1.4.0 | +| --freq=n[k][m] | st-flash,
st-util | The frequency of the SWD/JTAG interface can be specified, to override the default
1800 kHz configuration. This option solely accepts decimal values (5K or 1.8M) with
the unit `Hz` being left out. Valid frequencies are `5K, 15K, 25K, 50K, 100K,`
`125K, 240K, 480K, 950K, 1200K(1.2M), 1800K(1.8M), 4000K(4M)`. | v1.6.1 | +| --opt | st-flash | Optimisation can be enabled in order to skip flashing empty (0x00 or 0xff) bytes at
the end of binary file. This may cause some garbage data left after a flash operation.
This option was enabled by default in earlier releases. | v1.6.1 | +| --reset | st-flash | Trigger a reset both before and after flashing. | v1.0.0 | +| --version | st-info,
st-flash,
st-util | Print version information. | | +| --help | st-flash,
st-util | Print list of available commands. _(To be added to this table.)_ | | ### st-flash: Checksum for binary files + When flashing a file, a checksum is calculated for the binary file, both in md5 and the sum algorithm. The latter is also used by the official ST-Link utility tool from STMicroelectronics as described in the document: [`UM0892 - User manual - STM32 ST-LINK utility software description`](https://www.st.com/resource/en/user_manual/cd00262073-stm32-stlink-utility-software-description-stmicroelectronics.pdf). ### stlink-gui + The `stlink` toolset also provides a GUI which is an optional feature. It is only installed if a gtk3 toolset has been detected during package installation or compilation from source. It is not available for Windows. If you prefer to have an user interface on the latter system, please use the official `ST-LINK Utility` instead. The stlink-gui offers the following features: -* Connect/disconnect to a present STlink programmer -* Display basic device information -* Select a binary file from the local filesystem to flash it to the detected device connected to the programmer -* Export the memory of the connected chip to a file which can be saved to the local filesystem -* Display of the memory address map in the main window for each, the device memory and a loaded binary file -Within the GUI main window tooltips explain the available user elements. +- Connect/disconnect to a present STlink programmer +- Display basic device information +- Select a binary file from the local filesystem to flash it to the detected device connected to the programmer +- Export the memory of the connected chip to a file which can be saved to the local filesystem +- Display of the memory address map in the main window for each, the device memory and a loaded binary file +Within the GUI main window tooltips explain the available user elements. ## Solutions to common problems + ### a) Verify if udev rules are set correctly (by Dave Hylands) To investigate, start by plugging your STLINK device into the usb port. Then run `lsusb`. You should see an entry something like the following: @@ -77,7 +79,6 @@ to ensure that the rules actually take effect. Using the trigger command means t If the VID:PID of your device doesn't match those in any of the 3 files, then you may need to create a custom rule file to match your VID:PID. - ### b) NOTE: Chinese Fake-Chips CKS32F103C8T6 or CS32F103C8T6 being marked as "STM32F103C8T6" In contrast to "Clone chips" which identify themselves as such by their official marking (manufacturer, model, etc.), so called "Fake chips" do not. @@ -89,8 +90,8 @@ In this known example one finds the counterfeited "STM32F103C8T6" MCUs to identi In the following you find some hints on how to identify your chip and track down fraud: -* [How to Detect STM32 Fakes](https://www.cnx-software.com/2020/03/22/how-to-detect-stm32-fakes/) -* [Confirmation by STMicroelectronics](https://www.mikrocontroller.net/attachment/442839/couterfeit_STM.png) (Marking: 991KA 93 MYS 807) +- [How to Detect STM32 Fakes](https://www.cnx-software.com/2020/03/22/how-to-detect-stm32-fakes/) +- [Confirmation by STMicroelectronics](https://www.mikrocontroller.net/attachment/442839/couterfeit_STM.png) (Marking: 991KA 93 MYS 807) However it appears that not all counterfeited parts cause problems during operation, but some are known to not even being able to execute a basic "blinky" example binary. Further there can be problems that may not even show up or affect you directly, but somewhen later in time (or maybe never). This demonstrates there is no guarantee for a proper working chip with equal functionality compared to the original. @@ -100,11 +101,11 @@ Check your hardware and try to identify what you have in front of you before ass Please let us know, if you come across any further websites or tutorials that help to identify STM32 fake chips so we can list them here to help others. ------- +--- + ( Content below is currently unrevised and may be outdated as of Apr 2020. ) -Using STM32 discovery kits with open source tools -======== +# Using STM32 discovery kits with open source tools This guide details the use of STMicroelectronics STM32 discovery kits in an open source environment. @@ -121,11 +122,11 @@ from any vendor. It has some good, reliable examples for each of the Discovery b Even if you don’t plan on using libopencm3, the examples they provide will help you verify that: -- Your installed toolchain is capable of compiling for cortex M3/M4 - targets -- stlink is functional -- Your arm-none-eabi-gdb is functional -- Your board is functional +- Your installed toolchain is capable of compiling for cortex M3/M4 + targets +- stlink is functional +- Your arm-none-eabi-gdb is functional +- Your board is functional A GDB server must be started to interact with the STM32 by running st-util tool : @@ -173,7 +174,6 @@ Your program should now be running, and, if you used one of the blinking examples from libopencm3, the LEDs on the board should be blinking for you. - ## Building and flashing a program If you want to simply flash binary files to arbitrary sections of @@ -207,7 +207,6 @@ $> [sudo] ./st-flash write fancy_blink.bin 0x08000000 Upon reset, the board LEDs should be blinking. - ## Using the gdb server To run the gdb server: @@ -252,7 +251,6 @@ Transfer rate: 1 KB/sec, 560 bytes/write. (gdb) continue ``` - ## Resetting the chip from GDB You may reset the chip using GDB if you want. You'll need to use `target @@ -268,6 +266,9 @@ Kill the program being debugged? (y or n) y Starting program: /home/whitequark/ST/apps/bally/firmware.elf ``` +Note that st-link does not support 'run', as it does not load arbitrary programs without explicit commands. +In order to continue, one can use 'monitor reset' to reset the MCU. + Remember that you can shorten the commands. `tar ext :4242` is good enough for GDB. @@ -277,7 +278,6 @@ If you need to send a hard reset signal through `NRST` pin, you can use the foll (gdb) monitor jtag_reset ``` - ## Disassembling THUMB code in GDB By default, the disassemble command in GDB operates in ARM mode. The programs running on CORTEX-M3 are compiled in THUMB mode. @@ -287,7 +287,6 @@ To correctly disassemble them under GDB, uses an odd address. For instance, if y (gdb) disassemble 0x20000001 ``` - ## Running programs from SRAM You can run your firmware directly from SRAM if you want to. Just link @@ -300,7 +299,6 @@ it at 0x20000000 and do It will be loaded, and pc will be adjusted to point to start of the code, if it is linked correctly (i.e. ELF has correct entry point). - ## Writing to flash The GDB stub ships with a correct memory map, including the flash area. @@ -312,18 +310,16 @@ If you would link your executable to `0x08000000` and then do then it would be written to the memory. - ## Writing Option Bytes Example to read and write option bytes (currently writing only supported for STM32G0 and STM32L0) + ``` ./st-flash --debug --reset --format binary --flash=128k read option_bytes_dump.bin 0x1FFF7800 4 ./st-flash --debug --reset --format binary --flash=128k write option_bytes_dump.bin 0x1FFF7800 ``` - -FAQ -=== +# FAQ Q: My breakpoints do not work at all or only work once. From 45e9b5ee6e8e2128b837de064ab1a84f6f24c9c3 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Thu, 11 Mar 2021 14:15:37 +0100 Subject: [PATCH 175/503] General Project Update - Updated CHANGELOG.md - Updated list of contributors - Fixed travis CI build settings --- .travis.yml | 15 +++++++-------- CHANGELOG.md | 10 +++++++++- contributors.txt | 1 + 3 files changed, 17 insertions(+), 9 deletions(-) diff --git a/.travis.yml b/.travis.yml index 4437b3148..fefafbaf1 100644 --- a/.travis.yml +++ b/.travis.yml @@ -30,11 +30,11 @@ jobs: - os: linux dist: xenial env: BADGE=linux - compiler: clang-8 + compiler: clang addons: apt: - sources: ["ubuntu-toolchain-r-test", "llvm-toolchain-xenial-3.7"] - packages: ["clang-8", "libusb-1.0.0-dev", "libgtk-3-dev", "rpm"] + sources: ["ubuntu-toolchain-r-test"] + packages: ["libusb-1.0.0-dev", "libgtk-3-dev", "rpm"] - os: linux dist: bionic env: BADGE=linux @@ -98,11 +98,11 @@ jobs: - os: linux dist: xenial env: BADGE=linux - compiler: clang-8 + compiler: clang addons: apt: - sources: ["ubuntu-toolchain-r-test", "llvm-toolchain-xenial-3.7"] - packages: ["clang-8", "libusb-1.0.0-dev", "libgtk-3-dev", "rpm"] + sources: ["ubuntu-toolchain-r-test"] + packages: ["libusb-1.0.0-dev", "libgtk-3-dev", "rpm"] before_install: - CFLAGS="$CFLAGS -m32"; CXXFLAGS="$CXXFLAGS -m32"; LDFLAGS="$LDFLAGS -m32"; - os: linux @@ -111,11 +111,10 @@ jobs: compiler: clang-10 addons: apt: - sources: ["ubuntu-toolchain-r-test", "llvm-toolchain-bionic-6.0"] + sources: ["ubuntu-toolchain-r-test"] packages: ["clang-10", "libusb-1.0.0-dev", "libgtk-3-dev", "rpm"] before_install: - CFLAGS="$CFLAGS -m32"; CXXFLAGS="$CXXFLAGS -m32"; LDFLAGS="$LDFLAGS -m32"; - before_install: - os: linux dist: focal env: BADGE=linux diff --git a/CHANGELOG.md b/CHANGELOG.md index c4adaf2ba..912092b65 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -16,14 +16,19 @@ Features: - Link for WIN32 & APPLE with stlink-static ([#1069](https://github.com/stlink-org/stlink/pull/1069)) - Extended support for STM32H7 ([#1059](https://github.com/stlink-org/stlink/pull/1059), [#1063](https://github.com/stlink-org/stlink/pull/1063), [#1071](https://github.com/stlink-org/stlink/pull/1071)) - ITM functionality for STLink/V2 and STM32Fxx chipsets ([#136](https://github.com/stlink-org/stlink/pull/136), [#179](https://github.com/stlink-org/stlink/pull/179), [#815](https://github.com/stlink-org/stlink/pull/815), [#1072](https://github.com/stlink-org/stlink/pull/1072)) +- Included ITM functionality for building with MSVC ([#1080](https://github.com/stlink-org/stlink/pull/1080)) Updates & changes: +- [doc] Added note on `(gdb) run` command (commit [#03793d4](https://github.com/stlink-org/stlink/commit/03793d42b6078344a9ef8ad55f1d5d0fc19e486e), [#276](https://github.com/stlink-org/stlink/pull/276)) - [doc] `st-flash --reset` parameter (one solution for #356) ([#642](https://github.com/stlink-org/stlink/pull/642)) - [refactoring] General maintenance ([#864](https://github.com/stlink-org/stlink/pull/864), [#976](https://github.com/stlink-org/stlink/pull/976), [#978](https://github.com/stlink-org/stlink/pull/978)) - Imported debian pkg-settings ([#986](https://github.com/stlink-org/stlink/pull/986)) - Add support for FreeBSD's `libusb` reimplementation ([#992](https://github.com/stlink-org/stlink/pull/992), [#993](https://github.com/stlink-org/stlink/pull/993)) +- [doc] Added explanation about STM32F103 fake chips (commit [#a66557a](https://github.com/stlink-org/stlink/commit/a66557a102d48e69feb0a9746e8e42c4baf31fe2), [#1024](https://github.com/stlink-org/stlink/pull/1024)) - [doc] Added example for output of `st-info --probe` ([#1007](https://github.com/stlink-org/stlink/pull/1007), [#1049](https://github.com/stlink-org/stlink/pull/1049)) +- [refactoring] Correctly handle endianness without reference to host platform ([#1081](https://github.com/stlink-org/stlink/pull/1081)) +- Check format string for log messages ([#1093](https://github.com/stlink-org/stlink/pull/1093)) Fixes: @@ -33,7 +38,7 @@ Fixes: - Fixed installation path for desktop-file and icons ([#972](https://github.com/stlink-org/stlink/pull/972)) - Fix for static linking of `libssp` ([#973](https://github.com/stlink-org/stlink/pull/973), [#974](https://github.com/stlink-org/stlink/pull/974)) - [regression] Fixed wrong formatting for library install path ([#978](https://github.com/stlink-org/stlink/pull/978), [#1089](https://github.com/stlink-org/stlink/pull/1089)) -- Fixed installation of header files needed for compiling with `libstlink.so.1.6.1` ([#982](https://github.com/stlink-org/stlink/pull/982)) +- Fixed installation of header files needed for compiling with `libstlink.so.1.6.1` (commit [#31b1fa1](https://github.com/stlink-org/stlink/commit/31b1fa16201521e2aaf464576f2f169981abede0), [#982](https://github.com/stlink-org/stlink/pull/982)) - Fixed `connect under reset` for `st-flash` and `st-util` ([#983](https://github.com/stlink-org/stlink/pull/983)) - Fix for `mmap() size_t overflow` in `st-flash` ([#988](https://github.com/stlink-org/stlink/pull/988), [#989](https://github.com/stlink-org/stlink/pull/989)) - [regression] `stlink-gui` installation issue on Ubuntu-18.04 ([#1001](https://github.com/stlink-org/stlink/pull/1001), [#1004](https://github.com/stlink-org/stlink/pull/1004), [#1006](https://github.com/stlink-org/stlink/pull/1006)) @@ -41,7 +46,9 @@ Fixes: - [doc] Fixed wrong path for `rules.d` folder ([#1020](https://github.com/stlink-org/stlink/pull/1020)) - Use vl flashloader for all STM32F1 series ([#1041](https://github.com/stlink-org/stlink/pull/1041), [#1044](https://github.com/stlink-org/stlink/pull/1044)) - Fixed `gettimeofday` for MSVC ([#1074](https://github.com/stlink-org/stlink/pull/1074)) +- Bugfixes for compilation with clang ([#1076](https://github.com/stlink-org/stlink/pull/1076), [#1078](https://github.com/stlink-org/stlink/pull/1078)) - Fixed compilation with GCC 11 ([#1077](https://github.com/stlink-org/stlink/pull/1077)) +- [regression] Flash_loader: increased wait rounds for slow boards ([#1085](https://github.com/stlink-org/stlink/pull/1085)) # v1.6.1 @@ -371,6 +378,7 @@ Updates and fixes: - Fixed STM32F2xx memory map (Nicolas Schodet) - Memory map for STM32F42xxx and STM32F43xxx devices (Craig Lilley) - Stm32l0x flash loader (Robin Kreis) +- Use libusb synchronous api ([#194](https://github.com/stlink-org/stlink/pull/194), [#374](https://github.com/stlink-org/stlink/pull/374)) - Fixed segfault when programmer is already busy and `NULL` pointers are in the list ([#256](https://github.com/stlink-org/stlink/pull/256), [#394](https://github.com/stlink-org/stlink/pull/394)) - Send F4 memory-map and features for STM32F429 ([#188](https://github.com/stlink-org/stlink/pull/188), [#196](https://github.com/stlink-org/stlink/pull/196), [#250](https://github.com/stlink-org/stlink/pull/250), [#251](https://github.com/stlink-org/stlink/pull/251)) (Release v1.1.0) - Added AHB3 Peripherals definition for STM32F4 ([#218](https://github.com/stlink-org/stlink/pull/218), [#288](https://github.com/stlink-org/stlink/pull/288)) (Release v1.1.0) diff --git a/contributors.txt b/contributors.txt index 57801b9ab..38cc9cd42 100644 --- a/contributors.txt +++ b/contributors.txt @@ -74,6 +74,7 @@ Karl Palsson [karlp] Kevlar Harness Kyle Manna Lari Lehtomäki +Luuk van Dijk [lvdlvd] Martin Nowak Matteo Collina Max Chen From c0236dd12c9f07e78b73f774bf028dc102d8f04b Mon Sep 17 00:00:00 2001 From: Michael Nolan Date: Thu, 11 Mar 2021 13:22:00 -0500 Subject: [PATCH 176/503] Hopefully fix reading an invalid chip ID on STM32WB55 --- src/common.c | 30 ++++++++++++++++++++++++++++-- 1 file changed, 28 insertions(+), 2 deletions(-) diff --git a/src/common.c b/src/common.c index 99049196d..242b690af 100644 --- a/src/common.c +++ b/src/common.c @@ -1222,8 +1222,34 @@ int stlink_chip_id(stlink_t *sl, uint32_t *chip_id) { int ret; if (sl->core_id == STM32H7_CORE_ID) { - // STM32H7 chipid in 0x5c001000 (RM0433 pg3189) - ret = stlink_read_debug32(sl, 0x5c001000, chip_id); + /* STM32H7 chipid in 0x5c001000 (RM0433 pg3189) + * However, the STM32H7 is not the only chip with a JTAG + * IDCODE of 0x6ba02477, so we cannot rely solely on this info + * to select the address to read the chip id */ + + uint32_t chip_id_tmp; + // try reading from 0x5c001000 + ret = stlink_read_debug32(sl, 0x5c001000, &chip_id_tmp); + + // Extract the DEV_ID/CHIPID + uint32_t h7_chip_id = chip_id_tmp & 0xfff; + + if(ret != -1){ + // If we successfully read a H7 chip ID, return that + if((h7_chip_id == STLINK_CHIPID_STM32_H74XXX) || + (h7_chip_id == STLINK_CHIPID_STM32_H7AX) || + (h7_chip_id == STLINK_CHIPID_STM32_H72X)) { + *chip_id = chip_id_tmp; + return(ret); + } + } + + // If we had an error or were unsuccessful at reading an H7 + // series chip ID, try reading the chip ID from the default + // address + ret = stlink_read_debug32(sl, 0xE0042000, chip_id); + + } else { // default chipid address ret = stlink_read_debug32(sl, 0xE0042000, chip_id); From eff18d81d9c64ef9eaf4972d800de09be13ff141 Mon Sep 17 00:00:00 2001 From: 2a17 Date: Thu, 11 Mar 2021 23:04:14 +0000 Subject: [PATCH 177/503] option byte support improved --- src/st-flash/flash_opts.c | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/src/st-flash/flash_opts.c b/src/st-flash/flash_opts.c index e74ecc1ce..2ef72c12a 100644 --- a/src/st-flash/flash_opts.c +++ b/src/st-flash/flash_opts.c @@ -337,12 +337,27 @@ int flash_get_opts(struct flash_opts* o, int ac, char** av) { if (ac == 2) { uint32_t addr; - result = get_integer_from_char_array(av[1], &addr); + result = get_integer_from_char_array(av[0], &addr); if (result != 0) { return bad_arg ("addr"); } else { o->addr = (stm32_addr_t) addr; } + uint32_t val; + result = get_integer_from_char_array(av[1], &val); + if (result != 0) { + return bad_arg ("val"); + } else { + o->val = (uint32_t) val; + } + } else { + uint32_t val; + result = get_integer_from_char_array(av[0], &val); + if (result != 0) { + return bad_arg ("val"); + } else { + o->val = (uint32_t) val; + } } } else if (o->area == FLASH_OPTION_BYTES_BOOT_ADD) { // expect option bytes boot address if (ac != 1) { return invalid_args("option bytes boot_add write "); } From 93c59cc5c2bacf5901ad4550bf7a9a4041369dac Mon Sep 17 00:00:00 2001 From: 2a17 Date: Thu, 11 Mar 2021 23:49:51 +0000 Subject: [PATCH 178/503] spelling mistake 'feature request' changed to 'bug report' in bug report template --- .github/ISSUE_TEMPLATE/bug-report.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/ISSUE_TEMPLATE/bug-report.md b/.github/ISSUE_TEMPLATE/bug-report.md index a1b9d65a0..0e22c2ce9 100644 --- a/.github/ISSUE_TEMPLATE/bug-report.md +++ b/.github/ISSUE_TEMPLATE/bug-report.md @@ -8,7 +8,7 @@ labels: '' Thank you for giving feedback to the stlink project. **NOTICE: Please read and follow instructions in #906 before submitting a ticket. -This feature request will be deleted without notice when not enough information is provided! So please ensure that all fields are filled out.** +This bug report will be deleted without notice when not enough information is provided! So please ensure that all fields are filled out.** - [ ] I made serious effort to avoid creating duplicate or nearly similar issue From 7729fea5ed2bc743c64578f9690c40fff58a9821 Mon Sep 17 00:00:00 2001 From: 2a17 Date: Fri, 12 Mar 2021 12:22:58 +0000 Subject: [PATCH 179/503] unused parameter removed, comment and return message updated --- src/st-flash/flash_opts.c | 36 +++++++----------------------------- 1 file changed, 7 insertions(+), 29 deletions(-) diff --git a/src/st-flash/flash_opts.c b/src/st-flash/flash_opts.c index 2ef72c12a..2ee19bd48 100644 --- a/src/st-flash/flash_opts.c +++ b/src/st-flash/flash_opts.c @@ -328,36 +328,14 @@ int flash_get_opts(struct flash_opts* o, int ac, char** av) { case FLASH_CMD_WRITE: // TODO: should be boot add 0 and boot add 1 uint32 - if (o->area == FLASH_OPTION_BYTES) { // expect filename and optional address - if (ac >=1 && ac <= 2) { - o->filename = av[0]; - } else { - return invalid_args("write [addr]"); - } - - if (ac == 2) { - uint32_t addr; - result = get_integer_from_char_array(av[0], &addr); - if (result != 0) { - return bad_arg ("addr"); - } else { - o->addr = (stm32_addr_t) addr; - } - uint32_t val; - result = get_integer_from_char_array(av[1], &val); - if (result != 0) { - return bad_arg ("val"); - } else { - o->val = (uint32_t) val; - } + if (o->area == FLASH_OPTION_BYTES) { // expect option byte value + if (ac != 1) { return invalid_args("option byte write "); } + uint32_t val; + result = get_integer_from_char_array(av[0], &val); + if (result != 0) { + return bad_arg ("val"); } else { - uint32_t val; - result = get_integer_from_char_array(av[0], &val); - if (result != 0) { - return bad_arg ("val"); - } else { - o->val = (uint32_t) val; - } + o->val = (uint32_t) val; } } else if (o->area == FLASH_OPTION_BYTES_BOOT_ADD) { // expect option bytes boot address if (ac != 1) { return invalid_args("option bytes boot_add write "); } From e5767681f14de9851aa970a9299930ca68b2ed92 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Fri, 12 Mar 2021 18:39:08 +0100 Subject: [PATCH 180/503] [doc] Corrected tutorial.md Corrected info on --freq argument (Closes #1055) --- doc/tutorial.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/doc/tutorial.md b/doc/tutorial.md index f13c4c6f1..3a0f16fd9 100644 --- a/doc/tutorial.md +++ b/doc/tutorial.md @@ -5,7 +5,7 @@ | Option | Tool | Description | Available
since | | --------------- | ------------------------------------ | ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | -------------------- | | --flash=n[k][m] | st-flash | One can specify `--flash=128k` for example, to override the default value of 64k
for the STM32F103C8T6 to assume 128k of flash being present. This option accepts
decimal (128k), octal 0200k, or hex 0x80k values. Leaving the multiplier out is
equally valid, e.g.: `--flash=0x20000`. The size may be followed by an optional "k"
or "m" to multiply the given value by 1k (1024) or 1M respectively. | v1.4.0 | -| --freq=n[k][m] | st-flash,
st-util | The frequency of the SWD/JTAG interface can be specified, to override the default
1800 kHz configuration. This option solely accepts decimal values (5K or 1.8M) with
the unit `Hz` being left out. Valid frequencies are `5K, 15K, 25K, 50K, 100K,`
`125K, 240K, 480K, 950K, 1200K(1.2M), 1800K(1.8M), 4000K(4M)`. | v1.6.1 | +| --freq=n[k][m] | st-flash | The frequency of the SWD/JTAG interface can be specified, to override the default
1800 kHz configuration. This option solely accepts decimal values (5K or 1.8M) with
the unit `Hz` being left out. Valid frequencies are: `5K, 15K, 25K, 50K, 100K,`
`125K, 240K, 480K, 950K, 1200K(1.2M), 1800K(1.8M), 4000K(4M)`. | v1.6.1 | | --opt | st-flash | Optimisation can be enabled in order to skip flashing empty (0x00 or 0xff) bytes at
the end of binary file. This may cause some garbage data left after a flash operation.
This option was enabled by default in earlier releases. | v1.6.1 | | --reset | st-flash | Trigger a reset both before and after flashing. | v1.0.0 | | --version | st-info,
st-flash,
st-util | Print version information. | | From dd877b1883b94f4529f3765883f1ce1fe4744fa1 Mon Sep 17 00:00:00 2001 From: anton Date: Sun, 14 Mar 2021 21:09:40 +0500 Subject: [PATCH 181/503] Fixing support of stlink v1 --- src/stlink-lib/usb.c | 13 +++++-------- 1 file changed, 5 insertions(+), 8 deletions(-) diff --git a/src/stlink-lib/usb.c b/src/stlink-lib/usb.c index 0168834ca..d2b17fad6 100644 --- a/src/stlink-lib/usb.c +++ b/src/stlink-lib/usb.c @@ -301,7 +301,7 @@ int _stlink_usb_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { if (ret == -1) { return(ret); } - ret = send_only(slu, 0, data, len); + ret = send_only(slu, 1, data, len); if (ret == -1) { return(ret); } @@ -431,6 +431,8 @@ int _stlink_usb_status(stlink_t * sl) { } else { sl->core_stat = TARGET_UNKNOWN; } + } else { + sl->core_stat = TARGET_UNKNOWN; } return(0); @@ -469,19 +471,14 @@ int _stlink_usb_enter_swd_mode(stlink_t * sl) { unsigned char* const cmd = sl->c_buf; ssize_t size; unsigned char* const data = sl->q_buf; - const uint32_t rep_len = sl->version.stlink_v > 1 ? 2 : 0; + const uint32_t rep_len = sl->version.jtag_api == STLINK_JTAG_API_V1 ? 0 : 2; int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); cmd[i++] = STLINK_DEBUG_COMMAND; // select correct API-Version for entering SWD mode: V1 API (0x20) or V2 API (0x30). cmd[i++] = sl->version.jtag_api == STLINK_JTAG_API_V1 ? STLINK_DEBUG_APIV1_ENTER : STLINK_DEBUG_APIV2_ENTER; cmd[i++] = STLINK_DEBUG_ENTER_SWD; - - if (rep_len == 0) { - size = send_only(slu, 1, cmd, slu->cmd_len); - } else { - size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); - } + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); if (size == -1) { printf("[!] send_recv STLINK_DEBUG_ENTER\n"); From c39ed921e39519eb30084b22b8539d19ae5df741 Mon Sep 17 00:00:00 2001 From: Michael Nolan Date: Sun, 14 Mar 2021 20:53:00 -0400 Subject: [PATCH 182/503] Implement changes suggested by Ant-ON to select the chipid register --- src/common.c | 36 ++++++++++++++++-------------------- src/stlink-lib/reg.h | 5 +++++ 2 files changed, 21 insertions(+), 20 deletions(-) diff --git a/src/common.c b/src/common.c index 242b690af..a064254d3 100644 --- a/src/common.c +++ b/src/common.c @@ -1227,28 +1227,24 @@ int stlink_chip_id(stlink_t *sl, uint32_t *chip_id) { * IDCODE of 0x6ba02477, so we cannot rely solely on this info * to select the address to read the chip id */ - uint32_t chip_id_tmp; - // try reading from 0x5c001000 - ret = stlink_read_debug32(sl, 0x5c001000, &chip_id_tmp); - - // Extract the DEV_ID/CHIPID - uint32_t h7_chip_id = chip_id_tmp & 0xfff; - - if(ret != -1){ - // If we successfully read a H7 chip ID, return that - if((h7_chip_id == STLINK_CHIPID_STM32_H74XXX) || - (h7_chip_id == STLINK_CHIPID_STM32_H7AX) || - (h7_chip_id == STLINK_CHIPID_STM32_H72X)) { - *chip_id = chip_id_tmp; - return(ret); - } + uint32_t cpu_id; + *chip_id = 0; + ret = -1; + + // Read the CPU ID as well to determine if this really is an H7 part + if (stlink_read_debug32(sl, STLINK_REG_CM3_CPUID, &cpu_id)) + cpu_id = 0; + + // If it is, read the chipid from the new address + if (sl->core_id == STM32H7_CORE_ID && cpu_id == STLINK_REG_CMx_CPUID_CM7) { + // STM32H7 chipid in 0x5c001000 (RM0433 pg3189) + ret = stlink_read_debug32(sl, 0x5c001000, chip_id); } - // If we had an error or were unsuccessful at reading an H7 - // series chip ID, try reading the chip ID from the default - // address - ret = stlink_read_debug32(sl, 0xE0042000, chip_id); - + if (*chip_id == 0) { + // default chipid address + ret = stlink_read_debug32(sl, 0xE0042000, chip_id); + } } else { // default chipid address diff --git a/src/stlink-lib/reg.h b/src/stlink-lib/reg.h index 6d2c9f1af..5a796d7e1 100644 --- a/src/stlink-lib/reg.h +++ b/src/stlink-lib/reg.h @@ -3,6 +3,11 @@ #define STLINK_REG_CM3_CPUID 0xE000ED00 +#define STLINK_REG_CMx_CPUID_CM0 0x410CC200 +#define STLINK_REG_CMx_CPUID_CM3 0x412FC230 +#define STLINK_REG_CMx_CPUID_CM7 0x411FC272 + + #define STLINK_REG_CM3_FP_CTRL 0xE0002000 // Flash Patch Control Register #define STLINK_REG_CM3_FP_COMPn(n) (0xE0002008 + n*4) #define STLINK_REG_CM3_FP_CTRL_KEY (1 << 1) From 125cb2d7634d5cbc916e9c4bac6ddf80407ab605 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Wed, 17 Mar 2021 23:26:48 +0100 Subject: [PATCH 183/503] General Project Update - Updated CHANGELOG.md - Updated README.md - Formatting fixes -[doc] Updated tested devices & boards --- CHANGELOG.md | 10 +- README.md | 61 +++++----- doc/devices_boards.md | 253 +++++++++++++++++++++-------------------- doc/version_support.md | 112 +++++++++--------- 4 files changed, 217 insertions(+), 219 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index 912092b65..cacd79eef 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -20,7 +20,7 @@ Features: Updates & changes: -- [doc] Added note on `(gdb) run` command (commit [#03793d4](https://github.com/stlink-org/stlink/commit/03793d42b6078344a9ef8ad55f1d5d0fc19e486e), [#276](https://github.com/stlink-org/stlink/pull/276)) +- [doc] Added note on `(gdb) run` command (commit [#03793d4](https://github.com/stlink-org/stlink/commit/03793d42b6078344a9ef8ad55f1d5d0fc19e486e), [#267](https://github.com/stlink-org/stlink/pull/267)) - [doc] `st-flash --reset` parameter (one solution for #356) ([#642](https://github.com/stlink-org/stlink/pull/642)) - [refactoring] General maintenance ([#864](https://github.com/stlink-org/stlink/pull/864), [#976](https://github.com/stlink-org/stlink/pull/976), [#978](https://github.com/stlink-org/stlink/pull/978)) - Imported debian pkg-settings ([#986](https://github.com/stlink-org/stlink/pull/986)) @@ -42,13 +42,17 @@ Fixes: - Fixed `connect under reset` for `st-flash` and `st-util` ([#983](https://github.com/stlink-org/stlink/pull/983)) - Fix for `mmap() size_t overflow` in `st-flash` ([#988](https://github.com/stlink-org/stlink/pull/988), [#989](https://github.com/stlink-org/stlink/pull/989)) - [regression] `stlink-gui` installation issue on Ubuntu-18.04 ([#1001](https://github.com/stlink-org/stlink/pull/1001), [#1004](https://github.com/stlink-org/stlink/pull/1004), [#1006](https://github.com/stlink-org/stlink/pull/1006)) -- `st-util`: wrong register values passed to `gdb` (STLink/V2) ([#1002](https://github.com/stlink-org/stlink/pull/1002), [#1011](https://github.com/stlink-org/stlink/pull/1011), [#1026](https://github.com/stlink-org/stlink/pull/1026), [#1027](https://github.com/stlink-org/stlink/pull/1027)) +- `st-util`: wrong register values passed to `gdb` (STLink/V2) ([#1002](https://github.com/stlink-org/stlink/pull/1002), [#1011](https://github.com/stlink-org/stlink/pull/1011), [#1026](https://github.com/stlink-org/stlink/pull/1026), [#1027](https://github.com/stlink-org/stlink/pull/1027), [#1064](https://github.com/stlink-org/stlink/pull/1064), [#1065](https://github.com/stlink-org/stlink/pull/1065)) - [doc] Fixed wrong path for `rules.d` folder ([#1020](https://github.com/stlink-org/stlink/pull/1020)) - Use vl flashloader for all STM32F1 series ([#1041](https://github.com/stlink-org/stlink/pull/1041), [#1044](https://github.com/stlink-org/stlink/pull/1044)) +- st-util v1.6.1 does not recognize option --freq (commit [#e576768](https://github.com/stlink-org/stlink/commit/e5767681f14de9851aa970a9299930ca68b2ed92), [#1055](https://github.com/stlink-org/stlink/pull/1055)) - Fixed `gettimeofday` for MSVC ([#1074](https://github.com/stlink-org/stlink/pull/1074)) - Bugfixes for compilation with clang ([#1076](https://github.com/stlink-org/stlink/pull/1076), [#1078](https://github.com/stlink-org/stlink/pull/1078)) - Fixed compilation with GCC 11 ([#1077](https://github.com/stlink-org/stlink/pull/1077)) - [regression] Flash_loader: increased wait rounds for slow boards ([#1085](https://github.com/stlink-org/stlink/pull/1085)) +- Fixed support for writing option bytes ([#1102](https://github.com/stlink-org/stlink/pull/1102)) +- [doc] Corrected spelling mistake in bug report template ([#1103](https://github.com/stlink-org/stlink/pull/1103)) +- Fixed support for STLINK/V1 programmer ([#1045](https://github.com/stlink-org/stlink/pull/1045), [#1105](https://github.com/stlink-org/stlink/pull/1105)) # v1.6.1 @@ -380,8 +384,10 @@ Updates and fixes: - Stm32l0x flash loader (Robin Kreis) - Use libusb synchronous api ([#194](https://github.com/stlink-org/stlink/pull/194), [#374](https://github.com/stlink-org/stlink/pull/374)) - Fixed segfault when programmer is already busy and `NULL` pointers are in the list ([#256](https://github.com/stlink-org/stlink/pull/256), [#394](https://github.com/stlink-org/stlink/pull/394)) +- Fixed issue where "unknown chip id!" was seen every other time ([#352](https://github.com/stlink-org/stlink/pull/352), [#367](https://github.com/stlink-org/stlink/pull/367), [#381](https://github.com/stlink-org/stlink/pull/381)) - Send F4 memory-map and features for STM32F429 ([#188](https://github.com/stlink-org/stlink/pull/188), [#196](https://github.com/stlink-org/stlink/pull/196), [#250](https://github.com/stlink-org/stlink/pull/250), [#251](https://github.com/stlink-org/stlink/pull/251)) (Release v1.1.0) - Added AHB3 Peripherals definition for STM32F4 ([#218](https://github.com/stlink-org/stlink/pull/218), [#288](https://github.com/stlink-org/stlink/pull/288)) (Release v1.1.0) +- Reset: st-flash does not work when CPU is in sleep mode ([#62](https://github.com/stlink-org/stlink/pull/62)) (Release v1.0.0) - Corrected flash size register address for STM32F2 devices ([#278](https://github.com/stlink-org/stlink/pull/278)) (Release v1.0.0) Chip support added for: diff --git a/README.md b/README.md index 3799f46d2..8a8600947 100644 --- a/README.md +++ b/README.md @@ -1,5 +1,4 @@ -Open source version of the STMicroelectronics STlink Tools -========================================================== +# Open source version of the STMicroelectronics STlink Tools [![BSD licensed](https://img.shields.io/badge/license-BSD-blue.svg)](https://raw.githubusercontent.com/hyperium/hyper/master/LICENSE) [![GitHub release](https://img.shields.io/github/release/stlink-org/stlink.svg)](https://github.com/stlink-org/stlink/releases/latest) @@ -12,42 +11,40 @@ Open source version of the STMicroelectronics STlink Tools Recent new features and bugfixes can be found in the [Changelog](CHANGELOG.md) of this software project. - #### License The stlink library and tools are licensed under the **[BSD-3 License](LICENSE.md)**. - ## Introduction STLink is an open source toolset to program and debug STM32 devices and boards manufactured by STMicroelectronics. It supports several so called STLINK programmer boards (and clones thereof) which use a microcontroller chip to translate commands from USB to JTAG/SWD. There are four generations available on the market which are _all_ supported by this toolset: -* **STLINK/v1** _[obsolete as of 21-11-2019, continued support by this toolset] *)_ +- **STLINK/V1** _[obsolete as of 21-11-2019, continued support by this toolset] \*)_ - transport layer: SCSI passthru commands over USB - stand-alone programmer and present on STM32VL Discovery boards -* **STLINK/v2** +- **STLINK/V2** - transport layer: raw USB commands - stand-alone programmer and present on STM32L Discovery and Nucleo boards -* **STLINK/v2-1** +- **STLINK/V2-1** - transport layer: raw USB commands - present on some STM32 Nucleo boards -* **STLINK/v3** +- **STLINK/V3** - transport layer: raw USB commands - stand-alone programmer -_*)_ **Note: Support on macOS is limited to 10.14 - 10.15. Any later versions are no longer compatible with the STLINK/v1 due to technical reasons.** +_\*)_ **Note: Support for the STLINK/V1 on macOS is limited to 10.14 - 10.15. Due to the deprecation and removal of macOS Kernel Extensions (KEXT) there will be no support for this programmer on macOS 11 or any later version.** On the user level there is no difference in handling or operation between these different revisions. The STlink toolset includes: -* `st-info` - a programmer and chip information tool -* `st-flash` - a flash manipulation tool -* `st-util` - a GDB server (supported in Visual Studio Code / VSCodium via the [Cortex-Debug](https://github.com/Marus/cortex-debug) plugin) -* `stlink-lib` - a communication library -* `stlink-gui` - a GUI-Interface _[optional]_ - +- `st-info` - a programmer and chip information tool +- `st-flash` - a flash manipulation tool +- `st-trace` - a logging tool to record information on execution +- `st-util` - a GDB server (supported in Visual Studio Code / VSCodium via the [Cortex-Debug](https://github.com/Marus/cortex-debug) plugin) +- `stlink-lib` - a communication library +- `stlink-gui` - a GUI-Interface _[optional]_ ## Supported operating systems and hardware combinations @@ -58,12 +55,10 @@ Supported operating systems are listed in [version_support.md](doc/version_suppo The `stlink` toolset continues to maintain backwards compatibility with the **STLINK/v1** programmer.
Please note that on macOS this support is limited to versions 10.13 - 10.15. - ## Tutorial & HOWTO Our [tutorial](doc/tutorial.md) may help you along with some advanced tasks and additional info. - ## Installation **Windows**: @@ -77,8 +72,8 @@ Alternatively one may compile and install from source as described in our [compi We recommend to install from: -* [homebrew](https://formulae.brew.sh/formula/stlink) or -* [MacPorts](https://ports.macports.org/port/stlink) +- [homebrew](https://formulae.brew.sh/formula/stlink) or +- [MacPorts](https://ports.macports.org/port/stlink) Alternatively one can compile and install from source as described in our [compiling manual](doc/compiling.md#macOS). @@ -88,30 +83,28 @@ We recommend to install `stlink-tools` from the package repository of the used d **Note:** As packages distributed via the [Debian](https://packages.debian.org/buster/stlink-tools) and [Ubuntu](https://packages.ubuntu.com/stlink-tools) repositories differ from our self-maintained deb-package, we recommend to use the latter instead (see link below). It provides the opportunity to handle and fix user-reported package issues directly within the project and is not redundant to any limitations deriving from external maintenance guidelines. -* Debian Linux: [(Link)](https://github.com/stlink-org/stlink/releases) -* Ubuntu Linux: [(Link)](https://github.com/stlink-org/stlink/releases) -* Arch Linux: [(Link)](https://www.archlinux.org/packages/community/x86_64/stlink) -* Alpine Linux: [(Link)](https://pkgs.alpinelinux.org/packages?name=stlink) -* Fedora: [(Link)](https://src.fedoraproject.org/rpms/stlink) -* Gentoo Linux: [(Link)](https://packages.gentoo.org/packages/dev-embedded/stlink) +- Debian Linux: [(Link)](https://github.com/stlink-org/stlink/releases) +- Ubuntu Linux: [(Link)](https://github.com/stlink-org/stlink/releases) +- Arch Linux: [(Link)](https://www.archlinux.org/packages/community/x86_64/stlink) +- Alpine Linux: [(Link)](https://pkgs.alpinelinux.org/packages?name=stlink) +- Fedora: [(Link)](https://src.fedoraproject.org/rpms/stlink) +- Gentoo Linux: [(Link)](https://packages.gentoo.org/packages/dev-embedded/stlink) **Other Operating Systems**: -* RedHat/CentOS 8: Users can install from [EPEL repository](https://src.fedoraproject.org/rpms/stlink/branch/epel8) -* FreeBSD: Users can install from [freshports](https://www.freshports.org/devel/stlink) - +- RedHat/CentOS 8: Users can install from [EPEL repository](https://src.fedoraproject.org/rpms/stlink/branch/epel8) +- FreeBSD: Users can install from [freshports](https://www.freshports.org/devel/stlink) ## Installation from source (advanced users) When there is no executable available for your platform or you need the latest (possible unstable) version you need to compile the toolset yourself. This procedure is explained in the [compiling manual](doc/compiling.md). - ## Contributing and versioning -* The semantic versioning scheme is used. Read more at [semver.org](http://semver.org) -* Before creating a pull request, please _ALWAYS_ open a new issue for the discussion of the intended new features. Bugfixes don't require a discussion via a ticket-issue. However they should always be described in a few words as soon as they appear to help others as well. -* Contributors and/or maintainers may submit comments or request changes to patch-proposals and/or pull-requests. -* **ATTENTION: _NEVER EVER_ use the '#' character to count-up single points within a listing as '#' is _exclusively_ reserved for referencing GitHub issues and pull-requests. Otherwise you accidentally introduce false cross references within the project.** -* Please start new forks from the develop branch, as pull requests will go into this branch as well. +- The semantic versioning scheme is used. Read more at [semver.org](http://semver.org) +- Before creating a pull request, please _ALWAYS_ open a new issue for the discussion of the intended new features. Bugfixes don't require a discussion via a ticket-issue. However they should always be described in a few words as soon as they appear to help others as well. +- Contributors and/or maintainers may submit comments or request changes to patch-proposals and/or pull-requests. +- **ATTENTION: _NEVER EVER_ use the '#' character to count-up single points within a listing as '#' is _exclusively_ reserved for referencing GitHub issues and pull-requests. Otherwise you accidentally introduce false cross references within the project.** +- Please start new forks from the develop branch, as pull requests will go into this branch as well. Please also refer to our [Contribution Guidelines](CONTRIBUTING.md). diff --git a/doc/devices_boards.md b/doc/devices_boards.md index 97094b972..6396738c4 100644 --- a/doc/devices_boards.md +++ b/doc/devices_boards.md @@ -1,15 +1,13 @@ -Boards supported by the STlink toolset -====================================== +# Boards supported by the STlink toolset -The following devices are supported by the STlink tools. - -All Boards are expected to work with ST-Link-v2 programmers. +The following devices are supported by the stlink toolset. +All Boards are expected to work with ST-LINK/V2 programmers. **STM32F0 / ARM Cortex M0 / Core-ID: 0x0bb11477 (STM32F0_CORE_ID)** | Chip-ID | Product-Code | -| --- | --- | +| ------- | ------------------- | | 0x440 | STM32F0**30**x**8** | | 0x442 | STM32F0**30**x**C** | | 0x444 | STM32F0**3**xx**4** | @@ -22,19 +20,19 @@ All Boards are expected to work with ST-Link-v2 programmers. | 0x448 | STM32F0**72**xx | | 0x442 | STM32F0**9**xxx | -Tested boards [incl. STLink programmers]: -* Nucleo-F030R8 [v2-1] -* Nucleo-32 [v2-1] -* STM32F0-Discovery [v2] -* STM320518-EVAL -* Nucleo-F072RB [v2-1] -* Nucleo-F091RC [v2-1] +Tested boards [incl. STLINK programmers]: +- Nucleo-F030R8 [v2-1] +- Nucleo-F072RB [v2-1] +- Nucleo-F091RC [v2-1] +- Nucleo-32 [v2-1] +- STM32F0-Discovery [v2] +- STM320518-EVAL **STM32F1 / ARM Cortex M3 / Core-ID: 0x1ba01477 (STM32F1_CORE_ID)** | Product-Code | Product Line | -| --- | --- | +| ----------------- | ----------------------- | | STM32F10**0**yyxx | Value line (V) | | STM32F10**1**yyxx | Access line (A) | | STM32F10**2**yyxx | USB Access line (USB-A) | @@ -42,86 +40,83 @@ Tested boards [incl. STLink programmers]: | STM32F10**5**yyxx | Connectivity line (C) | | STM32F10**7**yyxx | Connectivity line (C) | -| Chip-ID | Product Line | Code (yy) | V | A | USB-A | P | C | -| --- | --- | --- | --- | --- | --- | --- | --- | -| 0x412 | Low-Density | x4 x6 | F100 | F101 | F102 | F103 | | -| 0x410 | Medium Density | x8 xB | | F101 | F102 | F103 | | -| 0x414 | High density | xC xD xE | | F101 | F103 | | | +| Chip-ID | Product Line | Code (yy) | V | A | USB-A | P | C | +| ------- | -------------------- | --------- | ---- | ---- | ----- | ---- | -------------- | +| 0x412 | Low-Density | x4 x6 | F100 | F101 | F102 | F103 | | +| 0x410 | Medium Density | x8 xB | | F101 | F102 | F103 | | +| 0x414 | High density | xC xD xE | | F101 | F103 | | | | 0x418 | STM32F105xx/107xx | x8 xB xC | | | | | F105
F107 | -| 0x420 | Medium density value | x8 xB | F100 | | | | | -| 0x428 | High density Value | xC xD xE | F100 | | | | | -| 0x430 | XL-Density | xF xG | | F101 | | F103 | | +| 0x420 | Medium density value | x8 xB | F100 | | | | | +| 0x428 | High density Value | xC xD xE | F100 | | | | | +| 0x430 | XL-Density | xF xG | | F101 | | F103 | | -Tested boards [incl. STLink programmers]: -* STM32VL-Discovery (STM32F100RBT6) with STLink-v1 [v1], [v2] -* STM32F103-Bluepill: C8Tx & R8xx [v2] -* Nucleo-F103RB [v2-1] -* HY-STM32 (STM32F103VETx) [v1, v2] -* DecaWave EVB1000 (STM32F105RCTx) [v1, v2] +Tested boards [incl. STLINK programmers]: +- STM32VL-Discovery (STM32F100RBT6) with STLINK/V1 [v1], [v2] +- STM32F103-Bluepill: C8Tx & R8xx [v2] +- Nucleo-F103RB [v2-1] +- HY-STM32 (STM32F103VETx) [v1, v2] +- DecaWave EVB1000 (STM32F105RCTx) [v1, v2] **STM32F2 / ARM Cortex M3 / Core-ID: 0x2ba01477 (STM32F2_CORE_ID)** -| Chip-ID | Product-Code | Product Line | -| --- | --- | --- | -| 0x411 | STM32F2yyxx | (all devices) | - +| Chip-ID | Product-Code | Product Line | +| ------- | ------------ | ------------- | +| 0x411 | STM32F2yyxx | (all devices) | **STM32F1 / ARM Cortex M3 / Core-ID: 0x2ba01477 (STM3F1c_CORE_ID)** -| Product-Code | Chip-ID | STLink
Programmer | Boards | -| --- | --- | --- | --- | -| CKS32F103C8Tx | 0x410 | v2 | "STM32"-Bluepill ( _**Fake-Marking !**_ )
STM32F103C8T6 clone from China Key Systems (CKS) | -| CKS32F103C8Tx | 0x410 | v2 | CKS32-Bluepill (Clone)
STM32F103C8T6 clone from China Key Systems (CKS) | - +| Product-Code | Chip-ID | STLink
Programmer | Boards | +| ------------- | ------- | ---------------------- | ----------------------------------------------------------------------------------------------- | +| CKS32F103C8Tx | 0x410 | v2 | "STM32"-Bluepill ( _**Fake-Marking !**_ )
STM32F103C8T6 clone from China Key Systems (CKS) | +| CKS32F103C8Tx | 0x410 | v2 | CKS32-Bluepill (Clone)
STM32F103C8T6 clone from China Key Systems (CKS) | **STM32F3 / ARM Cortex M4F / Core-ID: 0x2ba01477 (STM32F3_CORE_ID)** -| Product-Code | Product Line | -| --- | --- | -| STM32F3**01**yyxx | Access line (A) | -| STM32F3**02**yyxx | USB & CAN line (USB/CAN) | -| STM32F3**03**yyxx | Performance line (P) | -| STM32F3**34**yy | Digital Power line (DP) | -| STM32F3**73**yy | Precision Measurement line (PM) 64k/16k / 128k/24k / 265k/32k | -| STM32F3**18**yy | General Purpose line (GP) 64k/16k | -| STM32F3**28**yy | General Purpose line (GP) 64k/16k | -| STM32F3**58**yy | General Purpose line (GP) 265k/48k | -| STM32F3**78**yy | Precision Measurement line (PM) 265k/32k | -| STM32F3**98**yy | General Purpose line (GP) 512k/80k | - -| Chip-ID | Product Line | Code (yy) | A | USB/CAN | P | others | -| --- | --- | --- | --- | --- | --- | --- | -| 0x422 | _N/A_ | xB xC | | F302 | F303 | | -| 0x422 | _N/A_ | - | | | | F358 | +| Product-Code | Product Line | +| ----------------- | ------------------------------------------------------------- | +| STM32F3**01**yyxx | Access line (A) | +| STM32F3**02**yyxx | USB & CAN line (USB/CAN) | +| STM32F3**03**yyxx | Performance line (P) | +| STM32F3**34**yy | Digital Power line (DP) | +| STM32F3**73**yy | Precision Measurement line (PM) 64k/16k / 128k/24k / 265k/32k | +| STM32F3**18**yy | General Purpose line (GP) 64k/16k | +| STM32F3**28**yy | General Purpose line (GP) 64k/16k | +| STM32F3**58**yy | General Purpose line (GP) 265k/48k | +| STM32F3**78**yy | Precision Measurement line (PM) 265k/32k | +| STM32F3**98**yy | General Purpose line (GP) 512k/80k | + +| Chip-ID | Product Line | Code (yy) | A | USB/CAN | P | others | +| ------- | ------------ | --------- | ---- | ------- | ---- | -------------- | +| 0x422 | _N/A_ | xB xC | | F302 | F303 | | +| 0x422 | _N/A_ | - | | | | F358 | | 0x432 | _N/A_ | - | | | | F373
F378 | -| 0x438 | _N/A_ | x4 x6 x8 | | | F303 | | +| 0x438 | _N/A_ | x4 x6 x8 | | | F303 | | | 0x438 | _N/A_ | - | | | | F334
F328 | -| 0x439 | _N/A_ | x4 x6 x8 | F301 | F302 | | | -| 0x439 | _N/A_ | - | | | | F318 | -| 0x446 | _N/A_ | xD xE | | F302 | F303 | | -| 0x446 | _N/A_ | - | | | | F398 | +| 0x439 | _N/A_ | x4 x6 x8 | F301 | F302 | | | +| 0x439 | _N/A_ | - | | | | F318 | +| 0x446 | _N/A_ | xD xE | | F302 | F303 | | +| 0x446 | _N/A_ | - | | | | F398 | -Tested boards [incl. STLink programmers]: -* Nucleo-F302K8 [v2-1] -* Nucleo-F303K8 [v2-1] -* STM32F3348-Discovery [v2-1] -* Nucleo-F334R8 [v2-1] -* STM32F303-Discovery [v2] -* Nucleo-F303RE [v2-1] +Tested boards [incl. STLINK programmers]: +- Nucleo-F302K8 [v2-1] +- Nucleo-F303K8 [v2-1] +- Nucleo-F303RE [v2-1] +- Nucleo-F334R8 [v2-1] +- STM32F303-Discovery [v2] +- STM32F3348-Discovery [v2-1] **STM32F3 / ARM Cortex M4F / Core-ID: 0x2ba01477 (STM32F3c_CORE_ID)** -| Product-Code | Chip-ID | STLink
Programmer | Boards | -| --- | --- | --- | --- | -| GD32F303VGT6 | 0x430 | _N/A_ | STM32F303 clone from GigaDevice GD)
_unsupported_ | - +| Product-Code | Chip-ID | STLink
Programmer | Boards | +| ------------ | ------- | ---------------------- | ------------------------------------------------------ | +| GD32F303VGT6 | 0x430 | _N/A_ | STM32F303 clone from GigaDevice GD)
_unsupported_ | **STM32F4 / ARM Cortex M4F / Core-ID: 0x2ba01477 (STM32F4_CORE_ID)** | Chip-ID | Product-Code | -| --- | --- | +| ------- | ------------------- | | 0x413 | STM32F4**0**xxx | | 0x413 | STM32F4**1**xxx | | 0x419 | STM32F4**2**xxx | @@ -139,20 +134,20 @@ Tested boards [incl. STLink programmers]: | 0x463 | STM32F4**13**xx | | 0x463 | STM32F4**23**xx | -Tested boards [incl. STLink programmers]: -* STM32F407-Discovery [v2] -* 32F411E-Discovery with gyro, audio [v2] -* 32F429I-Discovery with LCD [v2] -* 32F439VIT6-Discovery [v2] (reseated MCU) -* Nucleo-F401RE [v2-1] -* Nucleo-F411RE [v2-1] -* 32F413H-Discovery [v2-1] +Tested boards [incl. STLINK programmers]: +- Nucleo-F401RE [v2-1] +- Nucleo-F411RE [v2-1] +- STM32F407-Discovery [v2] +- STM32F411E-Discovery with gyro, audio [v2] +- STM32F413H-Discovery [v2-1] +- STM32F429I-Discovery with LCD [v2] +- STM32F439VIT6-Discovery [v2] (reseated MCU) **STM32F7 / ARM Cortex M7F / Core-ID: 0x5ba02477 (STM32F7_CORE_ID)** | Chip-ID | Product-Code | -| --- | --- | +| ------- | --------------- | | 0x452 | STM32F7**2**xxx | | 0x452 | STM32F7**3**xxx | | 0x449 | STM32F7**4**xxx | @@ -160,37 +155,45 @@ Tested boards [incl. STLink programmers]: | 0x451 | STM32F7**6**xxx | | 0x451 | STM32F7**7**xxx | -Tested boards [incl. STLink programmers]: -* STM32F756NGHx evaluation board [v2-1] -* 32F769I-Discovery [v2-1] -* Nucleo-F722ZE [v2-1] -* Nucleo-F746ZG [v2-1] +Tested boards [incl. STLINK programmers]: + +- Nucleo-F722ZE [v2-1] +- Nucleo-F746ZG [v2-1] +- STM32F756NGHx evaluation board [v2-1] +- STM32F769I-Discovery [v2-1] + +**STM32H7 / ARM Cortex M7F / Core-ID: 0x6ba02477 (STM32H7_CORE_ID)** + +| Chip-ID | Product-Code | +| ------- | -------------- | +| 0x450 | STM32H74x/H75x | + +Tested boards [incl. STLINK programmers]: +- Nucleo-H745I-Q [v3] **STM32G0 / ARM Cortex M0+ / Core-ID: 0x0bc11477 (STM32G0_CORE_ID)** | Chip-ID | Product-Code | -| --- | --- | +| ------- | --------------- | | 0x466 | STM32G0**3**xxx | | 0x466 | STM32G0**4**xxx | | 0x460 | STM32G0**7**xxx | | 0x460 | STM32G0**8**xxx | - **STM32G4 / ARM Cortex M4F / Core-ID: 0x2ba01477 (STM32G4_CORE_ID)** | Chip-ID | Product-Code | -| --- | --- | +| ------- | --------------- | | 0x468 | STM32G4**31**xx | | 0x468 | STM32G4**41**xx | | 0x469 | STM32G4**7**xxx | | 0x469 | STM32G4**8**xxx | - **STM32L0 / ARM Cortex M0+ / Core-ID: 0x0bc11477 (STM32L0_CORE_ID)** | Chip-ID | Product-Code | -| --- | --- | +| ------- | --------------- | | 0x457 | STM32L0**1**xxx | | 0x457 | STM32L0**2**xxx | | 0x425 | STM32L0**31**xx | @@ -200,14 +203,14 @@ Tested boards [incl. STLink programmers]: | 0x447 | STM32L0**7**xxx | | 0x447 | STM32L0**8**xxx | -Tested boards [incl. STLink programmers]: -* Nucleo-L053R8 [v2-1] +Tested boards [incl. STLINK programmers]: +- Nucleo-L053R8 [v2-1] **STM32L1 / ARM Cortex M3 / Core-ID: 0x2ba01477 (STM32L1_CORE_ID)** | Chip-ID | Product-Code | -| --- | --- | +| ------- | ---------------- | | 0x416 | STM32L1xxx**6** | | 0x416 | STM32L1xxx**8** | | 0x416 | STM32L1xxx**B** | @@ -218,42 +221,42 @@ Tested boards [incl. STLink programmers]: | 0x436 | STM32L1xxx**D** | | 0x437 | STM32L1xxx**E** | -Tested boards [incl. STLink programmers]: -* Nucleo-L152RE [v2-1] -* 32L152C-Discovery [v2] +Tested boards [incl. STLINK programmers]: +- Nucleo-L152RE [v2-1] +- STM32L152C-Discovery [v2] **STM32L4 / ARM Cortex M4F / Core-ID: 0x2ba01477 (STM32L4_CORE_ID)** -| Chip-ID | Product-Code | -| --- | --- | -| 0x464 | STM32L4**12**xx | -| 0x464 | STM32L4**22**xx | -| 0x435 | STM32L4**3**xxx | -| 0x435 | STM32L4**4**xxx | -| 0x462 | STM32L4**5**xxx | -| 0x462 | STM32L4**6**xxx | -| 0x415 | STM32L4**7**xxx | -| 0x415 | STM32L4**8**xxx | -| 0x461 | STM32L4**96**xx | -| 0x461 | STM32L4**A6**xx | -| 0x470 | STM32L4**R**xx | -| 0x470 | STM32L4**S**xx | -| 0x471 | STM32L4**P5**xx | -| 0x471 | STM32L4**Q5**xx | - -Tested boards [incl. STLink programmers]: -* Nucleo-L432KC [v2-1] -* Nucleo-L452RE [v2-1] -* Nucleo-L476RG [v2-1] -* Nucleo-L496ZG [v2-1] -* 32L4R9I-Discovery [v2-1] - +| Chip-ID | Product-Code | +| ------- | --------------- | +| 0x464 | STM32L4**12**xx | +| 0x464 | STM32L4**22**xx | +| 0x435 | STM32L4**3**xxx | +| 0x435 | STM32L4**4**xxx | +| 0x462 | STM32L4**5**xxx | +| 0x462 | STM32L4**6**xxx | +| 0x415 | STM32L4**7**xxx | +| 0x415 | STM32L4**8**xxx | +| 0x461 | STM32L4**96**xx | +| 0x461 | STM32L4**A6**xx | +| 0x470 | STM32L4**R**xx | +| 0x470 | STM32L4**S**xx | +| 0x471 | STM32L4**P5**xx | +| 0x471 | STM32L4**Q5**xx | + +Tested boards [incl. STLINK programmers]: + +- Nucleo-L432KC [v2-1] +- Nucleo-L452RE [v2-1] +- Nucleo-L476RG [v2-1] +- Nucleo-L496ZG [v2-1] +- STM32L4R9I-Discovery [v2-1] **STM32W / ARM Cortex M3 / Core-ID: 0x2ba01477 (STM32W_CORE_ID)** -| Chip-ID | Product-Code | -| --- | --- | -| 0x495 | STM32WB**50**xx | -| 0x495 | STM32WB**55**xx | -| 0x497 | STM32WLE**5**xx | +| Chip-ID | Product-Code | +| ------- | --------------- | +| 0x495 | STM32WB**50**xx | +| 0x495 | STM32WB**55**xx | +| 0x497 | STM32WLE**5**xx | diff --git a/doc/version_support.md b/doc/version_support.md index afa2d2bd7..eca491b79 100644 --- a/doc/version_support.md +++ b/doc/version_support.md @@ -1,8 +1,7 @@ - _Source:_ pkgs.org - [libusb](https://pkgs.org/search/?q=libusb); [cmake](https://pkgs.org/search/?q=cmake); [gtk](https://pkgs.org/search/?q=gtk) (as of Apr 2020) - ## Supported Operating Systems + ### Microsoft Windows On Windows users should ensure that cmake 3.17.0 is installed.
@@ -10,72 +9,69 @@ Up on compiling c-make will check **automatically**, whether `libusb` 1.0.20 or If this is not the case, the installation routine will download the latest version (1.0.23 at the time of writing).
Thus no user interaction regarding libusb is necessary. -* Windows 10 -* Windows 8.1 - +- Windows 10 +- Windows 8.1 ### Apple macOS -| Package Repository | libusb
version | cmake
version | gtk-3
version | Supported macOS versions | -| --- | --- | --- | --- | --- | -| homebrew | 1.0.23 | 3.17.0 | 3.24.18
gtk+3 | 10.12 (Sierra)- 10.15 (Catalina) | -| MacPorts | 1.0.23 | 3.17.0 | 3.24.18
gtk3 | 10.6 (Snow Leopard) - 10.15 (Catalina) | - -NOTE: In order to use a STLINK/v1 programmer on macOS, versions 10.14 or 10.15 are required. +| Package Repository | libusb
version | cmake
version | gtk-3
version | Supported macOS versions | +| ------------------ | ------------------- | ------------------ | ------------------ | -------------------------------------- | +| homebrew | 1.0.23 | 3.17.0 | 3.24.18
gtk+3 | 10.12 (Sierra)- 10.15 (Catalina) | +| MacPorts | 1.0.23 | 3.17.0 | 3.24.18
gtk3 | 10.6 (Snow Leopard) - 10.15 (Catalina) | +NOTE: In order to use a STLINK/V1 programmer on macOS, versions 10.14 or 10.15 are required. ### Linux-/Unix-based: -| Operating System | libusb
version | cmake
version | gtk-3
version | Notes | -| --- | --- | --- | --- | --- | -| Alpine Edge | 1.0.23 | 3.17.0 | 3.99.0
gtk+3.0 | | -| ALT Linux Sisyphus | 1.0.23 | 3.17.0 | 3.24.18
libgtk+3 | | -| Arch Linux | 1.0.23 | 3.17.0 | 3.24.18
gtk3 | | -| Fedora Rawhide | 1.0.23 | 3.17.0 | 3.24.18
gtk3 | | named `libusbx`, but
`libusb`-codebase is used | -| KaOS | 1.0.23 | 3.17.0 | 3.24.18
gtk3 | | -| OpenMandriva Cooker | 1.0.23 | 3.17.0 | 3.24.18
libgtk+3.0
lib64gtk+3.0 | | -| PCLinuxOS | 1.0.23
lib64usb1.0 | 3.17.0 | 3.24.18
lib64gtk+3.0 | | -| Slackware Current | 1.0.23 | 3.17.0 | 3.24.18
gtk+3 | | -| Solus | 1.0.23 | 3.16.5 | 3.24.16
libgtk-3 | | -| Debian Sid | 1.0.23 | 3.16.3 | 3.24.18
libgtk-3 | | -| OpenMandriva Lx 4.1 | 1.0.23 | 3.16.3 | 3.24.13
libgtk+3.0
lib64gtk+3.0 | | -| Ubuntu 20.04 LTS (Focal Fossa) | 1.0.23 | 3.16.3 | 3.24.17
libgtk-3 | | -| openSUSE Tumbleweed | 1.0.23 | 3.16.2 | 3.24.16
gtk3 | | -| Alpine 3.11 | 1.0.23 | 3.15.5 | 3.24.13
gtk+3.0 | | -| Ubuntu 19.10 (Eoan Ermine) | 1.0.23 | 3.13.4 | 3.24.12
libgtk-3 | | -| Mageia Cauldron | 1.0.22 | 3.17.0 | 3.24.18
libgtk+3.0
lib64gtk+3.0 | | -| NetBSD 9.0 | 1.0.22 | 3.16.1 | 3.24.12
gtk+3 | | -| NetBSD 8.1 | 1.0.22 | 3.16.1 | 3.24.12
gtk+3 | | -| NetBSD 7.2 | 1.0.22 | 3.16.1 | _N/A_ | | -| Alpine 3.10 | 1.0.22 | 3.14.5 | 3.24.8
gtk+3.0 | | -| Fedora 31 | 1.0.22 | 3.14.5 | 3.24.12
gtk3 | named `libusbx`, but
`libusb`-codebase is used | -| Mageia 7.1 | 1.0.22 | 3.14.3 | 3.24.8
libgtk+3.0
lib64gtk+3.0 | | -| Fedora 30 | 1.0.22 | 3.14.2 | 3.24.8
gtk3 | named `libusbx`, but
`libusb`-codebase is used | -| Debian 10 (Buster) | 1.0.22 | 3.13.4 | 3.24.5
libgtk-3 | | -| Alpine 3.9 | 1.0.22 | 3.13.0 | 3.24.1
gtk+3.0 | | -| CentOS 8 | 1.0.22 | 3.11.4 | 3.22.30
gtk3 | named `libusbx`, but
`libusb`-codebase is used | -| openSUSE Leap 15.2 | 1.0.21 | 3.15.5 | 3.24.14
gtk3 | | -| openSUSE Leap 15.1 | 1.0.21 | 3.10.2 | 3.22.30
gtk3 | | -| Ubuntu 18.04 LTS (Bionic Beaver) | 1.0.21 | 3.10.2 | 3.22.30
libgtk-3 | | -| Debian 9 (Stretch) | 1.0.21 | 3.7.2 | 3.22.11
libgtk-3 | | -| Slackware 14.2 | **1.0.20** | 3.5.2 | 3.18.9
gtk+3 | | -| Ubuntu 16.04 LTS (Xenial Xerus) | **1.0.20** | 3.5.1 | 3.18.9
libgtk-3 | | -| OpenMandriva Lx 3.0 | **1.0.20** | **3.4.2** | 3.18.9
libgtk+3.0
lib64gtk+3.0 | | -| FreeBSD 13 | **1.0.16** - 1.0.18 | 3.15.5 | 3.24.10
gtk3 | linux_libusb-13.0r358841
(integrated) | -| FreeBSD 12 | **1.0.16** - 1.0.18 | 3.15.5 | 3.24.10
gtk3 | linux_libusb-11.0r261448_4
(integrated) | -| FreeBSD 11 | **1.0.16** - 1.0.18 | 3.15.5 | 3.24.10
gtk3 | linux_libusb-11.0r261448_4
(integrated) | - +| Operating System | libusb
version | cmake
version | gtk-3
version | Notes | +| -------------------------------- | ----------------------- | ------------------ | ----------------------------------------- | --------------------------------------------------- | --------------------------------------------------- | +| Alpine Edge | 1.0.23 | 3.17.0 | 3.99.0
gtk+3.0 | | +| ALT Linux Sisyphus | 1.0.23 | 3.17.0 | 3.24.18
libgtk+3 | | +| Arch Linux | 1.0.23 | 3.17.0 | 3.24.18
gtk3 | | +| Fedora Rawhide | 1.0.23 | 3.17.0 | 3.24.18
gtk3 | | named `libusbx`, but
`libusb`-codebase is used | +| KaOS | 1.0.23 | 3.17.0 | 3.24.18
gtk3 | | +| OpenMandriva Cooker | 1.0.23 | 3.17.0 | 3.24.18
libgtk+3.0
lib64gtk+3.0 | | +| PCLinuxOS | 1.0.23
lib64usb1.0 | 3.17.0 | 3.24.18
lib64gtk+3.0 | | +| Slackware Current | 1.0.23 | 3.17.0 | 3.24.18
gtk+3 | | +| Solus | 1.0.23 | 3.16.5 | 3.24.16
libgtk-3 | | +| Debian Sid | 1.0.23 | 3.16.3 | 3.24.18
libgtk-3 | | +| OpenMandriva Lx 4.1 | 1.0.23 | 3.16.3 | 3.24.13
libgtk+3.0
lib64gtk+3.0 | | +| Ubuntu 20.04 LTS (Focal Fossa) | 1.0.23 | 3.16.3 | 3.24.17
libgtk-3 | | +| openSUSE Tumbleweed | 1.0.23 | 3.16.2 | 3.24.16
gtk3 | | +| Alpine 3.11 | 1.0.23 | 3.15.5 | 3.24.13
gtk+3.0 | | +| Ubuntu 19.10 (Eoan Ermine) | 1.0.23 | 3.13.4 | 3.24.12
libgtk-3 | | +| Mageia Cauldron | 1.0.22 | 3.17.0 | 3.24.18
libgtk+3.0
lib64gtk+3.0 | | +| NetBSD 9.0 | 1.0.22 | 3.16.1 | 3.24.12
gtk+3 | | +| NetBSD 8.1 | 1.0.22 | 3.16.1 | 3.24.12
gtk+3 | | +| NetBSD 7.2 | 1.0.22 | 3.16.1 | _N/A_ | | +| Alpine 3.10 | 1.0.22 | 3.14.5 | 3.24.8
gtk+3.0 | | +| Fedora 31 | 1.0.22 | 3.14.5 | 3.24.12
gtk3 | named `libusbx`, but
`libusb`-codebase is used | +| Mageia 7.1 | 1.0.22 | 3.14.3 | 3.24.8
libgtk+3.0
lib64gtk+3.0 | | +| Fedora 30 | 1.0.22 | 3.14.2 | 3.24.8
gtk3 | named `libusbx`, but
`libusb`-codebase is used | +| Debian 10 (Buster) | 1.0.22 | 3.13.4 | 3.24.5
libgtk-3 | | +| Alpine 3.9 | 1.0.22 | 3.13.0 | 3.24.1
gtk+3.0 | | +| CentOS 8 | 1.0.22 | 3.11.4 | 3.22.30
gtk3 | named `libusbx`, but
`libusb`-codebase is used | +| openSUSE Leap 15.2 | 1.0.21 | 3.15.5 | 3.24.14
gtk3 | | +| openSUSE Leap 15.1 | 1.0.21 | 3.10.2 | 3.22.30
gtk3 | | +| Ubuntu 18.04 LTS (Bionic Beaver) | 1.0.21 | 3.10.2 | 3.22.30
libgtk-3 | | +| Debian 9 (Stretch) | 1.0.21 | 3.7.2 | 3.22.11
libgtk-3 | | +| Slackware 14.2 | **1.0.20** | 3.5.2 | 3.18.9
gtk+3 | | +| Ubuntu 16.04 LTS (Xenial Xerus) | **1.0.20** | 3.5.1 | 3.18.9
libgtk-3 | | +| OpenMandriva Lx 3.0 | **1.0.20** | **3.4.2** | 3.18.9
libgtk+3.0
lib64gtk+3.0 | | +| FreeBSD 13 | **1.0.16** - 1.0.18 | 3.15.5 | 3.24.10
gtk3 | linux_libusb-13.0r358841
(integrated) | +| FreeBSD 12 | **1.0.16** - 1.0.18 | 3.15.5 | 3.24.10
gtk3 | linux_libusb-11.0r261448_4
(integrated) | +| FreeBSD 11 | **1.0.16** - 1.0.18 | 3.15.5 | 3.24.10
gtk3 | linux_libusb-11.0r261448_4
(integrated) | ## Unsupported Operating Systems (as of Release v1.6.1) -| Operating System | libusb
version | cmake
version | End of
OS-Support | Notes | -| --- | --- | --- | --- | --- | -| CentOS 7 | 1.0.21 | **2.8.12.2** | | named `libusbx`, but
`libusb`-codebase is used | -| Debian 8 (Jessie) | 1.0.**19** | 3.**0.2** | Jun 2020 | -| Ubuntu 14.04 LTS (Trusty Tahr) | 1.0.**17** | **2.8.12.2** | Apr 2019 | -| CentOS 6 | 1.0.**9** | **2.8.12.2** | Dec 2020 | named `libusbx`, but
`libusb`-codebase is used | -| Slackware 14.1 | 1.0.**9** | **2.8.12** | | -| Slackware 14.0 | 1.0.**9** | **2.8.8** | | +| Operating System | libusb
version | cmake
version | End of
OS-Support | Notes | +| ------------------------------ | ------------------- | ------------------ | ---------------------- | --------------------------------------------------- | +| CentOS 7 | 1.0.21 | **2.8.12.2** | | named `libusbx`, but
`libusb`-codebase is used | +| Debian 8 (Jessie) | 1.0.**19** | 3.**0.2** | Jun 2020 | +| Ubuntu 14.04 LTS (Trusty Tahr) | 1.0.**17** | **2.8.12.2** | Apr 2019 | +| CentOS 6 | 1.0.**9** | **2.8.12.2** | Dec 2020 | named `libusbx`, but
`libusb`-codebase is used | +| Slackware 14.1 | 1.0.**9** | **2.8.12** | | +| Slackware 14.0 | 1.0.**9** | **2.8.8** | | _All other operating systems which are not listed are unsupported._ From dcdbd61fda443c34d416d44237799a1c6e08d018 Mon Sep 17 00:00:00 2001 From: Michael Nolan Date: Wed, 17 Mar 2021 20:02:41 -0400 Subject: [PATCH 184/503] Consolidate core id read code --- src/common.c | 44 ++++++++++++-------------------------------- 1 file changed, 12 insertions(+), 32 deletions(-) diff --git a/src/common.c b/src/common.c index a064254d3..5f2746e3d 100644 --- a/src/common.c +++ b/src/common.c @@ -1221,43 +1221,23 @@ int stlink_core_id(stlink_t *sl) { int stlink_chip_id(stlink_t *sl, uint32_t *chip_id) { int ret; - if (sl->core_id == STM32H7_CORE_ID) { - /* STM32H7 chipid in 0x5c001000 (RM0433 pg3189) - * However, the STM32H7 is not the only chip with a JTAG - * IDCODE of 0x6ba02477, so we cannot rely solely on this info - * to select the address to read the chip id */ - - uint32_t cpu_id; - *chip_id = 0; - ret = -1; - - // Read the CPU ID as well to determine if this really is an H7 part - if (stlink_read_debug32(sl, STLINK_REG_CM3_CPUID, &cpu_id)) - cpu_id = 0; - - // If it is, read the chipid from the new address - if (sl->core_id == STM32H7_CORE_ID && cpu_id == STLINK_REG_CMx_CPUID_CM7) { - // STM32H7 chipid in 0x5c001000 (RM0433 pg3189) - ret = stlink_read_debug32(sl, 0x5c001000, chip_id); - } - - if (*chip_id == 0) { - // default chipid address - ret = stlink_read_debug32(sl, 0xE0042000, chip_id); - } + uint32_t cpu_id; + *chip_id = 0; + ret = -1; - } else { - // default chipid address - ret = stlink_read_debug32(sl, 0xE0042000, chip_id); - } + // Read the CPU ID to determine where to read the core id from + if (stlink_read_debug32(sl, STLINK_REG_CM3_CPUID, &cpu_id)) + cpu_id = 0; - if (ret == -1) { - return(ret); + // If the chip is an H7, read the chipid from the new address + if (sl->core_id == STM32H7_CORE_ID && cpu_id == STLINK_REG_CMx_CPUID_CM7) { + // STM32H7 chipid in 0x5c001000 (RM0433 pg3189) + ret = stlink_read_debug32(sl, 0x5c001000, chip_id); } if (*chip_id == 0) { - // STM32H7 chipid in 0x5c001000 (RM0433 pg3189) - ret = stlink_read_debug32(sl, 0x5c001000, chip_id); + // default chipid address + ret = stlink_read_debug32(sl, 0xE0042000, chip_id); } if (*chip_id == 0) { From 9ed3d46c24c2a78d1e49474ec7529e7cd4c46d3b Mon Sep 17 00:00:00 2001 From: Tarek BOCHKATI Date: Tue, 16 Mar 2021 21:04:31 +0100 Subject: [PATCH 185/503] fix for stlink old DFU serial number omit the hla serial aka 'openocd serial' Only one valid serial is used which matches the serial as displayed in STM32CubeProgrammer and official ST tools. Signed-off-by: Tarek BOCHKATI --- doc/man/st-info.1 | 3 --- doc/man/st-info.md | 8 ++---- inc/stlink.h | 6 ++--- src/st-flash/flash.h | 2 +- src/st-flash/flash_opts.c | 12 +-------- src/st-info/info.c | 28 ++------------------- src/st-trace/trace.c | 19 +------------- src/st-util/gdb-server.c | 17 ++----------- src/stlink-lib/usb.c | 52 +++++++++++++++++++++++++++++++++------ src/stlink-lib/usb.h | 2 +- 10 files changed, 57 insertions(+), 92 deletions(-) diff --git a/doc/man/st-info.1 b/doc/man/st-info.1 index a0380f851..776ec7a3f 100644 --- a/doc/man/st-info.1 +++ b/doc/man/st-info.1 @@ -37,9 +37,6 @@ Display the chip ID of the device .B \-\-serial Display the serial code of the device .TP -.B \-\-hla\-serial -Display the hex escaped serial code of the device -.TP .B \-\-probe Display the summarized information of the connected programmers and devices diff --git a/doc/man/st-info.md b/doc/man/st-info.md index 9164642f2..91f9ea0b0 100644 --- a/doc/man/st-info.md +++ b/doc/man/st-info.md @@ -13,7 +13,7 @@ st-info - Provides information about connected STLink and STM32 devices # DESCRIPTION Provides information about connected STLink programmers and STM32 devices: -Serial code, OpenOCD hla-serial, flash, page size, sram, chipid, description. +Serial code, flash, page size, sram, chipid, description. The STLink device to probe can be specified via the environment variable STLINK_DEVICE on the format :. @@ -29,9 +29,6 @@ STLINK_DEVICE on the format :. \--serial : Display the serial code of the device -\--hla-serial -: Display the hex escaped serial code of the device - \--flash : Display amount of flash memory available in the device @@ -53,8 +50,7 @@ Display information about connected programmers and devices $ st-info --probe Found 1 stlink programmers - serial: 303033413030323233343338353130323334333133393339 - hla-serial: "\x30\x30\x33\x41\x30\x30\x32\x32\x33\x34\x33\x38\x35\x31\x30\x32\x33\x34\x33\x31\x33\x39\x33\x39" + serial: 57FF72067265575742132067 flash: 131072 (pagesize: 128) sram: 20480 chipid: 0x0447 diff --git a/inc/stlink.h b/inc/stlink.h index 9b5e56594..7bb1bc51e 100644 --- a/inc/stlink.h +++ b/inc/stlink.h @@ -79,7 +79,8 @@ enum target_state { #define STLINK_SWDCLK_15KHZ_DIVISOR 265 #define STLINK_SWDCLK_5KHZ_DIVISOR 798 -#define STLINK_SERIAL_MAX_SIZE 64 +#define STLINK_SERIAL_LENGTH 24 +#define STLINK_SERIAL_BUFFER_SIZE (STLINK_SERIAL_LENGTH + 1) #define STLINK_V3_MAX_FREQ_NB 10 @@ -191,8 +192,7 @@ struct _stlink { uint32_t chip_id; // set by stlink_load_device_params(), used to identify flash and sram enum target_state core_stat; // set by stlink_status() - char serial[STLINK_SERIAL_MAX_SIZE]; - int serial_size; + char serial[STLINK_SERIAL_BUFFER_SIZE]; int freq; // set by stlink_open_usb(), values: STLINK_SWDCLK_xxx_DIVISOR enum stlink_flash_type flash_type; diff --git a/src/st-flash/flash.h b/src/st-flash/flash.h index ca0ca2839..8a5c2ad29 100644 --- a/src/st-flash/flash.h +++ b/src/st-flash/flash.h @@ -14,7 +14,7 @@ enum flash_format {FLASH_FORMAT_BINARY = 0, FLASH_FORMAT_IHEX = 1}; enum flash_area {FLASH_MAIN_MEMORY = 0, FLASH_SYSTEM_MEMORY = 1, FLASH_OTP = 2, FLASH_OPTION_BYTES = 3, FLASH_OPTION_BYTES_BOOT_ADD = 4, FLASH_OPTCR = 5, FLASH_OPTCR1 = 6}; struct flash_opts { enum flash_cmd cmd; - uint8_t serial[STLINK_SERIAL_MAX_SIZE]; + uint8_t serial[STLINK_SERIAL_BUFFER_SIZE]; const char* filename; stm32_addr_t addr; size_t size; diff --git a/src/st-flash/flash_opts.c b/src/st-flash/flash_opts.c index 2ee19bd48..7d846e425 100644 --- a/src/st-flash/flash_opts.c +++ b/src/st-flash/flash_opts.c @@ -106,18 +106,8 @@ int flash_get_opts(struct flash_opts* o, int ac, char** av) { serial = av[0] + strlen("--serial="); } - /** @todo This is not really portable, as strlen really returns size_t we need to obey - and not cast it to a signed type. */ - int j = (int)strlen(serial); - int length = j / 2; // the length of the destination-array + memcpy(o->serial, serial, STLINK_SERIAL_BUFFER_SIZE); - if (j % 2 != 0) { return(-1); } - - for (size_t k = 0; j >= 0 && k < sizeof(o->serial); ++k, j -= 2) { - char buffer[3] = {0}; - memcpy(buffer, serial + j, 2); - o->serial[length - k] = (uint8_t)strtol(buffer, NULL, 16); - } } else if (strcmp(av[0], "--area") == 0 || starts_with(av[0], "--area=")) { const char * area; diff --git a/src/st-info/info.c b/src/st-info/info.c index 0fc4d4d8a..c1ac86373 100644 --- a/src/st-info/info.c +++ b/src/st-info/info.c @@ -9,7 +9,6 @@ static void usage(void) { puts("st-info --version"); puts("st-info --probe"); puts("st-info --serial"); - puts("st-info --hla-serial"); puts("st-info --flash [--connect-under-reset]"); puts("st-info --pagesize [--connect-under-reset]"); puts("st-info --sram [--connect-under-reset]"); @@ -17,24 +16,6 @@ static void usage(void) { puts("st-info --descr [--connect-under-reset]"); } -/* Print normal or OpenOCD hla_serial with newline */ -static void stlink_print_serial(stlink_t *sl, bool openocd) { - const char *fmt; - - if (openocd) { - printf("\""); - fmt = "\\x%02x"; - } else { - fmt = "%02x"; - } - - for (int n = 0; n < sl->serial_size; n++) { printf(fmt, sl->serial[n]); } - - if (openocd) { printf("\""); } - - printf("\n"); -} - static void stlink_print_version(stlink_t *sl) { // Implementation of version printing is minimalistic // but contains all available information from sl->version @@ -53,10 +34,7 @@ static void stlink_print_info(stlink_t *sl) { printf(" version: "); stlink_print_version(sl); - printf(" serial: "); - stlink_print_serial(sl, false); - printf(" hla-serial: "); - stlink_print_serial(sl, true); + printf(" serial: %s\n", sl->serial); printf(" flash: %u (pagesize: %u)\n", (uint32_t)sl->flash_size, (uint32_t)sl->flash_pgsz); printf(" sram: %u\n", (uint32_t)sl->sram_size); @@ -131,9 +109,7 @@ static int print_data(int ac, char **av) { if (stlink_current_mode(sl) != STLINK_DEV_DEBUG_MODE) { stlink_enter_swd_mode(sl); } if (strcmp(av[1], "--serial") == 0) { - stlink_print_serial(sl, false); - } else if (strcmp(av[1], "--hla-serial") == 0) { - stlink_print_serial(sl, true); + printf("%s\n", sl->serial); } else if (strcmp(av[1], "--flash") == 0) { printf("0x%x\n", (uint32_t)sl->flash_size); } else if (strcmp(av[1], "--pagesize") == 0) { diff --git a/src/st-trace/trace.c b/src/st-trace/trace.c index 71ba6b360..3180335a0 100644 --- a/src/st-trace/trace.c +++ b/src/st-trace/trace.c @@ -191,25 +191,8 @@ bool parse_options(int argc, char** argv, st_settings_t *settings) { return true; } -static void convert_serial_number_text_to_binary(const char* text, char binary_out[STLINK_SERIAL_MAX_SIZE]) { - size_t length = 0; - for (uint32_t n = 0; n < strlen(text) && length < STLINK_SERIAL_MAX_SIZE; n += 2) { - char buffer[3] = { 0 }; - memcpy(buffer, text + n, 2); - binary_out[length++] = (uint8_t)strtol(buffer, NULL, 16); - } -} - static stlink_t* stlink_connect(const st_settings_t* settings) { - if (settings->serial_number) { - // Open this specific stlink. - char binary_serial_number[STLINK_SERIAL_MAX_SIZE] = { 0 }; - convert_serial_number_text_to_binary(settings->serial_number, binary_serial_number); - return stlink_open_usb(settings->logging_level, false, binary_serial_number, 0); - } else { - // Otherwise, open any stlink. - return stlink_open_usb(settings->logging_level, false, NULL, 0); - } + return stlink_open_usb(settings->logging_level, false, settings->serial_number, 0); } static bool enable_trace(stlink_t* stlink, const st_settings_t* settings, uint32_t trace_frequency) { diff --git a/src/st-util/gdb-server.c b/src/st-util/gdb-server.c index 4177cef11..0f30c688a 100644 --- a/src/st-util/gdb-server.c +++ b/src/st-util/gdb-server.c @@ -43,7 +43,7 @@ static stlink_t *connected_stlink = NULL; static bool semihosting = false; static bool serial_specified = false; -static char serialnumber[STLINK_SERIAL_MAX_SIZE] = {0}; +static char serialnumber[STLINK_SERIAL_BUFFER_SIZE] = {0}; #if defined(_WIN32) #define close_socket win32_close_socket @@ -192,20 +192,7 @@ int parse_options(int argc, char** argv, st_state_t *st) { break; case SERIAL_OPTION: printf("use serial %s\n", optarg); - /* TODO: This is not really portable, as strlen really returns size_t, - * we need to obey and not cast it to a signed type. - */ - int j = (int)strlen(optarg); - int length = j / 2; // the length of the destination-array - - if (j % 2 != 0) { return(-1); } - - for (size_t k = 0; j >= 0 && k < sizeof(serialnumber); ++k, j -= 2) { - char buffer[3] = {0}; - memcpy(buffer, optarg + j, 2); - serialnumber[length - k] = (uint8_t)strtol(buffer, NULL, 16); - } - + memcpy(serialnumber, optarg, STLINK_SERIAL_BUFFER_SIZE); serial_specified = true; break; } diff --git a/src/stlink-lib/usb.c b/src/stlink-lib/usb.c index d2b17fad6..569815665 100644 --- a/src/stlink-lib/usb.c +++ b/src/stlink-lib/usb.c @@ -1159,7 +1159,44 @@ static stlink_backend_t _stlink_usb_backend = { _stlink_usb_read_trace }; -stlink_t *stlink_open_usb(enum ugly_loglevel verbose, int reset, char serial[STLINK_SERIAL_MAX_SIZE], int freq) { +/* return the length of serial or (0) in case of errors */ +size_t stlink_serial(struct libusb_device_handle *handle, struct libusb_device_descriptor *desc, char *serial) { + unsigned char desc_serial[(STLINK_SERIAL_LENGTH) * 2]; + + /* truncate the string in the serial buffer */ + serial[0] = '\0'; + + /* get the LANGID from String Descriptor Zero */ + int ret = libusb_get_string_descriptor(handle, 0, 0, desc_serial, sizeof(desc_serial)); + if (ret < 4) return 0; + + uint32_t langid = desc_serial[2] | (desc_serial[3] << 8); + + /* get the serial */ + ret = libusb_get_string_descriptor(handle, desc->iSerialNumber, langid, desc_serial, + sizeof(desc_serial)); + if (ret < 0) return 0; // could not read serial + + unsigned char len = desc_serial[0]; + + if (len == ((STLINK_SERIAL_LENGTH + 1) * 2)) { /* len == 50 */ + /* good ST-Link adapter */ + ret = libusb_get_string_descriptor_ascii( + handle, desc->iSerialNumber, (unsigned char *)serial, STLINK_SERIAL_BUFFER_SIZE); + if (ret < 0) return 0; + } else if (len == ((STLINK_SERIAL_LENGTH / 2 + 1) * 2)) { /* len == 26 */ + /* fix-up the buggy serial */ + for (unsigned int i = 0; i < STLINK_SERIAL_LENGTH; i += 2) + sprintf(serial + i, "%02X", desc_serial[i + 2]); + serial[STLINK_SERIAL_LENGTH] = '\0'; + } else { + return 0; + } + + return strlen(serial); +} + +stlink_t *stlink_open_usb(enum ugly_loglevel verbose, int reset, char serial[STLINK_SERIAL_BUFFER_SIZE], int freq) { stlink_t* sl = NULL; struct stlink_libusb* slu = NULL; int ret = -1; @@ -1236,15 +1273,14 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, int reset, char serial[STL if (ret) { continue; } // could not open device - sl->serial_size = libusb_get_string_descriptor_ascii( - handle, desc.iSerialNumber, (unsigned char *)sl->serial, sizeof(sl->serial)); + size_t serial_len = stlink_serial(handle, &desc, sl->serial); libusb_close(handle); - if (sl->serial_size < 0) { continue; } // could not read serial + if (serial_len != STLINK_SERIAL_LENGTH) { continue; } // could not read the serial // if no serial provided, or if serial match device, fixup version and protocol - if (((serial == NULL) || (*serial == 0)) || (memcmp(serial, &sl->serial, sl->serial_size) == 0)) { + if (((serial == NULL) || (*serial == 0)) || (memcmp(serial, &sl->serial, STLINK_SERIAL_LENGTH) == 0)) { if (STLINK_V1_USB_PID(desc.idProduct)) { slu->protocoll = 1; sl->version.stlink_v = 1; @@ -1433,7 +1469,7 @@ static size_t stlink_probe_usb_devs(libusb_device **devs, stlink_t **sldevs[]) { if (!STLINK_SUPPORTED_USB_PID(desc.idProduct)) { continue; } struct libusb_device_handle* handle; - char serial[STLINK_SERIAL_MAX_SIZE] = {0, }; + char serial[STLINK_SERIAL_BUFFER_SIZE] = {0, }; ret = libusb_open(dev, &handle); @@ -1447,11 +1483,11 @@ static size_t stlink_probe_usb_devs(libusb_device **devs, stlink_t **sldevs[]) { break; } - ret = libusb_get_string_descriptor_ascii(handle, desc.iSerialNumber, (unsigned char *)&serial, sizeof(serial)); + size_t serial_len = stlink_serial(handle, &desc, serial); libusb_close(handle); - if (ret < 0) { continue; } + if (serial_len != STLINK_SERIAL_LENGTH) { continue; } stlink_t *sl = stlink_open_usb(0, 1, serial, 0); diff --git a/src/stlink-lib/usb.h b/src/stlink-lib/usb.h index 717a82f6d..512370a10 100644 --- a/src/stlink-lib/usb.h +++ b/src/stlink-lib/usb.h @@ -67,7 +67,7 @@ struct stlink_libusb { * @retval NULL Error while opening the stlink * @retval !NULL Stlink found and ready to use */ -stlink_t *stlink_open_usb(enum ugly_loglevel verbose, int reset, char serial[STLINK_SERIAL_MAX_SIZE], int freq); +stlink_t *stlink_open_usb(enum ugly_loglevel verbose, int reset, char serial[STLINK_SERIAL_BUFFER_SIZE], int freq); size_t stlink_probe_usb(stlink_t **stdevs[]); void stlink_probe_usb_free(stlink_t **stdevs[], size_t size); From d9726fa86da888f54e463b21f624ee27e208e3a0 Mon Sep 17 00:00:00 2001 From: Ant-ON Date: Wed, 17 Mar 2021 12:38:38 +0500 Subject: [PATCH 186/503] Updated a target resetting documentation --- doc/man/st-flash.1 | 2 +- doc/man/st-flash.md | 2 +- doc/tutorial.md | 19 ++++++++++--------- src/st-flash/flash.c | 4 ++-- 4 files changed, 14 insertions(+), 13 deletions(-) diff --git a/doc/man/st-flash.1 b/doc/man/st-flash.1 index c2654f280..086046d2c 100644 --- a/doc/man/st-flash.1 +++ b/doc/man/st-flash.1 @@ -41,7 +41,7 @@ Print version information TODO .TP --reset -TODO +Trigger a reset both before and after flashing .TP --opt Enable ignore ending empty bytes optimization diff --git a/doc/man/st-flash.md b/doc/man/st-flash.md index d5565e923..80130c8f1 100644 --- a/doc/man/st-flash.md +++ b/doc/man/st-flash.md @@ -46,7 +46,7 @@ reset : TODO \--reset -: TODO +: Trigger a reset both before and after flashing \--opt : Enable ignore ending empty bytes optimization diff --git a/doc/tutorial.md b/doc/tutorial.md index 3a0f16fd9..d4cf89ce2 100644 --- a/doc/tutorial.md +++ b/doc/tutorial.md @@ -2,14 +2,15 @@ ## Available tools and options -| Option | Tool | Description | Available
since | -| --------------- | ------------------------------------ | ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | -------------------- | -| --flash=n[k][m] | st-flash | One can specify `--flash=128k` for example, to override the default value of 64k
for the STM32F103C8T6 to assume 128k of flash being present. This option accepts
decimal (128k), octal 0200k, or hex 0x80k values. Leaving the multiplier out is
equally valid, e.g.: `--flash=0x20000`. The size may be followed by an optional "k"
or "m" to multiply the given value by 1k (1024) or 1M respectively. | v1.4.0 | -| --freq=n[k][m] | st-flash | The frequency of the SWD/JTAG interface can be specified, to override the default
1800 kHz configuration. This option solely accepts decimal values (5K or 1.8M) with
the unit `Hz` being left out. Valid frequencies are: `5K, 15K, 25K, 50K, 100K,`
`125K, 240K, 480K, 950K, 1200K(1.2M), 1800K(1.8M), 4000K(4M)`. | v1.6.1 | -| --opt | st-flash | Optimisation can be enabled in order to skip flashing empty (0x00 or 0xff) bytes at
the end of binary file. This may cause some garbage data left after a flash operation.
This option was enabled by default in earlier releases. | v1.6.1 | -| --reset | st-flash | Trigger a reset both before and after flashing. | v1.0.0 | -| --version | st-info,
st-flash,
st-util | Print version information. | | -| --help | st-flash,
st-util | Print list of available commands. _(To be added to this table.)_ | | +| Option | Tool | Description | Available
since | +| --------------------- | ------------------------------------ | ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | -------------------- | +| --flash=n[k][m] | st-flash | One can specify `--flash=128k` for example, to override the default value of 64k
for the STM32F103C8T6 to assume 128k of flash being present. This option accepts
decimal (128k), octal 0200k, or hex 0x80k values. Leaving the multiplier out is
equally valid, e.g.: `--flash=0x20000`. The size may be followed by an optional "k"
or "m" to multiply the given value by 1k (1024) or 1M respectively. | v1.4.0 | +| --freq=n[k][m] | st-flash | The frequency of the SWD/JTAG interface can be specified, to override the default
1800 kHz configuration. This option solely accepts decimal values (5K or 1.8M) with
the unit `Hz` being left out. Valid frequencies are: `5K, 15K, 25K, 50K, 100K,`
`125K, 240K, 480K, 950K, 1200K(1.2M), 1800K(1.8M), 4000K(4M)`. | v1.6.1 | +| --opt | st-flash | Optimisation can be enabled in order to skip flashing empty (0x00 or 0xff) bytes at
the end of binary file. This may cause some garbage data left after a flash operation.
This option was enabled by default in earlier releases. | v1.6.1 | +| --reset | st-flash | Trigger a reset both before and after flashing. The default use the hardware reset
through `NRST` pin. The software system reset is used if the hardware reset failed
(`NRST` pin not connected). | v1.0.0 | +| --connect-under-reset | st-flash | Connect under reset. Option makes it possible to connect to the device before code
executing. This is useful when the target contains a code that go device to sleep,
disables of debug pins or other special code. | v1.6.1 | +| --version | st-info
st-flash
st-util | Print version information. | | +| --help | st-flash
st-util | Print list of available commands. _(To be added to this table.)_ | | ### st-flash: Checksum for binary files @@ -272,7 +273,7 @@ In order to continue, one can use 'monitor reset' to reset the MCU. Remember that you can shorten the commands. `tar ext :4242` is good enough for GDB. -If you need to send a hard reset signal through `NRST` pin, you can use the following command: +If you need to send a reset signal, you can use the following command: ``` (gdb) monitor jtag_reset diff --git a/src/st-flash/flash.c b/src/st-flash/flash.c index d8bd8772c..447daa158 100644 --- a/src/st-flash/flash.c +++ b/src/st-flash/flash.c @@ -26,8 +26,8 @@ static void cleanup(int signum) { } static void usage(void) { - puts("command line: ./st-flash [--debug] [--reset] [--opt] [--serial ] [--format ] [--flash=] [--freq=] [--area=] {read|write} [path] [addr] [size]"); - puts("command line: ./st-flash [--debug] [--freq=] [--serial ] erase"); + puts("command line: ./st-flash [--debug] [--reset] [--connect-under-reset] [--opt] [--serial ] [--format ] [--flash=] [--freq=] [--area=] {read|write} [path] [addr] [size]"); + puts("command line: ./st-flash [--debug] [--connect-under-reset] [--freq=] [--serial ] erase"); puts("command line: ./st-flash [--debug] [--freq=] [--serial ] reset"); puts(" , and : Use hex format."); puts(" : Use decimal, octal or hex (prefix 0xXXX) format, optionally followed by k=KB, or m=MB (eg. --flash=128k)"); From ebcf04f02bcb47f0d34d0b0a4992007ee19bfe5c Mon Sep 17 00:00:00 2001 From: anton Date: Wed, 17 Mar 2021 20:32:20 +0500 Subject: [PATCH 187/503] flash_loader: used timeout in ms --- src/stlink-lib/flash_loader.c | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/src/stlink-lib/flash_loader.c b/src/stlink-lib/flash_loader.c index b55953406..1224215e5 100644 --- a/src/stlink-lib/flash_loader.c +++ b/src/stlink-lib/flash_loader.c @@ -3,6 +3,7 @@ #include #include +#include #include "flash_loader.h" #define FLASH_REGS_BANK2_OFS 0x40 @@ -313,7 +314,7 @@ int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* int stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, const uint8_t* buf, size_t size) { struct stlink_reg rr; - int i = 0; + unsigned timeout; size_t count = 0; uint32_t flash_base = 0; const char *error = NULL; @@ -368,16 +369,19 @@ int stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t targe * the OS uses, the wait until the error message is reduced to the same order of magnitude * as what was intended. -- REW. */ -#define WAIT_ROUNDS 40 // wait until done (reaches breakpoint) - for (i = 0; i < WAIT_ROUNDS; i++) { + timeout = time_ms() + 500; + while (time_ms() < timeout) { usleep(10000); - if (stlink_is_core_halted(sl)) { break; } + if (stlink_is_core_halted(sl)) { + timeout = 0; + break; + } } - if (i >= WAIT_ROUNDS) { + if (timeout) { error = "Flash loader run error"; goto error; } From 41bbbc2e9650f873fa562977ac89242fd4ac19fe Mon Sep 17 00:00:00 2001 From: anton Date: Thu, 18 Mar 2021 19:28:40 +0500 Subject: [PATCH 188/503] flash_loader: fix check BUSY flag, code simplified --- flashloaders/Makefile | 75 ++++++++---- flashloaders/cleanroom.md | 38 +++---- flashloaders/stm32f0.s | 78 +++++++------ flashloaders/stm32f4.s | 32 ++++-- flashloaders/stm32f4lv.s | 38 ++++--- flashloaders/stm32f7.s | 32 ++++-- flashloaders/stm32f7lv.s | 38 ++++--- flashloaders/stm32l0x.s | 22 ---- flashloaders/stm32l4.s | 32 ++++-- flashloaders/stm32lx.s | 26 +++-- src/stlink-lib/flash_loader.c | 207 ++++++++++++++-------------------- src/stlink-lib/reg.h | 6 + 12 files changed, 320 insertions(+), 304 deletions(-) delete mode 100644 flashloaders/stm32l0x.s diff --git a/flashloaders/Makefile b/flashloaders/Makefile index 7b17cb2a0..3517e1499 100644 --- a/flashloaders/Makefile +++ b/flashloaders/Makefile @@ -4,35 +4,60 @@ # This makefile will save your time from dealing with compile errors # Adjust CC if needed -CC = /opt/local/gcc-arm-none-eabi-8-2018-q4-major/bin/arm-none-eabi-gcc - -CFLAGS_thumb1 = -mcpu=Cortex-M0 -Tlinker.ld -ffreestanding -nostdlib -CFLAGS_thumb2 = -mcpu=Cortex-M3 -Tlinker.ld -ffreestanding -nostdlib - -all: stm32vl.o stm32f0.o stm32l.o stm32f4.o stm32f4_lv.o stm32l4.o stm32f7.o stm32f7_lv.o - -stm32vl.o: stm32f0.s - $(CC) stm32f0.s $(CFLAGS_thumb2) -o stm32vl.o -stm32f0.o: stm32f0.s - $(CC) stm32f0.s $(CFLAGS_thumb1) -o stm32f0.o -stm32l.o: stm32lx.s - $(CC) stm32lx.s $(CFLAGS_thumb2) -o stm32l.o -stm32f4.o: stm32f4.s - $(CC) stm32f4.s $(CFLAGS_thumb2) -o stm32f4.o -stm32f4_lv.o: stm32f4lv.s - $(CC) stm32f4lv.s $(CFLAGS_thumb2) -o stm32f4_lv.o -stm32l4.o: stm32l4.s - $(CC) stm32l4.s $(CFLAGS_thumb2) -o stm32l4.o -stm32f7.o: stm32f7.s - $(CC) stm32f7.s $(CFLAGS_thumb2) -o stm32f7.o -stm32f7_lv.o: stm32f7lv.s - $(CC) stm32f7lv.s $(CFLAGS_thumb2) -o stm32f7_lv.o +CROSS_COMPILE ?= /opt/gcc-arm-none-eabi-6-2017-q2-update/bin/arm-none-eabi- -clean: - rm *.o +CC = $(CROSS_COMPILE)gcc +OBJCOPY = $(CROSS_COMPILE)objcopy + +XXD = xxd +XXDFLAGS = -i -c 4 + +CFLAGS_THUMB1 = -mcpu=Cortex-M0 -Tlinker.ld -ffreestanding -nostdlib +CFLAGS_THUMB2 = -mcpu=Cortex-M3 -Tlinker.ld -ffreestanding -nostdlib + +all: stm32vl.h stm32f0.h stm32lx.h stm32f4.h stm32f4lv.h stm32l4.h stm32f7.h stm32f7lv.h +stm32f0.h: stm32f0.s + $(CC) stm32f0.s $(CFLAGS_THUMB1) -o stm32f0.o + $(OBJCOPY) -O binary stm32f0.o stm32f0.bin + $(XXD) $(XXDFLAGS) stm32f0.bin stm32f0.h +stm32vl.h: stm32f0.s + $(CC) stm32f0.s $(CFLAGS_THUMB2) -o stm32vl.o + $(OBJCOPY) -O binary stm32vl.o stm32vl.bin + $(XXD) $(XXDFLAGS) stm32vl.bin stm32vl.h +stm32lx.h: stm32lx.s + $(CC) stm32lx.s $(CFLAGS_THUMB2) -o stm32lx.o + $(OBJCOPY) -O binary stm32lx.o stm32lx.bin + $(XXD) $(XXDFLAGS) stm32lx.bin stm32lx.h +stm32f4.h: stm32f4.s + $(CC) stm32f4.s $(CFLAGS_THUMB2) -o stm32f4.o + $(OBJCOPY) -O binary stm32f4.o stm32f4.bin + $(XXD) $(XXDFLAGS) stm32f4.bin stm32f4.h +stm32f4lv.h: stm32f4lv.s + $(CC) stm32f4lv.s $(CFLAGS_THUMB2) -o stm32f4lv.o + $(OBJCOPY) -O binary stm32f4lv.o stm32f4lv.bin + $(XXD) $(XXDFLAGS) stm32f4lv.bin stm32f4lv.h +stm32l4.h: stm32l4.s + $(CC) stm32l4.s $(CFLAGS_THUMB2) -o stm32l4.o + $(OBJCOPY) -O binary stm32l4.o stm32l4.bin + $(XXD) $(XXDFLAGS) stm32l4.bin stm32l4.h + +stm32f7.h: stm32f7.s + $(CC) stm32f7.s $(CFLAGS_THUMB2) -o stm32f7.o + $(OBJCOPY) -O binary stm32f7.o stm32f7.bin + $(XXD) $(XXDFLAGS) stm32f7.bin stm32f7.h + +stm32f7lv.h: stm32f7lv.s + $(CC) stm32f7lv.s $(CFLAGS_THUMB2) -o stm32f7lv.o + $(OBJCOPY) -O binary stm32f7lv.o stm32f7lv.bin + $(XXD) $(XXDFLAGS) stm32f7lv.bin stm32f7lv.h + +clean: + rm *.o + rm *.bin + rm *.h diff --git a/flashloaders/cleanroom.md b/flashloaders/cleanroom.md index a468efe49..b2cb9f00d 100644 --- a/flashloaders/cleanroom.md +++ b/flashloaders/cleanroom.md @@ -1,6 +1,4 @@ -Original Chinese version can be found below. - -# Clean Room Documentation English Version +# Flash Loader Documentation Code is situated in section `.text` @@ -12,11 +10,12 @@ All parameters would be passed over registers `r0`: the base address of the copy source `r1`: the base address of the copy destination -`r2`: the total word (4 bytes) count to be copied (with expeptions) +`r2`: the count of byte to be copied +`r3`: flash register offset (used to support two banks) **What the program is expected to do**: -Copy data from source to destination, after which trigger a breakpint to exit. Before exit, `r2` must be cleared to zero to indicate that the copy is done. +Copy data from source to destination, after which trigger a breakpint to exit. Before exit, `r2` must be less or equal to zero to indicate that the copy is done. **Limitation**: No stack operations are permitted. Registers ranging from `r3` to `r12` are free to use. Note that `r13` is `sp`(stack pointer), `r14` is `lr`(commonly used to store jump address), `r15` is `pc`(program counter). @@ -24,8 +23,6 @@ Copy data from source to destination, after which trigger a breakpint to exit. B ## stm32f0.s -**Exception**: `r2` stores the total half word (2 bytes) count to be copied - `flash_base`: 0x40022000 `FLASH_CR`: offset from `flash_base` is 16 @@ -37,11 +34,11 @@ Copy data from source to destination, after which trigger a breakpint to exit. B **Special requirements**: -Before every copy, read a word from FLASH_CR, set the lowest bit to 1 and write back. Copy one half word each time. +Before every copy, read a word from FLASH_CR, set the PG bit to 1 and write back. Copy one half word each time. -How to wait for the write process: read a word from FLASH_SR, loop until the content is not 1. After that, check FLASH_SR, proceed if the content is 4, otherwise exit. +How to wait for the write process: read a word from FLASH_SR, loop until the busy bit is reset. After that, FLASH_SR is check. The process is interrupted if the error bit (0x04) is set. -Exit: after the copying process and before triggering the breakpoint, clear the lowest bit in FLASH_CR. +Exit: after the copying process and before triggering the breakpoint, clear the PG bit in FLASH_CR. ## stm32f4.s @@ -56,7 +53,8 @@ Exit: after the copying process and before triggering the breakpoint, clear the **Special requirements**: Copy one word each time. -How to wait for the write process: read a half word from FLASH_SR, loop until the content is not 1. + +How to wait for the write process: read a word from FLASH_SR, loop until the busy bit is reset. ## stm32f4lv.s @@ -71,7 +69,7 @@ How to wait for the write process: read a half word from FLASH_SR, loop until th Copy one byte each time. -How to wait from the write process: read a half word from FLASH_SR, loop until the content is not 1. +How to wait from the write process: read a half word from FLASH_SR, loop until the busy bit is reset. ## stm32f7.s @@ -89,7 +87,7 @@ Mostly same with `stm32f4.s`. Require establishing a memory barrier after every Mostly same with `stm32f7.s`. Copy one byte each time. -## stm32l0x.s +## stm32lx.s **Special Requirements**: @@ -97,8 +95,6 @@ Copy one word each time. No wait for write. ## stm32l4.s -**Exception**: r2 stores the double word count to be copied. - `flash_base`: 0x40022000 `FLASH_BSY`: offset from `flash_base` is 0x12 @@ -109,14 +105,10 @@ Copy one word each time. No wait for write. Copy one double word each time (More than one registers are allowed). -How to wait for the write process: read a half word from `FLASH_BSY`, loop until the lowest bit turns non-1. - -## stm32lx.s +How to wait for the write process: read a half word from `FLASH_BSY`, loop until the busy bit is reset. -Same with stm32l0x.s. - -# 净室工程文档-原始中文版 +# 净室工程文档-原始中文版 (out of date) 代码位于的section：`.text` 编译制导添加`.syntax unified` @@ -139,8 +131,6 @@ Same with stm32l0x.s. ## stm32f0.s -例外：`r2`:拷贝half word（2字节）数 - 特殊地址定义：`flash_base`:定义为0x40022000 `FLASH_CR`: 相对`flash_base`的offset为16 @@ -230,4 +220,4 @@ Same with stm32l0x.s. ## stm32lx.s -要求与stm32l0x.s相同 \ No newline at end of file +要求与stm32l0x.s相同 diff --git a/flashloaders/stm32f0.s b/flashloaders/stm32f0.s index f30e4bfc6..e2a4b0f00 100644 --- a/flashloaders/stm32f0.s +++ b/flashloaders/stm32f0.s @@ -1,6 +1,14 @@ .syntax unified .text + /* + * Arguments: + * r0 - source memory ptr + * r1 - target memory ptr + * r2 - count of bytes + * r3 - flash register offset + */ + .global copy copy: /* @@ -17,54 +25,56 @@ copy: */ nop nop - ldr r7, =flash_base - ldr r4, [r7] - ldr r7, =flash_off_cr - ldr r6, [r7] - adds r6, r6, r4 - ldr r7, =flash_off_sr - ldr r5, [r7] - adds r5, r5, r4 -loop: - # FLASH_CR ^= 1 + # load flash control register address + # add r3 to flash_base for support dual bank (see flash_loader.c) + ldr r7, flash_base + add r7, r7, r3 + ldr r6, flash_off_cr + add r6, r6, r7 + ldr r5, flash_off_sr + add r5, r5, r7 + + # FLASH_CR |= 0x01 (set PG) ldr r7, =0x1 - ldr r3, [r6] - orrs r3, r3, r7 - str r3, [r6] + ldr r4, [r6] + orrs r4, r4, r7 + str r4, [r6] +loop: # copy 2 bytes - ldrh r3, [r0] - strh r3, [r1] + ldrh r4, [r0] + strh r4, [r1] - ldr r7, =2 - adds r0, r0, r7 - adds r1, r1, r7 + # increment address + adds r0, r0, #0x2 + adds r1, r1, #0x2 - # wait if FLASH_SR == 1 + # BUSY flag + ldr r7, =0x01 wait: - ldr r7, =0x1 - ldr r3, [r5] - tst r3, r7 - beq wait + # get FLASH_SR + ldr r4, [r5] - # exit if FLASH_SR != 4 - ldr r7, =0x4 - tst r3, r7 + # wait until BUSY flag is reset + tst r4, r7 + bne wait + + # test PGERR or WRPRTERR flag is reset + ldr r7, =0x14 + tst r4, r7 bne exit - # loop if r2 != 0 - ldr r7, =0x1 - subs r2, r2, r7 - cmp r2, #0 - bne loop + # loop if count > 0 + subs r2, r2, #0x2 + bgt loop exit: # FLASH_CR &= ~1 ldr r7, =0x1 - ldr r3, [r6] - bics r3, r3, r7 - str r3, [r6] + ldr r4, [r6] + bics r4, r4, r7 + str r4, [r6] bkpt diff --git a/flashloaders/stm32f4.s b/flashloaders/stm32f4.s index a88ad9e02..a66c70dac 100644 --- a/flashloaders/stm32f4.s +++ b/flashloaders/stm32f4.s @@ -1,6 +1,14 @@ .syntax unified .text + /* + * Arguments: + * r0 - source memory ptr + * r1 - target memory ptr + * r2 - count of bytes + * r3 - flash register offset + */ + .global copy copy: ldr r12, flash_base @@ -9,22 +17,24 @@ copy: loop: # copy 4 bytes - ldr r3, [r0] - str r3, [r1] + ldr r4, [r0] + str r4, [r1] + # increment address add r0, r0, #4 add r1, r1, #4 - # wait if FLASH_SR == 1 wait: - ldrh r3, [r10] - tst r3, #0x1 - beq wait - - # loop if r2 != 0 - sub r2, r2, #1 - cmp r2, #0 - bne loop + # get FLASH_SR + ldrh r4, [r10] + + # wait until BUSY flag is reset + tst r4, #0x1 + bne wait + + # loop if count > 0 + subs r2, r2, #4 + bgt loop exit: bkpt diff --git a/flashloaders/stm32f4lv.s b/flashloaders/stm32f4lv.s index 41467a9ef..b8fcfa048 100644 --- a/flashloaders/stm32f4lv.s +++ b/flashloaders/stm32f4lv.s @@ -1,36 +1,40 @@ .syntax unified .text + /* + * Arguments: + * r0 - source memory ptr + * r1 - target memory ptr + * r2 - count of bytes + * r3 - flash register offset + */ + .global copy copy: ldr r12, flash_base ldr r10, flash_off_sr add r10, r10, r12 - # tip 1: original r2 indicates the count of 4 bytes need to copy, - # but we can only copy one byte each time. - # as we have no flash larger than 1GB, we do a little trick here. - # tip 2: r2 is always a power of 2 - mov r2, r2, lsl#2 - loop: # copy 1 byte - ldrb r3, [r0] - strb r3, [r1] + ldrb r4, [r0] + strb r4, [r1] + # increment address add r0, r0, #1 add r1, r1, #1 - # wait if FLASH_SR == 1 wait: - ldrh r3, [r10] - tst r3, #0x1 - beq wait - - # loop if r2 != 0 - sub r2, r2, #1 - cmp r2, #0 - bne loop + # get FLASH_SR + ldrh r4, [r10] + + # wait until BUSY flag is reset + tst r4, #0x1 + bne wait + + # loop if count > 0 + subs r2, r2, #1 + bgt loop exit: bkpt diff --git a/flashloaders/stm32f7.s b/flashloaders/stm32f7.s index 3779a5ea6..4b43cebdc 100644 --- a/flashloaders/stm32f7.s +++ b/flashloaders/stm32f7.s @@ -1,6 +1,14 @@ .syntax unified .text + /* + * Arguments: + * r0 - source memory ptr + * r1 - target memory ptr + * r2 - count of bytes + * r3 - flash register offset + */ + .global copy copy: ldr r12, flash_base @@ -9,25 +17,27 @@ copy: loop: # copy 4 bytes - ldr r3, [r0] - str r3, [r1] + ldr r4, [r0] + str r4, [r1] + # increment address add r0, r0, #4 add r1, r1, #4 # memory barrier dsb sy - # wait if FLASH_SR == 1 wait: - ldrh r3, [r10] - tst r3, #0x1 - beq wait - - # loop if r2 != 0 - sub r2, r2, #1 - cmp r2, #0 - bne loop + # get FLASH_SR + ldrh r4, [r10] + + # wait until BUSY flag is reset + tst r4, #0x1 + bne wait + + # loop if count > 0 + subs r2, r2, #4 + bgt loop exit: bkpt diff --git a/flashloaders/stm32f7lv.s b/flashloaders/stm32f7lv.s index e7b66cc2c..78ff35dbc 100644 --- a/flashloaders/stm32f7lv.s +++ b/flashloaders/stm32f7lv.s @@ -1,39 +1,43 @@ .syntax unified .text + /* + * Arguments: + * r0 - source memory ptr + * r1 - target memory ptr + * r2 - count of bytes + * r3 - flash register offset + */ + .global copy copy: ldr r12, flash_base ldr r10, flash_off_sr add r10, r10, r12 - # tip 1: original r2 indicates the count in 4 bytes need to copy, - # but we can only copy one byte each time. - # as we have no flash larger than 1GB, we do a little trick here. - # tip 2: r2 is always a power of 2 - mov r2, r2, lsl#2 - loop: # copy 1 byte - ldrb r3, [r0] - strb r3, [r1] + ldrb r4, [r0] + strb r4, [r1] + # increment address add r0, r0, #1 add r1, r1, #1 # memory barrier dsb sy - # wait if FLASH_SR == 1 wait: - ldrh r3, [r10] - tst r3, #0x1 - beq wait - - # loop if r2 != 0 - sub r2, r2, #1 - cmp r2, #0 - bne loop + # get FLASH_SR + ldrh r4, [r10] + + # wait until BUSY flag is reset + tst r4, #0x1 + bne wait + + # loop if count > 0 + subs r2, r2, #1 + bgt loop exit: bkpt diff --git a/flashloaders/stm32l0x.s b/flashloaders/stm32l0x.s deleted file mode 100644 index f9c257e2e..000000000 --- a/flashloaders/stm32l0x.s +++ /dev/null @@ -1,22 +0,0 @@ - .syntax unified - .text - - .global copy -copy: -loop: - # copy 4 bytes - ldr r3, [r0] - str r3, [r1] - - ldr r7, =4 - add r0, r0, r7 - add r1, r1, r7 - - # loop if r2 != 0 - ldr r7, =1 - subs r2, r2, r7 - cmp r2, #0 - bne loop - -exit: - bkpt diff --git a/flashloaders/stm32l4.s b/flashloaders/stm32l4.s index 32c27a057..21e926f49 100644 --- a/flashloaders/stm32l4.s +++ b/flashloaders/stm32l4.s @@ -1,6 +1,14 @@ .syntax unified .text + /* + * Arguments: + * r0 - source memory ptr + * r1 - target memory ptr + * r2 - count of bytes + * r3 - flash register offset + */ + .global copy copy: ldr r12, flash_base @@ -9,24 +17,26 @@ copy: loop: # copy 8 bytes - ldr r3, [r0] + ldr r5, [r0] ldr r4, [r0, #4] - str r3, [r1] + str r5, [r1] str r4, [r1, #4] + # increment address add r0, r0, #8 add r1, r1, #8 - # wait if FLASH_BSY[0b] == 1 wait: - ldrh r3, [r10] - tst r3, #0x1 - beq wait - - # loop if r2 != 0 - sub r2, r2, #1 - cmp r2, #0 - bne loop + # get FLASH_SR + ldr r4, [r10] + + # wait until BUSY flag is reset + tst r4, #0x10000 + bne wait + + # loop if count > 0 + subs r2, r2, #8 + bgt loop exit: bkpt diff --git a/flashloaders/stm32lx.s b/flashloaders/stm32lx.s index f9c257e2e..69acdea7b 100644 --- a/flashloaders/stm32lx.s +++ b/flashloaders/stm32lx.s @@ -1,22 +1,28 @@ .syntax unified .text + /* + * Arguments: + * r0 - source memory ptr + * r1 - target memory ptr + * r2 - count of bytes + * r3 - flash register offset + */ + .global copy copy: loop: # copy 4 bytes - ldr r3, [r0] - str r3, [r1] + ldr r4, [r0] + str r4, [r1] - ldr r7, =4 - add r0, r0, r7 - add r1, r1, r7 + # increment address + add r0, r0, #4 + add r1, r1, #4 - # loop if r2 != 0 - ldr r7, =1 - subs r2, r2, r7 - cmp r2, #0 - bne loop + # loop if count > 0 + subs r2, r2, #4 + bgt loop exit: bkpt diff --git a/src/stlink-lib/flash_loader.c b/src/stlink-lib/flash_loader.c index 1224215e5..5bc314b07 100644 --- a/src/stlink-lib/flash_loader.c +++ b/src/stlink-lib/flash_loader.c @@ -13,89 +13,72 @@ /* flashloaders/stm32f0.s -- compiled with thumb2 */ static const uint8_t loader_code_stm32vl[] = { - 0x16, 0x4f, 0x3c, 0x68, - 0x16, 0x4f, 0x3e, 0x68, - 0x36, 0x19, 0x16, 0x4f, - 0x3d, 0x68, 0x2d, 0x19, + 0x00, 0xbf, 0x00, 0xbf, + 0x0f, 0x4f, 0x1f, 0x44, + 0x0f, 0x4e, 0x3e, 0x44, + 0x0f, 0x4d, 0x3d, 0x44, 0x4f, 0xf0, 0x01, 0x07, - 0x33, 0x68, 0x3b, 0x43, - 0x33, 0x60, 0x03, 0x88, - 0x0b, 0x80, 0x4f, 0xf0, - 0x02, 0x07, 0xc0, 0x19, - 0xc9, 0x19, 0x4f, 0xf0, - 0x01, 0x07, 0x2b, 0x68, - 0x3b, 0x42, 0xfa, 0xd0, - 0x4f, 0xf0, 0x04, 0x07, - 0x3b, 0x42, 0x04, 0xd1, + 0x34, 0x68, 0x3c, 0x43, + 0x34, 0x60, 0x04, 0x88, + 0x0c, 0x80, 0x02, 0x30, + 0x02, 0x31, 0x4f, 0xf0, + 0x01, 0x07, 0x2c, 0x68, + 0x3c, 0x42, 0xfc, 0xd1, + 0x4f, 0xf0, 0x14, 0x07, + 0x3c, 0x42, 0x01, 0xd1, + 0x02, 0x3a, 0xf0, 0xdc, 0x4f, 0xf0, 0x01, 0x07, - 0xd2, 0x1b, 0x00, 0x2a, - 0xe6, 0xd1, 0x4f, 0xf0, - 0x01, 0x07, 0x33, 0x68, - 0xbb, 0x43, 0x33, 0x60, - 0x00, 0xbe, 0x00, 0xbf, + 0x34, 0x68, 0xbc, 0x43, + 0x34, 0x60, 0x00, 0xbe, 0x00, 0x20, 0x02, 0x40, 0x10, 0x00, 0x00, 0x00, - 0x0c, 0x00, 0x00, 0x00, - 0x50, 0x00, 0x00, 0x20, - 0x54, 0x00, 0x00, 0x20, - 0x58, 0x00, 0x00, 0x20 + 0x0c, 0x00, 0x00, 0x00 }; /* flashloaders/stm32f0.s -- thumb1 only, same sequence as for STM32VL, bank ignored */ static const uint8_t loader_code_stm32f0[] = { 0xc0, 0x46, 0xc0, 0x46, - 0x13, 0x4f, 0x3c, 0x68, - 0x13, 0x4f, 0x3e, 0x68, - 0x36, 0x19, 0x13, 0x4f, - 0x3d, 0x68, 0x2d, 0x19, - 0x12, 0x4f, 0x33, 0x68, - 0x3b, 0x43, 0x33, 0x60, - 0x03, 0x88, 0x0b, 0x80, - 0x10, 0x4f, 0xc0, 0x19, - 0xc9, 0x19, 0x0e, 0x4f, - 0x2b, 0x68, 0x3b, 0x42, - 0xfb, 0xd0, 0x0e, 0x4f, - 0x3b, 0x42, 0x03, 0xd1, - 0x0a, 0x4f, 0xd2, 0x1b, - 0x00, 0x2a, 0xeb, 0xd1, - 0x08, 0x4f, 0x33, 0x68, - 0xbb, 0x43, 0x33, 0x60, - 0x00, 0xbe, 0xc0, 0x46, + 0x0d, 0x4f, 0x1f, 0x44, + 0x0d, 0x4e, 0x3e, 0x44, + 0x0d, 0x4d, 0x3d, 0x44, + 0x0d, 0x4f, 0x34, 0x68, + 0x3c, 0x43, 0x34, 0x60, + 0x04, 0x88, 0x0c, 0x80, + 0x02, 0x30, 0x02, 0x31, + 0x09, 0x4f, 0x2c, 0x68, + 0x3c, 0x42, 0xfc, 0xd1, + 0x08, 0x4f, 0x3c, 0x42, + 0x01, 0xd1, 0x02, 0x3a, + 0xf2, 0xdc, 0x05, 0x4f, + 0x34, 0x68, 0xbc, 0x43, + 0x34, 0x60, 0x00, 0xbe, 0x00, 0x20, 0x02, 0x40, 0x10, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x00, - 0x48, 0x00, 0x00, 0x20, - 0x4c, 0x00, 0x00, 0x20, - 0x50, 0x00, 0x00, 0x20, 0x01, 0x00, 0x00, 0x00, - 0x02, 0x00, 0x00, 0x00, - 0x04, 0x00, 0x00, 0x00 + 0x14, 0x00, 0x00, 0x00 }; -static const uint8_t loader_code_stm32l[] = { +static const uint8_t loader_code_stm32lx[] = { // flashloaders/stm32lx.s - - 0x03, 0x68, 0x0b, 0x60, - 0x4f, 0xf0, 0x04, 0x07, - 0x38, 0x44, 0x39, 0x44, - 0x4f, 0xf0, 0x01, 0x07, - 0xd2, 0x1b, 0x00, 0x2a, - 0xf4, 0xd1, 0x00, 0xbe, + 0x04, 0x68, 0x0c, 0x60, + 0x00, 0xf1, 0x04, 0x00, + 0x01, 0xf1, 0x04, 0x01, + 0x04, 0x3a, 0xf7, 0xdc, + 0x00, 0xbe }; static const uint8_t loader_code_stm32f4[] = { // flashloaders/stm32f4.s - - 0xdf, 0xf8, 0x28, 0xc0, - 0xdf, 0xf8, 0x28, 0xa0, - 0xe2, 0x44, 0x03, 0x68, - 0x0b, 0x60, 0x00, 0xf1, + 0xdf, 0xf8, 0x24, 0xc0, + 0xdf, 0xf8, 0x24, 0xa0, + 0xe2, 0x44, 0x04, 0x68, + 0x0c, 0x60, 0x00, 0xf1, 0x04, 0x00, 0x01, 0xf1, 0x04, 0x01, 0xba, 0xf8, - 0x00, 0x30, 0x13, 0xf0, - 0x01, 0x0f, 0xfa, 0xd0, - 0xa2, 0xf1, 0x01, 0x02, - 0x00, 0x2a, 0xf0, 0xd1, + 0x00, 0x40, 0x14, 0xf0, + 0x01, 0x0f, 0xfa, 0xd1, + 0x04, 0x3a, 0xf2, 0xdc, 0x00, 0xbe, 0x00, 0xbf, 0x00, 0x3c, 0x02, 0x40, 0x0e, 0x00, 0x00, 0x00 @@ -103,17 +86,15 @@ static const uint8_t loader_code_stm32f4[] = { static const uint8_t loader_code_stm32f4_lv[] = { // flashloaders/stm32f4lv.s - 0xdf, 0xf8, 0x2c, 0xc0, - 0xdf, 0xf8, 0x2c, 0xa0, - 0xe2, 0x44, 0x4f, 0xea, - 0x82, 0x02, 0x03, 0x78, - 0x0b, 0x70, 0x00, 0xf1, + 0xdf, 0xf8, 0x24, 0xc0, + 0xdf, 0xf8, 0x24, 0xa0, + 0xe2, 0x44, 0x04, 0x78, + 0x0c, 0x70, 0x00, 0xf1, 0x01, 0x00, 0x01, 0xf1, 0x01, 0x01, 0xba, 0xf8, - 0x00, 0x30, 0x13, 0xf0, - 0x01, 0x0f, 0xfa, 0xd0, - 0xa2, 0xf1, 0x01, 0x02, - 0x00, 0x2a, 0xf0, 0xd1, + 0x00, 0x40, 0x14, 0xf0, + 0x01, 0x0f, 0xfa, 0xd1, + 0x01, 0x3a, 0xf2, 0xdc, 0x00, 0xbe, 0x00, 0xbf, 0x00, 0x3c, 0x02, 0x40, 0x0e, 0x00, 0x00, 0x00 @@ -121,17 +102,16 @@ static const uint8_t loader_code_stm32f4_lv[] = { static const uint8_t loader_code_stm32l4[] = { // flashloaders/stm32l4.s - 0xdf, 0xf8, 0x2c, 0xc0, - 0xdf, 0xf8, 0x2c, 0xa0, - 0xe2, 0x44, 0x03, 0x68, - 0x44, 0x68, 0x0b, 0x60, + 0xdf, 0xf8, 0x28, 0xc0, + 0xdf, 0xf8, 0x28, 0xa0, + 0xe2, 0x44, 0x05, 0x68, + 0x44, 0x68, 0x0d, 0x60, 0x4c, 0x60, 0x00, 0xf1, 0x08, 0x00, 0x01, 0xf1, - 0x08, 0x01, 0xba, 0xf8, - 0x00, 0x30, 0x13, 0xf0, - 0x01, 0x0f, 0xfa, 0xd0, - 0xa2, 0xf1, 0x01, 0x02, - 0x00, 0x2a, 0xee, 0xd1, + 0x08, 0x01, 0xda, 0xf8, + 0x00, 0x40, 0x14, 0xf4, + 0x80, 0x3f, 0xfa, 0xd1, + 0x08, 0x3a, 0xf0, 0xdc, 0x00, 0xbe, 0x00, 0xbf, 0x00, 0x20, 0x02, 0x40, 0x12, 0x00, 0x00, 0x00 @@ -139,17 +119,16 @@ static const uint8_t loader_code_stm32l4[] = { static const uint8_t loader_code_stm32f7[] = { // flashloaders/stm32f7.s - 0xdf, 0xf8, 0x2c, 0xc0, - 0xdf, 0xf8, 0x2c, 0xa0, - 0xe2, 0x44, 0x03, 0x68, - 0x0b, 0x60, 0x00, 0xf1, + 0xdf, 0xf8, 0x28, 0xc0, + 0xdf, 0xf8, 0x28, 0xa0, + 0xe2, 0x44, 0x04, 0x68, + 0x0c, 0x60, 0x00, 0xf1, 0x04, 0x00, 0x01, 0xf1, 0x04, 0x01, 0xbf, 0xf3, 0x4f, 0x8f, 0xba, 0xf8, - 0x00, 0x30, 0x13, 0xf0, - 0x01, 0x0f, 0xfa, 0xd0, - 0xa2, 0xf1, 0x01, 0x02, - 0x00, 0x2a, 0xee, 0xd1, + 0x00, 0x40, 0x14, 0xf0, + 0x01, 0x0f, 0xfa, 0xd1, + 0x04, 0x3a, 0xf0, 0xdc, 0x00, 0xbe, 0x00, 0xbf, 0x00, 0x3c, 0x02, 0x40, 0x0e, 0x00, 0x00, 0x00 @@ -157,18 +136,16 @@ static const uint8_t loader_code_stm32f7[] = { static const uint8_t loader_code_stm32f7_lv[] = { // flashloaders/stm32f7lv.s - 0xdf, 0xf8, 0x30, 0xc0, - 0xdf, 0xf8, 0x30, 0xa0, - 0xe2, 0x44, 0x4f, 0xea, - 0x82, 0x02, 0x03, 0x78, - 0x0b, 0x70, 0x00, 0xf1, + 0xdf, 0xf8, 0x28, 0xc0, + 0xdf, 0xf8, 0x28, 0xa0, + 0xe2, 0x44, 0x04, 0x78, + 0x0c, 0x70, 0x00, 0xf1, 0x01, 0x00, 0x01, 0xf1, 0x01, 0x01, 0xbf, 0xf3, 0x4f, 0x8f, 0xba, 0xf8, - 0x00, 0x30, 0x13, 0xf0, - 0x01, 0x0f, 0xfa, 0xd0, - 0xa2, 0xf1, 0x01, 0x02, - 0x00, 0x2a, 0xee, 0xd1, + 0x00, 0x40, 0x14, 0xf0, + 0x01, 0x0f, 0xfa, 0xd1, + 0x01, 0x3a, 0xf0, 0xdc, 0x00, 0xbe, 0x00, 0xbf, 0x00, 0x3c, 0x02, 0x40, 0x0e, 0x00, 0x00, 0x00 @@ -234,8 +211,8 @@ int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* sl->chip_id == STLINK_CHIPID_STM32_L0 || sl->chip_id == STLINK_CHIPID_STM32_L0_CAT5 || sl->chip_id == STLINK_CHIPID_STM32_L0_CAT2) { // STM32l - loader_code = loader_code_stm32l; - loader_size = sizeof(loader_code_stm32l); + loader_code = loader_code_stm32lx; + loader_size = sizeof(loader_code_stm32lx); } else if (sl->core_id == STM32VL_CORE_ID || sl->chip_id == STLINK_CHIPID_STM32_F1_MEDIUM || sl->chip_id == STLINK_CHIPID_STM32_F1_HIGH || @@ -315,10 +292,9 @@ int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* int stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, const uint8_t* buf, size_t size) { struct stlink_reg rr; unsigned timeout; - size_t count = 0; uint32_t flash_base = 0; const char *error = NULL; - uint32_t dhcsr, dfsr; + uint32_t dhcsr, dfsr, cfsr, hfsr; DLOG("Running flash loader, write address:%#x, size: %u\n", target, (unsigned int)size); @@ -329,22 +305,6 @@ int stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t targe return(-1); } - if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || - (sl->flash_type == STLINK_FLASH_TYPE_F1_XL)) { - count = size / sizeof(uint16_t); - - if (size % sizeof(uint16_t)) { ++count; } - } else if (sl->flash_type == STLINK_FLASH_TYPE_F4 || - sl->flash_type == STLINK_FLASH_TYPE_L0) { - count = size / sizeof(uint32_t); - - if (size % sizeof(uint32_t)) { ++count; } - } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { - count = size / sizeof(uint64_t); - - if (size % sizeof(uint64_t)) { ++count; } - } - if ((sl->flash_type == STLINK_FLASH_TYPE_F1_XL) && (target >= FLASH_BANK2_START_ADDR)) { flash_base = FLASH_REGS_BANK2_OFS; } @@ -352,7 +312,7 @@ int stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t targe /* Setup core */ stlink_write_reg(sl, fl->buf_addr, 0); // source stlink_write_reg(sl, target, 1); // target - stlink_write_reg(sl, (uint32_t)count, 2); // count + stlink_write_reg(sl, (uint32_t)size, 2); // count stlink_write_reg(sl, flash_base, 3); // flash register base // only used on VL/F1_XL, but harmless for others stlink_write_reg(sl, fl->loader_addr, 15); // pc register @@ -376,9 +336,9 @@ int stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t targe usleep(10000); if (stlink_is_core_halted(sl)) { - timeout = 0; - break; - } + timeout = 0; + break; + } } if (timeout) { @@ -397,11 +357,14 @@ int stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t targe return(0); error: - dhcsr = dfsr = 0; + dhcsr = dfsr = cfsr = hfsr = 0; stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); stlink_read_debug32(sl, STLINK_REG_DFSR, &dfsr); + stlink_read_debug32(sl, STLINK_REG_CFSR, &cfsr); + stlink_read_debug32(sl, STLINK_REG_HFSR, &hfsr); stlink_read_all_regs(sl, &rr); - ELOG("%s (R2 0x%08X R15 0x%08X DHCSR 0x%08X DFSR 0x%08X)\n", error, rr.r[2], rr.r[15], dhcsr, dfsr); + ELOG("%s (R2 0x%X R15 0x%X DHCSR 0x%X DFSR 0x%X CFSR 0x%X HFSR 0x%X)\n", error, rr.r[2], rr.r[15], dhcsr, dfsr, cfsr, hfsr); + ELOG("(R0 0x%X R1 0x%X)\n", rr.r[0], rr.r[1]); return(-1); } diff --git a/src/stlink-lib/reg.h b/src/stlink-lib/reg.h index 6d2c9f1af..473231117 100644 --- a/src/stlink-lib/reg.h +++ b/src/stlink-lib/reg.h @@ -19,6 +19,12 @@ #define STLINK_REG_CM3_DWT_FUNn(n) (0xE0001028 + n*16) /* Cortex™-M3 Technical Reference Manual */ +/* Configurable Fault Status Register */ +#define STLINK_REG_CFSR 0xE000ED28 + +/* Hard Fault Status Register */ +#define STLINK_REG_HFSR 0xE000ED2C + /* Debug Halting Control and Status Register */ #define STLINK_REG_DFSR 0xE000ED30 #define STLINK_REG_DFSR_HALT (1 << 0) From 76f153035a90fc72dc075a75c3d0523c0e0f0ddb Mon Sep 17 00:00:00 2001 From: anton Date: Thu, 18 Mar 2021 23:03:10 +0500 Subject: [PATCH 189/503] flash_loader: disable interrupt before start --- src/common.c | 16 ++++++++++++++++ src/stlink-lib/flash_loader.c | 13 ++++++++----- 2 files changed, 24 insertions(+), 5 deletions(-) diff --git a/src/common.c b/src/common.c index 99049196d..eeccd5f5b 100644 --- a/src/common.c +++ b/src/common.c @@ -2730,6 +2730,13 @@ int stm32l1_write_half_pages( } int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { + + // force halt and disable interrupt + stlink_write_debug32(sl, STLINK_REG_DHCSR, STLINK_REG_DHCSR_DBGKEY | + STLINK_REG_DHCSR_C_DEBUGEN | + STLINK_REG_DHCSR_C_HALT | + STLINK_REG_DHCSR_C_MASKINTS); + if ((sl->flash_type == STLINK_FLASH_TYPE_F4) || (sl->flash_type == STLINK_FLASH_TYPE_F7) || (sl->flash_type == STLINK_FLASH_TYPE_L4)) { @@ -2998,6 +3005,8 @@ int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t addr } int stlink_flashloader_stop(stlink_t *sl) { + uint32_t dhcsr; + if ((sl->flash_type == STLINK_FLASH_TYPE_F4) || (sl->flash_type == STLINK_FLASH_TYPE_F7) || (sl->flash_type == STLINK_FLASH_TYPE_L4) || @@ -3028,6 +3037,13 @@ int stlink_flashloader_stop(stlink_t *sl) { stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); } + // enable interrupt + if (!stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr)) { + stlink_write_debug32(sl, STLINK_REG_DHCSR, STLINK_REG_DHCSR_DBGKEY | + STLINK_REG_DHCSR_C_DEBUGEN | + (dhcsr&(~STLINK_REG_DHCSR_C_MASKINTS))); + } + return(0); } diff --git a/src/stlink-lib/flash_loader.c b/src/stlink-lib/flash_loader.c index 5bc314b07..9fa897ccc 100644 --- a/src/stlink-lib/flash_loader.c +++ b/src/stlink-lib/flash_loader.c @@ -293,7 +293,6 @@ int stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t targe struct stlink_reg rr; unsigned timeout; uint32_t flash_base = 0; - const char *error = NULL; uint32_t dhcsr, dfsr, cfsr, hfsr; DLOG("Running flash loader, write address:%#x, size: %u\n", target, (unsigned int)size); @@ -342,7 +341,7 @@ int stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t targe } if (timeout) { - error = "Flash loader run error"; + ELOG("Flash loader run error\n"); goto error; } @@ -350,7 +349,7 @@ int stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t targe stlink_read_reg(sl, 2, &rr); if (rr.r[2] != 0) { - error = "Write error"; + ELOG("Write error\n"); goto error; } @@ -363,8 +362,12 @@ int stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t targe stlink_read_debug32(sl, STLINK_REG_CFSR, &cfsr); stlink_read_debug32(sl, STLINK_REG_HFSR, &hfsr); stlink_read_all_regs(sl, &rr); - ELOG("%s (R2 0x%X R15 0x%X DHCSR 0x%X DFSR 0x%X CFSR 0x%X HFSR 0x%X)\n", error, rr.r[2], rr.r[15], dhcsr, dfsr, cfsr, hfsr); - ELOG("(R0 0x%X R1 0x%X)\n", rr.r[0], rr.r[1]); + + WLOG("Loader state: R2 0x%X R15 0x%X\n", rr.r[2], rr.r[15]); + if (dhcsr != 0x3000B || dfsr != 0x3 || cfsr || hfsr) { + WLOG("MCU state: DHCSR 0x%X DFSR 0x%X CFSR 0x%X HFSR 0x%X\n", + dhcsr, dfsr, cfsr, hfsr); + } return(-1); } From bc9062c6c590e603e203567b6bfe14baf4c6a0af Mon Sep 17 00:00:00 2001 From: anton Date: Fri, 19 Mar 2021 18:59:09 +0500 Subject: [PATCH 190/503] flash_loader: preventing unpredictable behavior when disabling interrupts --- src/common.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/src/common.c b/src/common.c index eeccd5f5b..1fd023962 100644 --- a/src/common.c +++ b/src/common.c @@ -2731,7 +2731,11 @@ int stm32l1_write_half_pages( int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { - // force halt and disable interrupt + // According to DDI0419C, Table C1-7 firstly force halt + stlink_write_debug32(sl, STLINK_REG_DHCSR, STLINK_REG_DHCSR_DBGKEY | + STLINK_REG_DHCSR_C_DEBUGEN | + STLINK_REG_DHCSR_C_HALT); + // and only then disable interrupts stlink_write_debug32(sl, STLINK_REG_DHCSR, STLINK_REG_DHCSR_DBGKEY | STLINK_REG_DHCSR_C_DEBUGEN | STLINK_REG_DHCSR_C_HALT | From de89563057fca8d0aaa6b6dfa8655557523507e6 Mon Sep 17 00:00:00 2001 From: anton Date: Sat, 20 Mar 2021 14:09:52 +0500 Subject: [PATCH 191/503] gdb-server: added target description for all mcu --- src/st-util/gdb-server.c | 27 +++++++++++---------------- 1 file changed, 11 insertions(+), 16 deletions(-) diff --git a/src/st-util/gdb-server.c b/src/st-util/gdb-server.c index 4177cef11..e35e5c2e8 100644 --- a/src/st-util/gdb-server.c +++ b/src/st-util/gdb-server.c @@ -288,7 +288,7 @@ int main(int argc, char** argv) { return(0); } -static const char* const target_description_F4 = +static const char* const target_description = "" "" "" @@ -1178,13 +1178,7 @@ int serve(stlink_t *sl, st_state_t *st) { DLOG("query: %s;%s\n", queryName, params); if (!strcmp(queryName, "Supported")) { - if (sl->chip_id == STLINK_CHIPID_STM32_F4 || - sl->chip_id == STLINK_CHIPID_STM32_F4_HD || - sl->core_id == STM32F7_CORE_ID) { - reply = strdup("PacketSize=3fff;qXfer:memory-map:read+;qXfer:features:read+"); - } else { - reply = strdup("PacketSize=3fff;qXfer:memory-map:read+"); - } + reply = strdup("PacketSize=3fff;qXfer:memory-map:read+;qXfer:features:read+"); } else if (!strcmp(queryName, "Xfer")) { char *type, *op, *__s_addr, *s_length; char *tok = params; @@ -1202,14 +1196,15 @@ int serve(stlink_t *sl, st_state_t *st) { DLOG("Xfer: type:%s;op:%s;annex:%s;addr:%d;length:%d\n", type, op, annex, addr, length); - const char* data = NULL; - - if (!strcmp(type, "memory-map") && !strcmp(op, "read")) { + const char* data; + if (strcmp(op, "read")) { + data = NULL; + } else if (!strcmp(type, "memory-map")) { data = current_memory_map; - } - - if (!strcmp(type, "features") && !strcmp(op, "read")) { - data = target_description_F4; + } else if (!strcmp(type, "features")) { + data = target_description; + } else { + data = NULL; } if (data) { @@ -1592,7 +1587,7 @@ int serve(stlink_t *sl, st_state_t *st) { reply = strdup("E00"); } - if (ret) { DLOG("p packet: stlink_read_unsupported_reg failed with id %u\n", id); } + if (ret) { DLOG("p packet: could not read register with id %u\n", id); } if (reply == NULL) { // if reply is set to "E00", skip From 9083d43d15ed53c575d48c71f6dbf31c8882b4f1 Mon Sep 17 00:00:00 2001 From: anton Date: Sat, 20 Mar 2021 14:48:52 +0500 Subject: [PATCH 192/503] gdb-server: fixed initialization of flash segments --- src/st-util/gdb-server.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/st-util/gdb-server.c b/src/st-util/gdb-server.c index e35e5c2e8..080d434b3 100644 --- a/src/st-util/gdb-server.c +++ b/src/st-util/gdb-server.c @@ -817,10 +817,11 @@ static int flash_add_block(stm32_addr_t addr, unsigned length, stlink_t *sl) { } struct flash_block* new = malloc(sizeof(struct flash_block)); - new->next = flash_root; + new->next = flash_root; new->addr = addr; new->length = length; - new->data = calloc(length, 1); + new->data = malloc(length); + memset(new->data, stlink_get_erased_pattern(sl), length); flash_root = new; return(0); From 7c5ac5908cf16d1b1b8c7d355ac6856461aab3c4 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sat, 20 Mar 2021 12:18:56 +0100 Subject: [PATCH 193/503] Updated travis CI config for macOS --- .travis.yml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/.travis.yml b/.travis.yml index fefafbaf1..5d2e5fbdf 100644 --- a/.travis.yml +++ b/.travis.yml @@ -129,6 +129,8 @@ jobs: ### macOS ### - os: osx env: BADGE=osx + osx_image: xcode12.2 + name: macOS 10.15.7 compiler: gcc addons: homebrew: @@ -138,6 +140,8 @@ jobs: - gtk+3 - os: osx env: BADGE=osx + osx_image: xcode12.2 + name: macOS 10.15.7 compiler: clang addons: homebrew: From 5e0a502df812495bfa96fa9116a19f1306152b17 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sat, 20 Mar 2021 15:44:09 +0100 Subject: [PATCH 194/503] General Project Update - Updated CHANGELOG.md - Updated README.md - [doc] Official STLINK-V3 support (Closes #820, Closes #1022, Closes #1025) - Updated list of contributors - Updated info on version support - Minor formatting fixes --- CHANGELOG.md | 3 ++ README.md | 18 +++---- contributors.txt | 1 + doc/compiling.md | 113 ++++++++++++++++++++--------------------- doc/version_support.md | 80 ++++++++++++++--------------- 5 files changed, 109 insertions(+), 106 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index cacd79eef..7ca94dbc8 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -7,6 +7,7 @@ Release date: (TBD) Features: - Added support for STM32H742/743/753 ([#671](https://github.com/stlink-org/stlink/pull/671), [#793](https://github.com/stlink-org/stlink/pull/793), [#823](https://github.com/stlink-org/stlink/pull/823), [#998](https://github.com/stlink-org/stlink/pull/998), [#1052](https://github.com/stlink-org/stlink/pull/1052)) +- Official support for STLINK-V3 programmers ([#820](https://github.com/stlink-org/stlink/pull/820), [#1022](https://github.com/stlink-org/stlink/pull/1022), [#1025](https://github.com/stlink-org/stlink/pull/1025)) - Added preliminary support for STM32L5x2 ([#904](https://github.com/stlink-org/stlink/pull/904), [#999](https://github.com/stlink-org/stlink/pull/999)) - Option bytes on the STM32F767 ZIT6 Nucleo-144 ([#968](https://github.com/stlink-org/stlink/pull/968), [#997](https://github.com/stlink-org/stlink/pull/997)) - Use SetConsoleCtrlHandler for Windows ([#1021](https://github.com/stlink-org/stlink/pull/1021)) @@ -32,6 +33,7 @@ Updates & changes: Fixes: +- Fixed old DFU serial number for STLINK programmers ([#417](https://github.com/stlink-org/stlink/pull/417), [#494](https://github.com/stlink-org/stlink/pull/494), [#1106](https://github.com/stlink-org/stlink/pull/1106)) - [regression] Changed timeout on flash write ([#787](https://github.com/stlink-org/stlink/pull/787), [#981](https://github.com/stlink-org/stlink/pull/981), [#987](https://github.com/stlink-org/stlink/pull/987)) - cmake compile failure with external `CMAKE_MODULE_PATH` set ([#962](https://github.com/stlink-org/stlink/pull/962)) - doc/man: Fixed installation directory ([#970](https://github.com/stlink-org/stlink/pull/970)) @@ -53,6 +55,7 @@ Fixes: - Fixed support for writing option bytes ([#1102](https://github.com/stlink-org/stlink/pull/1102)) - [doc] Corrected spelling mistake in bug report template ([#1103](https://github.com/stlink-org/stlink/pull/1103)) - Fixed support for STLINK/V1 programmer ([#1045](https://github.com/stlink-org/stlink/pull/1045), [#1105](https://github.com/stlink-org/stlink/pull/1105)) +- Fixed STM32WB55 reading DEBUG IDCODE from the wrong address ([#1100](https://github.com/stlink-org/stlink/pull/1100), [#1101](https://github.com/stlink-org/stlink/pull/1101)) # v1.6.1 diff --git a/README.md b/README.md index 8a8600947..7ddc78005 100644 --- a/README.md +++ b/README.md @@ -17,21 +17,24 @@ The stlink library and tools are licensed under the **[BSD-3 License](LICENSE.md ## Introduction -STLink is an open source toolset to program and debug STM32 devices and boards manufactured by STMicroelectronics. +stlink is an open source toolset to program and debug STM32 devices and boards manufactured by STMicroelectronics. It supports several so called STLINK programmer boards (and clones thereof) which use a microcontroller chip to translate commands from USB to JTAG/SWD. There are four generations available on the market which are _all_ supported by this toolset: - **STLINK/V1** _[obsolete as of 21-11-2019, continued support by this toolset] \*)_ - transport layer: SCSI passthru commands over USB - - stand-alone programmer and present on STM32VL Discovery boards + - stand-alone programmer + - on-board on STM32VL Discovery boards - **STLINK/V2** - transport layer: raw USB commands - - stand-alone programmer and present on STM32L Discovery and Nucleo boards + - stand-alone programmer + - on-board on STM32L Discovery and STM32 Nucleo boards - **STLINK/V2-1** - transport layer: raw USB commands - - present on some STM32 Nucleo boards -- **STLINK/V3** + - on-board on some STM32 Nucleo boards +- **STLINK-V3** - transport layer: raw USB commands - - stand-alone programmer + - stand-alone programmer (STLINK-V3SET, STLINK-V3MINI, STLINK-V3MODS) + - on-board on some STM32 Nucleo boards _\*)_ **Note: Support for the STLINK/V1 on macOS is limited to 10.14 - 10.15. Due to the deprecation and removal of macOS Kernel Extensions (KEXT) there will be no support for this programmer on macOS 11 or any later version.** @@ -52,9 +55,6 @@ Currently known working combinations of programmers and targets are listed in [d Supported operating systems are listed in [version_support.md](doc/version_support.md). -The `stlink` toolset continues to maintain backwards compatibility with the **STLINK/v1** programmer.
-Please note that on macOS this support is limited to versions 10.13 - 10.15. - ## Tutorial & HOWTO Our [tutorial](doc/tutorial.md) may help you along with some advanced tasks and additional info. diff --git a/contributors.txt b/contributors.txt index 38cc9cd42..88f1f0c89 100644 --- a/contributors.txt +++ b/contributors.txt @@ -113,6 +113,7 @@ Simon Wright Stany Marcel Stefan Misik Sven Wegener +Tarek Bochkati [tarek-bochkati] (STMicroelectronics) Timothy Lee [timothytylee] Tuomo Kaikkonen Theodore A. Roth diff --git a/doc/compiling.md b/doc/compiling.md index 07193f357..eef207f95 100644 --- a/doc/compiling.md +++ b/doc/compiling.md @@ -1,14 +1,14 @@ # Compiling from sources ## Microsoft Windows (10, 8.1) + ### Common Requirements On Windows users should ensure that the following software is installed: -* `git` (_optional, but recommended_) -* `cmake` (3.17.0 or later) -* `MinGW-w64` (7.0.0 or later) with GCC toolchain 8.1.0 - +- `git` (_optional, but recommended_) +- `cmake` (3.17.0 or later) +- `MinGW-w64` (7.0.0 or later) with GCC toolchain 8.1.0 ### Installation @@ -16,12 +16,14 @@ On Windows users should ensure that the following software is installed: 2. Install `cmake` from
Ensure that you add cmake to the $PATH system variable when following the instructions by the setup assistant. 3. Install - - _EITHER_: **MinGW-w64** from (mingw-w64-install.exe)
- - _OR_: **MSVC toolchain** from Visual Studio Build Tools 2019 + +- _EITHER_: **MinGW-w64** from (mingw-w64-install.exe)
+- _OR_: **MSVC toolchain** from Visual Studio Build Tools 2019 + 4. Create a new destination folder at a place of your choice 5. Open the command-line (cmd.exe) and execute `cd C:\$Path-to-your-destination-folder$\` 6. Fetch the project sourcefiles by running `git clone https://github.com/stlink-org/stlink.git`from the command-line (cmd.exe)
- or download the stlink zip-sourcefolder from the Release page on GitHub + or download the stlink zip-sourcefolder from the Release page on GitHub #### MSVC toolchain - minimal installation @@ -31,15 +33,19 @@ Visual Studio IDE is not necessary, only Windows SDK & build tools are required 2. Navigate through menus as follows (might change overtime) `All downloads > Tools for Visual Studio 2019 > Build Tools for Visual Studio 2019 > Download` + 3. Start downloaded executable. After Visual Studio Installer bootstraps and main window pops up, open `Individual Components` tab, and pick - - latest build tools (eg. `MSVC v142 - VS 2019 C++ x64/x86 build tools (v14.25)`) - - latest Windows SDK (eg. `Windows 10 SDK (10.0.18362.0)`) + +- latest build tools (eg. `MSVC v142 - VS 2019 C++ x64/x86 build tools (v14.25)`) +- latest Windows SDK (eg. `Windows 10 SDK (10.0.18362.0)`) + 4. After installation finishes, you can press `Launch` button in Visual Studio Installer's main menu. - Thus you can open `Developer Command Prompt for VS 2019`. It is `cmd.exe` instance with adjusted PATHs including eg. `msbuild`. - Alternatively, you can use `Developer Powershell for VS 2019` which is the same thing for `powershell.exe`. Both are available from Start menu. - Another option is to add `msbuild` to PATH manually. Its location should be `C:\Program Files (x86)\Microsoft Visual Studio\2019\BuildTools\MSBuild\Current\Bin`. Then, it should be available from any `powershell.exe` or `cmd.exe` session. ### Building + #### MinGW-w64 1. Use the command-line to move to the `scripts` directory within the source-folder: `cd stlink\scripts\` @@ -50,7 +56,6 @@ Per default the build script (currently) uses `C:\Program Files\mingw-w64\x86_64 When installing different toolchains make sure to update the path in the `mingw64-build.bat`.
This can be achieved by opening the .bat file with a common text editor. - #### MSVC toolchain 1. In a command prompt, change the directory to the folder where the stlink files were cloned (or unzipped) to. @@ -59,12 +64,15 @@ This can be achieved by opening the .bat file with a common text editor. This will create a solution file `stlink.sln` in the build folder. Now, you can build whole `stlink` suite using following command: + ``` msbuild /m /p:Configuration=Release stlink.sln ``` + Options: + - `/m` - compilation runs in parallel utilizing multiple cores -- `/p:Configuration=Release` - generates *Release*, optimized build. +- `/p:Configuration=Release` - generates _Release_, optimized build. Directory `\build\Release` contains final executables. (`st-util.exe` is located in `\build\src\gdbserver\Release`). @@ -79,25 +87,25 @@ It can be copied from: `\build\3rdparty\libusb-{version}\MS{arch}\ [ST-LINK drivers](https://www.st.com/en/development-tools/stsw-link009.html) are required for `stlink` to work. ## Linux + ### Common requirements Install the following packages from your package repository: -* `git` -* `gcc` or `clang` or `mingw32-gcc` or `mingw64-gcc` (C-compiler; very likely gcc is already present) -* `build-essential` (on Debian based distros (Debian, Ubuntu)) -* `cmake` (3.4.2 or later, use the latest version available from the repository) -* `rpm` (on Debian based distros (Debian, Ubuntu), needed for package build with `make package`) -* `libusb-1.0` -* `libusb-1.0-0-dev` (development headers for building) -* `libgtk-3-dev` (_optional_, needed for `stlink-gui`) -* `pandoc` (_optional_, needed for generating manpages from markdown) +- `git` +- `gcc` or `clang` or `mingw32-gcc` or `mingw64-gcc` (C-compiler; very likely gcc is already present) +- `build-essential` (on Debian based distros (Debian, Ubuntu)) +- `cmake` (3.4.2 or later, use the latest version available from the repository) +- `rpm` (on Debian based distros (Debian, Ubuntu), needed for package build with `make package`) +- `libusb-1.0` +- `libusb-1.0-0-dev` (development headers for building) +- `libgtk-3-dev` (_optional_, needed for `stlink-gui`) +- `pandoc` (_optional_, needed for generating manpages from markdown) or execute (Debian-based systems only): `apt-get install gcc build-essential cmake libusb-1.0 libusb-1.0-0-dev libgtk-3-dev pandoc` (Replace gcc with the intended C-compiler if necessary or leave out any optional package not needed.) - ### Installation 1. Open a new terminal console @@ -105,7 +113,6 @@ or execute (Debian-based systems only): `apt-get install gcc build-essential cma 3. Change to this directory: `cd ~/git` 4. Fetch the project sourcefiles by running `git clone https://github.com/stlink-org/stlink.git` - ### Building #### Installation: @@ -120,21 +127,19 @@ or execute (Debian-based systems only): `apt-get install gcc build-essential cma As an option you may also install to an individual user-defined folder e.g `$HOME` with `make install DESTDIR=$HOME`. - -#### Removal: +#### Removal: 1. Run `make uninstall` to perform a clean uninstall of the package from the system. 2. Run `make clean` to clean the build-folder within the project source and remove all compiled and linked files and libraries. - ### Cross-Building for Windows Install the following packages from your package repository: -* `mingw-w64` -* `mingw-w64-common` -* `mingw-w64-i686-dev` -* `mingw-w64-x86-64-dev` +- `mingw-w64` +- `mingw-w64-common` +- `mingw-w64-i686-dev` +- `mingw-w64-x86-64-dev` After following the steps for installation above, proceed with from the build dircetory itself: @@ -144,7 +149,6 @@ $ sudo sh ./cmake/packaging/windows/generate_binaries.sh The generated zip-packages can be found in the subdirectory `./build/dist`. - ### Set device access permissions and the role of udev By default most distributions don't allow access to USB devices. @@ -162,22 +166,21 @@ $ sudo udevadm trigger udev will now create device node files, e.g. `/dev/stlinkv3_XX`, `/dev/stlinkv2_XX`, `/dev/stlinkv1_XX`. - ### Special note on the use of STLink/V1 programmers (legacy): As the STLINKV1's SCSI emulation is somehow broken, the best advice possibly is to tell your operating system to completely ignore it.
Choose one of the following options _before_ connecting the device to your computer: -* `modprobe -r usb-storage && modprobe usb-storage quirks=483:3744:i` -* _OR_ - 1. `echo "options usb-storage quirks=483:3744:i" >> /etc/modprobe.conf` - 2. `modprobe -r usb-storage && modprobe usb-storage` -* _OR_ - 1. `cp stlink_v1.modprobe.conf /etc/modprobe.d` - 2. `modprobe -r usb-storage && modprobe usb-storage` - +- `modprobe -r usb-storage && modprobe usb-storage quirks=483:3744:i` +- _OR_ + 1. `echo "options usb-storage quirks=483:3744:i" >> /etc/modprobe.conf` + 2. `modprobe -r usb-storage && modprobe usb-storage` +- _OR_ + 1. `cp stlink_v1.modprobe.conf /etc/modprobe.d` + 2. `modprobe -r usb-storage && modprobe usb-storage` ## macOS + ### Common requirements The best and recommended way is to install a package manager for open source software, @@ -185,21 +188,20 @@ either [homebrew](https://brew.sh) or [MacPorts](https://www.macports.org/). Then install the following dependencies from the package repository: -* `git` -* `gcc` or `llvm` (for clang) (C-compiler) -* `cmake` -* `libusb` -* `gtk+3` or `gtk3` (_optional_, needed for `stlink-gui`) +- `git` +- `gcc` or `llvm` (for clang) (C-compiler) +- `cmake` +- `libusb` +- `gtk+3` or `gtk3` (_optional_, needed for `stlink-gui`) To do this with only one simple command, type: -* for homebrew: - - with gcc: `sudo brew install git gcc cmake libusb gtk+3` or - - with clang: `sudo brew install git llvm cmake libusb gtk+3` or -* for MacPorts: - - with gcc: `sudo port install git gcc10 cmake libusb gtk3` or - - with clang: `sudo port install git llvm-10 cmake libusb gtk3` - +- for homebrew: + - with gcc: `sudo brew install git gcc cmake libusb gtk+3` or + - with clang: `sudo brew install git llvm cmake libusb gtk+3` or +- for MacPorts: + - with gcc: `sudo port install git gcc10 cmake libusb gtk3` or + - with clang: `sudo port install git llvm-10 cmake libusb gtk3` ### Installation @@ -208,7 +210,6 @@ To do this with only one simple command, type: 3. Change to this directory: `cd ~/git` 4. Fetch the project sourcefiles by running `git clone https://github.com/stlink-org/stlink.git` - ### Building 1. Change into the project source directory: `cd stlink` @@ -217,14 +218,13 @@ To do this with only one simple command, type: 4. Run `make debug` to create the _Debug_ target (_optional_)
The debug target is only necessary in order to modify the sources and to run under a debugger. - ## Build options + ### Build using a different directory for shared libs To put the compiled shared libs into a different directory during installation, you can use the cmake option `cmake -DLIB_INSTALL_DIR:PATH="/usr/lib64" ..`. - ### Standard installation directories The cmake build system of this toolset includes `GNUInstallDirs` to define GNU standard installation directories. @@ -232,8 +232,7 @@ This module provides install directory variables as defined by the GNU Coding St Below are the preset default cmake options, which apply if none of these options are redefined: -* `-DCMAKE_INSTALL_SYSCONFDIR=/etc` -* `-DCMAKE_INSTALL_PREFIX=/usr/local` - +- `-DCMAKE_INSTALL_SYSCONFDIR=/etc` +- `-DCMAKE_INSTALL_PREFIX=/usr/local` Author: nightwalker-87 diff --git a/doc/version_support.md b/doc/version_support.md index eca491b79..1edf2e19c 100644 --- a/doc/version_support.md +++ b/doc/version_support.md @@ -23,52 +23,52 @@ NOTE: In order to use a STLINK/V1 programmer on macOS, versions 10.14 or 10.15 a ### Linux-/Unix-based: -| Operating System | libusb
version | cmake
version | gtk-3
version | Notes | -| -------------------------------- | ----------------------- | ------------------ | ----------------------------------------- | --------------------------------------------------- | --------------------------------------------------- | -| Alpine Edge | 1.0.23 | 3.17.0 | 3.99.0
gtk+3.0 | | -| ALT Linux Sisyphus | 1.0.23 | 3.17.0 | 3.24.18
libgtk+3 | | -| Arch Linux | 1.0.23 | 3.17.0 | 3.24.18
gtk3 | | -| Fedora Rawhide | 1.0.23 | 3.17.0 | 3.24.18
gtk3 | | named `libusbx`, but
`libusb`-codebase is used | -| KaOS | 1.0.23 | 3.17.0 | 3.24.18
gtk3 | | -| OpenMandriva Cooker | 1.0.23 | 3.17.0 | 3.24.18
libgtk+3.0
lib64gtk+3.0 | | -| PCLinuxOS | 1.0.23
lib64usb1.0 | 3.17.0 | 3.24.18
lib64gtk+3.0 | | -| Slackware Current | 1.0.23 | 3.17.0 | 3.24.18
gtk+3 | | -| Solus | 1.0.23 | 3.16.5 | 3.24.16
libgtk-3 | | -| Debian Sid | 1.0.23 | 3.16.3 | 3.24.18
libgtk-3 | | -| OpenMandriva Lx 4.1 | 1.0.23 | 3.16.3 | 3.24.13
libgtk+3.0
lib64gtk+3.0 | | -| Ubuntu 20.04 LTS (Focal Fossa) | 1.0.23 | 3.16.3 | 3.24.17
libgtk-3 | | -| openSUSE Tumbleweed | 1.0.23 | 3.16.2 | 3.24.16
gtk3 | | -| Alpine 3.11 | 1.0.23 | 3.15.5 | 3.24.13
gtk+3.0 | | -| Ubuntu 19.10 (Eoan Ermine) | 1.0.23 | 3.13.4 | 3.24.12
libgtk-3 | | -| Mageia Cauldron | 1.0.22 | 3.17.0 | 3.24.18
libgtk+3.0
lib64gtk+3.0 | | -| NetBSD 9.0 | 1.0.22 | 3.16.1 | 3.24.12
gtk+3 | | -| NetBSD 8.1 | 1.0.22 | 3.16.1 | 3.24.12
gtk+3 | | -| NetBSD 7.2 | 1.0.22 | 3.16.1 | _N/A_ | | -| Alpine 3.10 | 1.0.22 | 3.14.5 | 3.24.8
gtk+3.0 | | -| Fedora 31 | 1.0.22 | 3.14.5 | 3.24.12
gtk3 | named `libusbx`, but
`libusb`-codebase is used | -| Mageia 7.1 | 1.0.22 | 3.14.3 | 3.24.8
libgtk+3.0
lib64gtk+3.0 | | -| Fedora 30 | 1.0.22 | 3.14.2 | 3.24.8
gtk3 | named `libusbx`, but
`libusb`-codebase is used | -| Debian 10 (Buster) | 1.0.22 | 3.13.4 | 3.24.5
libgtk-3 | | -| Alpine 3.9 | 1.0.22 | 3.13.0 | 3.24.1
gtk+3.0 | | -| CentOS 8 | 1.0.22 | 3.11.4 | 3.22.30
gtk3 | named `libusbx`, but
`libusb`-codebase is used | -| openSUSE Leap 15.2 | 1.0.21 | 3.15.5 | 3.24.14
gtk3 | | -| openSUSE Leap 15.1 | 1.0.21 | 3.10.2 | 3.22.30
gtk3 | | -| Ubuntu 18.04 LTS (Bionic Beaver) | 1.0.21 | 3.10.2 | 3.22.30
libgtk-3 | | -| Debian 9 (Stretch) | 1.0.21 | 3.7.2 | 3.22.11
libgtk-3 | | -| Slackware 14.2 | **1.0.20** | 3.5.2 | 3.18.9
gtk+3 | | -| Ubuntu 16.04 LTS (Xenial Xerus) | **1.0.20** | 3.5.1 | 3.18.9
libgtk-3 | | -| OpenMandriva Lx 3.0 | **1.0.20** | **3.4.2** | 3.18.9
libgtk+3.0
lib64gtk+3.0 | | -| FreeBSD 13 | **1.0.16** - 1.0.18 | 3.15.5 | 3.24.10
gtk3 | linux_libusb-13.0r358841
(integrated) | -| FreeBSD 12 | **1.0.16** - 1.0.18 | 3.15.5 | 3.24.10
gtk3 | linux_libusb-11.0r261448_4
(integrated) | -| FreeBSD 11 | **1.0.16** - 1.0.18 | 3.15.5 | 3.24.10
gtk3 | linux_libusb-11.0r261448_4
(integrated) | +| Operating System | libusb
version | cmake
version | gtk-3
version | Notes | +| -------------------------------- | ----------------------- | ------------------ | ----------------------------------------- | ----------------------------------------------------------------------------- | +| Alpine Edge | 1.0.23 | 3.17.0 | 3.99.0
gtk+3.0 | | +| ALT Linux Sisyphus | 1.0.23 | 3.17.0 | 3.24.18
libgtk+3 | | +| Arch Linux | 1.0.23 | 3.17.0 | 3.24.18
gtk3 | | +| Fedora Rawhide | 1.0.23 | 3.17.0 | 3.24.18
gtk3 | named `libusbx`, but
`libusb`-codebase is used | +| KaOS | 1.0.23 | 3.17.0 | 3.24.18
gtk3 | | +| OpenMandriva Cooker | 1.0.23 | 3.17.0 | 3.24.18
libgtk+3.0
lib64gtk+3.0 | | +| PCLinuxOS | 1.0.23
lib64usb1.0 | 3.17.0 | 3.24.18
lib64gtk+3.0 | | +| Slackware Current | 1.0.23 | 3.17.0 | 3.24.18
gtk+3 | | +| Solus | 1.0.23 | 3.16.5 | 3.24.16
libgtk-3 | | +| Debian Sid | 1.0.23 | 3.16.3 | 3.24.18
libgtk-3 | | +| OpenMandriva Lx 4.1 | 1.0.23 | 3.16.3 | 3.24.13
libgtk+3.0
lib64gtk+3.0 | | +| Ubuntu 20.04 LTS (Focal Fossa) | 1.0.23 | 3.16.3 | 3.24.17
libgtk-3 | | +| openSUSE Tumbleweed | 1.0.23 | 3.16.2 | 3.24.16
gtk3 | | +| Alpine 3.11 | 1.0.23 | 3.15.5 | 3.24.13
gtk+3.0 | | +| Ubuntu 19.10 (Eoan Ermine) | 1.0.23 | 3.13.4 | 3.24.12
libgtk-3 | | +| Mageia Cauldron | 1.0.22 | 3.17.0 | 3.24.18
libgtk+3.0
lib64gtk+3.0 | | +| NetBSD 9.0 | 1.0.22 | 3.16.1 | 3.24.12
gtk+3 | | +| NetBSD 8.1 | 1.0.22 | 3.16.1 | 3.24.12
gtk+3 | | +| NetBSD 7.2 | 1.0.22 | 3.16.1 | _N/A_ | | +| Alpine 3.10 | 1.0.22 | 3.14.5 | 3.24.8
gtk+3.0 | | +| Fedora 31 | 1.0.22 | 3.14.5 | 3.24.12
gtk3 | named `libusbx`, but
`libusb`-codebase is used | +| Mageia 7.1 | 1.0.22 | 3.14.3 | 3.24.8
libgtk+3.0
lib64gtk+3.0 | | +| Fedora 30 | 1.0.22 | 3.14.2 | 3.24.8
gtk3 | named `libusbx`, but
`libusb`-codebase is used | +| Debian 10 (Buster) | 1.0.22 | 3.13.4 | 3.24.5
libgtk-3 | | +| Alpine 3.9 | 1.0.22 | 3.13.0 | 3.24.1
gtk+3.0 | | +| CentOS 8 | 1.0.22 | 3.11.4 | 3.22.30
gtk3 | named `libusbx`, but
`libusb`-codebase is used | +| openSUSE Leap 15.2 | 1.0.21 | 3.15.5 | 3.24.14
gtk3 | | +| openSUSE Leap 15.1 | 1.0.21 | 3.10.2 | 3.22.30
gtk3 | | +| Ubuntu 18.04 LTS (Bionic Beaver) | 1.0.21 | 3.10.2 | 3.22.30
libgtk-3 | | +| Debian 9 (Stretch) | 1.0.21 | 3.7.2 | 3.22.11
libgtk-3 | | +| Slackware 14.2 | 1.0.20 | 3.5.2 | 3.18.9
gtk+3 | | +| Ubuntu 16.04 LTS (Xenial Xerus) | 1.0.20 | 3.5.1 | 3.18.9
libgtk-3 | | +| OpenMandriva Lx 3.0x | 1.0.20 | **3.4.2** | 3.18.9
libgtk+3.0
lib64gtk+3.0 | | +| FreeBSD 13 | **1.0.16 - 1.0.18** | 3.15.5 | 3.24.10
gtk3 | linux_libusb-13.0r358841
LIBUSB_API_VERSION 0x01000102
(integrated) | +| FreeBSD 12 | **1.0.16 - 1.0.18** | 3.15.5 | 3.24.10
gtk3 | linux_libusb-13.0r358841
LIBUSB_API_VERSION 0x01000102
(integrated) | +| FreeBSD 11 | **1.0.16 - 1.0.18** | 3.15.5 | 3.24.10
gtk3 | linux_libusb-13.0r358841
LIBUSB_API_VERSION 0x01000102
(integrated) | ## Unsupported Operating Systems (as of Release v1.6.1) | Operating System | libusb
version | cmake
version | End of
OS-Support | Notes | | ------------------------------ | ------------------- | ------------------ | ---------------------- | --------------------------------------------------- | | CentOS 7 | 1.0.21 | **2.8.12.2** | | named `libusbx`, but
`libusb`-codebase is used | -| Debian 8 (Jessie) | 1.0.**19** | 3.**0.2** | Jun 2020 | -| Ubuntu 14.04 LTS (Trusty Tahr) | 1.0.**17** | **2.8.12.2** | Apr 2019 | +| Debian 8 (Jessie) | 1.0.19 | **3.0.2** | Jun 2020 | +| Ubuntu 14.04 LTS (Trusty Tahr) | 1.0.17 | **2.8.12.2** | Apr 2019 | | CentOS 6 | 1.0.**9** | **2.8.12.2** | Dec 2020 | named `libusbx`, but
`libusb`-codebase is used | | Slackware 14.1 | 1.0.**9** | **2.8.12** | | | Slackware 14.0 | 1.0.**9** | **2.8.8** | | From 7c7ce954045d9734198d7345477b94bcf58f770e Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 21 Mar 2021 14:17:35 +0100 Subject: [PATCH 195/503] Create codeql-analysis.yml Setup for code scanning alerts --- .github/workflows/codeql-analysis.yml | 67 +++++++++++++++++++++++++++ 1 file changed, 67 insertions(+) create mode 100644 .github/workflows/codeql-analysis.yml diff --git a/.github/workflows/codeql-analysis.yml b/.github/workflows/codeql-analysis.yml new file mode 100644 index 000000000..202867cfc --- /dev/null +++ b/.github/workflows/codeql-analysis.yml @@ -0,0 +1,67 @@ +# For most projects, this workflow file will not need changing; you simply need +# to commit it to your repository. +# +# You may wish to alter this file to override the set of languages analyzed, +# or to provide custom queries or build logic. +# +# ******** NOTE ******** +# We have attempted to detect the languages in your repository. Please check +# the `language` matrix defined below to confirm you have the correct set of +# supported CodeQL languages. +# +name: "CodeQL" + +on: + push: + branches: [ develop, master ] + pull_request: + # The branches below must be a subset of the branches above + branches: [ develop ] + schedule: + - cron: '23 20 * * 2' + +jobs: + analyze: + name: Analyze + runs-on: ubuntu-latest + + strategy: + fail-fast: false + matrix: + language: [ 'cpp' ] + # CodeQL supports [ 'cpp', 'csharp', 'go', 'java', 'javascript', 'python' ] + # Learn more: + # https://docs.github.com/en/free-pro-team@latest/github/finding-security-vulnerabilities-and-errors-in-your-code/configuring-code-scanning#changing-the-languages-that-are-analyzed + + steps: + - name: Checkout repository + uses: actions/checkout@v2 + + # Initializes the CodeQL tools for scanning. + - name: Initialize CodeQL + uses: github/codeql-action/init@v1 + with: + languages: ${{ matrix.language }} + # If you wish to specify custom queries, you can do so here or in a config file. + # By default, queries listed here will override any specified in a config file. + # Prefix the list here with "+" to use these queries and those in the config file. + # queries: ./path/to/local/query, your-org/your-repo/queries@main + + # Autobuild attempts to build any compiled languages (C/C++, C#, or Java). + # If this step fails, then you should remove it and run the build manually (see below) + - name: Autobuild + uses: github/codeql-action/autobuild@v1 + + # ℹ️ Command-line programs to run using the OS shell. + # 📚 https://git.io/JvXDl + + # ✏️ If the Autobuild fails above, remove it and uncomment the following three lines + # and modify them (or add more) to build your code if your project + # uses a compiled language + + #- run: | + # make bootstrap + # make release + + - name: Perform CodeQL Analysis + uses: github/codeql-action/analyze@v1 From ab6094a615f31653c1f0b355e05c5a29a338aa39 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 21 Mar 2021 14:26:10 +0100 Subject: [PATCH 196/503] Create cmake.yml Added Github Action - CMake Workflow Build and test a CMake based project. --- .github/workflows/cmake.yml | 46 +++++++++++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) create mode 100644 .github/workflows/cmake.yml diff --git a/.github/workflows/cmake.yml b/.github/workflows/cmake.yml new file mode 100644 index 000000000..005915e6e --- /dev/null +++ b/.github/workflows/cmake.yml @@ -0,0 +1,46 @@ +name: CMake + +on: [push] + +env: + # Customize the CMake build type here (Release, Debug, RelWithDebInfo, etc.) + BUILD_TYPE: Release + +jobs: + build: + # The CMake configure and build commands are platform agnostic and should work equally + # well on Windows or Mac. You can convert this to a matrix build if you need + # cross-platform coverage. + # See: https://docs.github.com/en/free-pro-team@latest/actions/learn-github-actions/managing-complex-workflows#using-a-build-matrix + runs-on: ubuntu-latest + + steps: + - uses: actions/checkout@v2 + + - name: Create Build Environment + # Some projects don't allow in-source building, so create a separate build directory + # We'll use this as our working directory for all subsequent commands + run: cmake -E make_directory ${{github.workspace}}/build + + - name: Configure CMake + # Use a bash shell so we can use the same syntax for environment variable + # access regardless of the host operating system + shell: bash + working-directory: ${{github.workspace}}/build + # Note the current convention is to use the -S and -B options here to specify source + # and build directories, but this is only available with CMake 3.13 and higher. + # The CMake binaries on the Github Actions machines are (as of this writing) 3.12 + run: cmake $GITHUB_WORKSPACE -DCMAKE_BUILD_TYPE=$BUILD_TYPE + + - name: Build + working-directory: ${{github.workspace}}/build + shell: bash + # Execute the build. You can specify a specific target with "--target " + run: cmake --build . --config $BUILD_TYPE + + - name: Test + working-directory: ${{github.workspace}}/build + shell: bash + # Execute tests defined by the CMake configuration. + # See https://cmake.org/cmake/help/latest/manual/ctest.1.html for more detail + run: ctest -C $BUILD_TYPE From 812bc6ed4fae1078f00616d217a7b91e3480fa0f Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 21 Mar 2021 14:58:45 +0100 Subject: [PATCH 197/503] Create c-cpp.yml Added Github Action - Make Workflow Build and test a C/C++ project using Make. --- .github/workflows/c-cpp.yml | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) create mode 100644 .github/workflows/c-cpp.yml diff --git a/.github/workflows/c-cpp.yml b/.github/workflows/c-cpp.yml new file mode 100644 index 000000000..e211e4e54 --- /dev/null +++ b/.github/workflows/c-cpp.yml @@ -0,0 +1,23 @@ +name: C/C++ CI + +on: + push: + branches: [ testing ] + pull_request: + branches: [ testing ] + +jobs: + build: + + runs-on: ubuntu-latest + + steps: + - uses: actions/checkout@v2 + - name: configure + run: ./configure + - name: make + run: make + - name: make check + run: make check + - name: make distcheck + run: make distcheck From c677eb2f4dfd669bec7c73f1a324e0624908968a Mon Sep 17 00:00:00 2001 From: anton Date: Tue, 23 Mar 2021 20:06:47 +0500 Subject: [PATCH 198/503] flash_loader: makefile simplification --- flashloaders/Makefile | 75 +++++++++++++++---------------------------- 1 file changed, 25 insertions(+), 50 deletions(-) diff --git a/flashloaders/Makefile b/flashloaders/Makefile index 3517e1499..d4ca4d22a 100644 --- a/flashloaders/Makefile +++ b/flashloaders/Makefile @@ -1,10 +1,7 @@ -# Note that according to the original GPLed code, compiling is noted to be -# as simple as gcc -c, this fails with my tests where this will lead to a wrong -# address read by the program. -# This makefile will save your time from dealing with compile errors -# Adjust CC if needed +# The flash loader code cannot be compiled by the system gcc. This +# makefile use arm-none-eabi-gcc for this purpose -CROSS_COMPILE ?= /opt/gcc-arm-none-eabi-6-2017-q2-update/bin/arm-none-eabi- +CROSS_COMPILE ?= arm-none-eabi- CC = $(CROSS_COMPILE)gcc OBJCOPY = $(CROSS_COMPILE)objcopy @@ -12,52 +9,30 @@ OBJCOPY = $(CROSS_COMPILE)objcopy XXD = xxd XXDFLAGS = -i -c 4 -CFLAGS_THUMB1 = -mcpu=Cortex-M0 -Tlinker.ld -ffreestanding -nostdlib -CFLAGS_THUMB2 = -mcpu=Cortex-M3 -Tlinker.ld -ffreestanding -nostdlib +CFLAGS_ARMV6_M = -mcpu=Cortex-M0 -Tlinker.ld -ffreestanding -nostdlib +CFLAGS_ARMV7_M = -mcpu=Cortex-M3 -Tlinker.ld -ffreestanding -nostdlib all: stm32vl.h stm32f0.h stm32lx.h stm32f4.h stm32f4lv.h stm32l4.h stm32f7.h stm32f7lv.h + -stm32f0.h: stm32f0.s - $(CC) stm32f0.s $(CFLAGS_THUMB1) -o stm32f0.o - $(OBJCOPY) -O binary stm32f0.o stm32f0.bin - $(XXD) $(XXDFLAGS) stm32f0.bin stm32f0.h - -stm32vl.h: stm32f0.s - $(CC) stm32f0.s $(CFLAGS_THUMB2) -o stm32vl.o - $(OBJCOPY) -O binary stm32vl.o stm32vl.bin - $(XXD) $(XXDFLAGS) stm32vl.bin stm32vl.h - -stm32lx.h: stm32lx.s - $(CC) stm32lx.s $(CFLAGS_THUMB2) -o stm32lx.o - $(OBJCOPY) -O binary stm32lx.o stm32lx.bin - $(XXD) $(XXDFLAGS) stm32lx.bin stm32lx.h - -stm32f4.h: stm32f4.s - $(CC) stm32f4.s $(CFLAGS_THUMB2) -o stm32f4.o - $(OBJCOPY) -O binary stm32f4.o stm32f4.bin - $(XXD) $(XXDFLAGS) stm32f4.bin stm32f4.h - -stm32f4lv.h: stm32f4lv.s - $(CC) stm32f4lv.s $(CFLAGS_THUMB2) -o stm32f4lv.o - $(OBJCOPY) -O binary stm32f4lv.o stm32f4lv.bin - $(XXD) $(XXDFLAGS) stm32f4lv.bin stm32f4lv.h - -stm32l4.h: stm32l4.s - $(CC) stm32l4.s $(CFLAGS_THUMB2) -o stm32l4.o - $(OBJCOPY) -O binary stm32l4.o stm32l4.bin - $(XXD) $(XXDFLAGS) stm32l4.bin stm32l4.h - -stm32f7.h: stm32f7.s - $(CC) stm32f7.s $(CFLAGS_THUMB2) -o stm32f7.o - $(OBJCOPY) -O binary stm32f7.o stm32f7.bin - $(XXD) $(XXDFLAGS) stm32f7.bin stm32f7.h - -stm32f7lv.h: stm32f7lv.s - $(CC) stm32f7lv.s $(CFLAGS_THUMB2) -o stm32f7lv.o - $(OBJCOPY) -O binary stm32f7lv.o stm32f7lv.bin - $(XXD) $(XXDFLAGS) stm32f7lv.bin stm32f7lv.h +%.h: %.bin + $(XXD) $(XXDFLAGS) $< $@ + +%.bin: %.o + $(OBJCOPY) -O binary $< $@ + rm $< + +# separate rule for STM32F0 +stm32f0.o: stm32f0.s + $(CC) stm32f0.s $(CFLAGS_ARMV6_M) -o stm32f0.o + +# separate rule for STM32F1/F3 +stm32vl.o: stm32f0.s + $(CC) stm32f0.s $(CFLAGS_ARMV7_M) -o stm32vl.o + +# generic rule for all other ARMv7-M +%.o: *.s + $(CC) $< $(CFLAGS_ARMV7_M) -o $@ clean: - rm *.o - rm *.bin - rm *.h + rm -f *.h From ee2c9f508e3eaa39d72dd8d41dfe642800a4946e Mon Sep 17 00:00:00 2001 From: anton Date: Tue, 23 Mar 2021 22:33:00 +0500 Subject: [PATCH 199/503] Core ID reading rework --- inc/stm32.h | 7 ++++--- src/common.c | 41 ++++++++++++++++++++++++++++++++--------- src/stlink-lib/reg.h | 9 ++++++--- 3 files changed, 42 insertions(+), 15 deletions(-) diff --git a/inc/stm32.h b/inc/stm32.h index ca56a12f5..7d60ab5de 100644 --- a/inc/stm32.h +++ b/inc/stm32.h @@ -8,9 +8,10 @@ #define STM32_H /* Cortex core ids */ -#define STM32VL_CORE_ID 0x1ba01477 -#define STM32F7_CORE_ID 0x5ba02477 -#define STM32H7_CORE_ID 0x6ba02477 // STM32H7 JTAG ID Code (RM0433 pg3065) +#define STM32VL_CORE_ID 0x1ba01477 +#define STM32F7_CORE_ID 0x5ba02477 +#define STM32H7_CORE_ID 0x6ba02477 // STM32H7 SWD ID Code +#define STM32H7_CORE_ID_JTAG 0x6ba00477 // STM32H7 JTAG ID Code (RM0433 pg3065) /* Constant STM32 memory map figures */ #define STM32_FLASH_BASE ((uint32_t)0x08000000) diff --git a/src/common.c b/src/common.c index 5f2746e3d..b5bb67e9e 100644 --- a/src/common.c +++ b/src/common.c @@ -1229,20 +1229,43 @@ int stlink_chip_id(stlink_t *sl, uint32_t *chip_id) { if (stlink_read_debug32(sl, STLINK_REG_CM3_CPUID, &cpu_id)) cpu_id = 0; - // If the chip is an H7, read the chipid from the new address - if (sl->core_id == STM32H7_CORE_ID && cpu_id == STLINK_REG_CMx_CPUID_CM7) { + /* + * the chip_id register in the reference manual have + * DBGMCU_IDCODE / DBG_IDCODE name + * + */ + + uint32_t part_no = STLINK_REG_CM3_CPUID_PARTNO(cpu_id); + if ((sl->core_id == STM32H7_CORE_ID || + sl->core_id == STM32H7_CORE_ID_JTAG) && + part_no == STLINK_REG_CMx_CPUID_PARTNO_CM7) { // STM32H7 chipid in 0x5c001000 (RM0433 pg3189) ret = stlink_read_debug32(sl, 0x5c001000, chip_id); - } - - if (*chip_id == 0) { + } else if (part_no == STLINK_REG_CMx_CPUID_PARTNO_CM0) { + // STM32F0 (RM0091, pg914; RM0360, pg713) + // STM32L0 (RM0377, pg813; RM0367, pg915; RM0376, pg917) + // STM32G0 (RM0444, pg1367) + ret = stlink_read_debug32(sl, 0x40015800, chip_id); + } else if (part_no == STLINK_REG_CMx_CPUID_PARTNO_CM33) { + // STM32L5 (RM0438, pg2157) + ret = stlink_read_debug32(sl, 0xE0044000, chip_id); + } else /* СM3, СM4, CM7 */ { // default chipid address + + // STM32F1 (RM0008, pg1087; RM0041, pg681) + // STM32F2 (RM0033, pg1326) + // STM32F3 (RM0316, pg1095; RM0313, pg874) + // STM32F7 (RM0385, pg1676; RM0410, pg1912) + // STM32L1 (RM0038, pg861) + // STM32L4 (RM0351, pg1840; RM0394, pg1560) + // STM32G4 (RM0440, pg2086) + // STM32WB (RM0434, pg1406) ret = stlink_read_debug32(sl, 0xE0042000, chip_id); - } - if (*chip_id == 0) { - // Try Corex M0 DBGMCU_IDCODE register address - ret = stlink_read_debug32(sl, 0x40015800, chip_id); + // Fix chip_id for F4 rev A errata, read CPU ID, as CoreID is the same for F2/F4 + if (*chip_id == 0x411 && (cpu_id & 0xfff0) == 0xc240) { + *chip_id = 0x413; + } } return(ret); diff --git a/src/stlink-lib/reg.h b/src/stlink-lib/reg.h index 5a796d7e1..73f608cb6 100644 --- a/src/stlink-lib/reg.h +++ b/src/stlink-lib/reg.h @@ -3,9 +3,12 @@ #define STLINK_REG_CM3_CPUID 0xE000ED00 -#define STLINK_REG_CMx_CPUID_CM0 0x410CC200 -#define STLINK_REG_CMx_CPUID_CM3 0x412FC230 -#define STLINK_REG_CMx_CPUID_CM7 0x411FC272 +#define STLINK_REG_CM3_CPUID_PARTNO(cpuid) ((cpuid)&STLINK_REG_CMx_CPUID_PARTNO_MASK) +#define STLINK_REG_CMx_CPUID_PARTNO_MASK 0xFFF0 +#define STLINK_REG_CMx_CPUID_PARTNO_CM0 0xC200 +#define STLINK_REG_CMx_CPUID_PARTNO_CM3 0xC230 +#define STLINK_REG_CMx_CPUID_PARTNO_CM7 0xC270 +#define STLINK_REG_CMx_CPUID_PARTNO_CM33 0xD210 #define STLINK_REG_CM3_FP_CTRL 0xE0002000 // Flash Patch Control Register From 229c721189587760db5509c59b3c02e93e7035c8 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Wed, 24 Mar 2021 23:26:38 +0100 Subject: [PATCH 200/503] General Project Update - Added basic security policy - Updated info on version support for macOS - Updated tutorial.md > Added reference for st-info --probe command > Added section on unknown chip id error (Closes #107, Closes #568, Closes #669) > Added information on HW reset pin issue (Closes #220, Closes #238) --- CHANGELOG.md | 18 ++++++++---- SECURITY.md | 20 +++++++++++++ doc/tutorial.md | 67 ++++++++++++++++++++++++++++++++---------- doc/version_support.md | 8 ++--- 4 files changed, 87 insertions(+), 26 deletions(-) create mode 100644 SECURITY.md diff --git a/CHANGELOG.md b/CHANGELOG.md index 7ca94dbc8..e3f8e13b5 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -2,12 +2,13 @@ # v1.6.2 -Release date: (TBD) +Release date: (planned H1/2021) Features: +- Extended support for STM32H7 & rework of software reset ([#532](https://github.com/stlink-org/stlink/pull/532), [#1059](https://github.com/stlink-org/stlink/pull/1059), [#1063](https://github.com/stlink-org/stlink/pull/1063), [#1071](https://github.com/stlink-org/stlink/pull/1071)) - Added support for STM32H742/743/753 ([#671](https://github.com/stlink-org/stlink/pull/671), [#793](https://github.com/stlink-org/stlink/pull/793), [#823](https://github.com/stlink-org/stlink/pull/823), [#998](https://github.com/stlink-org/stlink/pull/998), [#1052](https://github.com/stlink-org/stlink/pull/1052)) -- Official support for STLINK-V3 programmers ([#820](https://github.com/stlink-org/stlink/pull/820), [#1022](https://github.com/stlink-org/stlink/pull/1022), [#1025](https://github.com/stlink-org/stlink/pull/1025)) +- Official support for STLINK-V3 programmers (commit [#5e0a502](https://github.com/stlink-org/stlink/commit/5e0a502df812495bfa96fa9116a19f1306152b17), [#820](https://github.com/stlink-org/stlink/pull/820), [#1022](https://github.com/stlink-org/stlink/pull/1022), [#1025](https://github.com/stlink-org/stlink/pull/1025)) - Added preliminary support for STM32L5x2 ([#904](https://github.com/stlink-org/stlink/pull/904), [#999](https://github.com/stlink-org/stlink/pull/999)) - Option bytes on the STM32F767 ZIT6 Nucleo-144 ([#968](https://github.com/stlink-org/stlink/pull/968), [#997](https://github.com/stlink-org/stlink/pull/997)) - Use SetConsoleCtrlHandler for Windows ([#1021](https://github.com/stlink-org/stlink/pull/1021)) @@ -15,12 +16,13 @@ Features: - `st-util`: Add specialized memory map for STM32H7 devices ([#1060](https://github.com/stlink-org/stlink/pull/1060)) - Support for STM32F4 option bytes ([#1062](https://github.com/stlink-org/stlink/pull/1062)) - Link for WIN32 & APPLE with stlink-static ([#1069](https://github.com/stlink-org/stlink/pull/1069)) -- Extended support for STM32H7 ([#1059](https://github.com/stlink-org/stlink/pull/1059), [#1063](https://github.com/stlink-org/stlink/pull/1063), [#1071](https://github.com/stlink-org/stlink/pull/1071)) - ITM functionality for STLink/V2 and STM32Fxx chipsets ([#136](https://github.com/stlink-org/stlink/pull/136), [#179](https://github.com/stlink-org/stlink/pull/179), [#815](https://github.com/stlink-org/stlink/pull/815), [#1072](https://github.com/stlink-org/stlink/pull/1072)) - Included ITM functionality for building with MSVC ([#1080](https://github.com/stlink-org/stlink/pull/1080)) Updates & changes: +- [doc] Added tutorial section on unknown chip id error ([#107](https://github.com/stlink-org/stlink/pull/107), [#568](https://github.com/stlink-org/stlink/pull/568), +- [doc] Updated documentation on target resetting ([#261](https://github.com/stlink-org/stlink/pull/261), [#533](https://github.com/stlink-org/stlink/pull/533), [#1107](https://github.com/stlink-org/stlink/pull/1107)) - [doc] Added note on `(gdb) run` command (commit [#03793d4](https://github.com/stlink-org/stlink/commit/03793d42b6078344a9ef8ad55f1d5d0fc19e486e), [#267](https://github.com/stlink-org/stlink/pull/267)) - [doc] `st-flash --reset` parameter (one solution for #356) ([#642](https://github.com/stlink-org/stlink/pull/642)) - [refactoring] General maintenance ([#864](https://github.com/stlink-org/stlink/pull/864), [#976](https://github.com/stlink-org/stlink/pull/976), [#978](https://github.com/stlink-org/stlink/pull/978)) @@ -33,6 +35,7 @@ Updates & changes: Fixes: +- Flash loader rework ([#356](https://github.com/stlink-org/stlink/pull/356), [#556](https://github.com/stlink-org/stlink/pull/556), [#593](https://github.com/stlink-org/stlink/pull/593), [#607](https://github.com/stlink-org/stlink/pull/607), [#612](https://github.com/stlink-org/stlink/pull/612), [#638](https://github.com/stlink-org/stlink/pull/638), [#661](https://github.com/stlink-org/stlink/pull/661), [#690](https://github.com/stlink-org/stlink/pull/690), [#979](https://github.com/stlink-org/stlink/pull/979), [#1043](https://github.com/stlink-org/stlink/pull/1043), [#1054](https://github.com/stlink-org/stlink/pull/1054), [#1105](https://github.com/stlink-org/stlink/pull/1105), [#1113](https://github.com/stlink-org/stlink/pull/1113)) - Fixed old DFU serial number for STLINK programmers ([#417](https://github.com/stlink-org/stlink/pull/417), [#494](https://github.com/stlink-org/stlink/pull/494), [#1106](https://github.com/stlink-org/stlink/pull/1106)) - [regression] Changed timeout on flash write ([#787](https://github.com/stlink-org/stlink/pull/787), [#981](https://github.com/stlink-org/stlink/pull/981), [#987](https://github.com/stlink-org/stlink/pull/987)) - cmake compile failure with external `CMAKE_MODULE_PATH` set ([#962](https://github.com/stlink-org/stlink/pull/962)) @@ -45,8 +48,10 @@ Fixes: - Fix for `mmap() size_t overflow` in `st-flash` ([#988](https://github.com/stlink-org/stlink/pull/988), [#989](https://github.com/stlink-org/stlink/pull/989)) - [regression] `stlink-gui` installation issue on Ubuntu-18.04 ([#1001](https://github.com/stlink-org/stlink/pull/1001), [#1004](https://github.com/stlink-org/stlink/pull/1004), [#1006](https://github.com/stlink-org/stlink/pull/1006)) - `st-util`: wrong register values passed to `gdb` (STLink/V2) ([#1002](https://github.com/stlink-org/stlink/pull/1002), [#1011](https://github.com/stlink-org/stlink/pull/1011), [#1026](https://github.com/stlink-org/stlink/pull/1026), [#1027](https://github.com/stlink-org/stlink/pull/1027), [#1064](https://github.com/stlink-org/stlink/pull/1064), [#1065](https://github.com/stlink-org/stlink/pull/1065)) +- GDB: Fixed problems with target description ([#1013](https://github.com/stlink-org/stlink/pull/1013), [#1088](https://github.com/stlink-org/stlink/pull/1088), [#1109](https://github.com/stlink-org/stlink/pull/1109)) - [doc] Fixed wrong path for `rules.d` folder ([#1020](https://github.com/stlink-org/stlink/pull/1020)) - Use vl flashloader for all STM32F1 series ([#1041](https://github.com/stlink-org/stlink/pull/1041), [#1044](https://github.com/stlink-org/stlink/pull/1044)) +- Fixed support for STLINK/V1 programmer ([#1045](https://github.com/stlink-org/stlink/pull/1045), [#1105](https://github.com/stlink-org/stlink/pull/1105)) - st-util v1.6.1 does not recognize option --freq (commit [#e576768](https://github.com/stlink-org/stlink/commit/e5767681f14de9851aa970a9299930ca68b2ed92), [#1055](https://github.com/stlink-org/stlink/pull/1055)) - Fixed `gettimeofday` for MSVC ([#1074](https://github.com/stlink-org/stlink/pull/1074)) - Bugfixes for compilation with clang ([#1076](https://github.com/stlink-org/stlink/pull/1076), [#1078](https://github.com/stlink-org/stlink/pull/1078)) @@ -54,7 +59,6 @@ Fixes: - [regression] Flash_loader: increased wait rounds for slow boards ([#1085](https://github.com/stlink-org/stlink/pull/1085)) - Fixed support for writing option bytes ([#1102](https://github.com/stlink-org/stlink/pull/1102)) - [doc] Corrected spelling mistake in bug report template ([#1103](https://github.com/stlink-org/stlink/pull/1103)) -- Fixed support for STLINK/V1 programmer ([#1045](https://github.com/stlink-org/stlink/pull/1045), [#1105](https://github.com/stlink-org/stlink/pull/1105)) - Fixed STM32WB55 reading DEBUG IDCODE from the wrong address ([#1100](https://github.com/stlink-org/stlink/pull/1100), [#1101](https://github.com/stlink-org/stlink/pull/1101)) # v1.6.1 @@ -179,8 +183,8 @@ Major changes and added features: Updates and fixes: -- Fixed `unkown chip id`, piped output and `st-util -v` ([#107](https://github.com/stlink-org/stlink/pull/107), [#665](https://github.com/stlink-org/stlink/pull/665), [#763](https://github.com/stlink-org/stlink/pull/763)) - Fixed an issue with versioning stuck at 1.4.0 for versions cloned with git ([#563](https://github.com/stlink-org/stlink/pull/563), [#762](https://github.com/stlink-org/stlink/pull/762), [#772](https://github.com/stlink-org/stlink/pull/772)) +- Fixed `unkown chip id`, piped output and `st-util -v` ([#665](https://github.com/stlink-org/stlink/pull/665), [#763](https://github.com/stlink-org/stlink/pull/763)) - Updated STM32F3xx chip ID that covers a few different devices ([#685](https://github.com/stlink-org/stlink/pull/685), [#758](https://github.com/stlink-org/stlink/pull/758)) - Made udev rules and modprobe conf installation optional ([#741](https://github.com/stlink-org/stlink/pull/741)) - Fixed case when `__FILE__` doesn't contain either `/` nor `\\` ([#745](https://github.com/stlink-org/stlink/pull/745)) @@ -385,12 +389,14 @@ Updates and fixes: - Fixed STM32F2xx memory map (Nicolas Schodet) - Memory map for STM32F42xxx and STM32F43xxx devices (Craig Lilley) - Stm32l0x flash loader (Robin Kreis) -- Use libusb synchronous api ([#194](https://github.com/stlink-org/stlink/pull/194), [#374](https://github.com/stlink-org/stlink/pull/374)) +- Modified determination of erased byte pattern when flashing ([#193](https://github.com/stlink-org/stlink/pull/193), [#377](https://github.com/stlink-org/stlink/pull/377)) +- Use libusb synchronous api ([#194](https://github.com/stlink-org/stlink/pull/194), [#225](https://github.com/stlink-org/stlink/pull/225), [#374](https://github.com/stlink-org/stlink/pull/374)) - Fixed segfault when programmer is already busy and `NULL` pointers are in the list ([#256](https://github.com/stlink-org/stlink/pull/256), [#394](https://github.com/stlink-org/stlink/pull/394)) - Fixed issue where "unknown chip id!" was seen every other time ([#352](https://github.com/stlink-org/stlink/pull/352), [#367](https://github.com/stlink-org/stlink/pull/367), [#381](https://github.com/stlink-org/stlink/pull/381)) - Send F4 memory-map and features for STM32F429 ([#188](https://github.com/stlink-org/stlink/pull/188), [#196](https://github.com/stlink-org/stlink/pull/196), [#250](https://github.com/stlink-org/stlink/pull/250), [#251](https://github.com/stlink-org/stlink/pull/251)) (Release v1.1.0) - Added AHB3 Peripherals definition for STM32F4 ([#218](https://github.com/stlink-org/stlink/pull/218), [#288](https://github.com/stlink-org/stlink/pull/288)) (Release v1.1.0) - Reset: st-flash does not work when CPU is in sleep mode ([#62](https://github.com/stlink-org/stlink/pull/62)) (Release v1.0.0) +- Ensure USB device search succeeds if the matched device is at index 0 ([#126](https://github.com/stlink-org/stlink/pull/126), [#151](https://github.com/stlink-org/stlink/pull/151)) (Release v1.0.0) - Corrected flash size register address for STM32F2 devices ([#278](https://github.com/stlink-org/stlink/pull/278)) (Release v1.0.0) Chip support added for: diff --git a/SECURITY.md b/SECURITY.md new file mode 100644 index 000000000..caa2740db --- /dev/null +++ b/SECURITY.md @@ -0,0 +1,20 @@ +# Security Policy + +## Supported Versions + +The following versions of the stlink toolset are currently being supported.
As this is a development toolset, please note that bugfixes will only be applied to the latest version. + +| Version | Supported | +| ------- | ------------------ | +| develop | :white_check_mark: | +| 1.6.x | :white_check_mark: | +| 1.5.x | :x: | +| 1.4.0 | :x: | +| 1.3.x | :x: | +| 1.2.0 | :x: | +| 1.1.0 | :x: | +| 1.0.0 | :x: | + +## Reporting a Vulnerability + +Detected vulnerabilities in the toolset should be reported by opening a regular bugreport issue. diff --git a/doc/tutorial.md b/doc/tutorial.md index d4cf89ce2..8b1220747 100644 --- a/doc/tutorial.md +++ b/doc/tutorial.md @@ -2,15 +2,16 @@ ## Available tools and options -| Option | Tool | Description | Available
since | -| --------------------- | ------------------------------------ | ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | -------------------- | -| --flash=n[k][m] | st-flash | One can specify `--flash=128k` for example, to override the default value of 64k
for the STM32F103C8T6 to assume 128k of flash being present. This option accepts
decimal (128k), octal 0200k, or hex 0x80k values. Leaving the multiplier out is
equally valid, e.g.: `--flash=0x20000`. The size may be followed by an optional "k"
or "m" to multiply the given value by 1k (1024) or 1M respectively. | v1.4.0 | -| --freq=n[k][m] | st-flash | The frequency of the SWD/JTAG interface can be specified, to override the default
1800 kHz configuration. This option solely accepts decimal values (5K or 1.8M) with
the unit `Hz` being left out. Valid frequencies are: `5K, 15K, 25K, 50K, 100K,`
`125K, 240K, 480K, 950K, 1200K(1.2M), 1800K(1.8M), 4000K(4M)`. | v1.6.1 | -| --opt | st-flash | Optimisation can be enabled in order to skip flashing empty (0x00 or 0xff) bytes at
the end of binary file. This may cause some garbage data left after a flash operation.
This option was enabled by default in earlier releases. | v1.6.1 | -| --reset | st-flash | Trigger a reset both before and after flashing. The default use the hardware reset
through `NRST` pin. The software system reset is used if the hardware reset failed
(`NRST` pin not connected). | v1.0.0 | -| --connect-under-reset | st-flash | Connect under reset. Option makes it possible to connect to the device before code
executing. This is useful when the target contains a code that go device to sleep,
disables of debug pins or other special code. | v1.6.1 | -| --version | st-info
st-flash
st-util | Print version information. | | -| --help | st-flash
st-util | Print list of available commands. _(To be added to this table.)_ | | +| Option | Tool | Description | Available
since | +| --------------------- | ---------------------------------- | ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ | -------------------- | +| --flash=n[k][m] | st-flash | One can specify `--flash=128k` for example, to override the default value of 64k for the STM32F103C8T6
to assume 128k of flash being present. This option accepts decimal (128k), octal 0200k, or hex 0x80k values.
Leaving the multiplier out is equally valid, e.g.: `--flash=0x20000`. The size may be followed by an optional
"k" or "m" to multiply the given value by 1k (1024) or 1M respectively. | v1.4.0 | +| --freq=n[k][m] | st-flash | The frequency of the SWD/JTAG interface can be specified, to override the default 1800 kHz configuration.
This option solely accepts decimal values (5K or 1.8M) with the unit `Hz` being left out. Valid frequencies are:
`5K, 15K, 25K, 50K, 100K, 125K, 240K, 480K, 950K, 1200K(1.2M), 1800K(1.8M), 4000K(4M)`. | v1.6.1 | +| --opt | st-flash | Optimisation can be enabled in order to skip flashing empty (0x00 or 0xff) bytes at the end of binary file.
This may cause some garbage data left after a flash operation. This option was enabled by default in earlier releases. | v1.6.1 | +| --reset | st-flash | Trigger a reset both before and after flashing. The default uses the hardware reset through `NRST` pin.
The software reset is used if the hardware reset failed (`NRST` pin not connected). | v1.0.0 | +| --connect-under-reset | st-flash | Connect under reset. Option makes it possible to connect to the device before code execution. This is useful
when the target contains code that lets the device go to sleep, disables debug pins or other special code. | v1.6.1 | +| --probe | st-info | Display hardware information about the connected programmer and target MCU. | v1.2.0 | +| --version | st-info
st-flash
st-util | Print version information. | v1.3.0 | +| --help | st-flash
st-util | Print list of available commands. | | ### st-flash: Checksum for binary files @@ -102,17 +103,52 @@ Check your hardware and try to identify what you have in front of you before ass Please let us know, if you come across any further websites or tutorials that help to identify STM32 fake chips so we can list them here to help others. ---- +### c) Appearance of the warning message `WARN src/common.c: unknown chip id!` + +The chip ID is the main identifier for STM32 MCU and their specific type and provides primary information on flash and SRAM architecture. +This so called `DBGMCU_IDCODE` register is allocated either at memory address `0xE0042000` or `0x40015800`. + +A failure of chip identification results in the error `WARN src/common.c: unknown chip id!`. +There are different variants of this message that refer to different issues: + +- `unknown chip id! 0` --> _currently unknown_ +- `unknown chip id! 0x1a` --> _currently unknown_ +- `unknown chip id! 0x001f` --> _currently unknown_ +- `unknown chip id! 0x3e8` --> _currently unknown_ +- `unknown chip id! 0xa05f0000` --> _currently unknown_ +- `unknown chip id! 0x3748` --> A target chip / board cannot be detected. + 1. No target is connected --> In this case `st-info --probe` displays `chip id 0x0748` with STLINK/V2 and `chip id 0x03e8` with STLINK-V3. + 2. The chip is connected but has gone into an undefined state of operation where the SWD pins are unresponsive. --> Try to use `--connect-under-reset` while pressing the reset button on the target board. + 3. A firmware-issue prevents the programmer from normal operation. --> Ensure that your programmer runs the latest firmware version and consider to upgrade any older version by using the official firmware upgrade tool provided by STMicroelectronics. +- `unknown chip id! 0xe0042000` --> The memory register holding the information on the chip ID could not be read. The following problems may lead to this case: + 1. This problem is caused by the SWDIO and SWCLK being configured for other purpose (GPIO, etc) other than Serial Wire configuration or Jtag --> A possible solution to this is to short the `BOOT0` pin with `VDD` (1) and to reset the chip / board by the execuing `st-flash erase` in order to return the MCU back to normal operation. Afterwards `BOOT0` should be set back to `GND` (0). + 2. There is a hardware defect in the connection between the MCU and the used programmer (solder points, cables, connectors). + +### d) Understanding hardware and software reset functionality for `st-flash` and reset-related device recovery + +Typically a reset signal is sent via the reset pin `NRST`. Using `st-flash` for flashing results in the following behaviour: -( Content below is currently unrevised and may be outdated as of Apr 2020. ) +- without the `--reset` option: `st-flash write` results in one reset signal on the `NRST` line +- with the `--reset` option: `st-flash write --reset` results in two subsequent reset signals on the `NRST` line -# Using STM32 discovery kits with open source tools +Depending on the used programmer the hardware reset line is not always connected. +This is especially the case for low-cost STLINK/V2 clone programmers. +Here the SWD connector consists of only 4 pins: `VCC`, `SWCLK`, `GND` and `SWDATA`. -This guide details the use of STMicroelectronics STM32 discovery kits in an open source environment. +When the physical reset line `NRST` is not connected, a reset is initiated by software via `SWD_SWDIO/JTAG_TMS` (software reset). +Just as mentioned above, flashing is possible here eiher with and without the `--reset` option. -## Installing a GNU toolchain +Configuring the STM32 pin `JTAG_TMS/SWD_SWDIO` as an output now also prevents the SWD interface from flashing and resetting the device. +In consequence this constellation typically requires a _hard reset_ to allow for the ST-Link/V2 programmer to reconnect to the target at all. -Any toolchain supporting the cortex m3 should do. +As soon as the device is in DFU mode, the `JTAG_TMS/SWD_SWDIO` pin is left in the default state with all JTAG pins available. +Here flashing of the device is now possible with and without the `--reset` option. + +The debug command `(gdb) monitor jtag_reset` sends a _hard reset_ signal via the `NRST` pin to reset the device and allows for flashing it (again). + +--- + +( Content below is currently unrevised and may be outdated as of Mar 2021. ) ## Using the GDB server @@ -201,7 +237,6 @@ Of course, you can use this instead of the gdb server, if you prefer. Just remember to use the “.bin” image, rather than the .elf file. ``` - # write blink.bin into FLASH $> [sudo] ./st-flash write fancy_blink.bin 0x08000000 ``` diff --git a/doc/version_support.md b/doc/version_support.md index 1edf2e19c..5d2cdd375 100644 --- a/doc/version_support.md +++ b/doc/version_support.md @@ -14,10 +14,10 @@ Thus no user interaction regarding libusb is necessary. ### Apple macOS -| Package Repository | libusb
version | cmake
version | gtk-3
version | Supported macOS versions | -| ------------------ | ------------------- | ------------------ | ------------------ | -------------------------------------- | -| homebrew | 1.0.23 | 3.17.0 | 3.24.18
gtk+3 | 10.12 (Sierra)- 10.15 (Catalina) | -| MacPorts | 1.0.23 | 3.17.0 | 3.24.18
gtk3 | 10.6 (Snow Leopard) - 10.15 (Catalina) | +| Package Repository | libusb
version | cmake
version | gtk-3
version | Supported macOS versions | +| ------------------ | ------------------- | ------------------ | ------------------ | ------------------------ | +| homebrew | 1.0.23 | 3.17.0 | 3.24.18
gtk+3 | 10.9 - 10.15 | +| MacPorts | 1.0.23 | 3.17.0 | 3.24.18
gtk3 | 10.4 - 10.15 | NOTE: In order to use a STLINK/V1 programmer on macOS, versions 10.14 or 10.15 are required. From b387c93ee007a2bde37daba8198a2108ec9704e5 Mon Sep 17 00:00:00 2001 From: anton Date: Thu, 25 Mar 2021 19:25:33 +0500 Subject: [PATCH 201/503] Extended set of command line arguments st-info: added --freq, --hot-plug and --connect-under-reset to probe st-util: added --freq --- doc/tutorial.md | 7 ++-- src/st-flash/flash.c | 11 +++--- src/st-flash/flash.h | 2 +- src/st-flash/flash_opts.c | 57 ++++++++---------------------- src/st-info/info.c | 74 +++++++++++++++++++++------------------ src/st-util/gdb-server.c | 36 ++++++++++++------- src/stlink-lib/helper.c | 14 ++++++++ src/stlink-lib/helper.h | 2 ++ src/stlink-lib/usb.c | 19 +++++----- src/stlink-lib/usb.h | 12 +++++-- 10 files changed, 122 insertions(+), 112 deletions(-) diff --git a/doc/tutorial.md b/doc/tutorial.md index 8b1220747..2403590ac 100644 --- a/doc/tutorial.md +++ b/doc/tutorial.md @@ -5,10 +5,11 @@ | Option | Tool | Description | Available
since | | --------------------- | ---------------------------------- | ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ | -------------------- | | --flash=n[k][m] | st-flash | One can specify `--flash=128k` for example, to override the default value of 64k for the STM32F103C8T6
to assume 128k of flash being present. This option accepts decimal (128k), octal 0200k, or hex 0x80k values.
Leaving the multiplier out is equally valid, e.g.: `--flash=0x20000`. The size may be followed by an optional
"k" or "m" to multiply the given value by 1k (1024) or 1M respectively. | v1.4.0 | -| --freq=n[k][m] | st-flash | The frequency of the SWD/JTAG interface can be specified, to override the default 1800 kHz configuration.
This option solely accepts decimal values (5K or 1.8M) with the unit `Hz` being left out. Valid frequencies are:
`5K, 15K, 25K, 50K, 100K, 125K, 240K, 480K, 950K, 1200K(1.2M), 1800K(1.8M), 4000K(4M)`. | v1.6.1 | +| --freq=n[k][m] | st-info
st-flash
st-util | The frequency of the SWD/JTAG interface can be specified, to override the default 1800 kHz configuration.
This option solely accepts decimal values (5K or 1.8M) with the unit `Hz` being left out. Valid frequencies are:
`5K, 15K, 25K, 50K, 100K, 125K, 240K, 480K, 950K, 1200K, 1800K, 4000K(4M)`. | v1.6.1 | | --opt | st-flash | Optimisation can be enabled in order to skip flashing empty (0x00 or 0xff) bytes at the end of binary file.
This may cause some garbage data left after a flash operation. This option was enabled by default in earlier releases. | v1.6.1 | | --reset | st-flash | Trigger a reset both before and after flashing. The default uses the hardware reset through `NRST` pin.
The software reset is used if the hardware reset failed (`NRST` pin not connected). | v1.0.0 | -| --connect-under-reset | st-flash | Connect under reset. Option makes it possible to connect to the device before code execution. This is useful
when the target contains code that lets the device go to sleep, disables debug pins or other special code. | v1.6.1 | +| --connect-under-reset | st-info
st-flash | Connect under reset. Option makes it possible to connect to the device before code execution. This is useful
when the target contains code that lets the device go to sleep, disables debug pins or other special code. | v1.6.1 | +| --hot-plug | st-info
st-util | Connect to the target without reset. | v1.6.2 | | --probe | st-info | Display hardware information about the connected programmer and target MCU. | v1.2.0 | | --version | st-info
st-flash
st-util | Print version information. | v1.3.0 | | --help | st-flash
st-util | Print list of available commands. | | @@ -262,7 +263,7 @@ There are a few options: -m, --multi Set gdb server to extended mode. st-util will continue listening for connections after disconnect. - -n, --no-reset + -n, --no-reset, --hot-plug Do not reset board on connection. ``` diff --git a/src/st-flash/flash.c b/src/st-flash/flash.c index 447daa158..5a226d57b 100644 --- a/src/st-flash/flash.c +++ b/src/st-flash/flash.c @@ -26,9 +26,9 @@ static void cleanup(int signum) { } static void usage(void) { - puts("command line: ./st-flash [--debug] [--reset] [--connect-under-reset] [--opt] [--serial ] [--format ] [--flash=] [--freq=] [--area=] {read|write} [path] [addr] [size]"); - puts("command line: ./st-flash [--debug] [--connect-under-reset] [--freq=] [--serial ] erase"); - puts("command line: ./st-flash [--debug] [--freq=] [--serial ] reset"); + puts("command line: ./st-flash [--debug] [--reset] [--connect-under-reset] [--opt] [--serial ] [--format ] [--flash=] [--freq=] [--area=] {read|write} [path] [addr] [size]"); + puts("command line: ./st-flash [--debug] [--connect-under-reset] [--freq=] [--serial ] erase"); + puts("command line: ./st-flash [--debug] [--freq=] [--serial ] reset"); puts(" , and : Use hex format."); puts(" : Use decimal, octal or hex (prefix 0xXXX) format, optionally followed by k=KB, or m=MB (eg. --flash=128k)"); puts(" : Can be 'binary' (default) or 'ihex', although must be specified for binary format only."); @@ -52,6 +52,7 @@ int main(int ac, char** av) { uint8_t * mem = NULL; o.size = 0; + o.connect = CONNECT_NORMAL; if (flash_get_opts(&o, ac - 1, av + 1) == -1) { printf("invalid command line\n"); @@ -61,9 +62,7 @@ int main(int ac, char** av) { printf("st-flash %s\n", STLINK_VERSION); - sl = stlink_open_usb(o.log_level, - o.connect_under_reset ? 2 : 1, - (char *)o.serial, o.freq); + sl = stlink_open_usb(o.log_level, o.connect, (char *)o.serial, o.freq); if (sl == NULL) { return(-1); } diff --git a/src/st-flash/flash.h b/src/st-flash/flash.h index 8a5c2ad29..cd08db70f 100644 --- a/src/st-flash/flash.h +++ b/src/st-flash/flash.h @@ -26,7 +26,7 @@ struct flash_opts { size_t flash_size; // --flash=n[k][m] int opt; // enable empty tail data drop optimization int freq; // --freq=n[k][m] frequency of JTAG/SWD - bool connect_under_reset; + enum connect_type connect; }; #define FLASH_OPTS_INITIALIZER {0, { 0 }, NULL, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} diff --git a/src/st-flash/flash_opts.c b/src/st-flash/flash_opts.c index 7d846e425..63774ea25 100644 --- a/src/st-flash/flash_opts.c +++ b/src/st-flash/flash_opts.c @@ -2,6 +2,8 @@ #include #include +#include + #include "flash.h" static bool starts_with(const char * str, const char * prefix) { @@ -140,50 +142,21 @@ int flash_get_opts(struct flash_opts* o, int ac, char** av) { return(-1); } - } else if (strcmp(av[0], "--freq") == 0 || starts_with(av[0], "--freq=")) { - const char* freq; - - if (strcmp(av[0], "--freq") == 0) { - ac--; - av++; - - if (ac < 1) { - return(-1); - } + } else if (strcmp(av[0], "--freq") == 0) { + ac--; + av++; - freq = av[0]; - } else { - freq = av[0] + strlen("--freq="); + if (ac < 1) { + return(-1); } - if (strcmp(freq, "5K") == 0 || strcmp(freq, "5k") == 0) { - o->freq = 5; - } else if (strcmp(freq, "15K") == 0 || strcmp(freq, "15k") == 0) { - o->freq = 15; - } else if (strcmp(freq, "25K") == 0 || strcmp(freq, "25k") == 0) { - o->freq = 25; - } else if (strcmp(freq, "50K") == 0 || strcmp(freq, "50k") == 0) { - o->freq = 50; - } else if (strcmp(freq, "100K") == 0 || strcmp(freq, "100k") == 0) { - o->freq = 100; - } else if (strcmp(freq, "125K") == 0 || strcmp(freq, "125k") == 0) { - o->freq = 125; - } else if (strcmp(freq, "240K") == 0 || strcmp(freq, "240k") == 0) { - o->freq = 240; - } else if (strcmp(freq, "480K") == 0 || strcmp(freq, "480k") == 0) { - o->freq = 480; - } else if (strcmp(freq, "950K") == 0 || strcmp(freq, "950k") == 0) { - o->freq = 950; - } else if (strcmp(freq, "1200K") == 0 || strcmp(freq, "1200k") == 0 || - strcmp(freq, "1.2M") == 0 || strcmp(freq, "1.2m") == 0) { - o->freq = 1200; - } else if (strcmp(freq, "1800K") == 0 || strcmp(freq, "1800k") == 0 || - strcmp(freq, "1.8M") == 0 || strcmp(freq, "1.8m") == 0) { - o->freq = 1800; - } else if (strcmp(freq, "4000K") == 0 || strcmp(freq, "4000k") == 0 || - strcmp(freq, "4M") == 0 || strcmp(freq, "4m") == 0) { - o->freq = 4000; - } else { + o->freq = arg_parse_freq(av[0]); + if (o->freq < 0) { + return(-1); + } + } else if (starts_with(av[0], "--freq=")) { + o->freq = arg_parse_freq(av[0] + strlen("--freq=")); + if (o->freq < 0) { return(-1); } } else if (strcmp(av[0], "--format") == 0 || starts_with(av[0], "--format=")) { @@ -219,7 +192,7 @@ int flash_get_opts(struct flash_opts* o, int ac, char** av) { o->flash_size = (size_t)flash_size; } } else if (strcmp(av[0], "--connect-under-reset") == 0) { - o->connect_under_reset = true; + o->connect = CONNECT_UNDER_RESET; } else { break; // non-option found diff --git a/src/st-info/info.c b/src/st-info/info.c index c1ac86373..a6b4e85c6 100644 --- a/src/st-info/info.c +++ b/src/st-info/info.c @@ -4,16 +4,17 @@ #include #include +#include static void usage(void) { puts("st-info --version"); - puts("st-info --probe"); + puts("st-info --probe [--connect-under-reset] [--hot-plug] [--freq=]"); puts("st-info --serial"); - puts("st-info --flash [--connect-under-reset]"); - puts("st-info --pagesize [--connect-under-reset]"); - puts("st-info --sram [--connect-under-reset]"); - puts("st-info --chipid [--connect-under-reset]"); - puts("st-info --descr [--connect-under-reset]"); + puts("st-info --flash [--connect-under-reset] [--hot-plug] [--freq=]"); + puts("st-info --pagesize [--connect-under-reset] [--hot-plug] [--freq=]"); + puts("st-info --sram [--connect-under-reset] [--hot-plug] [--freq=]"); + puts("st-info --chipid [--connect-under-reset] [--hot-plug] [--freq=]"); + puts("st-info --descr [--connect-under-reset] [--hot-plug] [--freq=]"); } static void stlink_print_version(stlink_t *sl) { @@ -45,11 +46,11 @@ static void stlink_print_info(stlink_t *sl) { if (params) { printf(" descr: %s\n", params->description); } } -static void stlink_probe(void) { +static void stlink_probe(enum connect_type connect, int freq) { stlink_t **stdevs; size_t size; - size = stlink_probe_usb(&stdevs); + size = stlink_probe_usb(&stdevs, connect, freq); printf("Found %u stlink programmers\n", (unsigned int)size); @@ -61,44 +62,47 @@ static void stlink_probe(void) { stlink_probe_usb_free(&stdevs, size); } -static stlink_t *stlink_open_first(bool under_reset) { +static int print_data(int ac, char **av) { stlink_t* sl = NULL; - sl = stlink_v1_open(0, 1); + enum connect_type connect = CONNECT_NORMAL; + int freq = 0; - if (sl == NULL) { - if (under_reset) { - sl = stlink_open_usb(0, 2, NULL, 0); - } else { - sl = stlink_open_usb(0, 1, NULL, 0); - } + if (strcmp(av[1], "--version") == 0) { + printf("v%s\n", STLINK_VERSION); + return(0); } - return(sl); -} + for (int i=2; i= 0) { continue; } + } + } else if (strncmp(av[i], "--freq=", 7) == 0) { + freq = arg_parse_freq(av[i] + 7); + if (freq >= 0) { continue; } + } -static int print_data(int ac, char **av) { - stlink_t* sl = NULL; - bool under_reset = false; + printf("Incorrect argument: %s\n\n", av[i]); + usage(); + return(-1); + } // probe needs all devices unclaimed if (strcmp(av[1], "--probe") == 0) { - stlink_probe(); - return(0); - } else if (strcmp(av[1], "--version") == 0) { - printf("v%s\n", STLINK_VERSION); + stlink_probe(connect, freq); return(0); } - if (ac == 3) { - if (strcmp(av[2], "--connect-under-reset") == 0) { - under_reset = true; - } else { - usage(); - return(-1); - } - } - - sl = stlink_open_first(under_reset); + // open first st-link device + sl = stlink_open_usb(0, connect, NULL, freq); if (sl == NULL) { return(-1); } diff --git a/src/st-util/gdb-server.c b/src/st-util/gdb-server.c index d7ca6d008..3dc3073e5 100644 --- a/src/st-util/gdb-server.c +++ b/src/st-util/gdb-server.c @@ -26,6 +26,7 @@ #endif #include +#include #include #include "gdb-remote.h" #include "gdb-server.h" @@ -63,7 +64,8 @@ typedef struct _st_state_t { int logging_level; int listen_port; int persistent; - int reset; + enum connect_type connect_mode; + int freq; } st_state_t; @@ -100,9 +102,9 @@ static stlink_t* do_connect(st_state_t *st) { stlink_t *sl = NULL; if (serial_specified) { - sl = stlink_open_usb(st->logging_level, st->reset, serialnumber, 0); + sl = stlink_open_usb(st->logging_level, st->connect_mode, serialnumber, st->freq); } else { - sl = stlink_open_usb(st->logging_level, st->reset, NULL, 0); + sl = stlink_open_usb(st->logging_level, st->connect_mode, NULL, st->freq); } return(sl); @@ -116,6 +118,8 @@ int parse_options(int argc, char** argv, st_state_t *st) { {"listen_port", required_argument, NULL, 'p'}, {"multi", optional_argument, NULL, 'm'}, {"no-reset", optional_argument, NULL, 'n'}, + {"hot-plug", optional_argument, NULL, 'n'}, + {"freq", optional_argument, NULL, 'F'}, {"version", no_argument, NULL, 'V'}, {"semihosting", no_argument, NULL, SEMIHOSTING_OPTION}, {"serial", required_argument, NULL, SERIAL_OPTION}, @@ -126,16 +130,16 @@ int parse_options(int argc, char** argv, st_state_t *st) { " -V, --version\t\tPrint the version\n" " -vXX, --verbose=XX\tSpecify a specific verbosity level (0..99)\n" " -v, --verbose\t\tSpecify generally verbose logging\n" - "\t\t\tChoose what version of stlink to use, (defaults to 2)\n" - " -1, --stlinkv1\tForce stlink version 1\n" " -p 4242, --listen_port=1234\n" "\t\t\tSet the gdb server listen port. " "(default port: " STRINGIFY(DEFAULT_GDB_LISTEN_PORT) ")\n" " -m, --multi\n" "\t\t\tSet gdb server to extended mode.\n" "\t\t\tst-util will continue listening for connections after disconnect.\n" - " -n, --no-reset\n" + " -n, --no-reset, --hot-plug\n" "\t\t\tDo not reset board on connection.\n" + " -F 1800K, --freq=1M\n" + "\t\t\tSet the frequency of the SWD/JTAG interface.\n" " --semihosting\n" "\t\t\tEnable semihosting support.\n" " --serial \n" @@ -160,7 +164,6 @@ int parse_options(int argc, char** argv, st_state_t *st) { exit(EXIT_SUCCESS); break; case 'v': - if (optarg) { st->logging_level = atoi(optarg); } else { @@ -170,7 +173,6 @@ int parse_options(int argc, char** argv, st_state_t *st) { break; case 'p': sscanf(optarg, "%i", &q); - if (q < 0) { fprintf(stderr, "Can't use a negative port to listen on: %d\n", q); exit(EXIT_FAILURE); @@ -178,11 +180,19 @@ int parse_options(int argc, char** argv, st_state_t *st) { st->listen_port = q; break; + case 'm': st->persistent = 1; break; case 'n': - st->reset = 0; + st->connect_mode = CONNECT_HOT_PLUG; + break; + case 'F': + st->freq = arg_parse_freq(optarg); + if (st->freq < 0) { + fprintf(stderr, "Can't parse a frequency: %s\n", optarg); + exit(EXIT_FAILURE); + } break; case 'V': printf("v%s\n", STLINK_VERSION); @@ -217,7 +227,7 @@ int main(int argc, char** argv) { // set defaults ... state.logging_level = DEFAULT_LOGGING_LEVEL; state.listen_port = DEFAULT_GDB_LISTEN_PORT; - state.reset = 1; // by default, reset board + state.connect_mode = CONNECT_NORMAL; // by default, reset board parse_options(argc, argv, &state); printf("st-util\n"); @@ -240,7 +250,7 @@ int main(int argc, char** argv) { signal(SIGSEGV, &cleanup); #endif - if (state.reset) { stlink_reset(sl); } + if (state.connect_mode != CONNECT_HOT_PLUG) { stlink_reset(sl); } DLOG("Chip ID is %#010x, Core ID is %#08x.\n", sl->chip_id, sl->core_id); @@ -1111,7 +1121,7 @@ int serve(stlink_t *sl, st_state_t *st) { stlink_force_debug(sl); - if (st->reset) { stlink_reset(sl); } + if (st->connect_mode != CONNECT_HOT_PLUG) { stlink_reset(sl); } init_code_breakpoints(sl); init_data_watchpoints(sl); @@ -1840,7 +1850,7 @@ int serve(stlink_t *sl, st_state_t *st) { connected_stlink = sl; - if (st->reset) { stlink_reset(sl); } + if (st->connect_mode != CONNECT_HOT_PLUG) { stlink_reset(sl); } ret = stlink_force_debug(sl); diff --git a/src/stlink-lib/helper.c b/src/stlink-lib/helper.c index 32d9b6c8d..1f0f71b8d 100644 --- a/src/stlink-lib/helper.c +++ b/src/stlink-lib/helper.c @@ -1,6 +1,7 @@ #include #include +#include #ifdef STLINK_HAVE_SYS_TIME_H #include @@ -13,3 +14,16 @@ unsigned time_ms() { gettimeofday(&tv, NULL); return (unsigned)(tv.tv_sec * 1000 + tv.tv_usec / 1000); } + +int arg_parse_freq(const char *str) { + char *tail; + int value = (int)strtol(str, &tail, 10); + + if ((tail[0] == 'm' || tail[0] == 'M') && tail[1] == '\0') { + value = value*1000; + } else if (((tail[0] != 'k' && tail[0] != 'K') || tail[1] != '\0') && tail[0] != '\0') { + return -1; + } + + return value; +} diff --git a/src/stlink-lib/helper.h b/src/stlink-lib/helper.h index 12c2ea2a7..96467377a 100644 --- a/src/stlink-lib/helper.h +++ b/src/stlink-lib/helper.h @@ -3,4 +3,6 @@ unsigned time_ms(); +int arg_parse_freq(const char *str); + #endif /* SYS_HELPER_H */ diff --git a/src/stlink-lib/usb.c b/src/stlink-lib/usb.c index 569815665..ce0d672c8 100644 --- a/src/stlink-lib/usb.c +++ b/src/stlink-lib/usb.c @@ -46,7 +46,7 @@ static int _stlink_match_speed_map(const uint32_t *map, unsigned int map_size, u // get abs value for comparison current_diff = (current_diff > 0) ? current_diff : -current_diff; - if ((current_diff < speed_diff) && khz >= map[i]) { + if (current_diff < speed_diff) { speed_diff = current_diff; speed_index = i; } @@ -741,6 +741,8 @@ int _stlink_usb_set_swdclk(stlink_t* sl, int clk_freq) { } return(0); + } else if (clk_freq) { + WLOG("ST-Link firmware does not support frequency setup\n"); } return(-1); @@ -1196,7 +1198,7 @@ size_t stlink_serial(struct libusb_device_handle *handle, struct libusb_device_d return strlen(serial); } -stlink_t *stlink_open_usb(enum ugly_loglevel verbose, int reset, char serial[STLINK_SERIAL_BUFFER_SIZE], int freq) { +stlink_t *stlink_open_usb(enum ugly_loglevel verbose, enum connect_type connect, char serial[STLINK_SERIAL_BUFFER_SIZE], int freq) { stlink_t* sl = NULL; struct stlink_libusb* slu = NULL; int ret = -1; @@ -1380,7 +1382,7 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, int reset, char serial[STL DLOG("JTAG/SWD freq set to %d\n", freq); stlink_set_swdclk(sl, freq); - if (reset == 2) { + if (connect == CONNECT_UNDER_RESET) { stlink_jtag_reset(sl, 0); if (stlink_current_mode(sl) != STLINK_DEV_DEBUG_MODE) { stlink_enter_swd_mode(sl); } @@ -1390,10 +1392,9 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, int reset, char serial[STL usleep(10000); } - if (stlink_current_mode(sl) != STLINK_DEV_DEBUG_MODE) { stlink_enter_swd_mode(sl); } - if (reset == 1) { + if (connect == CONNECT_NORMAL) { if ( sl->version.stlink_v > 1) { stlink_jtag_reset(sl, 2); } stlink_reset(sl); @@ -1420,7 +1421,7 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, int reset, char serial[STL return(NULL); } -static size_t stlink_probe_usb_devs(libusb_device **devs, stlink_t **sldevs[]) { +static size_t stlink_probe_usb_devs(libusb_device **devs, stlink_t **sldevs[], enum connect_type connect, int freq) { stlink_t **_sldevs; libusb_device *dev; int i = 0; @@ -1489,7 +1490,7 @@ static size_t stlink_probe_usb_devs(libusb_device **devs, stlink_t **sldevs[]) { if (serial_len != STLINK_SERIAL_LENGTH) { continue; } - stlink_t *sl = stlink_open_usb(0, 1, serial, 0); + stlink_t *sl = stlink_open_usb(0, connect, serial, freq); if (!sl) { ELOG("Failed to open USB device %#06x:%#06x\n", desc.idVendor, desc.idProduct); @@ -1504,7 +1505,7 @@ static size_t stlink_probe_usb_devs(libusb_device **devs, stlink_t **sldevs[]) { return(slcur); } -size_t stlink_probe_usb(stlink_t **stdevs[]) { +size_t stlink_probe_usb(stlink_t **stdevs[], enum connect_type connect, int freq) { libusb_device **devs; stlink_t **sldevs; @@ -1520,7 +1521,7 @@ size_t stlink_probe_usb(stlink_t **stdevs[]) { if (cnt < 0) { return(0); } - slcnt = stlink_probe_usb_devs(devs, &sldevs); + slcnt = stlink_probe_usb_devs(devs, &sldevs, connect, freq); libusb_free_device_list(devs, 1); libusb_exit(NULL); diff --git a/src/stlink-lib/usb.h b/src/stlink-lib/usb.h index 512370a10..f48ef225d 100644 --- a/src/stlink-lib/usb.h +++ b/src/stlink-lib/usb.h @@ -48,6 +48,12 @@ extern "C" { #define STLINK_SG_SIZE 31 #define STLINK_CMD_SIZE 16 +enum connect_type { + CONNECT_HOT_PLUG = 0, + CONNECT_NORMAL = 1, + CONNECT_UNDER_RESET = 2, +}; + struct stlink_libusb { libusb_context* libusb_ctx; libusb_device_handle* usb_handle; @@ -62,13 +68,13 @@ struct stlink_libusb { /** * Open a stlink * @param verbose Verbosity loglevel - * @param reset Reset stlink programmer + * @param connect Type of connect to target * @param serial Serial number to search for, when NULL the first stlink found is opened (binary format) * @retval NULL Error while opening the stlink * @retval !NULL Stlink found and ready to use */ -stlink_t *stlink_open_usb(enum ugly_loglevel verbose, int reset, char serial[STLINK_SERIAL_BUFFER_SIZE], int freq); -size_t stlink_probe_usb(stlink_t **stdevs[]); +stlink_t *stlink_open_usb(enum ugly_loglevel verbose, enum connect_type connect, char serial[STLINK_SERIAL_BUFFER_SIZE], int freq); +size_t stlink_probe_usb(stlink_t **stdevs[], enum connect_type connect, int freq); void stlink_probe_usb_free(stlink_t **stdevs[], size_t size); #ifdef __cplusplus From 5b8ee390eec6e83bfb67c026248f0cffc9e84ab0 Mon Sep 17 00:00:00 2001 From: Oleksiy Slyshyk Date: Sat, 27 Mar 2021 12:27:43 +0200 Subject: [PATCH 202/503] remove abort() from lib. related to #634 --- src/common.c | 19 ++++++++----------- 1 file changed, 8 insertions(+), 11 deletions(-) diff --git a/src/common.c b/src/common.c index 8fae08a09..72150953b 100644 --- a/src/common.c +++ b/src/common.c @@ -980,7 +980,7 @@ static inline uint32_t read_flash_sr(stlink_t *sl, unsigned bank) { } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { sr_reg = (bank==BANK_1)?FLASH_H7_SR1:FLASH_H7_SR2; } else { - ELOG("unsupported flash method, abort"); + ELOG("unsupported flash method, abort\n"); return(-1); } @@ -1010,7 +1010,7 @@ static inline unsigned int is_flash_busy(stlink_t *sl) { } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { sr_busy_shift = FLASH_H7_SR_QW; } else { - ELOG("unsupported flash method, abort"); + ELOG("unsupported flash method, abort\n"); return(-1); } @@ -1617,9 +1617,8 @@ int stlink_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { DLOG("*** stlink_write_mem32 %u bytes to %#x\n", len, addr); if (len % 4 != 0) { - fprintf(stderr, "Error: Data length doesn't have a 32 bit alignment: +%d byte.\n", - len % 4); - abort(); + ELOG("Data length doesn't have a 32 bit alignment: +%d byte.\n", len % 4); + return(-1); } return(sl->backend->write_mem32(sl, addr, len)); @@ -1629,9 +1628,8 @@ int stlink_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { DLOG("*** stlink_read_mem32 ***\n"); if (len % 4 != 0) { // !!! never ever: fw gives just wrong values - fprintf(stderr, "Error: Data length doesn't have a 32 bit alignment: +%d byte.\n", - len % 4); - abort(); + ELOG("Data length doesn't have a 32 bit alignment: +%d byte.\n", len % 4); + return(-1); } return(sl->backend->read_mem32(sl, addr, len)); @@ -1641,9 +1639,8 @@ int stlink_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len) { DLOG("*** stlink_write_mem8 ***\n"); if (len > 0x40) { // !!! never ever: Writing more then 0x40 bytes gives unexpected behaviour - fprintf(stderr, "Error: Data length > 64: +%d byte.\n", - len); - abort(); + ELOG("Data length > 64: +%d byte.\n", len); + return(-1); } return(sl->backend->write_mem8(sl, addr, len)); From 0b7221076a9b66cfb9647e4f06d55d66229e0799 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sat, 27 Mar 2021 11:41:09 +0100 Subject: [PATCH 203/503] General Project Update - Updated CHANGELOG.md - [doc] Update for GD32F303VGT6 in device list - [doc] Updated tutorial.md > Added refs for unknown chip id! 0 > Minor update for tool option table --- CHANGELOG.md | 8 ++++---- doc/devices_boards.md | 6 +++--- doc/tutorial.md | 8 +++++--- 3 files changed, 12 insertions(+), 10 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index e3f8e13b5..ee46901e7 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -2,7 +2,7 @@ # v1.6.2 -Release date: (planned H1/2021) +Release date: (planned Q2/2021) Features: @@ -21,7 +21,7 @@ Features: Updates & changes: -- [doc] Added tutorial section on unknown chip id error ([#107](https://github.com/stlink-org/stlink/pull/107), [#568](https://github.com/stlink-org/stlink/pull/568), +- [doc] Added tutorial section on unknown chip id error (commit [#229c721](https://github.com/stlink-org/stlink/commit/229c721189587760db5509c59b3c02e93e7035c8), [#107](https://github.com/stlink-org/stlink/pull/107), [#568](https://github.com/stlink-org/stlink/pull/568)) - [doc] Updated documentation on target resetting ([#261](https://github.com/stlink-org/stlink/pull/261), [#533](https://github.com/stlink-org/stlink/pull/533), [#1107](https://github.com/stlink-org/stlink/pull/1107)) - [doc] Added note on `(gdb) run` command (commit [#03793d4](https://github.com/stlink-org/stlink/commit/03793d42b6078344a9ef8ad55f1d5d0fc19e486e), [#267](https://github.com/stlink-org/stlink/pull/267)) - [doc] `st-flash --reset` parameter (one solution for #356) ([#642](https://github.com/stlink-org/stlink/pull/642)) @@ -35,8 +35,9 @@ Updates & changes: Fixes: -- Flash loader rework ([#356](https://github.com/stlink-org/stlink/pull/356), [#556](https://github.com/stlink-org/stlink/pull/556), [#593](https://github.com/stlink-org/stlink/pull/593), [#607](https://github.com/stlink-org/stlink/pull/607), [#612](https://github.com/stlink-org/stlink/pull/612), [#638](https://github.com/stlink-org/stlink/pull/638), [#661](https://github.com/stlink-org/stlink/pull/661), [#690](https://github.com/stlink-org/stlink/pull/690), [#979](https://github.com/stlink-org/stlink/pull/979), [#1043](https://github.com/stlink-org/stlink/pull/1043), [#1054](https://github.com/stlink-org/stlink/pull/1054), [#1105](https://github.com/stlink-org/stlink/pull/1105), [#1113](https://github.com/stlink-org/stlink/pull/1113)) +- Flash loader rework ([#356](https://github.com/stlink-org/stlink/pull/356), [#556](https://github.com/stlink-org/stlink/pull/556), [#593](https://github.com/stlink-org/stlink/pull/593), [#597](https://github.com/stlink-org/stlink/pull/597), [#607](https://github.com/stlink-org/stlink/pull/607), [#612](https://github.com/stlink-org/stlink/pull/612), [#638](https://github.com/stlink-org/stlink/pull/638), [#661](https://github.com/stlink-org/stlink/pull/661), [#690](https://github.com/stlink-org/stlink/pull/690), [#818](https://github.com/stlink-org/stlink/pull/818), [#854](https://github.com/stlink-org/stlink/pull/854), [#967](https://github.com/stlink-org/stlink/pull/967), [#979](https://github.com/stlink-org/stlink/pull/979), [#1043](https://github.com/stlink-org/stlink/pull/1043), [#1054](https://github.com/stlink-org/stlink/pull/1054), [#1092](https://github.com/stlink-org/stlink/pull/1092), [#1105](https://github.com/stlink-org/stlink/pull/1105), [#1113](https://github.com/stlink-org/stlink/pull/1113)) - Fixed old DFU serial number for STLINK programmers ([#417](https://github.com/stlink-org/stlink/pull/417), [#494](https://github.com/stlink-org/stlink/pull/494), [#1106](https://github.com/stlink-org/stlink/pull/1106)) +- Use vl flashloader for all STM32F1 series ([#769](https://github.com/stlink-org/stlink/pull/769), [#1041](https://github.com/stlink-org/stlink/pull/1041), [#1044](https://github.com/stlink-org/stlink/pull/1044)) - [regression] Changed timeout on flash write ([#787](https://github.com/stlink-org/stlink/pull/787), [#981](https://github.com/stlink-org/stlink/pull/981), [#987](https://github.com/stlink-org/stlink/pull/987)) - cmake compile failure with external `CMAKE_MODULE_PATH` set ([#962](https://github.com/stlink-org/stlink/pull/962)) - doc/man: Fixed installation directory ([#970](https://github.com/stlink-org/stlink/pull/970)) @@ -50,7 +51,6 @@ Fixes: - `st-util`: wrong register values passed to `gdb` (STLink/V2) ([#1002](https://github.com/stlink-org/stlink/pull/1002), [#1011](https://github.com/stlink-org/stlink/pull/1011), [#1026](https://github.com/stlink-org/stlink/pull/1026), [#1027](https://github.com/stlink-org/stlink/pull/1027), [#1064](https://github.com/stlink-org/stlink/pull/1064), [#1065](https://github.com/stlink-org/stlink/pull/1065)) - GDB: Fixed problems with target description ([#1013](https://github.com/stlink-org/stlink/pull/1013), [#1088](https://github.com/stlink-org/stlink/pull/1088), [#1109](https://github.com/stlink-org/stlink/pull/1109)) - [doc] Fixed wrong path for `rules.d` folder ([#1020](https://github.com/stlink-org/stlink/pull/1020)) -- Use vl flashloader for all STM32F1 series ([#1041](https://github.com/stlink-org/stlink/pull/1041), [#1044](https://github.com/stlink-org/stlink/pull/1044)) - Fixed support for STLINK/V1 programmer ([#1045](https://github.com/stlink-org/stlink/pull/1045), [#1105](https://github.com/stlink-org/stlink/pull/1105)) - st-util v1.6.1 does not recognize option --freq (commit [#e576768](https://github.com/stlink-org/stlink/commit/e5767681f14de9851aa970a9299930ca68b2ed92), [#1055](https://github.com/stlink-org/stlink/pull/1055)) - Fixed `gettimeofday` for MSVC ([#1074](https://github.com/stlink-org/stlink/pull/1074)) diff --git a/doc/devices_boards.md b/doc/devices_boards.md index 6396738c4..df4b5ed29 100644 --- a/doc/devices_boards.md +++ b/doc/devices_boards.md @@ -109,9 +109,9 @@ Tested boards [incl. STLINK programmers]: **STM32F3 / ARM Cortex M4F / Core-ID: 0x2ba01477 (STM32F3c_CORE_ID)** -| Product-Code | Chip-ID | STLink
Programmer | Boards | -| ------------ | ------- | ---------------------- | ------------------------------------------------------ | -| GD32F303VGT6 | 0x430 | _N/A_ | STM32F303 clone from GigaDevice GD)
_unsupported_ | +| Product-Code | Chip-ID | STLINK
Programmer | Boards | +| ------------ | ------- | ---------------------- | ---------------------------------- | +| GD32F303VGT6 | 0x430 | [v2] | STM32F303 clone from GigaDevice GD | **STM32F4 / ARM Cortex M4F / Core-ID: 0x2ba01477 (STM32F4_CORE_ID)** diff --git a/doc/tutorial.md b/doc/tutorial.md index 2403590ac..37c29ab6a 100644 --- a/doc/tutorial.md +++ b/doc/tutorial.md @@ -7,7 +7,7 @@ | --flash=n[k][m] | st-flash | One can specify `--flash=128k` for example, to override the default value of 64k for the STM32F103C8T6
to assume 128k of flash being present. This option accepts decimal (128k), octal 0200k, or hex 0x80k values.
Leaving the multiplier out is equally valid, e.g.: `--flash=0x20000`. The size may be followed by an optional
"k" or "m" to multiply the given value by 1k (1024) or 1M respectively. | v1.4.0 | | --freq=n[k][m] | st-info
st-flash
st-util | The frequency of the SWD/JTAG interface can be specified, to override the default 1800 kHz configuration.
This option solely accepts decimal values (5K or 1.8M) with the unit `Hz` being left out. Valid frequencies are:
`5K, 15K, 25K, 50K, 100K, 125K, 240K, 480K, 950K, 1200K, 1800K, 4000K(4M)`. | v1.6.1 | | --opt | st-flash | Optimisation can be enabled in order to skip flashing empty (0x00 or 0xff) bytes at the end of binary file.
This may cause some garbage data left after a flash operation. This option was enabled by default in earlier releases. | v1.6.1 | -| --reset | st-flash | Trigger a reset both before and after flashing. The default uses the hardware reset through `NRST` pin.
The software reset is used if the hardware reset failed (`NRST` pin not connected). | v1.0.0 | +| --reset | st-flash | Trigger a reset both before and after flashing. The default uses the hardware reset through `NRST` pin.
A software reset (via `AIRCR`; since v1.5.1) is used, if the hardware reset failed (`NRST` pin not connected). | v1.0.0 | | --connect-under-reset | st-info
st-flash | Connect under reset. Option makes it possible to connect to the device before code execution. This is useful
when the target contains code that lets the device go to sleep, disables debug pins or other special code. | v1.6.1 | | --hot-plug | st-info
st-util | Connect to the target without reset. | v1.6.2 | | --probe | st-info | Display hardware information about the connected programmer and target MCU. | v1.2.0 | @@ -112,12 +112,14 @@ This so called `DBGMCU_IDCODE` register is allocated either at memory address `0 A failure of chip identification results in the error `WARN src/common.c: unknown chip id!`. There are different variants of this message that refer to different issues: -- `unknown chip id! 0` --> _currently unknown_ +- `unknown chip id! 0` --> Target chip (board) is unknown. + 1. Microcontroller is in stop/standby mode. + 2. The signals `DIO` and `CLK` are reversed on the SWD-Interface. - `unknown chip id! 0x1a` --> _currently unknown_ - `unknown chip id! 0x001f` --> _currently unknown_ - `unknown chip id! 0x3e8` --> _currently unknown_ - `unknown chip id! 0xa05f0000` --> _currently unknown_ -- `unknown chip id! 0x3748` --> A target chip / board cannot be detected. +- `unknown chip id! 0x3748` --> A target chip (board) cannot be detected. 1. No target is connected --> In this case `st-info --probe` displays `chip id 0x0748` with STLINK/V2 and `chip id 0x03e8` with STLINK-V3. 2. The chip is connected but has gone into an undefined state of operation where the SWD pins are unresponsive. --> Try to use `--connect-under-reset` while pressing the reset button on the target board. 3. A firmware-issue prevents the programmer from normal operation. --> Ensure that your programmer runs the latest firmware version and consider to upgrade any older version by using the official firmware upgrade tool provided by STMicroelectronics. From 36434d5785bc752465b47b5b058e33da1df90794 Mon Sep 17 00:00:00 2001 From: anton Date: Sat, 27 Mar 2021 15:54:54 +0500 Subject: [PATCH 204/503] Added addition check of connected target --- src/common.c | 58 ++++++++++++++++++-------------------------- src/stlink-lib/reg.h | 12 ++++----- 2 files changed, 29 insertions(+), 41 deletions(-) diff --git a/src/common.c b/src/common.c index b5bb67e9e..f621a4b6d 100644 --- a/src/common.c +++ b/src/common.c @@ -1220,14 +1220,14 @@ int stlink_core_id(stlink_t *sl) { // do not call this procedure directly. int stlink_chip_id(stlink_t *sl, uint32_t *chip_id) { int ret; + cortex_m3_cpuid_t cpu_id; - uint32_t cpu_id; - *chip_id = 0; - ret = -1; - - // Read the CPU ID to determine where to read the core id from - if (stlink_read_debug32(sl, STLINK_REG_CM3_CPUID, &cpu_id)) - cpu_id = 0; + // Read the CPU ID to determine where to read the core id + if (stlink_cpu_id(sl, &cpu_id) || + cpu_id.implementer_id != STLINK_REG_CMx_CPUID_IMPL_ARM) { + ELOG("Can not connect to target. Please use \'connect under reset\' and try again\n"); + return -1; + } /* * the chip_id register in the reference manual have @@ -1235,18 +1235,17 @@ int stlink_chip_id(stlink_t *sl, uint32_t *chip_id) { * */ - uint32_t part_no = STLINK_REG_CM3_CPUID_PARTNO(cpu_id); if ((sl->core_id == STM32H7_CORE_ID || sl->core_id == STM32H7_CORE_ID_JTAG) && - part_no == STLINK_REG_CMx_CPUID_PARTNO_CM7) { + cpu_id.part == STLINK_REG_CMx_CPUID_PARTNO_CM7) { // STM32H7 chipid in 0x5c001000 (RM0433 pg3189) ret = stlink_read_debug32(sl, 0x5c001000, chip_id); - } else if (part_no == STLINK_REG_CMx_CPUID_PARTNO_CM0) { + } else if (cpu_id.part == STLINK_REG_CMx_CPUID_PARTNO_CM0) { // STM32F0 (RM0091, pg914; RM0360, pg713) // STM32L0 (RM0377, pg813; RM0367, pg915; RM0376, pg917) // STM32G0 (RM0444, pg1367) ret = stlink_read_debug32(sl, 0x40015800, chip_id); - } else if (part_no == STLINK_REG_CMx_CPUID_PARTNO_CM33) { + } else if (cpu_id.part == STLINK_REG_CMx_CPUID_PARTNO_CM33) { // STM32L5 (RM0438, pg2157) ret = stlink_read_debug32(sl, 0xE0044000, chip_id); } else /* СM3, СM4, CM7 */ { @@ -1261,9 +1260,16 @@ int stlink_chip_id(stlink_t *sl, uint32_t *chip_id) { // STM32G4 (RM0440, pg2086) // STM32WB (RM0434, pg1406) ret = stlink_read_debug32(sl, 0xE0042000, chip_id); + } + + if (ret || !(*chip_id)) { + *chip_id = 0; + ELOG("Could not find chip id!\n"); + } else { + *chip_id = (*chip_id) & 0xfff; // Fix chip_id for F4 rev A errata, read CPU ID, as CoreID is the same for F2/F4 - if (*chip_id == 0x411 && (cpu_id & 0xfff0) == 0xc240) { + if (*chip_id == 0x411 && cpu_id.part == STLINK_REG_CMx_CPUID_PARTNO_CM4) { *chip_id = 0x413; } } @@ -1272,7 +1278,7 @@ int stlink_chip_id(stlink_t *sl, uint32_t *chip_id) { } /** - * Cortex m3 tech ref manual, CPUID register description + * Cortex M tech ref manual, CPUID register description * @param sl stlink context * @param cpuid pointer to the result object */ @@ -1305,26 +1311,16 @@ int stlink_load_device_params(stlink_t *sl) { DLOG("Loading device parameters....\n"); const struct stlink_chipid_params *params = NULL; stlink_core_id(sl); - uint32_t chip_id = 0; uint32_t flash_size; - stlink_chip_id(sl, &chip_id); - sl->chip_id = chip_id & 0xfff; - - // Fix chip_id for F4 rev A errata , Read CPU ID, as CoreID is the same for F2/F4 - if (sl->chip_id == 0x411) { - uint32_t cpuid; - stlink_read_debug32(sl, 0xE000ED00, &cpuid); - - if ((cpuid & 0xfff0) == 0xc240) { - sl->chip_id = 0x413; - } + if (stlink_chip_id(sl, &sl->chip_id)) { + return(-1); } params = stlink_chipid_get_params(sl->chip_id); if (params == NULL) { - WLOG("unknown chip id! %#x\n", chip_id); + WLOG("unknown chip id! %#x\n", sl->chip_id); return(-1); } @@ -1390,19 +1386,11 @@ int stlink_load_device_params(stlink_t *sl) { sl->chip_flags &= ~CHIP_F_HAS_DUAL_BANK; } -#if 0 - // Old code -- REW - ILOG("Device connected is: %s, id %#x\n", params->description, chip_id); - // TODO: make note of variable page size here..... - ILOG("SRAM size: %#x bytes (%d KiB), Flash: %#x bytes (%d KiB) in pages of %u bytes\n", - sl->sram_size, sl->sram_size / 1024, sl->flash_size, sl->flash_size / 1024, - (unsigned int)sl->flash_pgsz); -#else ILOG("%s: %u KiB SRAM, %u KiB flash in at least %u %s pages.\n", params->description, (unsigned)(sl->sram_size / 1024), (unsigned)(sl->flash_size / 1024), (sl->flash_pgsz < 1024) ? (unsigned)(sl->flash_pgsz) : (unsigned)(sl->flash_pgsz / 1024), (sl->flash_pgsz < 1024) ? "byte" : "KiB"); -#endif + return(0); } diff --git a/src/stlink-lib/reg.h b/src/stlink-lib/reg.h index 73f608cb6..79570aa34 100644 --- a/src/stlink-lib/reg.h +++ b/src/stlink-lib/reg.h @@ -3,12 +3,12 @@ #define STLINK_REG_CM3_CPUID 0xE000ED00 -#define STLINK_REG_CM3_CPUID_PARTNO(cpuid) ((cpuid)&STLINK_REG_CMx_CPUID_PARTNO_MASK) -#define STLINK_REG_CMx_CPUID_PARTNO_MASK 0xFFF0 -#define STLINK_REG_CMx_CPUID_PARTNO_CM0 0xC200 -#define STLINK_REG_CMx_CPUID_PARTNO_CM3 0xC230 -#define STLINK_REG_CMx_CPUID_PARTNO_CM7 0xC270 -#define STLINK_REG_CMx_CPUID_PARTNO_CM33 0xD210 +#define STLINK_REG_CMx_CPUID_PARTNO_CM0 0xC20 +#define STLINK_REG_CMx_CPUID_PARTNO_CM3 0xC23 +#define STLINK_REG_CMx_CPUID_PARTNO_CM4 0xC24 +#define STLINK_REG_CMx_CPUID_PARTNO_CM7 0xC27 +#define STLINK_REG_CMx_CPUID_PARTNO_CM33 0xD21 +#define STLINK_REG_CMx_CPUID_IMPL_ARM 0x41 #define STLINK_REG_CM3_FP_CTRL 0xE0002000 // Flash Patch Control Register From da37fec19ee378d076fae2d615ea7082d99e110e Mon Sep 17 00:00:00 2001 From: anton Date: Sat, 27 Mar 2021 21:12:00 +0500 Subject: [PATCH 205/503] Applied missing changes to tests --- tests/flash.c | 21 +++++---------------- 1 file changed, 5 insertions(+), 16 deletions(-) diff --git a/tests/flash.c b/tests/flash.c index a8d479b2d..132066aba 100644 --- a/tests/flash.c +++ b/tests/flash.c @@ -131,17 +131,6 @@ static struct Test tests[] = { .freq = 5, .format = FLASH_FORMAT_BINARY } }, - { "--debug --freq=6k --reset write test.bin 0x80000000", -1, - { .cmd = FLASH_CMD_WRITE, - .serial = { 0 }, - .filename = "test.bin", - .addr = 0x80000000, - .size = 0, - .reset = 1, - .log_level = DEBUG_LOG_LEVEL, - .freq = 6, - .format = FLASH_FORMAT_BINARY } - }, { "--debug --reset read test.bin 0x80000000 1000", 0, { .cmd = FLASH_CMD_READ, .serial = { 0 }, @@ -211,10 +200,10 @@ static struct Test tests[] = { { "--debug --reset --format=binary write test.hex", -1, FLASH_OPTS_INITIALIZER }, { "--debug --reset --format=ihex write test.hex 0x80000000", -1, FLASH_OPTS_INITIALIZER }, { "--debug --reset write test.hex sometext", -1, FLASH_OPTS_INITIALIZER }, - { "--serial A1020304 erase sometext", -1, FLASH_OPTS_INITIALIZER }, - { "--serial A1020304 erase", 0, + { "--serial ABCEFF544851717867216044 erase sometext", -1, FLASH_OPTS_INITIALIZER }, + { "--serial ABCEFF544851717867216044 erase", 0, { .cmd = FLASH_CMD_ERASE, - .serial = "\xA1\x02\x03\x04", + .serial = "ABCEFF544851717867216044", .filename = NULL, .addr = 0, .size = 0, @@ -223,9 +212,9 @@ static struct Test tests[] = { .freq = 0, .format = FLASH_FORMAT_BINARY } }, - { "--serial=A1020304 erase", 0, + { "--serial=ABCEFF544851717867216044 erase", 0, { .cmd = FLASH_CMD_ERASE, - .serial = "\xA1\x02\x03\x04", + .serial = "ABCEFF544851717867216044", .filename = NULL, .addr = 0, .size = 0, From 878df31761f449e5846bb841085a320420c77c15 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sat, 27 Mar 2021 17:46:22 +0100 Subject: [PATCH 206/503] Updated CI config & issue templates - Initial support for GitHub CI workflows - Cleanup for Travis CI config - Minor fixes for issue templates --- .github/ISSUE_TEMPLATE/bug-report.md | 18 +- .github/ISSUE_TEMPLATE/feature-request.md | 16 +- .github/workflows/c-cpp.yml | 334 +++++++++++++++++++++- .github/workflows/cmake.yml | 46 --- .travis.sh | 13 - .travis.yml | 2 +- README.md | 1 + 7 files changed, 338 insertions(+), 92 deletions(-) delete mode 100644 .github/workflows/cmake.yml diff --git a/.github/ISSUE_TEMPLATE/bug-report.md b/.github/ISSUE_TEMPLATE/bug-report.md index 0e22c2ce9..16e0477f0 100644 --- a/.github/ISSUE_TEMPLATE/bug-report.md +++ b/.github/ISSUE_TEMPLATE/bug-report.md @@ -1,8 +1,8 @@ --- name: "Bug Report" about: "Report a bug" -title: "[STM32 device name]: [_$YourTitle_]" -labels: '' +title: "[STM32 device name]: $YourTitle" +labels: "" --- Thank you for giving feedback to the stlink project. @@ -12,18 +12,17 @@ This bug report will be deleted without notice when not enough information is pr - [ ] I made serious effort to avoid creating duplicate or nearly similar issue -In order to allow developers and other contributors to isolate and target your respective issue, please take some time to select the check boxes below -and fill out each of the following items appropriate to your specific problem. +In order to allow developers and other contributors to isolate and target your respective issue, please take some time to select the check boxes below and fill out each of the following items appropriate to your specific problem. -- [ ] Programmer/board type: [enter here] (e.g STLink /V1, /V2, /V2-onboard, /V2-clone, /V3) +- [ ] Programmer/board type: [enter here] (e.g STLINK /V1, /V2, /V2-onboard, /V2-clone, /V3) - [ ] Operating system an version: [enter here] (e.g Linux, macOS, Windows) -- [ ] **Stlink tools version** and/or git commit hash: [enter here] (e.g v1.6.1/git-d0416149) -- [ ] Stlink commandline tool name: [enter here] (e.g `st-info`, `st-flash`, `st-util`) +- [ ] **stlink tools version** and/or git commit hash: [enter here] (e.g v1.6.1/git-d0416149) +- [ ] stlink commandline tool name: [enter here] (e.g `st-info`, `st-flash`, `st-trace`, `st-util`) - [ ] Target chip (and board, if applicable): [enter here] (e.g STM32F103C8T6 (NUCLEO-F103RB)) -Futher we kindly ask you to describe the detected problem as detailed as possible and to add debug output if available, by using the following template: +Further we kindly ask you to describe the detected problem as detailed as possible and to add debug output if available, by using the following template: -Commandline-Output: +Commandline output: ``` OUTPUT/ERROR of the commandline tool(s) @@ -33,7 +32,6 @@ Expected/description: `short description of the expected value` - Thank you for your support. The stlink project maintainers diff --git a/.github/ISSUE_TEMPLATE/feature-request.md b/.github/ISSUE_TEMPLATE/feature-request.md index 3de593aa6..ddeb79357 100644 --- a/.github/ISSUE_TEMPLATE/feature-request.md +++ b/.github/ISSUE_TEMPLATE/feature-request.md @@ -1,7 +1,7 @@ --- name: "Feature Request" about: "Suggest an idea for this project" -title: "[feature] [_$YourTitle_]" +title: "[feature] $YourTitle" labels: code/feature-request --- @@ -12,18 +12,17 @@ This feature request will be deleted without notice when not enough information - [ ] I made serious effort to avoid creating duplicate or nearly similar issue -In order to allow developers and other contributors to isolate and target your respective issue, please take some time to select the check boxes below -and fill out each of the following items appropriate to your specific request. +In order to allow developers and other contributors to isolate and target your respective issue, please take some time to select the check boxes below and fill out each of the following items appropriate to your specific request. -- [ ] Programmer/board type: [enter here] (e.g STLink /V1, /V2, /V2-onboard, /V2-clone, /V3) +- [ ] Programmer/board type: [enter here] (e.g STLINK /V1, /V2, /V2-onboard, /V2-clone, /V3) - [ ] Operating system an version: [enter here] (e.g Linux, macOS, Windows) -- [ ] **Stlink tools version** and/or git commit hash: [enter here] (e.g v1.6.1/git-d0416149) -- [ ] Stlink commandline tool name: [enter here] (e.g `st-info`, `st-flash`, `st-util`) +- [ ] **stlink tools version** and/or git commit hash: [enter here] (e.g v1.6.1/git-d0416149) +- [ ] stlink commandline tool name: [enter here] (e.g `st-info`, `st-flash`, `st-trace`, `st-util`) - [ ] Target chip (and board, if applicable): [enter here] (e.g STM32F103C8T6 (NUCLEO-F103RB)) -Futher we kindly ask you to describe the detected problem as detailed as possible and to add debug output if available, by using the following template: +Further we kindly ask you to describe the detected problem as detailed as possible and to add debug output if available, by using the following template: -Commandline-Output: +Commandline output: ``` OUTPUT/ERROR of the commandline tool(s) @@ -33,7 +32,6 @@ Expected/description: `short description of the expected value` - Thank you for your support. The stlink project maintainers diff --git a/.github/workflows/c-cpp.yml b/.github/workflows/c-cpp.yml index e211e4e54..c792612c2 100644 --- a/.github/workflows/c-cpp.yml +++ b/.github/workflows/c-cpp.yml @@ -2,22 +2,330 @@ name: C/C++ CI on: push: - branches: [ testing ] + branches: [develop, testing] pull_request: - branches: [ testing ] + branches: [develop, testing] jobs: - build: + job_linux_1a: + name: ubuntu-20.04 gcc + runs-on: ubuntu-20.04 + steps: + - uses: actions/checkout@v2 + - name: Install dependencies + run: sudo apt-get install gcc-10 libusb-1.0.0-dev libgtk-3-dev rpm + - name: make debug + run: make debug + - name: make test + run: make test + - name: make release + run: make release + - name: make install + run: make install + - name: make package + run: make package + - name: make uninstall + run: make uninstall + - name: make clean + run: make clean + + job_linux_2a: + name: ubuntu-18.04 gcc + runs-on: ubuntu-18.04 + steps: + - uses: actions/checkout@v2 + - name: install dependencies + run: sudo apt-get install gcc-6 libusb-1.0.0-dev libgtk-3-dev rpm + - name: make debug + run: make debug + - name: make test + run: make test + - name: make release + run: make release + - name: make install + run: make install + - name: make package + run: make package + - name: make uninstall + run: make uninstall + - name: make clean + run: make clean + + job_linux_3a: + name: ubuntu-16.04 gcc + runs-on: ubuntu-16.04 + steps: + - uses: actions/checkout@v2 + - name: Install dependencies + run: sudo apt-get install gcc-5 libusb-1.0.0-dev libgtk-3-dev rpm + - name: make debug + run: make debug + - name: make test + run: make test + - name: make release + run: make release + - name: make install + run: make install + - name: make package + run: make package + - name: make uninstall + run: make uninstall + - name: make clean + run: make clean + + job_linux_1b: + name: ubuntu-20.04 clang + runs-on: ubuntu-20.04 + steps: + - uses: actions/checkout@v2 + - name: Install dependencies + run: sudo apt-get install clang-10 libusb-1.0.0-dev libgtk-3-dev rpm + - name: make debug + run: make debug + - name: make test + run: make test + - name: make release + run: make release + - name: make install + run: make install + - name: make package + run: make package + - name: make uninstall + run: make uninstall + - name: make clean + run: make clean + + job_linux_2b: + name: ubuntu-18.04 clang + runs-on: ubuntu-18.04 + steps: + - uses: actions/checkout@v2 + - name: install dependencies + run: sudo apt-get install clang-10 libusb-1.0.0-dev libgtk-3-dev rpm + - name: make debug + run: make debug + - name: make test + run: make test + - name: make release + run: make release + - name: make install + run: make install + - name: make package + run: make package + - name: make uninstall + run: make uninstall + - name: make clean + run: make clean + + job_linux_3b: + name: ubuntu-16.04 clang + runs-on: ubuntu-16.04 + steps: + - uses: actions/checkout@v2 + - name: Install dependencies + run: sudo apt-get install clang libusb-1.0.0-dev libgtk-3-dev rpm + - name: make debug + run: make debug + - name: make test + run: make test + - name: make release + run: make release + - name: make install + run: make install + - name: make package + run: make package + - name: make uninstall + run: make uninstall + - name: make clean + run: make clean + + job_linux_1c: + name: ubuntu-20.04 gcc 32-bit + runs-on: ubuntu-20.04 + steps: + - uses: actions/checkout@v2 + - name: Install dependencies + run: sudo apt-get install gcc-10 libusb-1.0.0-dev libgtk-3-dev rpm + - name: Set compiler flags + run: | + CFLAGS="$CFLAGS -m32" + CXXFLAGS="$CXXFLAGS -m32" + LDFLAGS="$LDFLAGS -m32" + - name: make debug + run: make debug + - name: make test + run: make test + - name: make release + run: make release + - name: make install + run: make install + - name: make package + run: make package + - name: make uninstall + run: make uninstall + - name: make clean + run: make clean + + job_linux_2c: + name: ubuntu-18.04 gcc 32-bit + runs-on: ubuntu-18.04 + steps: + - uses: actions/checkout@v2 + - name: install dependencies + run: sudo apt-get install gcc-6 libusb-1.0.0-dev libgtk-3-dev rpm + - name: Set compiler flags + run: | + CFLAGS="$CFLAGS -m32" + CXXFLAGS="$CXXFLAGS -m32" + LDFLAGS="$LDFLAGS -m32" + - name: make debug + run: make debug + - name: make test + run: make test + - name: make release + run: make release + - name: make install + run: make install + - name: make package + run: make package + - name: make uninstall + run: make uninstall + - name: make clean + run: make clean + + job_linux_3c: + name: ubuntu-16.04 gcc 32-bit + runs-on: ubuntu-16.04 + steps: + - uses: actions/checkout@v2 + - name: Install dependencies + run: sudo apt-get install gcc-5 libusb-1.0.0-dev libgtk-3-dev rpm + - name: Set compiler flags + run: | + CFLAGS="$CFLAGS -m32" + CXXFLAGS="$CXXFLAGS -m32" + LDFLAGS="$LDFLAGS -m32" + - name: make debug + run: make debug + - name: make test + run: make test + - name: make release + run: make release + - name: make install + run: make install + - name: make package + run: make package + - name: make uninstall + run: make uninstall + - name: make clean + run: make clean + + job_linux_4: + name: ubuntu-20.04 mingw64 + runs-on: ubuntu-20.04 + steps: + - uses: actions/checkout@v2 + - name: Install dependencies + run: sudo apt-get install gcc-10 libusb-1.0.0-dev libgtk-3-dev rpm mingw-w64 + - name: make debug + run: make debug + - name: make test + run: make test + - name: make release + run: make release + - name: make install + run: make install + - name: make package + run: make package + - name: make uninstall + run: make uninstall + - name: make clean + run: make clean + + # job_macos_1a: + # name: macos-11.0 gcc + # runs-on: macos-11.0 + # steps: + # - uses: actions/checkout@v2 + # - name: Install dependencies + # run: brew install gcc libusb gtk+3 + # - name: make debug + # run: make debug + # - name: make test + # run: make test + # - name: make release + # run: make release + # - name: make install + # run: make install + # - name: make package + # run: make package + # - name: make uninstall + # run: make uninstall + # - name: make clean + # run: make clean + + job_macos_2a: + name: macos-10.15 gcc + runs-on: macos-10.15 + steps: + - uses: actions/checkout@v2 + - name: Install dependencies + run: brew install gcc libusb gtk+3 + - name: make debug + run: make debug + - name: make test + run: make test + - name: make release + run: make release + - name: make install + run: make install + - name: make package + run: make package + - name: make uninstall + run: make uninstall + - name: make clean + run: make clean - runs-on: ubuntu-latest + # job_macos_1b: + # name: macos-11.0 clang + # runs-on: macos-11.0 + # steps: + # - uses: actions/checkout@v2 + # - name: Install dependencies + # run: brew install llvm libusb gtk+3 + # - name: make debug + # run: make debug + # - name: make test + # run: make test + # - name: make release + # run: make release + # - name: make install + # run: make install + # - name: make package + # run: make package + # - name: make uninstall + # run: make uninstall + # - name: make clean + # run: make clean + job_macos_2b: + name: macos-10.15 clang + runs-on: macos-10.15 steps: - - uses: actions/checkout@v2 - - name: configure - run: ./configure - - name: make - run: make - - name: make check - run: make check - - name: make distcheck - run: make distcheck + - uses: actions/checkout@v2 + - name: Install dependencies + run: brew install llvm libusb gtk+3 + - name: make debug + run: make debug + - name: make test + run: make test + - name: make release + run: make release + - name: make install + run: make install + - name: make package + run: make package + - name: make uninstall + run: make uninstall + - name: make clean + run: make clean diff --git a/.github/workflows/cmake.yml b/.github/workflows/cmake.yml deleted file mode 100644 index 005915e6e..000000000 --- a/.github/workflows/cmake.yml +++ /dev/null @@ -1,46 +0,0 @@ -name: CMake - -on: [push] - -env: - # Customize the CMake build type here (Release, Debug, RelWithDebInfo, etc.) - BUILD_TYPE: Release - -jobs: - build: - # The CMake configure and build commands are platform agnostic and should work equally - # well on Windows or Mac. You can convert this to a matrix build if you need - # cross-platform coverage. - # See: https://docs.github.com/en/free-pro-team@latest/actions/learn-github-actions/managing-complex-workflows#using-a-build-matrix - runs-on: ubuntu-latest - - steps: - - uses: actions/checkout@v2 - - - name: Create Build Environment - # Some projects don't allow in-source building, so create a separate build directory - # We'll use this as our working directory for all subsequent commands - run: cmake -E make_directory ${{github.workspace}}/build - - - name: Configure CMake - # Use a bash shell so we can use the same syntax for environment variable - # access regardless of the host operating system - shell: bash - working-directory: ${{github.workspace}}/build - # Note the current convention is to use the -S and -B options here to specify source - # and build directories, but this is only available with CMake 3.13 and higher. - # The CMake binaries on the Github Actions machines are (as of this writing) 3.12 - run: cmake $GITHUB_WORKSPACE -DCMAKE_BUILD_TYPE=$BUILD_TYPE - - - name: Build - working-directory: ${{github.workspace}}/build - shell: bash - # Execute the build. You can specify a specific target with "--target " - run: cmake --build . --config $BUILD_TYPE - - - name: Test - working-directory: ${{github.workspace}}/build - shell: bash - # Execute tests defined by the CMake configuration. - # See https://cmake.org/cmake/help/latest/manual/ctest.1.html for more detail - run: ctest -C $BUILD_TYPE diff --git a/.travis.sh b/.travis.sh index cc0958bf5..7683af001 100755 --- a/.travis.sh +++ b/.travis.sh @@ -11,61 +11,48 @@ DIR=$PWD if [ "$TRAVIS_JOB_NAME" == "linux-mingw" ]; then echo "--> Building Release for Windows (x86-64) ..." mkdir -p build-mingw && cd build-mingw - echo "-DCMAKE_SYSTEM_NAME=Windows -DTOOLCHAIN_PREFIX=x86_64-w64-mingw32 \ - -DCMAKE_TOOLCHAIN_FILE=$PWD/../cmake/modules/set_toolchain.cmake -DCMAKE_INSTALL_PREFIX=$PWD/install $DIR" cmake -DCMAKE_SYSTEM_NAME=Windows -DTOOLCHAIN_PREFIX=x86_64-w64-mingw32 \ -DCMAKE_TOOLCHAIN_FILE=$PWD/../cmake/modules/set_toolchain.cmake -DCMAKE_INSTALL_PREFIX=$PWD/install $DIR make && rm -rf build-mingw && cd - echo "--> Building Release for Windows (i686) ..." mkdir -p build-mingw && cd build-mingw - echo "-DCMAKE_SYSTEM_NAME=Windows -DTOOLCHAIN_PREFIX=i686-w64-mingw32 \ - -DCMAKE_TOOLCHAIN_FILE=$PWD/../cmake/modules/set_toolchain.cmake -DCMAKE_INSTALL_PREFIX=$PWD/install $DIR" cmake -DCMAKE_SYSTEM_NAME=Windows -DTOOLCHAIN_PREFIX=i686-w64-mingw32 \ -DCMAKE_TOOLCHAIN_FILE=$PWD/../cmake/modules/set_toolchain.cmake -DCMAKE_INSTALL_PREFIX=$PWD/install $DIR make && rm -rf build-mingw && cd - elif [ "$TRAVIS_OS_NAME" == "linux" ]; then sudo apt-get update -qq || true - sudo apt-get install -qq -y --no-install-recommends libgtk-3-dev echo "--> Building Debug..." mkdir -p build/Debug && cd build/Debug - echo "-DCMAKE_BUILD_TYPE=Debug -DCMAKE_INSTALL_PREFIX=$PWD/install" cmake -DCMAKE_BUILD_TYPE=Debug -DCMAKE_INSTALL_PREFIX=$PWD/install $DIR make && cd - echo "--> Building Release with package..." mkdir -p build/Release && cd build/Release - echo "-DCMAKE_BUILD_TYPE=Release -DCMAKE_INSTALL_PREFIX=$PWD/install" cmake -DCMAKE_BUILD_TYPE=Release -DCMAKE_INSTALL_PREFIX=$PWD/install $DIR make package && cd - elif [ "$TRAVIS_OS_NAME" == "osx" ]; then - brew install libusb - echo "--> Building Debug..." mkdir -p build/Debug && cd build/Debug - echo "-DCMAKE_BUILD_TYPE=Debug -DCMAKE_INSTALL_PREFIX=$PWD/install" cmake -DCMAKE_BUILD_TYPE=Debug -DCMAKE_INSTALL_PREFIX=$PWD/install $DIR make && cd - echo "--> Building Release with package..." mkdir -p build/Release && cd build/Release - echo "-DCMAKE_BUILD_TYPE=Release -DCMAKE_INSTALL_PREFIX=$PWD/install" cmake -DCMAKE_BUILD_TYPE=Release -DCMAKE_INSTALL_PREFIX=$PWD/install $DIR make package && cd - else # local test-build echo "--> Building Debug..." mkdir -p build/Debug && cd build/Debug - echo "-DCMAKE_BUILD_TYPE=Debug -DCMAKE_INSTALL_PREFIX=$PWD/install" cmake -DCMAKE_BUILD_TYPE=Debug -DCMAKE_INSTALL_PREFIX=$PWD/install ../../ make && cd - echo "--> Building Release with package..." mkdir -p build/Release && cd build/Release - echo "-DCMAKE_BUILD_TYPE=Release -DCMAKE_INSTALL_PREFIX=$PWD/install" cmake -DCMAKE_BUILD_TYPE=Release -DCMAKE_INSTALL_PREFIX=$PWD/install ../../ make package && cd - fi diff --git a/.travis.yml b/.travis.yml index 5d2e5fbdf..e866cc6ab 100644 --- a/.travis.yml +++ b/.travis.yml @@ -146,7 +146,7 @@ jobs: addons: homebrew: packages: - - clang + - llvm - libusb - gtk+3 diff --git a/README.md b/README.md index 7ddc78005..aafba5988 100644 --- a/README.md +++ b/README.md @@ -6,6 +6,7 @@ ![GitHub commits](https://img.shields.io/github/commits-since/stlink-org/stlink/v1.6.1/develop) ![GitHub activity](https://img.shields.io/github/commit-activity/m/stlink-org/stlink) ![GitHub contributors](https://img.shields.io/github/contributors/stlink-org/stlink) +[![C/C++ CI](https://github.com/stlink-org/stlink/actions/workflows/c-cpp.yml/badge.svg?branch=testing)](https://github.com/stlink-org/stlink/actions/workflows/c-cpp.yml) [![Linux Status](https://img.shields.io/travis/stlink-org/stlink/master?env=BADGE=linux&label=linux)](https://travis-ci.org/stlink-org/stlink) [![macOS Status](https://img.shields.io/travis/stlink-org/stlink/master?env=BADGE=osx&label=osx)](https://travis-ci.org/stlink-org/stlink) From a5a4a687c42045a139d9950036c5adddaa317bf6 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sat, 27 Mar 2021 21:01:31 +0100 Subject: [PATCH 207/503] Updated config for GitHub Actions CI workflow --- .github/workflows/c-cpp.yml | 228 ++++++++++++++++++------------------ 1 file changed, 114 insertions(+), 114 deletions(-) diff --git a/.github/workflows/c-cpp.yml b/.github/workflows/c-cpp.yml index c792612c2..b42d001af 100644 --- a/.github/workflows/c-cpp.yml +++ b/.github/workflows/c-cpp.yml @@ -2,9 +2,9 @@ name: C/C++ CI on: push: - branches: [develop, testing] + branches: [master, develop, testing] pull_request: - branches: [develop, testing] + branches: [master, develop, testing] jobs: job_linux_1a: @@ -20,14 +20,14 @@ jobs: run: make test - name: make release run: make release - - name: make install - run: make install - - name: make package - run: make package - - name: make uninstall - run: make uninstall - - name: make clean - run: make clean + - name: sudo make install + run: sudo make install + - name: sudo make package + run: sudo make package + - name: sudo make uninstall + run: sudo make uninstall + - name: sudo make clean + run: sudo make clean job_linux_2a: name: ubuntu-18.04 gcc @@ -42,14 +42,14 @@ jobs: run: make test - name: make release run: make release - - name: make install - run: make install - - name: make package - run: make package - - name: make uninstall - run: make uninstall - - name: make clean - run: make clean + - name: sudo make install + run: sudo make install + - name: sudo make package + run: sudo make package + - name: sudo make uninstall + run: sudo make uninstall + - name: sudo make clean + run: sudo make clean job_linux_3a: name: ubuntu-16.04 gcc @@ -64,14 +64,14 @@ jobs: run: make test - name: make release run: make release - - name: make install - run: make install - - name: make package - run: make package - - name: make uninstall - run: make uninstall - - name: make clean - run: make clean + - name: sudo make install + run: sudo make install + - name: sudo make package + run: sudo make package + - name: sudo make uninstall + run: sudo make uninstall + - name: sudo make clean + run: sudo make clean job_linux_1b: name: ubuntu-20.04 clang @@ -86,14 +86,14 @@ jobs: run: make test - name: make release run: make release - - name: make install - run: make install - - name: make package - run: make package - - name: make uninstall - run: make uninstall - - name: make clean - run: make clean + - name: sudo make install + run: sudo make install + - name: sudo make package + run: sudo make package + - name: sudo make uninstall + run: sudo make uninstall + - name: sudo make clean + run: sudo make clean job_linux_2b: name: ubuntu-18.04 clang @@ -108,14 +108,14 @@ jobs: run: make test - name: make release run: make release - - name: make install - run: make install - - name: make package - run: make package - - name: make uninstall - run: make uninstall - - name: make clean - run: make clean + - name: sudo make install + run: sudo make install + - name: sudo make package + run: sudo make package + - name: sudo make uninstall + run: sudo make uninstall + - name: sudo make clean + run: sudo make clean job_linux_3b: name: ubuntu-16.04 clang @@ -130,14 +130,14 @@ jobs: run: make test - name: make release run: make release - - name: make install - run: make install - - name: make package - run: make package - - name: make uninstall - run: make uninstall - - name: make clean - run: make clean + - name: sudo make install + run: sudo make install + - name: sudo make package + run: sudo make package + - name: sudo make uninstall + run: sudo make uninstall + - name: sudo make clean + run: sudo make clean job_linux_1c: name: ubuntu-20.04 gcc 32-bit @@ -157,14 +157,14 @@ jobs: run: make test - name: make release run: make release - - name: make install - run: make install - - name: make package - run: make package - - name: make uninstall - run: make uninstall - - name: make clean - run: make clean + - name: sudo make install + run: sudo make install + - name: sudo make package + run: sudo make package + - name: sudo make uninstall + run: sudo make uninstall + - name: sudo make clean + run: sudo make clean job_linux_2c: name: ubuntu-18.04 gcc 32-bit @@ -184,14 +184,14 @@ jobs: run: make test - name: make release run: make release - - name: make install - run: make install - - name: make package - run: make package - - name: make uninstall - run: make uninstall - - name: make clean - run: make clean + - name: sudo make install + run: sudo make install + - name: sudo make package + run: sudo make package + - name: sudo make uninstall + run: sudo make uninstall + - name: sudo make clean + run: sudo make clean job_linux_3c: name: ubuntu-16.04 gcc 32-bit @@ -211,14 +211,14 @@ jobs: run: make test - name: make release run: make release - - name: make install - run: make install - - name: make package - run: make package - - name: make uninstall - run: make uninstall - - name: make clean - run: make clean + - name: sudo make install + run: sudo make install + - name: sudo make package + run: sudo make package + - name: sudo make uninstall + run: sudo make uninstall + - name: sudo make clean + run: sudo make clean job_linux_4: name: ubuntu-20.04 mingw64 @@ -233,14 +233,14 @@ jobs: run: make test - name: make release run: make release - - name: make install - run: make install - - name: make package - run: make package - - name: make uninstall - run: make uninstall - - name: make clean - run: make clean + - name: sudo make install + run: sudo make install + - name: sudo make package + run: sudo make package + - name: sudo make uninstall + run: sudo make uninstall + - name: sudo make clean + run: sudo make clean # job_macos_1a: # name: macos-11.0 gcc @@ -255,14 +255,14 @@ jobs: # run: make test # - name: make release # run: make release - # - name: make install - # run: make install - # - name: make package - # run: make package - # - name: make uninstall - # run: make uninstall - # - name: make clean - # run: make clean + # - name: sudo make install + # run: sudo make install + # - name: sudo make package + # run: sudo make package + # - name: sudo make uninstall + # run: sudo make uninstall + # - name: sudo make clean + # run: sudo make clean job_macos_2a: name: macos-10.15 gcc @@ -277,14 +277,14 @@ jobs: run: make test - name: make release run: make release - - name: make install - run: make install - - name: make package - run: make package - - name: make uninstall - run: make uninstall - - name: make clean - run: make clean + - name: sudo make install + run: sudo make install + - name: sudo make package + run: sudo make package + - name: sudo make uninstall + run: sudo make uninstall + - name: sudo make clean + run: sudo make clean # job_macos_1b: # name: macos-11.0 clang @@ -299,14 +299,14 @@ jobs: # run: make test # - name: make release # run: make release - # - name: make install - # run: make install - # - name: make package - # run: make package - # - name: make uninstall - # run: make uninstall - # - name: make clean - # run: make clean + # - name: sudo make install + # run: sudo make install + # - name: sudo make package + # run: sudo make package + # - name: sudo make uninstall + # run: sudo make uninstall + # - name: sudo make clean + # run: sudo make clean job_macos_2b: name: macos-10.15 clang @@ -321,11 +321,11 @@ jobs: run: make test - name: make release run: make release - - name: make install - run: make install - - name: make package - run: make package - - name: make uninstall - run: make uninstall - - name: make clean - run: make clean + - name: sudo make install + run: sudo make install + - name: sudo make package + run: sudo make package + - name: sudo make uninstall + run: sudo make uninstall + - name: sudo make clean + run: sudo make clean From face74262f879bba5a330c8326064a383cac2b42 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 28 Mar 2021 00:30:33 +0100 Subject: [PATCH 208/503] Updated config for GitHub code scanning alerts --- .github/workflows/codeql-analysis.yml | 60 ++++++++++++++------------- 1 file changed, 31 insertions(+), 29 deletions(-) diff --git a/.github/workflows/codeql-analysis.yml b/.github/workflows/codeql-analysis.yml index 202867cfc..bab5fb048 100644 --- a/.github/workflows/codeql-analysis.yml +++ b/.github/workflows/codeql-analysis.yml @@ -13,12 +13,12 @@ name: "CodeQL" on: push: - branches: [ develop, master ] + branches: [develop, master] pull_request: # The branches below must be a subset of the branches above - branches: [ develop ] + branches: [develop] schedule: - - cron: '23 20 * * 2' + - cron: "23 20 * * 2" jobs: analyze: @@ -28,40 +28,42 @@ jobs: strategy: fail-fast: false matrix: - language: [ 'cpp' ] + language: ["cpp"] # CodeQL supports [ 'cpp', 'csharp', 'go', 'java', 'javascript', 'python' ] # Learn more: # https://docs.github.com/en/free-pro-team@latest/github/finding-security-vulnerabilities-and-errors-in-your-code/configuring-code-scanning#changing-the-languages-that-are-analyzed steps: - - name: Checkout repository - uses: actions/checkout@v2 + - name: Install dependencies + run: sudo apt-get install gcc-10 libusb-1.0.0-dev libgtk-3-dev rpm + - name: Checkout repository + uses: actions/checkout@v2 - # Initializes the CodeQL tools for scanning. - - name: Initialize CodeQL - uses: github/codeql-action/init@v1 - with: - languages: ${{ matrix.language }} - # If you wish to specify custom queries, you can do so here or in a config file. - # By default, queries listed here will override any specified in a config file. - # Prefix the list here with "+" to use these queries and those in the config file. - # queries: ./path/to/local/query, your-org/your-repo/queries@main + # Initializes the CodeQL tools for scanning. + - name: Initialize CodeQL + uses: github/codeql-action/init@v1 + with: + languages: ${{ matrix.language }} + # If you wish to specify custom queries, you can do so here or in a config file. + # By default, queries listed here will override any specified in a config file. + # Prefix the list here with "+" to use these queries and those in the config file. + # queries: ./path/to/local/query, your-org/your-repo/queries@main - # Autobuild attempts to build any compiled languages (C/C++, C#, or Java). - # If this step fails, then you should remove it and run the build manually (see below) - - name: Autobuild - uses: github/codeql-action/autobuild@v1 + # Autobuild attempts to build any compiled languages (C/C++, C#, or Java). + # If this step fails, then you should remove it and run the build manually (see below) + - name: Autobuild + uses: github/codeql-action/autobuild@v1 - # ℹ️ Command-line programs to run using the OS shell. - # 📚 https://git.io/JvXDl + # ℹ️ Command-line programs to run using the OS shell. + # 📚 https://git.io/JvXDl - # ✏️ If the Autobuild fails above, remove it and uncomment the following three lines - # and modify them (or add more) to build your code if your project - # uses a compiled language + # ✏️ If the Autobuild fails above, remove it and uncomment the following three lines + # and modify them (or add more) to build your code if your project + # uses a compiled language - #- run: | - # make bootstrap - # make release + #- run: | + # make bootstrap + # make release - - name: Perform CodeQL Analysis - uses: github/codeql-action/analyze@v1 + - name: Perform CodeQL Analysis + uses: github/codeql-action/analyze@v1 From d10a4f8def8189d4b14fad20b25b75bcf010e563 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 28 Mar 2021 00:35:03 +0100 Subject: [PATCH 209/503] Updated libusb to v1.0.24 --- cmake/modules/Findlibusb.cmake | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/cmake/modules/Findlibusb.cmake b/cmake/modules/Findlibusb.cmake index bc613779d..b3e5c7e2b 100644 --- a/cmake/modules/Findlibusb.cmake +++ b/cmake/modules/Findlibusb.cmake @@ -75,7 +75,7 @@ elseif (WIN32 OR (EXISTS "/etc/debian_version" AND MINGW)) if (NOT LIBUSB_FOUND) # Preparations for installing libusb library - set(LIBUSB_WIN_VERSION 1.0.23) # set libusb version + set(LIBUSB_WIN_VERSION 1.0.24) # set libusb version set(LIBUSB_WIN_ARCHIVE libusb-${LIBUSB_WIN_VERSION}.7z) if (WIN32 AND NOT EXISTS "/etc/debian_version") # ... on native Windows systems set(LIBUSB_WIN_ARCHIVE_PATH ${CMAKE_BINARY_DIR}/${LIBUSB_WIN_ARCHIVE}) @@ -92,7 +92,7 @@ elseif (WIN32 OR (EXISTS "/etc/debian_version" AND MINGW)) message(STATUS "downloading libusb ${LIBUSB_WIN_VERSION}") file(DOWNLOAD https://sourceforge.net/projects/libusb/files/libusb-1.0/libusb-${LIBUSB_WIN_VERSION}/libusb-${LIBUSB_WIN_VERSION}.7z/download - ${LIBUSB_WIN_ARCHIVE_PATH} EXPECTED_MD5 cf3d38d2ff053ef343d10c0b8b0950c2 + ${LIBUSB_WIN_ARCHIVE_PATH} EXPECTED_MD5 5c944b1c8aa9d43e026a94302d0f8ac4 ) endif () From 0496ecff48b7c122c243c4d449e44ad34e8ecba6 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Fri, 2 Apr 2021 16:43:54 +0200 Subject: [PATCH 210/503] Updated config for GitHub code scanning alerts --- .github/workflows/codeql-analysis.yml | 8 ++++---- README.md | 1 + 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/.github/workflows/codeql-analysis.yml b/.github/workflows/codeql-analysis.yml index bab5fb048..26313ecb5 100644 --- a/.github/workflows/codeql-analysis.yml +++ b/.github/workflows/codeql-analysis.yml @@ -13,12 +13,12 @@ name: "CodeQL" on: push: - branches: [develop, master] + branches: [ testing, develop, master ] pull_request: # The branches below must be a subset of the branches above - branches: [develop] + branches: [ testing, develop ] schedule: - - cron: "23 20 * * 2" + - cron: '00 20 * * 1' jobs: analyze: @@ -28,7 +28,7 @@ jobs: strategy: fail-fast: false matrix: - language: ["cpp"] + language: [ 'cpp' ] # CodeQL supports [ 'cpp', 'csharp', 'go', 'java', 'javascript', 'python' ] # Learn more: # https://docs.github.com/en/free-pro-team@latest/github/finding-security-vulnerabilities-and-errors-in-your-code/configuring-code-scanning#changing-the-languages-that-are-analyzed diff --git a/README.md b/README.md index aafba5988..644c3fd86 100644 --- a/README.md +++ b/README.md @@ -6,6 +6,7 @@ ![GitHub commits](https://img.shields.io/github/commits-since/stlink-org/stlink/v1.6.1/develop) ![GitHub activity](https://img.shields.io/github/commit-activity/m/stlink-org/stlink) ![GitHub contributors](https://img.shields.io/github/contributors/stlink-org/stlink) +[![CodeQL](https://github.com/stlink-org/stlink/actions/workflows/codeql-analysis.yml/badge.svg)](https://github.com/stlink-org/stlink/actions/workflows/codeql-analysis.yml) [![C/C++ CI](https://github.com/stlink-org/stlink/actions/workflows/c-cpp.yml/badge.svg?branch=testing)](https://github.com/stlink-org/stlink/actions/workflows/c-cpp.yml) [![Linux Status](https://img.shields.io/travis/stlink-org/stlink/master?env=BADGE=linux&label=linux)](https://travis-ci.org/stlink-org/stlink) [![macOS Status](https://img.shields.io/travis/stlink-org/stlink/master?env=BADGE=osx&label=osx)](https://travis-ci.org/stlink-org/stlink) From eebcb1acc8a29a156276852eb730e961883a9e71 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Fri, 2 Apr 2021 18:34:31 +0200 Subject: [PATCH 211/503] Revert "Updated libusb to v1.0.24" This reverts commit d10a4f8def8189d4b14fad20b25b75bcf010e563. --- cmake/modules/Findlibusb.cmake | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/cmake/modules/Findlibusb.cmake b/cmake/modules/Findlibusb.cmake index b3e5c7e2b..bc613779d 100644 --- a/cmake/modules/Findlibusb.cmake +++ b/cmake/modules/Findlibusb.cmake @@ -75,7 +75,7 @@ elseif (WIN32 OR (EXISTS "/etc/debian_version" AND MINGW)) if (NOT LIBUSB_FOUND) # Preparations for installing libusb library - set(LIBUSB_WIN_VERSION 1.0.24) # set libusb version + set(LIBUSB_WIN_VERSION 1.0.23) # set libusb version set(LIBUSB_WIN_ARCHIVE libusb-${LIBUSB_WIN_VERSION}.7z) if (WIN32 AND NOT EXISTS "/etc/debian_version") # ... on native Windows systems set(LIBUSB_WIN_ARCHIVE_PATH ${CMAKE_BINARY_DIR}/${LIBUSB_WIN_ARCHIVE}) @@ -92,7 +92,7 @@ elseif (WIN32 OR (EXISTS "/etc/debian_version" AND MINGW)) message(STATUS "downloading libusb ${LIBUSB_WIN_VERSION}") file(DOWNLOAD https://sourceforge.net/projects/libusb/files/libusb-1.0/libusb-${LIBUSB_WIN_VERSION}/libusb-${LIBUSB_WIN_VERSION}.7z/download - ${LIBUSB_WIN_ARCHIVE_PATH} EXPECTED_MD5 5c944b1c8aa9d43e026a94302d0f8ac4 + ${LIBUSB_WIN_ARCHIVE_PATH} EXPECTED_MD5 cf3d38d2ff053ef343d10c0b8b0950c2 ) endif () From 32ba234b305a8fa3ffdd5cd825a72973ad94a512 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Fri, 2 Apr 2021 18:36:05 +0200 Subject: [PATCH 212/503] Revert "Updated libusb to v1.0.24" This reverts commit d10a4f8def8189d4b14fad20b25b75bcf010e563. --- cmake/modules/Findlibusb.cmake | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/cmake/modules/Findlibusb.cmake b/cmake/modules/Findlibusb.cmake index b3e5c7e2b..bc613779d 100644 --- a/cmake/modules/Findlibusb.cmake +++ b/cmake/modules/Findlibusb.cmake @@ -75,7 +75,7 @@ elseif (WIN32 OR (EXISTS "/etc/debian_version" AND MINGW)) if (NOT LIBUSB_FOUND) # Preparations for installing libusb library - set(LIBUSB_WIN_VERSION 1.0.24) # set libusb version + set(LIBUSB_WIN_VERSION 1.0.23) # set libusb version set(LIBUSB_WIN_ARCHIVE libusb-${LIBUSB_WIN_VERSION}.7z) if (WIN32 AND NOT EXISTS "/etc/debian_version") # ... on native Windows systems set(LIBUSB_WIN_ARCHIVE_PATH ${CMAKE_BINARY_DIR}/${LIBUSB_WIN_ARCHIVE}) @@ -92,7 +92,7 @@ elseif (WIN32 OR (EXISTS "/etc/debian_version" AND MINGW)) message(STATUS "downloading libusb ${LIBUSB_WIN_VERSION}") file(DOWNLOAD https://sourceforge.net/projects/libusb/files/libusb-1.0/libusb-${LIBUSB_WIN_VERSION}/libusb-${LIBUSB_WIN_VERSION}.7z/download - ${LIBUSB_WIN_ARCHIVE_PATH} EXPECTED_MD5 5c944b1c8aa9d43e026a94302d0f8ac4 + ${LIBUSB_WIN_ARCHIVE_PATH} EXPECTED_MD5 cf3d38d2ff053ef343d10c0b8b0950c2 ) endif () From e0f7552fc1a13990f70da863c5fdaa1f64be649f Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sat, 3 Apr 2021 14:53:16 +0200 Subject: [PATCH 213/503] Updated CI build configuration - Ensure clean build system for all build targets - Rearranged & renamed build jobs - Completed set of 32-bit & 64-bit builds - Updated notifications for MinGW cross build - Added macOS 10.14 build environment for Travis CI --- .github/workflows/c-cpp.yml | 387 +++++++++++++++++++-------------- .travis.sh | 4 +- .travis.yml | 177 +++++---------- cmake/modules/Findlibusb.cmake | 2 + 4 files changed, 281 insertions(+), 289 deletions(-) diff --git a/.github/workflows/c-cpp.yml b/.github/workflows/c-cpp.yml index b42d001af..4769450ae 100644 --- a/.github/workflows/c-cpp.yml +++ b/.github/workflows/c-cpp.yml @@ -7,95 +7,145 @@ on: branches: [master, develop, testing] jobs: - job_linux_1a: - name: ubuntu-20.04 gcc - runs-on: ubuntu-20.04 + +# Linux + + job_linux_16_04_64_gcc: + name: ubuntu-16.04 gcc + runs-on: ubuntu-16.04 steps: - uses: actions/checkout@v2 - name: Install dependencies - run: sudo apt-get install gcc-10 libusb-1.0.0-dev libgtk-3-dev rpm + run: sudo apt-get install gcc-5 libusb-1.0.0-dev libgtk-3-dev rpm - name: make debug - run: make debug + run: sudo make clean && make debug - name: make test - run: make test + run: sudo make clean && make test - name: make release - run: make release + run: sudo make clean && make release - name: sudo make install - run: sudo make install + run: sudo make clean && sudo make install - name: sudo make package run: sudo make package - name: sudo make uninstall - run: sudo make uninstall - - name: sudo make clean - run: sudo make clean + run: sudo make uninstall && sudo make clean - job_linux_2a: - name: ubuntu-18.04 gcc - runs-on: ubuntu-18.04 + job_linux_16_04_32_gcc: + name: ubuntu-16.04 gcc 32-bit + runs-on: ubuntu-16.04 steps: - uses: actions/checkout@v2 - - name: install dependencies - run: sudo apt-get install gcc-6 libusb-1.0.0-dev libgtk-3-dev rpm + - name: Install dependencies + run: sudo apt-get install gcc-5 libusb-1.0.0-dev libgtk-3-dev rpm + - name: Set compiler flags + run: | + CFLAGS="$CFLAGS -m32" + CXXFLAGS="$CXXFLAGS -m32" + LDFLAGS="$LDFLAGS -m32" - name: make debug - run: make debug + run: sudo make clean && make debug - name: make test - run: make test + run: sudo make clean && make test - name: make release - run: make release + run: sudo make clean && make release - name: sudo make install - run: sudo make install + run: sudo make clean && sudo make install - name: sudo make package run: sudo make package - name: sudo make uninstall - run: sudo make uninstall - - name: sudo make clean - run: sudo make clean + run: sudo make uninstall && sudo make clean - job_linux_3a: - name: ubuntu-16.04 gcc + job_linux_16_04_64_clang: + name: ubuntu-16.04 clang runs-on: ubuntu-16.04 steps: - uses: actions/checkout@v2 - name: Install dependencies - run: sudo apt-get install gcc-5 libusb-1.0.0-dev libgtk-3-dev rpm + run: sudo apt-get install clang-3.5 libusb-1.0.0-dev libgtk-3-dev rpm - name: make debug - run: make debug + run: sudo make clean && make debug - name: make test - run: make test + run: sudo make clean && make test - name: make release - run: make release + run: sudo make clean && make release - name: sudo make install - run: sudo make install + run: sudo make clean && sudo make install - name: sudo make package run: sudo make package - name: sudo make uninstall - run: sudo make uninstall - - name: sudo make clean - run: sudo make clean + run: sudo make uninstall && sudo make clean - job_linux_1b: - name: ubuntu-20.04 clang - runs-on: ubuntu-20.04 + job_linux_16_04_32_clang: + name: ubuntu-16.04 clang 32-bit + runs-on: ubuntu-16.04 steps: - uses: actions/checkout@v2 - name: Install dependencies - run: sudo apt-get install clang-10 libusb-1.0.0-dev libgtk-3-dev rpm + run: sudo apt-get install clang-3.5 libusb-1.0.0-dev libgtk-3-dev rpm + - name: Set compiler flags + run: | + CFLAGS="$CFLAGS -m32" + CXXFLAGS="$CXXFLAGS -m32" + LDFLAGS="$LDFLAGS -m32" + - name: make debug + run: sudo make clean && make debug + - name: make test + run: sudo make clean && make test + - name: make release + run: sudo make clean && make release + - name: sudo make install + run: sudo make clean && sudo make install + - name: sudo make package + run: sudo make package + - name: sudo make uninstall + run: sudo make uninstall && sudo make clean + + job_linux_18_04_64_gcc: + name: ubuntu-18.04 gcc + runs-on: ubuntu-18.04 + steps: + - uses: actions/checkout@v2 + - name: install dependencies + run: sudo apt-get install gcc-6 libusb-1.0.0-dev libgtk-3-dev rpm - name: make debug - run: make debug + run: sudo make clean && make debug - name: make test - run: make test + run: sudo make clean && make test - name: make release - run: make release + run: sudo make clean && make release - name: sudo make install - run: sudo make install + run: sudo make clean && sudo make install - name: sudo make package run: sudo make package - name: sudo make uninstall - run: sudo make uninstall - - name: sudo make clean - run: sudo make clean + run: sudo make uninstall && sudo make clean - job_linux_2b: + job_linux_18_04_32_gcc: + name: ubuntu-18.04 gcc 32-bit + runs-on: ubuntu-18.04 + steps: + - uses: actions/checkout@v2 + - name: install dependencies + run: sudo apt-get install gcc-6 libusb-1.0.0-dev libgtk-3-dev rpm + - name: Set compiler flags + run: | + CFLAGS="$CFLAGS -m32" + CXXFLAGS="$CXXFLAGS -m32" + LDFLAGS="$LDFLAGS -m32" + - name: make debug + run: sudo make clean && make debug + - name: make test + run: sudo make clean && make test + - name: make release + run: sudo make clean && make release + - name: sudo make install + run: sudo make clean && sudo make install + - name: sudo make package + run: sudo make package + - name: sudo make uninstall + run: sudo make uninstall && sudo make clean + + job_linux_18_04_64_clang: name: ubuntu-18.04 clang runs-on: ubuntu-18.04 steps: @@ -103,43 +153,64 @@ jobs: - name: install dependencies run: sudo apt-get install clang-10 libusb-1.0.0-dev libgtk-3-dev rpm - name: make debug - run: make debug + run: sudo make clean && make debug - name: make test - run: make test + run: sudo make clean && make test - name: make release - run: make release + run: sudo make clean && make release - name: sudo make install - run: sudo make install + run: sudo make clean && sudo make install - name: sudo make package run: sudo make package - name: sudo make uninstall - run: sudo make uninstall - - name: sudo make clean - run: sudo make clean + run: sudo make uninstall && sudo make clean - job_linux_3b: - name: ubuntu-16.04 clang - runs-on: ubuntu-16.04 + job_linux_18_04_32_clang: + name: ubuntu-18.04 clang 32-bit + runs-on: ubuntu-18.04 + steps: + - uses: actions/checkout@v2 + - name: Install dependencies + run: sudo apt-get install clang-10 libusb-1.0.0-dev libgtk-3-dev rpm + - name: Set compiler flags + run: | + CFLAGS="$CFLAGS -m32" + CXXFLAGS="$CXXFLAGS -m32" + LDFLAGS="$LDFLAGS -m32" + - name: make debug + run: sudo make clean && make debug + - name: make test + run: sudo make clean && make test + - name: make release + run: sudo make clean && make release + - name: sudo make install + run: sudo make clean && sudo make install + - name: sudo make package + run: sudo make package + - name: sudo make uninstall + run: sudo make uninstall && sudo make clean + + job_linux_20_04_64_gcc: + name: ubuntu-20.04 gcc + runs-on: ubuntu-20.04 steps: - uses: actions/checkout@v2 - name: Install dependencies - run: sudo apt-get install clang libusb-1.0.0-dev libgtk-3-dev rpm + run: sudo apt-get install gcc-10 libusb-1.0.0-dev libgtk-3-dev rpm - name: make debug - run: make debug + run: sudo make clean && make debug - name: make test - run: make test + run: sudo make clean && make test - name: make release - run: make release + run: sudo make clean && make release - name: sudo make install - run: sudo make install + run: sudo make clean && sudo make install - name: sudo make package run: sudo make package - name: sudo make uninstall - run: sudo make uninstall - - name: sudo make clean - run: sudo make clean + run: sudo make uninstall && sudo make clean - job_linux_1c: + job_linux_20_04_32_gcc: name: ubuntu-20.04 gcc 32-bit runs-on: ubuntu-20.04 steps: @@ -152,97 +223,106 @@ jobs: CXXFLAGS="$CXXFLAGS -m32" LDFLAGS="$LDFLAGS -m32" - name: make debug - run: make debug + run: sudo make clean && make debug - name: make test - run: make test + run: sudo make clean && make test - name: make release - run: make release + run: sudo make clean && make release - name: sudo make install - run: sudo make install + run: sudo make clean && sudo make install - name: sudo make package run: sudo make package - name: sudo make uninstall - run: sudo make uninstall - - name: sudo make clean - run: sudo make clean + run: sudo make uninstall && sudo make clean - job_linux_2c: - name: ubuntu-18.04 gcc 32-bit - runs-on: ubuntu-18.04 + job_linux_20_04_64_clang: + name: ubuntu-20.04 clang + runs-on: ubuntu-20.04 steps: - uses: actions/checkout@v2 - - name: install dependencies - run: sudo apt-get install gcc-6 libusb-1.0.0-dev libgtk-3-dev rpm - - name: Set compiler flags - run: | - CFLAGS="$CFLAGS -m32" - CXXFLAGS="$CXXFLAGS -m32" - LDFLAGS="$LDFLAGS -m32" + - name: Install dependencies + run: sudo apt-get install clang-10 libusb-1.0.0-dev libgtk-3-dev rpm - name: make debug - run: make debug + run: sudo make clean && make debug - name: make test - run: make test + run: sudo make clean && make test - name: make release - run: make release + run: sudo make clean && make release - name: sudo make install - run: sudo make install + run: sudo make clean && sudo make install - name: sudo make package run: sudo make package - name: sudo make uninstall - run: sudo make uninstall - - name: sudo make clean - run: sudo make clean + run: sudo make uninstall && sudo make clean - job_linux_3c: - name: ubuntu-16.04 gcc 32-bit - runs-on: ubuntu-16.04 + job_linux_20_04_32_clang: + name: ubuntu-20.04 clang 32-bit + runs-on: ubuntu-20.04 steps: - uses: actions/checkout@v2 - name: Install dependencies - run: sudo apt-get install gcc-5 libusb-1.0.0-dev libgtk-3-dev rpm + run: sudo apt-get install clang-10 libusb-1.0.0-dev libgtk-3-dev rpm - name: Set compiler flags run: | CFLAGS="$CFLAGS -m32" CXXFLAGS="$CXXFLAGS -m32" LDFLAGS="$LDFLAGS -m32" - name: make debug - run: make debug + run: sudo make clean && make debug - name: make test - run: make test + run: sudo make clean && make test - name: make release - run: make release + run: sudo make clean && make release - name: sudo make install - run: sudo make install + run: sudo make clean && sudo make install - name: sudo make package run: sudo make package - name: sudo make uninstall - run: sudo make uninstall - - name: sudo make clean - run: sudo make clean + run: sudo make uninstall && sudo make clean - job_linux_4: - name: ubuntu-20.04 mingw64 - runs-on: ubuntu-20.04 +# macOS + + job_macos_10_15_gcc: + name: macos-10.15 gcc + runs-on: macos-10.15 + steps: + - uses: actions/checkout@v2 + - name: Install dependencies + run: brew install gcc libusb gtk+3 + - name: make debug + run: sudo make clean && make debug + - name: make test + run: sudo make clean && make test + - name: make release + run: sudo make clean && make release + - name: sudo make install + run: sudo make clean && sudo make install + - name: sudo make package + run: sudo make package + - name: sudo make uninstall + run: sudo make uninstall && sudo make clean + + job_macos_10_15_clang: + name: macos-10.15 clang + runs-on: macos-10.15 steps: - uses: actions/checkout@v2 - name: Install dependencies - run: sudo apt-get install gcc-10 libusb-1.0.0-dev libgtk-3-dev rpm mingw-w64 + run: brew install llvm libusb gtk+3 - name: make debug - run: make debug + run: sudo make clean && make debug - name: make test - run: make test + run: sudo make clean && make test - name: make release - run: make release + run: sudo make clean && make release - name: sudo make install - run: sudo make install + run: sudo make clean && sudo make install - name: sudo make package run: sudo make package - name: sudo make uninstall - run: sudo make uninstall - - name: sudo make clean - run: sudo make clean + run: sudo make uninstall && sudo make clean - # job_macos_1a: + # job_macos_11_gcc: # name: macos-11.0 gcc # runs-on: macos-11.0 # steps: @@ -250,43 +330,19 @@ jobs: # - name: Install dependencies # run: brew install gcc libusb gtk+3 # - name: make debug - # run: make debug + # run: sudo make clean && make debug # - name: make test - # run: make test + # run: sudo make clean && make test # - name: make release - # run: make release + # run: sudo make clean && make release # - name: sudo make install - # run: sudo make install + # run: sudo make clean && sudo make install # - name: sudo make package # run: sudo make package # - name: sudo make uninstall - # run: sudo make uninstall - # - name: sudo make clean - # run: sudo make clean + # run: sudo make uninstall && sudo make clean - job_macos_2a: - name: macos-10.15 gcc - runs-on: macos-10.15 - steps: - - uses: actions/checkout@v2 - - name: Install dependencies - run: brew install gcc libusb gtk+3 - - name: make debug - run: make debug - - name: make test - run: make test - - name: make release - run: make release - - name: sudo make install - run: sudo make install - - name: sudo make package - run: sudo make package - - name: sudo make uninstall - run: sudo make uninstall - - name: sudo make clean - run: sudo make clean - - # job_macos_1b: + # job_macos_11_clang: # name: macos-11.0 clang # runs-on: macos-11.0 # steps: @@ -294,38 +350,31 @@ jobs: # - name: Install dependencies # run: brew install llvm libusb gtk+3 # - name: make debug - # run: make debug + # run: sudo make clean && make debug # - name: make test - # run: make test + # run: sudo make clean && make test # - name: make release - # run: make release + # run: sudo make clean && make release # - name: sudo make install - # run: sudo make install + # run: sudo make clean && sudo make install # - name: sudo make package # run: sudo make package # - name: sudo make uninstall - # run: sudo make uninstall - # - name: sudo make clean - # run: sudo make clean + # run: sudo make uninstall && sudo make clean - job_macos_2b: - name: macos-10.15 clang - runs-on: macos-10.15 - steps: - - uses: actions/checkout@v2 - - name: Install dependencies - run: brew install llvm libusb gtk+3 - - name: make debug - run: make debug - - name: make test - run: make test - - name: make release - run: make release - - name: sudo make install - run: sudo make install - - name: sudo make package - run: sudo make package - - name: sudo make uninstall - run: sudo make uninstall - - name: sudo make clean - run: sudo make clean +# Linux MinGW cross compliation + + # job_linux_20_04_cross: + # name: ubuntu-20.04 mingw64 + # runs-on: ubuntu-20.04 + # steps: + # - uses: actions/checkout@v2 + # - name: Install dependencies + # run: sudo apt-get install gcc-10 libusb-1.0.0-dev libgtk-3-dev rpm mingw-w64 + # - name: Building Release for Windows (x86-64) ... + # run: sudo mkdir -p build-mingw && cd build-mingw && sudo cmake \ + # -DCMAKE_SYSTEM_NAME=Windows \ + # -DTOOLCHAIN_PREFIX=x86_64-w64-mingw32 \ + # -DCMAKE_TOOLCHAIN_FILE=$PWD/../cmake/modules/set_toolchain.cmake \ + # -DCMAKE_INSTALL_PREFIX=$PWD/install $PWD && \ + # sudo make && sudo rm -rf build-mingw && cd - diff --git a/.travis.sh b/.travis.sh index 7683af001..de2a42372 100755 --- a/.travis.sh +++ b/.travis.sh @@ -9,13 +9,13 @@ echo "WORK DIR:$DIR" DIR=$PWD if [ "$TRAVIS_JOB_NAME" == "linux-mingw" ]; then - echo "--> Building Release for Windows (x86-64) ..." + echo "--> Building for Windows (x86-64) ..." mkdir -p build-mingw && cd build-mingw cmake -DCMAKE_SYSTEM_NAME=Windows -DTOOLCHAIN_PREFIX=x86_64-w64-mingw32 \ -DCMAKE_TOOLCHAIN_FILE=$PWD/../cmake/modules/set_toolchain.cmake -DCMAKE_INSTALL_PREFIX=$PWD/install $DIR make && rm -rf build-mingw && cd - - echo "--> Building Release for Windows (i686) ..." + echo "--> Building for Windows (i686) ..." mkdir -p build-mingw && cd build-mingw cmake -DCMAKE_SYSTEM_NAME=Windows -DTOOLCHAIN_PREFIX=i686-w64-mingw32 \ -DCMAKE_TOOLCHAIN_FILE=$PWD/../cmake/modules/set_toolchain.cmake -DCMAKE_INSTALL_PREFIX=$PWD/install $DIR diff --git a/.travis.yml b/.travis.yml index e866cc6ab..2a788fd69 100644 --- a/.travis.yml +++ b/.travis.yml @@ -2,23 +2,7 @@ language: c jobs: include: - ### 64-bit builds on AMD64 ### - - os: linux - dist: xenial - env: BADGE=linux - compiler: gcc-5 - addons: - apt: - sources: ["ubuntu-toolchain-r-test"] - packages: ["gcc-5", "libusb-1.0.0-dev", "libgtk-3-dev", "rpm"] - - os: linux - dist: bionic - env: BADGE=linux - compiler: gcc-6 - addons: - apt: - sources: ["ubuntu-toolchain-r-test"] - packages: ["gcc-6", "libusb-1.0.0-dev", "libgtk-3-dev", "rpm"] + ### 64-bit build on AMD64 ### - os: linux dist: focal env: BADGE=linux @@ -27,30 +11,18 @@ jobs: apt: sources: ["ubuntu-toolchain-r-test"] packages: ["gcc-10", "libusb-1.0.0-dev", "libgtk-3-dev", "rpm"] - - os: linux - dist: xenial - env: BADGE=linux - compiler: clang - addons: - apt: - sources: ["ubuntu-toolchain-r-test"] - packages: ["libusb-1.0.0-dev", "libgtk-3-dev", "rpm"] - - os: linux - dist: bionic - env: BADGE=linux - compiler: clang-10 - addons: - apt: - sources: ["ubuntu-toolchain-r-test"] - packages: ["clang-10", "libusb-1.0.0-dev", "libgtk-3-dev", "rpm"] + + ### 32-bit build on AMD64 ### - os: linux dist: focal env: BADGE=linux - compiler: clang-10 + compiler: gcc-10 addons: apt: sources: ["ubuntu-toolchain-r-test"] - packages: ["clang-10", "libusb-1.0.0-dev", "libgtk-3-dev", "rpm"] + packages: ["gcc-10", "libusb-1.0.0-dev", "libgtk-3-dev", "rpm"] + before_install: + - CFLAGS="$CFLAGS -m32"; CXXFLAGS="$CXXFLAGS -m32"; LDFLAGS="$LDFLAGS -m32"; ### cross build on AMD64 ### - os: linux @@ -63,92 +35,61 @@ jobs: sources: ["ubuntu-toolchain-r-test"] packages: ["gcc-10", "libusb-1.0.0-dev", "libgtk-3-dev", "rpm", "mingw-w64"] - - ### 32-bit builds on AMD64 ### - - os: linux - dist: xenial - env: BADGE=linux - compiler: gcc-5 - addons: - apt: - sources: ["ubuntu-toolchain-r-test"] - packages: ["gcc-5", "libusb-1.0.0-dev", "libgtk-3-dev", "rpm"] - before_install: - - CFLAGS="$CFLAGS -m32"; CXXFLAGS="$CXXFLAGS -m32"; LDFLAGS="$LDFLAGS -m32"; - - os: linux - dist: bionic - env: BADGE=linux - compiler: gcc-6 - addons: - apt: - sources: ["ubuntu-toolchain-r-test"] - packages: ["gcc-6", "libusb-1.0.0-dev", "libgtk-3-dev", "rpm"] - before_install: - - CFLAGS="$CFLAGS -m32"; CXXFLAGS="$CXXFLAGS -m32"; LDFLAGS="$LDFLAGS -m32"; - - os: linux - dist: focal - env: BADGE=linux - compiler: gcc-10 - addons: - apt: - sources: ["ubuntu-toolchain-r-test"] - packages: ["gcc-10", "libusb-1.0.0-dev", "libgtk-3-dev", "rpm"] - before_install: - - CFLAGS="$CFLAGS -m32"; CXXFLAGS="$CXXFLAGS -m32"; LDFLAGS="$LDFLAGS -m32"; - - os: linux - dist: xenial - env: BADGE=linux - compiler: clang - addons: - apt: - sources: ["ubuntu-toolchain-r-test"] - packages: ["libusb-1.0.0-dev", "libgtk-3-dev", "rpm"] before_install: - - CFLAGS="$CFLAGS -m32"; CXXFLAGS="$CXXFLAGS -m32"; LDFLAGS="$LDFLAGS -m32"; - - os: linux - dist: bionic - env: BADGE=linux - compiler: clang-10 - addons: - apt: - sources: ["ubuntu-toolchain-r-test"] - packages: ["clang-10", "libusb-1.0.0-dev", "libgtk-3-dev", "rpm"] - before_install: - - CFLAGS="$CFLAGS -m32"; CXXFLAGS="$CXXFLAGS -m32"; LDFLAGS="$LDFLAGS -m32"; - - os: linux - dist: focal - env: BADGE=linux - compiler: clang-10 - addons: - apt: - sources: ["ubuntu-toolchain-r-test"] - packages: ["clang-10", "libusb-1.0.0-dev", "libgtk-3-dev", "rpm"] - before_install: - - CFLAGS="$CFLAGS -m32"; CXXFLAGS="$CXXFLAGS -m32"; LDFLAGS="$LDFLAGS -m32"; + - LDFLAGS="$LDFLAGS -NDEBUG"; ### macOS ### - - os: osx - env: BADGE=osx - osx_image: xcode12.2 - name: macOS 10.15.7 - compiler: gcc - addons: - homebrew: - packages: - - gcc - - libusb - - gtk+3 - - os: osx - env: BADGE=osx - osx_image: xcode12.2 - name: macOS 10.15.7 - compiler: clang - addons: - homebrew: - packages: - - llvm - - libusb - - gtk+3 + # - os: osx + # env: BADGE=osx + # osx_image: xcode11.3 + # name: macOS 10.14.6 gcc + # compiler: gcc + # addons: + # homebrew: + # packages: + # - gcc + # - libusb + # - gtk+3 + + # - os: osx + # env: BADGE=osx + # osx_image: xcode11.3 + # name: macOS 10.14.6 gcc 32-bit + # compiler: gcc + # addons: + # homebrew: + # packages: + # - gcc + # - libusb + # - gtk+3 + # before_install: + # - CFLAGS="$CFLAGS -m32"; CXXFLAGS="$CXXFLAGS -m32"; LDFLAGS="$LDFLAGS -m32"; + + # - os: osx + # env: BADGE=osx + # osx_image: xcode11.3 + # name: macOS 10.14.6 clang + # compiler: clang + # addons: + # homebrew: + # packages: + # - llvm + # - libusb + # - gtk+3 + + # - os: osx + # env: BADGE=osx + # osx_image: xcode11.3 + # name: macOS 10.14.6 clang 32-bit + # compiler: clang + # addons: + # homebrew: + # packages: + # - llvm + # - libusb + # - gtk+3 + # before_install: + # - CFLAGS="$CFLAGS -m32"; CXXFLAGS="$CXXFLAGS -m32"; LDFLAGS="$LDFLAGS -m32"; script: - git fetch --tags diff --git a/cmake/modules/Findlibusb.cmake b/cmake/modules/Findlibusb.cmake index bc613779d..3082a9509 100644 --- a/cmake/modules/Findlibusb.cmake +++ b/cmake/modules/Findlibusb.cmake @@ -46,8 +46,10 @@ elseif (CMAKE_SYSTEM_NAME STREQUAL "FreeBSD") elseif (WIN32 OR (EXISTS "/etc/debian_version" AND MINGW)) # Windows or MinGW-toolchain on Debian # for MinGW/MSYS/MSVC: 64-bit or 32-bit? if (CMAKE_SIZEOF_VOID_P EQUAL 8) + message(STATUS "=== Building for Windows (x86-64) ===") set(ARCH 64) else () + message(STATUS "=== Building for Windowsm (i686) ===") set(ARCH 32) endif () From 7cfab876e73f994c95697ba1b09a0a18c2602597 Mon Sep 17 00:00:00 2001 From: anton Date: Sat, 27 Mar 2021 19:14:37 +0500 Subject: [PATCH 214/503] flash_loader: fix typo in the stm32l4 loader --- flashloaders/stm32l4.s | 6 +++--- src/stlink-lib/flash_loader.c | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/flashloaders/stm32l4.s b/flashloaders/stm32l4.s index 21e926f49..50676be9a 100644 --- a/flashloaders/stm32l4.s +++ b/flashloaders/stm32l4.s @@ -12,7 +12,7 @@ .global copy copy: ldr r12, flash_base - ldr r10, flash_off_bsy + ldr r10, flash_off_sr add r10, r10, r12 loop: @@ -44,5 +44,5 @@ exit: .align 2 flash_base: .word 0x40022000 -flash_off_bsy: - .word 0x12 +flash_off_sr: + .word 0x10 diff --git a/src/stlink-lib/flash_loader.c b/src/stlink-lib/flash_loader.c index 9fa897ccc..20fd6aeed 100644 --- a/src/stlink-lib/flash_loader.c +++ b/src/stlink-lib/flash_loader.c @@ -114,7 +114,7 @@ static const uint8_t loader_code_stm32l4[] = { 0x08, 0x3a, 0xf0, 0xdc, 0x00, 0xbe, 0x00, 0xbf, 0x00, 0x20, 0x02, 0x40, - 0x12, 0x00, 0x00, 0x00 + 0x10, 0x00, 0x00, 0x00 }; static const uint8_t loader_code_stm32f7[] = { From c0653f6595e1c564f5a762982ef0c23a00ff3dea Mon Sep 17 00:00:00 2001 From: anton Date: Sat, 27 Mar 2021 19:17:13 +0500 Subject: [PATCH 215/503] flash_loader: improved handling errors --- flashloaders/Makefile | 2 +- src/stlink-lib/flash_loader.c | 19 +++++++++++++++++-- 2 files changed, 18 insertions(+), 3 deletions(-) diff --git a/flashloaders/Makefile b/flashloaders/Makefile index d4ca4d22a..8b01d5293 100644 --- a/flashloaders/Makefile +++ b/flashloaders/Makefile @@ -31,7 +31,7 @@ stm32vl.o: stm32f0.s $(CC) stm32f0.s $(CFLAGS_ARMV7_M) -o stm32vl.o # generic rule for all other ARMv7-M -%.o: *.s +%.o: %.s $(CC) $< $(CFLAGS_ARMV7_M) -o $@ clean: diff --git a/src/stlink-lib/flash_loader.c b/src/stlink-lib/flash_loader.c index 20fd6aeed..aea60f258 100644 --- a/src/stlink-lib/flash_loader.c +++ b/src/stlink-lib/flash_loader.c @@ -154,6 +154,7 @@ static const uint8_t loader_code_stm32f7_lv[] = { int stlink_flash_loader_init(stlink_t *sl, flash_loader_t *fl) { size_t size = 0; + uint32_t dfsr, cfsr, hfsr; // allocate the loader in SRAM if (stlink_flash_loader_write_to_sram(sl, &fl->loader_addr, &size) == -1) { @@ -165,6 +166,20 @@ int stlink_flash_loader_init(stlink_t *sl, flash_loader_t *fl) { fl->buf_addr = fl->loader_addr + (uint32_t)size; ILOG("Successfully loaded flash loader in sram\n"); + /* Clear Fault Status Register for handling flash loader error */ + if (!stlink_read_debug32(sl, STLINK_REG_DFSR, &dfsr) && dfsr) { + ILOG("Clear DFSR\n"); + stlink_write_debug32(sl, STLINK_REG_DFSR, dfsr); + } + if (!stlink_read_debug32(sl, STLINK_REG_CFSR, &cfsr) && cfsr) { + ILOG("Clear CFSR\n"); + stlink_write_debug32(sl, STLINK_REG_CFSR, cfsr); + } + if (!stlink_read_debug32(sl, STLINK_REG_HFSR, &hfsr) && hfsr) { + ILOG("Clear HFSR\n"); + stlink_write_debug32(sl, STLINK_REG_HFSR, hfsr); + } + return(0); } @@ -348,7 +363,7 @@ int stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t targe // check written byte count stlink_read_reg(sl, 2, &rr); - if (rr.r[2] != 0) { + if ((int32_t)rr.r[2] > 0) { ELOG("Write error\n"); goto error; } @@ -364,7 +379,7 @@ int stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t targe stlink_read_all_regs(sl, &rr); WLOG("Loader state: R2 0x%X R15 0x%X\n", rr.r[2], rr.r[15]); - if (dhcsr != 0x3000B || dfsr != 0x3 || cfsr || hfsr) { + if (dhcsr != 0x3000B || dfsr || cfsr || hfsr) { WLOG("MCU state: DHCSR 0x%X DFSR 0x%X CFSR 0x%X HFSR 0x%X\n", dhcsr, dfsr, cfsr, hfsr); } From bb96d613dd78f34b112dcbc91af0363315b7d0ff Mon Sep 17 00:00:00 2001 From: anton Date: Sat, 27 Mar 2021 19:37:20 +0500 Subject: [PATCH 216/503] Fix is_flash_busy on STM32F1 XL device --- src/common.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/common.c b/src/common.c index a17392cf1..640f37799 100644 --- a/src/common.c +++ b/src/common.c @@ -993,7 +993,7 @@ static inline unsigned int is_flash_busy(stlink_t *sl) { unsigned int res; if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || - (sl->flash_type == STLINK_FLASH_TYPE_F0) || + (sl->flash_type == STLINK_FLASH_TYPE_F1_XL) || (sl->flash_type == STLINK_FLASH_TYPE_L0)) { sr_busy_shift = FLASH_SR_BSY; } else if (sl->flash_type == STLINK_FLASH_TYPE_F4) { @@ -1010,7 +1010,7 @@ static inline unsigned int is_flash_busy(stlink_t *sl) { } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { sr_busy_shift = FLASH_H7_SR_QW; } else { - ELOG("unsupported flash method, abort\n"); + ELOG("unsupported flash method\n"); return(-1); } From be9c9dec7661f2b9e30fb26b85808bc132ee2c80 Mon Sep 17 00:00:00 2001 From: anton Date: Sun, 28 Mar 2021 21:36:12 +0500 Subject: [PATCH 217/503] flash_loader: fixed check of the flash loader results --- src/stlink-lib/flash_loader.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/src/stlink-lib/flash_loader.c b/src/stlink-lib/flash_loader.c index aea60f258..992f0a827 100644 --- a/src/stlink-lib/flash_loader.c +++ b/src/stlink-lib/flash_loader.c @@ -363,7 +363,13 @@ int stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t targe // check written byte count stlink_read_reg(sl, 2, &rr); - if ((int32_t)rr.r[2] > 0) { + /* The chunk size for loading is not rounded. The flash loader + * subtracts the size of the written block (1-8 bytes) from + * the remaining size each time. A negative value may mean that + * several bytes garbage has been written due to the unaligned + * firmware size. + */ + if ((int32_t)rr.r[2] > 0 || (int32_t)rr.r[2] < -7) { ELOG("Write error\n"); goto error; } From d0d52690d680d603264b90f6328e54aec4be793c Mon Sep 17 00:00:00 2001 From: anton Date: Mon, 29 Mar 2021 19:51:55 +0500 Subject: [PATCH 218/503] Added error checking in the FLASH_SR register after write and erase operations --- src/common.c | 214 +++++++++++++++++++++++++++++++++++++++++---------- 1 file changed, 175 insertions(+), 39 deletions(-) diff --git a/src/common.c b/src/common.c index 640f37799..7ebbb8d11 100644 --- a/src/common.c +++ b/src/common.c @@ -159,6 +159,9 @@ // G0/G4 FLASH status register #define STM32Gx_FLASH_SR_ERROR_MASK (0x3fa) +#define STM32Gx_FLASH_SR_PROGERR (3) +#define STM32Gx_FLASH_SR_WRPERR (4) +#define STM32Gx_FLASH_SR_PGAERR (5) #define STM32Gx_FLASH_SR_BSY (16) /* FLASH_SR Busy */ #define STM32Gx_FLASH_SR_EOP (0) /* FLASH_EOP End of Operation */ @@ -188,11 +191,15 @@ #define STM32WB_FLASH_SRRVR (STM32WB_FLASH_REGS_ADDR + 0x84) // WB Flash control register. -#define STM32WB_FLASH_CR_STRT (16) /* FLASH_CR Start */ -#define STM32WB_FLASH_CR_OPTLOCK (30) /* FLASH_CR Option Lock */ -#define STM32WB_FLASH_CR_LOCK (31) /* FLASH_CR Lock */ +#define STM32WB_FLASH_CR_STRT (16) /* Start */ +#define STM32WB_FLASH_CR_OPTLOCK (30) /* Option Lock */ +#define STM32WB_FLASH_CR_LOCK (31) /* Lock */ // WB Flash status register. -#define STM32WB_FLASH_SR_BSY (16) /* FLASH_SR Busy */ +#define STM32WB_FLASH_SR_ERROR_MASK (0x3f8) /* SR [9:3] */ +#define STM32WB_FLASH_SR_PROGERR (3) /* Programming alignment error */ +#define STM32WB_FLASH_SR_WRPERR (4) /* Write protection error */ +#define STM32WB_FLASH_SR_PGAERR (5) /* Programming error */ +#define STM32WB_FLASH_SR_BSY (16) /* Busy */ // 32L4 register base is at FLASH_REGS_ADDR (0x40022000) #define STM32L4_FLASH_KEYR (FLASH_REGS_ADDR + 0x08) @@ -201,8 +208,11 @@ #define STM32L4_FLASH_CR (FLASH_REGS_ADDR + 0x14) #define STM32L4_FLASH_OPTR (FLASH_REGS_ADDR + 0x20) +#define STM32L4_FLASH_SR_ERROR_MASK 0x3f8 /* SR [9:3] */ +#define STM32L4_FLASH_SR_PROGERR 3 +#define STM32L4_FLASH_SR_WRPERR 4 +#define STM32L4_FLASH_SR_PGAERR 5 #define STM32L4_FLASH_SR_BSY 16 -#define STM32L4_FLASH_SR_ERRMASK 0x3f8 /* SR [9:3] */ #define STM32L4_FLASH_CR_LOCK 31 /* Lock control register */ #define STM32L4_FLASH_CR_OPTLOCK 30 /* Lock option bytes */ @@ -234,7 +244,10 @@ #define STM32L0_FLASH_OPTLOCK (2) #define STM32L0_FLASH_OBL_LAUNCH (18) -#define STM32L0_FLASH_SR_ERROR_MASK 0x00003F00 +#define STM32L0_FLASH_SR_ERROR_MASK 0x00013F00 +#define STM32L0_FLASH_SR_WRPERR 8 +#define STM32L0_FLASH_SR_PGAERR 9 +#define STM32L0_FLASH_SR_NOTZEROERR 16 #define FLASH_ACR_OFF ((uint32_t) 0x00) #define FLASH_PECR_OFF ((uint32_t) 0x04) @@ -287,7 +300,10 @@ #define FLASH_F4_CR_SER 1 #define FLASH_F4_CR_SNB 3 #define FLASH_F4_CR_SNB_MASK 0xf8 -#define FLASH_F4_SR_BSY 16 +#define FLASH_F4_SR_ERROR_MASK 0x000000F0 +#define FLASH_F4_SR_PGAERR 5 +#define FLASH_F4_SR_WRPERR 4 +#define FLASH_F4_SR_BSY 16 // STM32F2 #define FLASH_F2_REGS_ADDR ((uint32_t)0x40023c00) @@ -980,7 +996,7 @@ static inline uint32_t read_flash_sr(stlink_t *sl, unsigned bank) { } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { sr_reg = (bank==BANK_1)?FLASH_H7_SR1:FLASH_H7_SR2; } else { - ELOG("unsupported flash method, abort\n"); + ELOG("method 'read_flash_sr' is unsupported\n"); return(-1); } @@ -988,6 +1004,35 @@ static inline uint32_t read_flash_sr(stlink_t *sl, unsigned bank) { return(res); } +static inline int write_flash_sr(stlink_t *sl, unsigned bank, uint32_t val) { + uint32_t sr_reg; + + if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || + (sl->flash_type == STLINK_FLASH_TYPE_F1_XL)) { + sr_reg = (bank==BANK_1)?FLASH_SR:FLASH_SR2; + } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { + sr_reg = get_stm32l0_flash_base(sl) + FLASH_SR_OFF; + } else if (sl->flash_type == STLINK_FLASH_TYPE_F4) { + sr_reg = FLASH_F4_SR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { + sr_reg = FLASH_F7_SR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { + sr_reg = STM32L4_FLASH_SR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || + sl->flash_type == STLINK_FLASH_TYPE_G4) { + sr_reg = STM32Gx_FLASH_SR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + sr_reg = STM32WB_FLASH_SR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + sr_reg = (bank==BANK_1)?FLASH_H7_SR1:FLASH_H7_SR2; + } else { + ELOG("method 'write_flash_sr' is unsupported\n"); + return(-1); + } + + return stlink_write_debug32(sl, sr_reg, val); +} + static inline unsigned int is_flash_busy(stlink_t *sl) { uint32_t sr_busy_shift; unsigned int res; @@ -1010,7 +1055,7 @@ static inline unsigned int is_flash_busy(stlink_t *sl) { } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { sr_busy_shift = FLASH_H7_SR_QW; } else { - ELOG("unsupported flash method\n"); + ELOG("method 'is_flash_busy' is unsupported\n"); return(-1); } @@ -1048,43 +1093,120 @@ static void wait_flash_busy_progress(stlink_t *sl) { fprintf(stdout, "\n"); } +static void clear_flash_error(stlink_t *sl) +{ + switch (sl->flash_type) { + case STLINK_FLASH_TYPE_F0: + write_flash_sr(sl, BANK_1, FLASH_SR_ERROR_MASK); + break; + case STLINK_FLASH_TYPE_F4: + write_flash_sr(sl, BANK_1, FLASH_F4_SR_ERROR_MASK); + break; + case STLINK_FLASH_TYPE_F7: + write_flash_sr(sl, BANK_1, FLASH_F7_SR_ERROR_MASK); + break; + case STLINK_FLASH_TYPE_G0: + case STLINK_FLASH_TYPE_G4: + write_flash_sr(sl, BANK_1, STM32Gx_FLASH_SR_ERROR_MASK); + break; + case STLINK_FLASH_TYPE_L0: + write_flash_sr(sl, BANK_1, STM32L0_FLASH_SR_ERROR_MASK); + break; + case STLINK_FLASH_TYPE_L4: + write_flash_sr(sl, BANK_1, STM32L4_FLASH_SR_ERROR_MASK); + break; + case STLINK_FLASH_TYPE_H7: + write_flash_sr(sl, BANK_1, FLASH_H7_SR_ERROR_MASK); + if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { + write_flash_sr(sl, BANK_2, FLASH_H7_SR_ERROR_MASK); + } + break; + case STLINK_FLASH_TYPE_WB: + write_flash_sr(sl, BANK_1, STM32WB_FLASH_SR_ERROR_MASK); + break; + default: + break; + } +} + static int check_flash_error(stlink_t *sl) { uint32_t res = 0; + uint32_t WRPERR, PROGERR, PGAERR; + + WRPERR = PROGERR = PGAERR = 0; switch (sl->flash_type) { case STLINK_FLASH_TYPE_F0: + case STLINK_FLASH_TYPE_F1_XL: res = read_flash_sr(sl, BANK_1) & FLASH_SR_ERROR_MASK; + if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL) { + res |= read_flash_sr(sl, BANK_2) & FLASH_SR_ERROR_MASK; + } + WRPERR = (1 << FLASH_SR_WRPRT_ERR); + PROGERR = (1 << FLASH_SR_PG_ERR); + break; + case STLINK_FLASH_TYPE_F4: + res = read_flash_sr(sl, BANK_1) & FLASH_F4_SR_ERROR_MASK; + WRPERR = (1 << FLASH_F4_SR_WRPERR); + PGAERR = (1 << FLASH_F4_SR_PGAERR); break; case STLINK_FLASH_TYPE_F7: res = read_flash_sr(sl, BANK_1) & FLASH_F7_SR_ERROR_MASK; + WRPERR = (1 << FLASH_F7_SR_WRP_ERR); + PROGERR = (1 << FLASH_F7_SR_PGP_ERR); break; case STLINK_FLASH_TYPE_G0: case STLINK_FLASH_TYPE_G4: res = read_flash_sr(sl, BANK_1) & STM32Gx_FLASH_SR_ERROR_MASK; + WRPERR = (1 << STM32Gx_FLASH_SR_WRPERR); + PROGERR = (1 << STM32Gx_FLASH_SR_PROGERR); + PGAERR = (1 << STM32Gx_FLASH_SR_PGAERR); break; case STLINK_FLASH_TYPE_L0: res = read_flash_sr(sl, BANK_1) & STM32L0_FLASH_SR_ERROR_MASK; + WRPERR = (1 << STM32L0_FLASH_SR_WRPERR); + PROGERR = (1 << STM32L0_FLASH_SR_NOTZEROERR); + PGAERR = (1 << STM32L0_FLASH_SR_PGAERR); + break; + case STLINK_FLASH_TYPE_L4: + res = read_flash_sr(sl, BANK_1) & STM32L4_FLASH_SR_ERROR_MASK; + WRPERR = (1 << STM32L4_FLASH_SR_WRPERR); + PROGERR = (1 << STM32L4_FLASH_SR_PROGERR); + PGAERR = (1 << STM32L4_FLASH_SR_PGAERR); break; case STLINK_FLASH_TYPE_H7: res = read_flash_sr(sl, BANK_1) & FLASH_H7_SR_ERROR_MASK; if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { res |= read_flash_sr(sl, BANK_2) & FLASH_H7_SR_ERROR_MASK; } - if (res) { - // Clear errors - stlink_write_debug32(sl, FLASH_H7_CCR1, res); - if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { - stlink_write_debug32(sl, FLASH_H7_CCR2, res); - } - } + WRPERR = (1 << FLASH_H7_SR_WRPERR); + break; + case STLINK_FLASH_TYPE_WB: + res = read_flash_sr(sl, BANK_1) & STM32WB_FLASH_SR_ERROR_MASK; + WRPERR = (1 << STM32WB_FLASH_SR_WRPERR); + PROGERR = (1 << STM32WB_FLASH_SR_PROGERR); + PGAERR = (1 << STM32WB_FLASH_SR_PGAERR); break; default: break; } if (res) { - ELOG("Flash programming error : %#010x\n", res); + if (WRPERR && (WRPERR&res)==WRPERR) { + ELOG("Flash memory is write protected\n"); + res &= ~WRPERR; + } else if (PROGERR && (PROGERR&res)==PROGERR) { + ELOG("Flash memory contains a non-erased value\n"); + res &= ~PROGERR; + } else if (PGAERR && (PGAERR&res)==PGAERR) { + ELOG("Invalid flash address\n"); + res &= ~PGAERR; + } + + if (res) { + ELOG("Flash programming error: %#010x\n", res); + } return(-1); } @@ -2372,12 +2494,14 @@ uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr) { * @return 0 on success -ve on failure */ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { + // wait for ongoing op to finish + wait_flash_busy(sl); + // clear flash IO errors + clear_flash_error(sl); + if (sl->flash_type == STLINK_FLASH_TYPE_F4 || sl->flash_type == STLINK_FLASH_TYPE_F7 || sl->flash_type == STLINK_FLASH_TYPE_L4) { - // wait for ongoing op to finish - wait_flash_busy(sl); - // unlock if locked unlock_flash_if(sl); @@ -2498,7 +2622,6 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { sl->flash_type == STLINK_FLASH_TYPE_G0 || sl->flash_type == STLINK_FLASH_TYPE_G4) { uint32_t val; - wait_flash_busy(sl); // wait for any ongoing Flash operation to finish unlock_flash_if(sl); set_flash_cr_per(sl, BANK_1); // set the 'enable Flash erase' bit @@ -2535,7 +2658,6 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { } else if (sl->flash_type == STLINK_FLASH_TYPE_F0 || sl->flash_type == STLINK_FLASH_TYPE_F1_XL) { unsigned bank = (flashaddr < STM32_F1_FLASH_BANK2_BASE)?BANK_1:BANK_2; - wait_flash_busy(sl); unlock_flash_if(sl); clear_flash_cr_pg(sl, bank); // clear the pg bit set_flash_cr_per(sl, bank); // set the page erase bit @@ -2545,7 +2667,6 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { lock_flash(sl); } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { unsigned bank = (flashaddr < STM32_H7_FLASH_BANK2_BASE)?BANK_1:BANK_2; - wait_flash_busy(sl); // wait for ongoing op to finish unlock_flash_if(sl); // unlock if locked uint32_t sector = calculate_H7_sectornum(sl, flashaddr, bank);// calculate the actual page from the address write_flash_cr_snb(sl, sector, bank); // select the page to erase @@ -2557,8 +2678,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { return(-1); } - // TODO: verify the erased page - return(0); + return check_flash_error(sl); } int stlink_erase_flash_mass(stlink_t *sl) { @@ -2574,7 +2694,7 @@ int stlink_erase_flash_mass(stlink_t *sl) { // addr must be an addr inside the page stm32_addr_t addr = (stm32_addr_t)sl->flash_base + i * (stm32_addr_t)sl->flash_pgsz; - if (stlink_erase_flash_page(sl, addr) == -1) { + if (stlink_erase_flash_page(sl, addr)) { WLOG("Failed to erase_flash_page(%#x) == -1\n", addr); return(-1); } @@ -2586,6 +2706,7 @@ int stlink_erase_flash_mass(stlink_t *sl) { fprintf(stdout, "\n"); } else { wait_flash_busy(sl); + clear_flash_error(sl); unlock_flash_if(sl); if (sl->flash_type == STLINK_FLASH_TYPE_H7 && sl->chip_id != STLINK_CHIPID_STM32_H7AX) { @@ -2596,7 +2717,7 @@ int stlink_erase_flash_mass(stlink_t *sl) { } } - set_flash_cr_mer(sl, 1, BANK_1); // set the mass erase bit + set_flash_cr_mer(sl, 1, BANK_1); // set the mass erase bit set_flash_cr_strt(sl, BANK_1); // start erase operation, reset by hw with busy bit if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL || @@ -2606,7 +2727,6 @@ int stlink_erase_flash_mass(stlink_t *sl) { } wait_flash_busy_progress(sl); - err = check_flash_error(sl); lock_flash(sl); // reset the mass erase bit @@ -2616,7 +2736,7 @@ int stlink_erase_flash_mass(stlink_t *sl) { set_flash_cr_mer(sl, 0, BANK_2); } - // TODO: verify the erased memory + err = check_flash_error(sl); } return(err); @@ -2751,6 +2871,11 @@ int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { STLINK_REG_DHCSR_C_HALT | STLINK_REG_DHCSR_C_MASKINTS); + // wait for ongoing op to finish + wait_flash_busy(sl); + // Clear errors + clear_flash_error(sl); + if ((sl->flash_type == STLINK_FLASH_TYPE_F4) || (sl->flash_type == STLINK_FLASH_TYPE_F7) || (sl->flash_type == STLINK_FLASH_TYPE_L4)) { @@ -2801,7 +2926,6 @@ int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { sl->flash_type == STLINK_FLASH_TYPE_G4) { ILOG("Starting Flash write for WB/G0/G4\n"); - wait_flash_busy(sl); unlock_flash_if(sl); // unlock flash if necessary set_flash_cr_pg(sl, BANK_1); // set PG 'allow programming' bit } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { @@ -2882,6 +3006,7 @@ int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t addr size_t size = len - off > buf_size ? buf_size : len - off; if (stlink_flash_loader_run(sl, fl, addr + (uint32_t)off, base + off, size) == -1) { ELOG("stlink_flash_loader_run(%#x) failed! == -1\n", (unsigned)(addr + off)); + check_flash_error(sl); return(-1); } @@ -2977,6 +3102,7 @@ int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t addr if (stlink_flash_loader_run(sl, fl, addr + (uint32_t)off, base + off, size) == -1) { ELOG("stlink_flash_loader_run(%#x) failed! == -1\n", (unsigned)(addr + off)); + check_flash_error(sl); return(-1); } @@ -3015,7 +3141,7 @@ int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t addr return(-1); } - return(0); + return check_flash_error(sl); } int stlink_flashloader_stop(stlink_t *sl) { @@ -3405,6 +3531,8 @@ static int stlink_write_option_bytes_gx( (void)len; uint32_t data; + clear_flash_error(sl); + write_uint32((unsigned char*)&data, *(uint32_t*)(base)); WLOG("Writing option bytes %#10x to %#10x\n", data, addr); stlink_write_debug32(sl, STM32Gx_FLASH_OPTR, data); @@ -3441,7 +3569,7 @@ static int stlink_write_option_bytes_l0( int ret = 0; // Clear errors - stlink_write_debug32(sl, flash_base + FLASH_SR_OFF, STM32L0_FLASH_REGS_ADDR); + clear_flash_error(sl); while (len != 0) { write_uint32((unsigned char*)&data, *(uint32_t*)(base)); // write options bytes @@ -3480,6 +3608,9 @@ static int stlink_write_option_bytes_l4( (void)addr; (void)len; + // Clear errors + clear_flash_error(sl); + // write options bytes uint32_t data; write_uint32((unsigned char*)&data, *(uint32_t*)(base)); @@ -3516,6 +3647,9 @@ static int stlink_write_option_bytes_f4( (void)addr; (void)len; + // Clear errors + clear_flash_error(sl); + write_uint32((unsigned char*)&option_byte, *(uint32_t*)(base)); // write option byte, ensuring we dont lock opt, and set strt bit @@ -3539,8 +3673,8 @@ static int stlink_write_option_bytes_f7(stlink_t *sl, uint8_t* base, stm32_addr_ uint32_t option_byte; int ret = 0; - //(void) addr; - //(void) len; + // Clear errors + clear_flash_error(sl); ILOG("Asked to write option byte %#10x to %#010x.\n", *(uint32_t*) (base), addr); write_uint32((unsigned char*) &option_byte, *(uint32_t*) (base)); @@ -3999,9 +4133,10 @@ int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t* base, ui static int stlink_write_option_control_register_f7(stlink_t *sl, uint32_t option_control_register) { int ret = 0; + // Clear errors + clear_flash_error(sl); + ILOG("Asked to write option control register 1 %#10x to %#010x.\n", option_control_register, FLASH_F7_OPTCR); - //write_uint32((unsigned char*) &option_byte, *(uint32_t*) (base)); - //ILOG("Write %d option bytes %#010x to %#010x!\n", len, option_byte, addr); /* write option byte, ensuring we dont lock opt, and set strt bit */ stlink_write_debug32(sl, FLASH_F7_OPTCR, (option_control_register & ~(1 << FLASH_F7_OPTCR_LOCK)) | (1 << FLASH_F7_OPTCR_START)); @@ -4010,7 +4145,7 @@ static int stlink_write_option_control_register_f7(stlink_t *sl, uint32_t option ret = check_flash_error(sl); if (!ret) - ILOG("Wrote option bytes %#010x to %#010x!\n", option_control_register, FLASH_F7_OPTCR1); + ILOG("Wrote option bytes %#010x to %#010x!\n", option_control_register, FLASH_F7_OPTCR); return ret; } @@ -4024,9 +4159,10 @@ static int stlink_write_option_control_register_f7(stlink_t *sl, uint32_t option static int stlink_write_option_control_register1_f7(stlink_t *sl, uint32_t option_control_register1) { int ret = 0; + // Clear errors + clear_flash_error(sl); + ILOG("Asked to write option control register 1 %#010x to %#010x.\n", option_control_register1, FLASH_F7_OPTCR1); - //write_uint32((unsigned char*) &option_byte, *(uint32_t*) (base)); - //ILOG("Write %d option bytes %#010x to %#010x!\n", len, option_byte, addr); /* write option byte, ensuring we dont lock opt, and set strt bit */ uint32_t current_control_register_value; From 817c8ad436eada97294fa93e6cc8e57fb1be9504 Mon Sep 17 00:00:00 2001 From: anton Date: Mon, 29 Mar 2021 20:31:57 +0500 Subject: [PATCH 219/503] flash_loader: fixed setup PG flag in F0/VL flash loaders, code cleared --- flashloaders/stm32f0.s | 6 ++-- src/common.c | 58 ++++++++++------------------------- src/stlink-lib/flash_loader.c | 18 +++++------ 3 files changed, 26 insertions(+), 56 deletions(-) diff --git a/flashloaders/stm32f0.s b/flashloaders/stm32f0.s index e2a4b0f00..23f1c43fe 100644 --- a/flashloaders/stm32f0.s +++ b/flashloaders/stm32f0.s @@ -35,10 +35,8 @@ copy: ldr r5, flash_off_sr add r5, r5, r7 - # FLASH_CR |= 0x01 (set PG) - ldr r7, =0x1 - ldr r4, [r6] - orrs r4, r4, r7 + # FLASH_CR = 0x01 (set PG) + ldr r4, =0x1 str r4, [r6] loop: diff --git a/src/common.c b/src/common.c index 7ebbb8d11..8585ff881 100644 --- a/src/common.c +++ b/src/common.c @@ -394,13 +394,21 @@ uint16_t read_uint16(const unsigned char *c, const int pt) { static uint32_t get_stm32l0_flash_base(stlink_t *sl) { switch (sl->chip_id) { + case STLINK_CHIPID_STM32_L0: + case STLINK_CHIPID_STM32_L0_CAT5: + case STLINK_CHIPID_STM32_L0_CAT2: + case STLINK_CHIPID_STM32_L011: + return(STM32L0_FLASH_REGS_ADDR); + case STLINK_CHIPID_STM32_L1_CAT2: case STLINK_CHIPID_STM32_L1_MEDIUM: case STLINK_CHIPID_STM32_L1_MEDIUM_PLUS: case STLINK_CHIPID_STM32_L1_HIGH: return(STM32L1_FLASH_REGS_ADDR); + default: - return(STM32L0_FLASH_REGS_ADDR); + WLOG("Flash base use default L0 address"); + return(STM32L0_FLASH_REGS_ADDR); } } @@ -2549,16 +2557,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { uint32_t val; - uint32_t flash_regs_base; - - if (sl->chip_id == STLINK_CHIPID_STM32_L0 || - sl->chip_id == STLINK_CHIPID_STM32_L0_CAT5 || - sl->chip_id == STLINK_CHIPID_STM32_L0_CAT2 || - sl->chip_id == STLINK_CHIPID_STM32_L011) { - flash_regs_base = STM32L0_FLASH_REGS_ADDR; - } else { - flash_regs_base = STM32L_FLASH_REGS_ADDR; - } + uint32_t flash_regs_base = get_stm32l0_flash_base(sl); // check if the locks are set stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); @@ -2592,15 +2591,6 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { // set pecr.{erase,prog} val |= (1 << 9) | (1 << 3); stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); -#if 0 - /* Wait for sr.busy to be cleared - * MP: Test shows that busy bit is not set here. Perhaps, PM0062 is wrong - * and we do not need to wait here for clearing the busy bit. - */ - do { - stlink_read_debug32(sl, STM32L_FLASH_SR, &val) - } while ((val & (1 << 0)) != 0); -#endif // write 0 to the first word of the page to be erased stlink_write_debug32(sl, flashaddr, 0); @@ -2610,9 +2600,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { * Test shows that a few iterations is performed in the following loop * before busy bit is cleared. */ - do - stlink_read_debug32(sl, flash_regs_base + FLASH_SR_OFF, &val); - while ((val & (1 << 0)) != 0); + wait_flash_busy(sl); // reset lock bits stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); @@ -2652,7 +2640,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { } set_flash_cr_strt(sl, BANK_1); // set the 'start operation' bit - wait_flash_busy(sl); // wait for the 'busy' bit to clear + wait_flash_busy(sl); // wait for the 'busy' bit to clear clear_flash_cr_per(sl, BANK_1); // clear the 'enable page erase' bit lock_flash(sl); } else if (sl->flash_type == STLINK_FLASH_TYPE_F0 || @@ -2664,6 +2652,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { write_flash_ar(sl, flashaddr, bank); // select the page to erase set_flash_cr_strt(sl, bank); // start erase operation, reset by hw with busy bit wait_flash_busy(sl); + clear_flash_cr_per(sl, bank); // clear the page erase bit lock_flash(sl); } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { unsigned bank = (flashaddr < STM32_H7_FLASH_BANK2_BASE)?BANK_1:BANK_2; @@ -2796,18 +2785,9 @@ int stm32l1_write_half_pages( unsigned int count; unsigned int num_half_pages = len / pagesize; uint32_t val; - uint32_t flash_regs_base; + uint32_t flash_regs_base = get_stm32l0_flash_base(sl); flash_loader_t fl; - if (sl->chip_id == STLINK_CHIPID_STM32_L0 || - sl->chip_id == STLINK_CHIPID_STM32_L0_CAT5 || - sl->chip_id == STLINK_CHIPID_STM32_L0_CAT2 || - sl->chip_id == STLINK_CHIPID_STM32_L011) { - flash_regs_base = STM32L0_FLASH_REGS_ADDR; - } else { - flash_regs_base = STM32L_FLASH_REGS_ADDR; - } - ILOG("Starting Half page flash write for STM32L core id\n"); /* Flash loader initialisation */ @@ -2824,9 +2804,7 @@ int stm32l1_write_half_pages( val |= (1 << FLASH_L1_PROG); stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); - do { - stlink_read_debug32(sl, flash_regs_base + FLASH_SR_OFF, &val); - } while ((val & (1 << 0)) != 0); + wait_flash_busy(sl); for (count = 0; count < num_half_pages; count++) { if (stlink_flash_loader_run( @@ -2845,9 +2823,7 @@ int stm32l1_write_half_pages( fflush(stdout); } - do { - stlink_read_debug32(sl, flash_regs_base + FLASH_SR_OFF, &val); - } while ((val & (1 << 0)) != 0); + wait_flash_busy(sl); } stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); @@ -3096,8 +3072,6 @@ int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t addr // unlock and set programming mode unlock_flash_if(sl); - if (sl->flash_type != STLINK_FLASH_TYPE_F1_XL) { set_flash_cr_pg(sl, BANK_1); } - DLOG("Finished unlocking flash, running loader!\n"); if (stlink_flash_loader_run(sl, fl, addr + (uint32_t)off, base + off, size) == -1) { diff --git a/src/stlink-lib/flash_loader.c b/src/stlink-lib/flash_loader.c index 992f0a827..e3b1a12ea 100644 --- a/src/stlink-lib/flash_loader.c +++ b/src/stlink-lib/flash_loader.c @@ -14,11 +14,10 @@ /* flashloaders/stm32f0.s -- compiled with thumb2 */ static const uint8_t loader_code_stm32vl[] = { 0x00, 0xbf, 0x00, 0xbf, - 0x0f, 0x4f, 0x1f, 0x44, - 0x0f, 0x4e, 0x3e, 0x44, - 0x0f, 0x4d, 0x3d, 0x44, - 0x4f, 0xf0, 0x01, 0x07, - 0x34, 0x68, 0x3c, 0x43, + 0x0e, 0x4f, 0x1f, 0x44, + 0x0e, 0x4e, 0x3e, 0x44, + 0x0e, 0x4d, 0x3d, 0x44, + 0x4f, 0xf0, 0x01, 0x04, 0x34, 0x60, 0x04, 0x88, 0x0c, 0x80, 0x02, 0x30, 0x02, 0x31, 0x4f, 0xf0, @@ -38,11 +37,10 @@ static const uint8_t loader_code_stm32vl[] = { /* flashloaders/stm32f0.s -- thumb1 only, same sequence as for STM32VL, bank ignored */ static const uint8_t loader_code_stm32f0[] = { 0xc0, 0x46, 0xc0, 0x46, - 0x0d, 0x4f, 0x1f, 0x44, - 0x0d, 0x4e, 0x3e, 0x44, - 0x0d, 0x4d, 0x3d, 0x44, - 0x0d, 0x4f, 0x34, 0x68, - 0x3c, 0x43, 0x34, 0x60, + 0x0c, 0x4f, 0x1f, 0x44, + 0x0c, 0x4e, 0x3e, 0x44, + 0x0c, 0x4d, 0x3d, 0x44, + 0x0c, 0x4c, 0x34, 0x60, 0x04, 0x88, 0x0c, 0x80, 0x02, 0x30, 0x02, 0x31, 0x09, 0x4f, 0x2c, 0x68, From b62cdcfab70e362b34b5875ad86b31c9e6fd6c73 Mon Sep 17 00:00:00 2001 From: anton Date: Mon, 29 Mar 2021 20:40:22 +0500 Subject: [PATCH 220/503] Added disabling the IWDG and WWDG in halt state --- src/common.c | 68 +++++++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 67 insertions(+), 1 deletion(-) diff --git a/src/common.c b/src/common.c index 8585ff881..26a3b3859 100644 --- a/src/common.c +++ b/src/common.c @@ -362,6 +362,25 @@ #define FLASH_H7_OPTSR_CUR (FLASH_H7_REGS_ADDR + 0x1c) #define FLASH_H7_OPTCCR (FLASH_H7_REGS_ADDR + 0x24) +#define STM32F0_DBGMCU_CR 0xE0042004 +#define STM32F0_DBGMCU_CR_IWDG_STOP 8 +#define STM32F0_DBGMCU_CR_WWDG_STOP 9 + +#define STM32F4_DBGMCU_APB1FZR1 0xE0042008 +#define STM32F4_DBGMCU_APB1FZR1_WWDG_STOP 11 +#define STM32F4_DBGMCU_APB1FZR1_IWDG_STOP 12 + +#define STM32L0_DBGMCU_APB1_FZ 0x40015808 +#define STM32L0_DBGMCU_APB1_FZ_WWDG_STOP 11 +#define STM32L0_DBGMCU_APB1_FZ_IWDG_STOP 12 + +#define STM32H7_DBGMCU_APB1HFZ 0x5C001054 +#define STM32H7_DBGMCU_APB1HFZ_IWDG_STOP 18 + +#define STM32WB_DBGMCU_APB1FZR1 0xE004203C +#define STM32WB_DBGMCU_APB1FZR1_WWDG_STOP 11 +#define STM32WB_DBGMCU_APB1FZR1_IWDG_STOP 12 + #define L1_WRITE_BLOCK_SIZE 0x80 #define L0_WRITE_BLOCK_SIZE 0x40 @@ -1221,6 +1240,50 @@ static int check_flash_error(stlink_t *sl) return(0); } +static void stop_wdg_in_debug(stlink_t *sl) { + uint32_t dbgmcu_cr; + uint32_t set; + uint32_t value; + + switch (sl->flash_type) { + case STLINK_FLASH_TYPE_F0: + case STLINK_FLASH_TYPE_F1_XL: + case STLINK_FLASH_TYPE_G4: + dbgmcu_cr = STM32F0_DBGMCU_CR; + set = (1< halted state. int stlink_force_debug(stlink_t *sl) { DLOG("*** stlink_force_debug_mode ***\n"); - return(sl->backend->force_debug(sl)); + int res = sl->backend->force_debug(sl); + // Stop the watchdogs in the halted state for suppress target reboot + stop_wdg_in_debug(sl); + return(res); } int stlink_exit_dfu_mode(stlink_t *sl) { From b0192478c8262476ead421890b1550d6a7b72ecc Mon Sep 17 00:00:00 2001 From: anton Date: Mon, 29 Mar 2021 20:56:03 +0500 Subject: [PATCH 221/503] Added disabling the DMA channels --- inc/stlink.h | 3 +- src/common.c | 83 +++++++++++++++++++++++++++++++++++++++- src/st-flash/flash.c | 13 ------- src/st-util/gdb-server.c | 2 +- src/stlink-gui/gui.c | 12 ------ 5 files changed, 84 insertions(+), 29 deletions(-) diff --git a/inc/stlink.h b/inc/stlink.h index 7bb1bc51e..61b8472f1 100644 --- a/inc/stlink.h +++ b/inc/stlink.h @@ -137,6 +137,7 @@ typedef uint32_t stm32_addr_t; typedef struct flash_loader { stm32_addr_t loader_addr; // loader sram addr stm32_addr_t buf_addr; // buffer sram address + uint32_t rcc_dma_bkp; // backup RCC DMA enable state } flash_loader_t; typedef struct _cortex_m3_cpuid_ { @@ -297,7 +298,7 @@ int stlink_fwrite_option_bytes(stlink_t *sl, const char* path, stm32_addr_t addr int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl); int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t addr, uint8_t* base, uint32_t len); -int stlink_flashloader_stop(stlink_t *sl); +int stlink_flashloader_stop(stlink_t *sl, flash_loader_t *fl); #include #include diff --git a/src/common.c b/src/common.c index 26a3b3859..60d7ff145 100644 --- a/src/common.c +++ b/src/common.c @@ -381,6 +381,27 @@ #define STM32WB_DBGMCU_APB1FZR1_WWDG_STOP 11 #define STM32WB_DBGMCU_APB1FZR1_IWDG_STOP 12 +#define STM32F1_RCC_AHBENR 0x40021014 +#define STM32F1_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN + +#define STM32F4_RCC_AHB1ENR 0x40023830 +#define STM32F4_RCC_DMAEN 0x00600000 // DMA2EN | DMA1EN + +#define STM32G0_RCC_AHBENR 0x40021038 +#define STM32G0_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN + +#define STM32G4_RCC_AHB1ENR 0x40021048 +#define STM32G4_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN + +#define STM32L0_RCC_AHBENR 0x40021030 +#define STM32L0_RCC_DMAEN 0x00000001 // DMAEN + +#define STM32H7_RCC_AHB1ENR 0x58024538 +#define STM32H7_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN + +#define STM32WB_RCC_AHB1ENR 0x58000048 +#define STM32WB_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN + #define L1_WRITE_BLOCK_SIZE 0x80 #define L0_WRITE_BLOCK_SIZE 0x40 @@ -1284,6 +1305,58 @@ static void stop_wdg_in_debug(stlink_t *sl) { } } +static void set_dma_state(stlink_t *sl, flash_loader_t* fl, int bckpRstr) { + uint32_t rcc, rcc_dma_mask, value; + + rcc = rcc_dma_mask = value = 0; + + switch (sl->flash_type) { + case STLINK_FLASH_TYPE_F0: + case STLINK_FLASH_TYPE_F1_XL: + rcc = STM32F1_RCC_AHBENR; + rcc_dma_mask = STM32F1_RCC_DMAEN; + break; + case STLINK_FLASH_TYPE_F4: + case STLINK_FLASH_TYPE_F7: + rcc = STM32F4_RCC_AHB1ENR; + rcc_dma_mask = STM32F4_RCC_DMAEN; + break; + case STLINK_FLASH_TYPE_G0: + rcc = STM32G0_RCC_AHBENR; + rcc_dma_mask = STM32G0_RCC_DMAEN; + break; + case STLINK_FLASH_TYPE_G4: + case STLINK_FLASH_TYPE_L4: + rcc = STM32G4_RCC_AHB1ENR; + rcc_dma_mask = STM32G4_RCC_DMAEN; + break; + case STLINK_FLASH_TYPE_L0: + rcc = STM32L0_RCC_AHBENR; + rcc_dma_mask = STM32L0_RCC_DMAEN; + break; + case STLINK_FLASH_TYPE_H7: + rcc = STM32H7_RCC_AHB1ENR; + rcc_dma_mask = STM32H7_RCC_DMAEN; + break; + case STLINK_FLASH_TYPE_WB: + rcc = STM32WB_RCC_AHB1ENR; + rcc_dma_mask = STM32WB_RCC_DMAEN; + break; + default: + return; + } + + if (!stlink_read_debug32(sl, rcc, &value)) { + if (bckpRstr) { + value = (value&(~rcc_dma_mask)) | fl->rcc_dma_bkp; + } else { + fl->rcc_dma_bkp = value&rcc_dma_mask; + value &= ~rcc_dma_mask; + } + stlink_write_debug32(sl, rcc, value); + } +} + static inline void write_flash_ar(stlink_t *sl, uint32_t n, unsigned bank) { stlink_write_debug32(sl, (bank==BANK_1)?FLASH_AR:FLASH_AR2, n); } @@ -2913,6 +2986,9 @@ int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { STLINK_REG_DHCSR_C_HALT | STLINK_REG_DHCSR_C_MASKINTS); + // disable DMA + set_dma_state(sl, fl, 0); + // wait for ongoing op to finish wait_flash_busy(sl); // Clear errors @@ -3184,7 +3260,7 @@ int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t addr return check_flash_error(sl); } -int stlink_flashloader_stop(stlink_t *sl) { +int stlink_flashloader_stop(stlink_t *sl, flash_loader_t *fl) { uint32_t dhcsr; if ((sl->flash_type == STLINK_FLASH_TYPE_F4) || @@ -3224,6 +3300,9 @@ int stlink_flashloader_stop(stlink_t *sl) { (dhcsr&(~STLINK_REG_DHCSR_C_MASKINTS))); } + // restore DMA state + set_dma_state(sl, fl, 1); + return(0); } @@ -3286,7 +3365,7 @@ int stlink_write_flash( ret = stlink_flashloader_write(sl, &fl, addr, base, len); if (ret) return ret; - ret = stlink_flashloader_stop(sl); + ret = stlink_flashloader_stop(sl, &fl); if (ret) return ret; diff --git a/src/st-flash/flash.c b/src/st-flash/flash.c index 5a226d57b..e870e116c 100644 --- a/src/st-flash/flash.c +++ b/src/st-flash/flash.c @@ -112,19 +112,6 @@ int main(int ac, char** av) { } } - // disable DMA - Set All DMA CCR Registers to zero. - AKS 1/7/2013 - if (sl->chip_id == STLINK_CHIPID_STM32_F4) { - memset(sl->q_buf, 0, 4); - - for (int i = 0; i < 8; i++) { - stlink_write_mem32(sl, 0x40026000 + 0x10 + 0x18 * i, 4); - stlink_write_mem32(sl, 0x40026400 + 0x10 + 0x18 * i, 4); - stlink_write_mem32(sl, 0x40026000 + 0x24 + 0x18 * i, 4); - stlink_write_mem32(sl, 0x40026400 + 0x24 + 0x18 * i, 4); - - } - } - // core must be halted to use RAM based flashloaders if (stlink_force_debug(sl)) { printf("Failed to halt the core\n"); diff --git a/src/st-util/gdb-server.c b/src/st-util/gdb-server.c index 3dc3073e5..8d63d9ee0 100644 --- a/src/st-util/gdb-server.c +++ b/src/st-util/gdb-server.c @@ -908,7 +908,7 @@ static int flash_go(stlink_t *sl) { } } - stlink_flashloader_stop(sl); + stlink_flashloader_stop(sl, &fl); stlink_soft_reset(sl, 1 /* halt on reset */); error = 0; diff --git a/src/stlink-gui/gui.c b/src/stlink-gui/gui.c index ed38fcc7c..d264cf9a5 100644 --- a/src/stlink-gui/gui.c +++ b/src/stlink-gui/gui.c @@ -514,18 +514,6 @@ static void connect_button_cb(GtkWidget *widget, gpointer data) { stlink_enter_swd_mode(gui->sl); } - // disable DMA - Set All DMA CCR Registers to zero. - AKS 1/7/2013 - if (gui->sl->chip_id == STLINK_CHIPID_STM32_F4) { - memset(gui->sl->q_buf, 0, 4); - - for (i = 0; i < 8; i++) { - stlink_write_mem32(gui->sl, 0x40026000 + 0x10 + 0x18 * i, 4); - stlink_write_mem32(gui->sl, 0x40026400 + 0x10 + 0x18 * i, 4); - stlink_write_mem32(gui->sl, 0x40026000 + 0x24 + 0x18 * i, 4); - stlink_write_mem32(gui->sl, 0x40026400 + 0x24 + 0x18 * i, 4); - } - } - stlink_gui_set_connected(gui); } From c793ca348fab43711cc3d24e8b9956ba90ca03d3 Mon Sep 17 00:00:00 2001 From: anton Date: Mon, 29 Mar 2021 22:19:48 +0500 Subject: [PATCH 222/503] Fixed GUI compilation --- src/stlink-gui/gui.c | 1 - 1 file changed, 1 deletion(-) diff --git a/src/stlink-gui/gui.c b/src/stlink-gui/gui.c index d264cf9a5..03e999b7f 100644 --- a/src/stlink-gui/gui.c +++ b/src/stlink-gui/gui.c @@ -489,7 +489,6 @@ static void stlink_gui_set_connected(STlinkGUI *gui) { static void connect_button_cb(GtkWidget *widget, gpointer data) { STlinkGUI *gui; - gint i; (void)widget; gui = STLINK_GUI(data); From 4334ce48b2c03497a6d415f8982fdb986409398c Mon Sep 17 00:00:00 2001 From: anton Date: Sun, 4 Apr 2021 11:45:21 +0500 Subject: [PATCH 223/503] flash_loader: added reset of IWDG If IWDG is enabled by hardware, then IWDG cannot be disabled by software --- inc/stlink.h | 1 + src/stlink-lib/flash_loader.c | 17 +++++++++++++++++ 2 files changed, 18 insertions(+) diff --git a/inc/stlink.h b/inc/stlink.h index 61b8472f1..855e5126d 100644 --- a/inc/stlink.h +++ b/inc/stlink.h @@ -138,6 +138,7 @@ typedef struct flash_loader { stm32_addr_t loader_addr; // loader sram addr stm32_addr_t buf_addr; // buffer sram address uint32_t rcc_dma_bkp; // backup RCC DMA enable state + uint32_t iwdg_kr; // IWDG key register address } flash_loader_t; typedef struct _cortex_m3_cpuid_ { diff --git a/src/stlink-lib/flash_loader.c b/src/stlink-lib/flash_loader.c index e3b1a12ea..80262cf07 100644 --- a/src/stlink-lib/flash_loader.c +++ b/src/stlink-lib/flash_loader.c @@ -9,6 +9,11 @@ #define FLASH_REGS_BANK2_OFS 0x40 #define FLASH_BANK2_START_ADDR 0x08080000 +#define STM32F0_WDG_KR 0x40003000 +#define STM32H7_WDG_KR 0x58004800 + +#define STM32F0_WDG_KR_KEY_RELOAD 0xAAAA + /* DO NOT MODIFY SOURCECODE DIRECTLY, EDIT ASSEMBLY FILES INSTEAD */ /* flashloaders/stm32f0.s -- compiled with thumb2 */ @@ -164,6 +169,13 @@ int stlink_flash_loader_init(stlink_t *sl, flash_loader_t *fl) { fl->buf_addr = fl->loader_addr + (uint32_t)size; ILOG("Successfully loaded flash loader in sram\n"); + // set address of IWDG key register for reset it + if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + fl->iwdg_kr = STM32H7_WDG_KR; + } else { + fl->iwdg_kr = STM32F0_WDG_KR; + } + /* Clear Fault Status Register for handling flash loader error */ if (!stlink_read_debug32(sl, STLINK_REG_DFSR, &dfsr) && dfsr) { ILOG("Clear DFSR\n"); @@ -329,6 +341,11 @@ int stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t targe // only used on VL/F1_XL, but harmless for others stlink_write_reg(sl, fl->loader_addr, 15); // pc register + /* Reset IWDG */ + if (fl->iwdg_kr) { + stlink_write_debug32(sl, fl->iwdg_kr, STM32F0_WDG_KR_KEY_RELOAD); + } + /* Run loader */ stlink_run(sl); From a3b1247d141592bd87fdb1f0aeec879e1b061eef Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 4 Apr 2021 23:40:10 +0200 Subject: [PATCH 224/503] General Project Update - Updated CHANGELOG.md - Added STLINK-V3E to supported programmers --- CHANGELOG.md | 22 ++++++++++++++-------- README.md | 2 +- 2 files changed, 15 insertions(+), 9 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index ee46901e7..57426342a 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -1,12 +1,14 @@ -# stlink ChangeLog +# stlink Changelog # v1.6.2 -Release date: (planned Q2/2021) +Release date: 2020-04-xx + +This release drops support for the STLINK/V1 programmer on macOS 10.13. Features: -- Extended support for STM32H7 & rework of software reset ([#532](https://github.com/stlink-org/stlink/pull/532), [#1059](https://github.com/stlink-org/stlink/pull/1059), [#1063](https://github.com/stlink-org/stlink/pull/1063), [#1071](https://github.com/stlink-org/stlink/pull/1071)) +- Extended support for STM32H7 & rework of software reset ([#532](https://github.com/stlink-org/stlink/pull/532), [#868](https://github.com/stlink-org/stlink/pull/868), [#1059](https://github.com/stlink-org/stlink/pull/1059), [#1063](https://github.com/stlink-org/stlink/pull/1063), [#1071](https://github.com/stlink-org/stlink/pull/1071)) - Added support for STM32H742/743/753 ([#671](https://github.com/stlink-org/stlink/pull/671), [#793](https://github.com/stlink-org/stlink/pull/793), [#823](https://github.com/stlink-org/stlink/pull/823), [#998](https://github.com/stlink-org/stlink/pull/998), [#1052](https://github.com/stlink-org/stlink/pull/1052)) - Official support for STLINK-V3 programmers (commit [#5e0a502](https://github.com/stlink-org/stlink/commit/5e0a502df812495bfa96fa9116a19f1306152b17), [#820](https://github.com/stlink-org/stlink/pull/820), [#1022](https://github.com/stlink-org/stlink/pull/1022), [#1025](https://github.com/stlink-org/stlink/pull/1025)) - Added preliminary support for STM32L5x2 ([#904](https://github.com/stlink-org/stlink/pull/904), [#999](https://github.com/stlink-org/stlink/pull/999)) @@ -18,6 +20,7 @@ Features: - Link for WIN32 & APPLE with stlink-static ([#1069](https://github.com/stlink-org/stlink/pull/1069)) - ITM functionality for STLink/V2 and STM32Fxx chipsets ([#136](https://github.com/stlink-org/stlink/pull/136), [#179](https://github.com/stlink-org/stlink/pull/179), [#815](https://github.com/stlink-org/stlink/pull/815), [#1072](https://github.com/stlink-org/stlink/pull/1072)) - Included ITM functionality for building with MSVC ([#1080](https://github.com/stlink-org/stlink/pull/1080)) +- Update for CI integration (commit [#0eebc9a](https://github.com/stlink-org/stlink/commit/0eebc9a74506e84d5c460ec325ae98064a81885e), [#1118](https://github.com/stlink-org/stlink/pull/1118)) Updates & changes: @@ -32,10 +35,11 @@ Updates & changes: - [doc] Added example for output of `st-info --probe` ([#1007](https://github.com/stlink-org/stlink/pull/1007), [#1049](https://github.com/stlink-org/stlink/pull/1049)) - [refactoring] Correctly handle endianness without reference to host platform ([#1081](https://github.com/stlink-org/stlink/pull/1081)) - Check format string for log messages ([#1093](https://github.com/stlink-org/stlink/pull/1093)) +- Removed abort() from stlink-lib ([#1116](https://github.com/stlink-org/stlink/pull/1116)) Fixes: -- Flash loader rework ([#356](https://github.com/stlink-org/stlink/pull/356), [#556](https://github.com/stlink-org/stlink/pull/556), [#593](https://github.com/stlink-org/stlink/pull/593), [#597](https://github.com/stlink-org/stlink/pull/597), [#607](https://github.com/stlink-org/stlink/pull/607), [#612](https://github.com/stlink-org/stlink/pull/612), [#638](https://github.com/stlink-org/stlink/pull/638), [#661](https://github.com/stlink-org/stlink/pull/661), [#690](https://github.com/stlink-org/stlink/pull/690), [#818](https://github.com/stlink-org/stlink/pull/818), [#854](https://github.com/stlink-org/stlink/pull/854), [#967](https://github.com/stlink-org/stlink/pull/967), [#979](https://github.com/stlink-org/stlink/pull/979), [#1043](https://github.com/stlink-org/stlink/pull/1043), [#1054](https://github.com/stlink-org/stlink/pull/1054), [#1092](https://github.com/stlink-org/stlink/pull/1092), [#1105](https://github.com/stlink-org/stlink/pull/1105), [#1113](https://github.com/stlink-org/stlink/pull/1113)) +- Flash loader rework ([#356](https://github.com/stlink-org/stlink/pull/356), [#556](https://github.com/stlink-org/stlink/pull/556), [#593](https://github.com/stlink-org/stlink/pull/593), [#597](https://github.com/stlink-org/stlink/pull/597), [#607](https://github.com/stlink-org/stlink/pull/607), [#612](https://github.com/stlink-org/stlink/pull/612), [#638](https://github.com/stlink-org/stlink/pull/638), [#661](https://github.com/stlink-org/stlink/pull/661), [#690](https://github.com/stlink-org/stlink/pull/690), [#818](https://github.com/stlink-org/stlink/pull/818), [#854](https://github.com/stlink-org/stlink/pull/854), [#868](https://github.com/stlink-org/stlink/pull/868), [#967](https://github.com/stlink-org/stlink/pull/967), [#979](https://github.com/stlink-org/stlink/pull/979), [#1043](https://github.com/stlink-org/stlink/pull/1043), [#1054](https://github.com/stlink-org/stlink/pull/1054), [#1092](https://github.com/stlink-org/stlink/pull/1092), [#1105](https://github.com/stlink-org/stlink/pull/1105), [#1113](https://github.com/stlink-org/stlink/pull/1113)) - Fixed old DFU serial number for STLINK programmers ([#417](https://github.com/stlink-org/stlink/pull/417), [#494](https://github.com/stlink-org/stlink/pull/494), [#1106](https://github.com/stlink-org/stlink/pull/1106)) - Use vl flashloader for all STM32F1 series ([#769](https://github.com/stlink-org/stlink/pull/769), [#1041](https://github.com/stlink-org/stlink/pull/1041), [#1044](https://github.com/stlink-org/stlink/pull/1044)) - [regression] Changed timeout on flash write ([#787](https://github.com/stlink-org/stlink/pull/787), [#981](https://github.com/stlink-org/stlink/pull/981), [#987](https://github.com/stlink-org/stlink/pull/987)) @@ -60,6 +64,8 @@ Fixes: - Fixed support for writing option bytes ([#1102](https://github.com/stlink-org/stlink/pull/1102)) - [doc] Corrected spelling mistake in bug report template ([#1103](https://github.com/stlink-org/stlink/pull/1103)) - Fixed STM32WB55 reading DEBUG IDCODE from the wrong address ([#1100](https://github.com/stlink-org/stlink/pull/1100), [#1101](https://github.com/stlink-org/stlink/pull/1101)) +- Applied missing changes to tests ([#1119](https://github.com/stlink-org/stlink/pull/1119)) +- Improvements for Chip_ID read ([#1120](https://github.com/stlink-org/stlink/pull/1120)) # v1.6.1 @@ -216,7 +222,7 @@ Release date: 2018-09-13 Major changes and added features: -- Added reset through `AIRCR` ([#540](https://github.com/stlink-org/stlink/pull/540), [#712](https://github.com/stlink-org/stlink/pull/712)) +- Added reset through `AIRCR` ([#254](https://github.com/stlink-org/stlink/pull/254), [#540](https://github.com/stlink-org/stlink/pull/540), [#712](https://github.com/stlink-org/stlink/pull/712)) - Added creation of icons for `.desktop` file ([#684](https://github.com/stlink-org/stlink/pull/684), [#708](https://github.com/stlink-org/stlink/pull/708)) - Added desktop file for linux ([#688](https://github.com/stlink-org/stlink/pull/688)) - Added button to export STM32 flash memory to a file ([#691](https://github.com/stlink-org/stlink/pull/691)) @@ -279,7 +285,6 @@ Major changes and added features: Updates and fixes: -- Fixed gdb-server: STM32L0xx has no `FP_CTRL` register for breakpoints ([#273](https://github.com/stlink-org/stlink/pull/273)) - Added `--flash=n[k][m]` command line option to override device model ([#305](https://github.com/stlink-org/stlink/pull/305), [#516](https://github.com/stlink-org/stlink/pull/516), [#576](https://github.com/stlink-org/stlink/pull/576)) - Updated `libusb` to 1.0.21 for Windows ([#562](https://github.com/stlink-org/stlink/pull/562)) - Fixed low-voltage flashing on STM32F7 devices ([#566](https://github.com/stlink-org/stlink/pull/566), [#567](https://github.com/stlink-org/stlink/pull/567)) @@ -324,11 +329,11 @@ Major changes and added features: - Added manpages (generated with `pandoc` from Markdown) ([#208](https://github.com/stlink-org/stlink/pull/208), [#464](https://github.com/stlink-org/stlink/pull/464), [#466](https://github.com/stlink-org/stlink/pull/466), [#467](https://github.com/stlink-org/stlink/pull/467)) - Removal of undocumented `st-term` utility, which is now replaced by `st-util` ARM semihosting feature ([#228](https://github.com/stlink-org/stlink/pull/228), [#507](https://github.com/stlink-org/stlink/pull/507), commit [#3fd0f09](https://github.com/stlink-org/stlink/commit/3fd0f099782506532198473b24f643a3f68d5ff9)) - Support serial numbers argument for `st-util` and `st-flash` to probe and control multiple connected programmers ([#318](https://github.com/stlink-org/stlink/pull/318), [#398](https://github.com/stlink-org/stlink/pull/398), [#541](https://github.com/stlink-org/stlink/pull/541)) +- Added 'k' (kill) command to gdb-server, which resets the connection ([#358](https://github.com/stlink-org/stlink/pull/358), [#525](https://github.com/stlink-org/stlink/pull/525), [#527](https://github.com/stlink-org/stlink/pull/527), [#528](https://github.com/stlink-org/stlink/pull/528)) - Merge `st-probe` tool into `st-info` ([#398](https://github.com/stlink-org/stlink/pull/398)) - Added support for native debian packaging ([#444](https://github.com/stlink-org/stlink/pull/444), [#472](https://github.com/stlink-org/stlink/pull/472), [#473](https://github.com/stlink-org/stlink/pull/473), [#482](https://github.com/stlink-org/stlink/pull/482), [#483](https://github.com/stlink-org/stlink/pull/483), [#484](https://github.com/stlink-org/stlink/pull/484), [#485](https://github.com/stlink-org/stlink/pull/485)) - Rewritten commandline parsing for `st-flash` ([#459](https://github.com/stlink-org/stlink/pull/459)) - Added `--reset` command to `st-flash` ([#505](https://github.com/stlink-org/stlink/pull/505)) -- st-util should detect when USB commands fail ([#525](https://github.com/stlink-org/stlink/pull/525), [#527](https://github.com/stlink-org/stlink/pull/527), [#528](https://github.com/stlink-org/stlink/pull/528)) Chip support added for: @@ -344,12 +349,12 @@ Chip support added for: Updates and fixes: +- Do a JTAG reset prior to reading CPU information when processor is in deep sleep ([#291](https://github.com/stlink-org/stlink/pull/291), [#428](https://github.com/stlink-org/stlink/pull/428), [#430](https://github.com/stlink-org/stlink/pull/430), [#451](https://github.com/stlink-org/stlink/pull/451)) - Fixed `unaligned addr or size` when trying to write a program in RAM ([#323](https://github.com/stlink-org/stlink/pull/323)) - Fixed flashing on `STM32_F3_SMALL` ([#325](https://github.com/stlink-org/stlink/pull/325)) - Fixed STM32L-problem with flash loader ([#390](https://github.com/stlink-org/stlink/pull/390), [#407](https://github.com/stlink-org/stlink/pull/407), [#408](https://github.com/stlink-org/stlink/pull/408)) - Don't read the target voltage on startup, because it crashes STM32F100 ([#423](https://github.com/stlink-org/stlink/pull/423), [#424](https://github.com/stlink-org/stlink/pull/424)) - Added a useful error message instead of `[!] send_recv` ([#425](https://github.com/stlink-org/stlink/pull/425), [#426](https://github.com/stlink-org/stlink/pull/426)) -- Do a JTAG reset prior to reading CPU information when processor is in deep sleep ([#428](https://github.com/stlink-org/stlink/pull/428), [#430](https://github.com/stlink-org/stlink/pull/430), [#451](https://github.com/stlink-org/stlink/pull/451)) - Fixed STM32F030 erase error ([#442](https://github.com/stlink-org/stlink/pull/442)) - Fixed memory map for STM32F7xx ([#453](https://github.com/stlink-org/stlink/pull/453), [#456](https://github.com/stlink-org/stlink/pull/456)) - Redesign of `st-flash` commandline options parsing ([#459](https://github.com/stlink-org/stlink/pull/459)) @@ -392,6 +397,7 @@ Updates and fixes: - Modified determination of erased byte pattern when flashing ([#193](https://github.com/stlink-org/stlink/pull/193), [#377](https://github.com/stlink-org/stlink/pull/377)) - Use libusb synchronous api ([#194](https://github.com/stlink-org/stlink/pull/194), [#225](https://github.com/stlink-org/stlink/pull/225), [#374](https://github.com/stlink-org/stlink/pull/374)) - Fixed segfault when programmer is already busy and `NULL` pointers are in the list ([#256](https://github.com/stlink-org/stlink/pull/256), [#394](https://github.com/stlink-org/stlink/pull/394)) +- Fixed gdb-server: Cortex M0 chips have no `FP_CTRL` register for breakpoints ([#266](https://github.com/stlink-org/stlink/pull/266), [#273](https://github.com/stlink-org/stlink/pull/273), [#341](https://github.com/stlink-org/stlink/pull/341)) - Fixed issue where "unknown chip id!" was seen every other time ([#352](https://github.com/stlink-org/stlink/pull/352), [#367](https://github.com/stlink-org/stlink/pull/367), [#381](https://github.com/stlink-org/stlink/pull/381)) - Send F4 memory-map and features for STM32F429 ([#188](https://github.com/stlink-org/stlink/pull/188), [#196](https://github.com/stlink-org/stlink/pull/196), [#250](https://github.com/stlink-org/stlink/pull/250), [#251](https://github.com/stlink-org/stlink/pull/251)) (Release v1.1.0) - Added AHB3 Peripherals definition for STM32F4 ([#218](https://github.com/stlink-org/stlink/pull/218), [#288](https://github.com/stlink-org/stlink/pull/288)) (Release v1.1.0) diff --git a/README.md b/README.md index 644c3fd86..93994db49 100644 --- a/README.md +++ b/README.md @@ -36,7 +36,7 @@ It supports several so called STLINK programmer boards (and clones thereof) whic - **STLINK-V3** - transport layer: raw USB commands - stand-alone programmer (STLINK-V3SET, STLINK-V3MINI, STLINK-V3MODS) - - on-board on some STM32 Nucleo boards + - on-board on some STM32 Nucleo boards (STLINK-V3E) _\*)_ **Note: Support for the STLINK/V1 on macOS is limited to 10.14 - 10.15. Due to the deprecation and removal of macOS Kernel Extensions (KEXT) there will be no support for this programmer on macOS 11 or any later version.** From 9a8e0aa6457640e27a0dbee5d994c3f8249fddf6 Mon Sep 17 00:00:00 2001 From: anton Date: Mon, 5 Apr 2021 21:15:18 +0500 Subject: [PATCH 225/503] Added the hot plug option to st-flash --- doc/tutorial.md | 2 +- src/st-flash/flash.c | 4 ++-- src/st-flash/flash_opts.c | 2 ++ 3 files changed, 5 insertions(+), 3 deletions(-) diff --git a/doc/tutorial.md b/doc/tutorial.md index 37c29ab6a..256513bc4 100644 --- a/doc/tutorial.md +++ b/doc/tutorial.md @@ -9,7 +9,7 @@ | --opt | st-flash | Optimisation can be enabled in order to skip flashing empty (0x00 or 0xff) bytes at the end of binary file.
This may cause some garbage data left after a flash operation. This option was enabled by default in earlier releases. | v1.6.1 | | --reset | st-flash | Trigger a reset both before and after flashing. The default uses the hardware reset through `NRST` pin.
A software reset (via `AIRCR`; since v1.5.1) is used, if the hardware reset failed (`NRST` pin not connected). | v1.0.0 | | --connect-under-reset | st-info
st-flash | Connect under reset. Option makes it possible to connect to the device before code execution. This is useful
when the target contains code that lets the device go to sleep, disables debug pins or other special code. | v1.6.1 | -| --hot-plug | st-info
st-util | Connect to the target without reset. | v1.6.2 | +| --hot-plug | st-info
st-flash
st-util | Connect to the target without reset. | v1.6.2 | | --probe | st-info | Display hardware information about the connected programmer and target MCU. | v1.2.0 | | --version | st-info
st-flash
st-util | Print version information. | v1.3.0 | | --help | st-flash
st-util | Print list of available commands. | | diff --git a/src/st-flash/flash.c b/src/st-flash/flash.c index e870e116c..356515ac4 100644 --- a/src/st-flash/flash.c +++ b/src/st-flash/flash.c @@ -26,8 +26,8 @@ static void cleanup(int signum) { } static void usage(void) { - puts("command line: ./st-flash [--debug] [--reset] [--connect-under-reset] [--opt] [--serial ] [--format ] [--flash=] [--freq=] [--area=] {read|write} [path] [addr] [size]"); - puts("command line: ./st-flash [--debug] [--connect-under-reset] [--freq=] [--serial ] erase"); + puts("command line: ./st-flash [--debug] [--reset] [--connect-under-reset] [--hot-plug] [--opt] [--serial ] [--format ] [--flash=] [--freq=] [--area=] {read|write} [path] [addr] [size]"); + puts("command line: ./st-flash [--debug] [--connect-under-reset] [--hot-plug] [--freq=] [--serial ] erase"); puts("command line: ./st-flash [--debug] [--freq=] [--serial ] reset"); puts(" , and : Use hex format."); puts(" : Use decimal, octal or hex (prefix 0xXXX) format, optionally followed by k=KB, or m=MB (eg. --flash=128k)"); diff --git a/src/st-flash/flash_opts.c b/src/st-flash/flash_opts.c index 63774ea25..172a24468 100644 --- a/src/st-flash/flash_opts.c +++ b/src/st-flash/flash_opts.c @@ -193,6 +193,8 @@ int flash_get_opts(struct flash_opts* o, int ac, char** av) { } } else if (strcmp(av[0], "--connect-under-reset") == 0) { o->connect = CONNECT_UNDER_RESET; + } else if (strcmp(av[0], "--hot-plug") == 0) { + o->connect = CONNECT_HOT_PLUG; } else { break; // non-option found From 696ea923ce7517a604d43adfe017c1cdda3b7339 Mon Sep 17 00:00:00 2001 From: anton Date: Mon, 5 Apr 2021 21:23:16 +0500 Subject: [PATCH 226/503] Changed the behavior of the st-flash reset option. The reset option conflicted with the connection type options (connect under reset, hot plug). Now reset of target is performed only after the completion of the firmware if the reset options is used. --- src/st-flash/flash.c | 14 -------------- 1 file changed, 14 deletions(-) diff --git a/src/st-flash/flash.c b/src/st-flash/flash.c index 356515ac4..edb54e195 100644 --- a/src/st-flash/flash.c +++ b/src/st-flash/flash.c @@ -98,20 +98,6 @@ int main(int ac, char** av) { } } - if (o.reset) { - if (sl->version.stlink_v > 1) { - if (stlink_jtag_reset(sl, 2)) { - printf("Failed to reset JTAG\n"); - goto on_error; - } - } - - if (stlink_reset(sl)) { - printf("Failed to reset device\n"); - goto on_error; - } - } - // core must be halted to use RAM based flashloaders if (stlink_force_debug(sl)) { printf("Failed to halt the core\n"); From d3bc853209a6785a1f87a2359839e80c15735563 Mon Sep 17 00:00:00 2001 From: anton Date: Mon, 5 Apr 2021 21:53:57 +0500 Subject: [PATCH 227/503] Update tutorial --- doc/tutorial.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/doc/tutorial.md b/doc/tutorial.md index 256513bc4..21f1498ee 100644 --- a/doc/tutorial.md +++ b/doc/tutorial.md @@ -7,7 +7,7 @@ | --flash=n[k][m] | st-flash | One can specify `--flash=128k` for example, to override the default value of 64k for the STM32F103C8T6
to assume 128k of flash being present. This option accepts decimal (128k), octal 0200k, or hex 0x80k values.
Leaving the multiplier out is equally valid, e.g.: `--flash=0x20000`. The size may be followed by an optional
"k" or "m" to multiply the given value by 1k (1024) or 1M respectively. | v1.4.0 | | --freq=n[k][m] | st-info
st-flash
st-util | The frequency of the SWD/JTAG interface can be specified, to override the default 1800 kHz configuration.
This option solely accepts decimal values (5K or 1.8M) with the unit `Hz` being left out. Valid frequencies are:
`5K, 15K, 25K, 50K, 100K, 125K, 240K, 480K, 950K, 1200K, 1800K, 4000K(4M)`. | v1.6.1 | | --opt | st-flash | Optimisation can be enabled in order to skip flashing empty (0x00 or 0xff) bytes at the end of binary file.
This may cause some garbage data left after a flash operation. This option was enabled by default in earlier releases. | v1.6.1 | -| --reset | st-flash | Trigger a reset both before and after flashing. The default uses the hardware reset through `NRST` pin.
A software reset (via `AIRCR`; since v1.5.1) is used, if the hardware reset failed (`NRST` pin not connected). | v1.0.0 | +| --reset | st-flash | Trigger a reset after flashing. The default uses the hardware reset through `NRST` pin.
A software reset (via `AIRCR`; since v1.5.1) is used, if the hardware reset failed (`NRST` pin not connected). | v1.0.0 | | --connect-under-reset | st-info
st-flash | Connect under reset. Option makes it possible to connect to the device before code execution. This is useful
when the target contains code that lets the device go to sleep, disables debug pins or other special code. | v1.6.1 | | --hot-plug | st-info
st-flash
st-util | Connect to the target without reset. | v1.6.2 | | --probe | st-info | Display hardware information about the connected programmer and target MCU. | v1.2.0 | From 4fc6344d44681a0add3bdce69ecf2d0e4e70db49 Mon Sep 17 00:00:00 2001 From: anton Date: Mon, 5 Apr 2021 22:13:17 +0500 Subject: [PATCH 228/503] flash_loader: fixed alignment of size of the lx loader --- src/stlink-lib/flash_loader.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/stlink-lib/flash_loader.c b/src/stlink-lib/flash_loader.c index 80262cf07..cd7096490 100644 --- a/src/stlink-lib/flash_loader.c +++ b/src/stlink-lib/flash_loader.c @@ -68,7 +68,7 @@ static const uint8_t loader_code_stm32lx[] = { 0x00, 0xf1, 0x04, 0x00, 0x01, 0xf1, 0x04, 0x01, 0x04, 0x3a, 0xf7, 0xdc, - 0x00, 0xbe + 0x00, 0xbe, 0x00, 0x00 }; static const uint8_t loader_code_stm32f4[] = { From 5ce54824a5ca819a7ff630b880268febb07ff3e3 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Mon, 5 Apr 2021 21:55:54 +0200 Subject: [PATCH 229/503] Updated CI & MinGW64 cross build configuration - Moved config for macOS 10.14 to GitHub Actions (Note: preparation only, yet inactive) - Removed macOS 10.14 builds from Travis CI - Removed Linux build config from Travis CI - Split 32- & 64-bit cross builds to separate jobs - Minor fixes for MinGW64 cross build config --- .github/workflows/c-cpp.yml | 90 ++++++++++++++++++++ .travis.sh | 22 ++--- .travis.yml | 79 ++--------------- cmake/modules/Findlibusb.cmake | 18 ++-- cmake/modules/c_flags.cmake | 2 +- cmake/packaging/windows/generate_binaries.sh | 18 ++-- 6 files changed, 123 insertions(+), 106 deletions(-) diff --git a/.github/workflows/c-cpp.yml b/.github/workflows/c-cpp.yml index 4769450ae..97f48d88d 100644 --- a/.github/workflows/c-cpp.yml +++ b/.github/workflows/c-cpp.yml @@ -282,6 +282,96 @@ jobs: # macOS + # job_macos_10_14_64_gcc: + # name: macos-10.14 gcc + # runs-on: macos-10.14 + # steps: + # - uses: actions/checkout@v2 + # - name: Install dependencies + # run: brew install gcc libusb gtk+3 + # - name: make debug + # run: sudo make clean && make debug + # - name: make test + # run: sudo make clean && make test + # - name: make release + # run: sudo make clean && make release + # - name: sudo make install + # run: sudo make clean && sudo make install + # - name: sudo make package + # run: sudo make package + # - name: sudo make uninstall + # run: sudo make uninstall && sudo make clean + + # job_macos_10_14_32_gcc: + # name: macos-10.14 gcc 32-bit + # runs-on: macos-10.14 + # steps: + # - uses: actions/checkout@v2 + # - name: Install dependencies + # run: brew install gcc libusb gtk+3 + # - name: Set compiler flags + # run: | + # CFLAGS="$CFLAGS -m32" + # CXXFLAGS="$CXXFLAGS -m32" + # LDFLAGS="$LDFLAGS -m32" + # - name: make debug + # run: sudo make clean && make debug + # - name: make test + # run: sudo make clean && make test + # - name: make release + # run: sudo make clean && make release + # - name: sudo make install + # run: sudo make clean && sudo make install + # - name: sudo make package + # run: sudo make package + # - name: sudo make uninstall + # run: sudo make uninstall && sudo make clean + + # job_macos_10_14_64_clang: + # name: macos-10.14 clang + # runs-on: macos-10.14 + # steps: + # - uses: actions/checkout@v2 + # - name: Install dependencies + # run: brew install llvm libusb gtk+3 + # - name: make debug + # run: sudo make clean && make debug + # - name: make test + # run: sudo make clean && make test + # - name: make release + # run: sudo make clean && make release + # - name: sudo make install + # run: sudo make clean && sudo make install + # - name: sudo make package + # run: sudo make package + # - name: sudo make uninstall + # run: sudo make uninstall && sudo make clean + + # job_macos_10_14_32_clang: + # name: macos-10.14 clang 32-bit + # runs-on: macos-10.14 + # steps: + # - uses: actions/checkout@v2 + # - name: Install dependencies + # run: brew install llvm libusb gtk+3 + # - name: Set compiler flags + # run: | + # CFLAGS="$CFLAGS -m32" + # CXXFLAGS="$CXXFLAGS -m32" + # LDFLAGS="$LDFLAGS -m32" + # - name: make debug + # run: sudo make clean && make debug + # - name: make test + # run: sudo make clean && make test + # - name: make release + # run: sudo make clean && make release + # - name: sudo make install + # run: sudo make clean && sudo make install + # - name: sudo make package + # run: sudo make package + # - name: sudo make uninstall + # run: sudo make uninstall && sudo make clean + job_macos_10_15_gcc: name: macos-10.15 gcc runs-on: macos-10.15 diff --git a/.travis.sh b/.travis.sh index de2a42372..e45cd3609 100755 --- a/.travis.sh +++ b/.travis.sh @@ -8,18 +8,19 @@ echo "----" echo "WORK DIR:$DIR" DIR=$PWD -if [ "$TRAVIS_JOB_NAME" == "linux-mingw" ]; then +if [ "$TRAVIS_JOB_NAME" == "linux-mingw-64" ]; then echo "--> Building for Windows (x86-64) ..." - mkdir -p build-mingw && cd build-mingw + mkdir -p build-mingw && cd build-mingw-64 cmake -DCMAKE_SYSTEM_NAME=Windows -DTOOLCHAIN_PREFIX=x86_64-w64-mingw32 \ -DCMAKE_TOOLCHAIN_FILE=$PWD/../cmake/modules/set_toolchain.cmake -DCMAKE_INSTALL_PREFIX=$PWD/install $DIR - make && rm -rf build-mingw && cd - + make && rm -rf build-mingw-64 && cd - +elif [ "$TRAVIS_JOB_NAME" == "linux-mingw-32" ]; then echo "--> Building for Windows (i686) ..." - mkdir -p build-mingw && cd build-mingw + mkdir -p build-mingw && cd build-mingw-32 cmake -DCMAKE_SYSTEM_NAME=Windows -DTOOLCHAIN_PREFIX=i686-w64-mingw32 \ -DCMAKE_TOOLCHAIN_FILE=$PWD/../cmake/modules/set_toolchain.cmake -DCMAKE_INSTALL_PREFIX=$PWD/install $DIR - make && rm -rf build-mingw && cd - + make && rm -rf build-mingw-32 && cd - elif [ "$TRAVIS_OS_NAME" == "linux" ]; then sudo apt-get update -qq || true @@ -34,17 +35,6 @@ elif [ "$TRAVIS_OS_NAME" == "linux" ]; then cmake -DCMAKE_BUILD_TYPE=Release -DCMAKE_INSTALL_PREFIX=$PWD/install $DIR make package && cd - -elif [ "$TRAVIS_OS_NAME" == "osx" ]; then - echo "--> Building Debug..." - mkdir -p build/Debug && cd build/Debug - cmake -DCMAKE_BUILD_TYPE=Debug -DCMAKE_INSTALL_PREFIX=$PWD/install $DIR - make && cd - - - echo "--> Building Release with package..." - mkdir -p build/Release && cd build/Release - cmake -DCMAKE_BUILD_TYPE=Release -DCMAKE_INSTALL_PREFIX=$PWD/install $DIR - make package && cd - - else # local test-build echo "--> Building Debug..." mkdir -p build/Debug && cd build/Debug diff --git a/.travis.yml b/.travis.yml index 2a788fd69..a733019a1 100644 --- a/.travis.yml +++ b/.travis.yml @@ -2,32 +2,22 @@ language: c jobs: include: - ### 64-bit build on AMD64 ### - - os: linux - dist: focal - env: BADGE=linux - compiler: gcc-10 - addons: - apt: - sources: ["ubuntu-toolchain-r-test"] - packages: ["gcc-10", "libusb-1.0.0-dev", "libgtk-3-dev", "rpm"] + ### cross builds on AMD64 ### - ### 32-bit build on AMD64 ### - os: linux dist: focal - env: BADGE=linux + env: BADGE=linux-mingw-64 + name: linux-mingw compiler: gcc-10 addons: apt: sources: ["ubuntu-toolchain-r-test"] - packages: ["gcc-10", "libusb-1.0.0-dev", "libgtk-3-dev", "rpm"] - before_install: - - CFLAGS="$CFLAGS -m32"; CXXFLAGS="$CXXFLAGS -m32"; LDFLAGS="$LDFLAGS -m32"; + packages: + ["gcc-10", "libusb-1.0.0-dev", "libgtk-3-dev", "rpm", "mingw-w64"] - ### cross build on AMD64 ### - os: linux dist: focal - env: BADGE=linux-mingw + env: BADGE=linux-mingw-32 name: linux-mingw compiler: gcc-10 addons: @@ -35,64 +25,9 @@ jobs: sources: ["ubuntu-toolchain-r-test"] packages: ["gcc-10", "libusb-1.0.0-dev", "libgtk-3-dev", "rpm", "mingw-w64"] - before_install: - - LDFLAGS="$LDFLAGS -NDEBUG"; - - ### macOS ### - # - os: osx - # env: BADGE=osx - # osx_image: xcode11.3 - # name: macOS 10.14.6 gcc - # compiler: gcc - # addons: - # homebrew: - # packages: - # - gcc - # - libusb - # - gtk+3 - - # - os: osx - # env: BADGE=osx - # osx_image: xcode11.3 - # name: macOS 10.14.6 gcc 32-bit - # compiler: gcc - # addons: - # homebrew: - # packages: - # - gcc - # - libusb - # - gtk+3 - # before_install: - # - CFLAGS="$CFLAGS -m32"; CXXFLAGS="$CXXFLAGS -m32"; LDFLAGS="$LDFLAGS -m32"; - - # - os: osx - # env: BADGE=osx - # osx_image: xcode11.3 - # name: macOS 10.14.6 clang - # compiler: clang - # addons: - # homebrew: - # packages: - # - llvm - # - libusb - # - gtk+3 - - # - os: osx - # env: BADGE=osx - # osx_image: xcode11.3 - # name: macOS 10.14.6 clang 32-bit - # compiler: clang - # addons: - # homebrew: - # packages: - # - llvm - # - libusb - # - gtk+3 - # before_install: - # - CFLAGS="$CFLAGS -m32"; CXXFLAGS="$CXXFLAGS -m32"; LDFLAGS="$LDFLAGS -m32"; script: - git fetch --tags - printenv - cmake --version - - if [[ "$TRAVIS_OS_NAME" == "linux" ]] || [[ "$TRAVIS_OS_NAME" == "osx" ]]; then ./.travis.sh; fi + - if [[ "$TRAVIS_OS_NAME" == "linux" ]]; then ./.travis.sh; fi diff --git a/cmake/modules/Findlibusb.cmake b/cmake/modules/Findlibusb.cmake index 3082a9509..257c682ce 100644 --- a/cmake/modules/Findlibusb.cmake +++ b/cmake/modules/Findlibusb.cmake @@ -10,7 +10,7 @@ include(FindPackageHandleStandardArgs) -if (APPLE) # macOS +if (APPLE) # macOS FIND_PATH( LIBUSB_INCLUDE_DIR NAMES libusb.h HINTS /usr /usr/local /opt @@ -27,7 +27,7 @@ if (APPLE) message(FATAL_ERROR "No libusb library found on your system! Install libusb-1.0 from Homebrew or MacPorts") endif () -elseif (CMAKE_SYSTEM_NAME STREQUAL "FreeBSD") # FreeBSD; libusb is integrated into the system +elseif (CMAKE_SYSTEM_NAME STREQUAL "FreeBSD") # FreeBSD; libusb is integrated into the system FIND_PATH( LIBUSB_INCLUDE_DIR NAMES libusb.h HINTS /usr/include @@ -43,13 +43,13 @@ elseif (CMAKE_SYSTEM_NAME STREQUAL "FreeBSD") message(FATAL_ERROR "Expected libusb library not found on your system! Verify your system integrity.") endif () -elseif (WIN32 OR (EXISTS "/etc/debian_version" AND MINGW)) # Windows or MinGW-toolchain on Debian - # for MinGW/MSYS/MSVC: 64-bit or 32-bit? +elseif (WIN32 OR (EXISTS "/etc/debian_version" AND MINGW)) # Windows or MinGW-toolchain on Debian + # MinGW/MSYS/MSVC: 64-bit or 32-bit? if (CMAKE_SIZEOF_VOID_P EQUAL 8) message(STATUS "=== Building for Windows (x86-64) ===") set(ARCH 64) else () - message(STATUS "=== Building for Windowsm (i686) ===") + message(STATUS "=== Building for Windows (i686) ===") set(ARCH 32) endif () @@ -77,14 +77,14 @@ elseif (WIN32 OR (EXISTS "/etc/debian_version" AND MINGW)) if (NOT LIBUSB_FOUND) # Preparations for installing libusb library - set(LIBUSB_WIN_VERSION 1.0.23) # set libusb version + set(LIBUSB_WIN_VERSION 1.0.23) # set libusb version set(LIBUSB_WIN_ARCHIVE libusb-${LIBUSB_WIN_VERSION}.7z) if (WIN32 AND NOT EXISTS "/etc/debian_version") # ... on native Windows systems set(LIBUSB_WIN_ARCHIVE_PATH ${CMAKE_BINARY_DIR}/${LIBUSB_WIN_ARCHIVE}) set(LIBUSB_WIN_OUTPUT_FOLDER ${CMAKE_BINARY_DIR}/3rdparty/libusb-${LIBUSB_WIN_VERSION}) - else (EXISTS "/etc/debian_version" AND MINGW) # ... only for cross-building on Debian - set(LIBUSB_WIN_ARCHIVE_PATH ${CMAKE_SOURCE_DIR}/build-mingw/${LIBUSB_WIN_ARCHIVE}) - set(LIBUSB_WIN_OUTPUT_FOLDER ${CMAKE_SOURCE_DIR}/build-mingw/3rdparty/libusb-${LIBUSB_WIN_VERSION}) + else (EXISTS "/etc/debian_version" AND MINGW) # ... only for cross-building on Debian + set(LIBUSB_WIN_ARCHIVE_PATH ${CMAKE_SOURCE_DIR}/build-mingw-${ARCH}/${LIBUSB_WIN_ARCHIVE}) + set(LIBUSB_WIN_OUTPUT_FOLDER ${CMAKE_SOURCE_DIR}/build-mingw-${ARCH}/3rdparty/libusb-${LIBUSB_WIN_VERSION}) endif () # Get libusb package diff --git a/cmake/modules/c_flags.cmake b/cmake/modules/c_flags.cmake index 8291ea0ee..5ed0c4d7d 100644 --- a/cmake/modules/c_flags.cmake +++ b/cmake/modules/c_flags.cmake @@ -41,7 +41,7 @@ if (NOT CMAKE_SYSTEM_NAME STREQUAL "OpenBSD") add_cflag_if_supported("-Wredundant-decls") endif () -if (NOT WIN32) +if (NOT (WIN32 OR (EXISTS "/etc/debian_version" AND MINGW))) add_cflag_if_supported("-fPIC") endif () diff --git a/cmake/packaging/windows/generate_binaries.sh b/cmake/packaging/windows/generate_binaries.sh index d38f8d62f..bf2453d10 100644 --- a/cmake/packaging/windows/generate_binaries.sh +++ b/cmake/packaging/windows/generate_binaries.sh @@ -6,23 +6,25 @@ #sudo apt-get install mingw-w64 # x86_64 -mkdir build-mingw -cd build-mingw +mkdir build-mingw-64 +cd build-mingw-64 cmake -DCMAKE_SYSTEM_NAME=Windows \ -DTOOLCHAIN_PREFIX=x86_64-w64-mingw32 \ - -DCMAKE_TOOLCHAIN_FILE=./cmake/modules/set_toolchain.cmake .. + -DCMAKE_TOOLCHAIN_FILE=./../cmake/modules/set_toolchain.cmake .. make package cp dist/*.zip ../build/Release/dist +make clean cd .. -rm -rf build-mingw +rm -rf build-mingw-64 # i686 -mkdir build-mingw -cd build-mingw +mkdir build-mingw-32 +cd build-mingw-32 cmake -DCMAKE_SYSTEM_NAME=Windows \ -DTOOLCHAIN_PREFIX=i686-w64-mingw32 \ - -DCMAKE_TOOLCHAIN_FILE=./cmake/modules/set_toolchain.cmake .. + -DCMAKE_TOOLCHAIN_FILE=./../cmake/modules/set_toolchain.cmake .. make package cp dist/*.zip ../build/Release/dist +make clean cd .. -rm -rf build-mingw +rm -rf build-mingw-32 From 89a495d169a15f42d8cfd1a68c6738c984d052f8 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Tue, 6 Apr 2021 00:46:44 +0200 Subject: [PATCH 230/503] Updated libusb to v1.0.24 Note: Due to a compilation bug in libusb v1.0.24, building of x86-64 windows binaries is currently not possible and has been deactivated. --- .gitignore | 1 + .travis.sh | 18 +++++++-------- .travis.yml | 24 ++++++++++---------- cmake/modules/Findlibusb.cmake | 6 ++--- cmake/packaging/windows/generate_binaries.sh | 24 ++++++++++---------- 5 files changed, 37 insertions(+), 36 deletions(-) diff --git a/.gitignore b/.gitignore index a07eed9ca..82c1195e4 100644 --- a/.gitignore +++ b/.gitignore @@ -1,5 +1,6 @@ build build-mingw +build-mingw-* .project .cmake/ diff --git a/.travis.sh b/.travis.sh index e45cd3609..58cea5746 100755 --- a/.travis.sh +++ b/.travis.sh @@ -8,20 +8,20 @@ echo "----" echo "WORK DIR:$DIR" DIR=$PWD -if [ "$TRAVIS_JOB_NAME" == "linux-mingw-64" ]; then - echo "--> Building for Windows (x86-64) ..." - mkdir -p build-mingw && cd build-mingw-64 - cmake -DCMAKE_SYSTEM_NAME=Windows -DTOOLCHAIN_PREFIX=x86_64-w64-mingw32 \ - -DCMAKE_TOOLCHAIN_FILE=$PWD/../cmake/modules/set_toolchain.cmake -DCMAKE_INSTALL_PREFIX=$PWD/install $DIR - make && rm -rf build-mingw-64 && cd - - -elif [ "$TRAVIS_JOB_NAME" == "linux-mingw-32" ]; then +if [ "$TRAVIS_JOB_NAME" == "linux-mingw-32" ]; then echo "--> Building for Windows (i686) ..." - mkdir -p build-mingw && cd build-mingw-32 + mkdir -p build-mingw-32 && cd build-mingw-32 cmake -DCMAKE_SYSTEM_NAME=Windows -DTOOLCHAIN_PREFIX=i686-w64-mingw32 \ -DCMAKE_TOOLCHAIN_FILE=$PWD/../cmake/modules/set_toolchain.cmake -DCMAKE_INSTALL_PREFIX=$PWD/install $DIR make && rm -rf build-mingw-32 && cd - +# elif [ "$TRAVIS_JOB_NAME" == "linux-mingw-64" ]; then +# echo "--> Building for Windows (x86-64) ..." +# mkdir -p build-mingw-64 && cd build-mingw-64 +# cmake -DCMAKE_SYSTEM_NAME=Windows -DTOOLCHAIN_PREFIX=x86_64-w64-mingw32 \ +# -DCMAKE_TOOLCHAIN_FILE=$PWD/../cmake/modules/set_toolchain.cmake -DCMAKE_INSTALL_PREFIX=$PWD/install $DIR +# make && rm -rf build-mingw-64 && cd - + elif [ "$TRAVIS_OS_NAME" == "linux" ]; then sudo apt-get update -qq || true diff --git a/.travis.yml b/.travis.yml index a733019a1..307c0bfa0 100644 --- a/.travis.yml +++ b/.travis.yml @@ -4,21 +4,10 @@ jobs: include: ### cross builds on AMD64 ### - - os: linux - dist: focal - env: BADGE=linux-mingw-64 - name: linux-mingw - compiler: gcc-10 - addons: - apt: - sources: ["ubuntu-toolchain-r-test"] - packages: - ["gcc-10", "libusb-1.0.0-dev", "libgtk-3-dev", "rpm", "mingw-w64"] - - os: linux dist: focal env: BADGE=linux-mingw-32 - name: linux-mingw + name: linux-mingw-32 compiler: gcc-10 addons: apt: @@ -26,6 +15,17 @@ jobs: packages: ["gcc-10", "libusb-1.0.0-dev", "libgtk-3-dev", "rpm", "mingw-w64"] + # - os: linux + # dist: focal + # env: BADGE=linux-mingw-64 + # name: linux-mingw-64 + # compiler: gcc-10 + # addons: + # apt: + # sources: ["ubuntu-toolchain-r-test"] + # packages: + # ["gcc-10", "libusb-1.0.0-dev", "libgtk-3-dev", "rpm", "mingw-w64"] + script: - git fetch --tags - printenv diff --git a/cmake/modules/Findlibusb.cmake b/cmake/modules/Findlibusb.cmake index 257c682ce..99f4d56ec 100644 --- a/cmake/modules/Findlibusb.cmake +++ b/cmake/modules/Findlibusb.cmake @@ -77,7 +77,7 @@ elseif (WIN32 OR (EXISTS "/etc/debian_version" AND MINGW)) # Windows or MinGW-to if (NOT LIBUSB_FOUND) # Preparations for installing libusb library - set(LIBUSB_WIN_VERSION 1.0.23) # set libusb version + set(LIBUSB_WIN_VERSION 1.0.24) # set libusb version set(LIBUSB_WIN_ARCHIVE libusb-${LIBUSB_WIN_VERSION}.7z) if (WIN32 AND NOT EXISTS "/etc/debian_version") # ... on native Windows systems set(LIBUSB_WIN_ARCHIVE_PATH ${CMAKE_BINARY_DIR}/${LIBUSB_WIN_ARCHIVE}) @@ -94,7 +94,7 @@ elseif (WIN32 OR (EXISTS "/etc/debian_version" AND MINGW)) # Windows or MinGW-to message(STATUS "downloading libusb ${LIBUSB_WIN_VERSION}") file(DOWNLOAD https://sourceforge.net/projects/libusb/files/libusb-1.0/libusb-${LIBUSB_WIN_VERSION}/libusb-${LIBUSB_WIN_VERSION}.7z/download - ${LIBUSB_WIN_ARCHIVE_PATH} EXPECTED_MD5 cf3d38d2ff053ef343d10c0b8b0950c2 + ${LIBUSB_WIN_ARCHIVE_PATH} EXPECTED_MD5 5c944b1c8aa9d43e026a94302d0f8ac4 ) endif () @@ -128,7 +128,7 @@ elseif (WIN32 OR (EXISTS "/etc/debian_version" AND MINGW)) # Windows or MinGW-to set(LIBUSB_NAME libusb-1.0.lib) find_library( LIBUSB_LIBRARY NAMES ${LIBUSB_NAME} - HINTS ${LIBUSB_WIN_OUTPUT_FOLDER}/MS${ARCH}/dll + HINTS ${LIBUSB_WIN_OUTPUT_FOLDER}/**/MS${ARCH}/dll NO_DEFAULT_PATH NO_CMAKE_FIND_ROOT_PATH ) diff --git a/cmake/packaging/windows/generate_binaries.sh b/cmake/packaging/windows/generate_binaries.sh index bf2453d10..5616ecb38 100644 --- a/cmake/packaging/windows/generate_binaries.sh +++ b/cmake/packaging/windows/generate_binaries.sh @@ -5,18 +5,6 @@ # Install this cross-compiler toolchain: #sudo apt-get install mingw-w64 -# x86_64 -mkdir build-mingw-64 -cd build-mingw-64 -cmake -DCMAKE_SYSTEM_NAME=Windows \ - -DTOOLCHAIN_PREFIX=x86_64-w64-mingw32 \ - -DCMAKE_TOOLCHAIN_FILE=./../cmake/modules/set_toolchain.cmake .. -make package -cp dist/*.zip ../build/Release/dist -make clean -cd .. -rm -rf build-mingw-64 - # i686 mkdir build-mingw-32 cd build-mingw-32 @@ -28,3 +16,15 @@ cp dist/*.zip ../build/Release/dist make clean cd .. rm -rf build-mingw-32 + +# x86_64 +# mkdir build-mingw-64 +# cd build-mingw-64 +# cmake -DCMAKE_SYSTEM_NAME=Windows \ +# -DTOOLCHAIN_PREFIX=x86_64-w64-mingw32 \ +# -DCMAKE_TOOLCHAIN_FILE=./../cmake/modules/set_toolchain.cmake .. +# make package +# cp dist/*.zip ../build/Release/dist +# make clean +# cd .. +# rm -rf build-mingw-64 From ee43e3b3571c8c7d253b158bbab2d330b3ef19cb Mon Sep 17 00:00:00 2001 From: anton Date: Tue, 6 Apr 2021 21:13:54 +0500 Subject: [PATCH 231/503] Unification of the reset function --- inc/stlink.h | 24 +++++++++-- src/common.c | 91 +++++++++++++++++++++++++++++++++++++-- src/st-flash/flash.c | 13 +----- src/st-trace/trace.c | 2 +- src/st-util/gdb-server.c | 92 +++++++++++++--------------------------- src/stlink-lib/sg.c | 2 +- src/stlink-lib/usb.c | 51 +--------------------- src/stlink-lib/usb.h | 6 --- tests/sg.c | 2 +- tests/usb.c | 2 +- 10 files changed, 145 insertions(+), 140 deletions(-) diff --git a/inc/stlink.h b/inc/stlink.h index 855e5126d..8fe6033d6 100644 --- a/inc/stlink.h +++ b/inc/stlink.h @@ -58,6 +58,11 @@ enum target_state { #define STLINK_JTAG_READDEBUG_32BIT 0x36 #define STLINK_JTAG_DRIVE_NRST 0x3C +/* NRST pin states */ +#define STLINK_JTAG_DRIVE_NRST_LOW 0x00 +#define STLINK_JTAG_DRIVE_NRST_HIGH 0x01 +#define STLINK_JTAG_DRIVE_NRST_PULSE 0x02 + #define STLINK_DEBUG_APIV2_SWD_SET_FREQ 0x43 #define STLINK_APIV3_SET_COM_FREQ 0x61 @@ -173,6 +178,19 @@ enum transport_type { TRANSPORT_TYPE_INVALID }; +enum connect_type { + CONNECT_HOT_PLUG = 0, + CONNECT_NORMAL = 1, + CONNECT_UNDER_RESET = 2, +}; + +enum reset_type { + RESET_AUTO = 0, + RESET_HARD = 1, + RESET_SOFT = 2, + RESET_SOFT_AND_HALT = 3, +}; + typedef struct _stlink stlink_t; #include @@ -231,9 +249,7 @@ int stlink_exit_debug_mode(stlink_t *sl); int stlink_exit_dfu_mode(stlink_t *sl); void stlink_close(stlink_t *sl); int stlink_core_id(stlink_t *sl); -int stlink_reset(stlink_t *sl); -int stlink_jtag_reset(stlink_t *sl, int value); -int stlink_soft_reset(stlink_t *sl, int halt_on_reset); +int stlink_reset(stlink_t *sl, enum reset_type type); int stlink_run(stlink_t *sl); int stlink_status(stlink_t *sl); int stlink_version(stlink_t *sl); @@ -301,6 +317,8 @@ int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl); int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t addr, uint8_t* base, uint32_t len); int stlink_flashloader_stop(stlink_t *sl, flash_loader_t *fl); +int stlink_target_connect(stlink_t *sl, enum connect_type connect); + #include #include #include diff --git a/src/common.c b/src/common.c index 60d7ff145..928091eb4 100644 --- a/src/common.c +++ b/src/common.c @@ -1663,10 +1663,6 @@ int stlink_load_device_params(stlink_t *sl) { return(0); } -int stlink_reset(stlink_t *sl) { - DLOG("*** stlink_reset ***\n"); - return(sl->backend->reset(sl)); -} int stlink_jtag_reset(stlink_t *sl, int value) { DLOG("*** stlink_jtag_reset ***\n"); @@ -1742,6 +1738,59 @@ int stlink_soft_reset(stlink_t *sl, int halt_on_reset) { return(0); } +int stlink_reset(stlink_t *sl, enum reset_type type) { + uint32_t dhcsr; + unsigned timeout; + + DLOG("*** stlink_reset ***\n"); + + if (type == RESET_AUTO) { + // clear S_RESET_ST in DHCSR register for reset state detection + stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); + } + + if (type == RESET_HARD || type == RESET_AUTO) { + // hardware target reset + if (sl->version.stlink_v > 1) { stlink_jtag_reset(sl, STLINK_JTAG_DRIVE_NRST_PULSE); } + if (sl->backend->reset(sl)) { return(-1); } + usleep(10000); + } + + if (type == RESET_AUTO) { + /* Check if the S_RESET_ST bit is set in DHCSR + * This means that a reset has occurred + * DDI0337E, p. 10-4, Debug Halting Control and Status Register */ + + dhcsr = 0; + stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); + if ((dhcsr & STLINK_REG_DHCSR_S_RESET_ST) == 0) { + // reset not done yet + // try reset through AIRCR so that NRST does not need to be connected + + WLOG("NRST is not connected\n"); + DLOG("Using reset through SYSRESETREQ\n"); + return stlink_soft_reset(sl, 0); + } + + // waiting for reset the S_RESET_ST bit within 500ms + timeout = time_ms() + 500; + while (time_ms() < timeout) { + dhcsr = STLINK_REG_DHCSR_S_RESET_ST; + stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); + if ((dhcsr&STLINK_REG_DHCSR_S_RESET_ST) == 0) + return(0); + } + + return(-1); + } + + if (type == RESET_SOFT || type == RESET_SOFT_AND_HALT) { + return stlink_soft_reset(sl, (type==RESET_SOFT_AND_HALT)); + } + + return(0); +} + int stlink_run(stlink_t *sl) { struct stlink_reg rr; DLOG("*** stlink_run ***\n"); @@ -4467,3 +4516,37 @@ int stlink_fwrite_option_bytes(stlink_t *sl, const char* path, stm32_addr_t addr return(err); } +int stlink_target_connect(stlink_t *sl, enum connect_type connect) { + uint32_t dhcsr; + + if (connect == CONNECT_UNDER_RESET) { + stlink_jtag_reset(sl, STLINK_JTAG_DRIVE_NRST_LOW); + + if (stlink_current_mode(sl) != STLINK_DEV_DEBUG_MODE) { stlink_enter_swd_mode(sl); } + stlink_force_debug(sl); + + // clear S_RESET_ST in DHCSR register + stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); + + stlink_jtag_reset(sl, STLINK_JTAG_DRIVE_NRST_HIGH); + usleep(10000); + + // check NRST connection + dhcsr = 0; + stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); + if ((dhcsr & STLINK_REG_DHCSR_S_RESET_ST) == 0) { + WLOG("NRST is not connected\n"); + } + + // addition soft reset for halt before the first instruction + stlink_soft_reset(sl, 1 /* halt on reset */); + } + + if (stlink_current_mode(sl) != STLINK_DEV_DEBUG_MODE) { stlink_enter_swd_mode(sl); } + + if (connect == CONNECT_NORMAL) { + stlink_reset(sl, RESET_AUTO); + } + + return stlink_load_device_params(sl); +} diff --git a/src/st-flash/flash.c b/src/st-flash/flash.c index edb54e195..5eb607758 100644 --- a/src/st-flash/flash.c +++ b/src/st-flash/flash.c @@ -188,14 +188,7 @@ int main(int ac, char** av) { goto on_error; } } else if (o.cmd == CMD_RESET) { - if (sl->version.stlink_v > 1) { - if (stlink_jtag_reset(sl, 2)) { - printf("Failed to reset JTAG\n"); - goto on_error; - } - } - - if (stlink_reset(sl)) { + if (stlink_reset(sl, RESET_AUTO)) { printf("Failed to reset device\n"); goto on_error; } @@ -263,9 +256,7 @@ int main(int ac, char** av) { } if (o.reset) { - if (sl->version.stlink_v > 1) { stlink_jtag_reset(sl, 2); } - - stlink_reset(sl); + stlink_reset(sl, RESET_AUTO); } err = 0; // success diff --git a/src/st-trace/trace.c b/src/st-trace/trace.c index 3180335a0..f40a9d683 100644 --- a/src/st-trace/trace.c +++ b/src/st-trace/trace.c @@ -203,7 +203,7 @@ static bool enable_trace(stlink_t* stlink, const st_settings_t* settings, uint32 return false; } - if (settings->reset_board && stlink_jtag_reset(stlink, 2)) { + if (settings->reset_board && stlink_reset(stlink, RESET_AUTO)) { ELOG("Unable to reset device\n"); if (!settings->force) return false; diff --git a/src/st-util/gdb-server.c b/src/st-util/gdb-server.c index 8d63d9ee0..c2a220df3 100644 --- a/src/st-util/gdb-server.c +++ b/src/st-util/gdb-server.c @@ -42,9 +42,6 @@ #define FLASH_PAGE (sl->flash_pgsz) static stlink_t *connected_stlink = NULL; -static bool semihosting = false; -static bool serial_specified = false; -static char serialnumber[STLINK_SERIAL_BUFFER_SIZE] = {0}; #if defined(_WIN32) #define close_socket win32_close_socket @@ -57,8 +54,6 @@ static char serialnumber[STLINK_SERIAL_BUFFER_SIZE] = {0}; static const char hex[] = "0123456789abcdef"; -static const char* current_memory_map = NULL; - typedef struct _st_state_t { // things from command line, bleh int logging_level; @@ -66,6 +61,9 @@ typedef struct _st_state_t { int persistent; enum connect_type connect_mode; int freq; + char serialnumber[STLINK_SERIAL_BUFFER_SIZE]; + bool semihosting; + const char* current_memory_map; } st_state_t; @@ -97,20 +95,6 @@ BOOL WINAPI CtrlHandler(DWORD fdwCtrlType) { } #endif - -static stlink_t* do_connect(st_state_t *st) { - stlink_t *sl = NULL; - - if (serial_specified) { - sl = stlink_open_usb(st->logging_level, st->connect_mode, serialnumber, st->freq); - } else { - sl = stlink_open_usb(st->logging_level, st->connect_mode, NULL, st->freq); - } - - return(sl); -} - - int parse_options(int argc, char** argv, st_state_t *st) { static struct option long_options[] = { {"help", no_argument, NULL, 'h'}, @@ -119,6 +103,7 @@ int parse_options(int argc, char** argv, st_state_t *st) { {"multi", optional_argument, NULL, 'm'}, {"no-reset", optional_argument, NULL, 'n'}, {"hot-plug", optional_argument, NULL, 'n'}, + {"connect-under-reset", optional_argument, NULL, 'u'}, {"freq", optional_argument, NULL, 'F'}, {"version", no_argument, NULL, 'V'}, {"semihosting", no_argument, NULL, SEMIHOSTING_OPTION}, @@ -138,6 +123,8 @@ int parse_options(int argc, char** argv, st_state_t *st) { "\t\t\tst-util will continue listening for connections after disconnect.\n" " -n, --no-reset, --hot-plug\n" "\t\t\tDo not reset board on connection.\n" + " -u, --connect-under-reset\n" + "\t\t\tConnect to the board before executing any instructions.\n" " -F 1800K, --freq=1M\n" "\t\t\tSet the frequency of the SWD/JTAG interface.\n" " --semihosting\n" @@ -182,11 +169,14 @@ int parse_options(int argc, char** argv, st_state_t *st) { break; case 'm': - st->persistent = 1; + st->persistent = true; break; case 'n': st->connect_mode = CONNECT_HOT_PLUG; break; + case 'u': + st->connect_mode = CONNECT_UNDER_RESET; + break; case 'F': st->freq = arg_parse_freq(optarg); if (st->freq < 0) { @@ -198,12 +188,11 @@ int parse_options(int argc, char** argv, st_state_t *st) { printf("v%s\n", STLINK_VERSION); exit(EXIT_SUCCESS); case SEMIHOSTING_OPTION: - semihosting = true; + st->semihosting = true; break; case SERIAL_OPTION: printf("use serial %s\n", optarg); - memcpy(serialnumber, optarg, STLINK_SERIAL_BUFFER_SIZE); - serial_specified = true; + memcpy(st->serialnumber, optarg, STLINK_SERIAL_BUFFER_SIZE); break; } @@ -232,8 +221,7 @@ int main(int argc, char** argv) { printf("st-util\n"); - sl = do_connect(&state); - + sl = stlink_open_usb(state.logging_level, state.connect_mode, state.serialnumber, state.freq); if (sl == NULL) { return(1); } if (sl->chip_id == STLINK_CHIPID_UNKNOWN) { @@ -241,7 +229,9 @@ int main(int argc, char** argv) { return(1); } + sl->verbose = 0; connected_stlink = sl; + #if defined(_WIN32) SetConsoleCtrlHandler((PHANDLER_ROUTINE) CtrlHandler, TRUE); #else @@ -250,18 +240,14 @@ int main(int argc, char** argv) { signal(SIGSEGV, &cleanup); #endif - if (state.connect_mode != CONNECT_HOT_PLUG) { stlink_reset(sl); } - DLOG("Chip ID is %#010x, Core ID is %#08x.\n", sl->chip_id, sl->core_id); - sl->verbose = 0; - current_memory_map = make_memory_map(sl); + state.current_memory_map = make_memory_map(sl); #if defined(_WIN32) WSADATA wsadata; if (WSAStartup(MAKEWORD(2, 2), &wsadata) != 0) { goto winsock_error; } - #endif init_cache(sl); @@ -865,16 +851,13 @@ static int flash_populate(stm32_addr_t addr, uint8_t* data, unsigned length) { return(0); } -static int flash_go(stlink_t *sl) { +static int flash_go(stlink_t *sl, st_state_t *st) { int error = -1; int ret; flash_loader_t fl; - // some kinds of clock settings do not allow writing to flash. - stlink_reset(sl); + stlink_target_connect(sl, st->connect_mode); stlink_force_debug(sl); - // delay to ensure that STM32 HSI clock and others have started up fully - usleep(10000); for (struct flash_block* fb = flash_root; fb; fb = fb->next) { ILOG("flash_erase: block %08x -> %04x\n", fb->addr, fb->length); @@ -909,7 +892,7 @@ static int flash_go(stlink_t *sl) { } stlink_flashloader_stop(sl, &fl); - stlink_soft_reset(sl, 1 /* halt on reset */); + stlink_reset(sl, RESET_SOFT_AND_HALT); error = 0; error: @@ -1119,10 +1102,9 @@ int serve(stlink_t *sl, st_state_t *st) { close_socket(sock); + stlink_target_connect(sl, st->connect_mode); stlink_force_debug(sl); - if (st->connect_mode != CONNECT_HOT_PLUG) { stlink_reset(sl); } - init_code_breakpoints(sl); init_data_watchpoints(sl); @@ -1198,7 +1180,7 @@ int serve(stlink_t *sl, st_state_t *st) { if (strcmp(op, "read")) { data = NULL; } else if (!strcmp(type, "memory-map")) { - data = current_memory_map; + data = st->current_memory_map; } else if (!strcmp(type, "features")) { data = target_description; } else { @@ -1269,22 +1251,14 @@ int serve(stlink_t *sl, st_state_t *st) { } else if (!strncmp(cmd, "jtag_reset", 10)) { // jtag_reset reply = strdup("OK"); - ret = stlink_jtag_reset(sl, 0); - - if (ret) { - DLOG("Rcmd: jtag_reset failed with jtag_reset\n"); - reply = strdup("E00"); - } - - ret = stlink_jtag_reset(sl, 1); + ret = stlink_reset(sl, RESET_HARD); if (ret) { DLOG("Rcmd: jtag_reset failed with jtag_reset\n"); reply = strdup("E00"); } ret = stlink_force_debug(sl); - if (ret) { DLOG("Rcmd: jtag_reset failed with force_debug\n"); reply = strdup("E00"); @@ -1297,14 +1271,12 @@ int serve(stlink_t *sl, st_state_t *st) { } else if (!strncmp(cmd, "reset", 5)) { // reset ret = stlink_force_debug(sl); - if (ret) { DLOG("Rcmd: reset failed with force_debug\n"); reply = strdup("E00"); } - ret = stlink_reset(sl); - + ret = stlink_reset(sl, RESET_AUTO); if (ret) { DLOG("Rcmd: reset failed with reset\n"); reply = strdup("E00"); @@ -1325,10 +1297,10 @@ int serve(stlink_t *sl, st_state_t *st) { while (isspace(*arg)) { arg++; } // skip whitespaces if (!strncmp(arg, "enable", 6) || !strncmp(arg, "1", 1)) { - semihosting = true; + st->semihosting = true; reply = strdup("OK"); } else if (!strncmp(arg, "disable", 7) || !strncmp(arg, "0", 1)) { - semihosting = false; + st->semihosting = false; reply = strdup("OK"); } else { DLOG("Rcmd: unknown semihosting arg: '%s'\n", arg); @@ -1407,7 +1379,7 @@ int serve(stlink_t *sl, st_state_t *st) { free(decoded); } else if (!strcmp(cmdName, "FlashDone")) { - if (flash_go(sl)) { + if (flash_go(sl, st)) { reply = strdup("E08"); } else { reply = strdup("OK"); @@ -1453,7 +1425,7 @@ int serve(stlink_t *sl, st_state_t *st) { int offset = 0; uint16_t insn; - if (!semihosting) { break; } + if (!st->semihosting) { break; } ret = stlink_read_all_regs (sl, ®); @@ -1821,7 +1793,7 @@ int serve(stlink_t *sl, st_state_t *st) { case 'R': { // reset the core. - ret = stlink_reset(sl); + ret = stlink_reset(sl, RESET_AUTO); if (ret) { DLOG("R packet : stlink_reset failed\n"); } init_code_breakpoints(sl); @@ -1835,25 +1807,19 @@ int serve(stlink_t *sl, st_state_t *st) { case 'k': // kill request - reset the connection itself ret = stlink_run(sl); - if (ret) { DLOG("Kill: stlink_run failed\n"); } ret = stlink_exit_debug_mode(sl); - if (ret) { DLOG("Kill: stlink_exit_debug_mode failed\n"); } stlink_close(sl); - sl = do_connect(st); - + sl = stlink_open_usb(st->logging_level, st->connect_mode, st->serialnumber, st->freq); if (sl == NULL || sl->chip_id == STLINK_CHIPID_UNKNOWN) { cleanup(0); } connected_stlink = sl; - if (st->connect_mode != CONNECT_HOT_PLUG) { stlink_reset(sl); } - ret = stlink_force_debug(sl); - if (ret) { DLOG("Kill: stlink_force_debug failed\n"); } init_cache(sl); diff --git a/src/stlink-lib/sg.c b/src/stlink-lib/sg.c index 840466e75..c5946ed19 100644 --- a/src/stlink-lib/sg.c +++ b/src/stlink-lib/sg.c @@ -1114,7 +1114,7 @@ stlink_t* stlink_v1_open(const int verbose, int reset) { stlink_enter_swd_mode(sl); // now we are ready to read the parameters - if (reset) { stlink_reset(sl); } + if (reset) { stlink_reset(sl, RESET_AUTO); } stlink_load_device_params(sl); ILOG("Successfully opened a stlink v1 debugger\n"); diff --git a/src/stlink-lib/usb.c b/src/stlink-lib/usb.c index ce0d672c8..99b5f51ef 100644 --- a/src/stlink-lib/usb.c +++ b/src/stlink-lib/usb.c @@ -512,13 +512,8 @@ int _stlink_usb_reset(stlink_t * sl) { unsigned char* const data = sl->q_buf; unsigned char* const cmd = sl->c_buf; ssize_t size; - uint32_t dhcsr; - unsigned timeout; int i, rep_len = 2; - // clear S_RESET_ST in DHCSR registr - _stlink_usb_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); - // send reset command i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); cmd[i++] = STLINK_DEBUG_COMMAND; @@ -536,30 +531,7 @@ int _stlink_usb_reset(stlink_t * sl) { return((int)size); } - usleep(10000); - - dhcsr = 0; - _stlink_usb_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); - if ((dhcsr & STLINK_REG_DHCSR_S_RESET_ST) == 0) { - // reset not done yet - // try reset through AIRCR so that NRST does not need to be connected - - WLOG("NRST is not connected\n"); - DLOG("Using reset through SYSRESETREQ\n"); - return stlink_soft_reset(sl, 0); - } - - // waiting for a reset within 500ms - timeout = time_ms() + 500; - while (time_ms() < timeout) { - // DDI0337E, p. 10-4, Debug Halting Control and Status Register - dhcsr = STLINK_REG_DHCSR_S_RESET_ST; - _stlink_usb_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); - if ((dhcsr&STLINK_REG_DHCSR_S_RESET_ST) == 0) - return(0); - } - - return(-1); + return(0); } int _stlink_usb_jtag_reset(stlink_t * sl, int value) { @@ -1382,26 +1354,7 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, enum connect_type connect, DLOG("JTAG/SWD freq set to %d\n", freq); stlink_set_swdclk(sl, freq); - if (connect == CONNECT_UNDER_RESET) { - stlink_jtag_reset(sl, 0); - - if (stlink_current_mode(sl) != STLINK_DEV_DEBUG_MODE) { stlink_enter_swd_mode(sl); } - - stlink_force_debug(sl); - stlink_jtag_reset(sl, 1); - usleep(10000); - } - - if (stlink_current_mode(sl) != STLINK_DEV_DEBUG_MODE) { stlink_enter_swd_mode(sl); } - - if (connect == CONNECT_NORMAL) { - if ( sl->version.stlink_v > 1) { stlink_jtag_reset(sl, 2); } - - stlink_reset(sl); - usleep(10000); - } - - stlink_load_device_params(sl); + stlink_target_connect(sl, connect); return(sl); on_libusb_error: diff --git a/src/stlink-lib/usb.h b/src/stlink-lib/usb.h index f48ef225d..27de32700 100644 --- a/src/stlink-lib/usb.h +++ b/src/stlink-lib/usb.h @@ -48,12 +48,6 @@ extern "C" { #define STLINK_SG_SIZE 31 #define STLINK_CMD_SIZE 16 -enum connect_type { - CONNECT_HOT_PLUG = 0, - CONNECT_NORMAL = 1, - CONNECT_UNDER_RESET = 2, -}; - struct stlink_libusb { libusb_context* libusb_ctx; libusb_device_handle* usb_handle; diff --git a/tests/sg.c b/tests/sg.c index 745df845f..7584ab5d4 100644 --- a/tests/sg.c +++ b/tests/sg.c @@ -46,7 +46,7 @@ int main(void) { // main() ripped out of old stlink-hw.c stlink_core_id(sl); stlink_status(sl); // stlink_force_debug(sl); - stlink_reset(sl); + stlink_reset(sl, RESET_AUTO); stlink_status(sl); // core system control block stlink_read_mem32(sl, 0xe000ed00, 4); diff --git a/tests/usb.c b/tests/usb.c index 03c135f00..5c5c2077d 100644 --- a/tests/usb.c +++ b/tests/usb.c @@ -93,7 +93,7 @@ int main(int ac, char** av) { stlink_status(sl); printf("-- reset\n"); - stlink_reset(sl); + stlink_reset(sl, RESET_AUTO); stlink_force_debug(sl); /* Test reg write */ stlink_write_reg(sl, 0x01234567, 3); From 6bd99d4b55cd33c7f3773eda8aadea10e1288b5e Mon Sep 17 00:00:00 2001 From: anton Date: Tue, 6 Apr 2021 22:03:52 +0500 Subject: [PATCH 232/503] flash_loader: fixed interrupt masking --- doc/dev/developer.txt | 7 ++++--- doc/tutorial.md | 2 +- inc/backend.h | 2 +- inc/stlink.h | 8 +++++++- src/common.c | 8 ++++---- src/st-flash/flash.c | 2 +- src/st-trace/trace.c | 2 +- src/st-util/gdb-server.c | 16 ++++++++-------- src/stlink-lib/flash_loader.c | 2 +- src/stlink-lib/sg.c | 3 ++- src/stlink-lib/usb.c | 7 +++++-- tests/sg.c | 4 ++-- tests/usb.c | 2 +- 13 files changed, 38 insertions(+), 27 deletions(-) diff --git a/doc/dev/developer.txt b/doc/dev/developer.txt index 9c4da22f7..e3091c003 100644 --- a/doc/dev/developer.txt +++ b/doc/dev/developer.txt @@ -244,18 +244,19 @@ Description: Backend: "jtag_reset" Arguments: sl: Pointer to the stlink data structure, returned by stlink_v1_open() or stlink_open_usb() - value: 0: drive low, 1: drive high, 2: ???? + value: 0: drive low, 1: drive high, 2: pulse Return: -1 for error. 0 for success. Include: inc/stlink.h -Prototype: int stlink_run(stlink_t *sl); +Prototype: int stlink_run(stlink_t *sl, enum run_type type); Definition: src/common.c Description: Just calls the backend "run" procedure. Backend: "run" Arguments: - sl: Pointer to the stlink data structure, returned by stlink_v1_open() or stlink_open_usb() + sl: Pointer to the stlink data structure, returned by stlink_v1_open() or stlink_open_usb() + type: RUN_NORMAL - run target, RUN_FLASH_LOADER - run target with masking interrupts Return: -1 for error. 0 for success. Include: inc/stlink.h diff --git a/doc/tutorial.md b/doc/tutorial.md index 21f1498ee..71af3d45e 100644 --- a/doc/tutorial.md +++ b/doc/tutorial.md @@ -8,7 +8,7 @@ | --freq=n[k][m] | st-info
st-flash
st-util | The frequency of the SWD/JTAG interface can be specified, to override the default 1800 kHz configuration.
This option solely accepts decimal values (5K or 1.8M) with the unit `Hz` being left out. Valid frequencies are:
`5K, 15K, 25K, 50K, 100K, 125K, 240K, 480K, 950K, 1200K, 1800K, 4000K(4M)`. | v1.6.1 | | --opt | st-flash | Optimisation can be enabled in order to skip flashing empty (0x00 or 0xff) bytes at the end of binary file.
This may cause some garbage data left after a flash operation. This option was enabled by default in earlier releases. | v1.6.1 | | --reset | st-flash | Trigger a reset after flashing. The default uses the hardware reset through `NRST` pin.
A software reset (via `AIRCR`; since v1.5.1) is used, if the hardware reset failed (`NRST` pin not connected). | v1.0.0 | -| --connect-under-reset | st-info
st-flash | Connect under reset. Option makes it possible to connect to the device before code execution. This is useful
when the target contains code that lets the device go to sleep, disables debug pins or other special code. | v1.6.1 | +| --connect-under-reset | st-info
st-flash
st-util | Connect under reset. Option makes it possible to connect to the device before code execution. This is useful
when the target contains code that lets the device go to sleep, disables debug pins or other special code. | v1.6.1 | | --hot-plug | st-info
st-flash
st-util | Connect to the target without reset. | v1.6.2 | | --probe | st-info | Display hardware information about the connected programmer and target MCU. | v1.2.0 | | --version | st-info
st-flash
st-util | Print version information. | v1.3.0 | diff --git a/inc/backend.h b/inc/backend.h index ebd438127..a45dccd82 100644 --- a/inc/backend.h +++ b/inc/backend.h @@ -10,7 +10,7 @@ int (*core_id) (stlink_t * stl); int (*reset) (stlink_t * stl); int (*jtag_reset) (stlink_t * stl, int value); - int (*run) (stlink_t * stl); + int (*run) (stlink_t * stl, enum run_type type); int (*status) (stlink_t * stl); int (*version) (stlink_t *sl); int (*read_debug32) (stlink_t *sl, uint32_t addr, uint32_t *data); diff --git a/inc/stlink.h b/inc/stlink.h index 8fe6033d6..ec119c145 100644 --- a/inc/stlink.h +++ b/inc/stlink.h @@ -191,6 +191,12 @@ enum reset_type { RESET_SOFT_AND_HALT = 3, }; +enum run_type { + RUN_NORMAL = 0, + RUN_FLASH_LOADER = 1, +}; + + typedef struct _stlink stlink_t; #include @@ -250,7 +256,7 @@ int stlink_exit_dfu_mode(stlink_t *sl); void stlink_close(stlink_t *sl); int stlink_core_id(stlink_t *sl); int stlink_reset(stlink_t *sl, enum reset_type type); -int stlink_run(stlink_t *sl); +int stlink_run(stlink_t *sl, enum run_type type); int stlink_status(stlink_t *sl); int stlink_version(stlink_t *sl); int stlink_read_debug32(stlink_t *sl, uint32_t addr, uint32_t *data); diff --git a/src/common.c b/src/common.c index 928091eb4..63086ab22 100644 --- a/src/common.c +++ b/src/common.c @@ -1791,7 +1791,7 @@ int stlink_reset(stlink_t *sl, enum reset_type type) { return(0); } -int stlink_run(stlink_t *sl) { +int stlink_run(stlink_t *sl, enum run_type type) { struct stlink_reg rr; DLOG("*** stlink_run ***\n"); @@ -1804,7 +1804,7 @@ int stlink_run(stlink_t *sl) { stlink_write_reg(sl, rr.xpsr | (1 << 24), 16); } - return(sl->backend->run(sl)); + return(sl->backend->run(sl, type)); } int stlink_set_swdclk(stlink_t *sl, int freq_khz) { @@ -2096,7 +2096,7 @@ int stlink_trace_read(stlink_t* sl, uint8_t* buf, size_t size) { void stlink_run_at(stlink_t *sl, stm32_addr_t addr) { stlink_write_reg(sl, addr, 15); /* pc register */ - stlink_run(sl); + stlink_run(sl, RUN_NORMAL); while (stlink_is_core_halted(sl)) { usleep(3000000); } } @@ -2258,7 +2258,7 @@ static void stlink_fwrite_finalize(stlink_t *sl, stm32_addr_t addr) { // set PC to the reset routine stlink_read_debug32(sl, addr + 4, &val); stlink_write_reg(sl, val, 15); - stlink_run(sl); + stlink_run(sl, RUN_NORMAL); } int stlink_mwrite_sram(stlink_t * sl, uint8_t* data, uint32_t length, stm32_addr_t addr) { diff --git a/src/st-flash/flash.c b/src/st-flash/flash.c index 5eb607758..ede0f1179 100644 --- a/src/st-flash/flash.c +++ b/src/st-flash/flash.c @@ -17,7 +17,7 @@ static void cleanup(int signum) { (void)signum; if (connected_stlink) { // switch back to mass storage mode before closing - stlink_run(connected_stlink); + stlink_run(connected_stlink, RUN_NORMAL); stlink_exit_debug_mode(connected_stlink); stlink_close(connected_stlink); } diff --git a/src/st-trace/trace.c b/src/st-trace/trace.c index f40a9d683..f28624475 100644 --- a/src/st-trace/trace.c +++ b/src/st-trace/trace.c @@ -539,7 +539,7 @@ int main(int argc, char** argv) memset(&trace, 0, sizeof(trace)); trace.start_time = time(NULL); - if (stlink_run(stlink)) { + if (stlink_run(stlink, RUN_NORMAL)) { ELOG("Unable to run device\n"); if (!settings.force) return APP_RESULT_STLINK_STATE_ERROR; diff --git a/src/st-util/gdb-server.c b/src/st-util/gdb-server.c index c2a220df3..c6d329456 100644 --- a/src/st-util/gdb-server.c +++ b/src/st-util/gdb-server.c @@ -74,7 +74,7 @@ static void init_cache(stlink_t *sl); static void _cleanup() { if (connected_stlink) { // Switch back to mass storage mode before closing - stlink_run(connected_stlink); + stlink_run(connected_stlink, RUN_NORMAL); stlink_exit_debug_mode(connected_stlink); stlink_close(connected_stlink); } @@ -252,11 +252,11 @@ int main(int argc, char** argv) { init_cache(sl); - do { // don't go beserk if serve() returns with error + do { // don't go beserk if serve() returns with error if (serve(sl, &state)) { usleep (1 * 1000); } - sl = connected_stlink; // in case serve() changed the connection - stlink_run(sl); // continue + sl = connected_stlink; // in case serve() changed the connection + stlink_run(sl, RUN_NORMAL); // continue } while (state.persistent); #if defined(_WIN32) @@ -1229,7 +1229,7 @@ int serve(stlink_t *sl, st_state_t *st) { if (!strncmp(cmd, "resume", 6)) { // resume DLOG("Rcmd: resume\n"); cache_sync(sl); - ret = stlink_run(sl); + ret = stlink_run(sl, RUN_NORMAL); if (ret) { DLOG("Rcmd: resume failed\n"); @@ -1396,7 +1396,7 @@ int serve(stlink_t *sl, st_state_t *st) { case 'c': cache_sync(sl); - ret = stlink_run(sl); + ret = stlink_run(sl, RUN_NORMAL); if (ret) { DLOG("Semihost: run failed\n"); } @@ -1466,7 +1466,7 @@ int serve(stlink_t *sl, st_state_t *st) { // continue execution cache_sync(sl); - ret = stlink_run(sl); + ret = stlink_run(sl, RUN_NORMAL); if (ret) { DLOG("Semihost: continue execution failed with stlink_run\n"); } } else { @@ -1806,7 +1806,7 @@ int serve(stlink_t *sl, st_state_t *st) { } case 'k': // kill request - reset the connection itself - ret = stlink_run(sl); + ret = stlink_run(sl, RUN_NORMAL); if (ret) { DLOG("Kill: stlink_run failed\n"); } ret = stlink_exit_debug_mode(sl); diff --git a/src/stlink-lib/flash_loader.c b/src/stlink-lib/flash_loader.c index cd7096490..ba5efdb8e 100644 --- a/src/stlink-lib/flash_loader.c +++ b/src/stlink-lib/flash_loader.c @@ -347,7 +347,7 @@ int stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t targe } /* Run loader */ - stlink_run(sl); + stlink_run(sl, RUN_FLASH_LOADER); /* This piece of code used to try to spin for .1 second by waiting doing 10000 rounds of 10 µs. * But because this usually runs on Unix-like OSes, the 10 µs get rounded up to the "tick" diff --git a/src/stlink-lib/sg.c b/src/stlink-lib/sg.c index c5946ed19..07971284f 100644 --- a/src/stlink-lib/sg.c +++ b/src/stlink-lib/sg.c @@ -731,8 +731,9 @@ void stlink_write_dreg(stlink_t *sl, uint32_t reg, uint32_t addr) { } // force the core exit the debug mode. -int _stlink_sg_run(stlink_t *sl) { +int _stlink_sg_run(stlink_t *sl, enum run_type type) { struct stlink_libsg *sg = sl->backend_data; + (void)(type); //unused clear_cdb(sg); sg->cdb_cmd_blk[1] = STLINK_DEBUG_RUNCORE; sl->q_len = 2; diff --git a/src/stlink-lib/usb.c b/src/stlink-lib/usb.c index 99b5f51ef..2754db06f 100644 --- a/src/stlink-lib/usb.c +++ b/src/stlink-lib/usb.c @@ -590,14 +590,17 @@ int _stlink_usb_step(stlink_t* sl) { /** * This seems to do a good job of restarting things from the beginning? * @param sl + * @param type */ -int _stlink_usb_run(stlink_t* sl) { +int _stlink_usb_run(stlink_t* sl, enum run_type type) { struct stlink_libusb * const slu = sl->backend_data; int res; if (sl->version.jtag_api != STLINK_JTAG_API_V1) { - res = _stlink_usb_write_debug32(sl, STLINK_REG_DHCSR, STLINK_REG_DHCSR_DBGKEY | STLINK_REG_DHCSR_C_DEBUGEN); + res = _stlink_usb_write_debug32(sl, STLINK_REG_DHCSR, + STLINK_REG_DHCSR_DBGKEY | STLINK_REG_DHCSR_C_DEBUGEN | + ((type==RUN_FLASH_LOADER)?STLINK_REG_DHCSR_C_MASKINTS:0)); return(res); } diff --git a/tests/sg.c b/tests/sg.c index 7584ab5d4..d88fbe760 100644 --- a/tests/sg.c +++ b/tests/sg.c @@ -159,7 +159,7 @@ int main(void) { // main() ripped out of old stlink-hw.c #endif #if 0 - stlink_run(sl); + stlink_run(sl, RUN_NORMAL); stlink_status(sl); stlink_force_debug(sl); stlink_status(sl); @@ -196,7 +196,7 @@ int main(void) { // main() ripped out of old stlink-hw.c #endif #if 0 - stlink_run(sl); + stlink_run(sl, RUN_NORMAL); stlink_status(sl); // back to mass mode, just in case ... stlink_exit_debug_mode(sl); diff --git a/tests/usb.c b/tests/usb.c index 5c5c2077d..742f5c578 100644 --- a/tests/usb.c +++ b/tests/usb.c @@ -111,7 +111,7 @@ int main(int ac, char** av) { stlink_step(sl); printf("-- run\n"); - stlink_run(sl); + stlink_run(sl, RUN_NORMAL); printf("-- exit_debug_mode\n"); stlink_exit_debug_mode(sl); From c2e898c9228e2b13378987354f602745e1ca7b1c Mon Sep 17 00:00:00 2001 From: anton Date: Tue, 6 Apr 2021 22:43:15 +0500 Subject: [PATCH 233/503] Manual NRST pulse shaping Automatic generation via argument two of the jtag_reset function seem doesn't to work --- src/common.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/src/common.c b/src/common.c index 63086ab22..1cb5c6db0 100644 --- a/src/common.c +++ b/src/common.c @@ -1751,7 +1751,12 @@ int stlink_reset(stlink_t *sl, enum reset_type type) { if (type == RESET_HARD || type == RESET_AUTO) { // hardware target reset - if (sl->version.stlink_v > 1) { stlink_jtag_reset(sl, STLINK_JTAG_DRIVE_NRST_PULSE); } + if (sl->version.stlink_v > 1) { + stlink_jtag_reset(sl, STLINK_JTAG_DRIVE_NRST_LOW); + // minimum reset pulse duration of 20 us (RM0008, 8.1.2 Power reset) + usleep(100); + stlink_jtag_reset(sl, STLINK_JTAG_DRIVE_NRST_HIGH); + } if (sl->backend->reset(sl)) { return(-1); } usleep(10000); } @@ -4522,6 +4527,9 @@ int stlink_target_connect(stlink_t *sl, enum connect_type connect) { if (connect == CONNECT_UNDER_RESET) { stlink_jtag_reset(sl, STLINK_JTAG_DRIVE_NRST_LOW); + // minimum reset pulse duration of 20 us (RM0008, 8.1.2 Power reset) + usleep(20); + if (stlink_current_mode(sl) != STLINK_DEV_DEBUG_MODE) { stlink_enter_swd_mode(sl); } stlink_force_debug(sl); From 31738583967b89cf6416fd45a17ca8a7adfe12e2 Mon Sep 17 00:00:00 2001 From: anton Date: Wed, 7 Apr 2021 20:57:17 +0500 Subject: [PATCH 234/503] gdb-server: set target configuration after client connects --- src/st-util/gdb-server.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/src/st-util/gdb-server.c b/src/st-util/gdb-server.c index c6d329456..006a0e3aa 100644 --- a/src/st-util/gdb-server.c +++ b/src/st-util/gdb-server.c @@ -242,16 +242,12 @@ int main(int argc, char** argv) { DLOG("Chip ID is %#010x, Core ID is %#08x.\n", sl->chip_id, sl->core_id); - state.current_memory_map = make_memory_map(sl); - #if defined(_WIN32) WSADATA wsadata; if (WSAStartup(MAKEWORD(2, 2), &wsadata) != 0) { goto winsock_error; } #endif - init_cache(sl); - do { // don't go beserk if serve() returns with error if (serve(sl, &state)) { usleep (1 * 1000); } @@ -1102,12 +1098,22 @@ int serve(stlink_t *sl, st_state_t *st) { close_socket(sock); + uint32_t chip_id = sl->chip_id; + stlink_target_connect(sl, st->connect_mode); stlink_force_debug(sl); + if (sl->chip_id != chip_id) { + WLOG("Target has changed!\n"); + } + init_code_breakpoints(sl); init_data_watchpoints(sl); + init_cache(sl); + + st->current_memory_map = make_memory_map(sl); + ILOG("GDB connected.\n"); /* From d2a2c9825a739d92f2c4b7604ca732a2c1e3161e Mon Sep 17 00:00:00 2001 From: anton Date: Mon, 12 Apr 2021 22:34:44 +0500 Subject: [PATCH 235/503] Fixed chipid detection on Cortex-MO+ core --- src/common.c | 3 ++- src/stlink-lib/reg.h | 1 + 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/src/common.c b/src/common.c index a17392cf1..f230bee64 100644 --- a/src/common.c +++ b/src/common.c @@ -1240,7 +1240,8 @@ int stlink_chip_id(stlink_t *sl, uint32_t *chip_id) { cpu_id.part == STLINK_REG_CMx_CPUID_PARTNO_CM7) { // STM32H7 chipid in 0x5c001000 (RM0433 pg3189) ret = stlink_read_debug32(sl, 0x5c001000, chip_id); - } else if (cpu_id.part == STLINK_REG_CMx_CPUID_PARTNO_CM0) { + } else if (cpu_id.part == STLINK_REG_CMx_CPUID_PARTNO_CM0 || + cpu_id.part == STLINK_REG_CMx_CPUID_PARTNO_CM0P) { // STM32F0 (RM0091, pg914; RM0360, pg713) // STM32L0 (RM0377, pg813; RM0367, pg915; RM0376, pg917) // STM32G0 (RM0444, pg1367) diff --git a/src/stlink-lib/reg.h b/src/stlink-lib/reg.h index 4849806d7..b581a269c 100644 --- a/src/stlink-lib/reg.h +++ b/src/stlink-lib/reg.h @@ -4,6 +4,7 @@ #define STLINK_REG_CM3_CPUID 0xE000ED00 #define STLINK_REG_CMx_CPUID_PARTNO_CM0 0xC20 +#define STLINK_REG_CMx_CPUID_PARTNO_CM0P 0xC60 #define STLINK_REG_CMx_CPUID_PARTNO_CM3 0xC23 #define STLINK_REG_CMx_CPUID_PARTNO_CM4 0xC24 #define STLINK_REG_CMx_CPUID_PARTNO_CM7 0xC27 From dfb00775a3e332c8575d8d5dfc86365de04ed2e3 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Thu, 15 Apr 2021 22:39:24 +0200 Subject: [PATCH 236/503] Updated changelog --- CHANGELOG.md | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index 57426342a..0ac52da73 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -1,6 +1,6 @@ # stlink Changelog -# v1.6.2 +# v1.7.0 Release date: 2020-04-xx @@ -8,7 +8,8 @@ This release drops support for the STLINK/V1 programmer on macOS 10.13. Features: -- Extended support for STM32H7 & rework of software reset ([#532](https://github.com/stlink-org/stlink/pull/532), [#868](https://github.com/stlink-org/stlink/pull/868), [#1059](https://github.com/stlink-org/stlink/pull/1059), [#1063](https://github.com/stlink-org/stlink/pull/1063), [#1071](https://github.com/stlink-org/stlink/pull/1071)) +- Extended set of cmd line arguments for st-info and st-util ([#332](https://github.com/stlink-org/stlink/pull/332), [#990](https://github.com/stlink-org/stlink/pull/990), [#1091](https://github.com/stlink-org/stlink/pull/1091), [#1114](https://github.com/stlink-org/stlink/pull/1114)) +- Extended support for STM32H7 & rework of software reset ([#532](https://github.com/stlink-org/stlink/pull/532), [#801](https://github.com/stlink-org/stlink/pull/801), [#868](https://github.com/stlink-org/stlink/pull/868), [#1059](https://github.com/stlink-org/stlink/pull/1059), [#1063](https://github.com/stlink-org/stlink/pull/1063), [#1071](https://github.com/stlink-org/stlink/pull/1071)) - Added support for STM32H742/743/753 ([#671](https://github.com/stlink-org/stlink/pull/671), [#793](https://github.com/stlink-org/stlink/pull/793), [#823](https://github.com/stlink-org/stlink/pull/823), [#998](https://github.com/stlink-org/stlink/pull/998), [#1052](https://github.com/stlink-org/stlink/pull/1052)) - Official support for STLINK-V3 programmers (commit [#5e0a502](https://github.com/stlink-org/stlink/commit/5e0a502df812495bfa96fa9116a19f1306152b17), [#820](https://github.com/stlink-org/stlink/pull/820), [#1022](https://github.com/stlink-org/stlink/pull/1022), [#1025](https://github.com/stlink-org/stlink/pull/1025)) - Added preliminary support for STM32L5x2 ([#904](https://github.com/stlink-org/stlink/pull/904), [#999](https://github.com/stlink-org/stlink/pull/999)) @@ -39,7 +40,7 @@ Updates & changes: Fixes: -- Flash loader rework ([#356](https://github.com/stlink-org/stlink/pull/356), [#556](https://github.com/stlink-org/stlink/pull/556), [#593](https://github.com/stlink-org/stlink/pull/593), [#597](https://github.com/stlink-org/stlink/pull/597), [#607](https://github.com/stlink-org/stlink/pull/607), [#612](https://github.com/stlink-org/stlink/pull/612), [#638](https://github.com/stlink-org/stlink/pull/638), [#661](https://github.com/stlink-org/stlink/pull/661), [#690](https://github.com/stlink-org/stlink/pull/690), [#818](https://github.com/stlink-org/stlink/pull/818), [#854](https://github.com/stlink-org/stlink/pull/854), [#868](https://github.com/stlink-org/stlink/pull/868), [#967](https://github.com/stlink-org/stlink/pull/967), [#979](https://github.com/stlink-org/stlink/pull/979), [#1043](https://github.com/stlink-org/stlink/pull/1043), [#1054](https://github.com/stlink-org/stlink/pull/1054), [#1092](https://github.com/stlink-org/stlink/pull/1092), [#1105](https://github.com/stlink-org/stlink/pull/1105), [#1113](https://github.com/stlink-org/stlink/pull/1113)) +- Flash loader rework ([#356](https://github.com/stlink-org/stlink/pull/356), [#556](https://github.com/stlink-org/stlink/pull/556), [#593](https://github.com/stlink-org/stlink/pull/593), [#597](https://github.com/stlink-org/stlink/pull/597), [#607](https://github.com/stlink-org/stlink/pull/607), [#612](https://github.com/stlink-org/stlink/pull/612), [#638](https://github.com/stlink-org/stlink/pull/638), [#661](https://github.com/stlink-org/stlink/pull/661), [#690](https://github.com/stlink-org/stlink/pull/690), [#807](https://github.com/stlink-org/stlink/pull/807), [#817](https://github.com/stlink-org/stlink/pull/817), [#818](https://github.com/stlink-org/stlink/pull/818), [#854](https://github.com/stlink-org/stlink/pull/854), [#868](https://github.com/stlink-org/stlink/pull/868), [#967](https://github.com/stlink-org/stlink/pull/967), [#979](https://github.com/stlink-org/stlink/pull/979), [#1043](https://github.com/stlink-org/stlink/pull/1043), [#1054](https://github.com/stlink-org/stlink/pull/1054), [#1092](https://github.com/stlink-org/stlink/pull/1092), [#1105](https://github.com/stlink-org/stlink/pull/1105), [#1113](https://github.com/stlink-org/stlink/pull/1113)) - Fixed old DFU serial number for STLINK programmers ([#417](https://github.com/stlink-org/stlink/pull/417), [#494](https://github.com/stlink-org/stlink/pull/494), [#1106](https://github.com/stlink-org/stlink/pull/1106)) - Use vl flashloader for all STM32F1 series ([#769](https://github.com/stlink-org/stlink/pull/769), [#1041](https://github.com/stlink-org/stlink/pull/1041), [#1044](https://github.com/stlink-org/stlink/pull/1044)) - [regression] Changed timeout on flash write ([#787](https://github.com/stlink-org/stlink/pull/787), [#981](https://github.com/stlink-org/stlink/pull/981), [#987](https://github.com/stlink-org/stlink/pull/987)) @@ -52,7 +53,7 @@ Fixes: - Fixed `connect under reset` for `st-flash` and `st-util` ([#983](https://github.com/stlink-org/stlink/pull/983)) - Fix for `mmap() size_t overflow` in `st-flash` ([#988](https://github.com/stlink-org/stlink/pull/988), [#989](https://github.com/stlink-org/stlink/pull/989)) - [regression] `stlink-gui` installation issue on Ubuntu-18.04 ([#1001](https://github.com/stlink-org/stlink/pull/1001), [#1004](https://github.com/stlink-org/stlink/pull/1004), [#1006](https://github.com/stlink-org/stlink/pull/1006)) -- `st-util`: wrong register values passed to `gdb` (STLink/V2) ([#1002](https://github.com/stlink-org/stlink/pull/1002), [#1011](https://github.com/stlink-org/stlink/pull/1011), [#1026](https://github.com/stlink-org/stlink/pull/1026), [#1027](https://github.com/stlink-org/stlink/pull/1027), [#1064](https://github.com/stlink-org/stlink/pull/1064), [#1065](https://github.com/stlink-org/stlink/pull/1065)) +- `st-util`: wrong register values passed to `gdb` (STLink/V2) ([#1002](https://github.com/stlink-org/stlink/pull/1002), [#1011](https://github.com/stlink-org/stlink/pull/1011), [#1026](https://github.com/stlink-org/stlink/pull/1026), [#1027](https://github.com/stlink-org/stlink/pull/1027), [#1038](https://github.com/stlink-org/stlink/pull/1038),[#1064](https://github.com/stlink-org/stlink/pull/1064), [#1065](https://github.com/stlink-org/stlink/pull/1065)) - GDB: Fixed problems with target description ([#1013](https://github.com/stlink-org/stlink/pull/1013), [#1088](https://github.com/stlink-org/stlink/pull/1088), [#1109](https://github.com/stlink-org/stlink/pull/1109)) - [doc] Fixed wrong path for `rules.d` folder ([#1020](https://github.com/stlink-org/stlink/pull/1020)) - Fixed support for STLINK/V1 programmer ([#1045](https://github.com/stlink-org/stlink/pull/1045), [#1105](https://github.com/stlink-org/stlink/pull/1105)) @@ -61,7 +62,7 @@ Fixes: - Bugfixes for compilation with clang ([#1076](https://github.com/stlink-org/stlink/pull/1076), [#1078](https://github.com/stlink-org/stlink/pull/1078)) - Fixed compilation with GCC 11 ([#1077](https://github.com/stlink-org/stlink/pull/1077)) - [regression] Flash_loader: increased wait rounds for slow boards ([#1085](https://github.com/stlink-org/stlink/pull/1085)) -- Fixed support for writing option bytes ([#1102](https://github.com/stlink-org/stlink/pull/1102)) +- Fixed support for writing option bytes ([#1102](https://github.com/stlink-org/stlink/pull/1102), [#1128](https://github.com/stlink-org/stlink/pull/1128)) - [doc] Corrected spelling mistake in bug report template ([#1103](https://github.com/stlink-org/stlink/pull/1103)) - Fixed STM32WB55 reading DEBUG IDCODE from the wrong address ([#1100](https://github.com/stlink-org/stlink/pull/1100), [#1101](https://github.com/stlink-org/stlink/pull/1101)) - Applied missing changes to tests ([#1119](https://github.com/stlink-org/stlink/pull/1119)) @@ -75,7 +76,7 @@ This release drops support for some older operating systems. Check project READM Features: -- Basic compatibility for STLink/V3 programmer ([#271](https://github.com/stlink-org/stlink/pull/271), [#863](https://github.com/stlink-org/stlink/pull/863), [#954](https://github.com/stlink-org/stlink/pull/954)) +- Basic compatibility for STLink/V3 programmer ([#271](https://github.com/stlink-org/stlink/pull/271), [#863](https://github.com/stlink-org/stlink/pull/863), [#954](https://github.com/stlink-org/stlink/pull/954), [#1023](https://github.com/stlink-org/stlink/pull/1023)) - Added support for JTAG command API v2 & distinguish protocol versions v1 and v2 - Compatibility with the STLink/V3 firmware which dropped support for the previous API v1 - As of firmware version J11 the STLink/V1 programmer supports API v2 commands as well @@ -142,6 +143,7 @@ Updates & changes: Fixes: +- Improvements and fixes of the flash loaders, unification of the reset function ([#244](https://github.com/stlink-org/stlink/pull/244), [#382](https://github.com/stlink-org/stlink/pull/382), [#705](https://github.com/stlink-org/stlink/pull/705), [#980](https://github.com/stlink-org/stlink/pull/980), [#995](https://github.com/stlink-org/stlink/pull/995), [#1115](https://github.com/stlink-org/stlink/pull/1115), [#1117](https://github.com/stlink-org/stlink/pull/1117), [#1122](https://github.com/stlink-org/stlink/pull/1122), [#1124](https://github.com/stlink-org/stlink/pull/1124)) - Fixed wait-loop for `flash_loader_run()` ([#290](https://github.com/stlink-org/stlink/pull/290)) - Better argument parsing for CLI tools: `stlink_open_usb` can address v1, v2, v3 ([#378](https://github.com/stlink-org/stlink/pull/378), [#922](https://github.com/stlink-org/stlink/pull/922)) - Clear the PG bit before setting the `PER` bit ([#579](https://github.com/stlink-org/stlink/pull/579), [#876](https://github.com/stlink-org/stlink/pull/876)) @@ -163,6 +165,7 @@ Fixes: - Set static link for `libssp` (stack-smashing protection) ([#960](https://github.com/stlink-org/stlink/pull/960), [#961](https://github.com/stlink-org/stlink/pull/961)) - Fixed udev rules installing to wrong directory ([#966](https://github.com/stlink-org/stlink/pull/966)) - Fixed formatting for options display in `st-flash` & `st-info` (commits [#c783d0e](https://github.com/stlink-org/stlink/commit/c783d0e777ccc83a7a8be26a4f4d3414e0478560) and [#562cd24](https://github.com/stlink-org/stlink/commit/562cd2496e696dbd22950925866aac662d81ee5f)) +- Fixed reading of chip ID on Cortex-M0+ core ([#1125](https://github.com/stlink-org/stlink/pull/1125), [#1126](https://github.com/stlink-org/stlink/pull/1126)) # v1.6.0 From 9c1315a73296841ed3c25b4ea9500c187ab8236d Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Fri, 16 Apr 2021 00:10:20 +0200 Subject: [PATCH 237/503] Fixed GitHub Actions code scanning alerts --- src/common.c | 6800 ++++++++++++++++++++------------------ src/st-trace/trace.c | 990 +++--- src/stlink-lib/logging.c | 127 +- 3 files changed, 4089 insertions(+), 3828 deletions(-) diff --git a/src/common.c b/src/common.c index 57322cefd..4541aa31c 100644 --- a/src/common.c +++ b/src/common.c @@ -1,20 +1,20 @@ #define DEBUG_FLASH 0 #include +#include #include #include #include -#include #include -#include #include -#include #include +#include +#include -#include +#include #include #include -#include +#include #ifdef STLINK_HAVE_SYS_MMAN_H #include @@ -35,7 +35,8 @@ /* stm32f FPEC flash controller interface, pm0063 manual */ // TODO - all of this needs to be abstracted out.... -// STM32F05x is identical, based on RM0091 (DM00031936, Doc ID 018940 Rev 2, August 2012) +// STM32F05x is identical, based on RM0091 (DM00031936, Doc ID 018940 Rev 2, +// August 2012) #define FLASH_REGS_ADDR 0x40022000 #define FLASH_REGS_SIZE 0x28 @@ -48,7 +49,8 @@ #define FLASH_OBR (FLASH_REGS_ADDR + 0x1c) #define FLASH_WRPR (FLASH_REGS_ADDR + 0x20) -// STM32F10x_XL has two flash memory banks with separate registers to control the second bank. +// STM32F10x_XL has two flash memory banks with separate registers to control +// the second bank. #define FLASH_KEYR2 (FLASH_REGS_ADDR + 0x44) #define FLASH_SR2 (FLASH_REGS_ADDR + 0x4c) #define FLASH_CR2 (FLASH_REGS_ADDR + 0x50) @@ -128,113 +130,112 @@ // Mostly the same as STM32G0 chips, but there are a few extra // registers because 'cat 3' devices can have two Flash banks. #define STM32G4_FLASH_REGS_ADDR (STM32Gx_FLASH_REGS_ADDR) -#define STM32G4_FLASH_PDKEYR (STM32G4_FLASH_REGS_ADDR + 0x04) -#define STM32G4_FLASH_PCROP1SR (STM32G4_FLASH_REGS_ADDR + 0x24) -#define STM32G4_FLASH_PCROP1ER (STM32G4_FLASH_REGS_ADDR + 0x28) -#define STM32G4_FLASH_WRP1AR (STM32G4_FLASH_REGS_ADDR + 0x2C) -#define STM32G4_FLASH_WRP1BR (STM32G4_FLASH_REGS_ADDR + 0x30) -#define STM32G4_FLASH_PCROP2SR (STM32G4_FLASH_REGS_ADDR + 0x44) -#define STM32G4_FLASH_PCROP2ER (STM32G4_FLASH_REGS_ADDR + 0x48) -#define STM32G4_FLASH_WRP2AR (STM32G4_FLASH_REGS_ADDR + 0x4C) -#define STM32G4_FLASH_WRP2BR (STM32G4_FLASH_REGS_ADDR + 0x50) -#define STM32G4_FLASH_SEC1R (STM32G4_FLASH_REGS_ADDR + 0x70) -#define STM32G4_FLASH_SEC2R (STM32G4_FLASH_REGS_ADDR + 0x74) +#define STM32G4_FLASH_PDKEYR (STM32G4_FLASH_REGS_ADDR + 0x04) +#define STM32G4_FLASH_PCROP1SR (STM32G4_FLASH_REGS_ADDR + 0x24) +#define STM32G4_FLASH_PCROP1ER (STM32G4_FLASH_REGS_ADDR + 0x28) +#define STM32G4_FLASH_WRP1AR (STM32G4_FLASH_REGS_ADDR + 0x2C) +#define STM32G4_FLASH_WRP1BR (STM32G4_FLASH_REGS_ADDR + 0x30) +#define STM32G4_FLASH_PCROP2SR (STM32G4_FLASH_REGS_ADDR + 0x44) +#define STM32G4_FLASH_PCROP2ER (STM32G4_FLASH_REGS_ADDR + 0x48) +#define STM32G4_FLASH_WRP2AR (STM32G4_FLASH_REGS_ADDR + 0x4C) +#define STM32G4_FLASH_WRP2BR (STM32G4_FLASH_REGS_ADDR + 0x50) +#define STM32G4_FLASH_SEC1R (STM32G4_FLASH_REGS_ADDR + 0x70) +#define STM32G4_FLASH_SEC2R (STM32G4_FLASH_REGS_ADDR + 0x74) // G0/G4 FLASH control register -#define STM32Gx_FLASH_CR_PG (0) /* Program */ -#define STM32Gx_FLASH_CR_PER (1) /* Page erase */ -#define STM32Gx_FLASH_CR_MER1 (2) /* Mass erase */ -#define STM32Gx_FLASH_CR_PNB (3) /* Page number */ -#define STM32G0_FLASH_CR_PNG_LEN (5) /* STM32G0: 5 page number bits */ -#define STM32G4_FLASH_CR_PNG_LEN (7) /* STM32G4: 7 page number bits */ -#define STM32Gx_FLASH_CR_MER2 (15) /* Mass erase (2nd bank)*/ -#define STM32Gx_FLASH_CR_STRT (16) /* Start */ -#define STM32Gx_FLASH_CR_OPTSTRT (17) /* Start of modification of option bytes */ -#define STM32Gx_FLASH_CR_FSTPG (18) /* Fast programming */ -#define STM32Gx_FLASH_CR_EOPIE (24) /* End of operation interrupt enable */ -#define STM32Gx_FLASH_CR_ERRIE (25) /* Error interrupt enable */ -#define STM32Gx_FLASH_CR_OBL_LAUNCH (27) /* Forces the option byte loading */ -#define STM32Gx_FLASH_CR_OPTLOCK (30) /* Options Lock */ -#define STM32Gx_FLASH_CR_LOCK (31) /* FLASH_CR Lock */ +#define STM32Gx_FLASH_CR_PG (0) /* Program */ +#define STM32Gx_FLASH_CR_PER (1) /* Page erase */ +#define STM32Gx_FLASH_CR_MER1 (2) /* Mass erase */ +#define STM32Gx_FLASH_CR_PNB (3) /* Page number */ +#define STM32G0_FLASH_CR_PNG_LEN (5) /* STM32G0: 5 page number bits */ +#define STM32G4_FLASH_CR_PNG_LEN (7) /* STM32G4: 7 page number bits */ +#define STM32Gx_FLASH_CR_MER2 (15) /* Mass erase (2nd bank)*/ +#define STM32Gx_FLASH_CR_STRT (16) /* Start */ +#define STM32Gx_FLASH_CR_OPTSTRT \ + (17) /* Start of modification of option bytes */ +#define STM32Gx_FLASH_CR_FSTPG (18) /* Fast programming */ +#define STM32Gx_FLASH_CR_EOPIE (24) /* End of operation interrupt enable */ +#define STM32Gx_FLASH_CR_ERRIE (25) /* Error interrupt enable */ +#define STM32Gx_FLASH_CR_OBL_LAUNCH (27) /* Forces the option byte loading */ +#define STM32Gx_FLASH_CR_OPTLOCK (30) /* Options Lock */ +#define STM32Gx_FLASH_CR_LOCK (31) /* FLASH_CR Lock */ // G0/G4 FLASH status register #define STM32Gx_FLASH_SR_ERROR_MASK (0x3fa) -#define STM32Gx_FLASH_SR_PROGERR (3) -#define STM32Gx_FLASH_SR_WRPERR (4) -#define STM32Gx_FLASH_SR_PGAERR (5) -#define STM32Gx_FLASH_SR_BSY (16) /* FLASH_SR Busy */ -#define STM32Gx_FLASH_SR_EOP (0) /* FLASH_EOP End of Operation */ +#define STM32Gx_FLASH_SR_PROGERR (3) +#define STM32Gx_FLASH_SR_WRPERR (4) +#define STM32Gx_FLASH_SR_PGAERR (5) +#define STM32Gx_FLASH_SR_BSY (16) /* FLASH_SR Busy */ +#define STM32Gx_FLASH_SR_EOP (0) /* FLASH_EOP End of Operation */ // G4 FLASH option register -#define STM32G4_FLASH_OPTR_DBANK (22) /* FLASH_OPTR Dual Bank Mode */ +#define STM32G4_FLASH_OPTR_DBANK (22) /* FLASH_OPTR Dual Bank Mode */ // WB (RM0434) #define STM32WB_FLASH_REGS_ADDR ((uint32_t)0x58004000) -#define STM32WB_FLASH_ACR (STM32WB_FLASH_REGS_ADDR + 0x00) -#define STM32WB_FLASH_KEYR (STM32WB_FLASH_REGS_ADDR + 0x08) -#define STM32WB_FLASH_OPT_KEYR (STM32WB_FLASH_REGS_ADDR + 0x0C) -#define STM32WB_FLASH_SR (STM32WB_FLASH_REGS_ADDR + 0x10) -#define STM32WB_FLASH_CR (STM32WB_FLASH_REGS_ADDR + 0x14) -#define STM32WB_FLASH_ECCR (STM32WB_FLASH_REGS_ADDR + 0x18) -#define STM32WB_FLASH_OPTR (STM32WB_FLASH_REGS_ADDR + 0x20) +#define STM32WB_FLASH_ACR (STM32WB_FLASH_REGS_ADDR + 0x00) +#define STM32WB_FLASH_KEYR (STM32WB_FLASH_REGS_ADDR + 0x08) +#define STM32WB_FLASH_OPT_KEYR (STM32WB_FLASH_REGS_ADDR + 0x0C) +#define STM32WB_FLASH_SR (STM32WB_FLASH_REGS_ADDR + 0x10) +#define STM32WB_FLASH_CR (STM32WB_FLASH_REGS_ADDR + 0x14) +#define STM32WB_FLASH_ECCR (STM32WB_FLASH_REGS_ADDR + 0x18) +#define STM32WB_FLASH_OPTR (STM32WB_FLASH_REGS_ADDR + 0x20) #define STM32WB_FLASH_PCROP1ASR (STM32WB_FLASH_REGS_ADDR + 0x24) #define STM32WB_FLASH_PCROP1AER (STM32WB_FLASH_REGS_ADDR + 0x28) -#define STM32WB_FLASH_WRP1AR (STM32WB_FLASH_REGS_ADDR + 0x2C) -#define STM32WB_FLASH_WRP1BR (STM32WB_FLASH_REGS_ADDR + 0x30) +#define STM32WB_FLASH_WRP1AR (STM32WB_FLASH_REGS_ADDR + 0x2C) +#define STM32WB_FLASH_WRP1BR (STM32WB_FLASH_REGS_ADDR + 0x30) #define STM32WB_FLASH_PCROP1BSR (STM32WB_FLASH_REGS_ADDR + 0x34) #define STM32WB_FLASH_PCROP1BER (STM32WB_FLASH_REGS_ADDR + 0x38) -#define STM32WB_FLASH_IPCCBR (STM32WB_FLASH_REGS_ADDR + 0x3C) -#define STM32WB_FLASH_C2ACR (STM32WB_FLASH_REGS_ADDR + 0x5C) -#define STM32WB_FLASH_C2SR (STM32WB_FLASH_REGS_ADDR + 0x60) -#define STM32WB_FLASH_C2CR (STM32WB_FLASH_REGS_ADDR + 0x64) -#define STM32WB_FLASH_SFR (STM32WB_FLASH_REGS_ADDR + 0x80) -#define STM32WB_FLASH_SRRVR (STM32WB_FLASH_REGS_ADDR + 0x84) +#define STM32WB_FLASH_IPCCBR (STM32WB_FLASH_REGS_ADDR + 0x3C) +#define STM32WB_FLASH_C2ACR (STM32WB_FLASH_REGS_ADDR + 0x5C) +#define STM32WB_FLASH_C2SR (STM32WB_FLASH_REGS_ADDR + 0x60) +#define STM32WB_FLASH_C2CR (STM32WB_FLASH_REGS_ADDR + 0x64) +#define STM32WB_FLASH_SFR (STM32WB_FLASH_REGS_ADDR + 0x80) +#define STM32WB_FLASH_SRRVR (STM32WB_FLASH_REGS_ADDR + 0x84) // WB Flash control register. -#define STM32WB_FLASH_CR_STRT (16) /* Start */ -#define STM32WB_FLASH_CR_OPTLOCK (30) /* Option Lock */ -#define STM32WB_FLASH_CR_LOCK (31) /* Lock */ +#define STM32WB_FLASH_CR_STRT (16) /* Start */ +#define STM32WB_FLASH_CR_OPTLOCK (30) /* Option Lock */ +#define STM32WB_FLASH_CR_LOCK (31) /* Lock */ // WB Flash status register. #define STM32WB_FLASH_SR_ERROR_MASK (0x3f8) /* SR [9:3] */ -#define STM32WB_FLASH_SR_PROGERR (3) /* Programming alignment error */ -#define STM32WB_FLASH_SR_WRPERR (4) /* Write protection error */ -#define STM32WB_FLASH_SR_PGAERR (5) /* Programming error */ -#define STM32WB_FLASH_SR_BSY (16) /* Busy */ +#define STM32WB_FLASH_SR_PROGERR (3) /* Programming alignment error */ +#define STM32WB_FLASH_SR_WRPERR (4) /* Write protection error */ +#define STM32WB_FLASH_SR_PGAERR (5) /* Programming error */ +#define STM32WB_FLASH_SR_BSY (16) /* Busy */ // 32L4 register base is at FLASH_REGS_ADDR (0x40022000) -#define STM32L4_FLASH_KEYR (FLASH_REGS_ADDR + 0x08) -#define STM32L4_FLASH_OPTKEYR (FLASH_REGS_ADDR + 0x0C) -#define STM32L4_FLASH_SR (FLASH_REGS_ADDR + 0x10) -#define STM32L4_FLASH_CR (FLASH_REGS_ADDR + 0x14) -#define STM32L4_FLASH_OPTR (FLASH_REGS_ADDR + 0x20) +#define STM32L4_FLASH_KEYR (FLASH_REGS_ADDR + 0x08) +#define STM32L4_FLASH_OPTKEYR (FLASH_REGS_ADDR + 0x0C) +#define STM32L4_FLASH_SR (FLASH_REGS_ADDR + 0x10) +#define STM32L4_FLASH_CR (FLASH_REGS_ADDR + 0x14) +#define STM32L4_FLASH_OPTR (FLASH_REGS_ADDR + 0x20) #define STM32L4_FLASH_SR_ERROR_MASK 0x3f8 /* SR [9:3] */ -#define STM32L4_FLASH_SR_PROGERR 3 -#define STM32L4_FLASH_SR_WRPERR 4 -#define STM32L4_FLASH_SR_PGAERR 5 -#define STM32L4_FLASH_SR_BSY 16 - -#define STM32L4_FLASH_CR_LOCK 31 /* Lock control register */ -#define STM32L4_FLASH_CR_OPTLOCK 30 /* Lock option bytes */ -#define STM32L4_FLASH_CR_PG 0 /* Program */ -#define STM32L4_FLASH_CR_PER 1 /* Page erase */ -#define STM32L4_FLASH_CR_MER1 2 /* Bank 1 erase */ -#define STM32L4_FLASH_CR_MER2 15 /* Bank 2 erase */ -#define STM32L4_FLASH_CR_STRT 16 /* Start command */ -#define STM32L4_FLASH_CR_OPTSTRT 17 /* Start writing option bytes */ -#define STM32L4_FLASH_CR_BKER 11 /* Bank select for page erase */ -#define STM32L4_FLASH_CR_PNB 3 /* Page number (8 bits) */ +#define STM32L4_FLASH_SR_PROGERR 3 +#define STM32L4_FLASH_SR_WRPERR 4 +#define STM32L4_FLASH_SR_PGAERR 5 +#define STM32L4_FLASH_SR_BSY 16 + +#define STM32L4_FLASH_CR_LOCK 31 /* Lock control register */ +#define STM32L4_FLASH_CR_OPTLOCK 30 /* Lock option bytes */ +#define STM32L4_FLASH_CR_PG 0 /* Program */ +#define STM32L4_FLASH_CR_PER 1 /* Page erase */ +#define STM32L4_FLASH_CR_MER1 2 /* Bank 1 erase */ +#define STM32L4_FLASH_CR_MER2 15 /* Bank 2 erase */ +#define STM32L4_FLASH_CR_STRT 16 /* Start command */ +#define STM32L4_FLASH_CR_OPTSTRT 17 /* Start writing option bytes */ +#define STM32L4_FLASH_CR_BKER 11 /* Bank select for page erase */ +#define STM32L4_FLASH_CR_PNB 3 /* Page number (8 bits) */ #define STM32L4_FLASH_CR_OBL_LAUNCH 27 /* Option bytes reload */ // Bits requesting flash operations (useful when we want to clear them) -#define STM32L4_FLASH_CR_OPBITS \ - (uint32_t)((1lu << STM32L4_FLASH_CR_PG) | \ - (1lu << STM32L4_FLASH_CR_PER) | \ - (1lu << STM32L4_FLASH_CR_MER1) | \ - (1lu << STM32L4_FLASH_CR_MER1)) +#define STM32L4_FLASH_CR_OPBITS \ + (uint32_t)((1lu << STM32L4_FLASH_CR_PG) | (1lu << STM32L4_FLASH_CR_PER) | \ + (1lu << STM32L4_FLASH_CR_MER1) | (1lu << STM32L4_FLASH_CR_MER1)) // Page is fully specified by BKER and PNB #define STM32L4_FLASH_CR_PAGEMASK (uint32_t)(0x1fflu << STM32L4_FLASH_CR_PNB) -#define STM32L4_FLASH_OPTR_DUALBANK 21 +#define STM32L4_FLASH_OPTR_DUALBANK 21 // STM32L0x flash register base and offsets RM0090 - DM00031020.pdf #define STM32L0_FLASH_REGS_ADDR ((uint32_t)0x40022000) @@ -245,21 +246,21 @@ #define STM32L0_FLASH_OBL_LAUNCH (18) #define STM32L0_FLASH_SR_ERROR_MASK 0x00013F00 -#define STM32L0_FLASH_SR_WRPERR 8 -#define STM32L0_FLASH_SR_PGAERR 9 +#define STM32L0_FLASH_SR_WRPERR 8 +#define STM32L0_FLASH_SR_PGAERR 9 #define STM32L0_FLASH_SR_NOTZEROERR 16 -#define FLASH_ACR_OFF ((uint32_t) 0x00) -#define FLASH_PECR_OFF ((uint32_t) 0x04) -#define FLASH_PDKEYR_OFF ((uint32_t) 0x08) -#define FLASH_PEKEYR_OFF ((uint32_t) 0x0c) -#define FLASH_PRGKEYR_OFF ((uint32_t) 0x10) -#define FLASH_OPTKEYR_OFF ((uint32_t) 0x14) -#define FLASH_SR_OFF ((uint32_t) 0x18) -#define FLASH_OBR_OFF ((uint32_t) 0x1c) -#define FLASH_WRPR_OFF ((uint32_t) 0x20) - -//STM32F7 +#define FLASH_ACR_OFF ((uint32_t)0x00) +#define FLASH_PECR_OFF ((uint32_t)0x04) +#define FLASH_PDKEYR_OFF ((uint32_t)0x08) +#define FLASH_PEKEYR_OFF ((uint32_t)0x0c) +#define FLASH_PRGKEYR_OFF ((uint32_t)0x10) +#define FLASH_OPTKEYR_OFF ((uint32_t)0x14) +#define FLASH_SR_OFF ((uint32_t)0x18) +#define FLASH_OBR_OFF ((uint32_t)0x1c) +#define FLASH_WRPR_OFF ((uint32_t)0x20) + +// STM32F7 #define FLASH_F7_REGS_ADDR ((uint32_t)0x40023c00) #define FLASH_F7_KEYR (FLASH_F7_REGS_ADDR + 0x04) #define FLASH_F7_OPT_KEYR (FLASH_F7_REGS_ADDR + 0x08) @@ -279,14 +280,17 @@ #define FLASH_F7_SR_PGP_ERR 6 /* Programming parallelism error */ #define FLASH_F7_SR_PGA_ERR 5 /* Programming alignment error */ #define FLASH_F7_SR_WRP_ERR 4 /* Write protection error */ -#define FLASH_F7_SR_OP_ERR 1 /* Operation error */ -#define FLASH_F7_SR_EOP 0 /* End of operation */ +#define FLASH_F7_SR_OP_ERR 1 /* Operation error */ +#define FLASH_F7_SR_EOP 0 /* End of operation */ #define FLASH_F7_OPTCR1_BOOT_ADD0 0 #define FLASH_F7_OPTCR1_BOOT_ADD1 16 -#define FLASH_F7_SR_ERROR_MASK ((1 << FLASH_F7_SR_ERS_ERR) | (1 << FLASH_F7_SR_PGP_ERR) | (1 << FLASH_F7_SR_PGA_ERR) | (1 << FLASH_F7_SR_WRP_ERR) | (1 << FLASH_F7_SR_OP_ERR)) +#define FLASH_F7_SR_ERROR_MASK \ + ((1 << FLASH_F7_SR_ERS_ERR) | (1 << FLASH_F7_SR_PGP_ERR) | \ + (1 << FLASH_F7_SR_PGA_ERR) | (1 << FLASH_F7_SR_WRP_ERR) | \ + (1 << FLASH_F7_SR_OP_ERR)) -//STM32F4 +// STM32F4 #define FLASH_F4_REGS_ADDR ((uint32_t)0x40023c00) #define FLASH_F4_KEYR (FLASH_F4_REGS_ADDR + 0x04) #define FLASH_F4_OPT_KEYR (FLASH_F4_REGS_ADDR + 0x08) @@ -301,9 +305,9 @@ #define FLASH_F4_CR_SNB 3 #define FLASH_F4_CR_SNB_MASK 0xf8 #define FLASH_F4_SR_ERROR_MASK 0x000000F0 -#define FLASH_F4_SR_PGAERR 5 -#define FLASH_F4_SR_WRPERR 4 -#define FLASH_F4_SR_BSY 16 +#define FLASH_F4_SR_PGAERR 5 +#define FLASH_F4_SR_WRPERR 4 +#define FLASH_F4_SR_BSY 16 // STM32F2 #define FLASH_F2_REGS_ADDR ((uint32_t)0x40023c00) @@ -327,15 +331,17 @@ #define FLASH_H7_CR_SER 2 #define FLASH_H7_CR_BER 3 #define FLASH_H7_CR_PSIZE 4 -#define FLASH_H7_CR_START(chipid) (chipid==STLINK_CHIPID_STM32_H7AX?5:7) +#define FLASH_H7_CR_START(chipid) (chipid == STLINK_CHIPID_STM32_H7AX ? 5 : 7) #define FLASH_H7_CR_SNB 8 #define FLASH_H7_CR_SNB_MASK 0x700 -#define FLASH_H7_SR_QW 2 +#define FLASH_H7_SR_QW 2 #define FLASH_H7_SR_WRPERR 17 #define FLASH_H7_SR_PGSERR 18 #define FLASH_H7_SR_STRBERR 19 -#define FLASH_H7_SR_ERROR_MASK ((1 << FLASH_H7_SR_PGSERR) | (1 << FLASH_H7_SR_STRBERR) | (1 << FLASH_H7_SR_WRPERR)) +#define FLASH_H7_SR_ERROR_MASK \ + ((1 << FLASH_H7_SR_PGSERR) | (1 << FLASH_H7_SR_STRBERR) | \ + (1 << FLASH_H7_SR_WRPERR)) #define FLASH_H7_OPTCR_OPTLOCK 0 #define FLASH_H7_OPTCR_OPTSTART 1 @@ -362,1189 +368,1188 @@ #define FLASH_H7_OPTSR_CUR (FLASH_H7_REGS_ADDR + 0x1c) #define FLASH_H7_OPTCCR (FLASH_H7_REGS_ADDR + 0x24) -#define STM32F0_DBGMCU_CR 0xE0042004 -#define STM32F0_DBGMCU_CR_IWDG_STOP 8 -#define STM32F0_DBGMCU_CR_WWDG_STOP 9 +#define STM32F0_DBGMCU_CR 0xE0042004 +#define STM32F0_DBGMCU_CR_IWDG_STOP 8 +#define STM32F0_DBGMCU_CR_WWDG_STOP 9 -#define STM32F4_DBGMCU_APB1FZR1 0xE0042008 +#define STM32F4_DBGMCU_APB1FZR1 0xE0042008 #define STM32F4_DBGMCU_APB1FZR1_WWDG_STOP 11 #define STM32F4_DBGMCU_APB1FZR1_IWDG_STOP 12 -#define STM32L0_DBGMCU_APB1_FZ 0x40015808 -#define STM32L0_DBGMCU_APB1_FZ_WWDG_STOP 11 -#define STM32L0_DBGMCU_APB1_FZ_IWDG_STOP 12 +#define STM32L0_DBGMCU_APB1_FZ 0x40015808 +#define STM32L0_DBGMCU_APB1_FZ_WWDG_STOP 11 +#define STM32L0_DBGMCU_APB1_FZ_IWDG_STOP 12 -#define STM32H7_DBGMCU_APB1HFZ 0x5C001054 -#define STM32H7_DBGMCU_APB1HFZ_IWDG_STOP 18 +#define STM32H7_DBGMCU_APB1HFZ 0x5C001054 +#define STM32H7_DBGMCU_APB1HFZ_IWDG_STOP 18 -#define STM32WB_DBGMCU_APB1FZR1 0xE004203C +#define STM32WB_DBGMCU_APB1FZR1 0xE004203C #define STM32WB_DBGMCU_APB1FZR1_WWDG_STOP 11 #define STM32WB_DBGMCU_APB1FZR1_IWDG_STOP 12 -#define STM32F1_RCC_AHBENR 0x40021014 -#define STM32F1_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN +#define STM32F1_RCC_AHBENR 0x40021014 +#define STM32F1_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN -#define STM32F4_RCC_AHB1ENR 0x40023830 -#define STM32F4_RCC_DMAEN 0x00600000 // DMA2EN | DMA1EN +#define STM32F4_RCC_AHB1ENR 0x40023830 +#define STM32F4_RCC_DMAEN 0x00600000 // DMA2EN | DMA1EN -#define STM32G0_RCC_AHBENR 0x40021038 -#define STM32G0_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN +#define STM32G0_RCC_AHBENR 0x40021038 +#define STM32G0_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN -#define STM32G4_RCC_AHB1ENR 0x40021048 -#define STM32G4_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN +#define STM32G4_RCC_AHB1ENR 0x40021048 +#define STM32G4_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN -#define STM32L0_RCC_AHBENR 0x40021030 -#define STM32L0_RCC_DMAEN 0x00000001 // DMAEN +#define STM32L0_RCC_AHBENR 0x40021030 +#define STM32L0_RCC_DMAEN 0x00000001 // DMAEN -#define STM32H7_RCC_AHB1ENR 0x58024538 -#define STM32H7_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN +#define STM32H7_RCC_AHB1ENR 0x58024538 +#define STM32H7_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN -#define STM32WB_RCC_AHB1ENR 0x58000048 -#define STM32WB_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN +#define STM32WB_RCC_AHB1ENR 0x58000048 +#define STM32WB_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN #define L1_WRITE_BLOCK_SIZE 0x80 #define L0_WRITE_BLOCK_SIZE 0x40 - // Endianness // https://commandcenter.blogspot.com/2012/04/byte-order-fallacy.html // These functions encode and decode little endian uint16 and uint32 values. -void write_uint32(unsigned char* buf, uint32_t ui) { - buf[0] = ui; - buf[1] = ui >> 8; - buf[2] = ui >> 16; - buf[3] = ui >> 24; +void write_uint32(unsigned char *buf, uint32_t ui) { + buf[0] = ui; + buf[1] = ui >> 8; + buf[2] = ui >> 16; + buf[3] = ui >> 24; } -void write_uint16(unsigned char* buf, uint16_t ui) { - buf[0] = ui ; - buf[1] = ui >> 8; +void write_uint16(unsigned char *buf, uint16_t ui) { + buf[0] = ui; + buf[1] = ui >> 8; } uint32_t read_uint32(const unsigned char *c, const int pt) { - return ((uint32_t)c[pt]) | ((uint32_t)c[pt+1] << 8) | ((uint32_t)c[pt+2] << 16) | ((uint32_t)c[pt+3] << 24) ; + return ((uint32_t)c[pt]) | ((uint32_t)c[pt + 1] << 8) | + ((uint32_t)c[pt + 2] << 16) | ((uint32_t)c[pt + 3] << 24); } uint16_t read_uint16(const unsigned char *c, const int pt) { - return ((uint16_t)c[pt]) | ((uint16_t)c[pt+1] << 8); + return ((uint16_t)c[pt]) | ((uint16_t)c[pt + 1] << 8); } +static uint32_t get_stm32l0_flash_base(stlink_t *sl) { + switch (sl->chip_id) { + case STLINK_CHIPID_STM32_L0: + case STLINK_CHIPID_STM32_L0_CAT5: + case STLINK_CHIPID_STM32_L0_CAT2: + case STLINK_CHIPID_STM32_L011: + return (STM32L0_FLASH_REGS_ADDR); -static uint32_t get_stm32l0_flash_base(stlink_t *sl) -{ - switch (sl->chip_id) { - case STLINK_CHIPID_STM32_L0: - case STLINK_CHIPID_STM32_L0_CAT5: - case STLINK_CHIPID_STM32_L0_CAT2: - case STLINK_CHIPID_STM32_L011: - return(STM32L0_FLASH_REGS_ADDR); - - case STLINK_CHIPID_STM32_L1_CAT2: - case STLINK_CHIPID_STM32_L1_MEDIUM: - case STLINK_CHIPID_STM32_L1_MEDIUM_PLUS: - case STLINK_CHIPID_STM32_L1_HIGH: - return(STM32L1_FLASH_REGS_ADDR); + case STLINK_CHIPID_STM32_L1_CAT2: + case STLINK_CHIPID_STM32_L1_MEDIUM: + case STLINK_CHIPID_STM32_L1_MEDIUM_PLUS: + case STLINK_CHIPID_STM32_L1_HIGH: + return (STM32L1_FLASH_REGS_ADDR); - default: - WLOG("Flash base use default L0 address"); - return(STM32L0_FLASH_REGS_ADDR); - } + default: + WLOG("Flash base use default L0 address"); + return (STM32L0_FLASH_REGS_ADDR); + } } static uint32_t __attribute__((unused)) read_flash_rdp(stlink_t *sl) { - uint32_t rdp; - stlink_read_debug32(sl, FLASH_WRPR, &rdp); - return(rdp & 0xff); + uint32_t rdp; + stlink_read_debug32(sl, FLASH_WRPR, &rdp); + return (rdp & 0xff); } static inline uint32_t read_flash_cr(stlink_t *sl, unsigned bank) { - uint32_t reg, res; - - if (sl->flash_type == STLINK_FLASH_TYPE_F4) { - reg = FLASH_F4_CR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { - reg = FLASH_F7_CR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { - reg = STM32L4_FLASH_CR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { - reg = STM32Gx_FLASH_CR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { - reg = STM32WB_FLASH_CR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { - reg = (bank == BANK_1)?FLASH_H7_CR1:FLASH_H7_CR2; - } else { - reg = (bank == BANK_1)?FLASH_CR:FLASH_CR2; - } - - stlink_read_debug32(sl, reg, &res); + uint32_t reg, res; + + if (sl->flash_type == STLINK_FLASH_TYPE_F4) { + reg = FLASH_F4_CR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { + reg = FLASH_F7_CR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { + reg = STM32L4_FLASH_CR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || + sl->flash_type == STLINK_FLASH_TYPE_G4) { + reg = STM32Gx_FLASH_CR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + reg = STM32WB_FLASH_CR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; + } else { + reg = (bank == BANK_1) ? FLASH_CR : FLASH_CR2; + } + + stlink_read_debug32(sl, reg, &res); #if DEBUG_FLASH - fprintf(stdout, "CR:0x%x\n", res); + fprintf(stdout, "CR:0x%x\n", res); #endif - return(res); + return (res); } static inline unsigned int is_flash_locked(stlink_t *sl) { - /* return non zero for true */ - uint32_t cr_lock_shift; - uint32_t cr_reg; - uint32_t n; - - if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || - (sl->flash_type == STLINK_FLASH_TYPE_F1_XL)) { - cr_reg = FLASH_CR; - cr_lock_shift = FLASH_CR_LOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F4) { - cr_reg = FLASH_F4_CR; - cr_lock_shift = FLASH_F4_CR_LOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { - cr_reg = FLASH_F7_CR; - cr_lock_shift = FLASH_F7_CR_LOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { - cr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF; - cr_lock_shift = STM32L0_FLASH_PELOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { - cr_reg = STM32L4_FLASH_CR; - cr_lock_shift = STM32L4_FLASH_CR_LOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { - cr_reg = STM32Gx_FLASH_CR; - cr_lock_shift = STM32Gx_FLASH_CR_LOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { - cr_reg = STM32WB_FLASH_CR; - cr_lock_shift = STM32WB_FLASH_CR_LOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { - cr_reg = FLASH_H7_CR1; - cr_lock_shift = FLASH_H7_CR_LOCK; - } else { - ELOG("unsupported flash method, abort\n"); - return(-1); - } - - stlink_read_debug32(sl, cr_reg, &n); - return(n & (1u << cr_lock_shift)); + /* return non zero for true */ + uint32_t cr_lock_shift; + uint32_t cr_reg; + uint32_t n; + + if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || + (sl->flash_type == STLINK_FLASH_TYPE_F1_XL)) { + cr_reg = FLASH_CR; + cr_lock_shift = FLASH_CR_LOCK; + } else if (sl->flash_type == STLINK_FLASH_TYPE_F4) { + cr_reg = FLASH_F4_CR; + cr_lock_shift = FLASH_F4_CR_LOCK; + } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { + cr_reg = FLASH_F7_CR; + cr_lock_shift = FLASH_F7_CR_LOCK; + } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { + cr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF; + cr_lock_shift = STM32L0_FLASH_PELOCK; + } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { + cr_reg = STM32L4_FLASH_CR; + cr_lock_shift = STM32L4_FLASH_CR_LOCK; + } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || + sl->flash_type == STLINK_FLASH_TYPE_G4) { + cr_reg = STM32Gx_FLASH_CR; + cr_lock_shift = STM32Gx_FLASH_CR_LOCK; + } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + cr_reg = STM32WB_FLASH_CR; + cr_lock_shift = STM32WB_FLASH_CR_LOCK; + } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + cr_reg = FLASH_H7_CR1; + cr_lock_shift = FLASH_H7_CR_LOCK; + } else { + ELOG("unsupported flash method, abort\n"); + return (-1); + } + + stlink_read_debug32(sl, cr_reg, &n); + return (n & (1u << cr_lock_shift)); } static void unlock_flash(stlink_t *sl) { - uint32_t key_reg, key2_reg = 0; - uint32_t flash_key1 = FLASH_KEY1; - uint32_t flash_key2 = FLASH_KEY2; - /* The unlock sequence consists of 2 write cycles where 2 key values are written - * to the FLASH_KEYR register. - * An invalid sequence results in a definitive lock of the FPEC block until next reset. - */ - - if (sl->flash_type == STLINK_FLASH_TYPE_F0) { - key_reg = FLASH_KEYR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL) { - key_reg = FLASH_KEYR; - key2_reg = FLASH_KEYR2; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F4) { - key_reg = FLASH_F4_KEYR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { - key_reg = FLASH_F7_KEYR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { - key_reg = get_stm32l0_flash_base(sl) + FLASH_PEKEYR_OFF; - flash_key1 = FLASH_L0_PEKEY1; - flash_key2 = FLASH_L0_PEKEY2; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { - key_reg = STM32L4_FLASH_KEYR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { - key_reg = STM32Gx_FLASH_KEYR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { - key_reg = STM32WB_FLASH_KEYR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { - key_reg = FLASH_H7_KEYR1; - if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { - key2_reg = FLASH_H7_KEYR2; - } - } else { - ELOG("unsupported flash method, abort\n"); - return; - } + uint32_t key_reg, key2_reg = 0; + uint32_t flash_key1 = FLASH_KEY1; + uint32_t flash_key2 = FLASH_KEY2; + /* The unlock sequence consists of 2 write cycles where 2 key values are + * written to the FLASH_KEYR register. An invalid sequence results in a + * definitive lock of the FPEC block until next reset. + */ + + if (sl->flash_type == STLINK_FLASH_TYPE_F0) { + key_reg = FLASH_KEYR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL) { + key_reg = FLASH_KEYR; + key2_reg = FLASH_KEYR2; + } else if (sl->flash_type == STLINK_FLASH_TYPE_F4) { + key_reg = FLASH_F4_KEYR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { + key_reg = FLASH_F7_KEYR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { + key_reg = get_stm32l0_flash_base(sl) + FLASH_PEKEYR_OFF; + flash_key1 = FLASH_L0_PEKEY1; + flash_key2 = FLASH_L0_PEKEY2; + } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { + key_reg = STM32L4_FLASH_KEYR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || + sl->flash_type == STLINK_FLASH_TYPE_G4) { + key_reg = STM32Gx_FLASH_KEYR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + key_reg = STM32WB_FLASH_KEYR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + key_reg = FLASH_H7_KEYR1; + if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { + key2_reg = FLASH_H7_KEYR2; + } + } else { + ELOG("unsupported flash method, abort\n"); + return; + } - stlink_write_debug32(sl, key_reg, flash_key1); - stlink_write_debug32(sl, key_reg, flash_key2); + stlink_write_debug32(sl, key_reg, flash_key1); + stlink_write_debug32(sl, key_reg, flash_key2); - if (key2_reg) { - stlink_write_debug32(sl, key2_reg, flash_key1); - stlink_write_debug32(sl, key2_reg, flash_key2); - } + if (key2_reg) { + stlink_write_debug32(sl, key2_reg, flash_key1); + stlink_write_debug32(sl, key2_reg, flash_key2); + } } /* unlock flash if already locked */ static int unlock_flash_if(stlink_t *sl) { - if (is_flash_locked(sl)) { - unlock_flash(sl); + if (is_flash_locked(sl)) { + unlock_flash(sl); - if (is_flash_locked(sl)) { - WLOG("Failed to unlock flash!\n"); - return(-1); - } + if (is_flash_locked(sl)) { + WLOG("Failed to unlock flash!\n"); + return (-1); } + } - DLOG("Successfully unlocked flash\n"); - return(0); + DLOG("Successfully unlocked flash\n"); + return (0); } static void lock_flash(stlink_t *sl) { - uint32_t cr_lock_shift, cr_reg, n, cr2_reg = 0; - uint32_t cr_mask = 0xffffffffu; - - if (sl->flash_type == STLINK_FLASH_TYPE_F0) { - cr_reg = FLASH_CR; - cr_lock_shift = FLASH_CR_LOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL) { - cr_reg = FLASH_CR; - cr2_reg = FLASH_CR2; - cr_lock_shift = FLASH_CR_LOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F4) { - cr_reg = FLASH_F4_CR; - cr_lock_shift = FLASH_F4_CR_LOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { - cr_reg = FLASH_F7_CR; - cr_lock_shift = FLASH_F7_CR_LOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { - cr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF; - cr_lock_shift = STM32L0_FLASH_PELOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { - cr_reg = STM32L4_FLASH_CR; - cr_lock_shift = STM32L4_FLASH_CR_LOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { - cr_reg = STM32Gx_FLASH_CR; - cr_lock_shift = STM32Gx_FLASH_CR_LOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { - cr_reg = STM32WB_FLASH_CR; - cr_lock_shift = STM32WB_FLASH_CR_LOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { - cr_reg = FLASH_H7_CR1; - if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { - cr2_reg = FLASH_H7_CR2; - } - cr_lock_shift = FLASH_H7_CR_LOCK; - cr_mask = ~(1u << FLASH_H7_CR_SER); - } else { - ELOG("unsupported flash method, abort\n"); - return; - } + uint32_t cr_lock_shift, cr_reg, n, cr2_reg = 0; + uint32_t cr_mask = 0xffffffffu; + + if (sl->flash_type == STLINK_FLASH_TYPE_F0) { + cr_reg = FLASH_CR; + cr_lock_shift = FLASH_CR_LOCK; + } else if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL) { + cr_reg = FLASH_CR; + cr2_reg = FLASH_CR2; + cr_lock_shift = FLASH_CR_LOCK; + } else if (sl->flash_type == STLINK_FLASH_TYPE_F4) { + cr_reg = FLASH_F4_CR; + cr_lock_shift = FLASH_F4_CR_LOCK; + } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { + cr_reg = FLASH_F7_CR; + cr_lock_shift = FLASH_F7_CR_LOCK; + } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { + cr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF; + cr_lock_shift = STM32L0_FLASH_PELOCK; + } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { + cr_reg = STM32L4_FLASH_CR; + cr_lock_shift = STM32L4_FLASH_CR_LOCK; + } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || + sl->flash_type == STLINK_FLASH_TYPE_G4) { + cr_reg = STM32Gx_FLASH_CR; + cr_lock_shift = STM32Gx_FLASH_CR_LOCK; + } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + cr_reg = STM32WB_FLASH_CR; + cr_lock_shift = STM32WB_FLASH_CR_LOCK; + } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + cr_reg = FLASH_H7_CR1; + if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { + cr2_reg = FLASH_H7_CR2; + } + cr_lock_shift = FLASH_H7_CR_LOCK; + cr_mask = ~(1u << FLASH_H7_CR_SER); + } else { + ELOG("unsupported flash method, abort\n"); + return; + } - stlink_read_debug32(sl, cr_reg, &n); - n &= cr_mask; - n |= (1u << cr_lock_shift); - stlink_write_debug32(sl, cr_reg, n); + stlink_read_debug32(sl, cr_reg, &n); + n &= cr_mask; + n |= (1u << cr_lock_shift); + stlink_write_debug32(sl, cr_reg, n); - if (cr2_reg) { - n = read_flash_cr(sl, BANK_2) | (1u << cr_lock_shift); - stlink_write_debug32(sl, cr2_reg, n); - } + if (cr2_reg) { + n = read_flash_cr(sl, BANK_2) | (1u << cr_lock_shift); + stlink_write_debug32(sl, cr2_reg, n); + } } static bool is_flash_option_locked(stlink_t *sl) { - uint32_t optlock_shift, optcr_reg; - int active_bit_level = 1; - uint32_t n; - - switch (sl->flash_type) { - case STLINK_FLASH_TYPE_F0: - case STLINK_FLASH_TYPE_F1_XL: - optcr_reg = FLASH_CR; - optlock_shift = FLASH_CR_OPTWRE; - active_bit_level = 0; /* bit is "option write enable", not lock */ - break; - case STLINK_FLASH_TYPE_F4: - optcr_reg = FLASH_F4_OPTCR; - optlock_shift = FLASH_F4_OPTCR_LOCK; - break; - case STLINK_FLASH_TYPE_F7: - optcr_reg = FLASH_F7_OPTCR; - optlock_shift = FLASH_F7_OPTCR_LOCK; - break; - case STLINK_FLASH_TYPE_L0: - optcr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF; - optlock_shift = STM32L0_FLASH_OPTLOCK; - break; - case STLINK_FLASH_TYPE_L4: - optcr_reg = STM32L4_FLASH_CR; - optlock_shift = STM32L4_FLASH_CR_OPTLOCK; - break; - case STLINK_FLASH_TYPE_G0: - case STLINK_FLASH_TYPE_G4: - optcr_reg = STM32Gx_FLASH_CR; - optlock_shift = STM32Gx_FLASH_CR_OPTLOCK; - break; - case STLINK_FLASH_TYPE_WB: - optcr_reg = STM32WB_FLASH_CR; - optlock_shift = STM32WB_FLASH_CR_OPTLOCK; - break; - case STLINK_FLASH_TYPE_H7: - optcr_reg = FLASH_H7_OPTCR; - optlock_shift = FLASH_H7_OPTCR_OPTLOCK; - break; - default: - ELOG("unsupported flash method, abort\n"); - return -1; - } - - stlink_read_debug32(sl, optcr_reg, &n); - - if (active_bit_level == 0) { - return(!(n & (1u << optlock_shift))); - } - - return(n & (1u << optlock_shift)); - + uint32_t optlock_shift, optcr_reg; + int active_bit_level = 1; + uint32_t n; + + switch (sl->flash_type) { + case STLINK_FLASH_TYPE_F0: + case STLINK_FLASH_TYPE_F1_XL: + optcr_reg = FLASH_CR; + optlock_shift = FLASH_CR_OPTWRE; + active_bit_level = 0; /* bit is "option write enable", not lock */ + break; + case STLINK_FLASH_TYPE_F4: + optcr_reg = FLASH_F4_OPTCR; + optlock_shift = FLASH_F4_OPTCR_LOCK; + break; + case STLINK_FLASH_TYPE_F7: + optcr_reg = FLASH_F7_OPTCR; + optlock_shift = FLASH_F7_OPTCR_LOCK; + break; + case STLINK_FLASH_TYPE_L0: + optcr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF; + optlock_shift = STM32L0_FLASH_OPTLOCK; + break; + case STLINK_FLASH_TYPE_L4: + optcr_reg = STM32L4_FLASH_CR; + optlock_shift = STM32L4_FLASH_CR_OPTLOCK; + break; + case STLINK_FLASH_TYPE_G0: + case STLINK_FLASH_TYPE_G4: + optcr_reg = STM32Gx_FLASH_CR; + optlock_shift = STM32Gx_FLASH_CR_OPTLOCK; + break; + case STLINK_FLASH_TYPE_WB: + optcr_reg = STM32WB_FLASH_CR; + optlock_shift = STM32WB_FLASH_CR_OPTLOCK; + break; + case STLINK_FLASH_TYPE_H7: + optcr_reg = FLASH_H7_OPTCR; + optlock_shift = FLASH_H7_OPTCR_OPTLOCK; + break; + default: + ELOG("unsupported flash method, abort\n"); + return -1; + } + + stlink_read_debug32(sl, optcr_reg, &n); + + if (active_bit_level == 0) { + return (!(n & (1u << optlock_shift))); + } + + return (n & (1u << optlock_shift)); } static int lock_flash_option(stlink_t *sl) { - uint32_t optlock_shift, optcr_reg, n, optcr2_reg = 0; - int active_bit_level = 1; - - switch (sl->flash_type) { - case STLINK_FLASH_TYPE_F0: - case STLINK_FLASH_TYPE_F1_XL: - optcr_reg = FLASH_CR; - optlock_shift = FLASH_CR_OPTWRE; - active_bit_level = 0; - break; - case STLINK_FLASH_TYPE_F4: - optcr_reg = FLASH_F4_OPTCR; - optlock_shift = FLASH_F4_OPTCR_LOCK; - break; - case STLINK_FLASH_TYPE_F7: - optcr_reg = FLASH_F7_OPTCR; - optlock_shift = FLASH_F7_OPTCR_LOCK; - break; - case STLINK_FLASH_TYPE_L0: - optcr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF; - optlock_shift = STM32L0_FLASH_OPTLOCK; - break; - case STLINK_FLASH_TYPE_L4: - optcr_reg = STM32L4_FLASH_CR; - optlock_shift = STM32L4_FLASH_CR_OPTLOCK; - break; - case STLINK_FLASH_TYPE_G0: - case STLINK_FLASH_TYPE_G4: - optcr_reg = STM32Gx_FLASH_CR; - optlock_shift = STM32Gx_FLASH_CR_OPTLOCK; - break; - case STLINK_FLASH_TYPE_WB: - optcr_reg = STM32WB_FLASH_CR; - optlock_shift = STM32WB_FLASH_CR_OPTLOCK; - break; - case STLINK_FLASH_TYPE_H7: - optcr_reg = FLASH_H7_OPTCR; - optlock_shift = FLASH_H7_OPTCR_OPTLOCK; - if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) - optcr2_reg = FLASH_H7_OPTCR2; - break; - default: - ELOG("unsupported flash method, abort\n"); - return -1; - } - - stlink_read_debug32(sl, optcr_reg, &n); + uint32_t optlock_shift, optcr_reg, n, optcr2_reg = 0; + int active_bit_level = 1; + + switch (sl->flash_type) { + case STLINK_FLASH_TYPE_F0: + case STLINK_FLASH_TYPE_F1_XL: + optcr_reg = FLASH_CR; + optlock_shift = FLASH_CR_OPTWRE; + active_bit_level = 0; + break; + case STLINK_FLASH_TYPE_F4: + optcr_reg = FLASH_F4_OPTCR; + optlock_shift = FLASH_F4_OPTCR_LOCK; + break; + case STLINK_FLASH_TYPE_F7: + optcr_reg = FLASH_F7_OPTCR; + optlock_shift = FLASH_F7_OPTCR_LOCK; + break; + case STLINK_FLASH_TYPE_L0: + optcr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF; + optlock_shift = STM32L0_FLASH_OPTLOCK; + break; + case STLINK_FLASH_TYPE_L4: + optcr_reg = STM32L4_FLASH_CR; + optlock_shift = STM32L4_FLASH_CR_OPTLOCK; + break; + case STLINK_FLASH_TYPE_G0: + case STLINK_FLASH_TYPE_G4: + optcr_reg = STM32Gx_FLASH_CR; + optlock_shift = STM32Gx_FLASH_CR_OPTLOCK; + break; + case STLINK_FLASH_TYPE_WB: + optcr_reg = STM32WB_FLASH_CR; + optlock_shift = STM32WB_FLASH_CR_OPTLOCK; + break; + case STLINK_FLASH_TYPE_H7: + optcr_reg = FLASH_H7_OPTCR; + optlock_shift = FLASH_H7_OPTCR_OPTLOCK; + if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) + optcr2_reg = FLASH_H7_OPTCR2; + break; + default: + ELOG("unsupported flash method, abort\n"); + return -1; + } + + stlink_read_debug32(sl, optcr_reg, &n); + + if (active_bit_level == 0) { + n &= ~(1u << optlock_shift); + } else { + n |= (1u << optlock_shift); + } + + stlink_write_debug32(sl, optcr_reg, n); + + if (optcr2_reg) { + stlink_read_debug32(sl, optcr2_reg, &n); if (active_bit_level == 0) { - n &= ~(1u << optlock_shift); + n &= ~(1u << optlock_shift); } else { - n |= (1u << optlock_shift); + n |= (1u << optlock_shift); } - stlink_write_debug32(sl, optcr_reg, n); + stlink_write_debug32(sl, optcr2_reg, n); + } - if (optcr2_reg) { - stlink_read_debug32(sl, optcr2_reg, &n); - - if (active_bit_level == 0) { - n &= ~(1u << optlock_shift); - } else { - n |= (1u << optlock_shift); - } - - stlink_write_debug32(sl, optcr2_reg, n); - } - - return(0); + return (0); } static int unlock_flash_option(stlink_t *sl) { - uint32_t optkey_reg, optkey2_reg = 0; - uint32_t optkey1 = FLASH_OPTKEY1; - uint32_t optkey2 = FLASH_OPTKEY2; - - switch (sl->flash_type) { - case STLINK_FLASH_TYPE_F0: - case STLINK_FLASH_TYPE_F1_XL: - optkey_reg = FLASH_OPTKEYR; - optkey1 = FLASH_F0_OPTKEY1; - optkey2 = FLASH_F0_OPTKEY2; - break; - case STLINK_FLASH_TYPE_F4: - optkey_reg = FLASH_F4_OPT_KEYR; - break; - case STLINK_FLASH_TYPE_F7: - optkey_reg = FLASH_F7_OPT_KEYR; - break; - case STLINK_FLASH_TYPE_L0: - optkey_reg = get_stm32l0_flash_base(sl) + FLASH_OPTKEYR_OFF; - optkey1 = FLASH_L0_OPTKEY1; - optkey2 = FLASH_L0_OPTKEY2; - break; - case STLINK_FLASH_TYPE_L4: - optkey_reg = STM32L4_FLASH_OPTKEYR; - break; - case STLINK_FLASH_TYPE_G0: - case STLINK_FLASH_TYPE_G4: - optkey_reg = STM32Gx_FLASH_OPTKEYR; - break; - case STLINK_FLASH_TYPE_WB: - optkey_reg = STM32WB_FLASH_OPT_KEYR; - break; - case STLINK_FLASH_TYPE_H7: - optkey_reg = FLASH_H7_OPT_KEYR; - if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) - optkey2_reg = FLASH_H7_OPT_KEYR2; - break; - default: - ELOG("unsupported flash method, abort\n"); - return(-1); - } - - stlink_write_debug32(sl, optkey_reg, optkey1); - stlink_write_debug32(sl, optkey_reg, optkey2); - - if (optkey2_reg) { - stlink_write_debug32(sl, optkey2_reg, optkey1); - stlink_write_debug32(sl, optkey2_reg, optkey2); - } - - return(0); + uint32_t optkey_reg, optkey2_reg = 0; + uint32_t optkey1 = FLASH_OPTKEY1; + uint32_t optkey2 = FLASH_OPTKEY2; + + switch (sl->flash_type) { + case STLINK_FLASH_TYPE_F0: + case STLINK_FLASH_TYPE_F1_XL: + optkey_reg = FLASH_OPTKEYR; + optkey1 = FLASH_F0_OPTKEY1; + optkey2 = FLASH_F0_OPTKEY2; + break; + case STLINK_FLASH_TYPE_F4: + optkey_reg = FLASH_F4_OPT_KEYR; + break; + case STLINK_FLASH_TYPE_F7: + optkey_reg = FLASH_F7_OPT_KEYR; + break; + case STLINK_FLASH_TYPE_L0: + optkey_reg = get_stm32l0_flash_base(sl) + FLASH_OPTKEYR_OFF; + optkey1 = FLASH_L0_OPTKEY1; + optkey2 = FLASH_L0_OPTKEY2; + break; + case STLINK_FLASH_TYPE_L4: + optkey_reg = STM32L4_FLASH_OPTKEYR; + break; + case STLINK_FLASH_TYPE_G0: + case STLINK_FLASH_TYPE_G4: + optkey_reg = STM32Gx_FLASH_OPTKEYR; + break; + case STLINK_FLASH_TYPE_WB: + optkey_reg = STM32WB_FLASH_OPT_KEYR; + break; + case STLINK_FLASH_TYPE_H7: + optkey_reg = FLASH_H7_OPT_KEYR; + if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) + optkey2_reg = FLASH_H7_OPT_KEYR2; + break; + default: + ELOG("unsupported flash method, abort\n"); + return (-1); + } + + stlink_write_debug32(sl, optkey_reg, optkey1); + stlink_write_debug32(sl, optkey_reg, optkey2); + + if (optkey2_reg) { + stlink_write_debug32(sl, optkey2_reg, optkey1); + stlink_write_debug32(sl, optkey2_reg, optkey2); + } + + return (0); } static int unlock_flash_option_if(stlink_t *sl) { - if (is_flash_option_locked(sl)) { - if (unlock_flash_option(sl)) { - ELOG("Could not unlock flash option!\n"); - return(-1); - } + if (is_flash_option_locked(sl)) { + if (unlock_flash_option(sl)) { + ELOG("Could not unlock flash option!\n"); + return (-1); + } - if (is_flash_option_locked(sl)) { - ELOG("Failed to unlock flash option!\n"); - return(-1); - } + if (is_flash_option_locked(sl)) { + ELOG("Failed to unlock flash option!\n"); + return (-1); } + } - DLOG("Successfully unlocked flash option\n"); - return(0); + DLOG("Successfully unlocked flash option\n"); + return (0); } static void set_flash_cr_pg(stlink_t *sl, unsigned bank) { - uint32_t cr_reg, x; - - x = read_flash_cr(sl, bank); - - if (sl->flash_type == STLINK_FLASH_TYPE_F4) { - cr_reg = FLASH_F4_CR; - x |= 1 << FLASH_CR_PG; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { - cr_reg = FLASH_F7_CR; - x |= 1 << FLASH_CR_PG; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { - cr_reg = STM32L4_FLASH_CR; - x &= ~STM32L4_FLASH_CR_OPBITS; - x |= (1 << STM32L4_FLASH_CR_PG); - } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { - cr_reg = STM32Gx_FLASH_CR; - x |= (1 << FLASH_CR_PG); - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { - cr_reg = STM32WB_FLASH_CR; - x |= (1 << FLASH_CR_PG); - } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { - cr_reg = (bank == BANK_1)?FLASH_H7_CR1:FLASH_H7_CR2; - x |= (1 << FLASH_H7_CR_PG); - } else { - cr_reg = FLASH_CR; - x = (1 << FLASH_CR_PG); - } - - stlink_write_debug32(sl, cr_reg, x); + uint32_t cr_reg, x; + + x = read_flash_cr(sl, bank); + + if (sl->flash_type == STLINK_FLASH_TYPE_F4) { + cr_reg = FLASH_F4_CR; + x |= 1 << FLASH_CR_PG; + } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { + cr_reg = FLASH_F7_CR; + x |= 1 << FLASH_CR_PG; + } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { + cr_reg = STM32L4_FLASH_CR; + x &= ~STM32L4_FLASH_CR_OPBITS; + x |= (1 << STM32L4_FLASH_CR_PG); + } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || + sl->flash_type == STLINK_FLASH_TYPE_G4) { + cr_reg = STM32Gx_FLASH_CR; + x |= (1 << FLASH_CR_PG); + } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + cr_reg = STM32WB_FLASH_CR; + x |= (1 << FLASH_CR_PG); + } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + cr_reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; + x |= (1 << FLASH_H7_CR_PG); + } else { + cr_reg = FLASH_CR; + x = (1 << FLASH_CR_PG); + } + + stlink_write_debug32(sl, cr_reg, x); } static void clear_flash_cr_pg(stlink_t *sl, unsigned bank) { - uint32_t cr_reg, n; - uint32_t bit = FLASH_CR_PG; - - if (sl->flash_type == STLINK_FLASH_TYPE_F4) { - cr_reg = FLASH_F4_CR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { - cr_reg = FLASH_F7_CR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { - cr_reg = STM32L4_FLASH_CR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { - cr_reg = STM32Gx_FLASH_CR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { - cr_reg = STM32WB_FLASH_CR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { - cr_reg = (bank == BANK_1)?FLASH_H7_CR1:FLASH_H7_CR2; - bit = FLASH_H7_CR_PG; - } else { - cr_reg = FLASH_CR; - } - - n = read_flash_cr(sl, bank) & ~(1 << bit); - stlink_write_debug32(sl, cr_reg, n); + uint32_t cr_reg, n; + uint32_t bit = FLASH_CR_PG; + + if (sl->flash_type == STLINK_FLASH_TYPE_F4) { + cr_reg = FLASH_F4_CR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { + cr_reg = FLASH_F7_CR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { + cr_reg = STM32L4_FLASH_CR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || + sl->flash_type == STLINK_FLASH_TYPE_G4) { + cr_reg = STM32Gx_FLASH_CR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + cr_reg = STM32WB_FLASH_CR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + cr_reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; + bit = FLASH_H7_CR_PG; + } else { + cr_reg = FLASH_CR; + } + + n = read_flash_cr(sl, bank) & ~(1 << bit); + stlink_write_debug32(sl, cr_reg, n); } static void set_flash_cr_per(stlink_t *sl, unsigned bank) { - uint32_t cr_reg, val; + uint32_t cr_reg, val; - if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { - cr_reg = STM32Gx_FLASH_CR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { - cr_reg = STM32WB_FLASH_CR; - } else { - cr_reg = (bank==BANK_1)?FLASH_CR:FLASH_CR2; - } + if (sl->flash_type == STLINK_FLASH_TYPE_G0 || + sl->flash_type == STLINK_FLASH_TYPE_G4) { + cr_reg = STM32Gx_FLASH_CR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + cr_reg = STM32WB_FLASH_CR; + } else { + cr_reg = (bank == BANK_1) ? FLASH_CR : FLASH_CR2; + } - stlink_read_debug32(sl, cr_reg, &val); - val |= (1 << FLASH_CR_PER); - stlink_write_debug32(sl, cr_reg, val); + stlink_read_debug32(sl, cr_reg, &val); + val |= (1 << FLASH_CR_PER); + stlink_write_debug32(sl, cr_reg, val); } static void clear_flash_cr_per(stlink_t *sl, unsigned bank) { - uint32_t cr_reg; + uint32_t cr_reg; - if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { - cr_reg = STM32Gx_FLASH_CR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { - cr_reg = STM32WB_FLASH_CR; - } else { - cr_reg = (bank==BANK_1)?FLASH_CR:FLASH_CR2; - } + if (sl->flash_type == STLINK_FLASH_TYPE_G0 || + sl->flash_type == STLINK_FLASH_TYPE_G4) { + cr_reg = STM32Gx_FLASH_CR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + cr_reg = STM32WB_FLASH_CR; + } else { + cr_reg = (bank == BANK_1) ? FLASH_CR : FLASH_CR2; + } - const uint32_t n = read_flash_cr(sl, bank) & ~(1 << FLASH_CR_PER); - stlink_write_debug32(sl, cr_reg, n); + const uint32_t n = read_flash_cr(sl, bank) & ~(1 << FLASH_CR_PER); + stlink_write_debug32(sl, cr_reg, n); } static void set_flash_cr_mer(stlink_t *sl, bool v, unsigned bank) { - uint32_t val, cr_reg, cr_mer, cr_pg; - - if (sl->flash_type == STLINK_FLASH_TYPE_F4) { - cr_reg = FLASH_F4_CR; - cr_mer = 1 << FLASH_CR_MER; - cr_pg = 1 << FLASH_CR_PG; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { - cr_reg = FLASH_F7_CR; - cr_mer = 1 << FLASH_CR_MER; - cr_pg = 1 << FLASH_CR_PG; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { - cr_reg = STM32L4_FLASH_CR; - cr_mer = (1 << STM32L4_FLASH_CR_MER1) | (1 << STM32L4_FLASH_CR_MER2); - cr_pg = (1 << STM32L4_FLASH_CR_PG); - } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { - cr_reg = STM32Gx_FLASH_CR; - cr_mer = (1 << STM32Gx_FLASH_CR_MER1); - - if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { - cr_mer |= (1 << STM32Gx_FLASH_CR_MER2); - } - - cr_pg = (1 << FLASH_CR_PG); - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { - cr_reg = STM32WB_FLASH_CR; - cr_mer = (1 << FLASH_CR_MER); - cr_pg = (1 << FLASH_CR_PG); - } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { - cr_reg = (bank==BANK_1)?FLASH_H7_CR1:FLASH_H7_CR2; - cr_mer = (1 << FLASH_H7_CR_BER); - cr_pg = (1 << FLASH_H7_CR_PG); - } else { - cr_reg = (bank==BANK_1)?FLASH_CR:FLASH_CR2; - cr_mer = (1 << FLASH_CR_MER); - cr_pg = (1 << FLASH_CR_PG); - } - - stlink_read_debug32(sl, cr_reg, &val); - - if (val & cr_pg) { - // STM32F030 will drop MER bit if PG was set - val &= ~cr_pg; - stlink_write_debug32(sl, cr_reg, val); - } + uint32_t val, cr_reg, cr_mer, cr_pg; + + if (sl->flash_type == STLINK_FLASH_TYPE_F4) { + cr_reg = FLASH_F4_CR; + cr_mer = 1 << FLASH_CR_MER; + cr_pg = 1 << FLASH_CR_PG; + } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { + cr_reg = FLASH_F7_CR; + cr_mer = 1 << FLASH_CR_MER; + cr_pg = 1 << FLASH_CR_PG; + } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { + cr_reg = STM32L4_FLASH_CR; + cr_mer = (1 << STM32L4_FLASH_CR_MER1) | (1 << STM32L4_FLASH_CR_MER2); + cr_pg = (1 << STM32L4_FLASH_CR_PG); + } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || + sl->flash_type == STLINK_FLASH_TYPE_G4) { + cr_reg = STM32Gx_FLASH_CR; + cr_mer = (1 << STM32Gx_FLASH_CR_MER1); + + if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { + cr_mer |= (1 << STM32Gx_FLASH_CR_MER2); + } + + cr_pg = (1 << FLASH_CR_PG); + } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + cr_reg = STM32WB_FLASH_CR; + cr_mer = (1 << FLASH_CR_MER); + cr_pg = (1 << FLASH_CR_PG); + } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + cr_reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; + cr_mer = (1 << FLASH_H7_CR_BER); + cr_pg = (1 << FLASH_H7_CR_PG); + } else { + cr_reg = (bank == BANK_1) ? FLASH_CR : FLASH_CR2; + cr_mer = (1 << FLASH_CR_MER); + cr_pg = (1 << FLASH_CR_PG); + } + + stlink_read_debug32(sl, cr_reg, &val); + + if (val & cr_pg) { + // STM32F030 will drop MER bit if PG was set + val &= ~cr_pg; + stlink_write_debug32(sl, cr_reg, val); + } - if (v) { - val |= cr_mer; - } else { - val &= ~cr_mer; - } + if (v) { + val |= cr_mer; + } else { + val &= ~cr_mer; + } - stlink_write_debug32(sl, cr_reg, val); + stlink_write_debug32(sl, cr_reg, val); } static void set_flash_cr_strt(stlink_t *sl, unsigned bank) { - uint32_t val, cr_reg, cr_strt; - - if (sl->flash_type == STLINK_FLASH_TYPE_F4) { - cr_reg = FLASH_F4_CR; - cr_strt = 1 << FLASH_F4_CR_STRT; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { - cr_reg = FLASH_F7_CR; - cr_strt = 1 << FLASH_F7_CR_STRT; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { - cr_reg = STM32L4_FLASH_CR; - cr_strt = (1 << STM32L4_FLASH_CR_STRT); - } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { - cr_reg = STM32Gx_FLASH_CR; - cr_strt = (1 << STM32Gx_FLASH_CR_STRT); - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { - cr_reg = STM32WB_FLASH_CR; - cr_strt = (1 << STM32WB_FLASH_CR_STRT); - } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { - cr_reg = (bank==BANK_1)?FLASH_H7_CR1:FLASH_H7_CR2; - cr_strt = 1 << FLASH_H7_CR_START(sl->chip_id); - } else { - cr_reg = (bank==BANK_1)?FLASH_CR:FLASH_CR2; - cr_strt = (1 << FLASH_CR_STRT); - } - - stlink_read_debug32(sl, cr_reg, &val); - val |= cr_strt; - stlink_write_debug32(sl, cr_reg, val); + uint32_t val, cr_reg, cr_strt; + + if (sl->flash_type == STLINK_FLASH_TYPE_F4) { + cr_reg = FLASH_F4_CR; + cr_strt = 1 << FLASH_F4_CR_STRT; + } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { + cr_reg = FLASH_F7_CR; + cr_strt = 1 << FLASH_F7_CR_STRT; + } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { + cr_reg = STM32L4_FLASH_CR; + cr_strt = (1 << STM32L4_FLASH_CR_STRT); + } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || + sl->flash_type == STLINK_FLASH_TYPE_G4) { + cr_reg = STM32Gx_FLASH_CR; + cr_strt = (1 << STM32Gx_FLASH_CR_STRT); + } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + cr_reg = STM32WB_FLASH_CR; + cr_strt = (1 << STM32WB_FLASH_CR_STRT); + } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + cr_reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; + cr_strt = 1 << FLASH_H7_CR_START(sl->chip_id); + } else { + cr_reg = (bank == BANK_1) ? FLASH_CR : FLASH_CR2; + cr_strt = (1 << FLASH_CR_STRT); + } + + stlink_read_debug32(sl, cr_reg, &val); + val |= cr_strt; + stlink_write_debug32(sl, cr_reg, val); } static inline uint32_t read_flash_sr(stlink_t *sl, unsigned bank) { - uint32_t res, sr_reg; - - if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || - (sl->flash_type == STLINK_FLASH_TYPE_F1_XL)) { - sr_reg = (bank==BANK_1)?FLASH_SR:FLASH_SR2; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { - sr_reg = get_stm32l0_flash_base(sl) + FLASH_SR_OFF; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F4) { - sr_reg = FLASH_F4_SR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { - sr_reg = FLASH_F7_SR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { - sr_reg = STM32L4_FLASH_SR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { - sr_reg = STM32Gx_FLASH_SR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { - sr_reg = STM32WB_FLASH_SR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { - sr_reg = (bank==BANK_1)?FLASH_H7_SR1:FLASH_H7_SR2; - } else { - ELOG("method 'read_flash_sr' is unsupported\n"); - return(-1); - } - - stlink_read_debug32(sl, sr_reg, &res); - return(res); + uint32_t res, sr_reg; + + if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || + (sl->flash_type == STLINK_FLASH_TYPE_F1_XL)) { + sr_reg = (bank == BANK_1) ? FLASH_SR : FLASH_SR2; + } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { + sr_reg = get_stm32l0_flash_base(sl) + FLASH_SR_OFF; + } else if (sl->flash_type == STLINK_FLASH_TYPE_F4) { + sr_reg = FLASH_F4_SR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { + sr_reg = FLASH_F7_SR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { + sr_reg = STM32L4_FLASH_SR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || + sl->flash_type == STLINK_FLASH_TYPE_G4) { + sr_reg = STM32Gx_FLASH_SR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + sr_reg = STM32WB_FLASH_SR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + sr_reg = (bank == BANK_1) ? FLASH_H7_SR1 : FLASH_H7_SR2; + } else { + ELOG("method 'read_flash_sr' is unsupported\n"); + return (-1); + } + + stlink_read_debug32(sl, sr_reg, &res); + return (res); } static inline int write_flash_sr(stlink_t *sl, unsigned bank, uint32_t val) { - uint32_t sr_reg; - - if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || - (sl->flash_type == STLINK_FLASH_TYPE_F1_XL)) { - sr_reg = (bank==BANK_1)?FLASH_SR:FLASH_SR2; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { - sr_reg = get_stm32l0_flash_base(sl) + FLASH_SR_OFF; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F4) { - sr_reg = FLASH_F4_SR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { - sr_reg = FLASH_F7_SR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { - sr_reg = STM32L4_FLASH_SR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { - sr_reg = STM32Gx_FLASH_SR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { - sr_reg = STM32WB_FLASH_SR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { - sr_reg = (bank==BANK_1)?FLASH_H7_SR1:FLASH_H7_SR2; - } else { - ELOG("method 'write_flash_sr' is unsupported\n"); - return(-1); - } - - return stlink_write_debug32(sl, sr_reg, val); + uint32_t sr_reg; + + if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || + (sl->flash_type == STLINK_FLASH_TYPE_F1_XL)) { + sr_reg = (bank == BANK_1) ? FLASH_SR : FLASH_SR2; + } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { + sr_reg = get_stm32l0_flash_base(sl) + FLASH_SR_OFF; + } else if (sl->flash_type == STLINK_FLASH_TYPE_F4) { + sr_reg = FLASH_F4_SR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { + sr_reg = FLASH_F7_SR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { + sr_reg = STM32L4_FLASH_SR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || + sl->flash_type == STLINK_FLASH_TYPE_G4) { + sr_reg = STM32Gx_FLASH_SR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + sr_reg = STM32WB_FLASH_SR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + sr_reg = (bank == BANK_1) ? FLASH_H7_SR1 : FLASH_H7_SR2; + } else { + ELOG("method 'write_flash_sr' is unsupported\n"); + return (-1); + } + + return stlink_write_debug32(sl, sr_reg, val); } static inline unsigned int is_flash_busy(stlink_t *sl) { - uint32_t sr_busy_shift; - unsigned int res; - - if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || - (sl->flash_type == STLINK_FLASH_TYPE_F1_XL) || - (sl->flash_type == STLINK_FLASH_TYPE_L0)) { - sr_busy_shift = FLASH_SR_BSY; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F4) { - sr_busy_shift = FLASH_F4_SR_BSY; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { - sr_busy_shift = FLASH_F7_SR_BSY; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { - sr_busy_shift = STM32L4_FLASH_SR_BSY; - } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { - sr_busy_shift = STM32Gx_FLASH_SR_BSY; - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { - sr_busy_shift = STM32WB_FLASH_SR_BSY; - } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { - sr_busy_shift = FLASH_H7_SR_QW; - } else { - ELOG("method 'is_flash_busy' is unsupported\n"); - return(-1); - } - - res = read_flash_sr(sl, BANK_1) & (1 << sr_busy_shift); - - if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL || - (sl->flash_type == STLINK_FLASH_TYPE_H7 && sl->chip_flags & CHIP_F_HAS_DUAL_BANK)) { - res |= read_flash_sr(sl, BANK_2) & (1 << sr_busy_shift); - } - - return(res); + uint32_t sr_busy_shift; + unsigned int res; + + if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || + (sl->flash_type == STLINK_FLASH_TYPE_F1_XL) || + (sl->flash_type == STLINK_FLASH_TYPE_L0)) { + sr_busy_shift = FLASH_SR_BSY; + } else if (sl->flash_type == STLINK_FLASH_TYPE_F4) { + sr_busy_shift = FLASH_F4_SR_BSY; + } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { + sr_busy_shift = FLASH_F7_SR_BSY; + } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { + sr_busy_shift = STM32L4_FLASH_SR_BSY; + } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || + sl->flash_type == STLINK_FLASH_TYPE_G4) { + sr_busy_shift = STM32Gx_FLASH_SR_BSY; + } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + sr_busy_shift = STM32WB_FLASH_SR_BSY; + } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + sr_busy_shift = FLASH_H7_SR_QW; + } else { + ELOG("method 'is_flash_busy' is unsupported\n"); + return (-1); + } + + res = read_flash_sr(sl, BANK_1) & (1 << sr_busy_shift); + + if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL || + (sl->flash_type == STLINK_FLASH_TYPE_H7 && + sl->chip_flags & CHIP_F_HAS_DUAL_BANK)) { + res |= read_flash_sr(sl, BANK_2) & (1 << sr_busy_shift); + } + + return (res); } static void wait_flash_busy(stlink_t *sl) { - // TODO: add some delays here - while (is_flash_busy(sl)) - ; + // TODO: add some delays here + while (is_flash_busy(sl)) + ; } static void wait_flash_busy_progress(stlink_t *sl) { - int i = 0; - fprintf(stdout, "Mass erasing"); - fflush(stdout); - - while (is_flash_busy(sl)) { - usleep(10000); - i++; - - if (i % 100 == 0) { - fprintf(stdout, "."); - fflush(stdout); - } - } - - fprintf(stdout, "\n"); -} - -static void clear_flash_error(stlink_t *sl) -{ - switch (sl->flash_type) { - case STLINK_FLASH_TYPE_F0: - write_flash_sr(sl, BANK_1, FLASH_SR_ERROR_MASK); - break; - case STLINK_FLASH_TYPE_F4: - write_flash_sr(sl, BANK_1, FLASH_F4_SR_ERROR_MASK); - break; - case STLINK_FLASH_TYPE_F7: - write_flash_sr(sl, BANK_1, FLASH_F7_SR_ERROR_MASK); - break; - case STLINK_FLASH_TYPE_G0: - case STLINK_FLASH_TYPE_G4: - write_flash_sr(sl, BANK_1, STM32Gx_FLASH_SR_ERROR_MASK); - break; - case STLINK_FLASH_TYPE_L0: - write_flash_sr(sl, BANK_1, STM32L0_FLASH_SR_ERROR_MASK); - break; - case STLINK_FLASH_TYPE_L4: - write_flash_sr(sl, BANK_1, STM32L4_FLASH_SR_ERROR_MASK); - break; - case STLINK_FLASH_TYPE_H7: - write_flash_sr(sl, BANK_1, FLASH_H7_SR_ERROR_MASK); - if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { - write_flash_sr(sl, BANK_2, FLASH_H7_SR_ERROR_MASK); - } - break; - case STLINK_FLASH_TYPE_WB: - write_flash_sr(sl, BANK_1, STM32WB_FLASH_SR_ERROR_MASK); - break; - default: - break; - } -} - -static int check_flash_error(stlink_t *sl) -{ - uint32_t res = 0; - uint32_t WRPERR, PROGERR, PGAERR; - - WRPERR = PROGERR = PGAERR = 0; - - switch (sl->flash_type) { - case STLINK_FLASH_TYPE_F0: - case STLINK_FLASH_TYPE_F1_XL: - res = read_flash_sr(sl, BANK_1) & FLASH_SR_ERROR_MASK; - if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL) { - res |= read_flash_sr(sl, BANK_2) & FLASH_SR_ERROR_MASK; - } - WRPERR = (1 << FLASH_SR_WRPRT_ERR); - PROGERR = (1 << FLASH_SR_PG_ERR); - break; - case STLINK_FLASH_TYPE_F4: - res = read_flash_sr(sl, BANK_1) & FLASH_F4_SR_ERROR_MASK; - WRPERR = (1 << FLASH_F4_SR_WRPERR); - PGAERR = (1 << FLASH_F4_SR_PGAERR); - break; - case STLINK_FLASH_TYPE_F7: - res = read_flash_sr(sl, BANK_1) & FLASH_F7_SR_ERROR_MASK; - WRPERR = (1 << FLASH_F7_SR_WRP_ERR); - PROGERR = (1 << FLASH_F7_SR_PGP_ERR); - break; - case STLINK_FLASH_TYPE_G0: - case STLINK_FLASH_TYPE_G4: - res = read_flash_sr(sl, BANK_1) & STM32Gx_FLASH_SR_ERROR_MASK; - WRPERR = (1 << STM32Gx_FLASH_SR_WRPERR); - PROGERR = (1 << STM32Gx_FLASH_SR_PROGERR); - PGAERR = (1 << STM32Gx_FLASH_SR_PGAERR); - break; - case STLINK_FLASH_TYPE_L0: - res = read_flash_sr(sl, BANK_1) & STM32L0_FLASH_SR_ERROR_MASK; - WRPERR = (1 << STM32L0_FLASH_SR_WRPERR); - PROGERR = (1 << STM32L0_FLASH_SR_NOTZEROERR); - PGAERR = (1 << STM32L0_FLASH_SR_PGAERR); - break; - case STLINK_FLASH_TYPE_L4: - res = read_flash_sr(sl, BANK_1) & STM32L4_FLASH_SR_ERROR_MASK; - WRPERR = (1 << STM32L4_FLASH_SR_WRPERR); - PROGERR = (1 << STM32L4_FLASH_SR_PROGERR); - PGAERR = (1 << STM32L4_FLASH_SR_PGAERR); - break; - case STLINK_FLASH_TYPE_H7: - res = read_flash_sr(sl, BANK_1) & FLASH_H7_SR_ERROR_MASK; - if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { - res |= read_flash_sr(sl, BANK_2) & FLASH_H7_SR_ERROR_MASK; - } - WRPERR = (1 << FLASH_H7_SR_WRPERR); - break; - case STLINK_FLASH_TYPE_WB: - res = read_flash_sr(sl, BANK_1) & STM32WB_FLASH_SR_ERROR_MASK; - WRPERR = (1 << STM32WB_FLASH_SR_WRPERR); - PROGERR = (1 << STM32WB_FLASH_SR_PROGERR); - PGAERR = (1 << STM32WB_FLASH_SR_PGAERR); - break; - default: - break; + int i = 0; + fprintf(stdout, "Mass erasing"); + fflush(stdout); + + while (is_flash_busy(sl)) { + usleep(10000); + i++; + + if (i % 100 == 0) { + fprintf(stdout, "."); + fflush(stdout); + } + } + + fprintf(stdout, "\n"); +} + +static void clear_flash_error(stlink_t *sl) { + switch (sl->flash_type) { + case STLINK_FLASH_TYPE_F0: + write_flash_sr(sl, BANK_1, FLASH_SR_ERROR_MASK); + break; + case STLINK_FLASH_TYPE_F4: + write_flash_sr(sl, BANK_1, FLASH_F4_SR_ERROR_MASK); + break; + case STLINK_FLASH_TYPE_F7: + write_flash_sr(sl, BANK_1, FLASH_F7_SR_ERROR_MASK); + break; + case STLINK_FLASH_TYPE_G0: + case STLINK_FLASH_TYPE_G4: + write_flash_sr(sl, BANK_1, STM32Gx_FLASH_SR_ERROR_MASK); + break; + case STLINK_FLASH_TYPE_L0: + write_flash_sr(sl, BANK_1, STM32L0_FLASH_SR_ERROR_MASK); + break; + case STLINK_FLASH_TYPE_L4: + write_flash_sr(sl, BANK_1, STM32L4_FLASH_SR_ERROR_MASK); + break; + case STLINK_FLASH_TYPE_H7: + write_flash_sr(sl, BANK_1, FLASH_H7_SR_ERROR_MASK); + if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { + write_flash_sr(sl, BANK_2, FLASH_H7_SR_ERROR_MASK); + } + break; + case STLINK_FLASH_TYPE_WB: + write_flash_sr(sl, BANK_1, STM32WB_FLASH_SR_ERROR_MASK); + break; + default: + break; + } +} + +static int check_flash_error(stlink_t *sl) { + uint32_t res = 0; + uint32_t WRPERR, PROGERR, PGAERR; + + WRPERR = PROGERR = PGAERR = 0; + + switch (sl->flash_type) { + case STLINK_FLASH_TYPE_F0: + case STLINK_FLASH_TYPE_F1_XL: + res = read_flash_sr(sl, BANK_1) & FLASH_SR_ERROR_MASK; + if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL) { + res |= read_flash_sr(sl, BANK_2) & FLASH_SR_ERROR_MASK; + } + WRPERR = (1 << FLASH_SR_WRPRT_ERR); + PROGERR = (1 << FLASH_SR_PG_ERR); + break; + case STLINK_FLASH_TYPE_F4: + res = read_flash_sr(sl, BANK_1) & FLASH_F4_SR_ERROR_MASK; + WRPERR = (1 << FLASH_F4_SR_WRPERR); + PGAERR = (1 << FLASH_F4_SR_PGAERR); + break; + case STLINK_FLASH_TYPE_F7: + res = read_flash_sr(sl, BANK_1) & FLASH_F7_SR_ERROR_MASK; + WRPERR = (1 << FLASH_F7_SR_WRP_ERR); + PROGERR = (1 << FLASH_F7_SR_PGP_ERR); + break; + case STLINK_FLASH_TYPE_G0: + case STLINK_FLASH_TYPE_G4: + res = read_flash_sr(sl, BANK_1) & STM32Gx_FLASH_SR_ERROR_MASK; + WRPERR = (1 << STM32Gx_FLASH_SR_WRPERR); + PROGERR = (1 << STM32Gx_FLASH_SR_PROGERR); + PGAERR = (1 << STM32Gx_FLASH_SR_PGAERR); + break; + case STLINK_FLASH_TYPE_L0: + res = read_flash_sr(sl, BANK_1) & STM32L0_FLASH_SR_ERROR_MASK; + WRPERR = (1 << STM32L0_FLASH_SR_WRPERR); + PROGERR = (1 << STM32L0_FLASH_SR_NOTZEROERR); + PGAERR = (1 << STM32L0_FLASH_SR_PGAERR); + break; + case STLINK_FLASH_TYPE_L4: + res = read_flash_sr(sl, BANK_1) & STM32L4_FLASH_SR_ERROR_MASK; + WRPERR = (1 << STM32L4_FLASH_SR_WRPERR); + PROGERR = (1 << STM32L4_FLASH_SR_PROGERR); + PGAERR = (1 << STM32L4_FLASH_SR_PGAERR); + break; + case STLINK_FLASH_TYPE_H7: + res = read_flash_sr(sl, BANK_1) & FLASH_H7_SR_ERROR_MASK; + if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { + res |= read_flash_sr(sl, BANK_2) & FLASH_H7_SR_ERROR_MASK; + } + WRPERR = (1 << FLASH_H7_SR_WRPERR); + break; + case STLINK_FLASH_TYPE_WB: + res = read_flash_sr(sl, BANK_1) & STM32WB_FLASH_SR_ERROR_MASK; + WRPERR = (1 << STM32WB_FLASH_SR_WRPERR); + PROGERR = (1 << STM32WB_FLASH_SR_PROGERR); + PGAERR = (1 << STM32WB_FLASH_SR_PGAERR); + break; + default: + break; + } + + if (res) { + if (WRPERR && (WRPERR & res) == WRPERR) { + ELOG("Flash memory is write protected\n"); + res &= ~WRPERR; + } else if (PROGERR && (PROGERR & res) == PROGERR) { + ELOG("Flash memory contains a non-erased value\n"); + res &= ~PROGERR; + } else if (PGAERR && (PGAERR & res) == PGAERR) { + ELOG("Invalid flash address\n"); + res &= ~PGAERR; } if (res) { - if (WRPERR && (WRPERR&res)==WRPERR) { - ELOG("Flash memory is write protected\n"); - res &= ~WRPERR; - } else if (PROGERR && (PROGERR&res)==PROGERR) { - ELOG("Flash memory contains a non-erased value\n"); - res &= ~PROGERR; - } else if (PGAERR && (PGAERR&res)==PGAERR) { - ELOG("Invalid flash address\n"); - res &= ~PGAERR; - } - - if (res) { - ELOG("Flash programming error: %#010x\n", res); - } - return(-1); + ELOG("Flash programming error: %#010x\n", res); } + return (-1); + } - return(0); + return (0); } static void stop_wdg_in_debug(stlink_t *sl) { - uint32_t dbgmcu_cr; - uint32_t set; - uint32_t value; - - switch (sl->flash_type) { - case STLINK_FLASH_TYPE_F0: - case STLINK_FLASH_TYPE_F1_XL: - case STLINK_FLASH_TYPE_G4: - dbgmcu_cr = STM32F0_DBGMCU_CR; - set = (1<flash_type) { - case STLINK_FLASH_TYPE_F0: - case STLINK_FLASH_TYPE_F1_XL: - rcc = STM32F1_RCC_AHBENR; - rcc_dma_mask = STM32F1_RCC_DMAEN; - break; - case STLINK_FLASH_TYPE_F4: - case STLINK_FLASH_TYPE_F7: - rcc = STM32F4_RCC_AHB1ENR; - rcc_dma_mask = STM32F4_RCC_DMAEN; - break; - case STLINK_FLASH_TYPE_G0: - rcc = STM32G0_RCC_AHBENR; - rcc_dma_mask = STM32G0_RCC_DMAEN; - break; - case STLINK_FLASH_TYPE_G4: - case STLINK_FLASH_TYPE_L4: - rcc = STM32G4_RCC_AHB1ENR; - rcc_dma_mask = STM32G4_RCC_DMAEN; - break; - case STLINK_FLASH_TYPE_L0: - rcc = STM32L0_RCC_AHBENR; - rcc_dma_mask = STM32L0_RCC_DMAEN; - break; - case STLINK_FLASH_TYPE_H7: - rcc = STM32H7_RCC_AHB1ENR; - rcc_dma_mask = STM32H7_RCC_DMAEN; - break; - case STLINK_FLASH_TYPE_WB: - rcc = STM32WB_RCC_AHB1ENR; - rcc_dma_mask = STM32WB_RCC_DMAEN; - break; - default: - return; - } + uint32_t dbgmcu_cr; + uint32_t set; + uint32_t value; + + switch (sl->flash_type) { + case STLINK_FLASH_TYPE_F0: + case STLINK_FLASH_TYPE_F1_XL: + case STLINK_FLASH_TYPE_G4: + dbgmcu_cr = STM32F0_DBGMCU_CR; + set = + (1 << STM32F0_DBGMCU_CR_IWDG_STOP) | (1 << STM32F0_DBGMCU_CR_WWDG_STOP); + break; + case STLINK_FLASH_TYPE_F4: + case STLINK_FLASH_TYPE_F7: + case STLINK_FLASH_TYPE_L4: + dbgmcu_cr = STM32F4_DBGMCU_APB1FZR1; + set = (1 << STM32F4_DBGMCU_APB1FZR1_IWDG_STOP) | + (1 << STM32F4_DBGMCU_APB1FZR1_WWDG_STOP); + break; + case STLINK_FLASH_TYPE_L0: + case STLINK_FLASH_TYPE_G0: + dbgmcu_cr = STM32L0_DBGMCU_APB1_FZ; + set = (1 << STM32L0_DBGMCU_APB1_FZ_IWDG_STOP) | + (1 << STM32L0_DBGMCU_APB1_FZ_WWDG_STOP); + break; + case STLINK_FLASH_TYPE_H7: + dbgmcu_cr = STM32H7_DBGMCU_APB1HFZ; + set = (1 << STM32H7_DBGMCU_APB1HFZ_IWDG_STOP); + break; + case STLINK_FLASH_TYPE_WB: + dbgmcu_cr = STM32WB_DBGMCU_APB1FZR1; + set = (1 << STM32WB_DBGMCU_APB1FZR1_IWDG_STOP) | + (1 << STM32WB_DBGMCU_APB1FZR1_WWDG_STOP); + break; + default: + return; + } + + if (!stlink_read_debug32(sl, dbgmcu_cr, &value)) { + stlink_write_debug32(sl, dbgmcu_cr, value | set); + } +} + +static void set_dma_state(stlink_t *sl, flash_loader_t *fl, int bckpRstr) { + uint32_t rcc, rcc_dma_mask, value; + + rcc = rcc_dma_mask = value = 0; + + switch (sl->flash_type) { + case STLINK_FLASH_TYPE_F0: + case STLINK_FLASH_TYPE_F1_XL: + rcc = STM32F1_RCC_AHBENR; + rcc_dma_mask = STM32F1_RCC_DMAEN; + break; + case STLINK_FLASH_TYPE_F4: + case STLINK_FLASH_TYPE_F7: + rcc = STM32F4_RCC_AHB1ENR; + rcc_dma_mask = STM32F4_RCC_DMAEN; + break; + case STLINK_FLASH_TYPE_G0: + rcc = STM32G0_RCC_AHBENR; + rcc_dma_mask = STM32G0_RCC_DMAEN; + break; + case STLINK_FLASH_TYPE_G4: + case STLINK_FLASH_TYPE_L4: + rcc = STM32G4_RCC_AHB1ENR; + rcc_dma_mask = STM32G4_RCC_DMAEN; + break; + case STLINK_FLASH_TYPE_L0: + rcc = STM32L0_RCC_AHBENR; + rcc_dma_mask = STM32L0_RCC_DMAEN; + break; + case STLINK_FLASH_TYPE_H7: + rcc = STM32H7_RCC_AHB1ENR; + rcc_dma_mask = STM32H7_RCC_DMAEN; + break; + case STLINK_FLASH_TYPE_WB: + rcc = STM32WB_RCC_AHB1ENR; + rcc_dma_mask = STM32WB_RCC_DMAEN; + break; + default: + return; + } - if (!stlink_read_debug32(sl, rcc, &value)) { - if (bckpRstr) { - value = (value&(~rcc_dma_mask)) | fl->rcc_dma_bkp; - } else { - fl->rcc_dma_bkp = value&rcc_dma_mask; - value &= ~rcc_dma_mask; - } - stlink_write_debug32(sl, rcc, value); + if (!stlink_read_debug32(sl, rcc, &value)) { + if (bckpRstr) { + value = (value & (~rcc_dma_mask)) | fl->rcc_dma_bkp; + } else { + fl->rcc_dma_bkp = value & rcc_dma_mask; + value &= ~rcc_dma_mask; } + stlink_write_debug32(sl, rcc, value); + } } static inline void write_flash_ar(stlink_t *sl, uint32_t n, unsigned bank) { - stlink_write_debug32(sl, (bank==BANK_1)?FLASH_AR:FLASH_AR2, n); + stlink_write_debug32(sl, (bank == BANK_1) ? FLASH_AR : FLASH_AR2, n); } -static inline void write_flash_cr_psiz(stlink_t *sl, uint32_t n, unsigned bank) { - uint32_t cr_reg, psize_shift; - uint32_t x = read_flash_cr(sl, bank); +static inline void write_flash_cr_psiz(stlink_t *sl, uint32_t n, + unsigned bank) { + uint32_t cr_reg, psize_shift; + uint32_t x = read_flash_cr(sl, bank); - if (sl->flash_type == STLINK_FLASH_TYPE_H7) { - cr_reg = (bank==BANK_1)?FLASH_H7_CR1:FLASH_H7_CR2; - psize_shift = FLASH_H7_CR_PSIZE; - } else { - cr_reg = FLASH_F4_CR; - psize_shift = 8; - } + if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + cr_reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; + psize_shift = FLASH_H7_CR_PSIZE; + } else { + cr_reg = FLASH_F4_CR; + psize_shift = 8; + } - x &= ~(0x03 << psize_shift); - x |= (n << psize_shift); + x &= ~(0x03 << psize_shift); + x |= (n << psize_shift); #if DEBUG_FLASH - fprintf(stdout, "PSIZ:0x%x 0x%x\n", x, n); + fprintf(stdout, "PSIZ:0x%x 0x%x\n", x, n); #endif - stlink_write_debug32(sl, cr_reg, x); + stlink_write_debug32(sl, cr_reg, x); } static inline void write_flash_cr_snb(stlink_t *sl, uint32_t n, unsigned bank) { - uint32_t cr_reg, snb_mask, snb_shift, ser_shift; - uint32_t x = read_flash_cr(sl, bank); - - if (sl->flash_type == STLINK_FLASH_TYPE_H7) { - cr_reg = (bank==BANK_1)?FLASH_H7_CR1:FLASH_H7_CR2; - snb_mask = FLASH_H7_CR_SNB_MASK; - snb_shift = FLASH_H7_CR_SNB; - ser_shift = FLASH_H7_CR_SER; - } else { - cr_reg = FLASH_F4_CR; - snb_mask = FLASH_F4_CR_SNB_MASK; - snb_shift = FLASH_F4_CR_SNB; - ser_shift = FLASH_F4_CR_SER; - } - - x &= ~snb_mask; - x |= (n << snb_shift); - x |= (1 << ser_shift); + uint32_t cr_reg, snb_mask, snb_shift, ser_shift; + uint32_t x = read_flash_cr(sl, bank); + + if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + cr_reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; + snb_mask = FLASH_H7_CR_SNB_MASK; + snb_shift = FLASH_H7_CR_SNB; + ser_shift = FLASH_H7_CR_SER; + } else { + cr_reg = FLASH_F4_CR; + snb_mask = FLASH_F4_CR_SNB_MASK; + snb_shift = FLASH_F4_CR_SNB; + ser_shift = FLASH_F4_CR_SER; + } + + x &= ~snb_mask; + x |= (n << snb_shift); + x |= (1 << ser_shift); #if DEBUG_FLASH - fprintf(stdout, "SNB:0x%x 0x%x\n", x, n); + fprintf(stdout, "SNB:0x%x 0x%x\n", x, n); #endif - stlink_write_debug32(sl, cr_reg, x); + stlink_write_debug32(sl, cr_reg, x); } static inline void write_flash_cr_bker_pnb(stlink_t *sl, uint32_t n) { - stlink_write_debug32(sl, STM32L4_FLASH_SR, 0xFFFFFFFF & ~(1 << STM32L4_FLASH_SR_BSY)); - uint32_t x = read_flash_cr(sl, BANK_1); - x &= ~STM32L4_FLASH_CR_OPBITS; - x &= ~STM32L4_FLASH_CR_PAGEMASK; - x &= ~(1 << STM32L4_FLASH_CR_MER1); - x &= ~(1 << STM32L4_FLASH_CR_MER2); - x |= (n << STM32L4_FLASH_CR_PNB); - x |= (uint32_t)(1lu << STM32L4_FLASH_CR_PER); + stlink_write_debug32(sl, STM32L4_FLASH_SR, + 0xFFFFFFFF & ~(1 << STM32L4_FLASH_SR_BSY)); + uint32_t x = read_flash_cr(sl, BANK_1); + x &= ~STM32L4_FLASH_CR_OPBITS; + x &= ~STM32L4_FLASH_CR_PAGEMASK; + x &= ~(1 << STM32L4_FLASH_CR_MER1); + x &= ~(1 << STM32L4_FLASH_CR_MER2); + x |= (n << STM32L4_FLASH_CR_PNB); + x |= (uint32_t)(1lu << STM32L4_FLASH_CR_PER); #if DEBUG_FLASH - fprintf(stdout, "BKER:PNB:0x%x 0x%x\n", x, n); + fprintf(stdout, "BKER:PNB:0x%x 0x%x\n", x, n); #endif - stlink_write_debug32(sl, STM32L4_FLASH_CR, x); + stlink_write_debug32(sl, STM32L4_FLASH_CR, x); } // Delegates to the backends... void stlink_close(stlink_t *sl) { - DLOG("*** stlink_close ***\n"); + DLOG("*** stlink_close ***\n"); - if (!sl) { - return; - } + if (!sl) { + return; + } - sl->backend->close(sl); - free(sl); + sl->backend->close(sl); + free(sl); } int stlink_exit_debug_mode(stlink_t *sl) { - int ret; + int ret; - DLOG("*** stlink_exit_debug_mode ***\n"); - ret = stlink_write_debug32(sl, STLINK_REG_DHCSR, STLINK_REG_DHCSR_DBGKEY); + DLOG("*** stlink_exit_debug_mode ***\n"); + ret = stlink_write_debug32(sl, STLINK_REG_DHCSR, STLINK_REG_DHCSR_DBGKEY); - if (ret == -1) { - return(ret); - } + if (ret == -1) { + return (ret); + } - return(sl->backend->exit_debug_mode(sl)); + return (sl->backend->exit_debug_mode(sl)); } int stlink_enter_swd_mode(stlink_t *sl) { - DLOG("*** stlink_enter_swd_mode ***\n"); - return(sl->backend->enter_swd_mode(sl)); + DLOG("*** stlink_enter_swd_mode ***\n"); + return (sl->backend->enter_swd_mode(sl)); } // Force the core into the debug mode -> halted state. int stlink_force_debug(stlink_t *sl) { - DLOG("*** stlink_force_debug_mode ***\n"); - int res = sl->backend->force_debug(sl); - // Stop the watchdogs in the halted state for suppress target reboot - stop_wdg_in_debug(sl); - return(res); + DLOG("*** stlink_force_debug_mode ***\n"); + int res = sl->backend->force_debug(sl); + // Stop the watchdogs in the halted state for suppress target reboot + stop_wdg_in_debug(sl); + return (res); } int stlink_exit_dfu_mode(stlink_t *sl) { - DLOG("*** stlink_exit_dfu_mode ***\n"); - return(sl->backend->exit_dfu_mode(sl)); + DLOG("*** stlink_exit_dfu_mode ***\n"); + return (sl->backend->exit_dfu_mode(sl)); } int stlink_core_id(stlink_t *sl) { - int ret; + int ret; - DLOG("*** stlink_core_id ***\n"); - ret = sl->backend->core_id(sl); + DLOG("*** stlink_core_id ***\n"); + ret = sl->backend->core_id(sl); - if (ret == -1) { - ELOG("Failed to read core_id\n"); - return(ret); - } + if (ret == -1) { + ELOG("Failed to read core_id\n"); + return (ret); + } - if (sl->verbose > 2) { - stlink_print_data(sl); - } + if (sl->verbose > 2) { + stlink_print_data(sl); + } - DLOG("core_id = 0x%08x\n", sl->core_id); - return(ret); + DLOG("core_id = 0x%08x\n", sl->core_id); + return (ret); } // stlink_chip_id() is called by stlink_load_device_params() // do not call this procedure directly. int stlink_chip_id(stlink_t *sl, uint32_t *chip_id) { - int ret; - cortex_m3_cpuid_t cpu_id; - - // Read the CPU ID to determine where to read the core id - if (stlink_cpu_id(sl, &cpu_id) || - cpu_id.implementer_id != STLINK_REG_CMx_CPUID_IMPL_ARM) { - ELOG("Can not connect to target. Please use \'connect under reset\' and try again\n"); - return -1; - } - - /* - * the chip_id register in the reference manual have - * DBGMCU_IDCODE / DBG_IDCODE name - * - */ - - if ((sl->core_id == STM32H7_CORE_ID || - sl->core_id == STM32H7_CORE_ID_JTAG) && - cpu_id.part == STLINK_REG_CMx_CPUID_PARTNO_CM7) { - // STM32H7 chipid in 0x5c001000 (RM0433 pg3189) - ret = stlink_read_debug32(sl, 0x5c001000, chip_id); - } else if (cpu_id.part == STLINK_REG_CMx_CPUID_PARTNO_CM0 || - cpu_id.part == STLINK_REG_CMx_CPUID_PARTNO_CM0P) { - // STM32F0 (RM0091, pg914; RM0360, pg713) - // STM32L0 (RM0377, pg813; RM0367, pg915; RM0376, pg917) - // STM32G0 (RM0444, pg1367) - ret = stlink_read_debug32(sl, 0x40015800, chip_id); - } else if (cpu_id.part == STLINK_REG_CMx_CPUID_PARTNO_CM33) { - // STM32L5 (RM0438, pg2157) - ret = stlink_read_debug32(sl, 0xE0044000, chip_id); - } else /* СM3, СM4, CM7 */ { - // default chipid address - - // STM32F1 (RM0008, pg1087; RM0041, pg681) - // STM32F2 (RM0033, pg1326) - // STM32F3 (RM0316, pg1095; RM0313, pg874) - // STM32F7 (RM0385, pg1676; RM0410, pg1912) - // STM32L1 (RM0038, pg861) - // STM32L4 (RM0351, pg1840; RM0394, pg1560) - // STM32G4 (RM0440, pg2086) - // STM32WB (RM0434, pg1406) - ret = stlink_read_debug32(sl, 0xE0042000, chip_id); - } - - if (ret || !(*chip_id)) { - *chip_id = 0; - ELOG("Could not find chip id!\n"); - } else { - *chip_id = (*chip_id) & 0xfff; - - // Fix chip_id for F4 rev A errata, read CPU ID, as CoreID is the same for F2/F4 - if (*chip_id == 0x411 && cpu_id.part == STLINK_REG_CMx_CPUID_PARTNO_CM4) { - *chip_id = 0x413; - } - } - - return(ret); + int ret; + cortex_m3_cpuid_t cpu_id; + + // Read the CPU ID to determine where to read the core id + if (stlink_cpu_id(sl, &cpu_id) || + cpu_id.implementer_id != STLINK_REG_CMx_CPUID_IMPL_ARM) { + ELOG("Can not connect to target. Please use \'connect under reset\' and " + "try again\n"); + return -1; + } + + /* + * the chip_id register in the reference manual have + * DBGMCU_IDCODE / DBG_IDCODE name + * + */ + + if ((sl->core_id == STM32H7_CORE_ID || sl->core_id == STM32H7_CORE_ID_JTAG) && + cpu_id.part == STLINK_REG_CMx_CPUID_PARTNO_CM7) { + // STM32H7 chipid in 0x5c001000 (RM0433 pg3189) + ret = stlink_read_debug32(sl, 0x5c001000, chip_id); + } else if (cpu_id.part == STLINK_REG_CMx_CPUID_PARTNO_CM0 || + cpu_id.part == STLINK_REG_CMx_CPUID_PARTNO_CM0P) { + // STM32F0 (RM0091, pg914; RM0360, pg713) + // STM32L0 (RM0377, pg813; RM0367, pg915; RM0376, pg917) + // STM32G0 (RM0444, pg1367) + ret = stlink_read_debug32(sl, 0x40015800, chip_id); + } else if (cpu_id.part == STLINK_REG_CMx_CPUID_PARTNO_CM33) { + // STM32L5 (RM0438, pg2157) + ret = stlink_read_debug32(sl, 0xE0044000, chip_id); + } else /* СM3, СM4, CM7 */ { + // default chipid address + + // STM32F1 (RM0008, pg1087; RM0041, pg681) + // STM32F2 (RM0033, pg1326) + // STM32F3 (RM0316, pg1095; RM0313, pg874) + // STM32F7 (RM0385, pg1676; RM0410, pg1912) + // STM32L1 (RM0038, pg861) + // STM32L4 (RM0351, pg1840; RM0394, pg1560) + // STM32G4 (RM0440, pg2086) + // STM32WB (RM0434, pg1406) + ret = stlink_read_debug32(sl, 0xE0042000, chip_id); + } + + if (ret || !(*chip_id)) { + *chip_id = 0; + ELOG("Could not find chip id!\n"); + } else { + *chip_id = (*chip_id) & 0xfff; + + // Fix chip_id for F4 rev A errata, read CPU ID, as CoreID is the same for + // F2/F4 + if (*chip_id == 0x411 && cpu_id.part == STLINK_REG_CMx_CPUID_PARTNO_CM4) { + *chip_id = 0x413; + } + } + + return (ret); } /** @@ -1553,21 +1558,21 @@ int stlink_chip_id(stlink_t *sl, uint32_t *chip_id) { * @param cpuid pointer to the result object */ int stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid) { - uint32_t raw; - - if (stlink_read_debug32(sl, STLINK_REG_CM3_CPUID, &raw)) { - cpuid->implementer_id = 0; - cpuid->variant = 0; - cpuid->part = 0; - cpuid->revision = 0; - return(-1); - } + uint32_t raw; - cpuid->implementer_id = (raw >> 24) & 0x7f; - cpuid->variant = (raw >> 20) & 0xf; - cpuid->part = (raw >> 4) & 0xfff; - cpuid->revision = raw & 0xf; - return(0); + if (stlink_read_debug32(sl, STLINK_REG_CM3_CPUID, &raw)) { + cpuid->implementer_id = 0; + cpuid->variant = 0; + cpuid->part = 0; + cpuid->revision = 0; + return (-1); + } + + cpuid->implementer_id = (raw >> 24) & 0x7f; + cpuid->variant = (raw >> 20) & 0xf; + cpuid->part = (raw >> 4) & 0xfff; + cpuid->revision = raw & 0xf; + return (0); } /** @@ -1576,256 +1581,269 @@ int stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid) { * @return 0 for success, or -1 for unsupported core type. */ int stlink_load_device_params(stlink_t *sl) { - // This seems to normally work so is unnecessary info for a normal user. - // Demoted to debug. -- REW - DLOG("Loading device parameters....\n"); - const struct stlink_chipid_params *params = NULL; - stlink_core_id(sl); - uint32_t flash_size; - - if (stlink_chip_id(sl, &sl->chip_id)) { - return(-1); - } + // This seems to normally work so is unnecessary info for a normal user. + // Demoted to debug. -- REW + DLOG("Loading device parameters....\n"); + const struct stlink_chipid_params *params = NULL; + stlink_core_id(sl); + uint32_t flash_size; + + if (stlink_chip_id(sl, &sl->chip_id)) { + return (-1); + } + + params = stlink_chipid_get_params(sl->chip_id); + + if (params == NULL) { + WLOG("unknown chip id! %#x\n", sl->chip_id); + return (-1); + } + + if (params->flash_type == STLINK_FLASH_TYPE_UNKNOWN) { + WLOG("Invalid flash type, please check device declaration\n"); + sl->flash_size = 0; + return (0); + } + + // These are fixed... + sl->flash_base = STM32_FLASH_BASE; + sl->sram_base = STM32_SRAM_BASE; + stlink_read_debug32(sl, (params->flash_size_reg) & ~3, &flash_size); + + if (params->flash_size_reg & 2) { + flash_size = flash_size >> 16; + } + + flash_size = flash_size & 0xffff; + + if ((sl->chip_id == STLINK_CHIPID_STM32_L1_MEDIUM || + sl->chip_id == STLINK_CHIPID_STM32_F1_VL_MEDIUM_LOW || + sl->chip_id == STLINK_CHIPID_STM32_L1_MEDIUM_PLUS) && + (flash_size == 0)) { + sl->flash_size = 128 * 1024; + } else if (sl->chip_id == STLINK_CHIPID_STM32_L1_CAT2) { + sl->flash_size = (flash_size & 0xff) * 1024; + } else if ((sl->chip_id & 0xFFF) == STLINK_CHIPID_STM32_L1_HIGH) { + // 0 is 384k and 1 is 256k + if (flash_size == 0) { + sl->flash_size = 384 * 1024; + } else { + sl->flash_size = 256 * 1024; + } + } else { + sl->flash_size = flash_size * 1024; + } + + sl->flash_type = params->flash_type; + sl->flash_pgsz = params->flash_pagesize; + sl->sram_size = params->sram_size; + sl->sys_base = params->bootrom_base; + sl->sys_size = params->bootrom_size; + sl->option_base = params->option_base; + sl->option_size = params->option_size; + sl->chip_flags = params->flags; + + // medium and low devices have the same chipid. ram size depends on flash + // size. STM32F100xx datasheet Doc ID 16455 Table 2 + if (sl->chip_id == STLINK_CHIPID_STM32_F1_VL_MEDIUM_LOW && + sl->flash_size < 64 * 1024) { + sl->sram_size = 0x1000; + } + + if (sl->chip_id == STLINK_CHIPID_STM32_G4_CAT3) { + uint32_t flash_optr; + stlink_read_debug32(sl, STM32Gx_FLASH_OPTR, &flash_optr); + + if (!(flash_optr & (1 << STM32G4_FLASH_OPTR_DBANK))) { + sl->flash_pgsz <<= 1; + } + } + + // H7 devices with small flash has one bank + if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK && + sl->flash_type == STLINK_FLASH_TYPE_H7) { + if ((flash_size / sl->flash_pgsz) <= 1) + sl->chip_flags &= ~CHIP_F_HAS_DUAL_BANK; + } + + ILOG("%s: %u KiB SRAM, %u KiB flash in at least %u %s pages.\n", + params->description, (unsigned)(sl->sram_size / 1024), + (unsigned)(sl->flash_size / 1024), + (sl->flash_pgsz < 1024) ? (unsigned)(sl->flash_pgsz) + : (unsigned)(sl->flash_pgsz / 1024), + (sl->flash_pgsz < 1024) ? "byte" : "KiB"); + + return (0); +} - params = stlink_chipid_get_params(sl->chip_id); +int stlink_jtag_reset(stlink_t *sl, int value) { + DLOG("*** stlink_jtag_reset ***\n"); + return (sl->backend->jtag_reset(sl, value)); +} - if (params == NULL) { - WLOG("unknown chip id! %#x\n", sl->chip_id); - return(-1); +int stlink_soft_reset(stlink_t *sl, int halt_on_reset) { + int ret; + unsigned timeout; + uint32_t dhcsr, dfsr; + + DLOG("*** stlink_soft_reset %s***\n", halt_on_reset ? "(halt) " : ""); + + // halt core and enable debugging (if not already done) + // C_DEBUGEN is required to Halt on reset (DDI0337E, p. 10-6) + stlink_write_debug32(sl, STLINK_REG_DHCSR, + STLINK_REG_DHCSR_DBGKEY | STLINK_REG_DHCSR_C_HALT | + STLINK_REG_DHCSR_C_DEBUGEN); + + // enable Halt on reset by set VC_CORERESET and TRCENA (DDI0337E, p. 10-10) + if (halt_on_reset) { + stlink_write_debug32( + sl, STLINK_REG_CM3_DEMCR, + STLINK_REG_CM3_DEMCR_TRCENA | STLINK_REG_CM3_DEMCR_VC_HARDERR | + STLINK_REG_CM3_DEMCR_VC_BUSERR | STLINK_REG_CM3_DEMCR_VC_CORERESET); + + // clear VCATCH in the DFSR register + stlink_write_debug32(sl, STLINK_REG_DFSR, STLINK_REG_DFSR_VCATCH); + } else { + stlink_write_debug32(sl, STLINK_REG_CM3_DEMCR, + STLINK_REG_CM3_DEMCR_TRCENA | + STLINK_REG_CM3_DEMCR_VC_HARDERR | + STLINK_REG_CM3_DEMCR_VC_BUSERR); + } + + // clear S_RESET_ST in the DHCSR register + stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); + + // soft reset (core reset) by SYSRESETREQ (DDI0337E, p. 8-23) + ret = stlink_write_debug32(sl, STLINK_REG_AIRCR, + STLINK_REG_AIRCR_VECTKEY | + STLINK_REG_AIRCR_SYSRESETREQ); + if (ret) { + ELOG("Soft reset failed: error write to AIRCR\n"); + return (ret); + } + + // waiting for a reset within 500ms + // DDI0337E, p. 10-4, Debug Halting Control and Status Register + timeout = time_ms() + 500; + while (time_ms() < timeout) { + // DDI0337E, p. 10-4, Debug Halting Control and Status Register + dhcsr = STLINK_REG_DHCSR_S_RESET_ST; + stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); + if ((dhcsr & STLINK_REG_DHCSR_S_RESET_ST) == 0) { + if (halt_on_reset) { + // waiting halt by the SYSRESETREQ exception + // DDI0403E, p. C1-699, Debug Fault Status Register + dfsr = 0; + stlink_read_debug32(sl, STLINK_REG_DFSR, &dfsr); + if ((dfsr & STLINK_REG_DFSR_VCATCH) == 0) { + continue; + } + } + timeout = 0; + break; } + } - if (params->flash_type == STLINK_FLASH_TYPE_UNKNOWN) { - WLOG("Invalid flash type, please check device declaration\n"); - sl->flash_size = 0; - return(0); - } + // reset DFSR register. DFSR is power-on reset only (DDI0337H, p. 7-5) + stlink_write_debug32(sl, STLINK_REG_DFSR, STLINK_REG_DFSR_CLEAR); - // These are fixed... - sl->flash_base = STM32_FLASH_BASE; - sl->sram_base = STM32_SRAM_BASE; - stlink_read_debug32(sl, (params->flash_size_reg) & ~3, &flash_size); + if (timeout) { + ELOG("Soft reset failed: timeout\n"); + return (-1); + } - if (params->flash_size_reg & 2) { - flash_size = flash_size >> 16; - } + return (0); +} - flash_size = flash_size & 0xffff; - - if ((sl->chip_id == STLINK_CHIPID_STM32_L1_MEDIUM || - sl->chip_id == STLINK_CHIPID_STM32_F1_VL_MEDIUM_LOW || - sl->chip_id == STLINK_CHIPID_STM32_L1_MEDIUM_PLUS) && (flash_size == 0)) { - sl->flash_size = 128 * 1024; - } else if (sl->chip_id == STLINK_CHIPID_STM32_L1_CAT2) { - sl->flash_size = (flash_size & 0xff) * 1024; - } else if ((sl->chip_id & 0xFFF) == STLINK_CHIPID_STM32_L1_HIGH) { - // 0 is 384k and 1 is 256k - if (flash_size == 0) { - sl->flash_size = 384 * 1024; - } else { - sl->flash_size = 256 * 1024; - } - } else { - sl->flash_size = flash_size * 1024; - } +int stlink_reset(stlink_t *sl, enum reset_type type) { + uint32_t dhcsr; + unsigned timeout; + + DLOG("*** stlink_reset ***\n"); + + if (type == RESET_AUTO) { + // clear S_RESET_ST in DHCSR register for reset state detection + stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); + } - sl->flash_type = params->flash_type; - sl->flash_pgsz = params->flash_pagesize; - sl->sram_size = params->sram_size; - sl->sys_base = params->bootrom_base; - sl->sys_size = params->bootrom_size; - sl->option_base = params->option_base; - sl->option_size = params->option_size; - sl->chip_flags = params->flags; - - // medium and low devices have the same chipid. ram size depends on flash size. - // STM32F100xx datasheet Doc ID 16455 Table 2 - if (sl->chip_id == STLINK_CHIPID_STM32_F1_VL_MEDIUM_LOW && sl->flash_size < 64 * 1024) { - sl->sram_size = 0x1000; + if (type == RESET_HARD || type == RESET_AUTO) { + // hardware target reset + if (sl->version.stlink_v > 1) { + stlink_jtag_reset(sl, STLINK_JTAG_DRIVE_NRST_LOW); + // minimum reset pulse duration of 20 us (RM0008, 8.1.2 Power reset) + usleep(100); + stlink_jtag_reset(sl, STLINK_JTAG_DRIVE_NRST_HIGH); + } + if (sl->backend->reset(sl)) { + return (-1); } + usleep(10000); + } - if (sl->chip_id == STLINK_CHIPID_STM32_G4_CAT3) { - uint32_t flash_optr; - stlink_read_debug32(sl, STM32Gx_FLASH_OPTR, &flash_optr); + if (type == RESET_AUTO) { + /* Check if the S_RESET_ST bit is set in DHCSR + * This means that a reset has occurred + * DDI0337E, p. 10-4, Debug Halting Control and Status Register */ + + dhcsr = 0; + stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); + if ((dhcsr & STLINK_REG_DHCSR_S_RESET_ST) == 0) { + // reset not done yet + // try reset through AIRCR so that NRST does not need to be connected - if (!(flash_optr & (1 << STM32G4_FLASH_OPTR_DBANK))) { sl->flash_pgsz <<= 1; } + WLOG("NRST is not connected\n"); + DLOG("Using reset through SYSRESETREQ\n"); + return stlink_soft_reset(sl, 0); } - // H7 devices with small flash has one bank - if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK && sl->flash_type == STLINK_FLASH_TYPE_H7) { - if ((flash_size/sl->flash_pgsz) <= 1) - sl->chip_flags &= ~CHIP_F_HAS_DUAL_BANK; + // waiting for reset the S_RESET_ST bit within 500ms + timeout = time_ms() + 500; + while (time_ms() < timeout) { + dhcsr = STLINK_REG_DHCSR_S_RESET_ST; + stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); + if ((dhcsr & STLINK_REG_DHCSR_S_RESET_ST) == 0) + return (0); } - ILOG("%s: %u KiB SRAM, %u KiB flash in at least %u %s pages.\n", - params->description, (unsigned)(sl->sram_size / 1024), (unsigned)(sl->flash_size / 1024), - (sl->flash_pgsz < 1024) ? (unsigned)(sl->flash_pgsz) : (unsigned)(sl->flash_pgsz / 1024), - (sl->flash_pgsz < 1024) ? "byte" : "KiB"); + return (-1); + } - return(0); + if (type == RESET_SOFT || type == RESET_SOFT_AND_HALT) { + return stlink_soft_reset(sl, (type == RESET_SOFT_AND_HALT)); + } + + return (0); } +int stlink_run(stlink_t *sl, enum run_type type) { + struct stlink_reg rr; + DLOG("*** stlink_run ***\n"); + + /* Make sure we are in Thumb mode + * Cortex-M chips don't support ARM mode instructions + * xPSR may be incorrect if the vector table has invalid data */ + stlink_read_reg(sl, 16, &rr); + if ((rr.xpsr & (1 << 24)) == 0) { + ILOG("Go to Thumb mode\n"); + stlink_write_reg(sl, rr.xpsr | (1 << 24), 16); + } -int stlink_jtag_reset(stlink_t *sl, int value) { - DLOG("*** stlink_jtag_reset ***\n"); - return(sl->backend->jtag_reset(sl, value)); + return (sl->backend->run(sl, type)); } -int stlink_soft_reset(stlink_t *sl, int halt_on_reset) { - int ret; - unsigned timeout; - uint32_t dhcsr, dfsr; - - DLOG("*** stlink_soft_reset %s***\n", halt_on_reset?"(halt) ":""); +int stlink_set_swdclk(stlink_t *sl, int freq_khz) { + DLOG("*** set_swdclk ***\n"); + return (sl->backend->set_swdclk(sl, freq_khz)); +} - // halt core and enable debugging (if not already done) - // C_DEBUGEN is required to Halt on reset (DDI0337E, p. 10-6) - stlink_write_debug32(sl, STLINK_REG_DHCSR, STLINK_REG_DHCSR_DBGKEY | - STLINK_REG_DHCSR_C_HALT | STLINK_REG_DHCSR_C_DEBUGEN); +int stlink_status(stlink_t *sl) { + int ret; - // enable Halt on reset by set VC_CORERESET and TRCENA (DDI0337E, p. 10-10) - if (halt_on_reset) { - stlink_write_debug32(sl, STLINK_REG_CM3_DEMCR, STLINK_REG_CM3_DEMCR_TRCENA | - STLINK_REG_CM3_DEMCR_VC_HARDERR | STLINK_REG_CM3_DEMCR_VC_BUSERR | - STLINK_REG_CM3_DEMCR_VC_CORERESET); - - // clear VCATCH in the DFSR register - stlink_write_debug32(sl, STLINK_REG_DFSR, STLINK_REG_DFSR_VCATCH); - } else { - stlink_write_debug32(sl, STLINK_REG_CM3_DEMCR, STLINK_REG_CM3_DEMCR_TRCENA | - STLINK_REG_CM3_DEMCR_VC_HARDERR | STLINK_REG_CM3_DEMCR_VC_BUSERR); - } - - // clear S_RESET_ST in the DHCSR register - stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); - - // soft reset (core reset) by SYSRESETREQ (DDI0337E, p. 8-23) - ret = stlink_write_debug32(sl, STLINK_REG_AIRCR, STLINK_REG_AIRCR_VECTKEY | - STLINK_REG_AIRCR_SYSRESETREQ); - if (ret) { - ELOG("Soft reset failed: error write to AIRCR\n"); - return(ret); - } - - // waiting for a reset within 500ms - // DDI0337E, p. 10-4, Debug Halting Control and Status Register - timeout = time_ms() + 500; - while (time_ms() < timeout) { - // DDI0337E, p. 10-4, Debug Halting Control and Status Register - dhcsr = STLINK_REG_DHCSR_S_RESET_ST; - stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); - if ((dhcsr&STLINK_REG_DHCSR_S_RESET_ST) == 0) { - if (halt_on_reset) { - // waiting halt by the SYSRESETREQ exception - // DDI0403E, p. C1-699, Debug Fault Status Register - dfsr = 0; - stlink_read_debug32(sl, STLINK_REG_DFSR, &dfsr); - if ((dfsr&STLINK_REG_DFSR_VCATCH) == 0) { - continue; - } - } - timeout = 0; - break; - } - } - - // reset DFSR register. DFSR is power-on reset only (DDI0337H, p. 7-5) - stlink_write_debug32(sl, STLINK_REG_DFSR, STLINK_REG_DFSR_CLEAR); - - if (timeout) { - ELOG("Soft reset failed: timeout\n"); - return(-1); - } - - return(0); -} - -int stlink_reset(stlink_t *sl, enum reset_type type) { - uint32_t dhcsr; - unsigned timeout; - - DLOG("*** stlink_reset ***\n"); - - if (type == RESET_AUTO) { - // clear S_RESET_ST in DHCSR register for reset state detection - stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); - } - - if (type == RESET_HARD || type == RESET_AUTO) { - // hardware target reset - if (sl->version.stlink_v > 1) { - stlink_jtag_reset(sl, STLINK_JTAG_DRIVE_NRST_LOW); - // minimum reset pulse duration of 20 us (RM0008, 8.1.2 Power reset) - usleep(100); - stlink_jtag_reset(sl, STLINK_JTAG_DRIVE_NRST_HIGH); - } - if (sl->backend->reset(sl)) { return(-1); } - usleep(10000); - } - - if (type == RESET_AUTO) { - /* Check if the S_RESET_ST bit is set in DHCSR - * This means that a reset has occurred - * DDI0337E, p. 10-4, Debug Halting Control and Status Register */ - - dhcsr = 0; - stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); - if ((dhcsr & STLINK_REG_DHCSR_S_RESET_ST) == 0) { - // reset not done yet - // try reset through AIRCR so that NRST does not need to be connected - - WLOG("NRST is not connected\n"); - DLOG("Using reset through SYSRESETREQ\n"); - return stlink_soft_reset(sl, 0); - } - - // waiting for reset the S_RESET_ST bit within 500ms - timeout = time_ms() + 500; - while (time_ms() < timeout) { - dhcsr = STLINK_REG_DHCSR_S_RESET_ST; - stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); - if ((dhcsr&STLINK_REG_DHCSR_S_RESET_ST) == 0) - return(0); - } - - return(-1); - } - - if (type == RESET_SOFT || type == RESET_SOFT_AND_HALT) { - return stlink_soft_reset(sl, (type==RESET_SOFT_AND_HALT)); - } - - return(0); -} - -int stlink_run(stlink_t *sl, enum run_type type) { - struct stlink_reg rr; - DLOG("*** stlink_run ***\n"); - - /* Make sure we are in Thumb mode - * Cortex-M chips don't support ARM mode instructions - * xPSR may be incorrect if the vector table has invalid data */ - stlink_read_reg(sl, 16, &rr); - if ((rr.xpsr & (1 << 24)) == 0) { - ILOG("Go to Thumb mode\n"); - stlink_write_reg(sl, rr.xpsr | (1 << 24), 16); - } - - return(sl->backend->run(sl, type)); -} - -int stlink_set_swdclk(stlink_t *sl, int freq_khz) { - DLOG("*** set_swdclk ***\n"); - return(sl->backend->set_swdclk(sl, freq_khz)); -} - -int stlink_status(stlink_t *sl) { - int ret; - - DLOG("*** stlink_status ***\n"); - ret = sl->backend->status(sl); - stlink_core_stat(sl); - return(ret); -} + DLOG("*** stlink_status ***\n"); + ret = sl->backend->status(sl); + stlink_core_stat(sl); + return (ret); +} /** * Decode the version bits, originally from -sg, verified with usb @@ -1833,1109 +1851,1192 @@ int stlink_status(stlink_t *sl) { * @param slv output parsed version object */ void _parse_version(stlink_t *sl, stlink_version_t *slv) { - sl->version.flags = 0; - - if (sl->version.stlink_v < 3) { - uint32_t b0 = sl->q_buf[0]; // lsb - uint32_t b1 = sl->q_buf[1]; - uint32_t b2 = sl->q_buf[2]; - uint32_t b3 = sl->q_buf[3]; - uint32_t b4 = sl->q_buf[4]; - uint32_t b5 = sl->q_buf[5]; // msb - - // b0 b1 || b2 b3 | b4 b5 - // 4b | 6b | 6b || 2B | 2B - // stlink_v | jtag_v | swim_v || st_vid | stlink_pid - - slv->stlink_v = (b0 & 0xf0) >> 4; - slv->jtag_v = ((b0 & 0x0f) << 2) | ((b1 & 0xc0) >> 6); - slv->swim_v = b1 & 0x3f; - slv->st_vid = (b3 << 8) | b2; - slv->stlink_pid = (b5 << 8) | b4; - - // ST-LINK/V1 from J11 switch to api-v2 (and support SWD) - if (slv->stlink_v == 1) { - slv->jtag_api = slv->jtag_v > 11 ? STLINK_JTAG_API_V2 : STLINK_JTAG_API_V1; - } else { - slv->jtag_api = STLINK_JTAG_API_V2; - - // preferred API to get last R/W status from J15 - if (sl->version.jtag_v >= 15) { - sl->version.flags |= STLINK_F_HAS_GETLASTRWSTATUS2; - } - - if (sl->version.jtag_v >= 13) { - sl->version.flags |= STLINK_F_HAS_TRACE; - sl->max_trace_freq = STLINK_V2_MAX_TRACE_FREQUENCY; - } - } + sl->version.flags = 0; + + if (sl->version.stlink_v < 3) { + uint32_t b0 = sl->q_buf[0]; // lsb + uint32_t b1 = sl->q_buf[1]; + uint32_t b2 = sl->q_buf[2]; + uint32_t b3 = sl->q_buf[3]; + uint32_t b4 = sl->q_buf[4]; + uint32_t b5 = sl->q_buf[5]; // msb + + // b0 b1 || b2 b3 | b4 b5 + // 4b | 6b | 6b || 2B | 2B + // stlink_v | jtag_v | swim_v || st_vid | stlink_pid + + slv->stlink_v = (b0 & 0xf0) >> 4; + slv->jtag_v = ((b0 & 0x0f) << 2) | ((b1 & 0xc0) >> 6); + slv->swim_v = b1 & 0x3f; + slv->st_vid = (b3 << 8) | b2; + slv->stlink_pid = (b5 << 8) | b4; + + // ST-LINK/V1 from J11 switch to api-v2 (and support SWD) + if (slv->stlink_v == 1) { + slv->jtag_api = + slv->jtag_v > 11 ? STLINK_JTAG_API_V2 : STLINK_JTAG_API_V1; } else { - // V3 uses different version format, for reference see OpenOCD source - // (that was written from docs available from ST under NDA): - // https://github.com/ntfreak/openocd/blob/a6dacdff58ef36fcdac00c53ec27f19de1fbce0d/src/jtag/drivers/stlink_usb.c#L965 - slv->stlink_v = sl->q_buf[0]; - slv->swim_v = sl->q_buf[1]; - slv->jtag_v = sl->q_buf[2]; - slv->st_vid = (uint32_t)((sl->q_buf[9] << 8) | sl->q_buf[8]); - slv->stlink_pid = (uint32_t)((sl->q_buf[11] << 8) | sl->q_buf[10]); - slv->jtag_api = STLINK_JTAG_API_V3; - /* preferred API to get last R/W status */ + slv->jtag_api = STLINK_JTAG_API_V2; + + // preferred API to get last R/W status from J15 + if (sl->version.jtag_v >= 15) { sl->version.flags |= STLINK_F_HAS_GETLASTRWSTATUS2; - sl->version.flags |= STLINK_F_HAS_TRACE; - sl->max_trace_freq = STLINK_V3_MAX_TRACE_FREQUENCY; - } + } - return; + if (sl->version.jtag_v >= 13) { + sl->version.flags |= STLINK_F_HAS_TRACE; + sl->max_trace_freq = STLINK_V2_MAX_TRACE_FREQUENCY; + } + } + } else { + // V3 uses different version format, for reference see OpenOCD source + // (that was written from docs available from ST under NDA): + // https://github.com/ntfreak/openocd/blob/a6dacdff58ef36fcdac00c53ec27f19de1fbce0d/src/jtag/drivers/stlink_usb.c#L965 + slv->stlink_v = sl->q_buf[0]; + slv->swim_v = sl->q_buf[1]; + slv->jtag_v = sl->q_buf[2]; + slv->st_vid = (uint32_t)((sl->q_buf[9] << 8) | sl->q_buf[8]); + slv->stlink_pid = (uint32_t)((sl->q_buf[11] << 8) | sl->q_buf[10]); + slv->jtag_api = STLINK_JTAG_API_V3; + /* preferred API to get last R/W status */ + sl->version.flags |= STLINK_F_HAS_GETLASTRWSTATUS2; + sl->version.flags |= STLINK_F_HAS_TRACE; + sl->max_trace_freq = STLINK_V3_MAX_TRACE_FREQUENCY; + } + + return; } int stlink_version(stlink_t *sl) { - DLOG("*** looking up stlink version\n"); + DLOG("*** looking up stlink version\n"); - if (sl->backend->version(sl)) { - return(-1); - } + if (sl->backend->version(sl)) { + return (-1); + } - _parse_version(sl, &sl->version); + _parse_version(sl, &sl->version); - DLOG("st vid = 0x%04x (expect 0x%04x)\n", sl->version.st_vid, STLINK_USB_VID_ST); - DLOG("stlink pid = 0x%04x\n", sl->version.stlink_pid); - DLOG("stlink version = 0x%x\n", sl->version.stlink_v); - DLOG("jtag version = 0x%x\n", sl->version.jtag_v); - DLOG("swim version = 0x%x\n", sl->version.swim_v); + DLOG("st vid = 0x%04x (expect 0x%04x)\n", sl->version.st_vid, + STLINK_USB_VID_ST); + DLOG("stlink pid = 0x%04x\n", sl->version.stlink_pid); + DLOG("stlink version = 0x%x\n", sl->version.stlink_v); + DLOG("jtag version = 0x%x\n", sl->version.jtag_v); + DLOG("swim version = 0x%x\n", sl->version.swim_v); - if (sl->version.jtag_v == 0) { - DLOG(" notice: the firmware doesn't support a jtag/swd interface\n"); - } + if (sl->version.jtag_v == 0) { + DLOG(" notice: the firmware doesn't support a jtag/swd interface\n"); + } - if (sl->version.swim_v == 0) { - DLOG(" notice: the firmware doesn't support a swim interface\n"); - } + if (sl->version.swim_v == 0) { + DLOG(" notice: the firmware doesn't support a swim interface\n"); + } - return(0); + return (0); } int stlink_target_voltage(stlink_t *sl) { - int voltage = -1; - DLOG("*** reading target voltage\n"); + int voltage = -1; + DLOG("*** reading target voltage\n"); - if (sl->backend->target_voltage != NULL) { - voltage = sl->backend->target_voltage(sl); + if (sl->backend->target_voltage != NULL) { + voltage = sl->backend->target_voltage(sl); - if (voltage != -1) { - DLOG("target voltage = %imV\n", voltage); - } else { - DLOG("error reading target voltage\n"); - } + if (voltage != -1) { + DLOG("target voltage = %imV\n", voltage); } else { - DLOG("reading voltage not supported by backend\n"); + DLOG("error reading target voltage\n"); } + } else { + DLOG("reading voltage not supported by backend\n"); + } - return(voltage); + return (voltage); } int stlink_read_debug32(stlink_t *sl, uint32_t addr, uint32_t *data) { - int ret; + int ret; - ret = sl->backend->read_debug32(sl, addr, data); - if (!ret) - DLOG("*** stlink_read_debug32 %#010x at %#010x\n", *data, addr); + ret = sl->backend->read_debug32(sl, addr, data); + if (!ret) + DLOG("*** stlink_read_debug32 %#010x at %#010x\n", *data, addr); - return(ret); + return (ret); } int stlink_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data) { - DLOG("*** stlink_write_debug32 %#010x to %#010x\n", data, addr); - return sl->backend->write_debug32(sl, addr, data); + DLOG("*** stlink_write_debug32 %#010x to %#010x\n", data, addr); + return sl->backend->write_debug32(sl, addr, data); } int stlink_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { - DLOG("*** stlink_write_mem32 %u bytes to %#x\n", len, addr); + DLOG("*** stlink_write_mem32 %u bytes to %#x\n", len, addr); - if (len % 4 != 0) { - ELOG("Data length doesn't have a 32 bit alignment: +%d byte.\n", len % 4); - return(-1); - } + if (len % 4 != 0) { + ELOG("Data length doesn't have a 32 bit alignment: +%d byte.\n", len % 4); + return (-1); + } - return(sl->backend->write_mem32(sl, addr, len)); + return (sl->backend->write_mem32(sl, addr, len)); } int stlink_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { - DLOG("*** stlink_read_mem32 ***\n"); + DLOG("*** stlink_read_mem32 ***\n"); - if (len % 4 != 0) { // !!! never ever: fw gives just wrong values - ELOG("Data length doesn't have a 32 bit alignment: +%d byte.\n", len % 4); - return(-1); - } + if (len % 4 != 0) { // !!! never ever: fw gives just wrong values + ELOG("Data length doesn't have a 32 bit alignment: +%d byte.\n", len % 4); + return (-1); + } - return(sl->backend->read_mem32(sl, addr, len)); + return (sl->backend->read_mem32(sl, addr, len)); } int stlink_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len) { - DLOG("*** stlink_write_mem8 ***\n"); + DLOG("*** stlink_write_mem8 ***\n"); - if (len > 0x40) { // !!! never ever: Writing more then 0x40 bytes gives unexpected behaviour - ELOG("Data length > 64: +%d byte.\n", len); - return(-1); - } + if (len > 0x40) { // !!! never ever: Writing more then 0x40 bytes gives + // unexpected behaviour + ELOG("Data length > 64: +%d byte.\n", len); + return (-1); + } - return(sl->backend->write_mem8(sl, addr, len)); + return (sl->backend->write_mem8(sl, addr, len)); } int stlink_read_all_regs(stlink_t *sl, struct stlink_reg *regp) { - DLOG("*** stlink_read_all_regs ***\n"); - return(sl->backend->read_all_regs(sl, regp)); + DLOG("*** stlink_read_all_regs ***\n"); + return (sl->backend->read_all_regs(sl, regp)); } int stlink_read_all_unsupported_regs(stlink_t *sl, struct stlink_reg *regp) { - DLOG("*** stlink_read_all_unsupported_regs ***\n"); - return(sl->backend->read_all_unsupported_regs(sl, regp)); + DLOG("*** stlink_read_all_unsupported_regs ***\n"); + return (sl->backend->read_all_unsupported_regs(sl, regp)); } int stlink_write_reg(stlink_t *sl, uint32_t reg, int idx) { - DLOG("*** stlink_write_reg\n"); - return(sl->backend->write_reg(sl, reg, idx)); + DLOG("*** stlink_write_reg\n"); + return (sl->backend->write_reg(sl, reg, idx)); } int stlink_read_reg(stlink_t *sl, int r_idx, struct stlink_reg *regp) { - DLOG("*** stlink_read_reg\n"); - DLOG(" (%d) ***\n", r_idx); + DLOG("*** stlink_read_reg\n"); + DLOG(" (%d) ***\n", r_idx); - if (r_idx > 20 || r_idx < 0) { - fprintf(stderr, "Error: register index must be in [0..20]\n"); - return(-1); - } + if (r_idx > 20 || r_idx < 0) { + fprintf(stderr, "Error: register index must be in [0..20]\n"); + return (-1); + } - return(sl->backend->read_reg(sl, r_idx, regp)); + return (sl->backend->read_reg(sl, r_idx, regp)); } -int stlink_read_unsupported_reg(stlink_t *sl, int r_idx, struct stlink_reg *regp) { - int r_convert; +int stlink_read_unsupported_reg(stlink_t *sl, int r_idx, + struct stlink_reg *regp) { + int r_convert; - DLOG("*** stlink_read_unsupported_reg\n"); - DLOG(" (%d) ***\n", r_idx); + DLOG("*** stlink_read_unsupported_reg\n"); + DLOG(" (%d) ***\n", r_idx); - /* Convert to values used by STLINK_REG_DCRSR */ - if (r_idx >= 0x1C && r_idx <= 0x1F) { // primask, basepri, faultmask, or control - r_convert = 0x14; - } else if (r_idx == 0x40) { // FPSCR - r_convert = 0x21; - } else if (r_idx >= 0x20 && r_idx < 0x40) { - r_convert = 0x40 + (r_idx - 0x20); - } else { - fprintf(stderr, "Error: register address must be in [0x1C..0x40]\n"); - return(-1); - } + /* Convert to values used by STLINK_REG_DCRSR */ + if (r_idx >= 0x1C && + r_idx <= 0x1F) { // primask, basepri, faultmask, or control + r_convert = 0x14; + } else if (r_idx == 0x40) { // FPSCR + r_convert = 0x21; + } else if (r_idx >= 0x20 && r_idx < 0x40) { + r_convert = 0x40 + (r_idx - 0x20); + } else { + fprintf(stderr, "Error: register address must be in [0x1C..0x40]\n"); + return (-1); + } - return(sl->backend->read_unsupported_reg(sl, r_convert, regp)); + return (sl->backend->read_unsupported_reg(sl, r_convert, regp)); } -int stlink_write_unsupported_reg(stlink_t *sl, uint32_t val, int r_idx, struct stlink_reg *regp) { - int r_convert; +int stlink_write_unsupported_reg(stlink_t *sl, uint32_t val, int r_idx, + struct stlink_reg *regp) { + int r_convert; - DLOG("*** stlink_write_unsupported_reg\n"); - DLOG(" (%d) ***\n", r_idx); + DLOG("*** stlink_write_unsupported_reg\n"); + DLOG(" (%d) ***\n", r_idx); - /* Convert to values used by STLINK_REG_DCRSR */ - if (r_idx >= 0x1C && r_idx <= 0x1F) { /* primask, basepri, faultmask, or control */ - r_convert = r_idx; // the backend function handles this - } else if (r_idx == 0x40) { // FPSCR - r_convert = 0x21; - } else if (r_idx >= 0x20 && r_idx < 0x40) { - r_convert = 0x40 + (r_idx - 0x20); - } else { - fprintf(stderr, "Error: register address must be in [0x1C..0x40]\n"); - return(-1); - } + /* Convert to values used by STLINK_REG_DCRSR */ + if (r_idx >= 0x1C && + r_idx <= 0x1F) { /* primask, basepri, faultmask, or control */ + r_convert = r_idx; // the backend function handles this + } else if (r_idx == 0x40) { // FPSCR + r_convert = 0x21; + } else if (r_idx >= 0x20 && r_idx < 0x40) { + r_convert = 0x40 + (r_idx - 0x20); + } else { + fprintf(stderr, "Error: register address must be in [0x1C..0x40]\n"); + return (-1); + } - return(sl->backend->write_unsupported_reg(sl, val, r_convert, regp)); + return (sl->backend->write_unsupported_reg(sl, val, r_convert, regp)); } bool stlink_is_core_halted(stlink_t *sl) { - stlink_status(sl); - return(sl->core_stat == TARGET_HALTED); + stlink_status(sl); + return (sl->core_stat == TARGET_HALTED); } int stlink_step(stlink_t *sl) { - DLOG("*** stlink_step ***\n"); - return(sl->backend->step(sl)); + DLOG("*** stlink_step ***\n"); + return (sl->backend->step(sl)); } int stlink_current_mode(stlink_t *sl) { - int mode = sl->backend->current_mode(sl); - - switch (mode) { - case STLINK_DEV_DFU_MODE: - DLOG("stlink current mode: dfu\n"); - return(mode); - case STLINK_DEV_DEBUG_MODE: - DLOG("stlink current mode: debug (jtag or swd)\n"); - return(mode); - case STLINK_DEV_MASS_MODE: - DLOG("stlink current mode: mass\n"); - return(mode); - } + int mode = sl->backend->current_mode(sl); - DLOG("stlink mode: unknown!\n"); - return(STLINK_DEV_UNKNOWN_MODE); -} + switch (mode) { + case STLINK_DEV_DFU_MODE: + DLOG("stlink current mode: dfu\n"); + return (mode); + case STLINK_DEV_DEBUG_MODE: + DLOG("stlink current mode: debug (jtag or swd)\n"); + return (mode); + case STLINK_DEV_MASS_MODE: + DLOG("stlink current mode: mass\n"); + return (mode); + } -int stlink_trace_enable(stlink_t* sl, uint32_t frequency) { - DLOG("*** stlink_trace_enable ***\n"); - return(sl->backend->trace_enable(sl, frequency)); + DLOG("stlink mode: unknown!\n"); + return (STLINK_DEV_UNKNOWN_MODE); } -int stlink_trace_disable(stlink_t* sl) { - DLOG("*** stlink_trace_disable ***\n"); - return(sl->backend->trace_disable(sl)); +int stlink_trace_enable(stlink_t *sl, uint32_t frequency) { + DLOG("*** stlink_trace_enable ***\n"); + return (sl->backend->trace_enable(sl, frequency)); } -int stlink_trace_read(stlink_t* sl, uint8_t* buf, size_t size) { - return(sl->backend->trace_read(sl, buf, size)); +int stlink_trace_disable(stlink_t *sl) { + DLOG("*** stlink_trace_disable ***\n"); + return (sl->backend->trace_disable(sl)); } +int stlink_trace_read(stlink_t *sl, uint8_t *buf, size_t size) { + return (sl->backend->trace_read(sl, buf, size)); +} // End of delegates.... Common code below here... - - // same as above with entrypoint. void stlink_run_at(stlink_t *sl, stm32_addr_t addr) { - stlink_write_reg(sl, addr, 15); /* pc register */ - stlink_run(sl, RUN_NORMAL); + stlink_write_reg(sl, addr, 15); /* pc register */ + stlink_run(sl, RUN_NORMAL); - while (stlink_is_core_halted(sl)) { usleep(3000000); } + while (stlink_is_core_halted(sl)) { + usleep(3000000); + } } - // this function is called by stlink_status() // do not call stlink_core_stat() directly, always use stlink_status() void stlink_core_stat(stlink_t *sl) { - switch (sl->core_stat ) { - case TARGET_RUNNING: - DLOG(" core status: running\n"); - return; - case TARGET_HALTED: - DLOG(" core status: halted\n"); - return; - case TARGET_RESET: - DLOG(" core status: reset\n"); - return; - case TARGET_DEBUG_RUNNING: - DLOG(" core status: debug running\n"); - return; - default: - DLOG(" core status: unknown\n"); - } + switch (sl->core_stat) { + case TARGET_RUNNING: + DLOG(" core status: running\n"); + return; + case TARGET_HALTED: + DLOG(" core status: halted\n"); + return; + case TARGET_RESET: + DLOG(" core status: reset\n"); + return; + case TARGET_DEBUG_RUNNING: + DLOG(" core status: debug running\n"); + return; + default: + DLOG(" core status: unknown\n"); + } } -void stlink_print_data(stlink_t * sl) { - if (sl->q_len <= 0 || sl->verbose < UDEBUG) { return; } +void stlink_print_data(stlink_t *sl) { + if (sl->q_len <= 0 || sl->verbose < UDEBUG) { + return; + } - if (sl->verbose > 2) { DLOG("data_len = %d 0x%x\n", sl->q_len, sl->q_len); } + if (sl->verbose > 2) { + DLOG("data_len = %d 0x%x\n", sl->q_len, sl->q_len); + } - for (int i = 0; i < sl->q_len; i++) { - if (i % 16 == 0) { - /* - if (sl->q_data_dir == Q_DATA_OUT) { - fprintf(stdout, "\n<- 0x%08x ", sl->q_addr + i); - } else { - fprintf(stdout, "\n-> 0x%08x ", sl->q_addr + i); - } - */ - } - //DLOG(" %02x", (unsigned int) sl->q_buf[i]); - fprintf(stderr, " %02x", (unsigned int) sl->q_buf[i]); + for (int i = 0; i < sl->q_len; i++) { + if (i % 16 == 0) { + /* + if (sl->q_data_dir == Q_DATA_OUT) { + fprintf(stdout, "\n<- 0x%08x ", sl->q_addr + i); + } else { + fprintf(stdout, "\n-> 0x%08x ", sl->q_addr + i); + } + */ } - //DLOG("\n\n"); - fprintf(stderr, "\n"); + // DLOG(" %02x", (unsigned int) sl->q_buf[i]); + fprintf(stderr, " %02x", (unsigned int)sl->q_buf[i]); + } + // DLOG("\n\n"); + fprintf(stderr, "\n"); } /* Memory mapped file */ typedef struct mapped_file { - uint8_t* base; - size_t len; + uint8_t *base; + size_t len; } mapped_file_t; -#define MAPPED_FILE_INITIALIZER { NULL, 0 } +#define MAPPED_FILE_INITIALIZER \ + { NULL, 0 } -static int map_file(mapped_file_t* mf, const char* path) { - int error = -1; - struct stat st; +static int map_file(mapped_file_t *mf, const char *path) { + int error = -1; + struct stat st; - const int fd = open(path, O_RDONLY | O_BINARY); + const int fd = open(path, O_RDONLY | O_BINARY); - if (fd == -1) { - fprintf(stderr, "open(%s) == -1\n", path); - return(-1); - } + if (fd == -1) { + fprintf(stderr, "open(%s) == -1\n", path); + return (-1); + } - if (fstat(fd, &st) == -1) { - fprintf(stderr, "fstat(%s) == -1\n", path); - goto on_error; - } + if (fstat(fd, &st) == -1) { + fprintf(stderr, "fstat(%s) == -1\n", path); + goto on_error; + } - if (sizeof(st.st_size) != sizeof(size_t)) { - // on 32 bit systems, check if there is an overflow - if (st.st_size > (off_t)INT32_MAX) { - fprintf(stderr, "mmap() size_t overflow for file %s\n", path); - goto on_error; - } + if (sizeof(st.st_size) != sizeof(size_t)) { + // on 32 bit systems, check if there is an overflow + if (st.st_size > (off_t)INT32_MAX) { + fprintf(stderr, "mmap() size_t overflow for file %s\n", path); + goto on_error; } + } - mf->base = (uint8_t*)mmap(NULL, (size_t)(st.st_size), PROT_READ, MAP_SHARED, fd, 0); + mf->base = + (uint8_t *)mmap(NULL, (size_t)(st.st_size), PROT_READ, MAP_SHARED, fd, 0); - if (mf->base == MAP_FAILED) { - fprintf(stderr, "mmap() == MAP_FAILED for file %s\n", path); - goto on_error; - } + if (mf->base == MAP_FAILED) { + fprintf(stderr, "mmap() == MAP_FAILED for file %s\n", path); + goto on_error; + } - mf->len = st.st_size; - error = 0; // success + mf->len = st.st_size; + error = 0; // success on_error: - close(fd); - return(error); + close(fd); + return (error); } -static void unmap_file(mapped_file_t * mf) { - munmap((void*)mf->base, mf->len); - mf->base = (unsigned char*)MAP_FAILED; - mf->len = 0; +static void unmap_file(mapped_file_t *mf) { + munmap((void *)mf->base, mf->len); + mf->base = (unsigned char *)MAP_FAILED; + mf->len = 0; } -/* Limit the block size to compare to 0x1800 as anything larger will stall the STLINK2 - * Maybe STLINK V1 needs smaller value! +/* Limit the block size to compare to 0x1800 as anything larger will stall the + * STLINK2 Maybe STLINK V1 needs smaller value! */ -static int check_file(stlink_t* sl, mapped_file_t* mf, stm32_addr_t addr) { - size_t off; - size_t n_cmp = sl->flash_pgsz; +static int check_file(stlink_t *sl, mapped_file_t *mf, stm32_addr_t addr) { + size_t off; + size_t n_cmp = sl->flash_pgsz; - if ( n_cmp > 0x1800) { n_cmp = 0x1800; } + if (n_cmp > 0x1800) { + n_cmp = 0x1800; + } - for (off = 0; off < mf->len; off += n_cmp) { - size_t aligned_size; + for (off = 0; off < mf->len; off += n_cmp) { + size_t aligned_size; - size_t cmp_size = n_cmp; // adjust last page size + size_t cmp_size = n_cmp; // adjust last page size - if ((off + n_cmp) > mf->len) { cmp_size = mf->len - off; } + if ((off + n_cmp) > mf->len) { + cmp_size = mf->len - off; + } - aligned_size = cmp_size; + aligned_size = cmp_size; - if (aligned_size & (4 - 1)) { aligned_size = (cmp_size + 4) & ~(4 - 1); } + if (aligned_size & (4 - 1)) { + aligned_size = (cmp_size + 4) & ~(4 - 1); + } - stlink_read_mem32(sl, addr + (uint32_t)off, aligned_size); + stlink_read_mem32(sl, addr + (uint32_t)off, aligned_size); - if (memcmp(sl->q_buf, mf->base + off, cmp_size)) { return(-1); } + if (memcmp(sl->q_buf, mf->base + off, cmp_size)) { + return (-1); } + } - return(0); + return (0); } static void md5_calculate(mapped_file_t *mf) { - // calculate md5 checksum of given binary file - Md5Context md5Context; - MD5_HASH md5Hash; - Md5Initialise(&md5Context); - Md5Update(&md5Context, mf->base, (uint32_t)mf->len); - Md5Finalise(&md5Context, &md5Hash); - printf("md5 checksum: "); + // calculate md5 checksum of given binary file + Md5Context md5Context; + MD5_HASH md5Hash; + Md5Initialise(&md5Context); + Md5Update(&md5Context, mf->base, (uint32_t)mf->len); + Md5Finalise(&md5Context, &md5Hash); + printf("md5 checksum: "); - for (int i = 0; i < (int)sizeof(md5Hash); i++) { printf("%x", md5Hash.bytes[i]); } + for (int i = 0; i < (int)sizeof(md5Hash); i++) { + printf("%x", md5Hash.bytes[i]); + } - printf(", "); + printf(", "); } static void stlink_checksum(mapped_file_t *mp) { - /* checksum that backward compatible with official ST tools */ - uint32_t sum = 0; - uint8_t *mp_byte = (uint8_t *)mp->base; + /* checksum that backward compatible with official ST tools */ + uint32_t sum = 0; + uint8_t *mp_byte = (uint8_t *)mp->base; - for (size_t i = 0; i < mp->len; ++i) { sum += mp_byte[i]; } + for (size_t i = 0; i < mp->len; ++i) { + sum += mp_byte[i]; + } - printf("stlink checksum: 0x%08x\n", sum); + printf("stlink checksum: 0x%08x\n", sum); } static void stlink_fwrite_finalize(stlink_t *sl, stm32_addr_t addr) { - unsigned int val; - // set stack - stlink_read_debug32(sl, addr, &val); - stlink_write_reg(sl, val, 13); - // set PC to the reset routine - stlink_read_debug32(sl, addr + 4, &val); - stlink_write_reg(sl, val, 15); - stlink_run(sl, RUN_NORMAL); -} - -int stlink_mwrite_sram(stlink_t * sl, uint8_t* data, uint32_t length, stm32_addr_t addr) { - // write the file in sram at addr - - int error = -1; - size_t off; - size_t len; - - // check addr range is inside the sram - if (addr < sl->sram_base) { - fprintf(stderr, "addr too low\n"); - goto on_error; - } else if ((addr + length) < addr) { - fprintf(stderr, "addr overruns\n"); - goto on_error; - } else if ((addr + length) > (sl->sram_base + sl->sram_size)) { - fprintf(stderr, "addr too high\n"); - goto on_error; - } else if (addr & 3) { - fprintf(stderr, "unaligned addr\n"); - goto on_error; - } - - len = length; - - if (len & 3) { len -= len & 3; } - - // do the copy by 1kB blocks - for (off = 0; off < len; off += 1024) { - size_t size = 1024; - - if ((off + size) > len) { size = len - off; } - - memcpy(sl->q_buf, data + off, size); - - if (size & 3) { size += 2; } // round size if needed - - stlink_write_mem32(sl, addr + (uint32_t)off, size); - } - - if (length > len) { - memcpy(sl->q_buf, data + len, length - len); - stlink_write_mem8(sl, addr + (uint32_t)len, length - len); - } - - - error = 0; // success - stlink_fwrite_finalize(sl, addr); + unsigned int val; + // set stack + stlink_read_debug32(sl, addr, &val); + stlink_write_reg(sl, val, 13); + // set PC to the reset routine + stlink_read_debug32(sl, addr + 4, &val); + stlink_write_reg(sl, val, 15); + stlink_run(sl, RUN_NORMAL); +} + +int stlink_mwrite_sram(stlink_t *sl, uint8_t *data, uint32_t length, + stm32_addr_t addr) { + // write the file in sram at addr + + int error = -1; + size_t off; + size_t len; + + // check addr range is inside the sram + if (addr < sl->sram_base) { + fprintf(stderr, "addr too low\n"); + goto on_error; + } else if ((addr + length) < addr) { + fprintf(stderr, "addr overruns\n"); + goto on_error; + } else if ((addr + length) > (sl->sram_base + sl->sram_size)) { + fprintf(stderr, "addr too high\n"); + goto on_error; + } else if (addr & 3) { + fprintf(stderr, "unaligned addr\n"); + goto on_error; + } + + len = length; + + if (len & 3) { + len -= len & 3; + } + + // do the copy by 1kB blocks + for (off = 0; off < len; off += 1024) { + size_t size = 1024; + + if ((off + size) > len) { + size = len - off; + } + + memcpy(sl->q_buf, data + off, size); + + if (size & 3) { + size += 2; + } // round size if needed + + stlink_write_mem32(sl, addr + (uint32_t)off, size); + } + + if (length > len) { + memcpy(sl->q_buf, data + len, length - len); + stlink_write_mem8(sl, addr + (uint32_t)len, length - len); + } + + error = 0; // success + stlink_fwrite_finalize(sl, addr); on_error: - return(error); + return (error); } -int stlink_fwrite_sram(stlink_t * sl, const char* path, stm32_addr_t addr) { - // write the file in sram at addr +int stlink_fwrite_sram(stlink_t *sl, const char *path, stm32_addr_t addr) { + // write the file in sram at addr - int error = -1; - size_t off; - size_t len; - mapped_file_t mf = MAPPED_FILE_INITIALIZER; + int error = -1; + size_t off; + size_t len; + mapped_file_t mf = MAPPED_FILE_INITIALIZER; - if (map_file(&mf, path) == -1) { - fprintf(stderr, "map_file() == -1\n"); - return(-1); - } + if (map_file(&mf, path) == -1) { + fprintf(stderr, "map_file() == -1\n"); + return (-1); + } - printf("file %s ", path); - md5_calculate(&mf); - stlink_checksum(&mf); - - // check if addr range is inside the SRAM - if (addr < sl->sram_base) { - fprintf(stderr, "addr too low\n"); - goto on_error; - } else if ((addr + mf.len) < addr) { - fprintf(stderr, "addr overruns\n"); - goto on_error; - } else if ((addr + mf.len) > (sl->sram_base + sl->sram_size)) { - fprintf(stderr, "addr too high\n"); - goto on_error; - } else if (addr & 3) { - fprintf(stderr, "unaligned addr\n"); - goto on_error; - } + printf("file %s ", path); + md5_calculate(&mf); + stlink_checksum(&mf); - len = mf.len; + // check if addr range is inside the SRAM + if (addr < sl->sram_base) { + fprintf(stderr, "addr too low\n"); + goto on_error; + } else if ((addr + mf.len) < addr) { + fprintf(stderr, "addr overruns\n"); + goto on_error; + } else if ((addr + mf.len) > (sl->sram_base + sl->sram_size)) { + fprintf(stderr, "addr too high\n"); + goto on_error; + } else if (addr & 3) { + fprintf(stderr, "unaligned addr\n"); + goto on_error; + } - if (len & 3) { len -= len & 3; } + len = mf.len; - // do the copy by 1kB blocks - for (off = 0; off < len; off += 1024) { - size_t size = 1024; + if (len & 3) { + len -= len & 3; + } - if ((off + size) > len) { size = len - off; } + // do the copy by 1kB blocks + for (off = 0; off < len; off += 1024) { + size_t size = 1024; - memcpy(sl->q_buf, mf.base + off, size); + if ((off + size) > len) { + size = len - off; + } - if (size & 3) { size += 2; } // round size if needed + memcpy(sl->q_buf, mf.base + off, size); - stlink_write_mem32(sl, addr + (uint32_t)off, size); - } + if (size & 3) { + size += 2; + } // round size if needed - if (mf.len > len) { - memcpy(sl->q_buf, mf.base + len, mf.len - len); - stlink_write_mem8(sl, addr + (uint32_t)len, mf.len - len); - } + stlink_write_mem32(sl, addr + (uint32_t)off, size); + } - // check the file has been written - if (check_file(sl, &mf, addr) == -1) { - fprintf(stderr, "check_file() == -1\n"); - goto on_error; - } + if (mf.len > len) { + memcpy(sl->q_buf, mf.base + len, mf.len - len); + stlink_write_mem8(sl, addr + (uint32_t)len, mf.len - len); + } - error = 0; // success - stlink_fwrite_finalize(sl, addr); + // check the file has been written + if (check_file(sl, &mf, addr) == -1) { + fprintf(stderr, "check_file() == -1\n"); + goto on_error; + } + + error = 0; // success + stlink_fwrite_finalize(sl, addr); on_error: - unmap_file(&mf); - return(error); + unmap_file(&mf); + return (error); } -typedef bool (*save_block_fn)(void* arg, uint8_t* block, ssize_t len); +typedef bool (*save_block_fn)(void *arg, uint8_t *block, ssize_t len); -static int stlink_read( - stlink_t* sl, stm32_addr_t addr, size_t size, save_block_fn fn, void* fn_arg) { +static int stlink_read(stlink_t *sl, stm32_addr_t addr, size_t size, + save_block_fn fn, void *fn_arg) { - int error = -1; + int error = -1; - if (size < 1) { size = sl->flash_size; } + if (size < 1) { + size = sl->flash_size; + } - if (size > sl->flash_size) { - size = sl->flash_size; - } + if (size > sl->flash_size) { + size = sl->flash_size; + } - size_t cmp_size = (sl->flash_pgsz > 0x1800) ? 0x1800 : sl->flash_pgsz; + size_t cmp_size = (sl->flash_pgsz > 0x1800) ? 0x1800 : sl->flash_pgsz; - for (size_t off = 0; off < size; off += cmp_size) { - size_t aligned_size; + for (size_t off = 0; off < size; off += cmp_size) { + size_t aligned_size; - // adjust last page size - if ((off + cmp_size) > size) { cmp_size = size - off; } + // adjust last page size + if ((off + cmp_size) > size) { + cmp_size = size - off; + } - aligned_size = cmp_size; + aligned_size = cmp_size; - if (aligned_size & (4 - 1)) { aligned_size = (cmp_size + 4) & ~(4 - 1); } + if (aligned_size & (4 - 1)) { + aligned_size = (cmp_size + 4) & ~(4 - 1); + } - stlink_read_mem32(sl, addr + (uint32_t)off, aligned_size); + stlink_read_mem32(sl, addr + (uint32_t)off, aligned_size); - if (!fn(fn_arg, sl->q_buf, aligned_size)) { goto on_error; } + if (!fn(fn_arg, sl->q_buf, aligned_size)) { + goto on_error; } + } - error = 0; // success + error = 0; // success on_error: - return(error); + return (error); } struct stlink_fread_worker_arg { - int fd; + int fd; }; -static bool stlink_fread_worker(void* arg, uint8_t* block, ssize_t len) { - struct stlink_fread_worker_arg* the_arg = (struct stlink_fread_worker_arg*)arg; +static bool stlink_fread_worker(void *arg, uint8_t *block, ssize_t len) { + struct stlink_fread_worker_arg *the_arg = + (struct stlink_fread_worker_arg *)arg; - if (write(the_arg->fd, block, len) != len) { - fprintf(stderr, "write() != aligned_size\n"); - return(false); - } else { - return(true); - } + if (write(the_arg->fd, block, len) != len) { + fprintf(stderr, "write() != aligned_size\n"); + return (false); + } else { + return (true); + } } struct stlink_fread_ihex_worker_arg { - FILE* file; - uint32_t addr; - uint32_t lba; - uint8_t buf[16]; - uint8_t buf_pos; + FILE *file; + uint32_t addr; + uint32_t lba; + uint8_t buf[16]; + uint8_t buf_pos; }; -static bool stlink_fread_ihex_newsegment(struct stlink_fread_ihex_worker_arg* the_arg) { - uint32_t addr = the_arg->addr; - uint8_t sum = 2 + 4 + (uint8_t)((addr & 0xFF000000) >> 24) + (uint8_t)((addr & 0x00FF0000) >> 16); +static bool +stlink_fread_ihex_newsegment(struct stlink_fread_ihex_worker_arg *the_arg) { + uint32_t addr = the_arg->addr; + uint8_t sum = 2 + 4 + (uint8_t)((addr & 0xFF000000) >> 24) + + (uint8_t)((addr & 0x00FF0000) >> 16); - if (17 != fprintf(the_arg->file, ":02000004%04X%02X\r\n", (addr & 0xFFFF0000) >> 16, - (uint8_t)(0x100 - sum))) { - return(false); - } + if (17 != fprintf(the_arg->file, ":02000004%04X%02X\r\n", + (addr & 0xFFFF0000) >> 16, (uint8_t)(0x100 - sum))) { + return (false); + } - the_arg->lba = (addr & 0xFFFF0000); - return(true); + the_arg->lba = (addr & 0xFFFF0000); + return (true); } -static bool stlink_fread_ihex_writeline(struct stlink_fread_ihex_worker_arg* the_arg) { - uint8_t count = the_arg->buf_pos; +static bool +stlink_fread_ihex_writeline(struct stlink_fread_ihex_worker_arg *the_arg) { + uint8_t count = the_arg->buf_pos; - if (count == 0) { return(true); } + if (count == 0) { + return (true); + } - uint32_t addr = the_arg->addr; + uint32_t addr = the_arg->addr; - if (the_arg->lba != (addr & 0xFFFF0000)) { // segment changed - if (!stlink_fread_ihex_newsegment(the_arg)) { - return(false); - } + if (the_arg->lba != (addr & 0xFFFF0000)) { // segment changed + if (!stlink_fread_ihex_newsegment(the_arg)) { + return (false); } + } - uint8_t sum = count + (uint8_t)((addr & 0x0000FF00) >> 8) + (uint8_t)(addr & 0x000000FF); + uint8_t sum = count + (uint8_t)((addr & 0x0000FF00) >> 8) + + (uint8_t)(addr & 0x000000FF); - if (9 != fprintf(the_arg->file, ":%02X%04X00", count, (addr & 0x0000FFFF))) { - return(false); - } + if (9 != fprintf(the_arg->file, ":%02X%04X00", count, (addr & 0x0000FFFF))) { + return (false); + } - for (uint8_t i = 0; i < count; ++i) { - uint8_t b = the_arg->buf[i]; - sum += b; + for (uint8_t i = 0; i < count; ++i) { + uint8_t b = the_arg->buf[i]; + sum += b; - if (2 != fprintf(the_arg->file, "%02X", b)) { - return(false); - } + if (2 != fprintf(the_arg->file, "%02X", b)) { + return (false); } + } - if (4 != fprintf(the_arg->file, "%02X\r\n", (uint8_t)(0x100 - sum))) { - return(false); - } + if (4 != fprintf(the_arg->file, "%02X\r\n", (uint8_t)(0x100 - sum))) { + return (false); + } - the_arg->addr += count; - the_arg->buf_pos = 0; + the_arg->addr += count; + the_arg->buf_pos = 0; - return(true); + return (true); } -static bool stlink_fread_ihex_init( - struct stlink_fread_ihex_worker_arg* the_arg, int fd, stm32_addr_t addr) { - the_arg->file = fdopen(fd, "w"); - the_arg->addr = addr; - the_arg->lba = 0; - the_arg->buf_pos = 0; +static bool stlink_fread_ihex_init(struct stlink_fread_ihex_worker_arg *the_arg, + int fd, stm32_addr_t addr) { + the_arg->file = fdopen(fd, "w"); + the_arg->addr = addr; + the_arg->lba = 0; + the_arg->buf_pos = 0; - return (the_arg->file != NULL); + return (the_arg->file != NULL); } -static bool stlink_fread_ihex_worker(void* arg, uint8_t* block, ssize_t len) { - struct stlink_fread_ihex_worker_arg* the_arg = (struct stlink_fread_ihex_worker_arg*)arg; - - for (ssize_t i = 0; i < len; ++i) { - if (the_arg->buf_pos == sizeof(the_arg->buf)) { // line is full - if (!stlink_fread_ihex_writeline(the_arg)) { return(false); } - } +static bool stlink_fread_ihex_worker(void *arg, uint8_t *block, ssize_t len) { + struct stlink_fread_ihex_worker_arg *the_arg = + (struct stlink_fread_ihex_worker_arg *)arg; - the_arg->buf[the_arg->buf_pos++] = block[i]; + for (ssize_t i = 0; i < len; ++i) { + if (the_arg->buf_pos == sizeof(the_arg->buf)) { // line is full + if (!stlink_fread_ihex_writeline(the_arg)) { + return (false); + } } - return(true); + the_arg->buf[the_arg->buf_pos++] = block[i]; + } + + return (true); } -static bool stlink_fread_ihex_finalize(struct stlink_fread_ihex_worker_arg* the_arg) { - if (!stlink_fread_ihex_writeline(the_arg)) { return(false); } +static bool +stlink_fread_ihex_finalize(struct stlink_fread_ihex_worker_arg *the_arg) { + if (!stlink_fread_ihex_writeline(the_arg)) { + return (false); + } - // FIXME: do we need the Start Linear Address? + // FIXME: do we need the Start Linear Address? - if (13 != fprintf(the_arg->file, ":00000001FF\r\n")) { // EoF - return(false); - } + if (13 != fprintf(the_arg->file, ":00000001FF\r\n")) { // EoF + return (false); + } - return (0 == fclose(the_arg->file)); + return (0 == fclose(the_arg->file)); } -int stlink_fread(stlink_t* sl, const char* path, bool is_ihex, stm32_addr_t addr, size_t size) { - // read size bytes from addr to file - ILOG("read from address %#010x size %u\n", addr, (unsigned)size); +int stlink_fread(stlink_t *sl, const char *path, bool is_ihex, + stm32_addr_t addr, size_t size) { + // read size bytes from addr to file + ILOG("read from address %#010x size %u\n", addr, (unsigned)size); - int error; - int fd = open(path, O_RDWR | O_TRUNC | O_CREAT | O_BINARY, 00700); + int error; + int fd = open(path, O_RDWR | O_TRUNC | O_CREAT | O_BINARY, 00700); - if (fd == -1) { - fprintf(stderr, "open(%s) == -1\n", path); - return(-1); - } + if (fd == -1) { + fprintf(stderr, "open(%s) == -1\n", path); + return (-1); + } - if (is_ihex) { - struct stlink_fread_ihex_worker_arg arg; + if (is_ihex) { + struct stlink_fread_ihex_worker_arg arg; - if (stlink_fread_ihex_init(&arg, fd, addr)) { - error = stlink_read(sl, addr, size, &stlink_fread_ihex_worker, &arg); + if (stlink_fread_ihex_init(&arg, fd, addr)) { + error = stlink_read(sl, addr, size, &stlink_fread_ihex_worker, &arg); - if (!stlink_fread_ihex_finalize(&arg)) { error = -1; } - } else { - error = -1; - } + if (!stlink_fread_ihex_finalize(&arg)) { + error = -1; + } } else { - struct stlink_fread_worker_arg arg = { fd }; - error = stlink_read(sl, addr, size, &stlink_fread_worker, &arg); + error = -1; } + } else { + struct stlink_fread_worker_arg arg = {fd}; + error = stlink_read(sl, addr, size, &stlink_fread_worker, &arg); + } - close(fd); - return(error); + close(fd); + return (error); } -int write_buffer_to_sram(stlink_t *sl, flash_loader_t* fl, const uint8_t* buf, size_t size) { - // write the buffer right after the loader - size_t chunk = size & ~0x3; - size_t rem = size & 0x3; +int write_buffer_to_sram(stlink_t *sl, flash_loader_t *fl, const uint8_t *buf, + size_t size) { + // write the buffer right after the loader + size_t chunk = size & ~0x3; + size_t rem = size & 0x3; - if (chunk) { - memcpy(sl->q_buf, buf, chunk); - stlink_write_mem32(sl, fl->buf_addr, chunk); - } + if (chunk) { + memcpy(sl->q_buf, buf, chunk); + stlink_write_mem32(sl, fl->buf_addr, chunk); + } - if (rem) { - memcpy(sl->q_buf, buf + chunk, rem); - stlink_write_mem8(sl, (fl->buf_addr) + (uint32_t)chunk, rem); - } + if (rem) { + memcpy(sl->q_buf, buf + chunk, rem); + stlink_write_mem8(sl, (fl->buf_addr) + (uint32_t)chunk, rem); + } - return(0); + return (0); } uint32_t calculate_F4_sectornum(uint32_t flashaddr) { - uint32_t offset = 0; - flashaddr &= ~STM32_FLASH_BASE; // page now holding the actual flash address - - if (flashaddr >= 0x100000) { - offset = 12; - flashaddr -= 0x100000; - } - - if (flashaddr < 0x4000) { - return (offset + 0); - } else if (flashaddr < 0x8000) { - return(offset + 1); - } else if (flashaddr < 0xc000) { - return(offset + 2); - } else if (flashaddr < 0x10000) { - return(offset + 3); - } else if (flashaddr < 0x20000) { - return(offset + 4); - } else { - return(offset + (flashaddr / 0x20000) + 4); - } - + uint32_t offset = 0; + flashaddr &= ~STM32_FLASH_BASE; // page now holding the actual flash address + + if (flashaddr >= 0x100000) { + offset = 12; + flashaddr -= 0x100000; + } + + if (flashaddr < 0x4000) { + return (offset + 0); + } else if (flashaddr < 0x8000) { + return (offset + 1); + } else if (flashaddr < 0xc000) { + return (offset + 2); + } else if (flashaddr < 0x10000) { + return (offset + 3); + } else if (flashaddr < 0x20000) { + return (offset + 4); + } else { + return (offset + (flashaddr / 0x20000) + 4); + } } uint32_t calculate_F7_sectornum(uint32_t flashaddr) { - flashaddr &= ~STM32_FLASH_BASE; // Page now holding the actual flash address - - if (flashaddr < 0x20000) { - return(flashaddr / 0x8000); - } else if (flashaddr < 0x40000) { - return(4); - } else { - return((flashaddr / 0x40000) + 4); - } + flashaddr &= ~STM32_FLASH_BASE; // Page now holding the actual flash address + if (flashaddr < 0x20000) { + return (flashaddr / 0x8000); + } else if (flashaddr < 0x40000) { + return (4); + } else { + return ((flashaddr / 0x40000) + 4); + } } -uint32_t calculate_H7_sectornum(stlink_t *sl, uint32_t flashaddr, unsigned bank) { - flashaddr &= ~((bank==BANK_1)?STM32_FLASH_BASE:STM32_H7_FLASH_BANK2_BASE); // sector holding the flash address - return(flashaddr / sl->flash_pgsz); +uint32_t calculate_H7_sectornum(stlink_t *sl, uint32_t flashaddr, + unsigned bank) { + flashaddr &= + ~((bank == BANK_1) + ? STM32_FLASH_BASE + : STM32_H7_FLASH_BANK2_BASE); // sector holding the flash address + return (flashaddr / sl->flash_pgsz); } // returns BKER:PNB for the given page address uint32_t calculate_L4_page(stlink_t *sl, uint32_t flashaddr) { - uint32_t bker = 0; - uint32_t flashopt; - stlink_read_debug32(sl, STM32L4_FLASH_OPTR, &flashopt); - flashaddr -= STM32_FLASH_BASE; - - if (sl->chip_id == STLINK_CHIPID_STM32_L4 || - sl->chip_id == STLINK_CHIPID_STM32_L496X || - sl->chip_id == STLINK_CHIPID_STM32_L4RX) { - // this chip use dual banked flash - if (flashopt & (uint32_t)(1lu << STM32L4_FLASH_OPTR_DUALBANK)) { - uint32_t banksize = (uint32_t)sl->flash_size / 2; - - if (flashaddr >= banksize) { - flashaddr -= banksize; - bker = 0x100; - } - } + uint32_t bker = 0; + uint32_t flashopt; + stlink_read_debug32(sl, STM32L4_FLASH_OPTR, &flashopt); + flashaddr -= STM32_FLASH_BASE; + + if (sl->chip_id == STLINK_CHIPID_STM32_L4 || + sl->chip_id == STLINK_CHIPID_STM32_L496X || + sl->chip_id == STLINK_CHIPID_STM32_L4RX) { + // this chip use dual banked flash + if (flashopt & (uint32_t)(1lu << STM32L4_FLASH_OPTR_DUALBANK)) { + uint32_t banksize = (uint32_t)sl->flash_size / 2; + + if (flashaddr >= banksize) { + flashaddr -= banksize; + bker = 0x100; + } } + } - // For 1MB chips without the dual-bank option set, the page address will overflow - // into the BKER bit, which gives us the correct bank:page value. - return(bker | flashaddr / (uint32_t)sl->flash_pgsz); + // For 1MB chips without the dual-bank option set, the page address will + // overflow into the BKER bit, which gives us the correct bank:page value. + return (bker | flashaddr / (uint32_t)sl->flash_pgsz); } uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr) { - if ((sl->chip_id == STLINK_CHIPID_STM32_F2) || - (sl->chip_id == STLINK_CHIPID_STM32_F4) || - (sl->chip_id == STLINK_CHIPID_STM32_F4_DE) || - (sl->chip_id == STLINK_CHIPID_STM32_F4_LP) || - (sl->chip_id == STLINK_CHIPID_STM32_F4_HD) || - (sl->chip_id == STLINK_CHIPID_STM32_F411RE) || - (sl->chip_id == STLINK_CHIPID_STM32_F446) || - (sl->chip_id == STLINK_CHIPID_STM32_F4_DSI) || - (sl->chip_id == STLINK_CHIPID_STM32_F72XXX) || - (sl->chip_id == STLINK_CHIPID_STM32_F412)) { - uint32_t sector = calculate_F4_sectornum(flashaddr); - - if (sector >= 12) { sector -= 12; } - - if (sector < 4) { - sl->flash_pgsz = 0x4000; - } else if (sector < 5) { - sl->flash_pgsz = 0x10000; - } else { - sl->flash_pgsz = 0x20000; - } - } else if (sl->chip_id == STLINK_CHIPID_STM32_F7 || - sl->chip_id == STLINK_CHIPID_STM32_F7XXXX) { - uint32_t sector = calculate_F7_sectornum(flashaddr); + if ((sl->chip_id == STLINK_CHIPID_STM32_F2) || + (sl->chip_id == STLINK_CHIPID_STM32_F4) || + (sl->chip_id == STLINK_CHIPID_STM32_F4_DE) || + (sl->chip_id == STLINK_CHIPID_STM32_F4_LP) || + (sl->chip_id == STLINK_CHIPID_STM32_F4_HD) || + (sl->chip_id == STLINK_CHIPID_STM32_F411RE) || + (sl->chip_id == STLINK_CHIPID_STM32_F446) || + (sl->chip_id == STLINK_CHIPID_STM32_F4_DSI) || + (sl->chip_id == STLINK_CHIPID_STM32_F72XXX) || + (sl->chip_id == STLINK_CHIPID_STM32_F412)) { + uint32_t sector = calculate_F4_sectornum(flashaddr); + + if (sector >= 12) { + sector -= 12; + } + + if (sector < 4) { + sl->flash_pgsz = 0x4000; + } else if (sector < 5) { + sl->flash_pgsz = 0x10000; + } else { + sl->flash_pgsz = 0x20000; + } + } else if (sl->chip_id == STLINK_CHIPID_STM32_F7 || + sl->chip_id == STLINK_CHIPID_STM32_F7XXXX) { + uint32_t sector = calculate_F7_sectornum(flashaddr); - if (sector < 4) { - sl->flash_pgsz = 0x8000; - } else if (sector < 5) { - sl->flash_pgsz = 0x20000; - } else { - sl->flash_pgsz = 0x40000; - } + if (sector < 4) { + sl->flash_pgsz = 0x8000; + } else if (sector < 5) { + sl->flash_pgsz = 0x20000; + } else { + sl->flash_pgsz = 0x40000; } + } - return((uint32_t)sl->flash_pgsz); + return ((uint32_t)sl->flash_pgsz); } /** - * Erase a page of flash, assumes sl is fully populated with things like chip/core ids + * Erase a page of flash, assumes sl is fully populated with things like + * chip/core ids * @param sl stlink context * @param flashaddr an address in the flash page to erase * @return 0 on success -ve on failure */ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { - // wait for ongoing op to finish - wait_flash_busy(sl); - // clear flash IO errors - clear_flash_error(sl); + // wait for ongoing op to finish + wait_flash_busy(sl); + // clear flash IO errors + clear_flash_error(sl); + + if (sl->flash_type == STLINK_FLASH_TYPE_F4 || + sl->flash_type == STLINK_FLASH_TYPE_F7 || + sl->flash_type == STLINK_FLASH_TYPE_L4) { + // unlock if locked + unlock_flash_if(sl); + + // select the page to erase + if ((sl->chip_id == STLINK_CHIPID_STM32_L4) || + (sl->chip_id == STLINK_CHIPID_STM32_L43X) || + (sl->chip_id == STLINK_CHIPID_STM32_L46X) || + (sl->chip_id == STLINK_CHIPID_STM32_L496X) || + (sl->chip_id == STLINK_CHIPID_STM32_L4RX)) { + // calculate the actual bank+page from the address + uint32_t page = calculate_L4_page(sl, flashaddr); + + fprintf(stderr, "EraseFlash - Page:0x%x Size:0x%x ", page, + stlink_calculate_pagesize(sl, flashaddr)); + + write_flash_cr_bker_pnb(sl, page); + } else if (sl->chip_id == STLINK_CHIPID_STM32_F7 || + sl->chip_id == STLINK_CHIPID_STM32_F7XXXX) { + // calculate the actual page from the address + uint32_t sector = calculate_F7_sectornum(flashaddr); - if (sl->flash_type == STLINK_FLASH_TYPE_F4 || - sl->flash_type == STLINK_FLASH_TYPE_F7 || - sl->flash_type == STLINK_FLASH_TYPE_L4) { - // unlock if locked - unlock_flash_if(sl); - - // select the page to erase - if ((sl->chip_id == STLINK_CHIPID_STM32_L4) || - (sl->chip_id == STLINK_CHIPID_STM32_L43X) || - (sl->chip_id == STLINK_CHIPID_STM32_L46X) || - (sl->chip_id == STLINK_CHIPID_STM32_L496X) || - (sl->chip_id == STLINK_CHIPID_STM32_L4RX)) { - // calculate the actual bank+page from the address - uint32_t page = calculate_L4_page(sl, flashaddr); - - fprintf(stderr, "EraseFlash - Page:0x%x Size:0x%x ", - page, stlink_calculate_pagesize(sl, flashaddr)); - - write_flash_cr_bker_pnb(sl, page); - } else if (sl->chip_id == STLINK_CHIPID_STM32_F7 || - sl->chip_id == STLINK_CHIPID_STM32_F7XXXX) { - // calculate the actual page from the address - uint32_t sector = calculate_F7_sectornum(flashaddr); - - fprintf(stderr, "EraseFlash - Sector:0x%x Size:0x%x ", - sector, stlink_calculate_pagesize(sl, flashaddr)); - write_flash_cr_snb(sl, sector, BANK_1); - } else { - // calculate the actual page from the address - uint32_t sector = calculate_F4_sectornum(flashaddr); + fprintf(stderr, "EraseFlash - Sector:0x%x Size:0x%x ", sector, + stlink_calculate_pagesize(sl, flashaddr)); + write_flash_cr_snb(sl, sector, BANK_1); + } else { + // calculate the actual page from the address + uint32_t sector = calculate_F4_sectornum(flashaddr); - fprintf(stderr, "EraseFlash - Sector:0x%x Size:0x%x ", - sector, stlink_calculate_pagesize(sl, flashaddr)); + fprintf(stderr, "EraseFlash - Sector:0x%x Size:0x%x ", sector, + stlink_calculate_pagesize(sl, flashaddr)); - // the SNB values for flash sectors in the second bank do not directly - // follow the values for the first bank on 2mb devices... - if (sector >= 12) { sector += 4; } + // the SNB values for flash sectors in the second bank do not directly + // follow the values for the first bank on 2mb devices... + if (sector >= 12) { + sector += 4; + } - write_flash_cr_snb(sl, sector, BANK_1); - } + write_flash_cr_snb(sl, sector, BANK_1); + } - set_flash_cr_strt(sl, BANK_1); // start erase operation - wait_flash_busy(sl); // wait for completion - lock_flash(sl); // TODO: fails to program if this is in + set_flash_cr_strt(sl, BANK_1); // start erase operation + wait_flash_busy(sl); // wait for completion + lock_flash(sl); // TODO: fails to program if this is in #if DEBUG_FLASH - fprintf(stdout, "Erase Final CR:0x%x\n", read_flash_cr(sl, BANK_1)); + fprintf(stdout, "Erase Final CR:0x%x\n", read_flash_cr(sl, BANK_1)); #endif - } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { + } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { - uint32_t val; - uint32_t flash_regs_base = get_stm32l0_flash_base(sl); + uint32_t val; + uint32_t flash_regs_base = get_stm32l0_flash_base(sl); - // check if the locks are set - stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); + // check if the locks are set + stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); - if ((val & (1 << 0)) || (val & (1 << 1))) { - // disable pecr protection - stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, FLASH_L0_PEKEY1); - stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, FLASH_L0_PEKEY2); + if ((val & (1 << 0)) || (val & (1 << 1))) { + // disable pecr protection + stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, + FLASH_L0_PEKEY1); + stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, + FLASH_L0_PEKEY2); - // check pecr.pelock is cleared - stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); + // check pecr.pelock is cleared + stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); - if (val & (1 << 0)) { - WLOG("pecr.pelock not clear (%#x)\n", val); - return(-1); - } + if (val & (1 << 0)) { + WLOG("pecr.pelock not clear (%#x)\n", val); + return (-1); + } - // unlock program memory - stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, FLASH_L0_PRGKEY1); - stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, FLASH_L0_PRGKEY2); + // unlock program memory + stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, + FLASH_L0_PRGKEY1); + stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, + FLASH_L0_PRGKEY2); - // check pecr.prglock is cleared - stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); + // check pecr.prglock is cleared + stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); - if (val & (1 << 1)) { - WLOG("pecr.prglock not clear (%#x)\n", val); - return(-1); - } - } + if (val & (1 << 1)) { + WLOG("pecr.prglock not clear (%#x)\n", val); + return (-1); + } + } - // set pecr.{erase,prog} - val |= (1 << 9) | (1 << 3); - stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); - - // write 0 to the first word of the page to be erased - stlink_write_debug32(sl, flashaddr, 0); - - /* MP: It is better to wait for clearing the busy bit after issuing page - * erase command, even though PM0062 recommends to wait before it. - * Test shows that a few iterations is performed in the following loop - * before busy bit is cleared. - */ - wait_flash_busy(sl); - - // reset lock bits - stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); - val |= (1 << 0) | (1 << 1) | (1 << 2); - stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB || - sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { - uint32_t val; - unlock_flash_if(sl); - set_flash_cr_per(sl, BANK_1); // set the 'enable Flash erase' bit - - // set the page to erase - if (sl->flash_type == STLINK_FLASH_TYPE_WB) { - uint32_t flash_page = ((flashaddr - STM32_FLASH_BASE) / (uint32_t)(sl->flash_pgsz)); - stlink_read_debug32(sl, STM32WB_FLASH_CR, &val); - - // sec 3.10.5 - PNB[7:0] is offset by 3. - val &= ~(0xFF << 3); // Clear previously set page number (if any) - val |= ((flash_page & 0xFF) << 3); - - stlink_write_debug32(sl, STM32WB_FLASH_CR, val); - } else if (sl->flash_type == STLINK_FLASH_TYPE_G0) { - uint32_t flash_page = ((flashaddr - STM32_FLASH_BASE) / (uint32_t)(sl->flash_pgsz)); - stlink_read_debug32(sl, STM32Gx_FLASH_CR, &val); - // sec 3.7.5 - PNB[5:0] is offset by 3. PER is 0x2. - val &= ~(0x3F << 3); - val |= ((flash_page & 0x3F) << 3) | (1 << FLASH_CR_PER); - stlink_write_debug32(sl, STM32Gx_FLASH_CR, val); - } else if (sl->flash_type == STLINK_FLASH_TYPE_G4) { - uint32_t flash_page = ((flashaddr - STM32_FLASH_BASE) / (uint32_t)(sl->flash_pgsz)); - stlink_read_debug32(sl, STM32Gx_FLASH_CR, &val); - // sec 3.7.5 - PNB[6:0] is offset by 3. PER is 0x2. - val &= ~(0x7F << 3); - val |= ((flash_page & 0x7F) << 3) | (1 << FLASH_CR_PER); - stlink_write_debug32(sl, STM32Gx_FLASH_CR, val); - } + // set pecr.{erase,prog} + val |= (1 << 9) | (1 << 3); + stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); - set_flash_cr_strt(sl, BANK_1); // set the 'start operation' bit - wait_flash_busy(sl); // wait for the 'busy' bit to clear - clear_flash_cr_per(sl, BANK_1); // clear the 'enable page erase' bit - lock_flash(sl); - } else if (sl->flash_type == STLINK_FLASH_TYPE_F0 || - sl->flash_type == STLINK_FLASH_TYPE_F1_XL) { - unsigned bank = (flashaddr < STM32_F1_FLASH_BANK2_BASE)?BANK_1:BANK_2; - unlock_flash_if(sl); - clear_flash_cr_pg(sl, bank); // clear the pg bit - set_flash_cr_per(sl, bank); // set the page erase bit - write_flash_ar(sl, flashaddr, bank); // select the page to erase - set_flash_cr_strt(sl, bank); // start erase operation, reset by hw with busy bit - wait_flash_busy(sl); - clear_flash_cr_per(sl, bank); // clear the page erase bit - lock_flash(sl); - } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { - unsigned bank = (flashaddr < STM32_H7_FLASH_BANK2_BASE)?BANK_1:BANK_2; - unlock_flash_if(sl); // unlock if locked - uint32_t sector = calculate_H7_sectornum(sl, flashaddr, bank);// calculate the actual page from the address - write_flash_cr_snb(sl, sector, bank); // select the page to erase - set_flash_cr_strt(sl, bank); // start erase operation - wait_flash_busy(sl); // wait for completion - lock_flash(sl); - } else { - WLOG("unknown coreid %x, page erase failed\n", sl->core_id); - return(-1); - } + // write 0 to the first word of the page to be erased + stlink_write_debug32(sl, flashaddr, 0); + + /* MP: It is better to wait for clearing the busy bit after issuing page + * erase command, even though PM0062 recommends to wait before it. + * Test shows that a few iterations is performed in the following loop + * before busy bit is cleared. + */ + wait_flash_busy(sl); + + // reset lock bits + stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); + val |= (1 << 0) | (1 << 1) | (1 << 2); + stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); + } else if (sl->flash_type == STLINK_FLASH_TYPE_WB || + sl->flash_type == STLINK_FLASH_TYPE_G0 || + sl->flash_type == STLINK_FLASH_TYPE_G4) { + uint32_t val; + unlock_flash_if(sl); + set_flash_cr_per(sl, BANK_1); // set the 'enable Flash erase' bit + + // set the page to erase + if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + uint32_t flash_page = + ((flashaddr - STM32_FLASH_BASE) / (uint32_t)(sl->flash_pgsz)); + stlink_read_debug32(sl, STM32WB_FLASH_CR, &val); + + // sec 3.10.5 - PNB[7:0] is offset by 3. + val &= ~(0xFF << 3); // Clear previously set page number (if any) + val |= ((flash_page & 0xFF) << 3); + + stlink_write_debug32(sl, STM32WB_FLASH_CR, val); + } else if (sl->flash_type == STLINK_FLASH_TYPE_G0) { + uint32_t flash_page = + ((flashaddr - STM32_FLASH_BASE) / (uint32_t)(sl->flash_pgsz)); + stlink_read_debug32(sl, STM32Gx_FLASH_CR, &val); + // sec 3.7.5 - PNB[5:0] is offset by 3. PER is 0x2. + val &= ~(0x3F << 3); + val |= ((flash_page & 0x3F) << 3) | (1 << FLASH_CR_PER); + stlink_write_debug32(sl, STM32Gx_FLASH_CR, val); + } else if (sl->flash_type == STLINK_FLASH_TYPE_G4) { + uint32_t flash_page = + ((flashaddr - STM32_FLASH_BASE) / (uint32_t)(sl->flash_pgsz)); + stlink_read_debug32(sl, STM32Gx_FLASH_CR, &val); + // sec 3.7.5 - PNB[6:0] is offset by 3. PER is 0x2. + val &= ~(0x7F << 3); + val |= ((flash_page & 0x7F) << 3) | (1 << FLASH_CR_PER); + stlink_write_debug32(sl, STM32Gx_FLASH_CR, val); + } + + set_flash_cr_strt(sl, BANK_1); // set the 'start operation' bit + wait_flash_busy(sl); // wait for the 'busy' bit to clear + clear_flash_cr_per(sl, BANK_1); // clear the 'enable page erase' bit + lock_flash(sl); + } else if (sl->flash_type == STLINK_FLASH_TYPE_F0 || + sl->flash_type == STLINK_FLASH_TYPE_F1_XL) { + unsigned bank = (flashaddr < STM32_F1_FLASH_BANK2_BASE) ? BANK_1 : BANK_2; + unlock_flash_if(sl); + clear_flash_cr_pg(sl, bank); // clear the pg bit + set_flash_cr_per(sl, bank); // set the page erase bit + write_flash_ar(sl, flashaddr, bank); // select the page to erase + set_flash_cr_strt(sl, + bank); // start erase operation, reset by hw with busy bit + wait_flash_busy(sl); + clear_flash_cr_per(sl, bank); // clear the page erase bit + lock_flash(sl); + } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + unsigned bank = (flashaddr < STM32_H7_FLASH_BANK2_BASE) ? BANK_1 : BANK_2; + unlock_flash_if(sl); // unlock if locked + uint32_t sector = calculate_H7_sectornum( + sl, flashaddr, bank); // calculate the actual page from the address + write_flash_cr_snb(sl, sector, bank); // select the page to erase + set_flash_cr_strt(sl, bank); // start erase operation + wait_flash_busy(sl); // wait for completion + lock_flash(sl); + } else { + WLOG("unknown coreid %x, page erase failed\n", sl->core_id); + return (-1); + } - return check_flash_error(sl); + return check_flash_error(sl); } int stlink_erase_flash_mass(stlink_t *sl) { - int err = 0; + int err = 0; - // TODO: User MER bit to mass-erase WB series. - if (sl->flash_type == STLINK_FLASH_TYPE_L0 || - sl->flash_type == STLINK_FLASH_TYPE_WB) { - // erase each page - int i = 0, num_pages = (int)(sl->flash_size / sl->flash_pgsz); + // TODO: User MER bit to mass-erase WB series. + if (sl->flash_type == STLINK_FLASH_TYPE_L0 || + sl->flash_type == STLINK_FLASH_TYPE_WB) { + // erase each page + int i = 0, num_pages = (int)(sl->flash_size / sl->flash_pgsz); - for (i = 0; i < num_pages; i++) { - // addr must be an addr inside the page - stm32_addr_t addr = (stm32_addr_t)sl->flash_base + i * (stm32_addr_t)sl->flash_pgsz; + for (i = 0; i < num_pages; i++) { + // addr must be an addr inside the page + stm32_addr_t addr = + (stm32_addr_t)sl->flash_base + i * (stm32_addr_t)sl->flash_pgsz; - if (stlink_erase_flash_page(sl, addr)) { - WLOG("Failed to erase_flash_page(%#x) == -1\n", addr); - return(-1); - } + if (stlink_erase_flash_page(sl, addr)) { + WLOG("Failed to erase_flash_page(%#x) == -1\n", addr); + return (-1); + } - fprintf(stdout, "-> Flash page at %5d/%5d erased\n", i, num_pages); - fflush(stdout); - } + fprintf(stdout, "-> Flash page at %5d/%5d erased\n", i, num_pages); + fflush(stdout); + } - fprintf(stdout, "\n"); - } else { - wait_flash_busy(sl); - clear_flash_error(sl); - unlock_flash_if(sl); - - if (sl->flash_type == STLINK_FLASH_TYPE_H7 && sl->chip_id != STLINK_CHIPID_STM32_H7AX) { - // set parallelism - write_flash_cr_psiz(sl, 3 /*64it*/, BANK_1); - if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { - write_flash_cr_psiz(sl, 3 /*64bit*/, BANK_2); - } - } + fprintf(stdout, "\n"); + } else { + wait_flash_busy(sl); + clear_flash_error(sl); + unlock_flash_if(sl); - set_flash_cr_mer(sl, 1, BANK_1); // set the mass erase bit - set_flash_cr_strt(sl, BANK_1); // start erase operation, reset by hw with busy bit + if (sl->flash_type == STLINK_FLASH_TYPE_H7 && + sl->chip_id != STLINK_CHIPID_STM32_H7AX) { + // set parallelism + write_flash_cr_psiz(sl, 3 /*64it*/, BANK_1); + if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { + write_flash_cr_psiz(sl, 3 /*64bit*/, BANK_2); + } + } - if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL || - (sl->flash_type == STLINK_FLASH_TYPE_H7 && sl->chip_flags & CHIP_F_HAS_DUAL_BANK)) { - set_flash_cr_mer(sl, 1, BANK_2); // set the mass erase bit in bank 2 - set_flash_cr_strt(sl, BANK_2); // start erase operation in bank 2 - } + set_flash_cr_mer(sl, 1, BANK_1); // set the mass erase bit + set_flash_cr_strt( + sl, BANK_1); // start erase operation, reset by hw with busy bit - wait_flash_busy_progress(sl); - lock_flash(sl); + if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL || + (sl->flash_type == STLINK_FLASH_TYPE_H7 && + sl->chip_flags & CHIP_F_HAS_DUAL_BANK)) { + set_flash_cr_mer(sl, 1, BANK_2); // set the mass erase bit in bank 2 + set_flash_cr_strt(sl, BANK_2); // start erase operation in bank 2 + } - // reset the mass erase bit - set_flash_cr_mer(sl, 0, BANK_1); - if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL || - (sl->flash_type == STLINK_FLASH_TYPE_H7 && sl->chip_flags & CHIP_F_HAS_DUAL_BANK)) { - set_flash_cr_mer(sl, 0, BANK_2); - } + wait_flash_busy_progress(sl); + lock_flash(sl); - err = check_flash_error(sl); + // reset the mass erase bit + set_flash_cr_mer(sl, 0, BANK_1); + if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL || + (sl->flash_type == STLINK_FLASH_TYPE_H7 && + sl->chip_flags & CHIP_F_HAS_DUAL_BANK)) { + set_flash_cr_mer(sl, 0, BANK_2); } - return(err); + err = check_flash_error(sl); + } + + return (err); } -int stlink_fcheck_flash(stlink_t *sl, const char* path, stm32_addr_t addr) { - // check the contents of path are at addr +int stlink_fcheck_flash(stlink_t *sl, const char *path, stm32_addr_t addr) { + // check the contents of path are at addr - int res; - mapped_file_t mf = MAPPED_FILE_INITIALIZER; + int res; + mapped_file_t mf = MAPPED_FILE_INITIALIZER; - if (map_file(&mf, path) == -1) { return(-1); } + if (map_file(&mf, path) == -1) { + return (-1); + } - res = check_file(sl, &mf, addr); - unmap_file(&mf); - return(res); + res = check_file(sl, &mf, addr); + unmap_file(&mf); + return (res); } /** @@ -2946,696 +3047,741 @@ int stlink_fcheck_flash(stlink_t *sl, const char* path, stm32_addr_t addr) { * @param length how much * @return 0 for success, -ve for failure */ -int stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, unsigned length) { - size_t off; - size_t cmp_size = (sl->flash_pgsz > 0x1800) ? 0x1800 : sl->flash_pgsz; - ILOG("Starting verification of write complete\n"); +int stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, + unsigned length) { + size_t off; + size_t cmp_size = (sl->flash_pgsz > 0x1800) ? 0x1800 : sl->flash_pgsz; + ILOG("Starting verification of write complete\n"); - for (off = 0; off < length; off += cmp_size) { - size_t aligned_size; + for (off = 0; off < length; off += cmp_size) { + size_t aligned_size; - // adjust last page size - if ((off + cmp_size) > length) { cmp_size = length - off; } - - aligned_size = cmp_size; - - if (aligned_size & (4 - 1)) { aligned_size = (cmp_size + 4) & ~(4 - 1); } - - stlink_read_mem32(sl, address + (uint32_t)off, aligned_size); - - if (memcmp(sl->q_buf, data + off, cmp_size)) { - ELOG("Verification of flash failed at offset: %u\n", (unsigned int)off); - return(-1); - } + // adjust last page size + if ((off + cmp_size) > length) { + cmp_size = length - off; } - ILOG("Flash written and verified! jolly good!\n"); - return(0); + aligned_size = cmp_size; -} - -int stm32l1_write_half_pages( - stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t len, uint32_t pagesize) { - unsigned int count; - unsigned int num_half_pages = len / pagesize; - uint32_t val; - uint32_t flash_regs_base = get_stm32l0_flash_base(sl); - flash_loader_t fl; - - ILOG("Starting Half page flash write for STM32L core id\n"); - - /* Flash loader initialisation */ - if (stlink_flash_loader_init(sl, &fl) == -1) { - WLOG("stlink_flash_loader_init() == -1\n"); - return(-1); + if (aligned_size & (4 - 1)) { + aligned_size = (cmp_size + 4) & ~(4 - 1); } - // unlock already done - stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); - val |= (1 << FLASH_L1_FPRG); - stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); - - val |= (1 << FLASH_L1_PROG); - stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); - - wait_flash_busy(sl); - - for (count = 0; count < num_half_pages; count++) { - if (stlink_flash_loader_run( - sl, &fl, addr + count * pagesize, base + count * pagesize, pagesize) == -1) { - WLOG("l1_stlink_flash_loader_run(%#x) failed! == -1\n", addr + count * pagesize); - stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); - val &= ~((1 << FLASH_L1_FPRG) | (1 << FLASH_L1_PROG)); - stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); - return(-1); - } + stlink_read_mem32(sl, address + (uint32_t)off, aligned_size); - // wait for sr.busy to be cleared - if (sl->verbose >= 1) { - // show progress; writing procedure is slow and previous errors are misleading - fprintf(stdout, "\r%3u/%u halfpages written", count + 1, num_half_pages); - fflush(stdout); - } - - wait_flash_busy(sl); + if (memcmp(sl->q_buf, data + off, cmp_size)) { + ELOG("Verification of flash failed at offset: %u\n", (unsigned int)off); + return (-1); } + } - stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); - val &= ~(1 << FLASH_L1_PROG); - stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); - stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); - val &= ~(1 << FLASH_L1_FPRG); - stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); - return(0); + ILOG("Flash written and verified! jolly good!\n"); + return (0); } -int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { - - // According to DDI0419C, Table C1-7 firstly force halt - stlink_write_debug32(sl, STLINK_REG_DHCSR, STLINK_REG_DHCSR_DBGKEY | - STLINK_REG_DHCSR_C_DEBUGEN | - STLINK_REG_DHCSR_C_HALT); - // and only then disable interrupts - stlink_write_debug32(sl, STLINK_REG_DHCSR, STLINK_REG_DHCSR_DBGKEY | - STLINK_REG_DHCSR_C_DEBUGEN | - STLINK_REG_DHCSR_C_HALT | - STLINK_REG_DHCSR_C_MASKINTS); - - // disable DMA - set_dma_state(sl, fl, 0); - - // wait for ongoing op to finish - wait_flash_busy(sl); - // Clear errors - clear_flash_error(sl); - - if ((sl->flash_type == STLINK_FLASH_TYPE_F4) || - (sl->flash_type == STLINK_FLASH_TYPE_F7) || - (sl->flash_type == STLINK_FLASH_TYPE_L4)) { - ILOG("Starting Flash write for F2/F4/F7/L4\n"); - - // Flash loader initialisation - if (stlink_flash_loader_init(sl, fl) == -1) { - ELOG("stlink_flash_loader_init() == -1\n"); - return(-1); - } - - unlock_flash_if(sl); // first unlock the cr - - int voltage; - if (sl->version.stlink_v == 1) { - WLOG("STLINK V1 cannot read voltage, use default voltage 3.2V\n"); - voltage = 3200; - } else { - voltage = stlink_target_voltage(sl); - } - - if (voltage == -1) { - ELOG("Failed to read Target voltage\n"); - return(-1); - } - - if (sl->flash_type == STLINK_FLASH_TYPE_L4) { - // L4 does not have a byte-write mode - if (voltage < 1710) { - ELOG("Target voltage (%d mV) too low for flash writes!\n", voltage); - return(-1); - } - } else { - if (voltage > 2700) { - ILOG("enabling 32-bit flash writes\n"); - write_flash_cr_psiz(sl, 2, BANK_1); - } else { - ILOG("Target voltage (%d mV) too low for 32-bit flash, " - "using 8-bit flash writes\n", voltage); - write_flash_cr_psiz(sl, 0, BANK_1); - } - } - - // set programming mode - set_flash_cr_pg(sl, BANK_1); - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB || - sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { - ILOG("Starting Flash write for WB/G0/G4\n"); - - unlock_flash_if(sl); // unlock flash if necessary - set_flash_cr_pg(sl, BANK_1); // set PG 'allow programming' bit - } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { - ILOG("Starting Flash write for L0\n"); - - uint32_t val; - uint32_t flash_regs_base; - if (sl->chip_id == STLINK_CHIPID_STM32_L0 || - sl->chip_id == STLINK_CHIPID_STM32_L0_CAT5 || - sl->chip_id == STLINK_CHIPID_STM32_L0_CAT2 || - sl->chip_id == STLINK_CHIPID_STM32_L011) { - flash_regs_base = STM32L0_FLASH_REGS_ADDR; - } else { - flash_regs_base = STM32L_FLASH_REGS_ADDR; - } - - // disable pecr protection - stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, FLASH_L0_PEKEY1); - stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, FLASH_L0_PEKEY2); - - // check pecr.pelock is cleared - stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); - if (val & (1 << 0)) { - ELOG("pecr.pelock not clear\n"); - return(-1); - } - - // unlock program memory - stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, FLASH_L0_PRGKEY1); - stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, FLASH_L0_PRGKEY2); +int stm32l1_write_half_pages(stlink_t *sl, stm32_addr_t addr, uint8_t *base, + uint32_t len, uint32_t pagesize) { + unsigned int count; + unsigned int num_half_pages = len / pagesize; + uint32_t val; + uint32_t flash_regs_base = get_stm32l0_flash_base(sl); + flash_loader_t fl; - // check pecr.prglock is cleared - stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); - if (val & (1 << 1)) { - ELOG("pecr.prglock not clear\n"); - return(-1); - } - } else if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || - (sl->flash_type == STLINK_FLASH_TYPE_F1_XL)) { - ILOG("Starting Flash write for VL/F0/F3/F1_XL\n"); - - // flash loader initialisation - if (stlink_flash_loader_init(sl, fl) == -1) { - ELOG("stlink_flash_loader_init() == -1\n"); - return(-1); - } - } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { - ILOG("Starting Flash write for H7\n"); + ILOG("Starting Half page flash write for STM32L core id\n"); - unlock_flash_if(sl); // unlock the cr - set_flash_cr_pg(sl, BANK_1); // set programming mode - if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { - set_flash_cr_pg(sl, BANK_2); - } - if (sl->chip_id != STLINK_CHIPID_STM32_H7AX) { - // set parallelism - write_flash_cr_psiz(sl, 3 /*64it*/, BANK_1); - if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { - write_flash_cr_psiz(sl, 3 /*64bit*/, BANK_2); - } - } - } else { - ELOG("unknown coreid, not sure how to write: %x\n", sl->core_id); - return(-1); - } + /* Flash loader initialisation */ + if (stlink_flash_loader_init(sl, &fl) == -1) { + WLOG("stlink_flash_loader_init() == -1\n"); + return (-1); + } - return(0); -} - -int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t addr, - uint8_t* base, uint32_t len) { - size_t off; - if ((sl->flash_type == STLINK_FLASH_TYPE_F4) || - (sl->flash_type == STLINK_FLASH_TYPE_F7) || - (sl->flash_type == STLINK_FLASH_TYPE_L4)) { - size_t buf_size = (sl->sram_size > 0x8000) ? 0x8000 : 0x4000; - for (off = 0; off < len;) { - size_t size = len - off > buf_size ? buf_size : len - off; - if (stlink_flash_loader_run(sl, fl, addr + (uint32_t)off, base + off, size) == -1) { - ELOG("stlink_flash_loader_run(%#x) failed! == -1\n", (unsigned)(addr + off)); - check_flash_error(sl); - return(-1); - } + // unlock already done + stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); + val |= (1 << FLASH_L1_FPRG); + stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); - off += size; - } - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB || - sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { - DLOG("Starting %3u page write\r\n", (unsigned int)(len / sl->flash_pgsz)); - for (off = 0; off < len; off += sizeof(uint32_t)) { - uint32_t data; - - if ((off % sl->flash_pgsz) > (sl->flash_pgsz - 5)) { - fprintf(stdout, "\r%3u/%3u pages written", - (unsigned int)(off / sl->flash_pgsz), - (unsigned int)(len / sl->flash_pgsz)); - fflush(stdout); - } - - write_uint32((unsigned char*)&data, *(uint32_t*)(base + off)); - stlink_write_debug32(sl, addr + (uint32_t)off, data); - wait_flash_busy(sl); // wait for 'busy' bit in FLASH_SR to clear - } - fprintf(stdout, "\n"); - - // flash writes happen as 2 words at a time - if ((off / sizeof(uint32_t)) % 2 != 0) { - stlink_write_debug32(sl, addr + (uint32_t)off, 0); // write a single word of zeros - wait_flash_busy(sl); // wait for 'busy' bit in FLASH_SR to clear - } - } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { - uint32_t val; - uint32_t flash_regs_base; - uint32_t pagesize; - - if (sl->chip_id == STLINK_CHIPID_STM32_L0 || - sl->chip_id == STLINK_CHIPID_STM32_L0_CAT5 || - sl->chip_id == STLINK_CHIPID_STM32_L0_CAT2 || - sl->chip_id == STLINK_CHIPID_STM32_L011) { - flash_regs_base = STM32L0_FLASH_REGS_ADDR; - pagesize = L0_WRITE_BLOCK_SIZE; - } else { - flash_regs_base = STM32L_FLASH_REGS_ADDR; - pagesize = L1_WRITE_BLOCK_SIZE; - } + val |= (1 << FLASH_L1_PROG); + stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); - off = 0; + wait_flash_busy(sl); - if (len > pagesize) { - if (stm32l1_write_half_pages(sl, addr, base, len, pagesize) == -1) { - // this may happen on a blank device! - WLOG("\nwrite_half_pages failed == -1\n"); - } else { - off = (len / pagesize) * pagesize; - } - } + for (count = 0; count < num_half_pages; count++) { + if (stlink_flash_loader_run(sl, &fl, addr + count * pagesize, + base + count * pagesize, pagesize) == -1) { + WLOG("l1_stlink_flash_loader_run(%#x) failed! == -1\n", + addr + count * pagesize); + stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); + val &= ~((1 << FLASH_L1_FPRG) | (1 << FLASH_L1_PROG)); + stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); + return (-1); + } - // write remaining word in program memory - for ( ; off < len; off += sizeof(uint32_t)) { - uint32_t data; + // wait for sr.busy to be cleared + if (sl->verbose >= 1) { + // show progress; writing procedure is slow and previous errors are + // misleading + fprintf(stdout, "\r%3u/%u halfpages written", count + 1, num_half_pages); + fflush(stdout); + } - if ((off % sl->flash_pgsz) > (sl->flash_pgsz - 5)) { - fprintf(stdout, "\r%3u/%3u pages written", - (unsigned int)(off / sl->flash_pgsz), - (unsigned int)(len / sl->flash_pgsz)); - fflush(stdout); - } + wait_flash_busy(sl); + } - write_uint32((unsigned char*)&data, *(uint32_t*)(base + off)); - stlink_write_debug32(sl, addr + (uint32_t)off, data); + stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); + val &= ~(1 << FLASH_L1_PROG); + stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); + stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); + val &= ~(1 << FLASH_L1_FPRG); + stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); + return (0); +} - // wait for sr.busy to be cleared - do { - stlink_read_debug32(sl, flash_regs_base + FLASH_SR_OFF, &val); - } while ((val & (1 << 0)) != 0); +int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { - // TODO: check redo write operation - } - fprintf(stdout, "\n"); - } else if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || - (sl->flash_type == STLINK_FLASH_TYPE_F1_XL)) { - int write_block_count = 0; - for (off = 0; off < len; off += sl->flash_pgsz) { - // adjust last write size - size_t size = len - off > sl->flash_pgsz ? sl->flash_pgsz : len - off; - - // unlock and set programming mode - unlock_flash_if(sl); - - DLOG("Finished unlocking flash, running loader!\n"); - - if (stlink_flash_loader_run(sl, fl, addr + (uint32_t)off, base + off, size) == -1) { - ELOG("stlink_flash_loader_run(%#x) failed! == -1\n", (unsigned)(addr + off)); - check_flash_error(sl); - return(-1); - } + // According to DDI0419C, Table C1-7 firstly force halt + stlink_write_debug32(sl, STLINK_REG_DHCSR, + STLINK_REG_DHCSR_DBGKEY | STLINK_REG_DHCSR_C_DEBUGEN | + STLINK_REG_DHCSR_C_HALT); + // and only then disable interrupts + stlink_write_debug32(sl, STLINK_REG_DHCSR, + STLINK_REG_DHCSR_DBGKEY | STLINK_REG_DHCSR_C_DEBUGEN | + STLINK_REG_DHCSR_C_HALT | + STLINK_REG_DHCSR_C_MASKINTS); + + // disable DMA + set_dma_state(sl, fl, 0); + + // wait for ongoing op to finish + wait_flash_busy(sl); + // Clear errors + clear_flash_error(sl); + + if ((sl->flash_type == STLINK_FLASH_TYPE_F4) || + (sl->flash_type == STLINK_FLASH_TYPE_F7) || + (sl->flash_type == STLINK_FLASH_TYPE_L4)) { + ILOG("Starting Flash write for F2/F4/F7/L4\n"); + + // Flash loader initialisation + if (stlink_flash_loader_init(sl, fl) == -1) { + ELOG("stlink_flash_loader_init() == -1\n"); + return (-1); + } + + unlock_flash_if(sl); // first unlock the cr + + int voltage; + if (sl->version.stlink_v == 1) { + WLOG("STLINK V1 cannot read voltage, use default voltage 3.2V\n"); + voltage = 3200; + } else { + voltage = stlink_target_voltage(sl); + } - lock_flash(sl); + if (voltage == -1) { + ELOG("Failed to read Target voltage\n"); + return (-1); + } - if (sl->verbose >= 1) { - // show progress; writing procedure is slow and previous errors are misleading - fprintf(stdout, "\r%3u/%3u pages written", ++write_block_count, - (unsigned int)((len + sl->flash_pgsz - 1) / sl->flash_pgsz)); - fflush(stdout); - } - } - if (sl->verbose >= 1) { - fprintf(stdout, "\n"); - } - } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { - for (off = 0; off < len;) { - // Program STM32H7x with 64-byte Flash words - size_t chunk = (len - off > 64) ? 64 : len - off; - memcpy(sl->q_buf, base + off, chunk); - stlink_write_mem32(sl, addr + (uint32_t)off, 64); - wait_flash_busy(sl); - - off += chunk; - - if (sl->verbose >= 1) { - // show progress - fprintf(stdout, "\r%u/%u bytes written", (unsigned int)off, (unsigned int)len); - fflush(stdout); - } - } - if (sl->verbose >= 1) { - fprintf(stdout, "\n"); - } + if (sl->flash_type == STLINK_FLASH_TYPE_L4) { + // L4 does not have a byte-write mode + if (voltage < 1710) { + ELOG("Target voltage (%d mV) too low for flash writes!\n", voltage); + return (-1); + } + } else { + if (voltage > 2700) { + ILOG("enabling 32-bit flash writes\n"); + write_flash_cr_psiz(sl, 2, BANK_1); + } else { + ILOG("Target voltage (%d mV) too low for 32-bit flash, " + "using 8-bit flash writes\n", + voltage); + write_flash_cr_psiz(sl, 0, BANK_1); + } + } + + // set programming mode + set_flash_cr_pg(sl, BANK_1); + } else if (sl->flash_type == STLINK_FLASH_TYPE_WB || + sl->flash_type == STLINK_FLASH_TYPE_G0 || + sl->flash_type == STLINK_FLASH_TYPE_G4) { + ILOG("Starting Flash write for WB/G0/G4\n"); + + unlock_flash_if(sl); // unlock flash if necessary + set_flash_cr_pg(sl, BANK_1); // set PG 'allow programming' bit + } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { + ILOG("Starting Flash write for L0\n"); + + uint32_t val; + uint32_t flash_regs_base; + if (sl->chip_id == STLINK_CHIPID_STM32_L0 || + sl->chip_id == STLINK_CHIPID_STM32_L0_CAT5 || + sl->chip_id == STLINK_CHIPID_STM32_L0_CAT2 || + sl->chip_id == STLINK_CHIPID_STM32_L011) { + flash_regs_base = STM32L0_FLASH_REGS_ADDR; } else { - return(-1); + flash_regs_base = STM32L_FLASH_REGS_ADDR; } - return check_flash_error(sl); -} + // disable pecr protection + stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, + FLASH_L0_PEKEY1); + stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, + FLASH_L0_PEKEY2); -int stlink_flashloader_stop(stlink_t *sl, flash_loader_t *fl) { - uint32_t dhcsr; - - if ((sl->flash_type == STLINK_FLASH_TYPE_F4) || - (sl->flash_type == STLINK_FLASH_TYPE_F7) || - (sl->flash_type == STLINK_FLASH_TYPE_L4) || - (sl->flash_type == STLINK_FLASH_TYPE_WB) || - (sl->flash_type == STLINK_FLASH_TYPE_G0) || - (sl->flash_type == STLINK_FLASH_TYPE_G4) || - (sl->flash_type == STLINK_FLASH_TYPE_H7)) { - - clear_flash_cr_pg(sl, BANK_1); - if (sl->flash_type == STLINK_FLASH_TYPE_H7 && sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { - clear_flash_cr_pg(sl, BANK_2); - } - lock_flash(sl); - } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { - uint32_t val; - uint32_t flash_regs_base; - if (sl->chip_id == STLINK_CHIPID_STM32_L0 || - sl->chip_id == STLINK_CHIPID_STM32_L0_CAT5 || - sl->chip_id == STLINK_CHIPID_STM32_L0_CAT2 || - sl->chip_id == STLINK_CHIPID_STM32_L011) { - flash_regs_base = STM32L0_FLASH_REGS_ADDR; - } else { - flash_regs_base = STM32L_FLASH_REGS_ADDR; - } - // reset lock bits - stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); - val |= (1 << 0) | (1 << 1) | (1 << 2); - stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); + // check pecr.pelock is cleared + stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); + if (val & (1 << 0)) { + ELOG("pecr.pelock not clear\n"); + return (-1); + } + + // unlock program memory + stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, + FLASH_L0_PRGKEY1); + stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, + FLASH_L0_PRGKEY2); + + // check pecr.prglock is cleared + stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); + if (val & (1 << 1)) { + ELOG("pecr.prglock not clear\n"); + return (-1); + } + } else if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || + (sl->flash_type == STLINK_FLASH_TYPE_F1_XL)) { + ILOG("Starting Flash write for VL/F0/F3/F1_XL\n"); + + // flash loader initialisation + if (stlink_flash_loader_init(sl, fl) == -1) { + ELOG("stlink_flash_loader_init() == -1\n"); + return (-1); + } + } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + ILOG("Starting Flash write for H7\n"); + + unlock_flash_if(sl); // unlock the cr + set_flash_cr_pg(sl, BANK_1); // set programming mode + if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { + set_flash_cr_pg(sl, BANK_2); + } + if (sl->chip_id != STLINK_CHIPID_STM32_H7AX) { + // set parallelism + write_flash_cr_psiz(sl, 3 /*64it*/, BANK_1); + if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { + write_flash_cr_psiz(sl, 3 /*64bit*/, BANK_2); + } + } + } else { + ELOG("unknown coreid, not sure how to write: %x\n", sl->core_id); + return (-1); + } + + return (0); +} + +int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, + stm32_addr_t addr, uint8_t *base, uint32_t len) { + size_t off; + if ((sl->flash_type == STLINK_FLASH_TYPE_F4) || + (sl->flash_type == STLINK_FLASH_TYPE_F7) || + (sl->flash_type == STLINK_FLASH_TYPE_L4)) { + size_t buf_size = (sl->sram_size > 0x8000) ? 0x8000 : 0x4000; + for (off = 0; off < len;) { + size_t size = len - off > buf_size ? buf_size : len - off; + if (stlink_flash_loader_run(sl, fl, addr + (uint32_t)off, base + off, + size) == -1) { + ELOG("stlink_flash_loader_run(%#x) failed! == -1\n", + (unsigned)(addr + off)); + check_flash_error(sl); + return (-1); + } + + off += size; + } + } else if (sl->flash_type == STLINK_FLASH_TYPE_WB || + sl->flash_type == STLINK_FLASH_TYPE_G0 || + sl->flash_type == STLINK_FLASH_TYPE_G4) { + DLOG("Starting %3u page write\r\n", (unsigned int)(len / sl->flash_pgsz)); + for (off = 0; off < len; off += sizeof(uint32_t)) { + uint32_t data; + + if ((off % sl->flash_pgsz) > (sl->flash_pgsz - 5)) { + fprintf(stdout, "\r%3u/%3u pages written", + (unsigned int)(off / sl->flash_pgsz), + (unsigned int)(len / sl->flash_pgsz)); + fflush(stdout); + } + + write_uint32((unsigned char *)&data, *(uint32_t *)(base + off)); + stlink_write_debug32(sl, addr + (uint32_t)off, data); + wait_flash_busy(sl); // wait for 'busy' bit in FLASH_SR to clear } + fprintf(stdout, "\n"); - // enable interrupt - if (!stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr)) { - stlink_write_debug32(sl, STLINK_REG_DHCSR, STLINK_REG_DHCSR_DBGKEY | - STLINK_REG_DHCSR_C_DEBUGEN | - (dhcsr&(~STLINK_REG_DHCSR_C_MASKINTS))); + // flash writes happen as 2 words at a time + if ((off / sizeof(uint32_t)) % 2 != 0) { + stlink_write_debug32(sl, addr + (uint32_t)off, + 0); // write a single word of zeros + wait_flash_busy(sl); // wait for 'busy' bit in FLASH_SR to clear + } + } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { + uint32_t val; + uint32_t flash_regs_base; + uint32_t pagesize; + + if (sl->chip_id == STLINK_CHIPID_STM32_L0 || + sl->chip_id == STLINK_CHIPID_STM32_L0_CAT5 || + sl->chip_id == STLINK_CHIPID_STM32_L0_CAT2 || + sl->chip_id == STLINK_CHIPID_STM32_L011) { + flash_regs_base = STM32L0_FLASH_REGS_ADDR; + pagesize = L0_WRITE_BLOCK_SIZE; + } else { + flash_regs_base = STM32L_FLASH_REGS_ADDR; + pagesize = L1_WRITE_BLOCK_SIZE; } - // restore DMA state - set_dma_state(sl, fl, 1); - - return(0); -} - -int stlink_write_flash( - stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t len, uint8_t eraseonly) { - size_t off; - int ret; - flash_loader_t fl; - ILOG("Attempting to write %d (%#x) bytes to stm32 address: %u (%#x)\n", len, len, addr, addr); - // check addr range is inside the flash - stlink_calculate_pagesize(sl, addr); - - if (addr < sl->flash_base) { - ELOG("addr too low %#x < %#x\n", addr, sl->flash_base); - return(-1); - } else if ((addr + len) < addr) { - ELOG("addr overruns\n"); - return(-1); - } else if ((addr + len) > (sl->flash_base + sl->flash_size)) { - ELOG("addr too high\n"); - return(-1); - } else if (addr & 1) { - ELOG("unaligned addr 0x%x\n", addr); - return(-1); - } else if (len & 1) { - WLOG("unaligned len 0x%x -- padding with zero\n", len); - len += 1; - } else if (addr & (sl->flash_pgsz - 1)) { - ELOG("addr not a multiple of current pagesize (%u bytes), not supported, " - "check page start address and compare with flash module organisation " - "in related ST reference manual of your device.\n", (unsigned)(sl->flash_pgsz)); - return(-1); + off = 0; + + if (len > pagesize) { + if (stm32l1_write_half_pages(sl, addr, base, len, pagesize) == -1) { + // this may happen on a blank device! + WLOG("\nwrite_half_pages failed == -1\n"); + } else { + off = (size_t)(len / pagesize) * pagesize; + } } - // make sure we've loaded the context with the chip details - stlink_core_id(sl); + // write remaining word in program memory + for (; off < len; off += sizeof(uint32_t)) { + uint32_t data; - // Erase each page - int page_count = 0; + if ((off % sl->flash_pgsz) > (sl->flash_pgsz - 5)) { + fprintf(stdout, "\r%3u/%3u pages written", + (unsigned int)(off / sl->flash_pgsz), + (unsigned int)(len / sl->flash_pgsz)); + fflush(stdout); + } - for (off = 0; off < len; off += stlink_calculate_pagesize(sl, addr + (uint32_t)off)) { - // addr must be an addr inside the page - if (stlink_erase_flash_page(sl, addr + (uint32_t)off) == -1) { - ELOG("Failed to erase_flash_page(%#x) == -1\n", (unsigned)(addr + off)); - return(-1); - } + write_uint32((unsigned char *)&data, *(uint32_t *)(base + off)); + stlink_write_debug32(sl, addr + (uint32_t)off, data); - ILOG("Flash page at addr: 0x%08lx erased\n", (unsigned long)(addr + off)); - page_count++; + // wait for sr.busy to be cleared + do { + stlink_read_debug32(sl, flash_regs_base + FLASH_SR_OFF, &val); + } while ((val & (1 << 0)) != 0); + + // TODO: check redo write operation } + fprintf(stdout, "\n"); + } else if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || + (sl->flash_type == STLINK_FLASH_TYPE_F1_XL)) { + int write_block_count = 0; + for (off = 0; off < len; off += sl->flash_pgsz) { + // adjust last write size + size_t size = len - off > sl->flash_pgsz ? sl->flash_pgsz : len - off; + + // unlock and set programming mode + unlock_flash_if(sl); + + DLOG("Finished unlocking flash, running loader!\n"); + + if (stlink_flash_loader_run(sl, fl, addr + (uint32_t)off, base + off, + size) == -1) { + ELOG("stlink_flash_loader_run(%#x) failed! == -1\n", + (unsigned)(addr + off)); + check_flash_error(sl); + return (-1); + } + + lock_flash(sl); + + if (sl->verbose >= 1) { + // show progress; writing procedure is slow and previous errors are + // misleading + fprintf(stdout, "\r%3u/%3u pages written", ++write_block_count, + (unsigned int)((len + sl->flash_pgsz - 1) / sl->flash_pgsz)); + fflush(stdout); + } + } + if (sl->verbose >= 1) { + fprintf(stdout, "\n"); + } + } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + for (off = 0; off < len;) { + // Program STM32H7x with 64-byte Flash words + size_t chunk = (len - off > 64) ? 64 : len - off; + memcpy(sl->q_buf, base + off, chunk); + stlink_write_mem32(sl, addr + (uint32_t)off, 64); + wait_flash_busy(sl); + + off += chunk; + + if (sl->verbose >= 1) { + // show progress + fprintf(stdout, "\r%u/%u bytes written", (unsigned int)off, + (unsigned int)len); + fflush(stdout); + } + } + if (sl->verbose >= 1) { + fprintf(stdout, "\n"); + } + } else { + return (-1); + } + + return check_flash_error(sl); +} - ILOG("Finished erasing %d pages of %u (%#x) bytes\n", - page_count, (unsigned)(sl->flash_pgsz), (unsigned)(sl->flash_pgsz)); +int stlink_flashloader_stop(stlink_t *sl, flash_loader_t *fl) { + uint32_t dhcsr; - if (eraseonly) { return(0); } + if ((sl->flash_type == STLINK_FLASH_TYPE_F4) || + (sl->flash_type == STLINK_FLASH_TYPE_F7) || + (sl->flash_type == STLINK_FLASH_TYPE_L4) || + (sl->flash_type == STLINK_FLASH_TYPE_WB) || + (sl->flash_type == STLINK_FLASH_TYPE_G0) || + (sl->flash_type == STLINK_FLASH_TYPE_G4) || + (sl->flash_type == STLINK_FLASH_TYPE_H7)) { - ret = stlink_flashloader_start(sl, &fl); - if (ret) - return ret; - ret = stlink_flashloader_write(sl, &fl, addr, base, len); - if (ret) - return ret; - ret = stlink_flashloader_stop(sl, &fl); - if (ret) - return ret; + clear_flash_cr_pg(sl, BANK_1); + if (sl->flash_type == STLINK_FLASH_TYPE_H7 && + sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { + clear_flash_cr_pg(sl, BANK_2); + } + lock_flash(sl); + } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { + uint32_t val; + uint32_t flash_regs_base; + if (sl->chip_id == STLINK_CHIPID_STM32_L0 || + sl->chip_id == STLINK_CHIPID_STM32_L0_CAT5 || + sl->chip_id == STLINK_CHIPID_STM32_L0_CAT2 || + sl->chip_id == STLINK_CHIPID_STM32_L011) { + flash_regs_base = STM32L0_FLASH_REGS_ADDR; + } else { + flash_regs_base = STM32L_FLASH_REGS_ADDR; + } + // reset lock bits + stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); + val |= (1 << 0) | (1 << 1) | (1 << 2); + stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); + } + + // enable interrupt + if (!stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr)) { + stlink_write_debug32(sl, STLINK_REG_DHCSR, + STLINK_REG_DHCSR_DBGKEY | STLINK_REG_DHCSR_C_DEBUGEN | + (dhcsr & (~STLINK_REG_DHCSR_C_MASKINTS))); + } + + // restore DMA state + set_dma_state(sl, fl, 1); + + return (0); +} + +int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t *base, + uint32_t len, uint8_t eraseonly) { + size_t off; + int ret; + flash_loader_t fl; + ILOG("Attempting to write %d (%#x) bytes to stm32 address: %u (%#x)\n", len, + len, addr, addr); + // check addr range is inside the flash + stlink_calculate_pagesize(sl, addr); + + if (addr < sl->flash_base) { + ELOG("addr too low %#x < %#x\n", addr, sl->flash_base); + return (-1); + } else if ((addr + len) < addr) { + ELOG("addr overruns\n"); + return (-1); + } else if ((addr + len) > (sl->flash_base + sl->flash_size)) { + ELOG("addr too high\n"); + return (-1); + } else if (addr & 1) { + ELOG("unaligned addr 0x%x\n", addr); + return (-1); + } else if (len & 1) { + WLOG("unaligned len 0x%x -- padding with zero\n", len); + len += 1; + } else if (addr & (sl->flash_pgsz - 1)) { + ELOG("addr not a multiple of current pagesize (%u bytes), not supported, " + "check page start address and compare with flash module organisation " + "in related ST reference manual of your device.\n", + (unsigned)(sl->flash_pgsz)); + return (-1); + } + + // make sure we've loaded the context with the chip details + stlink_core_id(sl); + + // Erase each page + int page_count = 0; + + for (off = 0; off < len; + off += stlink_calculate_pagesize(sl, addr + (uint32_t)off)) { + // addr must be an addr inside the page + if (stlink_erase_flash_page(sl, addr + (uint32_t)off) == -1) { + ELOG("Failed to erase_flash_page(%#x) == -1\n", (unsigned)(addr + off)); + return (-1); + } + + ILOG("Flash page at addr: 0x%08lx erased\n", (unsigned long)(addr + off)); + page_count++; + } + + ILOG("Finished erasing %d pages of %u (%#x) bytes\n", page_count, + (unsigned)(sl->flash_pgsz), (unsigned)(sl->flash_pgsz)); + + if (eraseonly) { + return (0); + } + + ret = stlink_flashloader_start(sl, &fl); + if (ret) + return ret; + ret = stlink_flashloader_write(sl, &fl, addr, base, len); + if (ret) + return ret; + ret = stlink_flashloader_stop(sl, &fl); + if (ret) + return ret; - return(stlink_verify_write_flash(sl, addr, base, len)); + return (stlink_verify_write_flash(sl, addr, base, len)); } // TODO: length not checked -static uint8_t stlink_parse_hex(const char* hex) { - uint8_t d[2]; - - for (int i = 0; i < 2; ++i) { - char c = *(hex + i); - - if (c >= '0' && c <= '9') { - d[i] = c - '0'; - } else if (c >= 'A' && c <= 'F') { - d[i] = c - 'A' + 10; - } else if (c >= 'a' && c <= 'f') { - d[i] = c - 'a' + 10; - } else { - return(0); // error - } +static uint8_t stlink_parse_hex(const char *hex) { + uint8_t d[2]; + + for (int i = 0; i < 2; ++i) { + char c = *(hex + i); + + if (c >= '0' && c <= '9') { + d[i] = c - '0'; + } else if (c >= 'A' && c <= 'F') { + d[i] = c - 'A' + 10; + } else if (c >= 'a' && c <= 'f') { + d[i] = c - 'a' + 10; + } else { + return (0); // error } + } - return((d[0] << 4) | (d[1])); + return ((d[0] << 4) | (d[1])); } -int stlink_parse_ihex(const char* path, uint8_t erased_pattern, uint8_t * * mem, size_t * size, - uint32_t * begin) { - int res = 0; - *begin = UINT32_MAX; - uint8_t* data = NULL; - uint32_t end = 0; - bool eof_found = false; +int stlink_parse_ihex(const char *path, uint8_t erased_pattern, uint8_t **mem, + size_t *size, uint32_t *begin) { + int res = 0; + *begin = UINT32_MAX; + uint8_t *data = NULL; + uint32_t end = 0; + bool eof_found = false; - for (int scan = 0; (res == 0) && (scan < 2); ++scan) { - // parse file two times - first to find memory range, second - to fill it - if (scan == 1) { - if (!eof_found) { - ELOG("No EoF recond\n"); - res = -1; - break; - } + for (int scan = 0; (res == 0) && (scan < 2); ++scan) { + // parse file two times - first to find memory range, second - to fill it + if (scan == 1) { + if (!eof_found) { + ELOG("No EoF recond\n"); + res = -1; + break; + } - if (*begin >= end) { - ELOG("No data found in file\n"); - res = -1; - break; - } + if (*begin >= end) { + ELOG("No data found in file\n"); + res = -1; + break; + } - *size = (end - *begin) + 1; - data = calloc(*size, 1); // use calloc to get NULL if out of memory + *size = (end - *begin) + 1; + data = calloc(*size, 1); // use calloc to get NULL if out of memory - if (!data) { - ELOG("Cannot allocate %u bytes\n", (unsigned)(*size)); - res = -1; - break; - } + if (!data) { + ELOG("Cannot allocate %u bytes\n", (unsigned)(*size)); + res = -1; + break; + } - memset(data, erased_pattern, *size); - } + memset(data, erased_pattern, *size); + } - FILE* file = fopen(path, "r"); + FILE *file = fopen(path, "r"); - if (!file) { - ELOG("Cannot open file\n"); - res = -1; - break; - } + if (!file) { + ELOG("Cannot open file\n"); + res = -1; + break; + } - uint32_t lba = 0; - char line[1 + 5 * 2 + 255 * 2 + 2]; + uint32_t lba = 0; + char line[1 + 5 * 2 + 255 * 2 + 2]; - while (fgets(line, sizeof(line), file)) { - if (line[0] == '\n' || line[0] == '\r') { continue; } // skip empty lines + while (fgets(line, sizeof(line), file)) { + if (line[0] == '\n' || line[0] == '\r') { + continue; + } // skip empty lines - if (line[0] != ':') { // no marker - wrong file format - ELOG("Wrong file format - no marker\n"); - res = -1; - break; - } + if (line[0] != ':') { // no marker - wrong file format + ELOG("Wrong file format - no marker\n"); + res = -1; + break; + } - size_t l = strlen(line); + size_t l = strlen(line); - while (l > 0 && (line[l - 1] == '\n' || line[l - 1] == '\r')) { --l; } // trim EoL + while (l > 0 && (line[l - 1] == '\n' || line[l - 1] == '\r')) { + --l; + } // trim EoL - if ((l < 11) || (l == (sizeof(line) - 1))) { // line too short or long - wrong file format - ELOG("Wrong file format - wrong line length\n"); - res = -1; - break; - } + if ((l < 11) || + (l == + (sizeof(line) - 1))) { // line too short or long - wrong file format + ELOG("Wrong file format - wrong line length\n"); + res = -1; + break; + } - uint8_t chksum = 0; // check sum + uint8_t chksum = 0; // check sum - for (size_t i = 1; i < l; i += 2) { chksum += stlink_parse_hex(line + i); } + for (size_t i = 1; i < l; i += 2) { + chksum += stlink_parse_hex(line + i); + } - if (chksum != 0) { - ELOG("Wrong file format - checksum mismatch\n"); - res = -1; - break; - } + if (chksum != 0) { + ELOG("Wrong file format - checksum mismatch\n"); + res = -1; + break; + } - uint8_t reclen = stlink_parse_hex(line + 1); + uint8_t reclen = stlink_parse_hex(line + 1); - if (((uint32_t)reclen + 5) * 2 + 1 != l) { - ELOG("Wrong file format - record length mismatch\n"); - res = -1; - break; - } + if (((uint32_t)reclen + 5) * 2 + 1 != l) { + ELOG("Wrong file format - record length mismatch\n"); + res = -1; + break; + } - uint16_t offset = ((uint16_t)stlink_parse_hex(line + 3) << 8) | - ((uint16_t)stlink_parse_hex(line + 5)); - uint8_t rectype = stlink_parse_hex(line + 7); - - switch (rectype) { - case 0: /* Data */ - if (scan == 0) { - uint32_t b = lba + offset; - uint32_t e = b + reclen - 1; - - if (b < *begin) { *begin = b; } - - if (e > end) { end = e; } - } else { - for (uint8_t i = 0; i < reclen; ++i) { - uint8_t b = stlink_parse_hex(line + 9 + i * 2); - uint32_t addr = lba + offset + i; - - if (addr >= *begin && addr <= end) { data[addr - *begin] = b; } - } - } - break; - case 1: /* EoF */ - eof_found = true; - break; - case 2: /* Extended Segment Address, unexpected */ - res = -1; - break; - case 3: /* Start Segment Address, unexpected */ - res = -1; - break; - case 4: /* Extended Linear Address */ - if (reclen == 2) { - lba = ((uint32_t)stlink_parse_hex(line + 9) << 24) | - ((uint32_t)stlink_parse_hex(line + 11) << 16); - } else { - ELOG("Wrong file format - wrong LBA length\n"); - res = -1; - } - break; - case 5: /* Start Linear Address - expected, but ignore */ - break; - default: - ELOG("Wrong file format - unexpected record type %d\n", rectype); - res = -1; - } + uint16_t offset = ((uint16_t)stlink_parse_hex(line + 3) << 8) | + ((uint16_t)stlink_parse_hex(line + 5)); + uint8_t rectype = stlink_parse_hex(line + 7); - if (res != 0) { break; } - } + switch (rectype) { + case 0: /* Data */ + if (scan == 0) { + uint32_t b = lba + offset; + uint32_t e = b + reclen - 1; - fclose(file); - } + if (b < *begin) { + *begin = b; + } - if (res == 0) { - *mem = data; - } else { - free(data); - } + if (e > end) { + end = e; + } + } else { + for (uint8_t i = 0; i < reclen; ++i) { + uint8_t b = stlink_parse_hex(line + 9 + i * 2); + uint32_t addr = lba + offset + i; - return(res); -} + if (addr >= *begin && addr <= end) { + data[addr - *begin] = b; + } + } + } + break; + case 1: /* EoF */ + eof_found = true; + break; + case 2: /* Extended Segment Address, unexpected */ + res = -1; + break; + case 3: /* Start Segment Address, unexpected */ + res = -1; + break; + case 4: /* Extended Linear Address */ + if (reclen == 2) { + lba = ((uint32_t)stlink_parse_hex(line + 9) << 24) | + ((uint32_t)stlink_parse_hex(line + 11) << 16); + } else { + ELOG("Wrong file format - wrong LBA length\n"); + res = -1; + } + break; + case 5: /* Start Linear Address - expected, but ignore */ + break; + default: + ELOG("Wrong file format - unexpected record type %d\n", rectype); + res = -1; + } -uint8_t stlink_get_erased_pattern(stlink_t *sl) { - if (sl->flash_type == STLINK_FLASH_TYPE_L0) { - return(0x00); - } else { - return(0xff); + if (res != 0) { + break; + } } -} -int stlink_mwrite_flash(stlink_t *sl, uint8_t* data, uint32_t length, stm32_addr_t addr) { - /* Write the block in flash at addr */ - int err; - unsigned int num_empty, idx; - uint8_t erased_pattern = stlink_get_erased_pattern(sl); + fclose(file); + } - /* - * This optimisation may cause unexpected garbage data remaining. - * Therfore it is turned off by default. - */ - if (sl->opt) { - idx = (unsigned int)length; + if (res == 0) { + *mem = data; + } else { + free(data); + } + + return (res); +} - for (num_empty = 0; num_empty != length; ++num_empty) - if (data[--idx] != erased_pattern) { break; } +uint8_t stlink_get_erased_pattern(stlink_t *sl) { + if (sl->flash_type == STLINK_FLASH_TYPE_L0) { + return (0x00); + } else { + return (0xff); + } +} + +int stlink_mwrite_flash(stlink_t *sl, uint8_t *data, uint32_t length, + stm32_addr_t addr) { + /* Write the block in flash at addr */ + int err; + unsigned int num_empty, idx; + uint8_t erased_pattern = stlink_get_erased_pattern(sl); + + /* + * This optimisation may cause unexpected garbage data remaining. + * Therfore it is turned off by default. + */ + if (sl->opt) { + idx = (unsigned int)length; + + for (num_empty = 0; num_empty != length; ++num_empty) + if (data[--idx] != erased_pattern) { + break; + } - num_empty -= (num_empty & 3); // Round down to words + num_empty -= (num_empty & 3); // Round down to words - if (num_empty != 0) { - ILOG("Ignoring %d bytes of 0x%02x at end of file\n", num_empty, erased_pattern); - } - } else { - num_empty = 0; + if (num_empty != 0) { + ILOG("Ignoring %d bytes of 0x%02x at end of file\n", num_empty, + erased_pattern); } + } else { + num_empty = 0; + } - /* - * TODO: investigate a kind of weird behaviour here: - * If the file is identified to be all-empty and four-bytes aligned, - * still flash the whole file even if ignoring message is printed. - */ - err = stlink_write_flash(sl, addr, data, - (num_empty == length) ? (uint32_t)length : (uint32_t)length - num_empty, - num_empty == length); - stlink_fwrite_finalize(sl, addr); - return(err); + /* + * TODO: investigate a kind of weird behaviour here: + * If the file is identified to be all-empty and four-bytes aligned, + * still flash the whole file even if ignoring message is printed. + */ + err = stlink_write_flash(sl, addr, data, + (num_empty == length) ? (uint32_t)length + : (uint32_t)length - num_empty, + num_empty == length); + stlink_fwrite_finalize(sl, addr); + return (err); } /** @@ -3645,49 +3791,53 @@ int stlink_mwrite_flash(stlink_t *sl, uint8_t* data, uint32_t length, stm32_addr * @param addr where to start writing * @return 0 on success, -ve on failure. */ -int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr) { - /* Write the file in flash at addr */ - int err; - unsigned int num_empty, idx; - uint8_t erased_pattern = stlink_get_erased_pattern(sl); - mapped_file_t mf = MAPPED_FILE_INITIALIZER; - - if (map_file(&mf, path) == -1) { - ELOG("map_file() == -1\n"); - return(-1); +int stlink_fwrite_flash(stlink_t *sl, const char *path, stm32_addr_t addr) { + /* Write the file in flash at addr */ + int err; + unsigned int num_empty, idx; + uint8_t erased_pattern = stlink_get_erased_pattern(sl); + mapped_file_t mf = MAPPED_FILE_INITIALIZER; + + if (map_file(&mf, path) == -1) { + ELOG("map_file() == -1\n"); + return (-1); + } + + printf("file %s ", path); + md5_calculate(&mf); + stlink_checksum(&mf); + + if (sl->opt) { + idx = (unsigned int)mf.len; + + for (num_empty = 0; num_empty != mf.len; ++num_empty) { + if (mf.base[--idx] != erased_pattern) { + break; + } } - printf("file %s ", path); - md5_calculate(&mf); - stlink_checksum(&mf); - - if (sl->opt) { - idx = (unsigned int)mf.len; + num_empty -= (num_empty & 3); // round down to words - for (num_empty = 0; num_empty != mf.len; ++num_empty) { - if (mf.base[--idx] != erased_pattern) { break; } - } - - num_empty -= (num_empty & 3); // round down to words - - if (num_empty != 0) { - ILOG("Ignoring %d bytes of 0x%02x at end of file\n", num_empty, erased_pattern); - } - } else { - num_empty = 0; + if (num_empty != 0) { + ILOG("Ignoring %d bytes of 0x%02x at end of file\n", num_empty, + erased_pattern); } + } else { + num_empty = 0; + } - /* - * TODO: investigate a kind of weird behaviour here: - * If the file is identified to be all-empty and four-bytes aligned, - * still flash the whole file even if ignoring message is printed. - */ - err = stlink_write_flash(sl, addr, mf.base, - (num_empty == mf.len) ? (uint32_t)mf.len : (uint32_t)mf.len - num_empty, - num_empty == mf.len); - stlink_fwrite_finalize(sl, addr); - unmap_file(&mf); - return(err); + /* + * TODO: investigate a kind of weird behaviour here: + * If the file is identified to be all-empty and four-bytes aligned, + * still flash the whole file even if ignoring message is printed. + */ + err = stlink_write_flash(sl, addr, mf.base, + (num_empty == mf.len) ? (uint32_t)mf.len + : (uint32_t)mf.len - num_empty, + num_empty == mf.len); + stlink_fwrite_finalize(sl, addr); + unmap_file(&mf); + return (err); } /** @@ -3697,35 +3847,35 @@ int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr) { * @param base option bytes to write * @return 0 on success, -ve on failure. */ -static int stlink_write_option_bytes_gx( - stlink_t *sl, uint8_t* base, stm32_addr_t addr, uint32_t len) { - /* Write options bytes */ - uint32_t val; - int ret = 0; - (void)len; - uint32_t data; +static int stlink_write_option_bytes_gx(stlink_t *sl, uint8_t *base, + stm32_addr_t addr, uint32_t len) { + /* Write options bytes */ + uint32_t val; + int ret = 0; + (void)len; + uint32_t data; - clear_flash_error(sl); + clear_flash_error(sl); - write_uint32((unsigned char*)&data, *(uint32_t*)(base)); - WLOG("Writing option bytes %#10x to %#10x\n", data, addr); - stlink_write_debug32(sl, STM32Gx_FLASH_OPTR, data); + write_uint32((unsigned char *)&data, *(uint32_t *)(base)); + WLOG("Writing option bytes %#10x to %#10x\n", data, addr); + stlink_write_debug32(sl, STM32Gx_FLASH_OPTR, data); - // Set Options Start bit - stlink_read_debug32(sl, STM32Gx_FLASH_CR, &val); - val |= (1 << STM32Gx_FLASH_CR_OPTSTRT); - stlink_write_debug32(sl, STM32Gx_FLASH_CR, val); + // Set Options Start bit + stlink_read_debug32(sl, STM32Gx_FLASH_CR, &val); + val |= (1 << STM32Gx_FLASH_CR_OPTSTRT); + stlink_write_debug32(sl, STM32Gx_FLASH_CR, val); - wait_flash_busy(sl); + wait_flash_busy(sl); - ret = check_flash_error(sl); + ret = check_flash_error(sl); - // Reload options - stlink_read_debug32(sl, STM32Gx_FLASH_CR, &val); - val |= (1 << STM32Gx_FLASH_CR_OBL_LAUNCH); - stlink_write_debug32(sl, STM32Gx_FLASH_CR, val); + // Reload options + stlink_read_debug32(sl, STM32Gx_FLASH_CR, &val); + val |= (1 << STM32Gx_FLASH_CR_OBL_LAUNCH); + stlink_write_debug32(sl, STM32Gx_FLASH_CR, val); - return(ret); + return (ret); } /** @@ -3735,36 +3885,39 @@ static int stlink_write_option_bytes_gx( * @param base option bytes to write * @return 0 on success, -ve on failure. */ -static int stlink_write_option_bytes_l0( - stlink_t *sl, uint8_t* base, stm32_addr_t addr, uint32_t len) { - uint32_t flash_base = get_stm32l0_flash_base(sl); - uint32_t val; - uint32_t data; - int ret = 0; - - // Clear errors - clear_flash_error(sl); +static int stlink_write_option_bytes_l0(stlink_t *sl, uint8_t *base, + stm32_addr_t addr, uint32_t len) { + uint32_t flash_base = get_stm32l0_flash_base(sl); + uint32_t val; + uint32_t data; + int ret = 0; - while (len != 0) { - write_uint32((unsigned char*)&data, *(uint32_t*)(base)); // write options bytes + // Clear errors + clear_flash_error(sl); - WLOG("Writing option bytes %#10x to %#10x\n", data, addr); - stlink_write_debug32(sl, addr, data); - wait_flash_busy(sl); + while (len != 0) { + write_uint32((unsigned char *)&data, + *(uint32_t *)(base)); // write options bytes - if ((ret = check_flash_error(sl))) { break; } + WLOG("Writing option bytes %#10x to %#10x\n", data, addr); + stlink_write_debug32(sl, addr, data); + wait_flash_busy(sl); - len -= 4; - addr += 4; - base += 4; + if ((ret = check_flash_error(sl))) { + break; } - // Reload options - stlink_read_debug32(sl, flash_base + FLASH_PECR_OFF, &val); - val |= (1 << STM32L0_FLASH_OBL_LAUNCH); - stlink_write_debug32(sl, flash_base + FLASH_PECR_OFF, val); + len -= 4; + addr += 4; + base += 4; + } + + // Reload options + stlink_read_debug32(sl, flash_base + FLASH_PECR_OFF, &val); + val |= (1 << STM32L0_FLASH_OBL_LAUNCH); + stlink_write_debug32(sl, flash_base + FLASH_PECR_OFF, val); - return(ret); + return (ret); } /** @@ -3774,67 +3927,67 @@ static int stlink_write_option_bytes_l0( * @param base option bytes to write * @return 0 on success, -ve on failure. */ -static int stlink_write_option_bytes_l4( - stlink_t *sl, uint8_t* base, stm32_addr_t addr, uint32_t len) { +static int stlink_write_option_bytes_l4(stlink_t *sl, uint8_t *base, + stm32_addr_t addr, uint32_t len) { - uint32_t val; - int ret = 0; - (void)addr; - (void)len; + uint32_t val; + int ret = 0; + (void)addr; + (void)len; - // Clear errors - clear_flash_error(sl); + // Clear errors + clear_flash_error(sl); - // write options bytes - uint32_t data; - write_uint32((unsigned char*)&data, *(uint32_t*)(base)); - WLOG("Writing option bytes 0x%04x\n", data); - stlink_write_debug32(sl, STM32L4_FLASH_OPTR, data); + // write options bytes + uint32_t data; + write_uint32((unsigned char *)&data, *(uint32_t *)(base)); + WLOG("Writing option bytes 0x%04x\n", data); + stlink_write_debug32(sl, STM32L4_FLASH_OPTR, data); - // set options start bit - stlink_read_debug32(sl, STM32L4_FLASH_CR, &val); - val |= (1 << STM32L4_FLASH_CR_OPTSTRT); - stlink_write_debug32(sl, STM32L4_FLASH_CR, val); + // set options start bit + stlink_read_debug32(sl, STM32L4_FLASH_CR, &val); + val |= (1 << STM32L4_FLASH_CR_OPTSTRT); + stlink_write_debug32(sl, STM32L4_FLASH_CR, val); - wait_flash_busy(sl); - ret = check_flash_error(sl); + wait_flash_busy(sl); + ret = check_flash_error(sl); - // apply options bytes immediate - stlink_read_debug32(sl, STM32L4_FLASH_CR, &val); - val |= (1 << STM32L4_FLASH_CR_OBL_LAUNCH); - stlink_write_debug32(sl, STM32L4_FLASH_CR, val); + // apply options bytes immediate + stlink_read_debug32(sl, STM32L4_FLASH_CR, &val); + val |= (1 << STM32L4_FLASH_CR_OBL_LAUNCH); + stlink_write_debug32(sl, STM32L4_FLASH_CR, val); - return(ret); + return (ret); } - /** * Write option bytes * @param sl * @param option_byte value to write * @return 0 on success, -ve on failure. */ -static int stlink_write_option_bytes_f4( - stlink_t *sl, uint8_t* base, stm32_addr_t addr, uint32_t len) { - uint32_t option_byte; - int ret = 0; - (void)addr; - (void)len; - - // Clear errors - clear_flash_error(sl); +static int stlink_write_option_bytes_f4(stlink_t *sl, uint8_t *base, + stm32_addr_t addr, uint32_t len) { + uint32_t option_byte; + int ret = 0; + (void)addr; + (void)len; - write_uint32((unsigned char*)&option_byte, *(uint32_t*)(base)); + // Clear errors + clear_flash_error(sl); - // write option byte, ensuring we dont lock opt, and set strt bit - stlink_write_debug32(sl, FLASH_F4_OPTCR, - (option_byte & ~(1 << FLASH_F4_OPTCR_LOCK)) | (1 << FLASH_F4_OPTCR_START)); + write_uint32((unsigned char *)&option_byte, *(uint32_t *)(base)); - wait_flash_busy(sl); - ret = check_flash_error(sl); + // write option byte, ensuring we dont lock opt, and set strt bit + stlink_write_debug32(sl, FLASH_F4_OPTCR, + (option_byte & ~(1 << FLASH_F4_OPTCR_LOCK)) | + (1 << FLASH_F4_OPTCR_START)); - // option bytes are reloaded at reset only, no obl. */ - return(ret); + wait_flash_busy(sl); + ret = check_flash_error(sl); + + // option bytes are reloaded at reset only, no obl. */ + return (ret); } /** @@ -3843,47 +3996,54 @@ static int stlink_write_option_bytes_f4( * @param option_byte value to write * @return 0 on success, -ve on failure. */ -static int stlink_write_option_bytes_f7(stlink_t *sl, uint8_t* base, stm32_addr_t addr, uint32_t len) { - uint32_t option_byte; - int ret = 0; +static int stlink_write_option_bytes_f7(stlink_t *sl, uint8_t *base, + stm32_addr_t addr, uint32_t len) { + uint32_t option_byte; + int ret = 0; - // Clear errors - clear_flash_error(sl); + // Clear errors + clear_flash_error(sl); - ILOG("Asked to write option byte %#10x to %#010x.\n", *(uint32_t*) (base), addr); - write_uint32((unsigned char*) &option_byte, *(uint32_t*) (base)); - ILOG("Write %d option bytes %#010x to %#010x!\n", len, option_byte, addr); + ILOG("Asked to write option byte %#10x to %#010x.\n", *(uint32_t *)(base), + addr); + write_uint32((unsigned char *)&option_byte, *(uint32_t *)(base)); + ILOG("Write %d option bytes %#010x to %#010x!\n", len, option_byte, addr); - if ( addr == 0 ) { - addr = FLASH_F7_OPTCR; - ILOG("No address provided, using %#10x\n", addr); - } + if (addr == 0) { + addr = FLASH_F7_OPTCR; + ILOG("No address provided, using %#10x\n", addr); + } - if ( addr == FLASH_F7_OPTCR ) { - /* write option byte, ensuring we dont lock opt, and set strt bit */ - stlink_write_debug32(sl, FLASH_F7_OPTCR, (option_byte & ~(1 << FLASH_F7_OPTCR_LOCK)) | (1 << FLASH_F7_OPTCR_START)); - } else if ( addr == FLASH_F7_OPTCR1 ) { - // Read FLASH_F7_OPTCR - uint32_t oldvalue; - stlink_read_debug32(sl, FLASH_F7_OPTCR, &oldvalue); - /* write option byte */ - stlink_write_debug32(sl, FLASH_F7_OPTCR1, option_byte); - // Write FLASH_F7_OPTCR lock and start address - stlink_write_debug32(sl, FLASH_F7_OPTCR, (oldvalue & ~(1 << FLASH_F7_OPTCR_LOCK)) | (1 << FLASH_F7_OPTCR_START)); - } else { - WLOG("WIP: write %#010x to address %#010x\n", option_byte, addr); - stlink_write_debug32(sl, addr, option_byte); - } + if (addr == FLASH_F7_OPTCR) { + /* write option byte, ensuring we dont lock opt, and set strt bit */ + stlink_write_debug32(sl, FLASH_F7_OPTCR, + (option_byte & ~(1 << FLASH_F7_OPTCR_LOCK)) | + (1 << FLASH_F7_OPTCR_START)); + } else if (addr == FLASH_F7_OPTCR1) { + // Read FLASH_F7_OPTCR + uint32_t oldvalue; + stlink_read_debug32(sl, FLASH_F7_OPTCR, &oldvalue); + /* write option byte */ + stlink_write_debug32(sl, FLASH_F7_OPTCR1, option_byte); + // Write FLASH_F7_OPTCR lock and start address + stlink_write_debug32(sl, FLASH_F7_OPTCR, + (oldvalue & ~(1 << FLASH_F7_OPTCR_LOCK)) | + (1 << FLASH_F7_OPTCR_START)); + } else { + WLOG("WIP: write %#010x to address %#010x\n", option_byte, addr); + stlink_write_debug32(sl, addr, option_byte); + } - wait_flash_busy(sl); + wait_flash_busy(sl); - ret = check_flash_error(sl); - if (!ret) - ILOG("Wrote %d option bytes %#010x to %#010x!\n", len, *(uint32_t*) base, addr); + ret = check_flash_error(sl); + if (!ret) + ILOG("Wrote %d option bytes %#010x to %#010x!\n", len, *(uint32_t *)base, + addr); - /* option bytes are reloaded at reset only, no obl. */ + /* option bytes are reloaded at reset only, no obl. */ - return ret; + return ret; } /** @@ -3894,64 +4054,67 @@ static int stlink_write_option_bytes_f7(stlink_t *sl, uint8_t* base, stm32_addr_ * @param len number of bytes to write (must be multiple of 4) * @return 0 on success, -ve on failure. */ -static int stlink_write_option_bytes_h7( - stlink_t *sl, uint8_t* base, stm32_addr_t addr, uint32_t len) { - uint32_t val; - uint32_t data; - - // Wait until previous flash option has completed - wait_flash_busy(sl); - - // Clear previous error - stlink_write_debug32(sl, FLASH_H7_OPTCCR, 1 << FLASH_H7_OPTCCR_CLR_OPTCHANGEERR); - - while (len != 0) { - switch (addr) { - case FLASH_H7_REGS_ADDR + 0x20: // FLASH_OPTSR_PRG - case FLASH_H7_REGS_ADDR + 0x2c: // FLASH_PRAR_PRG1 - case FLASH_H7_REGS_ADDR + 0x34: // FLASH_SCAR_PRG1 - case FLASH_H7_REGS_ADDR + 0x3c: // FLASH_WPSN_PRG1 - case FLASH_H7_REGS_ADDR + 0x44: // FLASH_BOOT_PRG - /* Write to FLASH_xxx_PRG registers */ - write_uint32((unsigned char*)&data, *(uint32_t*)(base)); // write options bytes - - WLOG("Writing option bytes %#10x to %#10x\n", data, addr); - - /* Skip if the value in the CUR register is identical */ - stlink_read_debug32(sl, addr - 4, &val); - if (val == data) { - break; - } - - /* Write new option byte values and start modification */ - stlink_write_debug32(sl, addr, data); - stlink_read_debug32(sl, FLASH_H7_OPTCR, &val); - val |= (1 << FLASH_H7_OPTCR_OPTSTART); - stlink_write_debug32(sl, FLASH_H7_OPTCR, val); - - /* Wait for the option bytes modification to complete */ - do { - stlink_read_debug32(sl, FLASH_H7_OPTSR_CUR, &val); - } while ((val & (1 << FLASH_H7_OPTSR_OPT_BUSY)) != 0); - - /* Check for errors */ - if ((val & (1 << FLASH_H7_OPTSR_OPTCHANGEERR)) != 0) { - stlink_write_debug32(sl, FLASH_H7_OPTCCR, 1 << FLASH_H7_OPTCCR_CLR_OPTCHANGEERR); - return -1; - } - break; - - default: - /* Skip non-programmable registers */ - break; - } +static int stlink_write_option_bytes_h7(stlink_t *sl, uint8_t *base, + stm32_addr_t addr, uint32_t len) { + uint32_t val; + uint32_t data; + + // Wait until previous flash option has completed + wait_flash_busy(sl); + + // Clear previous error + stlink_write_debug32(sl, FLASH_H7_OPTCCR, + 1 << FLASH_H7_OPTCCR_CLR_OPTCHANGEERR); + + while (len != 0) { + switch (addr) { + case FLASH_H7_REGS_ADDR + 0x20: // FLASH_OPTSR_PRG + case FLASH_H7_REGS_ADDR + 0x2c: // FLASH_PRAR_PRG1 + case FLASH_H7_REGS_ADDR + 0x34: // FLASH_SCAR_PRG1 + case FLASH_H7_REGS_ADDR + 0x3c: // FLASH_WPSN_PRG1 + case FLASH_H7_REGS_ADDR + 0x44: // FLASH_BOOT_PRG + /* Write to FLASH_xxx_PRG registers */ + write_uint32((unsigned char *)&data, + *(uint32_t *)(base)); // write options bytes + + WLOG("Writing option bytes %#10x to %#10x\n", data, addr); + + /* Skip if the value in the CUR register is identical */ + stlink_read_debug32(sl, addr - 4, &val); + if (val == data) { + break; + } + + /* Write new option byte values and start modification */ + stlink_write_debug32(sl, addr, data); + stlink_read_debug32(sl, FLASH_H7_OPTCR, &val); + val |= (1 << FLASH_H7_OPTCR_OPTSTART); + stlink_write_debug32(sl, FLASH_H7_OPTCR, val); + + /* Wait for the option bytes modification to complete */ + do { + stlink_read_debug32(sl, FLASH_H7_OPTSR_CUR, &val); + } while ((val & (1 << FLASH_H7_OPTSR_OPT_BUSY)) != 0); + + /* Check for errors */ + if ((val & (1 << FLASH_H7_OPTSR_OPTCHANGEERR)) != 0) { + stlink_write_debug32(sl, FLASH_H7_OPTCCR, + 1 << FLASH_H7_OPTCCR_CLR_OPTCHANGEERR); + return -1; + } + break; - len -= 4; - addr += 4; - base += 4; + default: + /* Skip non-programmable registers */ + break; } - return 0; + len -= 4; + addr += 4; + base += 4; + } + + return 0; } /** @@ -3960,8 +4123,9 @@ static int stlink_write_option_bytes_h7( * @param option_byte value to write * @return 0 on success, -ve on failure. */ -int stlink_read_option_control_register_Gx(stlink_t *sl, uint32_t* option_byte) { - return stlink_read_debug32(sl, STM32Gx_FLASH_OPTR, option_byte); +int stlink_read_option_control_register_Gx(stlink_t *sl, + uint32_t *option_byte) { + return stlink_read_debug32(sl, STM32Gx_FLASH_OPTR, option_byte); } /** @@ -3970,8 +4134,8 @@ int stlink_read_option_control_register_Gx(stlink_t *sl, uint32_t* option_byte) * @param option_byte value to write * @return 0 on success, -ve on failure. */ -int stlink_read_option_bytes_Gx(stlink_t *sl, uint32_t* option_byte) { - return stlink_read_option_control_register_Gx(sl, option_byte); +int stlink_read_option_bytes_Gx(stlink_t *sl, uint32_t *option_byte) { + return stlink_read_option_control_register_Gx(sl, option_byte); } /** @@ -3980,8 +4144,9 @@ int stlink_read_option_bytes_Gx(stlink_t *sl, uint32_t* option_byte) { * @param option_byte value to write * @return 0 on success, -ve on failure. */ -int stlink_read_option_control_register_f2(stlink_t *sl, uint32_t* option_byte) { - return stlink_read_debug32(sl, FLASH_F2_OPT_CR, option_byte); +int stlink_read_option_control_register_f2(stlink_t *sl, + uint32_t *option_byte) { + return stlink_read_debug32(sl, FLASH_F2_OPT_CR, option_byte); } /** @@ -3990,8 +4155,8 @@ int stlink_read_option_control_register_f2(stlink_t *sl, uint32_t* option_byte) * @param option_byte value to write * @return 0 on success, -ve on failure. */ -int stlink_read_option_bytes_f2(stlink_t *sl, uint32_t* option_byte) { - return stlink_read_option_control_register_f2(sl, option_byte); +int stlink_read_option_bytes_f2(stlink_t *sl, uint32_t *option_byte) { + return stlink_read_option_control_register_f2(sl, option_byte); } /** @@ -4000,8 +4165,9 @@ int stlink_read_option_bytes_f2(stlink_t *sl, uint32_t* option_byte) { * @param option_byte value to read * @return 0 on success, -ve on failure. */ -int stlink_read_option_control_register_f4(stlink_t *sl, uint32_t* option_byte) { - return stlink_read_debug32(sl, FLASH_F4_OPTCR, option_byte); +int stlink_read_option_control_register_f4(stlink_t *sl, + uint32_t *option_byte) { + return stlink_read_debug32(sl, FLASH_F4_OPTCR, option_byte); } /** @@ -4010,8 +4176,8 @@ int stlink_read_option_control_register_f4(stlink_t *sl, uint32_t* option_byte) * @param option_byte value to read * @return 0 on success, -ve on failure. */ -int stlink_read_option_bytes_f4(stlink_t *sl, uint32_t* option_byte) { - return stlink_read_option_control_register_f4(sl, option_byte); +int stlink_read_option_bytes_f4(stlink_t *sl, uint32_t *option_byte) { + return stlink_read_option_control_register_f4(sl, option_byte); } /** @@ -4020,9 +4186,10 @@ int stlink_read_option_bytes_f4(stlink_t *sl, uint32_t* option_byte) { * @param option_byte value to read * @return 0 on success, -ve on failure. */ -int stlink_read_option_control_register_f7(stlink_t *sl, uint32_t* option_byte) { - DLOG("@@@@ Read option control register byte from %#10x\n", FLASH_F7_OPTCR); - return stlink_read_debug32(sl, FLASH_F7_OPTCR, option_byte); +int stlink_read_option_control_register_f7(stlink_t *sl, + uint32_t *option_byte) { + DLOG("@@@@ Read option control register byte from %#10x\n", FLASH_F7_OPTCR); + return stlink_read_debug32(sl, FLASH_F7_OPTCR, option_byte); } /** @@ -4031,9 +4198,11 @@ int stlink_read_option_control_register_f7(stlink_t *sl, uint32_t* option_byte) * @param option_byte value to read * @return 0 on success, -ve on failure. */ -int stlink_read_option_control_register1_f7(stlink_t *sl, uint32_t* option_byte) { - DLOG("@@@@ Read option control register 1 byte from %#10x\n", FLASH_F7_OPTCR1); - return stlink_read_debug32(sl, FLASH_F7_OPTCR1, option_byte); +int stlink_read_option_control_register1_f7(stlink_t *sl, + uint32_t *option_byte) { + DLOG("@@@@ Read option control register 1 byte from %#10x\n", + FLASH_F7_OPTCR1); + return stlink_read_debug32(sl, FLASH_F7_OPTCR1, option_byte); } /** @@ -4042,9 +4211,9 @@ int stlink_read_option_control_register1_f7(stlink_t *sl, uint32_t* option_byte) * @param option_byte value to read * @return 0 on success, -ve on failure. */ -int stlink_read_option_bytes_boot_add_f7(stlink_t *sl, uint32_t* option_byte) { - DLOG("@@@@ Read option byte boot address\n"); - return stlink_read_option_control_register1_f7(sl, option_byte); +int stlink_read_option_bytes_boot_add_f7(stlink_t *sl, uint32_t *option_byte) { + DLOG("@@@@ Read option byte boot address\n"); + return stlink_read_option_control_register1_f7(sl, option_byte); } /** @@ -4056,18 +4225,22 @@ int stlink_read_option_bytes_boot_add_f7(stlink_t *sl, uint32_t* option_byte) { * Since multiple bytes can be read, we read and print all but one here * and then return the last one just like other devices */ -int stlink_read_option_bytes_f7(stlink_t *sl, uint32_t* option_byte) { - int err = -1; - for (uint8_t counter = 0; counter < (sl->option_size / 4 - 1); counter++) { - err = stlink_read_debug32(sl, sl->option_base + counter * sizeof(uint32_t), option_byte); - if (err == -1) { - return err; - } else { - printf("%08x\n", *option_byte); - } +int stlink_read_option_bytes_f7(stlink_t *sl, uint32_t *option_byte) { + int err = -1; + for (uint32_t counter = 0; counter < (sl->option_size / 4 - 1); counter++) { + err = stlink_read_debug32(sl, sl->option_base + counter * sizeof(uint32_t), + option_byte); + if (err == -1) { + return err; + } else { + printf("%08x\n", *option_byte); } + } - return stlink_read_debug32(sl, sl->option_base + (uint32_t) (sl->option_size / 4 - 1) * sizeof(uint32_t), option_byte); + return stlink_read_debug32( + sl, + sl->option_base + (uint32_t)(sl->option_size / 4 - 1) * sizeof(uint32_t), + option_byte); } /** @@ -4076,9 +4249,9 @@ int stlink_read_option_bytes_f7(stlink_t *sl, uint32_t* option_byte) { * @param option_byte option value * @return 0 on success, -ve on failure. */ -int stlink_read_option_bytes_generic(stlink_t *sl, uint32_t* option_byte) { - DLOG("@@@@ Read option bytes boot address from %#10x\n", sl->option_base); - return stlink_read_debug32(sl, sl->option_base, option_byte); +int stlink_read_option_bytes_generic(stlink_t *sl, uint32_t *option_byte) { + DLOG("@@@@ Read option bytes boot address from %#10x\n", sl->option_base); + return stlink_read_debug32(sl, sl->option_base, option_byte); } /** @@ -4087,7 +4260,8 @@ int stlink_read_option_bytes_generic(stlink_t *sl, uint32_t* option_byte) { * @param option_byte value to read * @return 0 on success, -ve on failure. */ -//int stlink_read_option_bytes_boot_add_generic(stlink_t *sl, uint32_t* option_byte) { +// int stlink_read_option_bytes_boot_add_generic(stlink_t *sl, uint32_t* +// option_byte) { // DLOG("@@@@ Read option bytes boot address from %#10x\n", sl->option_base); // return stlink_read_debug32(sl, sl->option_base, option_byte); //} @@ -4098,9 +4272,11 @@ int stlink_read_option_bytes_generic(stlink_t *sl, uint32_t* option_byte) { * @param option_byte value to read * @return 0 on success, -ve on failure. */ -//int stlink_read_option_control_register_generic(stlink_t *sl, uint32_t* option_byte) { -// DLOG("@@@@ Read option control register byte from %#10x\n", sl->option_base); -// return stlink_read_debug32(sl, sl->option_base, option_byte); +// int stlink_read_option_control_register_generic(stlink_t *sl, uint32_t* +// option_byte) { +// DLOG("@@@@ Read option control register byte from %#10x\n", +// sl->option_base); return stlink_read_debug32(sl, sl->option_base, +// option_byte); //} /** @@ -4109,9 +4285,11 @@ int stlink_read_option_bytes_generic(stlink_t *sl, uint32_t* option_byte) { * @param option_byte value to read * @return 0 on success, -ve on failure. */ -//int stlink_read_option_control_register1_generic(stlink_t *sl, uint32_t* option_byte) { -// DLOG("@@@@ Read option control register 1 byte from %#10x\n", sl->option_base); -// return stlink_read_debug32(sl, sl->option_base, option_byte); +// int stlink_read_option_control_register1_generic(stlink_t *sl, uint32_t* +// option_byte) { +// DLOG("@@@@ Read option control register 1 byte from %#10x\n", +// sl->option_base); return stlink_read_debug32(sl, sl->option_base, +// option_byte); //} /** @@ -4120,28 +4298,28 @@ int stlink_read_option_bytes_generic(stlink_t *sl, uint32_t* option_byte) { * @param option_byte option value * @return 0 on success, -ve on failure. */ -int stlink_read_option_bytes32(stlink_t *sl, uint32_t* option_byte) { - if (sl->option_base == 0) { - ELOG("Option bytes read is currently not supported for connected chip\n"); - return(-1); - } - - switch (sl->chip_id) { - case STLINK_CHIPID_STM32_F2: - return stlink_read_option_bytes_f2(sl, option_byte); - case STLINK_CHIPID_STM32_F4: - case STLINK_CHIPID_STM32_F446: - return stlink_read_option_bytes_f4(sl, option_byte); - case STLINK_CHIPID_STM32_F7XXXX: - return stlink_read_option_bytes_f7(sl, option_byte); - case STLINK_CHIPID_STM32_G0_CAT1: - case STLINK_CHIPID_STM32_G0_CAT2: - case STLINK_CHIPID_STM32_G4_CAT2: - case STLINK_CHIPID_STM32_G4_CAT3: - return stlink_read_option_bytes_Gx(sl, option_byte); - default: - return stlink_read_option_bytes_generic(sl, option_byte); - } +int stlink_read_option_bytes32(stlink_t *sl, uint32_t *option_byte) { + if (sl->option_base == 0) { + ELOG("Option bytes read is currently not supported for connected chip\n"); + return (-1); + } + + switch (sl->chip_id) { + case STLINK_CHIPID_STM32_F2: + return stlink_read_option_bytes_f2(sl, option_byte); + case STLINK_CHIPID_STM32_F4: + case STLINK_CHIPID_STM32_F446: + return stlink_read_option_bytes_f4(sl, option_byte); + case STLINK_CHIPID_STM32_F7XXXX: + return stlink_read_option_bytes_f7(sl, option_byte); + case STLINK_CHIPID_STM32_G0_CAT1: + case STLINK_CHIPID_STM32_G0_CAT2: + case STLINK_CHIPID_STM32_G4_CAT2: + case STLINK_CHIPID_STM32_G4_CAT3: + return stlink_read_option_bytes_Gx(sl, option_byte); + default: + return stlink_read_option_bytes_generic(sl, option_byte); + } } /** @@ -4150,20 +4328,20 @@ int stlink_read_option_bytes32(stlink_t *sl, uint32_t* option_byte) { * @param option_byte option value * @return 0 on success, -ve on failure. */ -int stlink_read_option_bytes_boot_add32(stlink_t *sl, uint32_t* option_byte) -{ - if (sl->option_base == 0) { - ELOG("Option bytes boot address read is currently not supported for connected chip\n"); - return -1; - } - - switch (sl->chip_id) { - case STLINK_CHIPID_STM32_F7XXXX: - return stlink_read_option_bytes_boot_add_f7(sl, option_byte); - default: - return -1; - //return stlink_read_option_bytes_boot_add_generic(sl, option_byte); - } +int stlink_read_option_bytes_boot_add32(stlink_t *sl, uint32_t *option_byte) { + if (sl->option_base == 0) { + ELOG("Option bytes boot address read is currently not supported for " + "connected chip\n"); + return -1; + } + + switch (sl->chip_id) { + case STLINK_CHIPID_STM32_F7XXXX: + return stlink_read_option_bytes_boot_add_f7(sl, option_byte); + default: + return -1; + // return stlink_read_option_bytes_boot_add_generic(sl, option_byte); + } } /** @@ -4172,20 +4350,19 @@ int stlink_read_option_bytes_boot_add32(stlink_t *sl, uint32_t* option_byte) * @param option_byte option value * @return 0 on success, -ve on failure. */ -int stlink_read_option_control_register32(stlink_t *sl, uint32_t* option_byte) -{ - if (sl->option_base == 0) { - ELOG("Option bytes read is currently not supported for connected chip\n"); - return -1; - } +int stlink_read_option_control_register32(stlink_t *sl, uint32_t *option_byte) { + if (sl->option_base == 0) { + ELOG("Option bytes read is currently not supported for connected chip\n"); + return -1; + } - switch (sl->chip_id) { - case STLINK_CHIPID_STM32_F7XXXX: - return stlink_read_option_control_register_f7(sl, option_byte); - default: - return -1; - //return stlink_read_option_control_register_generic(sl, option_byte); - } + switch (sl->chip_id) { + case STLINK_CHIPID_STM32_F7XXXX: + return stlink_read_option_control_register_f7(sl, option_byte); + default: + return -1; + // return stlink_read_option_control_register_generic(sl, option_byte); + } } /** @@ -4194,20 +4371,20 @@ int stlink_read_option_control_register32(stlink_t *sl, uint32_t* option_byte) * @param option_byte option value * @return 0 on success, -ve on failure. */ -int stlink_read_option_control_register1_32(stlink_t *sl, uint32_t* option_byte) -{ - if (sl->option_base == 0) { - ELOG("Option bytes read is currently not supported for connected chip\n"); - return -1; - } - - switch (sl->chip_id) { - case STLINK_CHIPID_STM32_F7XXXX: - return stlink_read_option_control_register1_f7(sl, option_byte); - default: - return -1; - //return stlink_read_option_control_register1_generic(sl, option_byte); - } +int stlink_read_option_control_register1_32(stlink_t *sl, + uint32_t *option_byte) { + if (sl->option_base == 0) { + ELOG("Option bytes read is currently not supported for connected chip\n"); + return -1; + } + + switch (sl->chip_id) { + case STLINK_CHIPID_STM32_F7XXXX: + return stlink_read_option_control_register1_f7(sl, option_byte); + default: + return -1; + // return stlink_read_option_control_register1_generic(sl, option_byte); + } } /** @@ -4216,10 +4393,11 @@ int stlink_read_option_control_register1_32(stlink_t *sl, uint32_t* option_byte) * @param option_byte value to write * @return 0 on success, -ve on failure. */ -int stlink_write_option_bytes32(stlink_t *sl, uint32_t option_byte) -{ - WLOG("About to write option byte %#10x to %#10x.\n", option_byte, sl->option_base); - return stlink_write_option_bytes(sl, sl->option_base, (uint8_t *) &option_byte, 4); +int stlink_write_option_bytes32(stlink_t *sl, uint32_t option_byte) { + WLOG("About to write option byte %#10x to %#10x.\n", option_byte, + sl->option_base); + return stlink_write_option_bytes(sl, sl->option_base, (uint8_t *)&option_byte, + 4); } /** @@ -4229,73 +4407,76 @@ int stlink_write_option_bytes32(stlink_t *sl, uint32_t option_byte) * @param base option bytes to write * @return 0 on success, -ve on failure. */ -int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t len) { - int ret = -1; - - if (sl->option_base == 0) { - ELOG("Option bytes writing is currently not supported for connected chip\n"); - return(-1); - } - - - if ((addr < sl->option_base) || addr > sl->option_base + sl->option_size) { - ELOG("Option bytes start address out of Option bytes range\n"); - return(-1); - } - - if (addr + len > sl->option_base + sl->option_size) { - ELOG("Option bytes data too long\n"); - return(-1); - } - - wait_flash_busy(sl); - - if (unlock_flash_if(sl)) { - ELOG("Flash unlock failed! System reset required to be able to unlock it again!\n"); - return(-1); - } - - if (unlock_flash_option_if(sl)) { - ELOG("Flash option unlock failed!\n"); - return(-1); - } - - switch (sl->flash_type) { - case STLINK_FLASH_TYPE_F4: - ret = stlink_write_option_bytes_f4(sl, base, addr, len); - break; - case STLINK_FLASH_TYPE_F7: - ret = stlink_write_option_bytes_f7(sl, base, addr, len); - break; - case STLINK_FLASH_TYPE_L0: - ret = stlink_write_option_bytes_l0(sl, base, addr, len); - break; - case STLINK_FLASH_TYPE_L4: - ret = stlink_write_option_bytes_l4(sl, base, addr, len); - break; - case STLINK_FLASH_TYPE_G0: - case STLINK_FLASH_TYPE_G4: - ret = stlink_write_option_bytes_gx(sl, base, addr, len); - break; - case STLINK_FLASH_TYPE_H7: - ret = stlink_write_option_bytes_h7(sl, base, addr, len); - break; - default: - ELOG("Option bytes writing is currently not implemented for connected chip\n"); - break; - } - - if (ret) { - ELOG("Flash option write failed!\n"); - } else { - ILOG("Wrote %d option bytes to %#010x!\n", len, addr); - } - - /* Re-lock flash. */ - lock_flash_option(sl); - lock_flash(sl); - - return ret; +int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t *base, + uint32_t len) { + int ret = -1; + + if (sl->option_base == 0) { + ELOG( + "Option bytes writing is currently not supported for connected chip\n"); + return (-1); + } + + if ((addr < sl->option_base) || addr > sl->option_base + sl->option_size) { + ELOG("Option bytes start address out of Option bytes range\n"); + return (-1); + } + + if (addr + len > sl->option_base + sl->option_size) { + ELOG("Option bytes data too long\n"); + return (-1); + } + + wait_flash_busy(sl); + + if (unlock_flash_if(sl)) { + ELOG("Flash unlock failed! System reset required to be able to unlock it " + "again!\n"); + return (-1); + } + + if (unlock_flash_option_if(sl)) { + ELOG("Flash option unlock failed!\n"); + return (-1); + } + + switch (sl->flash_type) { + case STLINK_FLASH_TYPE_F4: + ret = stlink_write_option_bytes_f4(sl, base, addr, len); + break; + case STLINK_FLASH_TYPE_F7: + ret = stlink_write_option_bytes_f7(sl, base, addr, len); + break; + case STLINK_FLASH_TYPE_L0: + ret = stlink_write_option_bytes_l0(sl, base, addr, len); + break; + case STLINK_FLASH_TYPE_L4: + ret = stlink_write_option_bytes_l4(sl, base, addr, len); + break; + case STLINK_FLASH_TYPE_G0: + case STLINK_FLASH_TYPE_G4: + ret = stlink_write_option_bytes_gx(sl, base, addr, len); + break; + case STLINK_FLASH_TYPE_H7: + ret = stlink_write_option_bytes_h7(sl, base, addr, len); + break; + default: + ELOG("Option bytes writing is currently not implemented for connected " + "chip\n"); + break; + } + + if (ret) { + ELOG("Flash option write failed!\n"); + } else { + ILOG("Wrote %d option bytes to %#010x!\n", len, addr); + } + + /* Re-lock flash. */ + lock_flash_option(sl); + lock_flash(sl); + + return ret; } /** @@ -4304,24 +4485,30 @@ int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t* base, ui * @param option_byte value to write * @return 0 on success, -ve on failure. */ -static int stlink_write_option_control_register_f7(stlink_t *sl, uint32_t option_control_register) { - int ret = 0; +static int +stlink_write_option_control_register_f7(stlink_t *sl, + uint32_t option_control_register) { + int ret = 0; - // Clear errors - clear_flash_error(sl); + // Clear errors + clear_flash_error(sl); - ILOG("Asked to write option control register 1 %#10x to %#010x.\n", option_control_register, FLASH_F7_OPTCR); + ILOG("Asked to write option control register 1 %#10x to %#010x.\n", + option_control_register, FLASH_F7_OPTCR); - /* write option byte, ensuring we dont lock opt, and set strt bit */ - stlink_write_debug32(sl, FLASH_F7_OPTCR, (option_control_register & ~(1 << FLASH_F7_OPTCR_LOCK)) | (1 << FLASH_F7_OPTCR_START)); + /* write option byte, ensuring we dont lock opt, and set strt bit */ + stlink_write_debug32(sl, FLASH_F7_OPTCR, + (option_control_register & ~(1 << FLASH_F7_OPTCR_LOCK)) | + (1 << FLASH_F7_OPTCR_START)); - wait_flash_busy(sl); + wait_flash_busy(sl); - ret = check_flash_error(sl); - if (!ret) - ILOG("Wrote option bytes %#010x to %#010x!\n", option_control_register, FLASH_F7_OPTCR); + ret = check_flash_error(sl); + if (!ret) + ILOG("Wrote option bytes %#010x to %#010x!\n", option_control_register, + FLASH_F7_OPTCR); - return ret; + return ret; } /** @@ -4330,29 +4517,36 @@ static int stlink_write_option_control_register_f7(stlink_t *sl, uint32_t option * @param option_byte value to write * @return 0 on success, -ve on failure. */ -static int stlink_write_option_control_register1_f7(stlink_t *sl, uint32_t option_control_register1) { - int ret = 0; +static int +stlink_write_option_control_register1_f7(stlink_t *sl, + uint32_t option_control_register1) { + int ret = 0; - // Clear errors - clear_flash_error(sl); + // Clear errors + clear_flash_error(sl); - ILOG("Asked to write option control register 1 %#010x to %#010x.\n", option_control_register1, FLASH_F7_OPTCR1); + ILOG("Asked to write option control register 1 %#010x to %#010x.\n", + option_control_register1, FLASH_F7_OPTCR1); - /* write option byte, ensuring we dont lock opt, and set strt bit */ - uint32_t current_control_register_value; - stlink_read_debug32(sl, FLASH_F7_OPTCR, ¤t_control_register_value); + /* write option byte, ensuring we dont lock opt, and set strt bit */ + uint32_t current_control_register_value; + stlink_read_debug32(sl, FLASH_F7_OPTCR, ¤t_control_register_value); - /* write option byte */ - stlink_write_debug32(sl, FLASH_F7_OPTCR1, option_control_register1); - stlink_write_debug32(sl, FLASH_F7_OPTCR, (current_control_register_value & ~(1 << FLASH_F7_OPTCR_LOCK)) | (1 << FLASH_F7_OPTCR_START)); + /* write option byte */ + stlink_write_debug32(sl, FLASH_F7_OPTCR1, option_control_register1); + stlink_write_debug32( + sl, FLASH_F7_OPTCR, + (current_control_register_value & ~(1 << FLASH_F7_OPTCR_LOCK)) | + (1 << FLASH_F7_OPTCR_START)); - wait_flash_busy(sl); + wait_flash_busy(sl); - ret = check_flash_error(sl); - if (!ret) - ILOG("Wrote option bytes %#010x to %#010x!\n", option_control_register1, FLASH_F7_OPTCR1); + ret = check_flash_error(sl); + if (!ret) + ILOG("Wrote option bytes %#010x to %#010x!\n", option_control_register1, + FLASH_F7_OPTCR1); - return ret; + return ret; } /** @@ -4361,9 +4555,11 @@ static int stlink_write_option_control_register1_f7(stlink_t *sl, uint32_t optio * @param option_byte value to write * @return 0 on success, -ve on failure. */ -static int stlink_write_option_bytes_boot_add_f7(stlink_t *sl, uint32_t option_byte_boot_add) { - ILOG("Asked to write option byte boot add %#010x.\n", option_byte_boot_add); - return stlink_write_option_control_register1_f7(sl, option_byte_boot_add); +static int +stlink_write_option_bytes_boot_add_f7(stlink_t *sl, + uint32_t option_byte_boot_add) { + ILOG("Asked to write option byte boot add %#010x.\n", option_byte_boot_add); + return stlink_write_option_control_register1_f7(sl, option_byte_boot_add); } /** @@ -4372,41 +4568,43 @@ static int stlink_write_option_bytes_boot_add_f7(stlink_t *sl, uint32_t option_b * @param option bytes boot address to write * @return 0 on success, -ve on failure. */ -int stlink_write_option_bytes_boot_add32(stlink_t *sl, uint32_t option_bytes_boot_add) -{ - int ret = -1; +int stlink_write_option_bytes_boot_add32(stlink_t *sl, + uint32_t option_bytes_boot_add) { + int ret = -1; - wait_flash_busy(sl); + wait_flash_busy(sl); - if (unlock_flash_if(sl)) { - ELOG("Flash unlock failed! System reset required to be able to unlock it again!\n"); - return -1; - } + if (unlock_flash_if(sl)) { + ELOG("Flash unlock failed! System reset required to be able to unlock it " + "again!\n"); + return -1; + } - if (unlock_flash_option_if(sl)) { - ELOG("Flash option unlock failed!\n"); - return -1; - } + if (unlock_flash_option_if(sl)) { + ELOG("Flash option unlock failed!\n"); + return -1; + } - switch (sl->flash_type) { - case STLINK_FLASH_TYPE_F7: - ret = stlink_write_option_bytes_boot_add_f7(sl, option_bytes_boot_add); - break; - default: - ELOG("Option bytes boot address writing is currently not implemented for connected chip\n"); - break; - } + switch (sl->flash_type) { + case STLINK_FLASH_TYPE_F7: + ret = stlink_write_option_bytes_boot_add_f7(sl, option_bytes_boot_add); + break; + default: + ELOG("Option bytes boot address writing is currently not implemented for " + "connected chip\n"); + break; + } - if (ret) - ELOG("Flash option write failed!\n"); - else - ILOG("Wrote option bytes boot address %#010x!\n", option_bytes_boot_add); + if (ret) + ELOG("Flash option write failed!\n"); + else + ILOG("Wrote option bytes boot address %#010x!\n", option_bytes_boot_add); - /* Re-lock flash. */ - lock_flash_option(sl); - lock_flash(sl); + /* Re-lock flash. */ + lock_flash_option(sl); + lock_flash(sl); - return ret; + return ret; } /** @@ -4415,41 +4613,43 @@ int stlink_write_option_bytes_boot_add32(stlink_t *sl, uint32_t option_bytes_boo * @param option bytes boot address to write * @return 0 on success, -ve on failure. */ -int stlink_write_option_control_register32(stlink_t *sl, uint32_t option_control_register) -{ - int ret = -1; +int stlink_write_option_control_register32(stlink_t *sl, + uint32_t option_control_register) { + int ret = -1; - wait_flash_busy(sl); + wait_flash_busy(sl); - if (unlock_flash_if(sl)) { - ELOG("Flash unlock failed! System reset required to be able to unlock it again!\n"); - return -1; - } + if (unlock_flash_if(sl)) { + ELOG("Flash unlock failed! System reset required to be able to unlock it " + "again!\n"); + return -1; + } - if (unlock_flash_option_if(sl)) { - ELOG("Flash option unlock failed!\n"); - return -1; - } + if (unlock_flash_option_if(sl)) { + ELOG("Flash option unlock failed!\n"); + return -1; + } - switch (sl->flash_type) { - case STLINK_FLASH_TYPE_F7: - ret = stlink_write_option_control_register_f7(sl, option_control_register); - break; - default: - ELOG("Option control register writing is currently not implemented for connected chip\n"); - break; - } + switch (sl->flash_type) { + case STLINK_FLASH_TYPE_F7: + ret = stlink_write_option_control_register_f7(sl, option_control_register); + break; + default: + ELOG("Option control register writing is currently not implemented for " + "connected chip\n"); + break; + } - if (ret) - ELOG("Flash option write failed!\n"); - else - ILOG("Wrote option control register %#010x!\n", option_control_register); + if (ret) + ELOG("Flash option write failed!\n"); + else + ILOG("Wrote option control register %#010x!\n", option_control_register); - /* Re-lock flash. */ - lock_flash_option(sl); - lock_flash(sl); + /* Re-lock flash. */ + lock_flash_option(sl); + lock_flash(sl); - return ret; + return ret; } /** @@ -4458,40 +4658,43 @@ int stlink_write_option_control_register32(stlink_t *sl, uint32_t option_control * @param option bytes boot address to write * @return 0 on success, -ve on failure. */ -int stlink_write_option_control_register1_32(stlink_t *sl, uint32_t option_control_register1) -{ - int ret = -1; +int stlink_write_option_control_register1_32( + stlink_t *sl, uint32_t option_control_register1) { + int ret = -1; - wait_flash_busy(sl); + wait_flash_busy(sl); - if (unlock_flash_if(sl)) { - ELOG("Flash unlock failed! System reset required to be able to unlock it again!\n"); - return -1; - } + if (unlock_flash_if(sl)) { + ELOG("Flash unlock failed! System reset required to be able to unlock it " + "again!\n"); + return -1; + } - if (unlock_flash_option_if(sl)) { - ELOG("Flash option unlock failed!\n"); - return -1; - } + if (unlock_flash_option_if(sl)) { + ELOG("Flash option unlock failed!\n"); + return -1; + } - switch (sl->flash_type) { - case STLINK_FLASH_TYPE_F7: - ret = stlink_write_option_control_register1_f7(sl, option_control_register1); - break; - default: - ELOG("Option control register 1 writing is currently not implemented for connected chip\n"); - break; - } + switch (sl->flash_type) { + case STLINK_FLASH_TYPE_F7: + ret = + stlink_write_option_control_register1_f7(sl, option_control_register1); + break; + default: + ELOG("Option control register 1 writing is currently not implemented for " + "connected chip\n"); + break; + } - if (ret) - ELOG("Flash option write failed!\n"); - else - ILOG("Wrote option control register 1 %#010x!\n", option_control_register1); + if (ret) + ELOG("Flash option write failed!\n"); + else + ILOG("Wrote option control register 1 %#010x!\n", option_control_register1); - lock_flash_option(sl); - lock_flash(sl); + lock_flash_option(sl); + lock_flash(sl); - return(ret); + return (ret); } /** @@ -4501,61 +4704,66 @@ int stlink_write_option_control_register1_32(stlink_t *sl, uint32_t option_contr * @param addr of the memory mapped option bytes * @return 0 on success, -ve on failure. */ -int stlink_fwrite_option_bytes(stlink_t *sl, const char* path, stm32_addr_t addr) { - /* Write the file in flash at addr */ - int err; - mapped_file_t mf = MAPPED_FILE_INITIALIZER; - - if (map_file(&mf, path) == -1) { - ELOG("map_file() == -1\n"); - return(-1); - } +int stlink_fwrite_option_bytes(stlink_t *sl, const char *path, + stm32_addr_t addr) { + /* Write the file in flash at addr */ + int err; + mapped_file_t mf = MAPPED_FILE_INITIALIZER; - printf("file %s ", path); - md5_calculate(&mf); - stlink_checksum(&mf); + if (map_file(&mf, path) == -1) { + ELOG("map_file() == -1\n"); + return (-1); + } - err = stlink_write_option_bytes(sl, addr, mf.base, (uint32_t)mf.len); - stlink_fwrite_finalize(sl, addr); - unmap_file(&mf); + printf("file %s ", path); + md5_calculate(&mf); + stlink_checksum(&mf); - return(err); + err = stlink_write_option_bytes(sl, addr, mf.base, (uint32_t)mf.len); + stlink_fwrite_finalize(sl, addr); + unmap_file(&mf); + + return (err); } int stlink_target_connect(stlink_t *sl, enum connect_type connect) { - uint32_t dhcsr; - - if (connect == CONNECT_UNDER_RESET) { - stlink_jtag_reset(sl, STLINK_JTAG_DRIVE_NRST_LOW); + uint32_t dhcsr; - // minimum reset pulse duration of 20 us (RM0008, 8.1.2 Power reset) - usleep(20); + if (connect == CONNECT_UNDER_RESET) { + stlink_jtag_reset(sl, STLINK_JTAG_DRIVE_NRST_LOW); - if (stlink_current_mode(sl) != STLINK_DEV_DEBUG_MODE) { stlink_enter_swd_mode(sl); } - stlink_force_debug(sl); + // minimum reset pulse duration of 20 us (RM0008, 8.1.2 Power reset) + usleep(20); - // clear S_RESET_ST in DHCSR register - stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); + if (stlink_current_mode(sl) != STLINK_DEV_DEBUG_MODE) { + stlink_enter_swd_mode(sl); + } + stlink_force_debug(sl); - stlink_jtag_reset(sl, STLINK_JTAG_DRIVE_NRST_HIGH); - usleep(10000); + // clear S_RESET_ST in DHCSR register + stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); - // check NRST connection - dhcsr = 0; - stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); - if ((dhcsr & STLINK_REG_DHCSR_S_RESET_ST) == 0) { - WLOG("NRST is not connected\n"); - } + stlink_jtag_reset(sl, STLINK_JTAG_DRIVE_NRST_HIGH); + usleep(10000); - // addition soft reset for halt before the first instruction - stlink_soft_reset(sl, 1 /* halt on reset */); + // check NRST connection + dhcsr = 0; + stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); + if ((dhcsr & STLINK_REG_DHCSR_S_RESET_ST) == 0) { + WLOG("NRST is not connected\n"); } - if (stlink_current_mode(sl) != STLINK_DEV_DEBUG_MODE) { stlink_enter_swd_mode(sl); } + // addition soft reset for halt before the first instruction + stlink_soft_reset(sl, 1 /* halt on reset */); + } - if (connect == CONNECT_NORMAL) { - stlink_reset(sl, RESET_AUTO); - } + if (stlink_current_mode(sl) != STLINK_DEV_DEBUG_MODE) { + stlink_enter_swd_mode(sl); + } + + if (connect == CONNECT_NORMAL) { + stlink_reset(sl, RESET_AUTO); + } - return stlink_load_device_params(sl); + return stlink_load_device_params(sl); } diff --git a/src/st-trace/trace.c b/src/st-trace/trace.c index f28624475..a02c64701 100644 --- a/src/st-trace/trace.c +++ b/src/st-trace/trace.c @@ -1,556 +1,596 @@ +#include +#include +#include +#include #include #include #include #include -#include -#include -#include -#include -#include #include +#include -#include -#include #include - +#include +#include #define DEFAULT_LOGGING_LEVEL 50 #define DEBUG_LOGGING_LEVEL 100 -#define APP_RESULT_SUCCESS 0 -#define APP_RESULT_INVALID_PARAMS 1 -#define APP_RESULT_STLINK_NOT_FOUND 2 -#define APP_RESULT_STLINK_MISSING_DEVICE 3 -#define APP_RESULT_STLINK_UNSUPPORTED_DEVICE 4 -#define APP_RESULT_STLINK_UNSUPPORTED_LINK 5 -#define APP_RESULT_UNSUPPORTED_TRACE_FREQUENCY 6 -#define APP_RESULT_STLINK_STATE_ERROR 7 +#define APP_RESULT_SUCCESS 0 +#define APP_RESULT_INVALID_PARAMS 1 +#define APP_RESULT_STLINK_NOT_FOUND 2 +#define APP_RESULT_STLINK_MISSING_DEVICE 3 +#define APP_RESULT_STLINK_UNSUPPORTED_DEVICE 4 +#define APP_RESULT_STLINK_UNSUPPORTED_LINK 5 +#define APP_RESULT_UNSUPPORTED_TRACE_FREQUENCY 6 +#define APP_RESULT_STLINK_STATE_ERROR 7 // See D4.2 of https://developer.arm.com/documentation/ddi0403/ed/ -#define TRACE_OP_IS_OVERFLOW(c) ((c) == 0x70) -#define TRACE_OP_IS_LOCAL_TIME(c) (((c) & 0x0f) == 0x00 && ((c) & 0x70) != 0x00) -#define TRACE_OP_IS_EXTENSION(c) (((c) & 0x0b) == 0x08) -#define TRACE_OP_IS_GLOBAL_TIME(c) (((c) & 0xdf) == 0x94) -#define TRACE_OP_IS_SOURCE(c) (((c) & 0x03) != 0x00) -#define TRACE_OP_IS_SW_SOURCE(c) (((c) & 0x03) != 0x00 && ((c) & 0x04) == 0x00) -#define TRACE_OP_IS_HW_SOURCE(c) (((c) & 0x03) != 0x00 && ((c) & 0x04) == 0x04) -#define TRACE_OP_IS_TARGET_SOURCE(c) ((c) == 0x01) -#define TRACE_OP_GET_CONTINUATION(c) ((c) & 0x80) -#define TRACE_OP_GET_SOURCE_SIZE(c) ((c) & 0x03) -#define TRACE_OP_GET_SW_SOURCE_ADDR(c) ((c) >> 3) - +#define TRACE_OP_IS_OVERFLOW(c) ((c) == 0x70) +#define TRACE_OP_IS_LOCAL_TIME(c) (((c)&0x0f) == 0x00 && ((c)&0x70) != 0x00) +#define TRACE_OP_IS_EXTENSION(c) (((c)&0x0b) == 0x08) +#define TRACE_OP_IS_GLOBAL_TIME(c) (((c)&0xdf) == 0x94) +#define TRACE_OP_IS_SOURCE(c) (((c)&0x03) != 0x00) +#define TRACE_OP_IS_SW_SOURCE(c) (((c)&0x03) != 0x00 && ((c)&0x04) == 0x00) +#define TRACE_OP_IS_HW_SOURCE(c) (((c)&0x03) != 0x00 && ((c)&0x04) == 0x04) +#define TRACE_OP_IS_TARGET_SOURCE(c) ((c) == 0x01) +#define TRACE_OP_GET_CONTINUATION(c) ((c)&0x80) +#define TRACE_OP_GET_SOURCE_SIZE(c) ((c)&0x03) +#define TRACE_OP_GET_SW_SOURCE_ADDR(c) ((c) >> 3) typedef struct { - bool show_help; - bool show_version; - int logging_level; - uint32_t core_frequency; - uint32_t trace_frequency; - bool reset_board; - bool force; - char* serial_number; + bool show_help; + bool show_version; + int logging_level; + uint32_t core_frequency; + uint32_t trace_frequency; + bool reset_board; + bool force; + char *serial_number; } st_settings_t; - // We use a simple state machine to parse the trace data. typedef enum { - TRACE_STATE_UNKNOWN, - TRACE_STATE_IDLE, - TRACE_STATE_TARGET_SOURCE, - TRACE_STATE_SKIP_FRAME, - TRACE_STATE_SKIP_4, - TRACE_STATE_SKIP_3, - TRACE_STATE_SKIP_2, - TRACE_STATE_SKIP_1, + TRACE_STATE_UNKNOWN, + TRACE_STATE_IDLE, + TRACE_STATE_TARGET_SOURCE, + TRACE_STATE_SKIP_FRAME, + TRACE_STATE_SKIP_4, + TRACE_STATE_SKIP_3, + TRACE_STATE_SKIP_2, + TRACE_STATE_SKIP_1, } trace_state; typedef struct { - time_t start_time; - bool configuration_checked; + time_t start_time; + bool configuration_checked; - trace_state state; + trace_state state; - uint32_t count_raw_bytes; - uint32_t count_target_data; - uint32_t count_time_packets; - uint32_t count_hw_overflow; - uint32_t count_sw_overflow; - uint32_t count_error; + uint32_t count_raw_bytes; + uint32_t count_target_data; + uint32_t count_time_packets; + uint32_t count_hw_overflow; + uint32_t count_sw_overflow; + uint32_t count_error; - uint8_t unknown_opcodes[256 / 8]; - uint32_t unknown_sources; + uint8_t unknown_opcodes[256 / 8]; + uint32_t unknown_sources; } st_trace_t; - -// We use a global flag to allow communicating to the main thread from the signal handler. +// We use a global flag to allow communicating to the main thread from the +// signal handler. static bool g_abort_trace = false; -static void abort_trace() { - g_abort_trace = true; -} +static void abort_trace() { g_abort_trace = true; } #if defined(_WIN32) BOOL WINAPI CtrlHandler(DWORD fdwCtrlType) { - (void)fdwCtrlType; - abort_trace(); - return FALSE; + (void)fdwCtrlType; + abort_trace(); + return FALSE; } #endif static void usage(void) { - puts("st-trace - usage:"); - puts(" -h, --help Print this help"); - puts(" -V, --version Print this version"); - puts(" -vXX, --verbose=XX Specify a specific verbosity level (0..99)"); - puts(" -v, --verbose Specify a generally verbose logging"); - puts(" -cXX, --clock=XX Specify the core frequency in MHz"); - puts(" -tXX, --trace=XX Specify the trace frequency in Hz"); - puts(" -n, --no-reset Do not reset board on connection"); - puts(" -sXX, --serial=XX Use a specific serial number"); - puts(" -f, --force Ignore most initialization errors"); + puts("st-trace - usage:"); + puts(" -h, --help Print this help"); + puts(" -V, --version Print this version"); + puts(" -vXX, --verbose=XX Specify a specific verbosity level (0..99)"); + puts(" -v, --verbose Specify a generally verbose logging"); + puts(" -cXX, --clock=XX Specify the core frequency in MHz"); + puts(" -tXX, --trace=XX Specify the trace frequency in Hz"); + puts(" -n, --no-reset Do not reset board on connection"); + puts(" -sXX, --serial=XX Use a specific serial number"); + puts(" -f, --force Ignore most initialization errors"); } -bool parse_options(int argc, char** argv, st_settings_t *settings) { - - static struct option long_options[] = { - {"help", no_argument, NULL, 'h'}, - {"version", no_argument, NULL, 'V'}, - {"verbose", optional_argument, NULL, 'v'}, - {"clock", required_argument, NULL, 'c'}, - {"trace", required_argument, NULL, 't'}, - {"no-reset", no_argument, NULL, 'n'}, - {"serial", required_argument, NULL, 's'}, - {"force", no_argument, NULL, 'f'}, - {0, 0, 0, 0}, - }; - int option_index = 0; - int c; - bool error = false; - - settings->show_help = false; - settings->show_version = false; - settings->logging_level = DEFAULT_LOGGING_LEVEL; - settings->core_frequency = 0; - settings->trace_frequency = 0; - settings->reset_board = true; - settings->force = false; - settings->serial_number = NULL; - ugly_init(settings->logging_level); - - while ((c = getopt_long(argc, argv, "hVv::c:ns:f", long_options, &option_index)) != -1) { - switch (c) { - case 'h': - settings->show_help = true; - break; - case 'V': - settings->show_version = true; - break; - case 'v': - if (optarg) { - settings->logging_level = atoi(optarg); - } else { - settings->logging_level = DEBUG_LOGGING_LEVEL; - } - ugly_init(settings->logging_level); - break; - case 'c': - settings->core_frequency = atoi(optarg) * 1000000; - break; - case 't': - settings->trace_frequency = atoi(optarg); - break; - case 'n': - settings->reset_board = false; - break; - case 'f': - settings->force = true; - break; - case 's': - settings->serial_number = optarg; - break; - case '?': - error = true; - break; - default: - ELOG("Unknown command line option: '%c' (0x%02x)\n", c, c); - error = true; - break; - } +bool parse_options(int argc, char **argv, st_settings_t *settings) { + + static struct option long_options[] = { + {"help", no_argument, NULL, 'h'}, + {"version", no_argument, NULL, 'V'}, + {"verbose", optional_argument, NULL, 'v'}, + {"clock", required_argument, NULL, 'c'}, + {"trace", required_argument, NULL, 't'}, + {"no-reset", no_argument, NULL, 'n'}, + {"serial", required_argument, NULL, 's'}, + {"force", no_argument, NULL, 'f'}, + {0, 0, 0, 0}, + }; + int option_index = 0; + int c; + bool error = false; + + settings->show_help = false; + settings->show_version = false; + settings->logging_level = DEFAULT_LOGGING_LEVEL; + settings->core_frequency = 0; + settings->trace_frequency = 0; + settings->reset_board = true; + settings->force = false; + settings->serial_number = NULL; + ugly_init(settings->logging_level); + + while ((c = getopt_long(argc, argv, "hVv::c:ns:f", long_options, + &option_index)) != -1) { + switch (c) { + case 'h': + settings->show_help = true; + break; + case 'V': + settings->show_version = true; + break; + case 'v': + if (optarg) { + settings->logging_level = atoi(optarg); + } else { + settings->logging_level = DEBUG_LOGGING_LEVEL; + } + ugly_init(settings->logging_level); + break; + case 'c': + settings->core_frequency = atoi(optarg) * 1000000; + break; + case 't': + settings->trace_frequency = atoi(optarg); + break; + case 'n': + settings->reset_board = false; + break; + case 'f': + settings->force = true; + break; + case 's': + settings->serial_number = optarg; + break; + case '?': + error = true; + break; + default: + ELOG("Unknown command line option: '%c' (0x%02x)\n", c, c); + error = true; + break; } + } - if (optind < argc) { - while (optind < argc) { - ELOG("Unknown command line argument: '%s'\n", argv[optind++]); - } - error = true; + if (optind < argc) { + while (optind < argc) { + ELOG("Unknown command line argument: '%s'\n", argv[optind++]); } + error = true; + } - if (error && !settings->force) - return false; + if (error && !settings->force) + return false; - return true; + return true; } -static stlink_t* stlink_connect(const st_settings_t* settings) { - return stlink_open_usb(settings->logging_level, false, settings->serial_number, 0); +static stlink_t *stlink_connect(const st_settings_t *settings) { + return stlink_open_usb(settings->logging_level, false, + settings->serial_number, 0); } -static bool enable_trace(stlink_t* stlink, const st_settings_t* settings, uint32_t trace_frequency) { - - if (stlink_force_debug(stlink)) { - ELOG("Unable to debug device\n"); - if (!settings->force) - return false; - } - - if (settings->reset_board && stlink_reset(stlink, RESET_AUTO)) { - ELOG("Unable to reset device\n"); - if (!settings->force) - return false; - } - - - stlink_write_debug32(stlink, STLINK_REG_DHCSR, STLINK_REG_DHCSR_DBGKEY | - STLINK_REG_DHCSR_C_DEBUGEN | - STLINK_REG_DHCSR_C_HALT); - stlink_write_debug32(stlink, STLINK_REG_DEMCR, STLINK_REG_DEMCR_TRCENA); - stlink_write_debug32(stlink, STLINK_REG_CM3_FP_CTRL, STLINK_REG_CM3_FP_CTRL_KEY); - stlink_write_debug32(stlink, STLINK_REG_DWT_FUNCTION0, 0); - stlink_write_debug32(stlink, STLINK_REG_DWT_FUNCTION1, 0); - stlink_write_debug32(stlink, STLINK_REG_DWT_FUNCTION2, 0); - stlink_write_debug32(stlink, STLINK_REG_DWT_FUNCTION3, 0); - stlink_write_debug32(stlink, STLINK_REG_DWT_CTRL, 0); - stlink_write_debug32(stlink, STLINK_REG_DBGMCU_CR, STLINK_REG_DBGMCU_CR_DBG_SLEEP | - STLINK_REG_DBGMCU_CR_DBG_STOP | - STLINK_REG_DBGMCU_CR_DBG_STANDBY | - STLINK_REG_DBGMCU_CR_TRACE_IOEN | - STLINK_REG_DBGMCU_CR_TRACE_MODE_ASYNC); - - if (stlink_trace_enable(stlink, trace_frequency)) { - ELOG("Unable to turn on tracing in stlink\n"); - if (!settings->force) - return false; - } - - stlink_write_debug32(stlink, STLINK_REG_TPI_CSPSR, STLINK_REG_TPI_CSPSR_PORT_SIZE_1); - - if (settings->core_frequency) { - uint32_t prescaler = settings->core_frequency / trace_frequency - 1; - if (prescaler > STLINK_REG_TPI_ACPR_MAX) { - ELOG("Trace frequency prescaler %d out of range. Try setting a faster trace frequency.\n", prescaler); - if (!settings->force) - return false; - } - stlink_write_debug32(stlink, STLINK_REG_TPI_ACPR, prescaler); // Set TPIU_ACPR clock divisor - } - stlink_write_debug32(stlink, STLINK_REG_TPI_FFCR, STLINK_REG_TPI_FFCR_TRIG_IN); - stlink_write_debug32(stlink, STLINK_REG_TPI_SPPR, STLINK_REG_TPI_SPPR_SWO_NRZ); - stlink_write_debug32(stlink, STLINK_REG_ITM_LAR, STLINK_REG_ITM_LAR_KEY); - stlink_write_debug32(stlink, STLINK_REG_ITM_TCC, 0x00000400); // Set sync counter - stlink_write_debug32(stlink, STLINK_REG_ITM_TCR, STLINK_REG_ITM_TCR_TRACE_BUS_ID_1 | - STLINK_REG_ITM_TCR_TS_ENA | - STLINK_REG_ITM_TCR_ITM_ENA); - stlink_write_debug32(stlink, STLINK_REG_ITM_TER, STLINK_REG_ITM_TER_PORTS_ALL); - stlink_write_debug32(stlink, STLINK_REG_ITM_TPR, STLINK_REG_ITM_TPR_PORTS_ALL); - stlink_write_debug32(stlink, STLINK_REG_DWT_CTRL, 4 * STLINK_REG_DWT_CTRL_NUM_COMP | - STLINK_REG_DWT_CTRL_CYC_TAP | - 0xF * STLINK_REG_DWT_CTRL_POST_INIT | - 0xF * STLINK_REG_DWT_CTRL_POST_PRESET | - STLINK_REG_DWT_CTRL_CYCCNT_ENA); - stlink_write_debug32(stlink, STLINK_REG_DEMCR, STLINK_REG_DEMCR_TRCENA); - - uint32_t prescaler; - stlink_read_debug32(stlink, STLINK_REG_TPI_ACPR_MAX, &prescaler); - if (prescaler) { - uint32_t system_clock_speed = (prescaler + 1) * trace_frequency; - uint32_t system_clock_speed_mhz = (system_clock_speed + 500000) / 1000000; - ILOG("Trace Port Interface configured to expect a %d MHz system clock.\n", system_clock_speed_mhz); - } else { - WLOG("Trace Port Interface not configured. Specify the system clock with a --clock=XX command\n"); - WLOG("line option or set it in your device's clock initialization routine, such as with:\n"); - WLOG(" TPI->ACPR = HAL_RCC_GetHCLKFreq() / %d - 1;\n", trace_frequency); +static bool enable_trace(stlink_t *stlink, const st_settings_t *settings, + uint32_t trace_frequency) { + + if (stlink_force_debug(stlink)) { + ELOG("Unable to debug device\n"); + if (!settings->force) + return false; + } + + if (settings->reset_board && stlink_reset(stlink, RESET_AUTO)) { + ELOG("Unable to reset device\n"); + if (!settings->force) + return false; + } + + stlink_write_debug32(stlink, STLINK_REG_DHCSR, + STLINK_REG_DHCSR_DBGKEY | STLINK_REG_DHCSR_C_DEBUGEN | + STLINK_REG_DHCSR_C_HALT); + stlink_write_debug32(stlink, STLINK_REG_DEMCR, STLINK_REG_DEMCR_TRCENA); + stlink_write_debug32(stlink, STLINK_REG_CM3_FP_CTRL, + STLINK_REG_CM3_FP_CTRL_KEY); + stlink_write_debug32(stlink, STLINK_REG_DWT_FUNCTION0, 0); + stlink_write_debug32(stlink, STLINK_REG_DWT_FUNCTION1, 0); + stlink_write_debug32(stlink, STLINK_REG_DWT_FUNCTION2, 0); + stlink_write_debug32(stlink, STLINK_REG_DWT_FUNCTION3, 0); + stlink_write_debug32(stlink, STLINK_REG_DWT_CTRL, 0); + stlink_write_debug32( + stlink, STLINK_REG_DBGMCU_CR, + STLINK_REG_DBGMCU_CR_DBG_SLEEP | STLINK_REG_DBGMCU_CR_DBG_STOP | + STLINK_REG_DBGMCU_CR_DBG_STANDBY | STLINK_REG_DBGMCU_CR_TRACE_IOEN | + STLINK_REG_DBGMCU_CR_TRACE_MODE_ASYNC); + + if (stlink_trace_enable(stlink, trace_frequency)) { + ELOG("Unable to turn on tracing in stlink\n"); + if (!settings->force) + return false; + } + + stlink_write_debug32(stlink, STLINK_REG_TPI_CSPSR, + STLINK_REG_TPI_CSPSR_PORT_SIZE_1); + + if (settings->core_frequency) { + uint32_t prescaler = settings->core_frequency / trace_frequency - 1; + if (prescaler > STLINK_REG_TPI_ACPR_MAX) { + ELOG("Trace frequency prescaler %d out of range. Try setting a faster " + "trace frequency.\n", + prescaler); + if (!settings->force) + return false; } - ILOG("Trace frequency set to %d Hz.\n", trace_frequency); - - return true; + stlink_write_debug32(stlink, STLINK_REG_TPI_ACPR, + prescaler); // Set TPIU_ACPR clock divisor + } + stlink_write_debug32(stlink, STLINK_REG_TPI_FFCR, + STLINK_REG_TPI_FFCR_TRIG_IN); + stlink_write_debug32(stlink, STLINK_REG_TPI_SPPR, + STLINK_REG_TPI_SPPR_SWO_NRZ); + stlink_write_debug32(stlink, STLINK_REG_ITM_LAR, STLINK_REG_ITM_LAR_KEY); + stlink_write_debug32(stlink, STLINK_REG_ITM_TCC, + 0x00000400); // Set sync counter + stlink_write_debug32(stlink, STLINK_REG_ITM_TCR, + STLINK_REG_ITM_TCR_TRACE_BUS_ID_1 | + STLINK_REG_ITM_TCR_TS_ENA | + STLINK_REG_ITM_TCR_ITM_ENA); + stlink_write_debug32(stlink, STLINK_REG_ITM_TER, + STLINK_REG_ITM_TER_PORTS_ALL); + stlink_write_debug32(stlink, STLINK_REG_ITM_TPR, + STLINK_REG_ITM_TPR_PORTS_ALL); + stlink_write_debug32(stlink, STLINK_REG_DWT_CTRL, + 4 * STLINK_REG_DWT_CTRL_NUM_COMP | + STLINK_REG_DWT_CTRL_CYC_TAP | + 0xF * STLINK_REG_DWT_CTRL_POST_INIT | + 0xF * STLINK_REG_DWT_CTRL_POST_PRESET | + STLINK_REG_DWT_CTRL_CYCCNT_ENA); + stlink_write_debug32(stlink, STLINK_REG_DEMCR, STLINK_REG_DEMCR_TRCENA); + + uint32_t prescaler; + stlink_read_debug32(stlink, STLINK_REG_TPI_ACPR_MAX, &prescaler); + if (prescaler) { + uint32_t system_clock_speed = (prescaler + 1) * trace_frequency; + uint32_t system_clock_speed_mhz = (system_clock_speed + 500000) / 1000000; + ILOG("Trace Port Interface configured to expect a %d MHz system clock.\n", + system_clock_speed_mhz); + } else { + WLOG("Trace Port Interface not configured. Specify the system clock with " + "a --clock=XX command\n"); + WLOG("line option or set it in your device's clock initialization routine, " + "such as with:\n"); + WLOG(" TPI->ACPR = HAL_RCC_GetHCLKFreq() / %d - 1;\n", trace_frequency); + } + ILOG("Trace frequency set to %d Hz.\n", trace_frequency); + + return true; } -static trace_state update_trace_idle(st_trace_t* trace, uint8_t c) { - // Handle a trace byte when we are in the idle state. - - if (TRACE_OP_IS_TARGET_SOURCE(c)) { - return TRACE_STATE_TARGET_SOURCE; - } - - if (TRACE_OP_IS_SOURCE(c)) { - uint8_t size = TRACE_OP_GET_SOURCE_SIZE(c); - if (TRACE_OP_IS_SW_SOURCE(c)) { - uint8_t addr = TRACE_OP_GET_SW_SOURCE_ADDR(c); - if (!(trace->unknown_sources & (1 << addr))) - WLOG("Unsupported source 0x%x size %d\n", addr, size); - trace->unknown_sources |= (1 << addr); - } - if (size == 1) return TRACE_STATE_SKIP_1; - if (size == 2) return TRACE_STATE_SKIP_2; - if (size == 3) return TRACE_STATE_SKIP_4; - } - - if (TRACE_OP_IS_LOCAL_TIME(c) || TRACE_OP_IS_GLOBAL_TIME(c)) { - trace->count_time_packets++; - return TRACE_OP_GET_CONTINUATION(c) ? TRACE_STATE_SKIP_FRAME : TRACE_STATE_IDLE; - } - - if (TRACE_OP_IS_EXTENSION(c)) { - return TRACE_OP_GET_CONTINUATION(c) ? TRACE_STATE_SKIP_FRAME : TRACE_STATE_IDLE; - } - - if (TRACE_OP_IS_OVERFLOW(c)) { - trace->count_hw_overflow++; - } - - if (!(trace->unknown_opcodes[c / 8] & (1 << c % 8))) - WLOG("Unknown opcode 0x%02x\n", c); - trace->unknown_opcodes[c / 8] |= (1 << c % 8); - - trace->count_error++; - return TRACE_OP_GET_CONTINUATION(c) ? TRACE_STATE_SKIP_FRAME : TRACE_STATE_IDLE; +static trace_state update_trace_idle(st_trace_t *trace, uint8_t c) { + // Handle a trace byte when we are in the idle state. + + if (TRACE_OP_IS_TARGET_SOURCE(c)) { + return TRACE_STATE_TARGET_SOURCE; + } + + if (TRACE_OP_IS_SOURCE(c)) { + uint8_t size = TRACE_OP_GET_SOURCE_SIZE(c); + if (TRACE_OP_IS_SW_SOURCE(c)) { + uint8_t addr = TRACE_OP_GET_SW_SOURCE_ADDR(c); + if (!(trace->unknown_sources & (1 << addr))) + WLOG("Unsupported source 0x%x size %d\n", addr, size); + trace->unknown_sources |= (1 << addr); + } + if (size == 1) + return TRACE_STATE_SKIP_1; + if (size == 2) + return TRACE_STATE_SKIP_2; + if (size == 3) + return TRACE_STATE_SKIP_4; + } + + if (TRACE_OP_IS_LOCAL_TIME(c) || TRACE_OP_IS_GLOBAL_TIME(c)) { + trace->count_time_packets++; + return TRACE_OP_GET_CONTINUATION(c) ? TRACE_STATE_SKIP_FRAME + : TRACE_STATE_IDLE; + } + + if (TRACE_OP_IS_EXTENSION(c)) { + return TRACE_OP_GET_CONTINUATION(c) ? TRACE_STATE_SKIP_FRAME + : TRACE_STATE_IDLE; + } + + if (TRACE_OP_IS_OVERFLOW(c)) { + trace->count_hw_overflow++; + } + + if (!(trace->unknown_opcodes[c / 8] & (1 << c % 8))) + WLOG("Unknown opcode 0x%02x\n", c); + trace->unknown_opcodes[c / 8] |= (1 << c % 8); + + trace->count_error++; + return TRACE_OP_GET_CONTINUATION(c) ? TRACE_STATE_SKIP_FRAME + : TRACE_STATE_IDLE; } -static trace_state update_trace(st_trace_t* trace, uint8_t c) { - trace->count_raw_bytes++; +static trace_state update_trace(st_trace_t *trace, uint8_t c) { + trace->count_raw_bytes++; - // Parse the input using a state machine. + // Parse the input using a state machine. - if (trace->state == TRACE_STATE_UNKNOWN) { - if (TRACE_OP_IS_TARGET_SOURCE(c) || TRACE_OP_IS_LOCAL_TIME(c) || TRACE_OP_IS_GLOBAL_TIME(c)) - trace->state = TRACE_STATE_IDLE; - } + if (trace->state == TRACE_STATE_UNKNOWN) { + if (TRACE_OP_IS_TARGET_SOURCE(c) || TRACE_OP_IS_LOCAL_TIME(c) || + TRACE_OP_IS_GLOBAL_TIME(c)) + trace->state = TRACE_STATE_IDLE; + } - switch (trace->state) - { - case TRACE_STATE_IDLE: - return update_trace_idle(trace, c); + switch (trace->state) { + case TRACE_STATE_IDLE: + return update_trace_idle(trace, c); - case TRACE_STATE_TARGET_SOURCE: - putchar(c); - if (c == '\n') - fflush(stdout); - trace->count_target_data++; - return TRACE_STATE_IDLE; + case TRACE_STATE_TARGET_SOURCE: + putchar(c); + if (c == '\n') + fflush(stdout); + trace->count_target_data++; + return TRACE_STATE_IDLE; - case TRACE_STATE_SKIP_FRAME: - return TRACE_OP_GET_CONTINUATION(c) ? TRACE_STATE_SKIP_FRAME : TRACE_STATE_IDLE; + case TRACE_STATE_SKIP_FRAME: + return TRACE_OP_GET_CONTINUATION(c) ? TRACE_STATE_SKIP_FRAME + : TRACE_STATE_IDLE; - case TRACE_STATE_SKIP_4: - return TRACE_STATE_SKIP_3; + case TRACE_STATE_SKIP_4: + return TRACE_STATE_SKIP_3; - case TRACE_STATE_SKIP_3: - return TRACE_STATE_SKIP_2; + case TRACE_STATE_SKIP_3: + return TRACE_STATE_SKIP_2; - case TRACE_STATE_SKIP_2: - return TRACE_STATE_SKIP_1; + case TRACE_STATE_SKIP_2: + return TRACE_STATE_SKIP_1; - case TRACE_STATE_SKIP_1: - return TRACE_STATE_IDLE; + case TRACE_STATE_SKIP_1: + return TRACE_STATE_IDLE; - case TRACE_STATE_UNKNOWN: - return TRACE_STATE_UNKNOWN; + case TRACE_STATE_UNKNOWN: + return TRACE_STATE_UNKNOWN; - default: - ELOG("Invalid state %d. This should never happen\n", trace->state); - return TRACE_STATE_IDLE; - } + default: + ELOG("Invalid state %d. This should never happen\n", trace->state); + return TRACE_STATE_IDLE; + } } -static bool read_trace(stlink_t* stlink, st_trace_t* trace) { - uint8_t buffer[STLINK_TRACE_BUF_LEN]; - int length = stlink_trace_read(stlink, buffer, sizeof(buffer)); - - if (length < 0) { - ELOG("Error reading trace (%d)\n", length); - return false; - } - - if (length == 0) { - usleep(100); - return true; - } - - if (length == sizeof(buffer)) { - if (trace->count_sw_overflow++) - DLOG("Buffer overflow.\n"); - else - WLOG("Buffer overflow. Try using a slower trace frequency.\n"); - trace->state = TRACE_STATE_UNKNOWN; - } +static bool read_trace(stlink_t *stlink, st_trace_t *trace) { + uint8_t buffer[STLINK_TRACE_BUF_LEN]; + int length = stlink_trace_read(stlink, buffer, sizeof(buffer)); - for (int i = 0; i < length; i++) { - trace->state = update_trace(trace, buffer[i]); - } + if (length < 0) { + ELOG("Error reading trace (%d)\n", length); + return false; + } + if (length == 0) { + usleep(100); return true; -} - -static void check_for_configuration_error(stlink_t* stlink, st_trace_t* trace, uint32_t trace_frequency) { - // Only check configuration one time after the first 10 seconds of running. - time_t elapsed_time_s = time(NULL) - trace->start_time; - if (trace->configuration_checked || elapsed_time_s < 10) { - return; - } - trace->configuration_checked = true; + } - // Simple huristic to determine if we are configured poorly. - bool error_no_data = (trace->count_raw_bytes < 100); - bool error_low_data = (trace->count_time_packets < 10 && trace->count_target_data < 1000); - bool error_bad_data = (trace->count_error > 1 || trace->unknown_sources > 0); - bool error_dropped_data = (trace->count_sw_overflow > 0); + if (length == sizeof(buffer)) { + if (trace->count_sw_overflow++) + DLOG("Buffer overflow.\n"); + else + WLOG("Buffer overflow. Try using a slower trace frequency.\n"); + trace->state = TRACE_STATE_UNKNOWN; + } - if (!error_no_data && !error_low_data && !error_bad_data && !error_dropped_data) - return; - - WLOG("****\n"); - WLOG("We do not appear to be retrieving data from the stlink correctly.\n"); - - if (error_dropped_data) { - WLOG("Try setting a slower trace frequency with the --trace=%d command line option.\n", trace_frequency / 2); - } + for (int i = 0; i < length; i++) { + trace->state = update_trace(trace, buffer[i]); + } - if (error_no_data || error_low_data || error_bad_data) { - uint32_t prescaler; - stlink_read_debug32(stlink, STLINK_REG_TPI_ACPR, &prescaler); - if (prescaler) { - uint32_t system_clock_speed = (prescaler + 1) * trace_frequency; - uint32_t system_clock_speed_mhz = (system_clock_speed + 500000) / 1000000; - WLOG("Verify the system clock is running at %d MHz.\n", system_clock_speed_mhz); - } - WLOG("Try specifying the system clock with the --clock=XX command line option.\n"); - WLOG("Try setting the trace speed in your device's clock initialization routine:\n"); - WLOG(" TPI->ACPR = HAL_RCC_GetHCLKFreq() / %d - 1;\n", trace_frequency); - } + return true; +} - WLOG("Diagnostic Information:\n"); - WLOG("Raw Bytes: %d\n", trace->count_raw_bytes); - WLOG("Target Data: %d\n", trace->count_target_data); - WLOG("Time Packets: %d\n", trace->count_time_packets); - WLOG("Hardware Overflow Count: %d\n", trace->count_hw_overflow); - WLOG("Software Overflow Count: %d\n", trace->count_sw_overflow); - WLOG("Errors: %d\n", trace->count_error); - - char buffer[1024]; - memset(buffer, 0, sizeof(buffer)); - uint32_t offset = 0; - for (uint32_t i = 0; i <= 0xFF; i++) - if (trace->unknown_opcodes[i / 8] & (1 << i % 8)) - offset += snprintf(buffer + offset, sizeof(buffer) - offset, "%02x, ", i); - WLOG("Unknown Opcodes: %s\n", buffer); - - memset(buffer, 0, sizeof(buffer)); - offset = 0; - for (uint32_t i = 0; i < 32; i++) - if (trace->unknown_sources & (1 << i)) - offset += snprintf(buffer + offset, sizeof(buffer) - offset, "%d, ", i); - WLOG("Unknown Sources: %s\n", buffer); - - WLOG("Chip ID: 0x%04x\n", stlink->chip_id); - WLOG("****\n"); +static void check_for_configuration_error(stlink_t *stlink, st_trace_t *trace, + uint32_t trace_frequency) { + // Only check configuration one time after the first 10 seconds of running. + time_t elapsed_time_s = time(NULL) - trace->start_time; + if (trace->configuration_checked || elapsed_time_s < 10) { + return; + } + trace->configuration_checked = true; + + // Simple huristic to determine if we are configured poorly. + bool error_no_data = (trace->count_raw_bytes < 100); + bool error_low_data = + (trace->count_time_packets < 10 && trace->count_target_data < 1000); + bool error_bad_data = (trace->count_error > 1 || trace->unknown_sources > 0); + bool error_dropped_data = (trace->count_sw_overflow > 0); + + if (!error_no_data && !error_low_data && !error_bad_data && + !error_dropped_data) + return; + + WLOG("****\n"); + WLOG("We do not appear to be retrieving data from the stlink correctly.\n"); + + if (error_dropped_data) { + WLOG("Try setting a slower trace frequency with the --trace=%d command " + "line option.\n", + trace_frequency / 2); + } + + if (error_no_data || error_low_data || error_bad_data) { + uint32_t prescaler; + stlink_read_debug32(stlink, STLINK_REG_TPI_ACPR, &prescaler); + if (prescaler) { + uint32_t system_clock_speed = (prescaler + 1) * trace_frequency; + uint32_t system_clock_speed_mhz = (system_clock_speed + 500000) / 1000000; + WLOG("Verify the system clock is running at %d MHz.\n", + system_clock_speed_mhz); + } + WLOG("Try specifying the system clock with the --clock=XX command line " + "option.\n"); + WLOG("Try setting the trace speed in your device's clock initialization " + "routine:\n"); + WLOG(" TPI->ACPR = HAL_RCC_GetHCLKFreq() / %d - 1;\n", trace_frequency); + } + + WLOG("Diagnostic Information:\n"); + WLOG("Raw Bytes: %d\n", trace->count_raw_bytes); + WLOG("Target Data: %d\n", trace->count_target_data); + WLOG("Time Packets: %d\n", trace->count_time_packets); + WLOG("Hardware Overflow Count: %d\n", trace->count_hw_overflow); + WLOG("Software Overflow Count: %d\n", trace->count_sw_overflow); + WLOG("Errors: %d\n", trace->count_error); + + char buffer[1024]; + memset(buffer, 0, sizeof(buffer)); + uint32_t offset = 0; + for (uint32_t i = 0; i <= 0xFF; i++) + if (trace->unknown_opcodes[i / 8] & (1 << i % 8)) { + uint32_t n = + snprintf(buffer + offset, sizeof(buffer) - offset, "%02x, ", i); + if (n >= sizeof(buffer) - offset) { + break; + } + offset += n; + } + WLOG("Unknown Opcodes: %s\n", buffer); + + memset(buffer, 0, sizeof(buffer)); + offset = 0; + for (uint32_t i = 0; i < 32; i++) + if (trace->unknown_sources & (1 << i)) { + uint32_t n = + snprintf(buffer + offset, sizeof(buffer) - offset, "%d, ", i); + if (n >= sizeof(buffer) - offset) { + break; + } + offset += n; + } + WLOG("Unknown Sources: %s\n", buffer); + + WLOG("Chip ID: 0x%04x\n", stlink->chip_id); + WLOG("****\n"); } -int main(int argc, char** argv) -{ +int main(int argc, char **argv) { #if defined(_WIN32) - SetConsoleCtrlHandler((PHANDLER_ROUTINE)CtrlHandler, TRUE); + SetConsoleCtrlHandler((PHANDLER_ROUTINE)CtrlHandler, TRUE); #else - signal(SIGINT, &abort_trace); - signal(SIGTERM, &abort_trace); - signal(SIGSEGV, &abort_trace); - signal(SIGPIPE, &abort_trace); + signal(SIGINT, &abort_trace); + signal(SIGTERM, &abort_trace); + signal(SIGSEGV, &abort_trace); + signal(SIGPIPE, &abort_trace); #endif + st_settings_t settings; + if (!parse_options(argc, argv, &settings)) { + usage(); + return APP_RESULT_INVALID_PARAMS; + } + + DLOG("show_help = %s\n", settings.show_help ? "true" : "false"); + DLOG("show_version = %s\n", settings.show_version ? "true" : "false"); + DLOG("logging_level = %d\n", settings.logging_level); + DLOG("core_frequency = %d Hz\n", settings.core_frequency); + DLOG("trace_frequency = %d Hz\n", settings.trace_frequency); + DLOG("reset_board = %s\n", settings.reset_board ? "true" : "false"); + DLOG("force = %s\n", settings.force ? "true" : "false"); + DLOG("serial_number = %s\n", + settings.serial_number ? settings.serial_number : "any"); + + if (settings.show_help) { + usage(); + return APP_RESULT_SUCCESS; + } - st_settings_t settings; - if (!parse_options(argc, argv, &settings)) { - usage(); - return APP_RESULT_INVALID_PARAMS; - } - - DLOG("show_help = %s\n", settings.show_help ? "true" : "false"); - DLOG("show_version = %s\n", settings.show_version ? "true" : "false"); - DLOG("logging_level = %d\n", settings.logging_level); - DLOG("core_frequency = %d Hz\n", settings.core_frequency); - DLOG("trace_frequency = %d Hz\n", settings.trace_frequency); - DLOG("reset_board = %s\n", settings.reset_board ? "true" : "false"); - DLOG("force = %s\n", settings.force ? "true" : "false"); - DLOG("serial_number = %s\n", settings.serial_number ? settings.serial_number : "any"); - - if (settings.show_help) { - usage(); - return APP_RESULT_SUCCESS; - } - - if (settings.show_version) { - printf("v%s\n", STLINK_VERSION); - return APP_RESULT_SUCCESS; - } - - stlink_t* stlink = stlink_connect(&settings); - if (!stlink) { - ELOG("Unable to locate an stlink\n"); - return APP_RESULT_STLINK_NOT_FOUND; - } - - stlink->verbose = settings.logging_level; - - if (stlink->chip_id == STLINK_CHIPID_UNKNOWN) { - ELOG("Your stlink is not connected to a device\n"); - if (!settings.force) - return APP_RESULT_STLINK_MISSING_DEVICE; - } - - if (!(stlink->version.flags & STLINK_F_HAS_TRACE)) { - ELOG("Your stlink does not support tracing\n"); - if (!settings.force) - return APP_RESULT_STLINK_UNSUPPORTED_LINK; - } - - if (!(stlink->chip_flags & CHIP_F_HAS_SWO_TRACING)) { - const struct stlink_chipid_params *params = stlink_chipid_get_params(stlink->chip_id); - ELOG("We do not support SWO output for device '%s'\n", params->description); - if (!settings.force) - return APP_RESULT_STLINK_UNSUPPORTED_DEVICE; - } - - uint32_t trace_frequency = settings.trace_frequency; - if (!trace_frequency) - trace_frequency = STLINK_DEFAULT_TRACE_FREQUENCY; - if (trace_frequency > stlink->max_trace_freq) { - ELOG("Invalid trace frequency %d (max %d)\n", trace_frequency, stlink->max_trace_freq); - if (!settings.force) - return APP_RESULT_UNSUPPORTED_TRACE_FREQUENCY; - } - - if (!enable_trace(stlink, &settings, trace_frequency)) { - ELOG("Unable to enable trace mode\n"); - if (!settings.force) - return APP_RESULT_STLINK_STATE_ERROR; - } - - ILOG("Reading Trace\n"); - st_trace_t trace; - memset(&trace, 0, sizeof(trace)); - trace.start_time = time(NULL); - - if (stlink_run(stlink, RUN_NORMAL)) { - ELOG("Unable to run device\n"); - if (!settings.force) - return APP_RESULT_STLINK_STATE_ERROR; - } - - while (!g_abort_trace && read_trace(stlink, &trace)) { - check_for_configuration_error(stlink, &trace, trace_frequency); - } - - stlink_trace_disable(stlink); - stlink_close(stlink); - + if (settings.show_version) { + printf("v%s\n", STLINK_VERSION); return APP_RESULT_SUCCESS; + } + + stlink_t *stlink = stlink_connect(&settings); + if (!stlink) { + ELOG("Unable to locate an stlink\n"); + return APP_RESULT_STLINK_NOT_FOUND; + } + + stlink->verbose = settings.logging_level; + + if (stlink->chip_id == STLINK_CHIPID_UNKNOWN) { + ELOG("Your stlink is not connected to a device\n"); + if (!settings.force) + return APP_RESULT_STLINK_MISSING_DEVICE; + } + + if (!(stlink->version.flags & STLINK_F_HAS_TRACE)) { + ELOG("Your stlink does not support tracing\n"); + if (!settings.force) + return APP_RESULT_STLINK_UNSUPPORTED_LINK; + } + + if (!(stlink->chip_flags & CHIP_F_HAS_SWO_TRACING)) { + const struct stlink_chipid_params *params = + stlink_chipid_get_params(stlink->chip_id); + ELOG("We do not support SWO output for device '%s'\n", params->description); + if (!settings.force) + return APP_RESULT_STLINK_UNSUPPORTED_DEVICE; + } + + uint32_t trace_frequency = settings.trace_frequency; + if (!trace_frequency) + trace_frequency = STLINK_DEFAULT_TRACE_FREQUENCY; + if (trace_frequency > stlink->max_trace_freq) { + ELOG("Invalid trace frequency %d (max %d)\n", trace_frequency, + stlink->max_trace_freq); + if (!settings.force) + return APP_RESULT_UNSUPPORTED_TRACE_FREQUENCY; + } + + if (!enable_trace(stlink, &settings, trace_frequency)) { + ELOG("Unable to enable trace mode\n"); + if (!settings.force) + return APP_RESULT_STLINK_STATE_ERROR; + } + + ILOG("Reading Trace\n"); + st_trace_t trace; + memset(&trace, 0, sizeof(trace)); + trace.start_time = time(NULL); + + if (stlink_run(stlink, RUN_NORMAL)) { + ELOG("Unable to run device\n"); + if (!settings.force) + return APP_RESULT_STLINK_STATE_ERROR; + } + + while (!g_abort_trace && read_trace(stlink, &trace)) { + check_for_configuration_error(stlink, &trace, trace_frequency); + } + + stlink_trace_disable(stlink); + stlink_close(stlink); + + return APP_RESULT_SUCCESS; } diff --git a/src/stlink-lib/logging.c b/src/stlink-lib/logging.c index ce0a2baab..87978230d 100644 --- a/src/stlink-lib/logging.c +++ b/src/stlink-lib/logging.c @@ -1,12 +1,13 @@ /* * UglyLogging * - * Slow, yet another wheel reinvented, but enough to make the rest of our code pretty enough. + * Slow, yet another wheel reinvented, but enough to make the rest of our code + * pretty enough. */ +#include #include #include #include -#include #include #include "logging.h" @@ -14,77 +15,89 @@ static int max_level = UDEBUG; int ugly_init(int maximum_threshold) { - max_level = maximum_threshold; - return(0); + max_level = maximum_threshold; + return (0); } int ugly_log(int level, const char *tag, const char *format, ...) { - if (level > max_level) { - return(0); - } + if (level > max_level) { + return (0); + } - fflush(stdout); // flush to maintain order of streams + fflush(stdout); // flush to maintain order of streams - va_list args; - va_start(args, format); - time_t mytt = time(NULL); - struct tm *tt; - tt = localtime(&mytt); - fprintf(stderr, "%d-%02d-%02dT%02d:%02d:%02d ", tt->tm_year + 1900, tt->tm_mon + 1, - tt->tm_mday, tt->tm_hour, tt->tm_min, tt->tm_sec); + va_list args; + va_start(args, format); + time_t mytt = time(NULL); + struct tm *tt; + tt = localtime(&mytt); + fprintf(stderr, "%d-%02d-%02dT%02d:%02d:%02d ", tt->tm_year + 1900, + tt->tm_mon + 1, tt->tm_mday, tt->tm_hour, tt->tm_min, tt->tm_sec); - switch (level) { - case UDEBUG: - fprintf(stderr, "DEBUG %s: ", tag); - break; - case UINFO: - fprintf(stderr, "INFO %s: ", tag); - break; - case UWARN: - fprintf(stderr, "WARN %s: ", tag); - break; - case UERROR: - fprintf(stderr, "ERROR %s: ", tag); - break; - default: - fprintf(stderr, "%d %s: ", level, tag); - break; - } + switch (level) { + case UDEBUG: + fprintf(stderr, "DEBUG %s: ", tag); + break; + case UINFO: + fprintf(stderr, "INFO %s: ", tag); + break; + case UWARN: + fprintf(stderr, "WARN %s: ", tag); + break; + case UERROR: + fprintf(stderr, "ERROR %s: ", tag); + break; + default: + fprintf(stderr, "%d %s: ", level, tag); + break; + } - vfprintf(stderr, format, args); - fflush(stderr); - va_end(args); - return(1); + vfprintf(stderr, format, args); + fflush(stderr); + va_end(args); + return (1); } /* * Log message levels. - * - LIBUSB_LOG_LEVEL_NONE (0) : no messages ever printed by the library (default) + * - LIBUSB_LOG_LEVEL_NONE (0) : no messages ever printed by the library + * (default) * - LIBUSB_LOG_LEVEL_ERROR (1) : error messages are printed to stderr - * - LIBUSB_LOG_LEVEL_WARNING (2) : warning and error messages are printed to stderr - * - LIBUSB_LOG_LEVEL_INFO (3) : informational messages are printed to stderr - * - LIBUSB_LOG_LEVEL_DEBUG (4) : debug and informational messages are printed to stderr + * - LIBUSB_LOG_LEVEL_WARNING (2) : warning and error messages are printed to + * stderr + * - LIBUSB_LOG_LEVEL_INFO (3) : informational messages are printed to + * stderr + * - LIBUSB_LOG_LEVEL_DEBUG (4) : debug and informational messages are + * printed to stderr */ int ugly_libusb_log_level(enum ugly_loglevel v) { #ifdef __FreeBSD__ - // FreeBSD includes its own reimplementation of libusb. - // Its libusb_set_debug() function expects a lib_debug_level - // instead of a lib_log_level and is verbose enough to drown out - // all other output. - switch (v) { - case UDEBUG: return (3); // LIBUSB_DEBUG_FUNCTION + LIBUSB_DEBUG_TRANSFER - case UINFO: return (1); // LIBUSB_DEBUG_FUNCTION only - case UWARN: return (0); // LIBUSB_DEBUG_NO - case UERROR: return (0); // LIBUSB_DEBUG_NO - } - return (0); + // FreeBSD includes its own reimplementation of libusb. + // Its libusb_set_debug() function expects a lib_debug_level + // instead of a lib_log_level and is verbose enough to drown out + // all other output. + switch (v) { + case UDEBUG: + return (3); // LIBUSB_DEBUG_FUNCTION + LIBUSB_DEBUG_TRANSFER + case UINFO: + return (1); // LIBUSB_DEBUG_FUNCTION only + case UWARN: + return (0); // LIBUSB_DEBUG_NO + case UERROR: + return (0); // LIBUSB_DEBUG_NO + } + return (0); #else - switch (v) { - case UDEBUG: return (4); - case UINFO: return (3); - case UWARN: return (2); - case UERROR: return (1); - } + switch (v) { + case UDEBUG: + return (4); + case UINFO: + return (3); + case UWARN: return (2); + case UERROR: + return (1); + } + return (2); #endif } From 553590b31b91f6edaafd75c895f0e87163037b42 Mon Sep 17 00:00:00 2001 From: "R.E. Wolff" Date: Fri, 16 Apr 2021 19:09:06 +0200 Subject: [PATCH 238/503] chipid in files code --- src/st-util/gdb-server.c | 1 + src/stlink-lib/chipid.c | 192 ++++++++++++++++++++++++++++++++++++++- src/stlink-lib/chipid.h | 5 +- 3 files changed, 194 insertions(+), 4 deletions(-) diff --git a/src/st-util/gdb-server.c b/src/st-util/gdb-server.c index 006a0e3aa..797f4391b 100644 --- a/src/st-util/gdb-server.c +++ b/src/st-util/gdb-server.c @@ -220,6 +220,7 @@ int main(int argc, char** argv) { parse_options(argc, argv, &state); printf("st-util\n"); + init_chipids (NULL); sl = stlink_open_usb(state.logging_level, state.connect_mode, state.serialnumber, state.freq); if (sl == NULL) { return(1); } diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index 221234bbb..e51e00201 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -1,7 +1,14 @@ #include #include "chipid.h" -static const struct stlink_chipid_params devices[] = { +#include +#include +#include +#include +#include +#include + +static struct stlink_chipid_params devices[] = { { // RM0410 document was used to find these paramaters .chip_id = STLINK_CHIPID_STM32_F7XXXX, @@ -711,8 +718,9 @@ static const struct stlink_chipid_params devices[] = { }, }; -const struct stlink_chipid_params *stlink_chipid_get_params(uint32_t chipid) { - const struct stlink_chipid_params *params = NULL; + +struct stlink_chipid_params *stlink_chipid_get_params_old(uint32_t chipid) { + struct stlink_chipid_params *params = NULL; for (size_t n = 0; n < STLINK_ARRAY_SIZE(devices); n++) if (devices[n].chip_id == chipid) { @@ -722,3 +730,181 @@ const struct stlink_chipid_params *stlink_chipid_get_params(uint32_t chipid) { return(params); } + +struct stlink_chipid_params *devicelist; + + + +void dump_a_chip (FILE *fp, struct stlink_chipid_params *dev) +{ + fprintf (fp, "# Chipid file for %s\n", dev->description); + fprintf (fp, "#\n"); + fprintf (fp, "chip_id %x\n", dev->chip_id); + fprintf (fp, "description %s\n", dev->description); + fprintf (fp, "flash_type %x\n", dev->flash_type); + fprintf (fp, "flash_pagesize %x\n", dev->flash_pagesize); + fprintf (fp, "sram_size %x\n", dev->sram_size); + fprintf (fp, "bootrom_base %x\n", dev->bootrom_base); + fprintf (fp, "bootrom_size %x\n", dev->bootrom_size); + fprintf (fp, "option_base %x\n", dev->option_base); + fprintf (fp, "option_size %x\n", dev->option_size); + fprintf (fp, "flags %x\n\n", dev->flags); +} + + + +struct stlink_chipid_params *stlink_chipid_get_params(uint32_t chipid) { + struct stlink_chipid_params *params = NULL; + struct stlink_chipid_params *p2; + + // fprintf (stderr, "getparams: %x\n", chipid); + for (params = devicelist ; params != NULL ; params = params -> next) + if (params->chip_id == chipid) break; + + p2 = stlink_chipid_get_params_old (chipid); + + if (memcmp (p2, params, sizeof (struct stlink_chipid_params) - sizeof (struct stlink_chipid_params *)) != 0) { + //fprintf (stderr, "Error, chipid params not identical\n"); + //return NULL; + fprintf (stderr, "---------- old ------------\n"); + dump_a_chip (stderr, p2); + fprintf (stderr, "---------- new ------------\n"); + dump_a_chip (stderr, params); + } + return(params); +} + + +void process_chipfile (char *fname) +{ + FILE *fp; + char *p, buf[1025]; + char word[64], value[64]; + struct stlink_chipid_params *ts; + int nc; + + fprintf (stderr, "processing chipfile %s.\n", fname); + fp = fopen (fname, "r"); + if (!fp) { + perror (fname); + return; + } + + ts = calloc (sizeof (struct stlink_chipid_params), 1); + while (fgets (buf, 1024, fp) != NULL) { + for (p=buf;isspace (*p);p++); + if (!*p) continue; // we hit end-of-line wiht only whitespace + if (*p == '#') continue; // ignore comments. + + sscanf (p, "%s %s", word, value); + if (strcmp (word, "chip_id") == 0) { + sscanf (value, "%x", &ts->chip_id); + } else if (strcmp (word, "description") == 0) { + //ts->description = strdup (value); + buf[strlen(p)-1] = 0; // chomp newline + sscanf (p, "%*s %n", &nc); + ts->description = strdup (p+nc); + } else if (strcmp (word, "flash_type") == 0) { + sscanf (value, "%x", &ts->flash_type); + } else if (strcmp (word, "flash_size_reg") == 0) { + sscanf (value, "%x", &ts->flash_size_reg); + } else if (strcmp (word, "flash_pagesize") == 0) { + sscanf (value, "%x", &ts->flash_pagesize); + } else if (strcmp (word, "sram_size") == 0) { + sscanf (value, "%x", &ts->sram_size); + } else if (strcmp (word, "bootrom_base") == 0) { + sscanf (value, "%x", &ts->bootrom_base); + } else if (strcmp (word, "bootrom_size") == 0) { + sscanf (value, "%x", &ts->bootrom_size); + } else if (strcmp (word, "option_base") == 0) { + sscanf (value, "%x", &ts->option_base); + } else if (strcmp (word, "option_size") == 0) { + sscanf (value, "%x", &ts->option_size); + } else if (strcmp (word, "flags") == 0) { + sscanf (value, "%x", &ts->flags); + } else { + fprintf (stderr, "Unknown keyword in %s: %s\n", + fname, word); + } + } + ts->next = devicelist; + devicelist = ts; +} + + +void dump_chips (void) +{ + struct stlink_chipid_params *ts; + char *p, buf[100]; + FILE *fp; + + for (size_t n = 0; n < STLINK_ARRAY_SIZE(devices); n++) { + ts = &devices[n]; + + strcpy (buf, ts->description); + while ((p = strchr (buf, '/'))) // change slashes to underscore. + *p = '_'; + strcat (buf, ".chip"); + fp = fopen (buf, "w"); + fprintf (fp, "# Chipid file for %s\n", ts->description); + fprintf (fp, "#\n"); + fprintf (fp, "chip_id %x\n", ts->chip_id); + fprintf (fp, "description %s\n", ts->description); + fprintf (fp, "flash_type %x\n", ts->flash_type); + fprintf (fp, "flash_pagesize %x\n", ts->flash_pagesize); + fprintf (fp, "sram_size %x\n", ts->sram_size); + fprintf (fp, "bootrom_base %x\n", ts->bootrom_base); + fprintf (fp, "bootrom_size %x\n", ts->bootrom_size); + fprintf (fp, "option_base %x\n", ts->option_base); + fprintf (fp, "option_size %x\n", ts->option_size); + fprintf (fp, "flags %x\n\n", ts->flags); + fclose (fp); + } +} + + + +void init_chipids (char *dir_to_scan) +{ + DIR *d; + int nl; // namelen + struct dirent *dir; + if (!dir_to_scan) dir_to_scan = "./"; + + devicelist = NULL; + fprintf (stderr, "stlink_chipid_params %ld\n", sizeof (struct stlink_chipid_params)); + //dump_chips (); + d = opendir("."); + if (d) { + while ((dir = readdir(d)) != NULL) { + nl = strlen (dir->d_name); + if (strcmp (dir->d_name + nl - 5, ".chip") == 0) { + char buf[1024]; + sprintf (buf, "%s/%s", dir_to_scan, dir->d_name); + process_chipfile (buf); + } + } + closedir(d); + } else { + perror (dir_to_scan); + return; // XXX + } +#if 0 + { + struct stlink_chipid_params *p, *op; + int i; + p = devicelist; + for (i=0;i<5;i++, p = p->next) { + op = stlink_chipid_get_params_old (p->chip_id); + fprintf (stderr, "---------- old ------------\n"); + dump_a_chip (stderr, op); + fprintf (stderr, "---------- new ------------\n"); + dump_a_chip (stderr, p); + + } + } +#endif +} + + + diff --git a/src/stlink-lib/chipid.h b/src/stlink-lib/chipid.h index f790e7899..d398b5c97 100644 --- a/src/stlink-lib/chipid.h +++ b/src/stlink-lib/chipid.h @@ -87,9 +87,12 @@ struct stlink_chipid_params { uint32_t option_base; uint32_t option_size; uint32_t flags; + struct stlink_chipid_params * next; }; -const struct stlink_chipid_params *stlink_chipid_get_params(uint32_t chipid); + +struct stlink_chipid_params *stlink_chipid_get_params(uint32_t chipid); + void init_chipids (char *dir_to_scan); #ifdef __cplusplus } From 9396e4ee1e03b427b4ec501dabce8d4eb6952089 Mon Sep 17 00:00:00 2001 From: "R.E. Wolff" Date: Fri, 16 Apr 2021 19:11:57 +0200 Subject: [PATCH 239/503] Added chips.zip --- src/chips.zip | Bin 0 -> 16336 bytes 1 file changed, 0 insertions(+), 0 deletions(-) create mode 100644 src/chips.zip diff --git a/src/chips.zip b/src/chips.zip new file mode 100644 index 0000000000000000000000000000000000000000..e11e5cc6a4b9adb265d7aacbd718588f4720ae12 GIT binary patch literal 16336 zcmb7KcRbbK|F`!ZB_o?;T`sPX>@7)l8Cj7Xa?R{bLUt+{Wkgo83aM<8oe|Z?EFwbq zy|2Ew?^~ar`_bdv^2dFi^X#1SI+JpGe;;@lj2M=-b}nv$ zdb)%d*m|{I=JWMl<{ofj3{0FEYz&OO4{hN4G{83qF!1ig>l8+YulfSNRRV+j;QN{) zI&c95)E*E5k^3G6cL@Qt~x%CyfrCqzwtuiu^Y zgqv`-#qeE{9SC{0vlBv=mu<4VEepZVNO;A!DQ+`fS1j-5owg)^F=0QN~=EHrH(d$NPx^CZSk9dI3SA3`9a12LG=l-bd9O zt5a4@RAaEc8{eA!WA(Kz&hFRx-H)E|dlpeA6*5l*Tlrodpp|sd%b45R!OQCZoT{Gm zk7@YuoK;&g-STR#mCC?Ri#n=6o7z<6s|A5_IaWp;=69B5Z$9Z9lESh(zBQv#oY&p@ z2#y2C29s!L_YLy_2$X|JXo?6OP2yav99b}g1m~N7DCb#%kQ&YAwA~1rU_1y}>3o{8H+v;jo6|+)PTJ`FxQ_N5preeKertZp? z2>aM6QOY=|%~QkV)1Tl$>L=2aoHq8NcP9>n2rCT+*53&X zx`WfCBEq6@#ohX<^K~zN=#j_D1UOdBEWeLc5plAr{h-k*okhY4b`GWsu-RGrocMR2 zeRdnaxfsfmK(8AT8d04UC3_N|QeoyjV_r~O9M~Xjo_8jfLL+|A>`h^NG`|mr;!5t! zna@jHBIe%N1v%fwVXgIc<^>CaAgUR}UE3*MMK%9@L= z0HG>ioH!um;biaR?CHc}WqrfW()wstF&ae85E8}pv!N`l{J8T@r6jU&HiowTX*;nMaB8h~j4Mk6KWrrwNQm51=ALA}x^ik4Y z&Y2S?^1Fa-=Ttep-ci4Ntv-=AF8S8RO$l3f$qc2E4NNcx3*zlpfx!A-0fXj%gQf@+ zZl)^7{RrjkCTI?+v&i&qcgATlnC9`}$6>*+(BDA(EM9%^8U+ z`SU*p?CRxlohCZY&TSH6M{2Nsd3jG``YLZ?>m`m?gZHwT)S6OC^@uozTWGFddy^%> zZK~-Uy7aZ)z~EBN7s%zft|GhhMyLHUV}r;8n89>h++tWVc;>MxvWK1#r!g}+SSSrFcTA|aMgKN=uhLfZzvv;)1 zs0n2Vd~#*WNb`Et^cXGpB=DeytnVAXJaZg>e(b4qL$P3`UcDAqBl}BgFg<)Wwq`g$ z4JDpIQR5j45aCgxJ2({F4wT&OZSvODJkgn{ zc6Qd6v!gnx7d9d%H|ZZrIPB!#V&iQ8^5#B4a>R};b$5z-&KRTd0{KwU$88v|xTPtW z18L#nZl0zO29jyzr_oqNFyw`V)kf(3tONIk*txO7&A{x>$l0L8=v^anF$!L!sE8csDyC(ALpuHTy(7C)hM&N7xmAe=ygnM=x0@& zp50R))u$$K5(m_UmHP-hTGF0d#n~vc&fImoQBzdR&=oh@2iv;Xx9MwyiFc;?-6C-khDW zo4cGZ8b_%tQhUPh^td%W7~Ha(sb!*fv4&coF_TJFy-Xy8-(V1DR?NpG!^S$|9DRd} z@VtDnx@^LjX1~gpOgQu*ZPS3y4;9|qGFQVrc~lDrwkIDvU!UfCgo$$EOxolo5w`}M ziy6p^iXOQwh+J$xJ`2VlQ*a$UncYqy`Vf1BFwJ3MHsh7f%w8(?(@^4j%&SYX2_fCJ zl|7BR6}%11d>wN6uY}6$y3)i-3fomkBAQdO&4Rv5O}5Zsr~mp&zn1s?R6^o{)2cBM z+h#d`ogVw*=MMk(HWzOmYvDz``J>-oVIeXA)LR2X+!`3-)`+8VYmnHG_YkTkKB=7% zl7AmVW=k#XG|~qP3(CzP|F#TdmS!C7A$<0VTDZ(svpR3yyW&aG*-zT{ni1wbvb>`HZ{%Paem>7j*k>{UTe5u zM?8a;a1tdqbNRHMi8yF=z(9&;B51`kAu=GH!P)X@QQN_w%gMQw^*FCwdU?E%nyzwxZxrHGSxa=A-_5_9wjZWk*^C=hB{AhdbQSpD5>f_(#@%^S<$UKY&IpFb+3G z6P-;#M6vygUo9)7H&pwB>|7w3CYDy;ES7YAZaSiHNtl@Q`}mfcssvMw>g+;;0=8xE z6Zoj<6(UKlxU|n3ckO=ERR4;?TwZ%P^UwWXWJ3(VZTWJ#5|@;OO``P+UWpRr?Tu%m z3uNp+K6TXWBvqEZ87=xVWhS5a@F4(TfQZP4F-%zmh+)b=dWO!;KcFHWfSdlvp882I z&CE-VNs+q(J$=#r6ebP3rr&w%IvKqbr#M;En!3bBAD1uU(UR1<)mHqVeSKeHD%I$# z3@N|q)f8qSmMXI-f1qDHx-S2;F=tnJ7;EsyODoiu6 zld9uSuxdKRYxzFL^E#O%UEx~)y)9x*2g_t#MP?PILGx(A?pG1p;X0|qR#)q&49PN_ zUD(*@bTtM#$s6fRVib4Rp7q^u?Pz#^&HG-5J~e6#hHvp9N=d~1Kzbk{|KWkWfGA%S zccok81cqiNc+X|aGEt|z#!CTZV1$2xyrLVUaEM5nXaI2Bm7ij zqS&pg=+V>bc6=pU5js6%&phP zH0GiGkNhi(US)RYS8&05;X_t|ji3T9D3u`+hDRPMa282{@BQRGZ1otfMKI^1hvF$~ zKSF!-rHgGma~zjyR1+fjcvCmy`fR-k?Xrc_ z&F^xO)g4KvWOHy?uZI-|GRSCQ!XA_k7 zxu@BAY+=wm;N{{3eBR2H>*0CVn(~4ZR*#~O}BFN@czI8Z_~?L zW@4cLJ46z5?0})Bh=drTHj@)WD+C-o{^UJ|@)hmxiaiM~Tot*0PPMEjt3ilAqI~O{ z%ol^7>BZ03%S;G{aTh)*I6l)l+Ydy6=l#!<3&L(sQ52mYs24mY$kipem_^Yq;|0A? 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Wolff" Date: Fri, 16 Apr 2021 21:15:22 +0200 Subject: [PATCH 240/503] fixed a couple of warnings that macos compiler reports. --- src/stlink-lib/chipid.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index e51e00201..2d4237934 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -731,8 +731,7 @@ struct stlink_chipid_params *stlink_chipid_get_params_old(uint32_t chipid) { return(params); } -struct stlink_chipid_params *devicelist; - +static struct stlink_chipid_params *devicelist; void dump_a_chip (FILE *fp, struct stlink_chipid_params *dev) @@ -867,7 +866,7 @@ void dump_chips (void) void init_chipids (char *dir_to_scan) { DIR *d; - int nl; // namelen + size_t nl; // namelen struct dirent *dir; if (!dir_to_scan) dir_to_scan = "./"; From e4078b118f288d869907f664eb4db42870dd4c33 Mon Sep 17 00:00:00 2001 From: "R.E. Wolff" Date: Fri, 16 Apr 2021 21:25:44 +0200 Subject: [PATCH 241/503] removed unnecessary debug statement that didn't work on windows --- src/stlink-lib/chipid.c | 1 - 1 file changed, 1 deletion(-) diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index 2d4237934..e094f910f 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -871,7 +871,6 @@ void init_chipids (char *dir_to_scan) if (!dir_to_scan) dir_to_scan = "./"; devicelist = NULL; - fprintf (stderr, "stlink_chipid_params %ld\n", sizeof (struct stlink_chipid_params)); //dump_chips (); d = opendir("."); if (d) { From 6993491f90b15581668088a6e522b8fb9a3bb84e Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Wed, 21 Apr 2021 00:00:33 +0200 Subject: [PATCH 242/503] Revert "Updated libusb to v1.0.24" This reverts commit 89a495d169a15f42d8cfd1a68c6738c984d052f8. --- .gitignore | 1 - .travis.sh | 18 +++++++-------- .travis.yml | 24 ++++++++++---------- cmake/modules/Findlibusb.cmake | 6 ++--- cmake/packaging/windows/generate_binaries.sh | 24 ++++++++++---------- 5 files changed, 36 insertions(+), 37 deletions(-) diff --git a/.gitignore b/.gitignore index 82c1195e4..a07eed9ca 100644 --- a/.gitignore +++ b/.gitignore @@ -1,6 +1,5 @@ build build-mingw -build-mingw-* .project .cmake/ diff --git a/.travis.sh b/.travis.sh index 58cea5746..e45cd3609 100755 --- a/.travis.sh +++ b/.travis.sh @@ -8,20 +8,20 @@ echo "----" echo "WORK DIR:$DIR" DIR=$PWD -if [ "$TRAVIS_JOB_NAME" == "linux-mingw-32" ]; then +if [ "$TRAVIS_JOB_NAME" == "linux-mingw-64" ]; then + echo "--> Building for Windows (x86-64) ..." + mkdir -p build-mingw && cd build-mingw-64 + cmake -DCMAKE_SYSTEM_NAME=Windows -DTOOLCHAIN_PREFIX=x86_64-w64-mingw32 \ + -DCMAKE_TOOLCHAIN_FILE=$PWD/../cmake/modules/set_toolchain.cmake -DCMAKE_INSTALL_PREFIX=$PWD/install $DIR + make && rm -rf build-mingw-64 && cd - + +elif [ "$TRAVIS_JOB_NAME" == "linux-mingw-32" ]; then echo "--> Building for Windows (i686) ..." - mkdir -p build-mingw-32 && cd build-mingw-32 + mkdir -p build-mingw && cd build-mingw-32 cmake -DCMAKE_SYSTEM_NAME=Windows -DTOOLCHAIN_PREFIX=i686-w64-mingw32 \ -DCMAKE_TOOLCHAIN_FILE=$PWD/../cmake/modules/set_toolchain.cmake -DCMAKE_INSTALL_PREFIX=$PWD/install $DIR make && rm -rf build-mingw-32 && cd - -# elif [ "$TRAVIS_JOB_NAME" == "linux-mingw-64" ]; then -# echo "--> Building for Windows (x86-64) ..." -# mkdir -p build-mingw-64 && cd build-mingw-64 -# cmake -DCMAKE_SYSTEM_NAME=Windows -DTOOLCHAIN_PREFIX=x86_64-w64-mingw32 \ -# -DCMAKE_TOOLCHAIN_FILE=$PWD/../cmake/modules/set_toolchain.cmake -DCMAKE_INSTALL_PREFIX=$PWD/install $DIR -# make && rm -rf build-mingw-64 && cd - - elif [ "$TRAVIS_OS_NAME" == "linux" ]; then sudo apt-get update -qq || true diff --git a/.travis.yml b/.travis.yml index 307c0bfa0..a733019a1 100644 --- a/.travis.yml +++ b/.travis.yml @@ -6,8 +6,8 @@ jobs: - os: linux dist: focal - env: BADGE=linux-mingw-32 - name: linux-mingw-32 + env: BADGE=linux-mingw-64 + name: linux-mingw compiler: gcc-10 addons: apt: @@ -15,16 +15,16 @@ jobs: packages: ["gcc-10", "libusb-1.0.0-dev", "libgtk-3-dev", "rpm", "mingw-w64"] - # - os: linux - # dist: focal - # env: BADGE=linux-mingw-64 - # name: linux-mingw-64 - # compiler: gcc-10 - # addons: - # apt: - # sources: ["ubuntu-toolchain-r-test"] - # packages: - # ["gcc-10", "libusb-1.0.0-dev", "libgtk-3-dev", "rpm", "mingw-w64"] + - os: linux + dist: focal + env: BADGE=linux-mingw-32 + name: linux-mingw + compiler: gcc-10 + addons: + apt: + sources: ["ubuntu-toolchain-r-test"] + packages: + ["gcc-10", "libusb-1.0.0-dev", "libgtk-3-dev", "rpm", "mingw-w64"] script: - git fetch --tags diff --git a/cmake/modules/Findlibusb.cmake b/cmake/modules/Findlibusb.cmake index 99f4d56ec..257c682ce 100644 --- a/cmake/modules/Findlibusb.cmake +++ b/cmake/modules/Findlibusb.cmake @@ -77,7 +77,7 @@ elseif (WIN32 OR (EXISTS "/etc/debian_version" AND MINGW)) # Windows or MinGW-to if (NOT LIBUSB_FOUND) # Preparations for installing libusb library - set(LIBUSB_WIN_VERSION 1.0.24) # set libusb version + set(LIBUSB_WIN_VERSION 1.0.23) # set libusb version set(LIBUSB_WIN_ARCHIVE libusb-${LIBUSB_WIN_VERSION}.7z) if (WIN32 AND NOT EXISTS "/etc/debian_version") # ... on native Windows systems set(LIBUSB_WIN_ARCHIVE_PATH ${CMAKE_BINARY_DIR}/${LIBUSB_WIN_ARCHIVE}) @@ -94,7 +94,7 @@ elseif (WIN32 OR (EXISTS "/etc/debian_version" AND MINGW)) # Windows or MinGW-to message(STATUS "downloading libusb ${LIBUSB_WIN_VERSION}") file(DOWNLOAD https://sourceforge.net/projects/libusb/files/libusb-1.0/libusb-${LIBUSB_WIN_VERSION}/libusb-${LIBUSB_WIN_VERSION}.7z/download - ${LIBUSB_WIN_ARCHIVE_PATH} EXPECTED_MD5 5c944b1c8aa9d43e026a94302d0f8ac4 + ${LIBUSB_WIN_ARCHIVE_PATH} EXPECTED_MD5 cf3d38d2ff053ef343d10c0b8b0950c2 ) endif () @@ -128,7 +128,7 @@ elseif (WIN32 OR (EXISTS "/etc/debian_version" AND MINGW)) # Windows or MinGW-to set(LIBUSB_NAME libusb-1.0.lib) find_library( LIBUSB_LIBRARY NAMES ${LIBUSB_NAME} - HINTS ${LIBUSB_WIN_OUTPUT_FOLDER}/**/MS${ARCH}/dll + HINTS ${LIBUSB_WIN_OUTPUT_FOLDER}/MS${ARCH}/dll NO_DEFAULT_PATH NO_CMAKE_FIND_ROOT_PATH ) diff --git a/cmake/packaging/windows/generate_binaries.sh b/cmake/packaging/windows/generate_binaries.sh index 5616ecb38..bf2453d10 100644 --- a/cmake/packaging/windows/generate_binaries.sh +++ b/cmake/packaging/windows/generate_binaries.sh @@ -5,6 +5,18 @@ # Install this cross-compiler toolchain: #sudo apt-get install mingw-w64 +# x86_64 +mkdir build-mingw-64 +cd build-mingw-64 +cmake -DCMAKE_SYSTEM_NAME=Windows \ + -DTOOLCHAIN_PREFIX=x86_64-w64-mingw32 \ + -DCMAKE_TOOLCHAIN_FILE=./../cmake/modules/set_toolchain.cmake .. +make package +cp dist/*.zip ../build/Release/dist +make clean +cd .. +rm -rf build-mingw-64 + # i686 mkdir build-mingw-32 cd build-mingw-32 @@ -16,15 +28,3 @@ cp dist/*.zip ../build/Release/dist make clean cd .. rm -rf build-mingw-32 - -# x86_64 -# mkdir build-mingw-64 -# cd build-mingw-64 -# cmake -DCMAKE_SYSTEM_NAME=Windows \ -# -DTOOLCHAIN_PREFIX=x86_64-w64-mingw32 \ -# -DCMAKE_TOOLCHAIN_FILE=./../cmake/modules/set_toolchain.cmake .. -# make package -# cp dist/*.zip ../build/Release/dist -# make clean -# cd .. -# rm -rf build-mingw-64 From c115ab2e0fcc3103e2ceb848c18b12641cfe7d0e Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sat, 24 Apr 2021 14:16:29 +0200 Subject: [PATCH 243/503] General Project Update - Formatting fixes - Commented CI build setting for Ubuntu 16.04 - Updated CHANGELOG.md --- .github/workflows/c-cpp.yml | 210 +++++++++++---------- CHANGELOG.md | 4 +- inc/stm32.h | 31 ++-- src/stlink-lib/chipid.c | 353 ++++++++++++++++++++---------------- 4 files changed, 323 insertions(+), 275 deletions(-) diff --git a/.github/workflows/c-cpp.yml b/.github/workflows/c-cpp.yml index 97f48d88d..ef9e5f172 100644 --- a/.github/workflows/c-cpp.yml +++ b/.github/workflows/c-cpp.yml @@ -7,98 +7,97 @@ on: branches: [master, develop, testing] jobs: + # Linux -# Linux - - job_linux_16_04_64_gcc: - name: ubuntu-16.04 gcc - runs-on: ubuntu-16.04 - steps: - - uses: actions/checkout@v2 - - name: Install dependencies - run: sudo apt-get install gcc-5 libusb-1.0.0-dev libgtk-3-dev rpm - - name: make debug - run: sudo make clean && make debug - - name: make test - run: sudo make clean && make test - - name: make release - run: sudo make clean && make release - - name: sudo make install - run: sudo make clean && sudo make install - - name: sudo make package - run: sudo make package - - name: sudo make uninstall - run: sudo make uninstall && sudo make clean + # job_linux_16_04_64_gcc: + # name: ubuntu-16.04 gcc + # runs-on: ubuntu-16.04 + # steps: + # - uses: actions/checkout@v2 + # - name: Install dependencies + # run: sudo apt-get install gcc-5 libusb-1.0.0-dev libgtk-3-dev rpm + # - name: make debug + # run: sudo make clean && make debug + # - name: make test + # run: sudo make clean && make test + # - name: make release + # run: sudo make clean && make release + # - name: sudo make install + # run: sudo make clean && sudo make install + # - name: sudo make package + # run: sudo make package + # - name: sudo make uninstall + # run: sudo make uninstall && sudo make clean - job_linux_16_04_32_gcc: - name: ubuntu-16.04 gcc 32-bit - runs-on: ubuntu-16.04 - steps: - - uses: actions/checkout@v2 - - name: Install dependencies - run: sudo apt-get install gcc-5 libusb-1.0.0-dev libgtk-3-dev rpm - - name: Set compiler flags - run: | - CFLAGS="$CFLAGS -m32" - CXXFLAGS="$CXXFLAGS -m32" - LDFLAGS="$LDFLAGS -m32" - - name: make debug - run: sudo make clean && make debug - - name: make test - run: sudo make clean && make test - - name: make release - run: sudo make clean && make release - - name: sudo make install - run: sudo make clean && sudo make install - - name: sudo make package - run: sudo make package - - name: sudo make uninstall - run: sudo make uninstall && sudo make clean + # job_linux_16_04_32_gcc: + # name: ubuntu-16.04 gcc 32-bit + # runs-on: ubuntu-16.04 + # steps: + # - uses: actions/checkout@v2 + # - name: Install dependencies + # run: sudo apt-get install gcc-5 libusb-1.0.0-dev libgtk-3-dev rpm + # - name: Set compiler flags + # run: | + # CFLAGS="$CFLAGS -m32" + # CXXFLAGS="$CXXFLAGS -m32" + # LDFLAGS="$LDFLAGS -m32" + # - name: make debug + # run: sudo make clean && make debug + # - name: make test + # run: sudo make clean && make test + # - name: make release + # run: sudo make clean && make release + # - name: sudo make install + # run: sudo make clean && sudo make install + # - name: sudo make package + # run: sudo make package + # - name: sudo make uninstall + # run: sudo make uninstall && sudo make clean - job_linux_16_04_64_clang: - name: ubuntu-16.04 clang - runs-on: ubuntu-16.04 - steps: - - uses: actions/checkout@v2 - - name: Install dependencies - run: sudo apt-get install clang-3.5 libusb-1.0.0-dev libgtk-3-dev rpm - - name: make debug - run: sudo make clean && make debug - - name: make test - run: sudo make clean && make test - - name: make release - run: sudo make clean && make release - - name: sudo make install - run: sudo make clean && sudo make install - - name: sudo make package - run: sudo make package - - name: sudo make uninstall - run: sudo make uninstall && sudo make clean + # job_linux_16_04_64_clang: + # name: ubuntu-16.04 clang + # runs-on: ubuntu-16.04 + # steps: + # - uses: actions/checkout@v2 + # - name: Install dependencies + # run: sudo apt-get install clang-3.5 libusb-1.0.0-dev libgtk-3-dev rpm + # - name: make debug + # run: sudo make clean && make debug + # - name: make test + # run: sudo make clean && make test + # - name: make release + # run: sudo make clean && make release + # - name: sudo make install + # run: sudo make clean && sudo make install + # - name: sudo make package + # run: sudo make package + # - name: sudo make uninstall + # run: sudo make uninstall && sudo make clean - job_linux_16_04_32_clang: - name: ubuntu-16.04 clang 32-bit - runs-on: ubuntu-16.04 - steps: - - uses: actions/checkout@v2 - - name: Install dependencies - run: sudo apt-get install clang-3.5 libusb-1.0.0-dev libgtk-3-dev rpm - - name: Set compiler flags - run: | - CFLAGS="$CFLAGS -m32" - CXXFLAGS="$CXXFLAGS -m32" - LDFLAGS="$LDFLAGS -m32" - - name: make debug - run: sudo make clean && make debug - - name: make test - run: sudo make clean && make test - - name: make release - run: sudo make clean && make release - - name: sudo make install - run: sudo make clean && sudo make install - - name: sudo make package - run: sudo make package - - name: sudo make uninstall - run: sudo make uninstall && sudo make clean + # job_linux_16_04_32_clang: + # name: ubuntu-16.04 clang 32-bit + # runs-on: ubuntu-16.04 + # steps: + # - uses: actions/checkout@v2 + # - name: Install dependencies + # run: sudo apt-get install clang-3.5 libusb-1.0.0-dev libgtk-3-dev rpm + # - name: Set compiler flags + # run: | + # CFLAGS="$CFLAGS -m32" + # CXXFLAGS="$CXXFLAGS -m32" + # LDFLAGS="$LDFLAGS -m32" + # - name: make debug + # run: sudo make clean && make debug + # - name: make test + # run: sudo make clean && make test + # - name: make release + # run: sudo make clean && make release + # - name: sudo make install + # run: sudo make clean && sudo make install + # - name: sudo make package + # run: sudo make package + # - name: sudo make uninstall + # run: sudo make uninstall && sudo make clean job_linux_18_04_64_gcc: name: ubuntu-18.04 gcc @@ -144,7 +143,7 @@ jobs: run: sudo make package - name: sudo make uninstall run: sudo make uninstall && sudo make clean - + job_linux_18_04_64_clang: name: ubuntu-18.04 clang runs-on: ubuntu-18.04 @@ -280,7 +279,7 @@ jobs: - name: sudo make uninstall run: sudo make uninstall && sudo make clean -# macOS + # macOS # job_macos_10_14_64_gcc: # name: macos-10.14 gcc @@ -411,7 +410,6 @@ jobs: run: sudo make package - name: sudo make uninstall run: sudo make uninstall && sudo make clean - # job_macos_11_gcc: # name: macos-11.0 gcc # runs-on: macos-11.0 @@ -431,7 +429,6 @@ jobs: # run: sudo make package # - name: sudo make uninstall # run: sudo make uninstall && sudo make clean - # job_macos_11_clang: # name: macos-11.0 clang # runs-on: macos-11.0 @@ -451,20 +448,19 @@ jobs: # run: sudo make package # - name: sudo make uninstall # run: sudo make uninstall && sudo make clean - # Linux MinGW cross compliation - # job_linux_20_04_cross: - # name: ubuntu-20.04 mingw64 - # runs-on: ubuntu-20.04 - # steps: - # - uses: actions/checkout@v2 - # - name: Install dependencies - # run: sudo apt-get install gcc-10 libusb-1.0.0-dev libgtk-3-dev rpm mingw-w64 - # - name: Building Release for Windows (x86-64) ... - # run: sudo mkdir -p build-mingw && cd build-mingw && sudo cmake \ - # -DCMAKE_SYSTEM_NAME=Windows \ - # -DTOOLCHAIN_PREFIX=x86_64-w64-mingw32 \ - # -DCMAKE_TOOLCHAIN_FILE=$PWD/../cmake/modules/set_toolchain.cmake \ - # -DCMAKE_INSTALL_PREFIX=$PWD/install $PWD && \ - # sudo make && sudo rm -rf build-mingw && cd - +# job_linux_20_04_cross: +# name: ubuntu-20.04 mingw64 +# runs-on: ubuntu-20.04 +# steps: +# - uses: actions/checkout@v2 +# - name: Install dependencies +# run: sudo apt-get install gcc-10 libusb-1.0.0-dev libgtk-3-dev rpm mingw-w64 +# - name: Building Release for Windows (x86-64) ... +# run: sudo mkdir -p build-mingw && cd build-mingw && sudo cmake \ +# -DCMAKE_SYSTEM_NAME=Windows \ +# -DTOOLCHAIN_PREFIX=x86_64-w64-mingw32 \ +# -DCMAKE_TOOLCHAIN_FILE=$PWD/../cmake/modules/set_toolchain.cmake \ +# -DCMAKE_INSTALL_PREFIX=$PWD/install $PWD && \ +# sudo make && sudo rm -rf build-mingw && cd - diff --git a/CHANGELOG.md b/CHANGELOG.md index 0ac52da73..a3e7dbafc 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -41,7 +41,7 @@ Updates & changes: Fixes: - Flash loader rework ([#356](https://github.com/stlink-org/stlink/pull/356), [#556](https://github.com/stlink-org/stlink/pull/556), [#593](https://github.com/stlink-org/stlink/pull/593), [#597](https://github.com/stlink-org/stlink/pull/597), [#607](https://github.com/stlink-org/stlink/pull/607), [#612](https://github.com/stlink-org/stlink/pull/612), [#638](https://github.com/stlink-org/stlink/pull/638), [#661](https://github.com/stlink-org/stlink/pull/661), [#690](https://github.com/stlink-org/stlink/pull/690), [#807](https://github.com/stlink-org/stlink/pull/807), [#817](https://github.com/stlink-org/stlink/pull/817), [#818](https://github.com/stlink-org/stlink/pull/818), [#854](https://github.com/stlink-org/stlink/pull/854), [#868](https://github.com/stlink-org/stlink/pull/868), [#967](https://github.com/stlink-org/stlink/pull/967), [#979](https://github.com/stlink-org/stlink/pull/979), [#1043](https://github.com/stlink-org/stlink/pull/1043), [#1054](https://github.com/stlink-org/stlink/pull/1054), [#1092](https://github.com/stlink-org/stlink/pull/1092), [#1105](https://github.com/stlink-org/stlink/pull/1105), [#1113](https://github.com/stlink-org/stlink/pull/1113)) -- Fixed old DFU serial number for STLINK programmers ([#417](https://github.com/stlink-org/stlink/pull/417), [#494](https://github.com/stlink-org/stlink/pull/494), [#1106](https://github.com/stlink-org/stlink/pull/1106)) +- Fixed old DFU serial number for STLINK programmers ([#417](https://github.com/stlink-org/stlink/pull/417), [#494](https://github.com/stlink-org/stlink/pull/494), [#1106](https://github.com/stlink-org/stlink/pull/1106), [#1121](https://github.com/stlink-org/stlink/pull/1121)) - Use vl flashloader for all STM32F1 series ([#769](https://github.com/stlink-org/stlink/pull/769), [#1041](https://github.com/stlink-org/stlink/pull/1041), [#1044](https://github.com/stlink-org/stlink/pull/1044)) - [regression] Changed timeout on flash write ([#787](https://github.com/stlink-org/stlink/pull/787), [#981](https://github.com/stlink-org/stlink/pull/981), [#987](https://github.com/stlink-org/stlink/pull/987)) - cmake compile failure with external `CMAKE_MODULE_PATH` set ([#962](https://github.com/stlink-org/stlink/pull/962)) @@ -165,7 +165,7 @@ Fixes: - Set static link for `libssp` (stack-smashing protection) ([#960](https://github.com/stlink-org/stlink/pull/960), [#961](https://github.com/stlink-org/stlink/pull/961)) - Fixed udev rules installing to wrong directory ([#966](https://github.com/stlink-org/stlink/pull/966)) - Fixed formatting for options display in `st-flash` & `st-info` (commits [#c783d0e](https://github.com/stlink-org/stlink/commit/c783d0e777ccc83a7a8be26a4f4d3414e0478560) and [#562cd24](https://github.com/stlink-org/stlink/commit/562cd2496e696dbd22950925866aac662d81ee5f)) -- Fixed reading of chip ID on Cortex-M0+ core ([#1125](https://github.com/stlink-org/stlink/pull/1125), [#1126](https://github.com/stlink-org/stlink/pull/1126)) +- Fixed reading of chip ID on Cortex-M0+ core ([#1125](https://github.com/stlink-org/stlink/pull/1125), [#1126](https://github.com/stlink-org/stlink/pull/1126), [#1133](https://github.com/stlink-org/stlink/pull/1133)) # v1.6.0 diff --git a/inc/stm32.h b/inc/stm32.h index 7d60ab5de..21da2f563 100644 --- a/inc/stm32.h +++ b/inc/stm32.h @@ -8,24 +8,31 @@ #define STM32_H /* Cortex core ids */ -#define STM32VL_CORE_ID 0x1ba01477 -#define STM32F7_CORE_ID 0x5ba02477 -#define STM32H7_CORE_ID 0x6ba02477 // STM32H7 SWD ID Code +#define STM32VL_CORE_ID 0x1ba01477 +#define STM32F7_CORE_ID 0x5ba02477 +#define STM32H7_CORE_ID 0x6ba02477 // STM32H7 SWD ID Code #define STM32H7_CORE_ID_JTAG 0x6ba00477 // STM32H7 JTAG ID Code (RM0433 pg3065) /* Constant STM32 memory map figures */ -#define STM32_FLASH_BASE ((uint32_t)0x08000000) -#define STM32_F1_FLASH_BANK2_BASE ((uint32_t)0x08080000) -#define STM32_H7_FLASH_BANK2_BASE ((uint32_t)0x08100000) -#define STM32_SRAM_BASE ((uint32_t)0x20000000) -#define STM32_G0_OPTION_BYTES_BASE ((uint32_t)0x1FFF7800) -#define STM32_G4_OPTION_BYTES_BASE ((uint32_t)0x1FFFF800) -#define STM32_L0_CATx_OPTION_BYTES_BASE ((uint32_t)0x1FF80000) +#define STM32_SRAM_BASE ((uint32_t)0x20000000) +#define STM32_FLASH_BASE ((uint32_t)0x08000000) +#define STM32_F1_FLASH_BANK2_BASE ((uint32_t)0x08080000) +#define STM32_H7_FLASH_BANK2_BASE ((uint32_t)0x08100000) + #define STM32_F2_OPTION_BYTES_BASE ((uint32_t)0x1FFFC000) -#define STM32_L4_OPTION_BYTES_BASE ((uint32_t)0x1FFF7800) -#define STM32_L1_OPTION_BYTES_BASE ((uint32_t)0x1FF80000) #define STM32_F4_OPTION_BYTES_BASE ((uint32_t)0x40023C14) #define STM32_F7_OPTION_BYTES_BASE ((uint32_t)0x1FFF0000) #define STM32_H7_OPTION_BYTES_BASE ((uint32_t)0x5200201C) +#define STM32_G0_OPTION_BYTES_BASE ((uint32_t)0x1FFF7800) +#define STM32_L4_OPTION_BYTES_BASE ((uint32_t)0x1FFF7800) + +#define STM32_L0_OPTION_BYTES_BASE ((uint32_t)0x1FF80000) +#define STM32_L1_OPTION_BYTES_BASE ((uint32_t)0x1FF80000) + +#define STM32_F0_OPTION_BYTES_BASE ((uint32_t)0x1FFFF800) +#define STM32_F1_OPTION_BYTES_BASE ((uint32_t)0x1FFFF800) +#define STM32_F3_OPTION_BYTES_BASE ((uint32_t)0x1FFFF800) +#define STM32_G4_OPTION_BYTES_BASE ((uint32_t)0x1FFFF800) + #endif // STM32_H diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index 221234bbb..187a6d957 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -7,12 +7,15 @@ static const struct stlink_chipid_params devices[] = { .chip_id = STLINK_CHIPID_STM32_F7XXXX, .description = "F76xxx", .flash_type = STLINK_FLASH_TYPE_F7, - .flash_size_reg = 0x1ff0f442, // section 45.2 - .flash_pagesize = 0x800, // No flash pages - .sram_size = 0x80000, // "SRAM" byte size in hex from - .bootrom_base = 0x00200000, // ! "System memory" starting address from - .bootrom_size = 0xEDC0, // ! @todo "System memory" byte size in hex from - .option_base = STM32_F7_OPTION_BYTES_BASE, // Used for reading back the option bytes, writing uses FLASH_F7_OPTCR and FLASH_F7_OPTCR1 + .flash_size_reg = 0x1ff0f442, // section 45.2 + .flash_pagesize = 0x800, // No flash pages + .sram_size = 0x80000, // "SRAM" byte size in hex from + .bootrom_base = 0x00200000, // ! "System memory" starting address from + .bootrom_size = 0xEDC0, // ! @todo "System memory" byte size in hex from + .option_base = + STM32_F7_OPTION_BYTES_BASE, // Used for reading back the option + // bytes, writing uses FLASH_F7_OPTCR + // and FLASH_F7_OPTCR1 .option_size = 0x20, .flags = CHIP_F_HAS_SWO_TRACING, }, @@ -21,11 +24,13 @@ static const struct stlink_chipid_params devices[] = { .chip_id = STLINK_CHIPID_STM32_F7, .description = "F7xx", .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1ff0f442, // section 41.2 - .flash_pagesize = 0x800, // No flash pages - .sram_size = 0x50000, // "SRAM" byte size in hex from DS Fig 18 - .bootrom_base = 0x00100000, // "System memory" starting address from DS Fig 18 - .bootrom_size = 0xEDC0, // "System memory" byte size in hex from DS Fig 18 + .flash_size_reg = 0x1ff0f442, // section 41.2 + .flash_pagesize = 0x800, // No flash pages + .sram_size = 0x50000, // "SRAM" byte size in hex from DS Fig 18 + .bootrom_base = + 0x00100000, // "System memory" starting address from DS Fig 18 + .bootrom_size = + 0xEDC0, // "System memory" byte size in hex from DS Fig 18 .flags = CHIP_F_HAS_SWO_TRACING, }, { @@ -33,14 +38,17 @@ static const struct stlink_chipid_params devices[] = { .chip_id = STLINK_CHIPID_STM32_F72XXX, .description = "F72x/F73x", .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1ff07a22, // section 35.2 - .flash_pagesize = 0x800, // No flash pages - .sram_size = 0x40000, // "SRAM" byte size in hex from DS Fig 24 - .bootrom_base = 0x00100000, // "System memory" starting address from DS Fig 24 - .bootrom_size = 0xEDC0, // "System memory" byte size in hex from DS Fig 24 + .flash_size_reg = 0x1ff07a22, // section 35.2 + .flash_pagesize = 0x800, // No flash pages + .sram_size = 0x40000, // "SRAM" byte size in hex from DS Fig 24 + .bootrom_base = + 0x00100000, // "System memory" starting address from DS Fig 24 + .bootrom_size = + 0xEDC0, // "System memory" byte size in hex from DS Fig 24 .flags = CHIP_F_HAS_SWO_TRACING, }, - { // table 2, PM0063 + { + // table 2, PM0063 .chip_id = STLINK_CHIPID_STM32_F1_MEDIUM, .description = "F1xx Medium-density", .flash_type = STLINK_FLASH_TYPE_F0, @@ -51,11 +59,12 @@ static const struct stlink_chipid_params devices[] = { .bootrom_size = 0x800, .flags = CHIP_F_HAS_SWO_TRACING, }, - { // table 1, PM0059 + { + // table 1, PM0059 .chip_id = STLINK_CHIPID_STM32_F2, .description = "F2xx", .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1fff7a22, // as in RM0033 Rev 5 + .flash_size_reg = 0x1fff7a22, // as in RM0033 Rev 5 .flash_pagesize = 0x20000, .sram_size = 0x20000, .bootrom_base = 0x1fff0000, @@ -64,7 +73,8 @@ static const struct stlink_chipid_params devices[] = { .option_size = 4, .flags = CHIP_F_HAS_SWO_TRACING, }, - { // PM0063 + { + // PM0063 .chip_id = STLINK_CHIPID_STM32_F1_LOW, .description = "F1 Low-density device", .flash_type = STLINK_FLASH_TYPE_F0, @@ -79,7 +89,7 @@ static const struct stlink_chipid_params devices[] = { .chip_id = STLINK_CHIPID_STM32_F4, .description = "F4xx", .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1FFF7A22, // As in rm0090 since Rev 2 + .flash_size_reg = 0x1FFF7A22, // As in rm0090 since Rev 2 .flash_pagesize = 0x4000, .sram_size = 0x30000, .bootrom_base = 0x1fff0000, @@ -92,7 +102,7 @@ static const struct stlink_chipid_params devices[] = { .chip_id = STLINK_CHIPID_STM32_F4_DSI, .description = "F46x/F47x", .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1FFF7A22, // As in rm0090 since Rev 2 + .flash_size_reg = 0x1FFF7A22, // As in rm0090 since Rev 2 .flash_pagesize = 0x4000, .sram_size = 0x40000, .bootrom_base = 0x1fff0000, @@ -103,7 +113,7 @@ static const struct stlink_chipid_params devices[] = { .chip_id = STLINK_CHIPID_STM32_F4_HD, .description = "F42x/F43x", .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1FFF7A22, // As in rm0090 since Rev 2 + .flash_size_reg = 0x1FFF7A22, // As in rm0090 since Rev 2 .flash_pagesize = 0x4000, .sram_size = 0x40000, .bootrom_base = 0x1fff0000, @@ -224,7 +234,8 @@ static const struct stlink_chipid_params devices[] = { .bootrom_size = 0x4800, .flags = CHIP_F_HAS_SWO_TRACING, }, - { // Low and Medium density VL have same chipid. RM0041 25.6.1 + { + // Low and Medium density VL have same chipid. RM0041 25.6.1 .chip_id = STLINK_CHIPID_STM32_F1_VL_MEDIUM_LOW, .description = "F1xx Value Line", .flash_type = STLINK_FLASH_TYPE_F0, @@ -315,11 +326,12 @@ static const struct stlink_chipid_params devices[] = { .chip_id = STLINK_CHIPID_STM32_F0_CAN, .description = "F07x", .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) - .flash_pagesize = 0x800, // Page sizes listed in Table 4 - .sram_size = 0x4000, // "SRAM" byte size in hex from Table 2 - .bootrom_base = 0x1fffC800, // "System memory" starting address from Table 2 - .bootrom_size = 0x3000, // "System memory" byte size in hex from Table 2 + .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) + .flash_pagesize = 0x800, // Page sizes listed in Table 4 + .sram_size = 0x4000, // "SRAM" byte size in hex from Table 2 + .bootrom_base = + 0x1fffC800, // "System memory" starting address from Table 2 + .bootrom_size = 0x3000, // "System memory" byte size in hex from Table 2 }, { // Use this as an example for mapping future chips: @@ -327,11 +339,12 @@ static const struct stlink_chipid_params devices[] = { .chip_id = STLINK_CHIPID_STM32_F0, .description = "F0xx", .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) - .flash_pagesize = 0x400, // Page sizes listed in Table 4 - .sram_size = 0x2000, // "SRAM" byte size in hex from Table 2 - .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2 - .bootrom_size = 0xC00, // "System memory" byte size in hex from Table 2 + .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) + .flash_pagesize = 0x400, // Page sizes listed in Table 4 + .sram_size = 0x2000, // "SRAM" byte size in hex from Table 2 + .bootrom_base = + 0x1fffec00, // "System memory" starting address from Table 2 + .bootrom_size = 0xC00, // "System memory" byte size in hex from Table 2 }, { // RM0402 document was used to find these parameters @@ -339,11 +352,12 @@ static const struct stlink_chipid_params devices[] = { .chip_id = STLINK_CHIPID_STM32_F412, .description = "F412", .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1FFF7A22, // "Flash size data register" (pg1135) - .flash_pagesize = 0x4000, // Table 5. Flash module organization ? - .sram_size = 0x40000, // "SRAM" byte size in hex from Table 4 - .bootrom_base = 0x1FFF0000, // "System memory" starting address from Table 4 - .bootrom_size = 0x7800, // "System memory" byte size in hex from Table 4 + .flash_size_reg = 0x1FFF7A22, // "Flash size data register" (pg1135) + .flash_pagesize = 0x4000, // Table 5. Flash module organization ? + .sram_size = 0x40000, // "SRAM" byte size in hex from Table 4 + .bootrom_base = + 0x1FFF0000, // "System memory" starting address from Table 4 + .bootrom_size = 0x7800, // "System memory" byte size in hex from Table 4 .flags = CHIP_F_HAS_SWO_TRACING, }, { @@ -352,22 +366,27 @@ static const struct stlink_chipid_params devices[] = { .chip_id = STLINK_CHIPID_STM32_F413, .description = "F413", .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1FFF7A22, // "Flash size data register" Section 35.2 - .flash_pagesize = 0x4000, // Table 5. Flash module organization (variable sector sizes, but 0x4000 is smallest) - .sram_size = 0x50000, // "SRAM" byte size in hex from Figure 2 (Table 4 only says 0x40000) - .bootrom_base = 0x1FFF0000, // "System memory" starting address from Table 4 - .bootrom_size = 0x7800, // "System memory" byte size in hex from Table 4 + .flash_size_reg = 0x1FFF7A22, // "Flash size data register" Section 35.2 + .flash_pagesize = + 0x4000, // Table 5. Flash module organization (variable sector + // sizes, but 0x4000 is smallest) + .sram_size = 0x50000, // "SRAM" byte size in hex from Figure 2 (Table 4 + // only says 0x40000) + .bootrom_base = + 0x1FFF0000, // "System memory" starting address from Table 4 + .bootrom_size = 0x7800, // "System memory" byte size in hex from Table 4 .flags = CHIP_F_HAS_SWO_TRACING, }, { .chip_id = STLINK_CHIPID_STM32_F09X, .description = "F09X", .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) - .flash_pagesize = 0x800, // Page sizes listed in Table 4 (pg 56) - .sram_size = 0x8000, // "SRAM" byte size in hex from Table 2 (pg 50) - .bootrom_base = 0x1fffd800, // "System memory" starting address from Table 2 - .bootrom_size = 0x2000, // "System memory" byte size in hex from Table 2 + .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) + .flash_pagesize = 0x800, // Page sizes listed in Table 4 (pg 56) + .sram_size = 0x8000, // "SRAM" byte size in hex from Table 2 (pg 50) + .bootrom_base = + 0x1fffd800, // "System memory" starting address from Table 2 + .bootrom_size = 0x2000, // "System memory" byte size in hex from Table 2 }, { // Use this as an example for mapping future chips: @@ -375,11 +394,12 @@ static const struct stlink_chipid_params devices[] = { .chip_id = STLINK_CHIPID_STM32_F04, .description = "F04x", .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) - .flash_pagesize = 0x400, // Page sizes listed in Table 4 - .sram_size = 0x1800, // "SRAM" byte size in hex from Table 2 - .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2 - .bootrom_size = 0xC00, // "System memory" byte size in hex from Table 2 + .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) + .flash_pagesize = 0x400, // Page sizes listed in Table 4 + .sram_size = 0x1800, // "SRAM" byte size in hex from Table 2 + .bootrom_base = + 0x1fffec00, // "System memory" starting address from Table 2 + .bootrom_size = 0xC00, // "System memory" byte size in hex from Table 2 }, { // Use this as an example for mapping future chips: @@ -387,11 +407,12 @@ static const struct stlink_chipid_params devices[] = { .chip_id = STLINK_CHIPID_STM32_F0_SMALL, .description = "F0xx small", .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) - .flash_pagesize = 0x400, // Page sizes listed in Table 4 - .sram_size = 0x1000, // "SRAM" byte size in hex from Table 2 - .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2 - .bootrom_size = 0xC00, // "System memory" byte size in hex from Table 2 + .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) + .flash_pagesize = 0x400, // Page sizes listed in Table 4 + .sram_size = 0x1000, // "SRAM" byte size in hex from Table 2 + .bootrom_base = + 0x1fffec00, // "System memory" starting address from Table 2 + .bootrom_size = 0xC00, // "System memory" byte size in hex from Table 2 }, { // STM32F30x @@ -416,7 +437,7 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0x2000, .bootrom_base = 0x1ff0000, .bootrom_size = 0x1000, - .option_base = STM32_L0_CATx_OPTION_BYTES_BASE, + .option_base = STM32_L0_OPTION_BYTES_BASE, .option_size = 20, }, { @@ -430,7 +451,7 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0x5000, .bootrom_base = 0x1ff0000, .bootrom_size = 0x2000, - .option_base = STM32_L0_CATx_OPTION_BYTES_BASE, + .option_base = STM32_L0_OPTION_BYTES_BASE, .option_size = 20, }, { @@ -444,7 +465,7 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0x2000, .bootrom_base = 0x1ff0000, .bootrom_size = 0x1000, - .option_base = STM32_L0_CATx_OPTION_BYTES_BASE, + .option_base = STM32_L0_OPTION_BYTES_BASE, .option_size = 20, }, { @@ -466,10 +487,10 @@ static const struct stlink_chipid_params devices[] = { .chip_id = STLINK_CHIPID_STM32_F303_HIGH, .description = "F303 high density", .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7cc, // 34.2.1 Flash size data register - .flash_pagesize = 0x800, // 4.2.1 Flash memory organization - .sram_size = 0x10000, // 3.3 Embedded SRAM - .bootrom_base = 0x1fffd800, // 3.3.2 / Table 4 System Memory + .flash_size_reg = 0x1ffff7cc, // 34.2.1 Flash size data register + .flash_pagesize = 0x800, // 4.2.1 Flash memory organization + .sram_size = 0x10000, // 3.3 Embedded SRAM + .bootrom_base = 0x1fffd800, // 3.3.2 / Table 4 System Memory .bootrom_size = 0x2000, .flags = CHIP_F_HAS_SWO_TRACING, }, @@ -479,15 +500,18 @@ static const struct stlink_chipid_params devices[] = { .chip_id = STLINK_CHIPID_STM32_L4, .description = "L4xx", .flash_type = STLINK_FLASH_TYPE_L4, - .flash_size_reg = 0x1FFF75e0, // "Flash size data register" (sec 45.2, page 1671) - .flash_pagesize = 0x800, // 2k (sec 3.2, page 78; also appears in sec 3.3.1 - // and tables 4-6 on pages 79-81) - // SRAM1 is "up to" 96k in the standard Cortex-M memory map; - // SRAM2 is 32k mapped at at 0x10000000 (sec 2.3, page 73 for - // sizes; table 2, page 74 for SRAM2 location) + .flash_size_reg = + 0x1FFF75e0, // "Flash size data register" (sec 45.2, page 1671) + .flash_pagesize = + 0x800, // 2k (sec 3.2, page 78; also appears in sec 3.3.1 + // and tables 4-6 on pages 79-81) + // SRAM1 is "up to" 96k in the standard Cortex-M memory map; + // SRAM2 is 32k mapped at at 0x10000000 (sec 2.3, page 73 for + // sizes; table 2, page 74 for SRAM2 location) .sram_size = 0x18000, - .bootrom_base = 0x1fff0000, // Tables 4-6, pages 80-81 (Bank 1 system memory) - .bootrom_size = 0x7000, // 28k (per bank), same source as base + .bootrom_base = + 0x1fff0000, // Tables 4-6, pages 80-81 (Bank 1 system memory) + .bootrom_size = 0x7000, // 28k (per bank), same source as base .option_base = STM32_L4_OPTION_BYTES_BASE, .option_size = 4, .flags = CHIP_F_HAS_SWO_TRACING, @@ -498,11 +522,13 @@ static const struct stlink_chipid_params devices[] = { .chip_id = STLINK_CHIPID_STM32_L4RX, .description = "L4Rx", .flash_type = STLINK_FLASH_TYPE_L4, - .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 52.2, page 2049) - .flash_pagesize = 0x1000, // 4k, section 3.3, pg 97 - .sram_size = 0xa0000, // 192k (SRAM1) + 64k SRAM2 + 384k SRAM3 = 640k, or 0xA0000 - .bootrom_base = 0x1fff0000, // 3.3.1, pg 99 - .bootrom_size = 0x7000, // 28k (per bank), same source as base (pg 99) + .flash_size_reg = + 0x1fff75e0, // "Flash size data register" (sec 52.2, page 2049) + .flash_pagesize = 0x1000, // 4k, section 3.3, pg 97 + .sram_size = + 0xa0000, // 192k (SRAM1) + 64k SRAM2 + 384k SRAM3 = 640k, or 0xA0000 + .bootrom_base = 0x1fff0000, // 3.3.1, pg 99 + .bootrom_size = 0x7000, // 28k (per bank), same source as base (pg 99) .flags = CHIP_F_HAS_SWO_TRACING, }, { @@ -511,13 +537,16 @@ static const struct stlink_chipid_params devices[] = { .chip_id = STLINK_CHIPID_STM32_L41X, .description = "L41x", .flash_type = STLINK_FLASH_TYPE_L4, - .flash_size_reg = 0x1fff75e0, // "Flash size data register" (RM0394, sec 47.2, page 1586) - .flash_pagesize = 0x800, // 2k (DS12469, sec 3.4, page 17) - // SRAM1 is 32k at 0x20000000 - // SRAM2 is 8k at 0x10000000 and 0x20008000 (DS12469, sec 3.5, page 18) - .sram_size = 0xa000, // 40k (DS12469, sec 3.5, page 18) - .bootrom_base = 0x1fff0000, // System Memory (RM0394, sec 3.3.1, table 8) - .bootrom_size = 0x7000, // 28k, same source as base + .flash_size_reg = 0x1fff75e0, // "Flash size data register" (RM0394, + // sec 47.2, page 1586) + .flash_pagesize = 0x800, // 2k (DS12469, sec 3.4, page 17) + // SRAM1 is 32k at 0x20000000 + // SRAM2 is 8k at 0x10000000 and 0x20008000 + // (DS12469, sec 3.5, page 18) + .sram_size = 0xa000, // 40k (DS12469, sec 3.5, page 18) + .bootrom_base = + 0x1fff0000, // System Memory (RM0394, sec 3.3.1, table 8) + .bootrom_size = 0x7000, // 28k, same source as base .flags = CHIP_F_HAS_SWO_TRACING, }, { @@ -526,15 +555,18 @@ static const struct stlink_chipid_params devices[] = { .chip_id = STLINK_CHIPID_STM32_L43X, .description = "L43x/L44x", .flash_type = STLINK_FLASH_TYPE_L4, - .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 43.2, page 1410) - .flash_pagesize = 0x800, // 2k (sec 3.2, page 74; also appears in sec 3.3.1 - // and tables 7-8 on pages 75-76) - // SRAM1 is "up to" 64k in the standard Cortex-M memory map; - // SRAM2 is 16k mapped at 0x10000000 (sec 2.3, page 73 for - // sizes; table 2, page 74 for SRAM2 location) + .flash_size_reg = + 0x1fff75e0, // "Flash size data register" (sec 43.2, page 1410) + .flash_pagesize = + 0x800, // 2k (sec 3.2, page 74; also appears in sec 3.3.1 + // and tables 7-8 on pages 75-76) + // SRAM1 is "up to" 64k in the standard Cortex-M memory map; + // SRAM2 is 16k mapped at 0x10000000 (sec 2.3, page 73 for + // sizes; table 2, page 74 for SRAM2 location) .sram_size = 0xc000, - .bootrom_base = 0x1fff0000, // Tables 4-6, pages 80-81 (Bank 1 system memory) - .bootrom_size = 0x7000, // 28k (per bank), same source as base + .bootrom_base = + 0x1fff0000, // Tables 4-6, pages 80-81 (Bank 1 system memory) + .bootrom_size = 0x7000, // 28k (per bank), same source as base .option_base = STM32_L4_OPTION_BYTES_BASE, .option_size = 4, .flags = CHIP_F_HAS_SWO_TRACING, @@ -545,13 +577,15 @@ static const struct stlink_chipid_params devices[] = { .chip_id = STLINK_CHIPID_STM32_L496X, .description = "L496x/L4A6x", .flash_type = STLINK_FLASH_TYPE_L4, - .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 49.2, page 1809) - .flash_pagesize = 0x800, // Page erase (2 Kbyte) (sec 3.2, page 93) - // SRAM1 is 256k at 0x20000000 - // SRAM2 is 64k at 0x20040000 (sec 2.2.1, fig 2, page 74) - .sram_size = 0x40000, // Embedded SRAM (sec 2.4, page 84) - .bootrom_base = 0x1fff0000, // System Memory (Bank 1) (sec 3.3.1) - .bootrom_size = 0x7000, // 28k (per bank), same source as base + .flash_size_reg = + 0x1fff75e0, // "Flash size data register" (sec 49.2, page 1809) + .flash_pagesize = + 0x800, // Page erase (2 Kbyte) (sec 3.2, page 93) + // SRAM1 is 256k at 0x20000000 + // SRAM2 is 64k at 0x20040000 (sec 2.2.1, fig 2, page 74) + .sram_size = 0x40000, // Embedded SRAM (sec 2.4, page 84) + .bootrom_base = 0x1fff0000, // System Memory (Bank 1) (sec 3.3.1) + .bootrom_size = 0x7000, // 28k (per bank), same source as base .option_base = STM32_L4_OPTION_BYTES_BASE, .option_size = 4, .flags = CHIP_F_HAS_SWO_TRACING, @@ -562,14 +596,18 @@ static const struct stlink_chipid_params devices[] = { .chip_id = STLINK_CHIPID_STM32_L46X, .description = "L45x/46x", .flash_type = STLINK_FLASH_TYPE_L4, - .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 45.2, page 1463) - .flash_pagesize = 0x800, // 2k (sec 3.2, page 73; also appears in sec 3.3.1 - // and tables 7 on pages 73-74) - // SRAM1 is 128k at 0x20000000; - // SRAM2 is 32k mapped at 0x10000000 (sec 2.4.2, table 3-4, page 68, also fig 2 on page 63) + .flash_size_reg = + 0x1fff75e0, // "Flash size data register" (sec 45.2, page 1463) + .flash_pagesize = + 0x800, // 2k (sec 3.2, page 73; also appears in sec 3.3.1 + // and tables 7 on pages 73-74) + // SRAM1 is 128k at 0x20000000; + // SRAM2 is 32k mapped at 0x10000000 (sec 2.4.2, table 3-4, + // page 68, also fig 2 on page 63) .sram_size = 0x20000, - .bootrom_base = 0x1fff0000, // Tables 6, pages 71-72 (Bank 1 system memory, also fig 2 on page 63) - .bootrom_size = 0x7000, // 28k (per bank), same source as base + .bootrom_base = 0x1fff0000, // Tables 6, pages 71-72 (Bank 1 system + // memory, also fig 2 on page 63) + .bootrom_size = 0x7000, // 28k (per bank), same source as base .flags = CHIP_F_HAS_SWO_TRACING, }, { @@ -588,11 +626,11 @@ static const struct stlink_chipid_params devices[] = { .chip_id = STLINK_CHIPID_STM32_G0_CAT1, .description = "G030/G031/G041", .flash_type = STLINK_FLASH_TYPE_G0, - .flash_size_reg = 0x1FFF75E0, // Section 38.2 - .flash_pagesize = 0x800, // 2k (sec 3.2) - .sram_size = 0x2000, // 8k (sec 2.3) + .flash_size_reg = 0x1FFF75E0, // Section 38.2 + .flash_pagesize = 0x800, // 2k (sec 3.2) + .sram_size = 0x2000, // 8k (sec 2.3) .bootrom_base = 0x1fff0000, - .bootrom_size = 0x2000, // 8k (sec 2.2.2 table 3) + .bootrom_size = 0x2000, // 8k (sec 2.2.2 table 3) .option_base = STM32_G0_OPTION_BYTES_BASE, .option_size = 4, }, @@ -601,11 +639,11 @@ static const struct stlink_chipid_params devices[] = { .chip_id = STLINK_CHIPID_STM32_G0_CAT2, .description = "G070/G071/G081", .flash_type = STLINK_FLASH_TYPE_G0, - .flash_size_reg = 0x1FFF75E0, // Section 38.2 - .flash_pagesize = 0x800, // 2k (sec 3.2) - .sram_size = 0x9000, // 36k (sec 2.3) + .flash_size_reg = 0x1FFF75E0, // Section 38.2 + .flash_pagesize = 0x800, // 2k (sec 3.2) + .sram_size = 0x9000, // 36k (sec 2.3) .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7000, // 28k (sec 2.2.2 table 2) + .bootrom_size = 0x7000, // 28k (sec 2.2.2 table 2) .option_base = STM32_G0_OPTION_BYTES_BASE, .option_size = 4, }, @@ -614,14 +652,15 @@ static const struct stlink_chipid_params devices[] = { .chip_id = STLINK_CHIPID_STM32_G4_CAT2, .description = "G4 Category-2", .flash_type = STLINK_FLASH_TYPE_G4, - .flash_size_reg = 0x1FFF75E0, // Section 47.2 - .flash_pagesize = 0x800, // 2k (sec 3.3.1) - // SRAM1 is 16k at 0x20000000 - // SRAM2 is 6k at 0x20014000 - // SRAM3/CCM is 10k at 0x10000000, aliased at 0x20018000 - .sram_size = 0x8000, // 32k (sec 2.4) + .flash_size_reg = 0x1FFF75E0, // Section 47.2 + .flash_pagesize = + 0x800, // 2k (sec 3.3.1) + // SRAM1 is 16k at 0x20000000 + // SRAM2 is 6k at 0x20014000 + // SRAM3/CCM is 10k at 0x10000000, aliased at 0x20018000 + .sram_size = 0x8000, // 32k (sec 2.4) .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7000, // 28k (table 2) + .bootrom_size = 0x7000, // 28k (table 2) .option_base = STM32_G4_OPTION_BYTES_BASE, .option_size = 4, .flags = CHIP_F_HAS_SWO_TRACING, @@ -631,14 +670,15 @@ static const struct stlink_chipid_params devices[] = { .chip_id = STLINK_CHIPID_STM32_G4_CAT3, .description = "G4 Category-3", .flash_type = STLINK_FLASH_TYPE_G4, - .flash_size_reg = 0x1FFF75E0, // Section 47.2 - .flash_pagesize = 0x800, // 2k (sec 3.3.1) - // SRAM1 is 80k at 0x20000000 - // SRAM2 is 16k at 0x20014000 - // SRAM3/CCM is 32k at 0x10000000, aliased at 0x20018000 - .sram_size = 0x18000, // 128k (sec 2.4) + .flash_size_reg = 0x1FFF75E0, // Section 47.2 + .flash_pagesize = + 0x800, // 2k (sec 3.3.1) + // SRAM1 is 80k at 0x20000000 + // SRAM2 is 16k at 0x20014000 + // SRAM3/CCM is 32k at 0x10000000, aliased at 0x20018000 + .sram_size = 0x18000, // 128k (sec 2.4) .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7000, // 28k (table 2) + .bootrom_size = 0x7000, // 28k (table 2) .option_base = STM32_G4_OPTION_BYTES_BASE, .option_size = 4, .flags = CHIP_F_HAS_DUAL_BANK | CHIP_F_HAS_SWO_TRACING, @@ -649,7 +689,7 @@ static const struct stlink_chipid_params devices[] = { .description = "WB55", .flash_type = STLINK_FLASH_TYPE_WB, .flash_size_reg = 0x1FFF75E0, - .flash_pagesize = 0x1000, // 4k + .flash_pagesize = 0x1000, // 4k .sram_size = 0x40000, .bootrom_base = 0x1fff0000, // see the memory map .bootrom_size = 0x7000, @@ -660,13 +700,15 @@ static const struct stlink_chipid_params devices[] = { .chip_id = STLINK_CHIPID_STM32_H74XXX, .description = "H74x/H75x", .flash_type = STLINK_FLASH_TYPE_H7, - .flash_size_reg = 0x1ff1e880, // "Flash size register" (pg3272) - .flash_pagesize = 0x20000, // 128k sector (pg147) - .sram_size = 0x20000, // 128k "DTCM" from Table 7 - .bootrom_base = 0x1ff00000, // "System memory" starting address from Table 7 - .bootrom_size = 0x20000, // "System memory" byte size in hex from Table 7 + .flash_size_reg = 0x1ff1e880, // "Flash size register" (pg3272) + .flash_pagesize = 0x20000, // 128k sector (pg147) + .sram_size = 0x20000, // 128k "DTCM" from Table 7 + .bootrom_base = + 0x1ff00000, // "System memory" starting address from Table 7 + .bootrom_size = + 0x20000, // "System memory" byte size in hex from Table 7 .option_base = STM32_H7_OPTION_BYTES_BASE, - .option_size = 44, // FLASH_OPTSR_CUR to FLASH_BOOT_PRGR from Table 28 + .option_size = 44, // FLASH_OPTSR_CUR to FLASH_BOOT_PRGR from Table 28 .flags = CHIP_F_HAS_DUAL_BANK | CHIP_F_HAS_SWO_TRACING, }, { @@ -674,11 +716,13 @@ static const struct stlink_chipid_params devices[] = { .chip_id = STLINK_CHIPID_STM32_H7AX, .description = "H7Ax/H7Bx", .flash_type = STLINK_FLASH_TYPE_H7, - .flash_size_reg = 0x08FFF80C, // "Flash size register" (p.2949) - .flash_pagesize = 0x2000, // 8k sector (p.146) - .sram_size = 0x20000, // 128k "DTCM" (Figure 1) - .bootrom_base = 0x1FF00000, // "System memory" starting address (Table 12-14) - .bootrom_size = 0x20000, // "System memory" byte size in hex splitted to two banks (Table 12-14) + .flash_size_reg = 0x08FFF80C, // "Flash size register" (p.2949) + .flash_pagesize = 0x2000, // 8k sector (p.146) + .sram_size = 0x20000, // 128k "DTCM" (Figure 1) + .bootrom_base = + 0x1FF00000, // "System memory" starting address (Table 12-14) + .bootrom_size = 0x20000, // "System memory" byte size in hex splitted to + // two banks (Table 12-14) .option_base = STM32_H7_OPTION_BYTES_BASE, .option_size = 44, .flags = CHIP_F_HAS_DUAL_BANK | CHIP_F_HAS_SWO_TRACING, @@ -688,11 +732,12 @@ static const struct stlink_chipid_params devices[] = { .chip_id = STLINK_CHIPID_STM32_H72X, .description = "H72x/H73x", .flash_type = STLINK_FLASH_TYPE_H7, - .flash_size_reg = 0x1FF1E880, // "Flash size register" (p.3286) - .flash_pagesize = 0x20000, // 128k sector (p.152) - .sram_size = 0x20000, // 128k "DTCM" (Figure 1) - .bootrom_base = 0x1FF00000, // "System memory" starting address (Table 6) - .bootrom_size = 0x20000, // "System memory" byte size in hex (Table 6) + .flash_size_reg = 0x1FF1E880, // "Flash size register" (p.3286) + .flash_pagesize = 0x20000, // 128k sector (p.152) + .sram_size = 0x20000, // 128k "DTCM" (Figure 1) + .bootrom_base = + 0x1FF00000, // "System memory" starting address (Table 6) + .bootrom_size = 0x20000, // "System memory" byte size in hex (Table 6) .option_base = STM32_H7_OPTION_BYTES_BASE, .option_size = 44, .flags = CHIP_F_HAS_SWO_TRACING, @@ -712,13 +757,13 @@ static const struct stlink_chipid_params devices[] = { }; const struct stlink_chipid_params *stlink_chipid_get_params(uint32_t chipid) { - const struct stlink_chipid_params *params = NULL; + const struct stlink_chipid_params *params = NULL; - for (size_t n = 0; n < STLINK_ARRAY_SIZE(devices); n++) - if (devices[n].chip_id == chipid) { - params = &devices[n]; - break; - } + for (size_t n = 0; n < STLINK_ARRAY_SIZE(devices); n++) + if (devices[n].chip_id == chipid) { + params = &devices[n]; + break; + } - return(params); + return (params); } From b97296be8f22421b5beb21a4462bf8e515f74ab8 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sat, 24 Apr 2021 22:47:02 +0200 Subject: [PATCH 244/503] Release v1.7.0 --- .gitignore | 3 ++- .version | 2 +- CHANGELOG.md | 12 ++++++------ README.md | 4 ++-- cmake/packaging/windows/generate_binaries.sh | 4 ++-- 5 files changed, 13 insertions(+), 12 deletions(-) diff --git a/.gitignore b/.gitignore index a07eed9ca..1a5fd5ab1 100644 --- a/.gitignore +++ b/.gitignore @@ -1,5 +1,6 @@ build -build-mingw +build-mingw-32 +build-mingw-64 .project .cmake/ diff --git a/.version b/.version index 9c6d6293b..bd8bf882d 100644 --- a/.version +++ b/.version @@ -1 +1 @@ -1.6.1 +1.7.0 diff --git a/CHANGELOG.md b/CHANGELOG.md index a3e7dbafc..9f63eca81 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -2,14 +2,14 @@ # v1.7.0 -Release date: 2020-04-xx +Release date: 2021-04-25 This release drops support for the STLINK/V1 programmer on macOS 10.13. Features: - Extended set of cmd line arguments for st-info and st-util ([#332](https://github.com/stlink-org/stlink/pull/332), [#990](https://github.com/stlink-org/stlink/pull/990), [#1091](https://github.com/stlink-org/stlink/pull/1091), [#1114](https://github.com/stlink-org/stlink/pull/1114)) -- Extended support for STM32H7 & rework of software reset ([#532](https://github.com/stlink-org/stlink/pull/532), [#801](https://github.com/stlink-org/stlink/pull/801), [#868](https://github.com/stlink-org/stlink/pull/868), [#1059](https://github.com/stlink-org/stlink/pull/1059), [#1063](https://github.com/stlink-org/stlink/pull/1063), [#1071](https://github.com/stlink-org/stlink/pull/1071)) +- Extended support for STM32H7 & rework of software reset ([#532](https://github.com/stlink-org/stlink/pull/532), [#801](https://github.com/stlink-org/stlink/pull/801), [#868](https://github.com/stlink-org/stlink/pull/868), [#1008](https://github.com/stlink-org/stlink/pull/1008), [#1059](https://github.com/stlink-org/stlink/pull/1059), [#1063](https://github.com/stlink-org/stlink/pull/1063), [#1071](https://github.com/stlink-org/stlink/pull/1071)) - Added support for STM32H742/743/753 ([#671](https://github.com/stlink-org/stlink/pull/671), [#793](https://github.com/stlink-org/stlink/pull/793), [#823](https://github.com/stlink-org/stlink/pull/823), [#998](https://github.com/stlink-org/stlink/pull/998), [#1052](https://github.com/stlink-org/stlink/pull/1052)) - Official support for STLINK-V3 programmers (commit [#5e0a502](https://github.com/stlink-org/stlink/commit/5e0a502df812495bfa96fa9116a19f1306152b17), [#820](https://github.com/stlink-org/stlink/pull/820), [#1022](https://github.com/stlink-org/stlink/pull/1022), [#1025](https://github.com/stlink-org/stlink/pull/1025)) - Added preliminary support for STM32L5x2 ([#904](https://github.com/stlink-org/stlink/pull/904), [#999](https://github.com/stlink-org/stlink/pull/999)) @@ -40,7 +40,8 @@ Updates & changes: Fixes: -- Flash loader rework ([#356](https://github.com/stlink-org/stlink/pull/356), [#556](https://github.com/stlink-org/stlink/pull/556), [#593](https://github.com/stlink-org/stlink/pull/593), [#597](https://github.com/stlink-org/stlink/pull/597), [#607](https://github.com/stlink-org/stlink/pull/607), [#612](https://github.com/stlink-org/stlink/pull/612), [#638](https://github.com/stlink-org/stlink/pull/638), [#661](https://github.com/stlink-org/stlink/pull/661), [#690](https://github.com/stlink-org/stlink/pull/690), [#807](https://github.com/stlink-org/stlink/pull/807), [#817](https://github.com/stlink-org/stlink/pull/817), [#818](https://github.com/stlink-org/stlink/pull/818), [#854](https://github.com/stlink-org/stlink/pull/854), [#868](https://github.com/stlink-org/stlink/pull/868), [#967](https://github.com/stlink-org/stlink/pull/967), [#979](https://github.com/stlink-org/stlink/pull/979), [#1043](https://github.com/stlink-org/stlink/pull/1043), [#1054](https://github.com/stlink-org/stlink/pull/1054), [#1092](https://github.com/stlink-org/stlink/pull/1092), [#1105](https://github.com/stlink-org/stlink/pull/1105), [#1113](https://github.com/stlink-org/stlink/pull/1113)) +- Improvements and fixes of the flash loaders, unification of the reset function ([#244](https://github.com/stlink-org/stlink/pull/244), [#382](https://github.com/stlink-org/stlink/pull/382), [#705](https://github.com/stlink-org/stlink/pull/705), [#980](https://github.com/stlink-org/stlink/pull/980), [#995](https://github.com/stlink-org/stlink/pull/995), [#1008](https://github.com/stlink-org/stlink/pull/1008), [#1115](https://github.com/stlink-org/stlink/pull/1115), [#1117](https://github.com/stlink-org/stlink/pull/1117), [#1122](https://github.com/stlink-org/stlink/pull/1122), [#1124](https://github.com/stlink-org/stlink/pull/1124)) +- Flash loader rework ([#356](https://github.com/stlink-org/stlink/pull/356), [#556](https://github.com/stlink-org/stlink/pull/556), [#593](https://github.com/stlink-org/stlink/pull/593), [#597](https://github.com/stlink-org/stlink/pull/597), [#607](https://github.com/stlink-org/stlink/pull/607), [#612](https://github.com/stlink-org/stlink/pull/612), [#638](https://github.com/stlink-org/stlink/pull/638), [#661](https://github.com/stlink-org/stlink/pull/661), [#690](https://github.com/stlink-org/stlink/pull/690), [#807](https://github.com/stlink-org/stlink/pull/807), [#817](https://github.com/stlink-org/stlink/pull/817), [#818](https://github.com/stlink-org/stlink/pull/818), [#854](https://github.com/stlink-org/stlink/pull/854), [#868](https://github.com/stlink-org/stlink/pull/868), [#967](https://github.com/stlink-org/stlink/pull/967), [#979](https://github.com/stlink-org/stlink/pull/979), [#1008](https://github.com/stlink-org/stlink/pull/1008), [#1043](https://github.com/stlink-org/stlink/pull/1043), [#1054](https://github.com/stlink-org/stlink/pull/1054), [#1092](https://github.com/stlink-org/stlink/pull/1092), [#1105](https://github.com/stlink-org/stlink/pull/1105), [#1113](https://github.com/stlink-org/stlink/pull/1113)) - Fixed old DFU serial number for STLINK programmers ([#417](https://github.com/stlink-org/stlink/pull/417), [#494](https://github.com/stlink-org/stlink/pull/494), [#1106](https://github.com/stlink-org/stlink/pull/1106), [#1121](https://github.com/stlink-org/stlink/pull/1121)) - Use vl flashloader for all STM32F1 series ([#769](https://github.com/stlink-org/stlink/pull/769), [#1041](https://github.com/stlink-org/stlink/pull/1041), [#1044](https://github.com/stlink-org/stlink/pull/1044)) - [regression] Changed timeout on flash write ([#787](https://github.com/stlink-org/stlink/pull/787), [#981](https://github.com/stlink-org/stlink/pull/981), [#987](https://github.com/stlink-org/stlink/pull/987)) @@ -53,7 +54,7 @@ Fixes: - Fixed `connect under reset` for `st-flash` and `st-util` ([#983](https://github.com/stlink-org/stlink/pull/983)) - Fix for `mmap() size_t overflow` in `st-flash` ([#988](https://github.com/stlink-org/stlink/pull/988), [#989](https://github.com/stlink-org/stlink/pull/989)) - [regression] `stlink-gui` installation issue on Ubuntu-18.04 ([#1001](https://github.com/stlink-org/stlink/pull/1001), [#1004](https://github.com/stlink-org/stlink/pull/1004), [#1006](https://github.com/stlink-org/stlink/pull/1006)) -- `st-util`: wrong register values passed to `gdb` (STLink/V2) ([#1002](https://github.com/stlink-org/stlink/pull/1002), [#1011](https://github.com/stlink-org/stlink/pull/1011), [#1026](https://github.com/stlink-org/stlink/pull/1026), [#1027](https://github.com/stlink-org/stlink/pull/1027), [#1038](https://github.com/stlink-org/stlink/pull/1038),[#1064](https://github.com/stlink-org/stlink/pull/1064), [#1065](https://github.com/stlink-org/stlink/pull/1065)) +- `st-util`: wrong register values passed to `gdb` (STLink/V2) ([#1002](https://github.com/stlink-org/stlink/pull/1002), [#1011](https://github.com/stlink-org/stlink/pull/1011), [#1026](https://github.com/stlink-org/stlink/pull/1026), [#1027](https://github.com/stlink-org/stlink/pull/1027), [#1038](https://github.com/stlink-org/stlink/pull/1038), [#1064](https://github.com/stlink-org/stlink/pull/1064), [#1065](https://github.com/stlink-org/stlink/pull/1065)) - GDB: Fixed problems with target description ([#1013](https://github.com/stlink-org/stlink/pull/1013), [#1088](https://github.com/stlink-org/stlink/pull/1088), [#1109](https://github.com/stlink-org/stlink/pull/1109)) - [doc] Fixed wrong path for `rules.d` folder ([#1020](https://github.com/stlink-org/stlink/pull/1020)) - Fixed support for STLINK/V1 programmer ([#1045](https://github.com/stlink-org/stlink/pull/1045), [#1105](https://github.com/stlink-org/stlink/pull/1105)) @@ -66,7 +67,7 @@ Fixes: - [doc] Corrected spelling mistake in bug report template ([#1103](https://github.com/stlink-org/stlink/pull/1103)) - Fixed STM32WB55 reading DEBUG IDCODE from the wrong address ([#1100](https://github.com/stlink-org/stlink/pull/1100), [#1101](https://github.com/stlink-org/stlink/pull/1101)) - Applied missing changes to tests ([#1119](https://github.com/stlink-org/stlink/pull/1119)) -- Improvements for Chip_ID read ([#1120](https://github.com/stlink-org/stlink/pull/1120)) +- Improvements for Chip_ID read ([#1008](https://github.com/stlink-org/stlink/pull/1008), [#1120](https://github.com/stlink-org/stlink/pull/1120)) # v1.6.1 @@ -143,7 +144,6 @@ Updates & changes: Fixes: -- Improvements and fixes of the flash loaders, unification of the reset function ([#244](https://github.com/stlink-org/stlink/pull/244), [#382](https://github.com/stlink-org/stlink/pull/382), [#705](https://github.com/stlink-org/stlink/pull/705), [#980](https://github.com/stlink-org/stlink/pull/980), [#995](https://github.com/stlink-org/stlink/pull/995), [#1115](https://github.com/stlink-org/stlink/pull/1115), [#1117](https://github.com/stlink-org/stlink/pull/1117), [#1122](https://github.com/stlink-org/stlink/pull/1122), [#1124](https://github.com/stlink-org/stlink/pull/1124)) - Fixed wait-loop for `flash_loader_run()` ([#290](https://github.com/stlink-org/stlink/pull/290)) - Better argument parsing for CLI tools: `stlink_open_usb` can address v1, v2, v3 ([#378](https://github.com/stlink-org/stlink/pull/378), [#922](https://github.com/stlink-org/stlink/pull/922)) - Clear the PG bit before setting the `PER` bit ([#579](https://github.com/stlink-org/stlink/pull/579), [#876](https://github.com/stlink-org/stlink/pull/876)) diff --git a/README.md b/README.md index 93994db49..600879580 100644 --- a/README.md +++ b/README.md @@ -3,7 +3,7 @@ [![BSD licensed](https://img.shields.io/badge/license-BSD-blue.svg)](https://raw.githubusercontent.com/hyperium/hyper/master/LICENSE) [![GitHub release](https://img.shields.io/github/release/stlink-org/stlink.svg)](https://github.com/stlink-org/stlink/releases/latest) [![Downloads](https://img.shields.io/github/downloads/stlink-org/stlink/total)](https://github.com/stlink-org/stlink/releases/latest) -![GitHub commits](https://img.shields.io/github/commits-since/stlink-org/stlink/v1.6.1/develop) +![GitHub commits](https://img.shields.io/github/commits-since/stlink-org/stlink/v1.7.0/develop) ![GitHub activity](https://img.shields.io/github/commit-activity/m/stlink-org/stlink) ![GitHub contributors](https://img.shields.io/github/contributors/stlink-org/stlink) [![CodeQL](https://github.com/stlink-org/stlink/actions/workflows/codeql-analysis.yml/badge.svg)](https://github.com/stlink-org/stlink/actions/workflows/codeql-analysis.yml) @@ -66,7 +66,7 @@ Our [tutorial](doc/tutorial.md) may help you along with some advanced tasks and **Windows**: As of Release v1.6.1 stand-alone Windows binaries are made available (again) on the release page of the project. -Please ensure to select the correct version for your system (i686 or x86_64). The archive file can be unzipped to any desired location as it does not contain any hardcoded paths. However we suggest to move the unzipped application folder to `C:\Program Files\` on 32-bit systems and to `C:\Program Files (x86)\` on 64-bit systems (the toolset is a 32-bit). +Please ensure to select the correct version for your system (i686 or x86_64). The archive file can be unzipped to any desired location as it does not contain any hardcoded paths. However we suggest to move the unzipped application folder to `C:\Program Files\` on 32-bit systems and to `C:\Program Files (x86)\` on 64-bit systems (the toolset is 32-bit). Alternatively one may compile and install from source as described in our [compiling manual](doc/compiling.md#Windows). diff --git a/cmake/packaging/windows/generate_binaries.sh b/cmake/packaging/windows/generate_binaries.sh index bf2453d10..f3642c316 100644 --- a/cmake/packaging/windows/generate_binaries.sh +++ b/cmake/packaging/windows/generate_binaries.sh @@ -12,7 +12,7 @@ cmake -DCMAKE_SYSTEM_NAME=Windows \ -DTOOLCHAIN_PREFIX=x86_64-w64-mingw32 \ -DCMAKE_TOOLCHAIN_FILE=./../cmake/modules/set_toolchain.cmake .. make package -cp dist/*.zip ../build/Release/dist +sudo cp dist/*.zip ../build/Release/dist make clean cd .. rm -rf build-mingw-64 @@ -24,7 +24,7 @@ cmake -DCMAKE_SYSTEM_NAME=Windows \ -DTOOLCHAIN_PREFIX=i686-w64-mingw32 \ -DCMAKE_TOOLCHAIN_FILE=./../cmake/modules/set_toolchain.cmake .. make package -cp dist/*.zip ../build/Release/dist +sudo cp dist/*.zip ../build/Release/dist make clean cd .. rm -rf build-mingw-32 From 80c31a15a4ae447e0e300b5564a7c61f839f8b7f Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 25 Apr 2021 01:43:12 +0200 Subject: [PATCH 245/503] General Project Update - Updated issue templates - Updated CONTRIBUTING.md (Closes #906) - Updated changelogs for deb and rpm packages - Updated CHANGELOG.md --- .github/ISSUE_TEMPLATE/bug-report.md | 17 +++++++++-------- .github/ISSUE_TEMPLATE/feature-request.md | 17 +++++++++-------- CHANGELOG.md | 12 ++++++++++++ CONTRIBUTING.md | 11 +++++++++++ cmake/packaging/deb/changelog | 6 ++++++ cmake/packaging/rpm/changelog | 3 +++ doc/release.md | 2 +- 7 files changed, 51 insertions(+), 17 deletions(-) diff --git a/.github/ISSUE_TEMPLATE/bug-report.md b/.github/ISSUE_TEMPLATE/bug-report.md index 16e0477f0..c733c2c2e 100644 --- a/.github/ISSUE_TEMPLATE/bug-report.md +++ b/.github/ISSUE_TEMPLATE/bug-report.md @@ -5,14 +5,19 @@ title: "[STM32 device name]: $YourTitle" labels: "" --- -Thank you for giving feedback to the stlink project. +**Thank you for giving feedback to the stlink project.** -**NOTICE: Please read and follow instructions in #906 before submitting a ticket. -This bug report will be deleted without notice when not enough information is provided! So please ensure that all fields are filled out.** +--- + +**NOTE: In order to offer sufficient and the best possible support, please read /CONTRIBUTING.md and follow the given instructions _before_ submitting a ticket.** + +**Bug reports and/or feature requests will be deleted, if they violate our contribution guidelines and if no issue-template is used!** Thank you for your support. + +--- - [ ] I made serious effort to avoid creating duplicate or nearly similar issue -In order to allow developers and other contributors to isolate and target your respective issue, please take some time to select the check boxes below and fill out each of the following items appropriate to your specific problem. +In order to allow developers to isolate and target your respective issue, please take some time to select the check boxes below and fill out each of the following items appropriate to your specific problem. - [ ] Programmer/board type: [enter here] (e.g STLINK /V1, /V2, /V2-onboard, /V2-clone, /V3) - [ ] Operating system an version: [enter here] (e.g Linux, macOS, Windows) @@ -31,7 +36,3 @@ OUTPUT/ERROR of the commandline tool(s) Expected/description: `short description of the expected value` - -Thank you for your support. - -The stlink project maintainers diff --git a/.github/ISSUE_TEMPLATE/feature-request.md b/.github/ISSUE_TEMPLATE/feature-request.md index ddeb79357..d57dbefed 100644 --- a/.github/ISSUE_TEMPLATE/feature-request.md +++ b/.github/ISSUE_TEMPLATE/feature-request.md @@ -5,14 +5,19 @@ title: "[feature] $YourTitle" labels: code/feature-request --- -Thank you for giving feedback to the stlink project. +**Thank you for giving feedback to the stlink project.** -**NOTICE: Please read and follow instructions in #906 before submitting a ticket. -This feature request will be deleted without notice when not enough information is provided! So please ensure that all fields are filled out.** +--- + +**NOTE: In order to offer sufficient and the best possible support, please read /CONTRIBUTING.md and follow the given instructions _before_ submitting a ticket.** + +**Bug reports and/or feature requests will be deleted, if they violate our contribution guidelines and if no issue-template is used!** Thank you for your support. + +--- - [ ] I made serious effort to avoid creating duplicate or nearly similar issue -In order to allow developers and other contributors to isolate and target your respective issue, please take some time to select the check boxes below and fill out each of the following items appropriate to your specific request. +In order to allow developers to isolate and target your respective issue, please take some time to select the check boxes below and fill out each of the following items appropriate to your specific request. - [ ] Programmer/board type: [enter here] (e.g STLINK /V1, /V2, /V2-onboard, /V2-clone, /V3) - [ ] Operating system an version: [enter here] (e.g Linux, macOS, Windows) @@ -31,7 +36,3 @@ OUTPUT/ERROR of the commandline tool(s) Expected/description: `short description of the expected value` - -Thank you for your support. - -The stlink project maintainers diff --git a/CHANGELOG.md b/CHANGELOG.md index 9f63eca81..1b003d97e 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -1,5 +1,17 @@ # stlink Changelog +# v1.7.1 + +Release date: 2021-xx-xx + +Features: + +Updates & changes: + +- Added instructions for bug-reports and feature-requests to contribution guidelines ([#906](https://github.com/stlink-org/stlink/pull/906)) + +Fixes: + # v1.7.0 Release date: 2021-04-25 diff --git a/CONTRIBUTING.md b/CONTRIBUTING.md index a9bb02661..6c1842aca 100644 --- a/CONTRIBUTING.md +++ b/CONTRIBUTING.md @@ -12,6 +12,17 @@ We love your input! We want to make contributing to this project as easy and tra We use GitHub to host code, to track issues and feature requests, as well as accept pull requests. Report a bug by [opening a new issue]() with one of the available templates. It's that easy! +**NOTE: In order to offer sufficient and the best possible support, please read and follow the instructions below before submitting a ticket:** + +1) If using a ST-Link-v2 programmer: Convince yourself that it is recognised as an USB device by your computer, thus reporting device and manufacturer ID. Use a diagnostic tool to probe for enumerated USB devices, e.g [`lsusb -v`](https://linux.die.net/man/8/lsusb) on unix-based systems. +2) **Use the [ST-Link firmware upgrade tool](https://www.st.com/en/development-tools/stsw-link007.html) based on Java to read out the current firmware version and update to the latest available version. This also works for _non-genuine_ ST programmers and boards.** +3) Try to make sure you have a working toolchain before starting to build. +4) **Update to the _latest_ release version or maybe even use the `develop` branch.** +5) Search for your problem in the available open issues, _before_ opening a new ticket. +6) Make sure to **use the available issue templates** to submit a bug-report or a feature-request. **Do not replace the prepared text, edit the placeholders instead. _Describe_ your problem.** +7) Avoid to add new comments to closed issues unless they confirm a solution already available. +8) Don't comment on tickets which do not specifically address your device or hardware - open a new ticket instead. +9) Consider if you can help to solve other issues (e.g. you have the same hardware) ## Coding conventions To read code written by other contributors can turn out to be quite demanding - a variable which seems to self-explaining, may appear cryptic to other readers. If you plan to contribute, please take this into account and feel encouraged to help others understand your code. In order to help you along, we have composed some contribution guidelines for this project. As this project already has a history you may find parts in the codebase that do not seem to comply with these guidelines, but we are trying to improve continuosly. However we can do even better, if every contributor considers the following points: diff --git a/cmake/packaging/deb/changelog b/cmake/packaging/deb/changelog index 24bb0152b..4d4d86c2b 100644 --- a/cmake/packaging/deb/changelog +++ b/cmake/packaging/deb/changelog @@ -1,3 +1,9 @@ +stlink (1.7.0) unstable; urgency=medium + + * Release v1.7.0 + + -- Nightwalker-87 Sun, 25 Apr 2021 00:00:00 +0100 + stlink (1.6.1) unstable; urgency=medium * Initial cpack-based package release for Debian/Ubuntu diff --git a/cmake/packaging/rpm/changelog b/cmake/packaging/rpm/changelog index 564bd95ae..3d1c76996 100644 --- a/cmake/packaging/rpm/changelog +++ b/cmake/packaging/rpm/changelog @@ -1,2 +1,5 @@ +* Sun Apr 25 2021 Nightwalker-87 - 1.7.0 +- Release v1.7.0 + * Mon Jun 01 2020 Nightwalker-87 - 1.6.1 - Initial cpack-based RPM package release diff --git a/doc/release.md b/doc/release.md index b44183b80..a67fcd743 100644 --- a/doc/release.md +++ b/doc/release.md @@ -3,7 +3,7 @@ Release This document describes the necessary steps for developers to create a release: -1. Update `CHANGELOG.md` +1. Update `CHANGELOG.md`, `cmake/packaging/deb/changelog` & `cmake/packaging/rpm/changelog` 2. Update `.version` with semantic version: `x.x.x` 3. Update `README.md` with semantic version `x.x.x` in commits badge 4. Create and push git tag and commits `git tag x.x.x` From 2b3a31609cc25a8248cab9beb2d19f5818f1d3ab Mon Sep 17 00:00:00 2001 From: anton Date: Sun, 25 Apr 2021 12:25:15 +0500 Subject: [PATCH 246/503] Moved set the PG flag from loader to code --- flashloaders/stm32f0.s | 14 ------------- src/common.c | 18 +++++++++++++--- src/stlink-lib/flash_loader.c | 39 +++++++++++++---------------------- 3 files changed, 29 insertions(+), 42 deletions(-) diff --git a/flashloaders/stm32f0.s b/flashloaders/stm32f0.s index 23f1c43fe..76bfd9b95 100644 --- a/flashloaders/stm32f0.s +++ b/flashloaders/stm32f0.s @@ -30,15 +30,9 @@ copy: # add r3 to flash_base for support dual bank (see flash_loader.c) ldr r7, flash_base add r7, r7, r3 - ldr r6, flash_off_cr - add r6, r6, r7 ldr r5, flash_off_sr add r5, r5, r7 - # FLASH_CR = 0x01 (set PG) - ldr r4, =0x1 - str r4, [r6] - loop: # copy 2 bytes ldrh r4, [r0] @@ -68,18 +62,10 @@ wait: bgt loop exit: - # FLASH_CR &= ~1 - ldr r7, =0x1 - ldr r4, [r6] - bics r4, r4, r7 - str r4, [r6] - bkpt .align 2 flash_base: .word 0x40022000 -flash_off_cr: - .word 0x10 flash_off_sr: .word 0x0c diff --git a/src/common.c b/src/common.c index 4541aa31c..fcd54e93e 100644 --- a/src/common.c +++ b/src/common.c @@ -3257,6 +3257,15 @@ int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { ELOG("stlink_flash_loader_init() == -1\n"); return (-1); } + + // unlock flash + unlock_flash_if(sl); + + // set programming mode + set_flash_cr_pg(sl, BANK_1); + if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL) { + set_flash_cr_pg(sl, BANK_2); + } } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { ILOG("Starting Flash write for H7\n"); @@ -3437,7 +3446,9 @@ int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, int stlink_flashloader_stop(stlink_t *sl, flash_loader_t *fl) { uint32_t dhcsr; - if ((sl->flash_type == STLINK_FLASH_TYPE_F4) || + if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || + (sl->flash_type == STLINK_FLASH_TYPE_F1_XL) || + (sl->flash_type == STLINK_FLASH_TYPE_F4) || (sl->flash_type == STLINK_FLASH_TYPE_F7) || (sl->flash_type == STLINK_FLASH_TYPE_L4) || (sl->flash_type == STLINK_FLASH_TYPE_WB) || @@ -3446,8 +3457,9 @@ int stlink_flashloader_stop(stlink_t *sl, flash_loader_t *fl) { (sl->flash_type == STLINK_FLASH_TYPE_H7)) { clear_flash_cr_pg(sl, BANK_1); - if (sl->flash_type == STLINK_FLASH_TYPE_H7 && - sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { + if ((sl->flash_type == STLINK_FLASH_TYPE_H7 && + sl->chip_flags & CHIP_F_HAS_DUAL_BANK) || + sl->flash_type == STLINK_FLASH_TYPE_F1_XL) { clear_flash_cr_pg(sl, BANK_2); } lock_flash(sl); diff --git a/src/stlink-lib/flash_loader.c b/src/stlink-lib/flash_loader.c index ba5efdb8e..c9e7661e9 100644 --- a/src/stlink-lib/flash_loader.c +++ b/src/stlink-lib/flash_loader.c @@ -19,44 +19,33 @@ /* flashloaders/stm32f0.s -- compiled with thumb2 */ static const uint8_t loader_code_stm32vl[] = { 0x00, 0xbf, 0x00, 0xbf, - 0x0e, 0x4f, 0x1f, 0x44, - 0x0e, 0x4e, 0x3e, 0x44, - 0x0e, 0x4d, 0x3d, 0x44, - 0x4f, 0xf0, 0x01, 0x04, - 0x34, 0x60, 0x04, 0x88, - 0x0c, 0x80, 0x02, 0x30, - 0x02, 0x31, 0x4f, 0xf0, - 0x01, 0x07, 0x2c, 0x68, - 0x3c, 0x42, 0xfc, 0xd1, - 0x4f, 0xf0, 0x14, 0x07, - 0x3c, 0x42, 0x01, 0xd1, - 0x02, 0x3a, 0xf0, 0xdc, + 0x09, 0x4f, 0x1f, 0x44, + 0x09, 0x4d, 0x3d, 0x44, + 0x04, 0x88, 0x0c, 0x80, + 0x02, 0x30, 0x02, 0x31, 0x4f, 0xf0, 0x01, 0x07, - 0x34, 0x68, 0xbc, 0x43, - 0x34, 0x60, 0x00, 0xbe, + 0x2c, 0x68, 0x3c, 0x42, + 0xfc, 0xd1, 0x4f, 0xf0, + 0x14, 0x07, 0x3c, 0x42, + 0x01, 0xd1, 0x02, 0x3a, + 0xf0, 0xdc, 0x00, 0xbe, 0x00, 0x20, 0x02, 0x40, - 0x10, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x00 }; /* flashloaders/stm32f0.s -- thumb1 only, same sequence as for STM32VL, bank ignored */ static const uint8_t loader_code_stm32f0[] = { 0xc0, 0x46, 0xc0, 0x46, - 0x0c, 0x4f, 0x1f, 0x44, - 0x0c, 0x4e, 0x3e, 0x44, - 0x0c, 0x4d, 0x3d, 0x44, - 0x0c, 0x4c, 0x34, 0x60, + 0x08, 0x4f, 0x1f, 0x44, + 0x08, 0x4d, 0x3d, 0x44, 0x04, 0x88, 0x0c, 0x80, 0x02, 0x30, 0x02, 0x31, - 0x09, 0x4f, 0x2c, 0x68, + 0x06, 0x4f, 0x2c, 0x68, 0x3c, 0x42, 0xfc, 0xd1, - 0x08, 0x4f, 0x3c, 0x42, + 0x05, 0x4f, 0x3c, 0x42, 0x01, 0xd1, 0x02, 0x3a, - 0xf2, 0xdc, 0x05, 0x4f, - 0x34, 0x68, 0xbc, 0x43, - 0x34, 0x60, 0x00, 0xbe, + 0xf2, 0xdc, 0x00, 0xbe, 0x00, 0x20, 0x02, 0x40, - 0x10, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x14, 0x00, 0x00, 0x00 From 498d11b12be197392b8939d82549941beb87c52a Mon Sep 17 00:00:00 2001 From: anton Date: Sun, 25 Apr 2021 12:25:45 +0500 Subject: [PATCH 247/503] Moved the interrupt masking into flash loader init function --- src/common.c | 11 ----------- src/stlink-lib/flash_loader.c | 11 +++++++++++ 2 files changed, 11 insertions(+), 11 deletions(-) diff --git a/src/common.c b/src/common.c index fcd54e93e..d694ace8f 100644 --- a/src/common.c +++ b/src/common.c @@ -3137,17 +3137,6 @@ int stm32l1_write_half_pages(stlink_t *sl, stm32_addr_t addr, uint8_t *base, } int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { - - // According to DDI0419C, Table C1-7 firstly force halt - stlink_write_debug32(sl, STLINK_REG_DHCSR, - STLINK_REG_DHCSR_DBGKEY | STLINK_REG_DHCSR_C_DEBUGEN | - STLINK_REG_DHCSR_C_HALT); - // and only then disable interrupts - stlink_write_debug32(sl, STLINK_REG_DHCSR, - STLINK_REG_DHCSR_DBGKEY | STLINK_REG_DHCSR_C_DEBUGEN | - STLINK_REG_DHCSR_C_HALT | - STLINK_REG_DHCSR_C_MASKINTS); - // disable DMA set_dma_state(sl, fl, 0); diff --git a/src/stlink-lib/flash_loader.c b/src/stlink-lib/flash_loader.c index c9e7661e9..4ec91258b 100644 --- a/src/stlink-lib/flash_loader.c +++ b/src/stlink-lib/flash_loader.c @@ -148,6 +148,17 @@ int stlink_flash_loader_init(stlink_t *sl, flash_loader_t *fl) { size_t size = 0; uint32_t dfsr, cfsr, hfsr; + /* Interrupt masking. + * According to DDI0419C, Table C1-7 firstly force halt */ + stlink_write_debug32(sl, STLINK_REG_DHCSR, + STLINK_REG_DHCSR_DBGKEY | STLINK_REG_DHCSR_C_DEBUGEN | + STLINK_REG_DHCSR_C_HALT); + /* and only then disable interrupts */ + stlink_write_debug32(sl, STLINK_REG_DHCSR, + STLINK_REG_DHCSR_DBGKEY | STLINK_REG_DHCSR_C_DEBUGEN | + STLINK_REG_DHCSR_C_HALT | + STLINK_REG_DHCSR_C_MASKINTS); + // allocate the loader in SRAM if (stlink_flash_loader_write_to_sram(sl, &fl->loader_addr, &size) == -1) { WLOG("Failed to write flash loader to sram!\n"); From c959f348132ab3607a9ca8a23348f8d961e7852b Mon Sep 17 00:00:00 2001 From: anton Date: Sun, 25 Apr 2021 12:34:02 +0500 Subject: [PATCH 248/503] Added support for writing option bytes of F0/F1/F3 targets --- src/common.c | 185 ++++++++++++++++++++++++++++++++++++++-- src/stlink-lib/chipid.c | 36 +++++++- 2 files changed, 212 insertions(+), 9 deletions(-) diff --git a/src/common.c b/src/common.c index d694ace8f..7ddd37032 100644 --- a/src/common.c +++ b/src/common.c @@ -87,9 +87,11 @@ #define FLASH_CR_PER 1 #define FLASH_CR_MER 2 #define FLASH_CR_OPTPG 4 +#define FLASH_CR_OPTER 5 #define FLASH_CR_STRT 6 #define FLASH_CR_LOCK 7 #define FLASH_CR_OPTWRE 9 +#define FLASH_CR_OBL_LAUNCH 13 #define STM32L_FLASH_REGS_ADDR ((uint32_t)0x40023c00) #define STM32L_FLASH_ACR (STM32L_FLASH_REGS_ADDR + 0x00) @@ -3841,6 +3843,64 @@ int stlink_fwrite_flash(stlink_t *sl, const char *path, stm32_addr_t addr) { return (err); } +/** + * Write option bytes + * @param sl + * @param base option bytes to write + * @param addr of the memory mapped option bytes + * @param len of options bytes to write + * @return 0 on success, -ve on failure. + */ +static int stlink_write_option_bytes_f0( + stlink_t *sl, uint8_t* base, stm32_addr_t addr, uint32_t len) { + int ret = 0; + + if (len < 12 || addr != STM32_F0_OPTION_BYTES_BASE) { + WLOG("Only full write of option bytes area is supported\n"); + return -1; + } + + clear_flash_error(sl); + + WLOG("Erasing option bytes\n"); + + /* erase option bytes */ + stlink_write_debug32(sl, FLASH_CR, (1 << FLASH_CR_OPTER) | (1 << FLASH_CR_OPTWRE)); + ret = stlink_write_debug32(sl, FLASH_CR, (1 << FLASH_CR_OPTER) | (1 << FLASH_CR_STRT) | (1 << FLASH_CR_OPTWRE)); + if (ret) { + return ret; + } + + wait_flash_busy(sl); + + ret = check_flash_error(sl); + if (ret) { + return ret; + } + + WLOG("Writing option bytes to %#10x\n", addr); + + /* Set the Option PG bit to enable programming */ + stlink_write_debug32(sl, FLASH_CR, (1 << FLASH_CR_OPTPG) | (1 << FLASH_CR_OPTWRE)); + + /* Use flash loader for write OP + * because flash memory writable by half word */ + flash_loader_t fl; + ret = stlink_flash_loader_init(sl, &fl); + if (ret) { + return ret; + } + ret = stlink_flash_loader_run(sl, &fl, addr, base, len); + if (ret) { + return ret; + } + + /* Reload option bytes */ + stlink_write_debug32(sl, FLASH_CR, (1 << FLASH_CR_OBL_LAUNCH)); + + return check_flash_error(sl); +} + /** * Write option bytes * @param sl @@ -4193,6 +4253,18 @@ int stlink_read_option_control_register_f7(stlink_t *sl, return stlink_read_debug32(sl, FLASH_F7_OPTCR, option_byte); } +/** + * Read option bytes + * @param sl + * @param option_byte value to read + * @return 0 on success, -ve on failure. + */ +int stlink_read_option_control_register_f0(stlink_t *sl, + uint32_t *option_byte) { + DLOG("@@@@ Read option control register byte from %#10x\n", FLASH_OBR); + return stlink_read_debug32(sl, FLASH_OBR, option_byte); +} + /** * Read option bytes * @param sl @@ -4336,8 +4408,8 @@ int stlink_read_option_bytes_boot_add32(stlink_t *sl, uint32_t *option_byte) { return -1; } - switch (sl->chip_id) { - case STLINK_CHIPID_STM32_F7XXXX: + switch (sl->flash_type) { + case STLINK_FLASH_TYPE_F7: return stlink_read_option_bytes_boot_add_f7(sl, option_byte); default: return -1; @@ -4357,12 +4429,14 @@ int stlink_read_option_control_register32(stlink_t *sl, uint32_t *option_byte) { return -1; } - switch (sl->chip_id) { - case STLINK_CHIPID_STM32_F7XXXX: + switch (sl->flash_type) { + case STLINK_FLASH_TYPE_F0: + case STLINK_FLASH_TYPE_F1_XL: + return stlink_read_option_control_register_f0(sl, option_byte); + case STLINK_FLASH_TYPE_F7: return stlink_read_option_control_register_f7(sl, option_byte); default: return -1; - // return stlink_read_option_control_register_generic(sl, option_byte); } } @@ -4379,8 +4453,8 @@ int stlink_read_option_control_register1_32(stlink_t *sl, return -1; } - switch (sl->chip_id) { - case STLINK_CHIPID_STM32_F7XXXX: + switch (sl->flash_type) { + case STLINK_FLASH_TYPE_F7: return stlink_read_option_control_register1_f7(sl, option_byte); default: return -1; @@ -4442,6 +4516,10 @@ int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t *base, } switch (sl->flash_type) { + case STLINK_FLASH_TYPE_F0: + case STLINK_FLASH_TYPE_F1_XL: + ret = stlink_write_option_bytes_f0(sl, base, addr, len); + break; case STLINK_FLASH_TYPE_F4: ret = stlink_write_option_bytes_f4(sl, base, addr, len); break; @@ -4512,6 +4590,95 @@ stlink_write_option_control_register_f7(stlink_t *sl, return ret; } + +/** + * Write option bytes + * @param sl + * @param option_byte value to write + * @return 0 on success, -ve on failure. + */ +static int +stlink_write_option_control_register_f0(stlink_t *sl, + uint32_t option_control_register) { + int ret = 0; + uint16_t opt_val[8]; + unsigned protection, optiondata; + uint16_t user_options, user_data, rdp; + unsigned option_offset, user_data_offset; + + ILOG("Asked to write option control register %#10x to %#010x.\n", + option_control_register, FLASH_OBR); + + /* Clear errors */ + clear_flash_error(sl); + + /* Retrieve current values */ + ret = stlink_read_debug32(sl, FLASH_OBR, &optiondata); + if (ret) { + return ret; + } + ret = stlink_read_debug32(sl, FLASH_WRPR, &protection); + if (ret) { + return ret; + } + + /* Translate OBR value to flash store structure + * F0: RM0091, Option byte description, pp. 75-78 + * F1: PM0075, Option byte description, pp. 19-22 + * F3: RM0316, Option byte description, pp. 85-87 */ + switch(sl->chip_id) + { + case 0x422: /* STM32F30x */ + case 0x432: /* STM32F37x */ + case 0x438: /* STM32F303x6/8 and STM32F328 */ + case 0x446: /* STM32F303xD/E and STM32F398xE */ + case 0x439: /* stm32f302x6/8 */ + case 0x440: /* stm32f05x */ + case 0x444: /* stm32f03x */ + case 0x445: /* stm32f04x */ + case 0x448: /* stm32f07x */ + case 0x442: /* stm32f09x */ + option_offset = 6; + user_data_offset = 16; + rdp = 0x55AA; + break; + default: + option_offset = 0; + user_data_offset = 10; + rdp = 0x5AA5; + break; + } + + user_options = (option_control_register >> option_offset >> 2) & 0xFFFF; + user_data = (option_control_register >> user_data_offset) & 0xFFFF; + +#define VAL_WITH_COMPLEMENT(v) (uint16_t)(((v)&0xFF) | (((~(v))<<8)&0xFF00)) + + opt_val[0] = (option_control_register & (1 << 1/*OPT_READOUT*/)) ? 0xFFFF : rdp; + opt_val[1] = VAL_WITH_COMPLEMENT(user_options); + opt_val[2] = VAL_WITH_COMPLEMENT(user_data); + opt_val[3] = VAL_WITH_COMPLEMENT(user_data >> 8); + opt_val[4] = VAL_WITH_COMPLEMENT(protection); + opt_val[5] = VAL_WITH_COMPLEMENT(protection >> 8); + opt_val[6] = VAL_WITH_COMPLEMENT(protection >> 16); + opt_val[7] = VAL_WITH_COMPLEMENT(protection >> 24); + +#undef VAL_WITH_COMPLEMENT + + /* Write bytes and check errors */ + ret = stlink_write_option_bytes_f0(sl, (uint8_t*)opt_val, STM32_F0_OPTION_BYTES_BASE, sizeof(opt_val)); + if (ret) + return ret; + + ret = check_flash_error(sl); + if (!ret) { + ILOG("Wrote option bytes %#010x to %#010x!\n", option_control_register, + FLASH_OBR); + } + + return ret; +} + /** * Write option bytes * @param sl @@ -4632,6 +4799,10 @@ int stlink_write_option_control_register32(stlink_t *sl, } switch (sl->flash_type) { + case STLINK_FLASH_TYPE_F0: + case STLINK_FLASH_TYPE_F1_XL: + ret = stlink_write_option_control_register_f0(sl, option_control_register); + break; case STLINK_FLASH_TYPE_F7: ret = stlink_write_option_control_register_f7(sl, option_control_register); break; diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index 187a6d957..3d4339526 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -57,6 +57,8 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0x5000, .bootrom_base = 0x1ffff000, .bootrom_size = 0x800, + .option_base = STM32_F0_OPTION_BYTES_BASE, + .option_size = 16, .flags = CHIP_F_HAS_SWO_TRACING, }, { @@ -83,6 +85,8 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0x2800, .bootrom_base = 0x1ffff000, .bootrom_size = 0x800, + .option_base = STM32_F0_OPTION_BYTES_BASE, + .option_size = 16, .flags = CHIP_F_HAS_SWO_TRACING, }, { @@ -162,6 +166,8 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0x10000, .bootrom_base = 0x1ffff000, .bootrom_size = 0x800, + .option_base = STM32_F0_OPTION_BYTES_BASE, + .option_size = 16, .flags = CHIP_F_HAS_SWO_TRACING, }, { @@ -232,6 +238,8 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0x10000, .bootrom_base = 0x1fffb000, .bootrom_size = 0x4800, + .option_base = STM32_F0_OPTION_BYTES_BASE, + .option_size = 16, .flags = CHIP_F_HAS_SWO_TRACING, }, { @@ -244,6 +252,8 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0x2000, // 0x1000 for low density devices .bootrom_base = 0x1ffff000, .bootrom_size = 0x800, + .option_base = STM32_F0_OPTION_BYTES_BASE, + .option_size = 16, .flags = CHIP_F_HAS_SWO_TRACING, }, { @@ -283,6 +293,8 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0xa000, .bootrom_base = 0x1ffff000, .bootrom_size = 0x800, + .option_base = STM32_F0_OPTION_BYTES_BASE, + .option_size = 16, .flags = CHIP_F_HAS_SWO_TRACING, }, { @@ -296,6 +308,8 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0xa000, .bootrom_base = 0x1ffff000, .bootrom_size = 0x800, + .option_base = STM32_F0_OPTION_BYTES_BASE, + .option_size = 16, .flags = CHIP_F_HAS_SWO_TRACING, }, { @@ -307,6 +321,8 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0x8000, .bootrom_base = 0x1ffff000, .bootrom_size = 0x800, + .option_base = STM32_F0_OPTION_BYTES_BASE, + .option_size = 16, .flags = CHIP_F_HAS_SWO_TRACING, }, { @@ -332,12 +348,14 @@ static const struct stlink_chipid_params devices[] = { .bootrom_base = 0x1fffC800, // "System memory" starting address from Table 2 .bootrom_size = 0x3000, // "System memory" byte size in hex from Table 2 + .option_base = STM32_F0_OPTION_BYTES_BASE, + .option_size = 16, }, { // Use this as an example for mapping future chips: // RM0091 document was used to find these paramaters .chip_id = STLINK_CHIPID_STM32_F0, - .description = "F0xx", + .description = "F05x", .flash_type = STLINK_FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) .flash_pagesize = 0x400, // Page sizes listed in Table 4 @@ -345,6 +363,8 @@ static const struct stlink_chipid_params devices[] = { .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2 .bootrom_size = 0xC00, // "System memory" byte size in hex from Table 2 + .option_base = STM32_F0_OPTION_BYTES_BASE, + .option_size = 16, }, { // RM0402 document was used to find these parameters @@ -387,6 +407,8 @@ static const struct stlink_chipid_params devices[] = { .bootrom_base = 0x1fffd800, // "System memory" starting address from Table 2 .bootrom_size = 0x2000, // "System memory" byte size in hex from Table 2 + .option_base = STM32_F0_OPTION_BYTES_BASE, + .option_size = 16, }, { // Use this as an example for mapping future chips: @@ -400,12 +422,14 @@ static const struct stlink_chipid_params devices[] = { .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2 .bootrom_size = 0xC00, // "System memory" byte size in hex from Table 2 + .option_base = STM32_F0_OPTION_BYTES_BASE, + .option_size = 16, }, { // Use this as an example for mapping future chips: // RM0091 document was used to find these paramaters .chip_id = STLINK_CHIPID_STM32_F0_SMALL, - .description = "F0xx small", + .description = "F03x", .flash_type = STLINK_FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) .flash_pagesize = 0x400, // Page sizes listed in Table 4 @@ -413,6 +437,8 @@ static const struct stlink_chipid_params devices[] = { .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2 .bootrom_size = 0xC00, // "System memory" byte size in hex from Table 2 + .option_base = STM32_F0_OPTION_BYTES_BASE, + .option_size = 16, }, { // STM32F30x @@ -424,6 +450,8 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0xa000, .bootrom_base = 0x1fffd800, .bootrom_size = 0x2000, + .option_base = STM32_F0_OPTION_BYTES_BASE, + .option_size = 16, .flags = CHIP_F_HAS_SWO_TRACING, }, { @@ -479,6 +507,8 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0x3000, .bootrom_base = 0x1fffd800, .bootrom_size = 0x2000, + .option_base = STM32_F0_OPTION_BYTES_BASE, + .option_size = 16, .flags = CHIP_F_HAS_SWO_TRACING, }, { @@ -492,6 +522,8 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0x10000, // 3.3 Embedded SRAM .bootrom_base = 0x1fffd800, // 3.3.2 / Table 4 System Memory .bootrom_size = 0x2000, + .option_base = STM32_F0_OPTION_BYTES_BASE, + .option_size = 16, .flags = CHIP_F_HAS_SWO_TRACING, }, { From eeaef981a5dcf6bec6d9b6cada398abcf34b8737 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 25 Apr 2021 19:58:09 +0200 Subject: [PATCH 249/503] Re-enabled GitHub Actions CI for Ubuntu 16.04 --- .github/workflows/c-cpp.yml | 174 ++++++++++++++++++------------------ 1 file changed, 88 insertions(+), 86 deletions(-) diff --git a/.github/workflows/c-cpp.yml b/.github/workflows/c-cpp.yml index ef9e5f172..f68a9e53c 100644 --- a/.github/workflows/c-cpp.yml +++ b/.github/workflows/c-cpp.yml @@ -9,95 +9,95 @@ on: jobs: # Linux - # job_linux_16_04_64_gcc: - # name: ubuntu-16.04 gcc - # runs-on: ubuntu-16.04 - # steps: - # - uses: actions/checkout@v2 - # - name: Install dependencies - # run: sudo apt-get install gcc-5 libusb-1.0.0-dev libgtk-3-dev rpm - # - name: make debug - # run: sudo make clean && make debug - # - name: make test - # run: sudo make clean && make test - # - name: make release - # run: sudo make clean && make release - # - name: sudo make install - # run: sudo make clean && sudo make install - # - name: sudo make package - # run: sudo make package - # - name: sudo make uninstall - # run: sudo make uninstall && sudo make clean + job_linux_16_04_64_gcc: + name: ubuntu-16.04 gcc + runs-on: ubuntu-16.04 + steps: + - uses: actions/checkout@v2 + - name: Install dependencies + run: sudo apt-get install gcc-5 libusb-1.0.0-dev libgtk-3-dev rpm + - name: make debug + run: sudo make clean && make debug + - name: make test + run: sudo make clean && make test + - name: make release + run: sudo make clean && make release + - name: sudo make install + run: sudo make clean && sudo make install + - name: sudo make package + run: sudo make package + - name: sudo make uninstall + run: sudo make uninstall && sudo make clean - # job_linux_16_04_32_gcc: - # name: ubuntu-16.04 gcc 32-bit - # runs-on: ubuntu-16.04 - # steps: - # - uses: actions/checkout@v2 - # - name: Install dependencies - # run: sudo apt-get install gcc-5 libusb-1.0.0-dev libgtk-3-dev rpm - # - name: Set compiler flags - # run: | - # CFLAGS="$CFLAGS -m32" - # CXXFLAGS="$CXXFLAGS -m32" - # LDFLAGS="$LDFLAGS -m32" - # - name: make debug - # run: sudo make clean && make debug - # - name: make test - # run: sudo make clean && make test - # - name: make release - # run: sudo make clean && make release - # - name: sudo make install - # run: sudo make clean && sudo make install - # - name: sudo make package - # run: sudo make package - # - name: sudo make uninstall - # run: sudo make uninstall && sudo make clean + job_linux_16_04_32_gcc: + name: ubuntu-16.04 gcc 32-bit + runs-on: ubuntu-16.04 + steps: + - uses: actions/checkout@v2 + - name: Install dependencies + run: sudo apt-get install gcc-5 libusb-1.0.0-dev libgtk-3-dev rpm + - name: Set compiler flags + run: | + CFLAGS="$CFLAGS -m32" + CXXFLAGS="$CXXFLAGS -m32" + LDFLAGS="$LDFLAGS -m32" + - name: make debug + run: sudo make clean && make debug + - name: make test + run: sudo make clean && make test + - name: make release + run: sudo make clean && make release + - name: sudo make install + run: sudo make clean && sudo make install + - name: sudo make package + run: sudo make package + - name: sudo make uninstall + run: sudo make uninstall && sudo make clean - # job_linux_16_04_64_clang: - # name: ubuntu-16.04 clang - # runs-on: ubuntu-16.04 - # steps: - # - uses: actions/checkout@v2 - # - name: Install dependencies - # run: sudo apt-get install clang-3.5 libusb-1.0.0-dev libgtk-3-dev rpm - # - name: make debug - # run: sudo make clean && make debug - # - name: make test - # run: sudo make clean && make test - # - name: make release - # run: sudo make clean && make release - # - name: sudo make install - # run: sudo make clean && sudo make install - # - name: sudo make package - # run: sudo make package - # - name: sudo make uninstall - # run: sudo make uninstall && sudo make clean + job_linux_16_04_64_clang: + name: ubuntu-16.04 clang + runs-on: ubuntu-16.04 + steps: + - uses: actions/checkout@v2 + - name: Install dependencies + run: sudo apt-get install clang-3.5 libusb-1.0.0-dev libgtk-3-dev rpm + - name: make debug + run: sudo make clean && make debug + - name: make test + run: sudo make clean && make test + - name: make release + run: sudo make clean && make release + - name: sudo make install + run: sudo make clean && sudo make install + - name: sudo make package + run: sudo make package + - name: sudo make uninstall + run: sudo make uninstall && sudo make clean - # job_linux_16_04_32_clang: - # name: ubuntu-16.04 clang 32-bit - # runs-on: ubuntu-16.04 - # steps: - # - uses: actions/checkout@v2 - # - name: Install dependencies - # run: sudo apt-get install clang-3.5 libusb-1.0.0-dev libgtk-3-dev rpm - # - name: Set compiler flags - # run: | - # CFLAGS="$CFLAGS -m32" - # CXXFLAGS="$CXXFLAGS -m32" - # LDFLAGS="$LDFLAGS -m32" - # - name: make debug - # run: sudo make clean && make debug - # - name: make test - # run: sudo make clean && make test - # - name: make release - # run: sudo make clean && make release - # - name: sudo make install - # run: sudo make clean && sudo make install - # - name: sudo make package - # run: sudo make package - # - name: sudo make uninstall - # run: sudo make uninstall && sudo make clean + job_linux_16_04_32_clang: + name: ubuntu-16.04 clang 32-bit + runs-on: ubuntu-16.04 + steps: + - uses: actions/checkout@v2 + - name: Install dependencies + run: sudo apt-get install clang-3.5 libusb-1.0.0-dev libgtk-3-dev rpm + - name: Set compiler flags + run: | + CFLAGS="$CFLAGS -m32" + CXXFLAGS="$CXXFLAGS -m32" + LDFLAGS="$LDFLAGS -m32" + - name: make debug + run: sudo make clean && make debug + - name: make test + run: sudo make clean && make test + - name: make release + run: sudo make clean && make release + - name: sudo make install + run: sudo make clean && sudo make install + - name: sudo make package + run: sudo make package + - name: sudo make uninstall + run: sudo make uninstall && sudo make clean job_linux_18_04_64_gcc: name: ubuntu-18.04 gcc @@ -410,6 +410,7 @@ jobs: run: sudo make package - name: sudo make uninstall run: sudo make uninstall && sudo make clean + # job_macos_11_gcc: # name: macos-11.0 gcc # runs-on: macos-11.0 @@ -448,6 +449,7 @@ jobs: # run: sudo make package # - name: sudo make uninstall # run: sudo make uninstall && sudo make clean + # Linux MinGW cross compliation # job_linux_20_04_cross: From 1e8333e8ac8b7767a83bde6e3e43cd90f3fe0faf Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 25 Apr 2021 20:39:12 +0200 Subject: [PATCH 250/503] Fix for failed merge conflict resolve --- src/stlink-lib/chipid.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index c505ed23a..f260af168 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -763,8 +763,8 @@ static struct stlink_chipid_params devices[] = { }, }; -const struct stlink_chipid_params *stlink_chipid_get_params(uint32_t chipid) { - const struct stlink_chipid_params *params = NULL; +struct stlink_chipid_params *stlink_chipid_get_params_old(uint32_t chipid) { + struct stlink_chipid_params *params = NULL; for (size_t n = 0; n < STLINK_ARRAY_SIZE(devices); n++) if (devices[n].chip_id == chipid) { From 939998de76a904d82ba8248baacf4fc26d98badc Mon Sep 17 00:00:00 2001 From: anton Date: Tue, 27 Apr 2021 19:46:28 +0500 Subject: [PATCH 251/503] Fixed security warning --- src/stlink-lib/logging.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/stlink-lib/logging.c b/src/stlink-lib/logging.c index 87978230d..d7ce13473 100644 --- a/src/stlink-lib/logging.c +++ b/src/stlink-lib/logging.c @@ -29,10 +29,10 @@ int ugly_log(int level, const char *tag, const char *format, ...) { va_list args; va_start(args, format); time_t mytt = time(NULL); - struct tm *tt; - tt = localtime(&mytt); - fprintf(stderr, "%d-%02d-%02dT%02d:%02d:%02d ", tt->tm_year + 1900, - tt->tm_mon + 1, tt->tm_mday, tt->tm_hour, tt->tm_min, tt->tm_sec); + struct tm tt; + localtime_r(&mytt, &tt); + fprintf(stderr, "%d-%02d-%02dT%02d:%02d:%02d ", tt.tm_year + 1900, + tt.tm_mon + 1, tt.tm_mday, tt.tm_hour, tt.tm_min, tt.tm_sec); switch (level) { case UDEBUG: From b652bc48549009a9d85ce7b1fc2449c146c05ae4 Mon Sep 17 00:00:00 2001 From: "R.E. Wolff" Date: Wed, 28 Apr 2021 17:31:34 +0200 Subject: [PATCH 252/503] Chips files in the right place in the sources --- config/chips/F04x.chip | 13 +++++++++++++ config/chips/F07x.chip | 13 +++++++++++++ config/chips/F09X.chip | 13 +++++++++++++ config/chips/F0xx small.chip | 13 +++++++++++++ config/chips/F0xx.chip | 13 +++++++++++++ config/chips/F1 Connectivity line.chip | 13 +++++++++++++ config/chips/F1 Low-density device.chip | 13 +++++++++++++ config/chips/F1xx High-density value line.chip | 13 +++++++++++++ config/chips/F1xx High-density.chip | 13 +++++++++++++ config/chips/F1xx Medium-density.chip | 13 +++++++++++++ config/chips/F1xx Value Line.chip | 13 +++++++++++++ config/chips/F1xx XL-density.chip | 13 +++++++++++++ config/chips/F2xx.chip | 13 +++++++++++++ config/chips/F303 high density.chip | 13 +++++++++++++ config/chips/F334 medium density.chip | 13 +++++++++++++ config/chips/F3xx small.chip | 13 +++++++++++++ config/chips/F3xx.chip | 13 +++++++++++++ config/chips/F410.chip | 13 +++++++++++++ config/chips/F412.chip | 13 +++++++++++++ config/chips/F413.chip | 13 +++++++++++++ config/chips/F42x_F43x.chip | 13 +++++++++++++ config/chips/F446.chip | 13 +++++++++++++ config/chips/F46x_F47x.chip | 13 +++++++++++++ config/chips/F4xx (Dynamic Efficency).chip | 13 +++++++++++++ config/chips/F4xx (low power).chip | 13 +++++++++++++ config/chips/F4xx.chip | 13 +++++++++++++ config/chips/F72x_F73x.chip | 13 +++++++++++++ config/chips/F76xxx.chip | 13 +++++++++++++ config/chips/F7xx.chip | 13 +++++++++++++ config/chips/G030_G031_G041.chip | 13 +++++++++++++ config/chips/G070_G071_G081.chip | 13 +++++++++++++ config/chips/G4 Category-2.chip | 13 +++++++++++++ config/chips/G4 Category-3.chip | 13 +++++++++++++ config/chips/H72x_H73x.chip | 13 +++++++++++++ config/chips/H74x_H75x.chip | 13 +++++++++++++ config/chips/H7Ax_H7Bx.chip | 13 +++++++++++++ config/chips/L011.chip | 13 +++++++++++++ config/chips/L0x3.chip | 13 +++++++++++++ config/chips/L0xx Category 2.chip | 13 +++++++++++++ config/chips/L0xx Category 5.chip | 13 +++++++++++++ config/chips/L152RE.chip | 13 +++++++++++++ config/chips/L1xx Cat.2.chip | 13 +++++++++++++ config/chips/L1xx High-density.chip | 13 +++++++++++++ config/chips/L1xx Medium-Plus-density.chip | 13 +++++++++++++ config/chips/L1xx Medium-density.chip | 13 +++++++++++++ config/chips/L41x.chip | 13 +++++++++++++ config/chips/L43x_L44x.chip | 13 +++++++++++++ config/chips/L45x_46x.chip | 13 +++++++++++++ config/chips/L496x_L4A6x.chip | 13 +++++++++++++ config/chips/L4Rx.chip | 13 +++++++++++++ config/chips/L4xx.chip | 13 +++++++++++++ config/chips/WB55.chip | 13 +++++++++++++ config/chips/stm32f411re.chip | 13 +++++++++++++ config/chips/unknown device.chip | 13 +++++++++++++ src/chips.zip | Bin 16336 -> 0 bytes 55 files changed, 702 insertions(+) create mode 100644 config/chips/F04x.chip create mode 100644 config/chips/F07x.chip create mode 100644 config/chips/F09X.chip create mode 100644 config/chips/F0xx small.chip create mode 100644 config/chips/F0xx.chip create mode 100644 config/chips/F1 Connectivity line.chip create mode 100644 config/chips/F1 Low-density device.chip create mode 100644 config/chips/F1xx High-density value line.chip create mode 100644 config/chips/F1xx High-density.chip create mode 100644 config/chips/F1xx Medium-density.chip create mode 100644 config/chips/F1xx Value Line.chip create mode 100644 config/chips/F1xx XL-density.chip create mode 100644 config/chips/F2xx.chip create mode 100644 config/chips/F303 high density.chip create mode 100644 config/chips/F334 medium density.chip create mode 100644 config/chips/F3xx small.chip create mode 100644 config/chips/F3xx.chip create mode 100644 config/chips/F410.chip create mode 100644 config/chips/F412.chip create mode 100644 config/chips/F413.chip create mode 100644 config/chips/F42x_F43x.chip create mode 100644 config/chips/F446.chip create mode 100644 config/chips/F46x_F47x.chip create mode 100644 config/chips/F4xx (Dynamic Efficency).chip create mode 100644 config/chips/F4xx (low power).chip create mode 100644 config/chips/F4xx.chip create mode 100644 config/chips/F72x_F73x.chip create mode 100644 config/chips/F76xxx.chip create mode 100644 config/chips/F7xx.chip create mode 100644 config/chips/G030_G031_G041.chip create mode 100644 config/chips/G070_G071_G081.chip create mode 100644 config/chips/G4 Category-2.chip create mode 100644 config/chips/G4 Category-3.chip create mode 100644 config/chips/H72x_H73x.chip create mode 100644 config/chips/H74x_H75x.chip create mode 100644 config/chips/H7Ax_H7Bx.chip create mode 100644 config/chips/L011.chip create mode 100644 config/chips/L0x3.chip create mode 100644 config/chips/L0xx Category 2.chip create mode 100644 config/chips/L0xx Category 5.chip create mode 100644 config/chips/L152RE.chip create mode 100644 config/chips/L1xx Cat.2.chip create mode 100644 config/chips/L1xx High-density.chip create mode 100644 config/chips/L1xx Medium-Plus-density.chip create mode 100644 config/chips/L1xx Medium-density.chip create mode 100644 config/chips/L41x.chip create mode 100644 config/chips/L43x_L44x.chip create mode 100644 config/chips/L45x_46x.chip create mode 100644 config/chips/L496x_L4A6x.chip create mode 100644 config/chips/L4Rx.chip create mode 100644 config/chips/L4xx.chip create mode 100644 config/chips/WB55.chip create mode 100644 config/chips/stm32f411re.chip create mode 100644 config/chips/unknown device.chip delete mode 100644 src/chips.zip diff --git a/config/chips/F04x.chip b/config/chips/F04x.chip new file mode 100644 index 000000000..72db26f8c --- /dev/null +++ b/config/chips/F04x.chip @@ -0,0 +1,13 @@ +# Chipid file for F04x +# +chip_id 445 +description F04x +flash_type 1 +flash_pagesize 400 +sram_size 1800 +bootrom_base 1fffec00 +bootrom_size c00 +option_base 0 +option_size 0 +flags 0 + diff --git a/config/chips/F07x.chip b/config/chips/F07x.chip new file mode 100644 index 000000000..cfedfa76f --- /dev/null +++ b/config/chips/F07x.chip @@ -0,0 +1,13 @@ +# Chipid file for F07x +# +chip_id 448 +description F07x +flash_type 1 +flash_pagesize 800 +sram_size 4000 +bootrom_base 1fffc800 +bootrom_size 3000 +option_base 0 +option_size 0 +flags 0 + diff --git a/config/chips/F09X.chip b/config/chips/F09X.chip new file mode 100644 index 000000000..a622cf2f5 --- /dev/null +++ b/config/chips/F09X.chip @@ -0,0 +1,13 @@ +# Chipid file for F09X +# +chip_id 442 +description F09X +flash_type 1 +flash_pagesize 800 +sram_size 8000 +bootrom_base 1fffd800 +bootrom_size 2000 +option_base 0 +option_size 0 +flags 0 + diff --git a/config/chips/F0xx small.chip b/config/chips/F0xx small.chip new file mode 100644 index 000000000..65aea58ac --- /dev/null +++ b/config/chips/F0xx small.chip @@ -0,0 +1,13 @@ +# Chipid file for F0xx small +# +chip_id 444 +description F0xx small +flash_type 1 +flash_pagesize 400 +sram_size 1000 +bootrom_base 1fffec00 +bootrom_size c00 +option_base 0 +option_size 0 +flags 0 + diff --git a/config/chips/F0xx.chip b/config/chips/F0xx.chip new file mode 100644 index 000000000..5a5529412 --- /dev/null +++ b/config/chips/F0xx.chip @@ -0,0 +1,13 @@ +# Chipid file for F0xx +# +chip_id 440 +description F0xx +flash_type 1 +flash_pagesize 400 +sram_size 2000 +bootrom_base 1fffec00 +bootrom_size c00 +option_base 0 +option_size 0 +flags 0 + diff --git a/config/chips/F1 Connectivity line.chip b/config/chips/F1 Connectivity line.chip new file mode 100644 index 000000000..676fd1945 --- /dev/null +++ b/config/chips/F1 Connectivity line.chip @@ -0,0 +1,13 @@ +# Chipid file for F1 Connectivity line +# +chip_id 418 +description F1 Connectivity line +flash_type 1 +flash_pagesize 800 +sram_size 10000 +bootrom_base 1fffb000 +bootrom_size 4800 +option_base 0 +option_size 0 +flags 2 + diff --git a/config/chips/F1 Low-density device.chip b/config/chips/F1 Low-density device.chip new file mode 100644 index 000000000..dcb5e279e --- /dev/null +++ b/config/chips/F1 Low-density device.chip @@ -0,0 +1,13 @@ +# Chipid file for F1 Low-density device +# +chip_id 412 +description F1 Low-density device +flash_type 1 +flash_pagesize 400 +sram_size 2800 +bootrom_base 1ffff000 +bootrom_size 800 +option_base 0 +option_size 0 +flags 2 + diff --git a/config/chips/F1xx High-density value line.chip b/config/chips/F1xx High-density value line.chip new file mode 100644 index 000000000..f30014122 --- /dev/null +++ b/config/chips/F1xx High-density value line.chip @@ -0,0 +1,13 @@ +# Chipid file for F1xx High-density value line +# +chip_id 428 +description F1xx High-density value line +flash_type 1 +flash_pagesize 800 +sram_size 8000 +bootrom_base 1ffff000 +bootrom_size 800 +option_base 0 +option_size 0 +flags 2 + diff --git a/config/chips/F1xx High-density.chip b/config/chips/F1xx High-density.chip new file mode 100644 index 000000000..ed02e691a --- /dev/null +++ b/config/chips/F1xx High-density.chip @@ -0,0 +1,13 @@ +# Chipid file for F1xx High-density +# +chip_id 414 +description F1xx High-density +flash_type 1 +flash_pagesize 800 +sram_size 10000 +bootrom_base 1ffff000 +bootrom_size 800 +option_base 0 +option_size 0 +flags 2 + diff --git a/config/chips/F1xx Medium-density.chip b/config/chips/F1xx Medium-density.chip new file mode 100644 index 000000000..32266b74e --- /dev/null +++ b/config/chips/F1xx Medium-density.chip @@ -0,0 +1,13 @@ +# Chipid file for F1xx Medium-density +# +chip_id 410 +description F1xx Medium-density +flash_type 1 +flash_pagesize 400 +sram_size 5000 +bootrom_base 1ffff000 +bootrom_size 800 +option_base 0 +option_size 0 +flags 2 + diff --git a/config/chips/F1xx Value Line.chip b/config/chips/F1xx Value Line.chip new file mode 100644 index 000000000..929b95496 --- /dev/null +++ b/config/chips/F1xx Value Line.chip @@ -0,0 +1,13 @@ +# Chipid file for F1xx Value Line +# +chip_id 420 +description F1xx Value Line +flash_type 1 +flash_pagesize 400 +sram_size 2000 +bootrom_base 1ffff000 +bootrom_size 800 +option_base 0 +option_size 0 +flags 2 + diff --git a/config/chips/F1xx XL-density.chip b/config/chips/F1xx XL-density.chip new file mode 100644 index 000000000..a7125a429 --- /dev/null +++ b/config/chips/F1xx XL-density.chip @@ -0,0 +1,13 @@ +# Chipid file for F1xx XL-density +# +chip_id 430 +description F1xx XL-density +flash_type 2 +flash_pagesize 800 +sram_size 18000 +bootrom_base 1fffe000 +bootrom_size 1800 +option_base 0 +option_size 0 +flags 2 + diff --git a/config/chips/F2xx.chip b/config/chips/F2xx.chip new file mode 100644 index 000000000..b31be46f3 --- /dev/null +++ b/config/chips/F2xx.chip @@ -0,0 +1,13 @@ +# Chipid file for F2xx +# +chip_id 411 +description F2xx +flash_type 3 +flash_pagesize 20000 +sram_size 20000 +bootrom_base 1fff0000 +bootrom_size 7800 +option_base 1fffc000 +option_size 4 +flags 2 + diff --git a/config/chips/F303 high density.chip b/config/chips/F303 high density.chip new file mode 100644 index 000000000..716c37c1e --- /dev/null +++ b/config/chips/F303 high density.chip @@ -0,0 +1,13 @@ +# Chipid file for F303 high density +# +chip_id 446 +description F303 high density +flash_type 1 +flash_pagesize 800 +sram_size 10000 +bootrom_base 1fffd800 +bootrom_size 2000 +option_base 0 +option_size 0 +flags 2 + diff --git a/config/chips/F334 medium density.chip b/config/chips/F334 medium density.chip new file mode 100644 index 000000000..424f1063c --- /dev/null +++ b/config/chips/F334 medium density.chip @@ -0,0 +1,13 @@ +# Chipid file for F334 medium density +# +chip_id 438 +description F334 medium density +flash_type 1 +flash_pagesize 800 +sram_size 3000 +bootrom_base 1fffd800 +bootrom_size 2000 +option_base 0 +option_size 0 +flags 2 + diff --git a/config/chips/F3xx small.chip b/config/chips/F3xx small.chip new file mode 100644 index 000000000..7f6f5159c --- /dev/null +++ b/config/chips/F3xx small.chip @@ -0,0 +1,13 @@ +# Chipid file for F3xx small +# +chip_id 439 +description F3xx small +flash_type 1 +flash_pagesize 800 +sram_size a000 +bootrom_base 1fffd800 +bootrom_size 2000 +option_base 0 +option_size 0 +flags 2 + diff --git a/config/chips/F3xx.chip b/config/chips/F3xx.chip new file mode 100644 index 000000000..4195f9007 --- /dev/null +++ b/config/chips/F3xx.chip @@ -0,0 +1,13 @@ +# Chipid file for F3xx +# +chip_id 432 +description F3xx +flash_type 1 +flash_pagesize 800 +sram_size a000 +bootrom_base 1ffff000 +bootrom_size 800 +option_base 0 +option_size 0 +flags 2 + diff --git a/config/chips/F410.chip b/config/chips/F410.chip new file mode 100644 index 000000000..3fb1b3d2a --- /dev/null +++ b/config/chips/F410.chip @@ -0,0 +1,13 @@ +# Chipid file for F410 +# +chip_id 458 +description F410 +flash_type 3 +flash_pagesize 4000 +sram_size 8000 +bootrom_base 1fff0000 +bootrom_size 7800 +option_base 0 +option_size 0 +flags 2 + diff --git a/config/chips/F412.chip b/config/chips/F412.chip new file mode 100644 index 000000000..138e6c273 --- /dev/null +++ b/config/chips/F412.chip @@ -0,0 +1,13 @@ +# Chipid file for F412 +# +chip_id 441 +description F412 +flash_type 3 +flash_pagesize 4000 +sram_size 40000 +bootrom_base 1fff0000 +bootrom_size 7800 +option_base 0 +option_size 0 +flags 2 + diff --git a/config/chips/F413.chip b/config/chips/F413.chip new file mode 100644 index 000000000..305a808dc --- /dev/null +++ b/config/chips/F413.chip @@ -0,0 +1,13 @@ +# Chipid file for F413 +# +chip_id 463 +description F413 +flash_type 3 +flash_pagesize 4000 +sram_size 50000 +bootrom_base 1fff0000 +bootrom_size 7800 +option_base 0 +option_size 0 +flags 2 + diff --git a/config/chips/F42x_F43x.chip b/config/chips/F42x_F43x.chip new file mode 100644 index 000000000..c279a0e1d --- /dev/null +++ b/config/chips/F42x_F43x.chip @@ -0,0 +1,13 @@ +# Chipid file for F42x/F43x +# +chip_id 419 +description F42x/F43x +flash_type 3 +flash_pagesize 4000 +sram_size 40000 +bootrom_base 1fff0000 +bootrom_size 7800 +option_base 0 +option_size 0 +flags 2 + diff --git a/config/chips/F446.chip b/config/chips/F446.chip new file mode 100644 index 000000000..6f372c067 --- /dev/null +++ b/config/chips/F446.chip @@ -0,0 +1,13 @@ +# Chipid file for F446 +# +chip_id 421 +description F446 +flash_type 3 +flash_pagesize 20000 +sram_size 20000 +bootrom_base 1fff0000 +bootrom_size 7800 +option_base 1fffc000 +option_size 4 +flags 2 + diff --git a/config/chips/F46x_F47x.chip b/config/chips/F46x_F47x.chip new file mode 100644 index 000000000..6d03bbea2 --- /dev/null +++ b/config/chips/F46x_F47x.chip @@ -0,0 +1,13 @@ +# Chipid file for F46x/F47x +# +chip_id 434 +description F46x/F47x +flash_type 3 +flash_pagesize 4000 +sram_size 40000 +bootrom_base 1fff0000 +bootrom_size 7800 +option_base 0 +option_size 0 +flags 2 + diff --git a/config/chips/F4xx (Dynamic Efficency).chip b/config/chips/F4xx (Dynamic Efficency).chip new file mode 100644 index 000000000..fda012826 --- /dev/null +++ b/config/chips/F4xx (Dynamic Efficency).chip @@ -0,0 +1,13 @@ +# Chipid file for F4xx (Dynamic Efficency) +# +chip_id 433 +description F4xx (Dynamic Efficency) +flash_type 3 +flash_pagesize 4000 +sram_size 18000 +bootrom_base 1fff0000 +bootrom_size 7800 +option_base 0 +option_size 0 +flags 2 + diff --git a/config/chips/F4xx (low power).chip b/config/chips/F4xx (low power).chip new file mode 100644 index 000000000..db9e99ffa --- /dev/null +++ b/config/chips/F4xx (low power).chip @@ -0,0 +1,13 @@ +# Chipid file for F4xx (low power) +# +chip_id 423 +description F4xx (low power) +flash_type 3 +flash_pagesize 4000 +sram_size 10000 +bootrom_base 1fff0000 +bootrom_size 7800 +option_base 0 +option_size 0 +flags 2 + diff --git a/config/chips/F4xx.chip b/config/chips/F4xx.chip new file mode 100644 index 000000000..a9dd110c5 --- /dev/null +++ b/config/chips/F4xx.chip @@ -0,0 +1,13 @@ +# Chipid file for F4xx +# +chip_id 413 +description F4xx +flash_type 3 +flash_pagesize 4000 +sram_size 30000 +bootrom_base 1fff0000 +bootrom_size 7800 +option_base 40023c14 +option_size 4 +flags 2 + diff --git a/config/chips/F72x_F73x.chip b/config/chips/F72x_F73x.chip new file mode 100644 index 000000000..a673b04f0 --- /dev/null +++ b/config/chips/F72x_F73x.chip @@ -0,0 +1,13 @@ +# Chipid file for F72x/F73x +# +chip_id 452 +description F72x/F73x +flash_type 3 +flash_pagesize 800 +sram_size 40000 +bootrom_base 100000 +bootrom_size edc0 +option_base 0 +option_size 0 +flags 2 + diff --git a/config/chips/F76xxx.chip b/config/chips/F76xxx.chip new file mode 100644 index 000000000..c8f9ee108 --- /dev/null +++ b/config/chips/F76xxx.chip @@ -0,0 +1,13 @@ +# Chipid file for F76xxx +# +chip_id 451 +description F76xxx +flash_type 4 +flash_pagesize 800 +sram_size 80000 +bootrom_base 200000 +bootrom_size edc0 +option_base 1fff0000 +option_size 20 +flags 2 + diff --git a/config/chips/F7xx.chip b/config/chips/F7xx.chip new file mode 100644 index 000000000..c704ce2e2 --- /dev/null +++ b/config/chips/F7xx.chip @@ -0,0 +1,13 @@ +# Chipid file for F7xx +# +chip_id 449 +description F7xx +flash_type 3 +flash_pagesize 800 +sram_size 50000 +bootrom_base 100000 +bootrom_size edc0 +option_base 0 +option_size 0 +flags 2 + diff --git a/config/chips/G030_G031_G041.chip b/config/chips/G030_G031_G041.chip new file mode 100644 index 000000000..c6553904e --- /dev/null +++ b/config/chips/G030_G031_G041.chip @@ -0,0 +1,13 @@ +# Chipid file for G030/G031/G041 +# +chip_id 466 +description G030/G031/G041 +flash_type 7 +flash_pagesize 800 +sram_size 2000 +bootrom_base 1fff0000 +bootrom_size 2000 +option_base 1fff7800 +option_size 4 +flags 0 + diff --git a/config/chips/G070_G071_G081.chip b/config/chips/G070_G071_G081.chip new file mode 100644 index 000000000..ab57bbd27 --- /dev/null +++ b/config/chips/G070_G071_G081.chip @@ -0,0 +1,13 @@ +# Chipid file for G070/G071/G081 +# +chip_id 460 +description G070/G071/G081 +flash_type 7 +flash_pagesize 800 +sram_size 9000 +bootrom_base 1fff0000 +bootrom_size 7000 +option_base 1fff7800 +option_size 4 +flags 0 + diff --git a/config/chips/G4 Category-2.chip b/config/chips/G4 Category-2.chip new file mode 100644 index 000000000..400152cd6 --- /dev/null +++ b/config/chips/G4 Category-2.chip @@ -0,0 +1,13 @@ +# Chipid file for G4 Category-2 +# +chip_id 468 +description G4 Category-2 +flash_type 8 +flash_pagesize 800 +sram_size 8000 +bootrom_base 1fff0000 +bootrom_size 7000 +option_base 1ffff800 +option_size 4 +flags 2 + diff --git a/config/chips/G4 Category-3.chip b/config/chips/G4 Category-3.chip new file mode 100644 index 000000000..f8ea053f7 --- /dev/null +++ b/config/chips/G4 Category-3.chip @@ -0,0 +1,13 @@ +# Chipid file for G4 Category-3 +# +chip_id 469 +description G4 Category-3 +flash_type 8 +flash_pagesize 800 +sram_size 18000 +bootrom_base 1fff0000 +bootrom_size 7000 +option_base 1ffff800 +option_size 4 +flags 3 + diff --git a/config/chips/H72x_H73x.chip b/config/chips/H72x_H73x.chip new file mode 100644 index 000000000..e63c855c8 --- /dev/null +++ b/config/chips/H72x_H73x.chip @@ -0,0 +1,13 @@ +# Chipid file for H72x/H73x +# +chip_id 483 +description H72x/H73x +flash_type a +flash_pagesize 20000 +sram_size 20000 +bootrom_base 1ff00000 +bootrom_size 20000 +option_base 5200201c +option_size 2c +flags 2 + diff --git a/config/chips/H74x_H75x.chip b/config/chips/H74x_H75x.chip new file mode 100644 index 000000000..24e85ff66 --- /dev/null +++ b/config/chips/H74x_H75x.chip @@ -0,0 +1,13 @@ +# Chipid file for H74x/H75x +# +chip_id 450 +description H74x/H75x +flash_type a +flash_pagesize 20000 +sram_size 20000 +bootrom_base 1ff00000 +bootrom_size 20000 +option_base 5200201c +option_size 2c +flags 3 + diff --git a/config/chips/H7Ax_H7Bx.chip b/config/chips/H7Ax_H7Bx.chip new file mode 100644 index 000000000..bffd23603 --- /dev/null +++ b/config/chips/H7Ax_H7Bx.chip @@ -0,0 +1,13 @@ +# Chipid file for H7Ax/H7Bx +# +chip_id 480 +description H7Ax/H7Bx +flash_type a +flash_pagesize 2000 +sram_size 20000 +bootrom_base 1ff00000 +bootrom_size 20000 +option_base 5200201c +option_size 2c +flags 3 + diff --git a/config/chips/L011.chip b/config/chips/L011.chip new file mode 100644 index 000000000..02223ddcf --- /dev/null +++ b/config/chips/L011.chip @@ -0,0 +1,13 @@ +# Chipid file for L011 +# +chip_id 457 +description L011 +flash_type 5 +flash_pagesize 80 +sram_size 2000 +bootrom_base 1ff00000 +bootrom_size 2000 +option_base 0 +option_size 0 +flags 0 + diff --git a/config/chips/L0x3.chip b/config/chips/L0x3.chip new file mode 100644 index 000000000..60d75e863 --- /dev/null +++ b/config/chips/L0x3.chip @@ -0,0 +1,13 @@ +# Chipid file for L0x3 +# +chip_id 417 +description L0x3 +flash_type 5 +flash_pagesize 80 +sram_size 2000 +bootrom_base 1ff0000 +bootrom_size 1000 +option_base 1ff80000 +option_size 14 +flags 0 + diff --git a/config/chips/L0xx Category 2.chip b/config/chips/L0xx Category 2.chip new file mode 100644 index 000000000..1cb9e1307 --- /dev/null +++ b/config/chips/L0xx Category 2.chip @@ -0,0 +1,13 @@ +# Chipid file for L0xx Category 2 +# +chip_id 425 +description L0xx Category 2 +flash_type 5 +flash_pagesize 80 +sram_size 2000 +bootrom_base 1ff0000 +bootrom_size 1000 +option_base 1ff80000 +option_size 14 +flags 0 + diff --git a/config/chips/L0xx Category 5.chip b/config/chips/L0xx Category 5.chip new file mode 100644 index 000000000..35df2fb02 --- /dev/null +++ b/config/chips/L0xx Category 5.chip @@ -0,0 +1,13 @@ +# Chipid file for L0xx Category 5 +# +chip_id 447 +description L0xx Category 5 +flash_type 5 +flash_pagesize 80 +sram_size 5000 +bootrom_base 1ff0000 +bootrom_size 2000 +option_base 1ff80000 +option_size 14 +flags 0 + diff --git a/config/chips/L152RE.chip b/config/chips/L152RE.chip new file mode 100644 index 000000000..ec9d24442 --- /dev/null +++ b/config/chips/L152RE.chip @@ -0,0 +1,13 @@ +# Chipid file for L152RE +# +chip_id 437 +description L152RE +flash_type 5 +flash_pagesize 100 +sram_size 14000 +bootrom_base 1ff00000 +bootrom_size 1000 +option_base 0 +option_size 0 +flags 2 + diff --git a/config/chips/L1xx Cat.2.chip b/config/chips/L1xx Cat.2.chip new file mode 100644 index 000000000..7a3080c60 --- /dev/null +++ b/config/chips/L1xx Cat.2.chip @@ -0,0 +1,13 @@ +# Chipid file for L1xx Cat.2 +# +chip_id 429 +description L1xx Cat.2 +flash_type 5 +flash_pagesize 100 +sram_size 8000 +bootrom_base 1ff00000 +bootrom_size 1000 +option_base 0 +option_size 0 +flags 2 + diff --git a/config/chips/L1xx High-density.chip b/config/chips/L1xx High-density.chip new file mode 100644 index 000000000..4f6c85929 --- /dev/null +++ b/config/chips/L1xx High-density.chip @@ -0,0 +1,13 @@ +# Chipid file for L1xx High-density +# +chip_id 436 +description L1xx High-density +flash_type 5 +flash_pagesize 100 +sram_size c000 +bootrom_base 1ff00000 +bootrom_size 1000 +option_base 1ff80000 +option_size 8 +flags 2 + diff --git a/config/chips/L1xx Medium-Plus-density.chip b/config/chips/L1xx Medium-Plus-density.chip new file mode 100644 index 000000000..30ce11e92 --- /dev/null +++ b/config/chips/L1xx Medium-Plus-density.chip @@ -0,0 +1,13 @@ +# Chipid file for L1xx Medium-Plus-density +# +chip_id 427 +description L1xx Medium-Plus-density +flash_type 5 +flash_pagesize 100 +sram_size 8000 +bootrom_base 1ff00000 +bootrom_size 1000 +option_base 0 +option_size 0 +flags 2 + diff --git a/config/chips/L1xx Medium-density.chip b/config/chips/L1xx Medium-density.chip new file mode 100644 index 000000000..a1817c5d6 --- /dev/null +++ b/config/chips/L1xx Medium-density.chip @@ -0,0 +1,13 @@ +# Chipid file for L1xx Medium-density +# +chip_id 416 +description L1xx Medium-density +flash_type 5 +flash_pagesize 100 +sram_size 4000 +bootrom_base 1ff00000 +bootrom_size 1000 +option_base 0 +option_size 0 +flags 2 + diff --git a/config/chips/L41x.chip b/config/chips/L41x.chip new file mode 100644 index 000000000..008c9bfa2 --- /dev/null +++ b/config/chips/L41x.chip @@ -0,0 +1,13 @@ +# Chipid file for L41x +# +chip_id 464 +description L41x +flash_type 6 +flash_pagesize 800 +sram_size a000 +bootrom_base 1fff0000 +bootrom_size 7000 +option_base 0 +option_size 0 +flags 2 + diff --git a/config/chips/L43x_L44x.chip b/config/chips/L43x_L44x.chip new file mode 100644 index 000000000..1d956c15e --- /dev/null +++ b/config/chips/L43x_L44x.chip @@ -0,0 +1,13 @@ +# Chipid file for L43x/L44x +# +chip_id 435 +description L43x/L44x +flash_type 6 +flash_pagesize 800 +sram_size c000 +bootrom_base 1fff0000 +bootrom_size 7000 +option_base 1fff7800 +option_size 4 +flags 2 + diff --git a/config/chips/L45x_46x.chip b/config/chips/L45x_46x.chip new file mode 100644 index 000000000..438821fcc --- /dev/null +++ b/config/chips/L45x_46x.chip @@ -0,0 +1,13 @@ +# Chipid file for L45x/46x +# +chip_id 462 +description L45x/46x +flash_type 6 +flash_pagesize 800 +sram_size 20000 +bootrom_base 1fff0000 +bootrom_size 7000 +option_base 0 +option_size 0 +flags 2 + diff --git a/config/chips/L496x_L4A6x.chip b/config/chips/L496x_L4A6x.chip new file mode 100644 index 000000000..b607e18cc --- /dev/null +++ b/config/chips/L496x_L4A6x.chip @@ -0,0 +1,13 @@ +# Chipid file for L496x/L4A6x +# +chip_id 461 +description L496x/L4A6x +flash_type 6 +flash_pagesize 800 +sram_size 40000 +bootrom_base 1fff0000 +bootrom_size 7000 +option_base 1fff7800 +option_size 4 +flags 2 + diff --git a/config/chips/L4Rx.chip b/config/chips/L4Rx.chip new file mode 100644 index 000000000..e42aba017 --- /dev/null +++ b/config/chips/L4Rx.chip @@ -0,0 +1,13 @@ +# Chipid file for L4Rx +# +chip_id 470 +description L4Rx +flash_type 6 +flash_pagesize 1000 +sram_size a0000 +bootrom_base 1fff0000 +bootrom_size 7000 +option_base 0 +option_size 0 +flags 2 + diff --git a/config/chips/L4xx.chip b/config/chips/L4xx.chip new file mode 100644 index 000000000..10ec24455 --- /dev/null +++ b/config/chips/L4xx.chip @@ -0,0 +1,13 @@ +# Chipid file for L4xx +# +chip_id 415 +description L4xx +flash_type 6 +flash_pagesize 800 +sram_size 18000 +bootrom_base 1fff0000 +bootrom_size 7000 +option_base 1fff7800 +option_size 4 +flags 2 + diff --git a/config/chips/WB55.chip b/config/chips/WB55.chip new file mode 100644 index 000000000..bdc0d4449 --- /dev/null +++ b/config/chips/WB55.chip @@ -0,0 +1,13 @@ +# Chipid file for WB55 +# +chip_id 495 +description WB55 +flash_type 9 +flash_pagesize 1000 +sram_size 40000 +bootrom_base 1fff0000 +bootrom_size 7000 +option_base 0 +option_size 0 +flags 2 + diff --git a/config/chips/stm32f411re.chip b/config/chips/stm32f411re.chip new file mode 100644 index 000000000..ef889c139 --- /dev/null +++ b/config/chips/stm32f411re.chip @@ -0,0 +1,13 @@ +# Chipid file for stm32f411re +# +chip_id 431 +description stm32f411re +flash_type 3 +flash_pagesize 4000 +sram_size 20000 +bootrom_base 1fff0000 +bootrom_size 7800 +option_base 0 +option_size 0 +flags 2 + diff --git a/config/chips/unknown device.chip b/config/chips/unknown device.chip new file mode 100644 index 000000000..63ba47a30 --- /dev/null +++ b/config/chips/unknown device.chip @@ -0,0 +1,13 @@ +# Chipid file for unknown device +# +chip_id 0 +description unknown device +flash_type 0 +flash_pagesize 0 +sram_size 0 +bootrom_base 0 +bootrom_size 0 +option_base 0 +option_size 0 +flags 0 + diff --git a/src/chips.zip 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Wolff" Date: Wed, 28 Apr 2021 18:41:16 +0200 Subject: [PATCH 253/503] Moved the chips files to our own etc directory. --- CMakeLists.txt | 8 ++++++++ src/st-util/gdb-server.c | 3 +-- src/stlink-lib/chipid.c | 4 ++-- 3 files changed, 11 insertions(+), 4 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index 064aa06d5..feca0431a 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -9,6 +9,11 @@ set(CMAKE_ARCHIVE_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}/lib) set(CMAKE_LIBRARY_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}/lib) set(CMAKE_RUNTIME_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}/bin) +set(CMAKE_STLINK_ETC_DIR etc) +set(CMAKE_ETC_CHIPS_DIR ${CMAKE_STLINK_ETC_DIR}/stlink/chips) +set(CMAKE_ETC_CHIPS_DIR_ABS ${CMAKE_INSTALL_PREFIX}/${CMAKE_ETC_CHIPS_DIR}) +add_definitions( -DETC_STLINK_DIR="${CMAKE_ETC_CHIPS_DIR_ABS}" ) + ### # General project settings @@ -274,6 +279,9 @@ install(TARGETS st-info DESTINATION ${CMAKE_INSTALL_BINDIR}) install(TARGETS st-util DESTINATION ${CMAKE_INSTALL_BINDIR}) install(TARGETS st-trace DESTINATION ${CMAKE_INSTALL_BINDIR}) +file(GLOB CHIP_FILES ${CMAKE_SOURCE_DIR}/config/chips/*.chip) +install(FILES ${CHIP_FILES} DESTINATION ${CMAKE_ETC_CHIPS_DIR}) + ### # Device configuration (Linux only) diff --git a/src/st-util/gdb-server.c b/src/st-util/gdb-server.c index 797f4391b..6fe8774f7 100644 --- a/src/st-util/gdb-server.c +++ b/src/st-util/gdb-server.c @@ -219,8 +219,7 @@ int main(int argc, char** argv) { state.connect_mode = CONNECT_NORMAL; // by default, reset board parse_options(argc, argv, &state); - printf("st-util\n"); - init_chipids (NULL); + init_chipids (ETC_STLINK_DIR); sl = stlink_open_usb(state.logging_level, state.connect_mode, state.serialnumber, state.freq); if (sl == NULL) { return(1); } diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index e094f910f..bcb017740 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -782,7 +782,7 @@ void process_chipfile (char *fname) struct stlink_chipid_params *ts; int nc; - fprintf (stderr, "processing chipfile %s.\n", fname); + //fprintf (stderr, "processing chipfile %s.\n", fname); fp = fopen (fname, "r"); if (!fp) { perror (fname); @@ -872,7 +872,7 @@ void init_chipids (char *dir_to_scan) devicelist = NULL; //dump_chips (); - d = opendir("."); + d = opendir(dir_to_scan); if (d) { while ((dir = readdir(d)) != NULL) { nl = strlen (dir->d_name); From 7ee9fbcbd3c2e74253249f92ebfbb28204d131e4 Mon Sep 17 00:00:00 2001 From: "R.E. Wolff" Date: Wed, 28 Apr 2021 18:52:43 +0200 Subject: [PATCH 254/503] Added init to other programs --- src/st-flash/flash.c | 1 + src/st-info/info.c | 2 ++ src/st-trace/trace.c | 2 ++ src/st-util/gdb-server.c | 2 ++ src/stlink-gui/gui.c | 2 ++ 5 files changed, 9 insertions(+) diff --git a/src/st-flash/flash.c b/src/st-flash/flash.c index ede0f1179..cbcd00f47 100644 --- a/src/st-flash/flash.c +++ b/src/st-flash/flash.c @@ -61,6 +61,7 @@ int main(int ac, char** av) { } printf("st-flash %s\n", STLINK_VERSION); + init_chipids (ETC_STLINK_DIR); sl = stlink_open_usb(o.log_level, o.connect, (char *)o.serial, o.freq); diff --git a/src/st-info/info.c b/src/st-info/info.c index a6b4e85c6..7e3e47374 100644 --- a/src/st-info/info.c +++ b/src/st-info/info.c @@ -146,6 +146,8 @@ int main(int ac, char** av) { return(-1); } + init_chipids (ETC_STLINK_DIR); + err = print_data(ac, av); return(err); diff --git a/src/st-trace/trace.c b/src/st-trace/trace.c index a02c64701..754a55c72 100644 --- a/src/st-trace/trace.c +++ b/src/st-trace/trace.c @@ -509,6 +509,8 @@ int main(int argc, char **argv) { usage(); return APP_RESULT_INVALID_PARAMS; } + init_chipids (ETC_STLINK_DIR); + DLOG("show_help = %s\n", settings.show_help ? "true" : "false"); DLOG("show_version = %s\n", settings.show_version ? "true" : "false"); diff --git a/src/st-util/gdb-server.c b/src/st-util/gdb-server.c index 6fe8774f7..49daa9799 100644 --- a/src/st-util/gdb-server.c +++ b/src/st-util/gdb-server.c @@ -219,6 +219,8 @@ int main(int argc, char** argv) { state.connect_mode = CONNECT_NORMAL; // by default, reset board parse_options(argc, argv, &state); + printf("st-util %s\n", STLINK_VERSION); + init_chipids (ETC_STLINK_DIR); sl = stlink_open_usb(state.logging_level, state.connect_mode, state.serialnumber, state.freq); diff --git a/src/stlink-gui/gui.c b/src/stlink-gui/gui.c index 03e999b7f..354ca1088 100644 --- a/src/stlink-gui/gui.c +++ b/src/stlink-gui/gui.c @@ -894,6 +894,8 @@ int main(int argc, char **argv) { gtk_init(&argc, &argv); + init_chipids (ETC_STLINK_DIR); + gui = g_object_new(STLINK_TYPE_GUI, NULL); stlink_gui_build_ui(gui); stlink_gui_init_dnd(gui); From 7e7bd7403efbcf5761465b003ed17ab09a74202f Mon Sep 17 00:00:00 2001 From: anton Date: Thu, 29 Apr 2021 22:47:18 +0500 Subject: [PATCH 255/503] Using localtime instead safe variant in case of compiler below C11 --- src/stlink-lib/logging.c | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/src/stlink-lib/logging.c b/src/stlink-lib/logging.c index d7ce13473..817f3d68e 100644 --- a/src/stlink-lib/logging.c +++ b/src/stlink-lib/logging.c @@ -8,6 +8,7 @@ #include #include #include +#define __STDC_WANT_LIB_EXT1__ 1 #include #include "logging.h" @@ -29,10 +30,22 @@ int ugly_log(int level, const char *tag, const char *format, ...) { va_list args; va_start(args, format); time_t mytt = time(NULL); + + struct tm *ptt; +#if defined(__STDC_VERSION__) && (__STDC_VERSION__ >= 201112L) // C11 struct tm tt; + ptt = &tt; +# if defined (_WIN32) || defined(__STDC_LIB_EXT1__) + localtime_s(&tt, &mytt); +# else localtime_r(&mytt, &tt); - fprintf(stderr, "%d-%02d-%02dT%02d:%02d:%02d ", tt.tm_year + 1900, - tt.tm_mon + 1, tt.tm_mday, tt.tm_hour, tt.tm_min, tt.tm_sec); +# endif +#else + ptt = localtime(&mytt); +#endif + + fprintf(stderr, "%d-%02d-%02dT%02d:%02d:%02d ", ptt->tm_year + 1900, + ptt->tm_mon + 1, ptt->tm_mday, ptt->tm_hour, ptt->tm_min, ptt->tm_sec); switch (level) { case UDEBUG: From a06d13552da5884bd994fddf2655db243e3a6a48 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 2 May 2021 20:38:40 +0200 Subject: [PATCH 256/503] General Project Update - [doc] Minor spelling fixes. - [doc] Updated tool options in tutorial.md - [doc] Clean-up in tutorial.md - Corrected memory size supplements - [doc] Addtional link on STM32 Clone MCUs --- README.md | 2 +- doc/tutorial.md | 76 ++++++++-------------------------------- src/st-flash/flash.c | 6 ++-- src/st-flash/flash.h | 4 +-- src/st-info/info.c | 12 +++---- src/st-util/gdb-server.c | 4 +-- src/stlink-lib/helper.c | 4 +-- tests/flash.c | 2 +- 8 files changed, 31 insertions(+), 79 deletions(-) diff --git a/README.md b/README.md index 600879580..acc2441f8 100644 --- a/README.md +++ b/README.md @@ -1,4 +1,4 @@ -# Open source version of the STMicroelectronics STlink Tools +# Open source version of the STMicroelectronics STLINK Tools [![BSD licensed](https://img.shields.io/badge/license-BSD-blue.svg)](https://raw.githubusercontent.com/hyperium/hyper/master/LICENSE) [![GitHub release](https://img.shields.io/github/release/stlink-org/stlink.svg)](https://github.com/stlink-org/stlink/releases/latest) diff --git a/doc/tutorial.md b/doc/tutorial.md index 71af3d45e..f8f0cbb05 100644 --- a/doc/tutorial.md +++ b/doc/tutorial.md @@ -4,8 +4,9 @@ | Option | Tool | Description | Available
since | | --------------------- | ---------------------------------- | ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ | -------------------- | -| --flash=n[k][m] | st-flash | One can specify `--flash=128k` for example, to override the default value of 64k for the STM32F103C8T6
to assume 128k of flash being present. This option accepts decimal (128k), octal 0200k, or hex 0x80k values.
Leaving the multiplier out is equally valid, e.g.: `--flash=0x20000`. The size may be followed by an optional
"k" or "m" to multiply the given value by 1k (1024) or 1M respectively. | v1.4.0 | -| --freq=n[k][m] | st-info
st-flash
st-util | The frequency of the SWD/JTAG interface can be specified, to override the default 1800 kHz configuration.
This option solely accepts decimal values (5K or 1.8M) with the unit `Hz` being left out. Valid frequencies are:
`5K, 15K, 25K, 50K, 100K, 125K, 240K, 480K, 950K, 1200K, 1800K, 4000K(4M)`. | v1.6.1 | +| --flash=n[k, M] | st-flash | One can specify `--flash=128k` for example, to override the default value of 64k for the STM32F103C8T6
to assume 128k of flash being present. This option accepts decimal (128k), octal 0200k, or hex 0x80k values.
Leaving the multiplier out is equally valid, e.g.: `--flash=0x20000`. The size may be followed by an optional
"k" or "M" to multiply the given value by 1k (1024) or 1M (1024 x 1024) respectively.
One can read arbitary addresses of memory out to a binary file with: `st-flash read out.bin 0x8000000 4096`.
In this example `4096 bytes` are read and subsequently written to `out.bin`.
Binary files (here: `in.bin`) are written into flash memory with: `st-flash write in.bin 0x8000000` | v1.4.0 | +| --format | st-flash | Specify file image format to read or write. Valid formats are `binary` and `ihex`. | v1.3.0 +| --freq=n[k, M] | st-info
st-flash
st-util | The frequency of the SWD/JTAG interface can be specified, to override the default 1800 kHz configuration.
This option solely accepts decimal values with the unit `Hz` being left out. Valid frequencies are:
`5k, 15k, 25k, 50k, 100k, 125k, 240k, 480k, 950k, 1200k (1.2M), 1800k (1.8M), 4000k (4M)`. | v1.6.1 | | --opt | st-flash | Optimisation can be enabled in order to skip flashing empty (0x00 or 0xff) bytes at the end of binary file.
This may cause some garbage data left after a flash operation. This option was enabled by default in earlier releases. | v1.6.1 | | --reset | st-flash | Trigger a reset after flashing. The default uses the hardware reset through `NRST` pin.
A software reset (via `AIRCR`; since v1.5.1) is used, if the hardware reset failed (`NRST` pin not connected). | v1.0.0 | | --connect-under-reset | st-info
st-flash
st-util | Connect under reset. Option makes it possible to connect to the device before code execution. This is useful
when the target contains code that lets the device go to sleep, disables debug pins or other special code. | v1.6.1 | @@ -14,10 +15,19 @@ | --version | st-info
st-flash
st-util | Print version information. | v1.3.0 | | --help | st-flash
st-util | Print list of available commands. | | +### Reading & Writing Option Bytes + +Example to read and write option bytes: + +``` +./st-flash --debug read option_bytes_dump.bin 0x1FFF7800 4 +./st-flash --debug write option_bytes_dump.bin 0x1FFF7800 +``` + ### st-flash: Checksum for binary files When flashing a file, a checksum is calculated for the binary file, both in md5 and the sum algorithm. -The latter is also used by the official ST-Link utility tool from STMicroelectronics as described in the document: [`UM0892 - User manual - STM32 ST-LINK utility software description`](https://www.st.com/resource/en/user_manual/cd00262073-stm32-stlink-utility-software-description-stmicroelectronics.pdf). +The latter is also used by the official ST-LINK utility tool from STMicroelectronics as described in the document: [`UM0892 - User manual STM32 ST-LINK utility software description`](https://www.st.com/resource/en/user_manual/cd00262073-stm32-stlink-utility-software-description-stmicroelectronics.pdf). ### stlink-gui @@ -95,6 +105,7 @@ In the following you find some hints on how to identify your chip and track down - [How to Detect STM32 Fakes](https://www.cnx-software.com/2020/03/22/how-to-detect-stm32-fakes/) - [Confirmation by STMicroelectronics](https://www.mikrocontroller.net/attachment/442839/couterfeit_STM.png) (Marking: 991KA 93 MYS 807) +- [STM32 Clones: The Good, The Bad And The Ugly](https://hackaday.com/2020/10/22/stm32-clones-the-good-the-bad-and-the-ugly/) However it appears that not all counterfeited parts cause problems during operation, but some are known to not even being able to execute a basic "blinky" example binary. Further there can be problems that may not even show up or affect you directly, but somewhen later in time (or maybe never). This demonstrates there is no guarantee for a proper working chip with equal functionality compared to the original. @@ -115,10 +126,6 @@ There are different variants of this message that refer to different issues: - `unknown chip id! 0` --> Target chip (board) is unknown. 1. Microcontroller is in stop/standby mode. 2. The signals `DIO` and `CLK` are reversed on the SWD-Interface. -- `unknown chip id! 0x1a` --> _currently unknown_ -- `unknown chip id! 0x001f` --> _currently unknown_ -- `unknown chip id! 0x3e8` --> _currently unknown_ -- `unknown chip id! 0xa05f0000` --> _currently unknown_ - `unknown chip id! 0x3748` --> A target chip (board) cannot be detected. 1. No target is connected --> In this case `st-info --probe` displays `chip id 0x0748` with STLINK/V2 and `chip id 0x03e8` with STLINK-V3. 2. The chip is connected but has gone into an undefined state of operation where the SWD pins are unresponsive. --> Try to use `--connect-under-reset` while pressing the reset button on the target board. @@ -214,38 +221,6 @@ Your program should now be running, and, if you used one of the blinking examples from libopencm3, the LEDs on the board should be blinking for you. -## Building and flashing a program - -If you want to simply flash binary files to arbitrary sections of -memory, or read arbitary addresses of memory out to a binary file, use -the st-flash tool, as shown below: - -``` -# stlink command to read 4096 from flash into out.bin -$> ./st-flash read out.bin 0x8000000 4096 - -# stlinkv command to write the file in.bin into flash -$> ./st-flash write in.bin 0x8000000 -``` - -It is also possible to write a hexfile which is more convinient: - -``` -$> ./st-flash --format ihex write myapp.hex -``` - -#### - -Of course, you can use this instead of the gdb server, if you prefer. -Just remember to use the “.bin” image, rather than the .elf file. - -``` -# write blink.bin into FLASH -$> [sudo] ./st-flash write fancy_blink.bin 0x08000000 -``` - -Upon reset, the board LEDs should be blinking. - ## Using the gdb server To run the gdb server: @@ -348,26 +323,3 @@ If you would link your executable to `0x08000000` and then do ``` then it would be written to the memory. - -## Writing Option Bytes - -Example to read and write option bytes (currently writing only supported for STM32G0 and STM32L0) - -``` -./st-flash --debug --reset --format binary --flash=128k read option_bytes_dump.bin 0x1FFF7800 4 -./st-flash --debug --reset --format binary --flash=128k write option_bytes_dump.bin 0x1FFF7800 -``` - -# FAQ - -Q: My breakpoints do not work at all or only work once. - -A: Optimizations can cause severe instruction reordering. For example, if you are doing something like `REG = 0x100;' in a loop, the code may be split into two parts: loading 0x100 into some intermediate register and moving that value to REG. When you set up a breakpoint, GDB will hook to the first instruction, which may be called only once if there are enough unused registers. In my experience, -O3 causes that frequently. - -Q: At some point I use GDB command `next', and it hangs. - -A: Sometimes when you will try to use GDB `next` command to skip a loop, it will use a rather inefficient single-stepping way of doing that. Set up a breakpoint manually in that case and do `continue`. - -Q: Load command does not work in GDB. - -A: Some people report XML/EXPAT is not enabled by default when compiling GDB. Memory map parsing thus fail. Use --enable-expat. diff --git a/src/st-flash/flash.c b/src/st-flash/flash.c index ede0f1179..a94d78254 100644 --- a/src/st-flash/flash.c +++ b/src/st-flash/flash.c @@ -26,9 +26,9 @@ static void cleanup(int signum) { } static void usage(void) { - puts("command line: ./st-flash [--debug] [--reset] [--connect-under-reset] [--hot-plug] [--opt] [--serial ] [--format ] [--flash=] [--freq=] [--area=] {read|write} [path] [addr] [size]"); - puts("command line: ./st-flash [--debug] [--connect-under-reset] [--hot-plug] [--freq=] [--serial ] erase"); - puts("command line: ./st-flash [--debug] [--freq=] [--serial ] reset"); + puts("command line: ./st-flash [--debug] [--reset] [--connect-under-reset] [--hot-plug] [--opt] [--serial ] [--format ] [--flash=] [--freq=] [--area=] {read|write} [path] [addr] [size]"); + puts("command line: ./st-flash [--debug] [--connect-under-reset] [--hot-plug] [--freq=] [--serial ] erase"); + puts("command line: ./st-flash [--debug] [--freq=] [--serial ] reset"); puts(" , and : Use hex format."); puts(" : Use decimal, octal or hex (prefix 0xXXX) format, optionally followed by k=KB, or m=MB (eg. --flash=128k)"); puts(" : Can be 'binary' (default) or 'ihex', although must be specified for binary format only."); diff --git a/src/st-flash/flash.h b/src/st-flash/flash.h index cd08db70f..f3d431d65 100644 --- a/src/st-flash/flash.h +++ b/src/st-flash/flash.h @@ -23,9 +23,9 @@ struct flash_opts { enum flash_format format; enum flash_area area; uint32_t val; - size_t flash_size; // --flash=n[k][m] + size_t flash_size; // --flash=n[k, M] int opt; // enable empty tail data drop optimization - int freq; // --freq=n[k][m] frequency of JTAG/SWD + int freq; // --freq=n[k, M] frequency of JTAG/SWD enum connect_type connect; }; diff --git a/src/st-info/info.c b/src/st-info/info.c index a6b4e85c6..a9551cd49 100644 --- a/src/st-info/info.c +++ b/src/st-info/info.c @@ -8,13 +8,13 @@ static void usage(void) { puts("st-info --version"); - puts("st-info --probe [--connect-under-reset] [--hot-plug] [--freq=]"); + puts("st-info --probe [--connect-under-reset] [--hot-plug] [--freq=]"); puts("st-info --serial"); - puts("st-info --flash [--connect-under-reset] [--hot-plug] [--freq=]"); - puts("st-info --pagesize [--connect-under-reset] [--hot-plug] [--freq=]"); - puts("st-info --sram [--connect-under-reset] [--hot-plug] [--freq=]"); - puts("st-info --chipid [--connect-under-reset] [--hot-plug] [--freq=]"); - puts("st-info --descr [--connect-under-reset] [--hot-plug] [--freq=]"); + puts("st-info --flash [--connect-under-reset] [--hot-plug] [--freq=]"); + puts("st-info --pagesize [--connect-under-reset] [--hot-plug] [--freq=]"); + puts("st-info --sram [--connect-under-reset] [--hot-plug] [--freq=]"); + puts("st-info --chipid [--connect-under-reset] [--hot-plug] [--freq=]"); + puts("st-info --descr [--connect-under-reset] [--hot-plug] [--freq=]"); } static void stlink_print_version(stlink_t *sl) { diff --git a/src/st-util/gdb-server.c b/src/st-util/gdb-server.c index 006a0e3aa..83d8c3746 100644 --- a/src/st-util/gdb-server.c +++ b/src/st-util/gdb-server.c @@ -113,7 +113,7 @@ int parse_options(int argc, char** argv, st_state_t *st) { const char * help_str = "%s - usage:\n\n" " -h, --help\t\tPrint this help\n" " -V, --version\t\tPrint the version\n" - " -vXX, --verbose=XX\tSpecify a specific verbosity level (0..99)\n" + " -vXX, --verbose=XX\tSpecify a specific verbosity level (0...99)\n" " -v, --verbose\t\tSpecify generally verbose logging\n" " -p 4242, --listen_port=1234\n" "\t\t\tSet the gdb server listen port. " @@ -125,7 +125,7 @@ int parse_options(int argc, char** argv, st_state_t *st) { "\t\t\tDo not reset board on connection.\n" " -u, --connect-under-reset\n" "\t\t\tConnect to the board before executing any instructions.\n" - " -F 1800K, --freq=1M\n" + " -F 1800k, --freq=1M\n" "\t\t\tSet the frequency of the SWD/JTAG interface.\n" " --semihosting\n" "\t\t\tEnable semihosting support.\n" diff --git a/src/stlink-lib/helper.c b/src/stlink-lib/helper.c index 1f0f71b8d..15e6397bf 100644 --- a/src/stlink-lib/helper.c +++ b/src/stlink-lib/helper.c @@ -19,9 +19,9 @@ int arg_parse_freq(const char *str) { char *tail; int value = (int)strtol(str, &tail, 10); - if ((tail[0] == 'm' || tail[0] == 'M') && tail[1] == '\0') { + if (tail[0] == 'M' && tail[1] == '\0') { value = value*1000; - } else if (((tail[0] != 'k' && tail[0] != 'K') || tail[1] != '\0') && tail[0] != '\0') { + } else if ((tail[0] != 'k' || tail[1] != '\0') && tail[0] != '\0') { return -1; } diff --git a/tests/flash.c b/tests/flash.c index 132066aba..1140566af 100644 --- a/tests/flash.c +++ b/tests/flash.c @@ -109,7 +109,7 @@ static struct Test tests[] = { .freq = 5, .format = FLASH_FORMAT_BINARY } }, - { "--debug --freq 15K --reset write test.bin 0x80000000", 0, + { "--debug --freq 15k --reset write test.bin 0x80000000", 0, { .cmd = FLASH_CMD_WRITE, .serial = { 0 }, .filename = "test.bin", From afad37cc7e80efb1dc460bd9edd0b974d1cce449 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Mon, 3 May 2021 22:27:27 +0200 Subject: [PATCH 257/503] Added Travis CI build test for macOS 10.14 --- .travis.sh | 4 +--- .travis.yml | 56 ++++++++++++++++++++++++++++++++++++++++++++++++++++- 2 files changed, 56 insertions(+), 4 deletions(-) diff --git a/.travis.sh b/.travis.sh index e45cd3609..a156db203 100755 --- a/.travis.sh +++ b/.travis.sh @@ -22,9 +22,7 @@ elif [ "$TRAVIS_JOB_NAME" == "linux-mingw-32" ]; then -DCMAKE_TOOLCHAIN_FILE=$PWD/../cmake/modules/set_toolchain.cmake -DCMAKE_INSTALL_PREFIX=$PWD/install $DIR make && rm -rf build-mingw-32 && cd - -elif [ "$TRAVIS_OS_NAME" == "linux" ]; then - sudo apt-get update -qq || true - +elif [ "$TRAVIS_OS_NAME" == "osx" ]; then echo "--> Building Debug..." mkdir -p build/Debug && cd build/Debug cmake -DCMAKE_BUILD_TYPE=Debug -DCMAKE_INSTALL_PREFIX=$PWD/install $DIR diff --git a/.travis.yml b/.travis.yml index a733019a1..c54c0c6f4 100644 --- a/.travis.yml +++ b/.travis.yml @@ -26,8 +26,62 @@ jobs: packages: ["gcc-10", "libusb-1.0.0-dev", "libgtk-3-dev", "rpm", "mingw-w64"] + ### macOS ### + + - os: osx + env: BADGE=osx + osx_image: xcode10.3 + name: macOS 10.14.4 gcc + compiler: gcc + addons: + homebrew: + packages: + - gcc + - libusb + - gtk+3 + + - os: osx + env: BADGE=osx + osx_image: xcode10.3 + name: macOS 10.14.4 gcc 32-bit + compiler: gcc + addons: + homebrew: + packages: + - gcc + - libusb + - gtk+3 + before_install: + - CFLAGS="$CFLAGS -m32"; CXXFLAGS="$CXXFLAGS -m32"; LDFLAGS="$LDFLAGS -m32"; + + - os: osx + env: BADGE=osx + osx_image: xcode10.3 + name: macOS 10.14.4 clang + compiler: clang + addons: + homebrew: + packages: + - clang + - libusb + - gtk+3 + + - os: osx + env: BADGE=osx + osx_image: xcode10.3 + name: macOS 10.14.4 clang 32-bit + compiler: gcc + addons: + homebrew: + packages: + - clang + - libusb + - gtk+3 + before_install: + - CFLAGS="$CFLAGS -m32"; CXXFLAGS="$CXXFLAGS -m32"; LDFLAGS="$LDFLAGS -m32"; + script: - git fetch --tags - printenv - cmake --version - - if [[ "$TRAVIS_OS_NAME" == "linux" ]]; then ./.travis.sh; fi + - if [[ "$TRAVIS_OS_NAME" == "linux" ]] || [[ "$TRAVIS_OS_NAME" == "osx" ]]; then ./.travis.sh; fi From df69dfa93c77aaeefd1d011f400343c18a836a6b Mon Sep 17 00:00:00 2001 From: Jipeng Zhang Date: Sun, 9 May 2021 23:42:00 -0700 Subject: [PATCH 258/503] add chipids of STM32G0B0/G0B1/G0C1/G050/G051/G061 --- src/stlink-lib/chipid.c | 32 +++++++++++++++++++++++++++++--- src/stlink-lib/chipid.h | 2 ++ 2 files changed, 31 insertions(+), 3 deletions(-) diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index 187a6d957..46cfc267f 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -630,12 +630,12 @@ static const struct stlink_chipid_params devices[] = { .flash_pagesize = 0x800, // 2k (sec 3.2) .sram_size = 0x2000, // 8k (sec 2.3) .bootrom_base = 0x1fff0000, - .bootrom_size = 0x2000, // 8k (sec 2.2.2 table 3) + .bootrom_size = 0x2000, // 8k (sec 2.2.2 table 5 on RM0444 & table 4 on RM0454) .option_base = STM32_G0_OPTION_BYTES_BASE, .option_size = 4, }, { - // STM32G071/081 (from RM0444) + // STM32G070/071/081 (from RM0454 & RM0444) .chip_id = STLINK_CHIPID_STM32_G0_CAT2, .description = "G070/G071/G081", .flash_type = STLINK_FLASH_TYPE_G0, @@ -643,7 +643,33 @@ static const struct stlink_chipid_params devices[] = { .flash_pagesize = 0x800, // 2k (sec 3.2) .sram_size = 0x9000, // 36k (sec 2.3) .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7000, // 28k (sec 2.2.2 table 2) + .bootrom_size = 0x7000, // 28k (sec 2.2.2 table 3 on RM0444 & table 3 on RM0454) + .option_base = STM32_G0_OPTION_BYTES_BASE, + .option_size = 4, + }, + { + // STM32G0B0/0B1/0C1 (from RM0454 & RM0444) + .chip_id = STLINK_CHIPID_STM32_G0_CAT3, + .description = "G0B0/G0B1/G0C1", + .flash_type = STLINK_FLASH_TYPE_G0, + .flash_size_reg = 0x1FFF75E0, // Section 38.2 + .flash_pagesize = 0x800, // 2k (sec 3.2) + .sram_size = 0x24000, // 144k (sec 2.3) + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x7000, // 28k (sec 2.2.2 table 2 on RM0444 & table 2 on RM0454) + .option_base = STM32_G0_OPTION_BYTES_BASE, + .option_size = 4, + }, + { + // STM32G050/051/061 (from RM0454 & RM0444) + .chip_id = STLINK_CHIPID_STM32_G0_CAT4, + .description = "G050/G051/G061", + .flash_type = STLINK_FLASH_TYPE_G0, + .flash_size_reg = 0x1FFF75E0, // Section 38.2 + .flash_pagesize = 0x800, // 2k (sec 3.2) + .sram_size = 0x4800, // 18k (sec 2.3) + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x2000, // 8k (sec 2.2.2 table 4 on RM0444 & table 4 on RM0454) .option_base = STM32_G0_OPTION_BYTES_BASE, .option_size = 4, }, diff --git a/src/stlink-lib/chipid.h b/src/stlink-lib/chipid.h index f790e7899..bb575a287 100644 --- a/src/stlink-lib/chipid.h +++ b/src/stlink-lib/chipid.h @@ -56,11 +56,13 @@ enum stlink_stm32_chipids { STLINK_CHIPID_STM32_H74XXX = 0x450, /* Found on page 3189 in the RM0433*/ STLINK_CHIPID_STM32_F7XXXX = 0x451, STLINK_CHIPID_STM32_F72XXX = 0x452, /* ID found on the NucleoF722ZE board */ + STLINK_CHIPID_STM32_G0_CAT4 = 0x456, /* G050/G051/G061 found on RM0444/RM0454 */ STLINK_CHIPID_STM32_L011 = 0x457, STLINK_CHIPID_STM32_F410 = 0x458, STLINK_CHIPID_STM32_G0_CAT2 = 0x460, /* G070/G071/081 */ STLINK_CHIPID_STM32_F413 = 0x463, STLINK_CHIPID_STM32_G0_CAT1 = 0x466, /* G030/G031/041 */ + STLINK_CHIPID_STM32_G0_CAT3 = 0x467, /* G0B0/G0B1/G0C1 found on RM0444/RM0454 */ STLINK_CHIPID_STM32_G4_CAT2 = 0x468, /* See: RM 0440 s46.6.1 "MCU device ID code" */ STLINK_CHIPID_STM32_G4_CAT3 = 0x469, STLINK_CHIPID_STM32_L4RX = 0x470, /* ID found on the STM32L4R9I-DISCO board */ From f02618c53c3d312aad8bb1cf8f0fb369b1af6ba3 Mon Sep 17 00:00:00 2001 From: Kristie Simpson Date: Tue, 11 May 2021 08:45:05 -0600 Subject: [PATCH 259/503] Adding option byte info for STM32F411XX --- src/common.c | 2 +- src/st-util/gdb-server.c | 2 +- src/stlink-lib/chipid.c | 6 ++++-- src/stlink-lib/chipid.h | 2 +- src/stlink-lib/flash_loader.c | 2 +- 5 files changed, 8 insertions(+), 6 deletions(-) diff --git a/src/common.c b/src/common.c index 7ddd37032..80190f756 100644 --- a/src/common.c +++ b/src/common.c @@ -2739,7 +2739,7 @@ uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr) { (sl->chip_id == STLINK_CHIPID_STM32_F4_DE) || (sl->chip_id == STLINK_CHIPID_STM32_F4_LP) || (sl->chip_id == STLINK_CHIPID_STM32_F4_HD) || - (sl->chip_id == STLINK_CHIPID_STM32_F411RE) || + (sl->chip_id == STLINK_CHIPID_STM32_F411XX) || (sl->chip_id == STLINK_CHIPID_STM32_F446) || (sl->chip_id == STLINK_CHIPID_STM32_F4_DSI) || (sl->chip_id == STLINK_CHIPID_STM32_F72XXX) || diff --git a/src/st-util/gdb-server.c b/src/st-util/gdb-server.c index 83d8c3746..6b68c8143 100644 --- a/src/st-util/gdb-server.c +++ b/src/st-util/gdb-server.c @@ -533,7 +533,7 @@ char* make_memory_map(stlink_t *sl) { if (sl->chip_id == STLINK_CHIPID_STM32_F4 || sl->chip_id == STLINK_CHIPID_STM32_F446 || - sl->chip_id == STLINK_CHIPID_STM32_F411RE) { + sl->chip_id == STLINK_CHIPID_STM32_F411XX) { strcpy(map, memory_map_template_F4); } else if (sl->chip_id == STLINK_CHIPID_STM32_F4_DE) { strcpy(map, memory_map_template_F4_DE); diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index 3d4339526..3a653701d 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -136,14 +136,16 @@ static const struct stlink_chipid_params devices[] = { .flags = CHIP_F_HAS_SWO_TRACING, }, { - .chip_id = STLINK_CHIPID_STM32_F411RE, - .description = "stm32f411re", + .chip_id = STLINK_CHIPID_STM32_F411XX, + .description = "STM32F411xC/E", .flash_type = STLINK_FLASH_TYPE_F4, .flash_size_reg = 0x1FFF7A22, .flash_pagesize = 0x4000, .sram_size = 0x20000, .bootrom_base = 0x1fff0000, .bootrom_size = 0x7800, + .option_base = STM32_F4_OPTION_BYTES_BASE, + .option_size = 4, .flags = CHIP_F_HAS_SWO_TRACING, }, { diff --git a/src/stlink-lib/chipid.h b/src/stlink-lib/chipid.h index f790e7899..23aca5bd2 100644 --- a/src/stlink-lib/chipid.h +++ b/src/stlink-lib/chipid.h @@ -32,7 +32,7 @@ enum stlink_stm32_chipids { STLINK_CHIPID_STM32_F1_VL_HIGH = 0x428, STLINK_CHIPID_STM32_L1_CAT2 = 0x429, STLINK_CHIPID_STM32_F1_XL = 0x430, - STLINK_CHIPID_STM32_F411RE = 0x431, + STLINK_CHIPID_STM32_F411XX = 0x431, STLINK_CHIPID_STM32_F37x = 0x432, STLINK_CHIPID_STM32_F4_DE = 0x433, STLINK_CHIPID_STM32_F4_DSI = 0x434, diff --git a/src/stlink-lib/flash_loader.c b/src/stlink-lib/flash_loader.c index 4ec91258b..d492716db 100644 --- a/src/stlink-lib/flash_loader.c +++ b/src/stlink-lib/flash_loader.c @@ -260,7 +260,7 @@ int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* sl->chip_id == STLINK_CHIPID_STM32_F4_HD || sl->chip_id == STLINK_CHIPID_STM32_F4_DSI || sl->chip_id == STLINK_CHIPID_STM32_F410 || - sl->chip_id == STLINK_CHIPID_STM32_F411RE || + sl->chip_id == STLINK_CHIPID_STM32_F411XX || sl->chip_id == STLINK_CHIPID_STM32_F412 || sl->chip_id == STLINK_CHIPID_STM32_F413 || sl->chip_id == STLINK_CHIPID_STM32_F446) { From aa5dd2ccd2413d0fc6ea2f5035ec3d11119239ac Mon Sep 17 00:00:00 2001 From: anton Date: Thu, 13 May 2021 23:06:02 +0500 Subject: [PATCH 260/503] Reworked connection under reset --- src/common.c | 17 +++++++++++------ src/st-flash/flash.c | 2 +- src/stlink-lib/usb.c | 11 ++++++++++- 3 files changed, 22 insertions(+), 8 deletions(-) diff --git a/src/common.c b/src/common.c index 80190f756..556008d4d 100644 --- a/src/common.c +++ b/src/common.c @@ -4902,21 +4902,26 @@ int stlink_target_connect(stlink_t *sl, enum connect_type connect) { uint32_t dhcsr; if (connect == CONNECT_UNDER_RESET) { + stlink_enter_swd_mode(sl); + stlink_jtag_reset(sl, STLINK_JTAG_DRIVE_NRST_LOW); + stlink_force_debug(sl); + // minimum reset pulse duration of 20 us (RM0008, 8.1.2 Power reset) usleep(20); - if (stlink_current_mode(sl) != STLINK_DEV_DEBUG_MODE) { - stlink_enter_swd_mode(sl); - } - stlink_force_debug(sl); - // clear S_RESET_ST in DHCSR register stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); stlink_jtag_reset(sl, STLINK_JTAG_DRIVE_NRST_HIGH); - usleep(10000); + + // try to halted core after reset + unsigned timeout = time_ms() + 10; + while (time_ms() < timeout) { + sl->backend->force_debug(sl); + usleep(100); + } // check NRST connection dhcsr = 0; diff --git a/src/st-flash/flash.c b/src/st-flash/flash.c index a94d78254..262784e1e 100644 --- a/src/st-flash/flash.c +++ b/src/st-flash/flash.c @@ -68,7 +68,7 @@ int main(int ac, char** av) { if (sl->flash_type == STLINK_FLASH_TYPE_UNKNOWN) { printf("Failed to connect to target\n"); - return(-1); + goto on_error; } if ( o.flash_size != 0u && o.flash_size != sl->flash_size ) { diff --git a/src/stlink-lib/usb.c b/src/stlink-lib/usb.c index 2754db06f..1d26508eb 100644 --- a/src/stlink-lib/usb.c +++ b/src/stlink-lib/usb.c @@ -1343,11 +1343,20 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, enum connect_type connect, // initialize stlink version (sl->version) stlink_version(sl); - if (stlink_current_mode(sl) == STLINK_DEV_DFU_MODE) { + int mode = stlink_current_mode(sl); + if (mode == STLINK_DEV_DFU_MODE) { // this seems to work, and is unnecessary information for the user. // demoted to debug -- REW DLOG("-- exit_dfu_mode\n"); stlink_exit_dfu_mode(sl); + } else if (mode == STLINK_DEV_DEBUG_MODE && + connect == CONNECT_UNDER_RESET) { + // for the connect under reset only + // OpenOСD says (official documentation is not available) that + // the NRST pin must be pull down before selecting the SWD/JTAG mode + WLOG("-- exit_debug_mode\n"); + stlink_exit_debug_mode(sl); + _stlink_usb_jtag_reset(sl, STLINK_JTAG_DRIVE_NRST_LOW); } sl->freq = freq; From 616fd437d48044ddffad729f818960cabfd53911 Mon Sep 17 00:00:00 2001 From: anton Date: Fri, 14 May 2021 21:49:17 +0500 Subject: [PATCH 261/503] Removed warning that could mislead the user --- src/common.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/src/common.c b/src/common.c index 556008d4d..3931a8b42 100644 --- a/src/common.c +++ b/src/common.c @@ -1926,11 +1926,7 @@ int stlink_version(stlink_t *sl) { DLOG("swim version = 0x%x\n", sl->version.swim_v); if (sl->version.jtag_v == 0) { - DLOG(" notice: the firmware doesn't support a jtag/swd interface\n"); - } - - if (sl->version.swim_v == 0) { - DLOG(" notice: the firmware doesn't support a swim interface\n"); + WLOG(" warning: stlink doesn't support JTAG/SWD interface\n"); } return (0); From 22fba0249fe51bdcae607101c5b8a637345eeca8 Mon Sep 17 00:00:00 2001 From: anton Date: Sat, 15 May 2021 22:32:57 +0500 Subject: [PATCH 262/503] Cleaned up code, made minor fixes --- inc/stlink.h | 31 +++------------- src/common.c | 48 +++++++++++++------------ src/st-flash/flash.c | 14 -------- src/st-info/info.c | 9 ----- src/stlink-gui/gui.c | 13 +------ src/stlink-lib/commands.h | 22 ++++++++++-- src/stlink-lib/sg.c | 8 ++--- src/stlink-lib/usb.c | 76 ++++++++++++++++++--------------------- 8 files changed, 89 insertions(+), 132 deletions(-) diff --git a/inc/stlink.h b/inc/stlink.h index ec119c145..3bc518c87 100644 --- a/inc/stlink.h +++ b/inc/stlink.h @@ -25,7 +25,7 @@ extern "C" { // #define Q_BUF_LEN 96 #define Q_BUF_LEN (1024 * 100) -// STLINK_DEBUG_RESETSYS, etc: +/* Statuses of core */ enum target_state { TARGET_UNKNOWN = 0, TARGET_RUNNING = 1, @@ -37,38 +37,15 @@ enum target_state { #define STLINK_CORE_RUNNING 0x80 #define STLINK_CORE_HALTED 0x81 -#define STLINK_GET_VERSION 0xF1 -#define STLINK_GET_CURRENT_MODE 0xF5 -#define STLINK_GET_TARGET_VOLTAGE 0xF7 - -#define STLINK_DEBUG_COMMAND 0xF2 -#define STLINK_DFU_COMMAND 0xF3 -#define STLINK_DFU_EXIT 0x07 - -// STLINK_GET_CURRENT_MODE +/* STLINK modes */ #define STLINK_DEV_DFU_MODE 0x00 #define STLINK_DEV_MASS_MODE 0x01 #define STLINK_DEV_DEBUG_MODE 0x02 #define STLINK_DEV_UNKNOWN_MODE -1 -// TODO - possible poor names... -#define STLINK_SWD_ENTER 0x30 -#define STLINK_SWD_READCOREID 0x32 // TBD -#define STLINK_JTAG_WRITEDEBUG_32BIT 0x35 -#define STLINK_JTAG_READDEBUG_32BIT 0x36 -#define STLINK_JTAG_DRIVE_NRST 0x3C - /* NRST pin states */ -#define STLINK_JTAG_DRIVE_NRST_LOW 0x00 -#define STLINK_JTAG_DRIVE_NRST_HIGH 0x01 -#define STLINK_JTAG_DRIVE_NRST_PULSE 0x02 - -#define STLINK_DEBUG_APIV2_SWD_SET_FREQ 0x43 - -#define STLINK_APIV3_SET_COM_FREQ 0x61 -#define STLINK_APIV3_GET_COM_FREQ 0x62 - -#define STLINK_APIV3_GET_VERSION_EX 0xFB +#define STLINK_DEBUG_APIV2_DRIVE_NRST_LOW 0x00 +#define STLINK_DEBUG_APIV2_DRIVE_NRST_HIGH 0x01 /* Baud rate divisors for SWDCLK */ #define STLINK_SWDCLK_4MHZ_DIVISOR 0 diff --git a/src/common.c b/src/common.c index 3931a8b42..ee91fa487 100644 --- a/src/common.c +++ b/src/common.c @@ -1275,8 +1275,8 @@ static void stop_wdg_in_debug(stlink_t *sl) { case STLINK_FLASH_TYPE_F1_XL: case STLINK_FLASH_TYPE_G4: dbgmcu_cr = STM32F0_DBGMCU_CR; - set = - (1 << STM32F0_DBGMCU_CR_IWDG_STOP) | (1 << STM32F0_DBGMCU_CR_WWDG_STOP); + set = (1 << STM32F0_DBGMCU_CR_IWDG_STOP) | + (1 << STM32F0_DBGMCU_CR_WWDG_STOP); break; case STLINK_FLASH_TYPE_F4: case STLINK_FLASH_TYPE_F7: @@ -1441,13 +1441,14 @@ void stlink_close(stlink_t *sl) { } int stlink_exit_debug_mode(stlink_t *sl) { - int ret; - DLOG("*** stlink_exit_debug_mode ***\n"); - ret = stlink_write_debug32(sl, STLINK_REG_DHCSR, STLINK_REG_DHCSR_DBGKEY); - if (ret == -1) { - return (ret); + if (sl->flash_type != STLINK_FLASH_TYPE_UNKNOWN) { + // stop debugging if the target has been identified + int ret = stlink_write_debug32(sl, STLINK_REG_DHCSR, STLINK_REG_DHCSR_DBGKEY); + if (ret == -1) { + return (ret); + } } return (sl->backend->exit_debug_mode(sl)); @@ -1462,9 +1463,12 @@ int stlink_enter_swd_mode(stlink_t *sl) { int stlink_force_debug(stlink_t *sl) { DLOG("*** stlink_force_debug_mode ***\n"); int res = sl->backend->force_debug(sl); + if (res) { + return (res); + } // Stop the watchdogs in the halted state for suppress target reboot stop_wdg_in_debug(sl); - return (res); + return (0); } int stlink_exit_dfu_mode(stlink_t *sl) { @@ -1540,6 +1544,7 @@ int stlink_chip_id(stlink_t *sl, uint32_t *chip_id) { if (ret || !(*chip_id)) { *chip_id = 0; + ret = ret?:-1; ELOG("Could not find chip id!\n"); } else { *chip_id = (*chip_id) & 0xfff; @@ -1771,10 +1776,10 @@ int stlink_reset(stlink_t *sl, enum reset_type type) { if (type == RESET_HARD || type == RESET_AUTO) { // hardware target reset if (sl->version.stlink_v > 1) { - stlink_jtag_reset(sl, STLINK_JTAG_DRIVE_NRST_LOW); + stlink_jtag_reset(sl, STLINK_DEBUG_APIV2_DRIVE_NRST_LOW); // minimum reset pulse duration of 20 us (RM0008, 8.1.2 Power reset) usleep(100); - stlink_jtag_reset(sl, STLINK_JTAG_DRIVE_NRST_HIGH); + stlink_jtag_reset(sl, STLINK_DEBUG_APIV2_DRIVE_NRST_HIGH); } if (sl->backend->reset(sl)) { return (-1); @@ -4895,24 +4900,21 @@ int stlink_fwrite_option_bytes(stlink_t *sl, const char *path, } int stlink_target_connect(stlink_t *sl, enum connect_type connect) { - uint32_t dhcsr; - if (connect == CONNECT_UNDER_RESET) { stlink_enter_swd_mode(sl); - stlink_jtag_reset(sl, STLINK_JTAG_DRIVE_NRST_LOW); + stlink_jtag_reset(sl, STLINK_DEBUG_APIV2_DRIVE_NRST_LOW); - stlink_force_debug(sl); + // try to halt the core before reset + // this is useful if the NRST pin is not connected + sl->backend->force_debug(sl); // minimum reset pulse duration of 20 us (RM0008, 8.1.2 Power reset) usleep(20); - // clear S_RESET_ST in DHCSR register - stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); - - stlink_jtag_reset(sl, STLINK_JTAG_DRIVE_NRST_HIGH); + stlink_jtag_reset(sl, STLINK_DEBUG_APIV2_DRIVE_NRST_HIGH); - // try to halted core after reset + // try to halt the core after reset unsigned timeout = time_ms() + 10; while (time_ms() < timeout) { sl->backend->force_debug(sl); @@ -4920,7 +4922,7 @@ int stlink_target_connect(stlink_t *sl, enum connect_type connect) { } // check NRST connection - dhcsr = 0; + uint32_t dhcsr = 0; stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); if ((dhcsr & STLINK_REG_DHCSR_S_RESET_ST) == 0) { WLOG("NRST is not connected\n"); @@ -4930,8 +4932,10 @@ int stlink_target_connect(stlink_t *sl, enum connect_type connect) { stlink_soft_reset(sl, 1 /* halt on reset */); } - if (stlink_current_mode(sl) != STLINK_DEV_DEBUG_MODE) { - stlink_enter_swd_mode(sl); + if (stlink_current_mode(sl) != STLINK_DEV_DEBUG_MODE && + stlink_enter_swd_mode(sl)) { + printf("Failed to enter SWD mode\n"); + return -1; } if (connect == CONNECT_NORMAL) { diff --git a/src/st-flash/flash.c b/src/st-flash/flash.c index 262784e1e..be1ef60c2 100644 --- a/src/st-flash/flash.c +++ b/src/st-flash/flash.c @@ -84,20 +84,6 @@ int main(int ac, char** av) { signal(SIGTERM, &cleanup); signal(SIGSEGV, &cleanup); - if (stlink_current_mode(sl) == STLINK_DEV_DFU_MODE) { - if (stlink_exit_dfu_mode(sl)) { - printf("Failed to exit DFU mode\n"); - goto on_error; - } - } - - if (stlink_current_mode(sl) != STLINK_DEV_DEBUG_MODE) { - if (stlink_enter_swd_mode(sl)) { - printf("Failed to enter SWD mode\n"); - goto on_error; - } - } - // core must be halted to use RAM based flashloaders if (stlink_force_debug(sl)) { printf("Failed to halt the core\n"); diff --git a/src/st-info/info.c b/src/st-info/info.c index a9551cd49..7eda5d6ff 100644 --- a/src/st-info/info.c +++ b/src/st-info/info.c @@ -42,7 +42,6 @@ static void stlink_print_info(stlink_t *sl) { printf(" chipid: 0x%.4x\n", sl->chip_id); params = stlink_chipid_get_params(sl->chip_id); - if (params) { printf(" descr: %s\n", params->description); } } @@ -103,15 +102,8 @@ static int print_data(int ac, char **av) { // open first st-link device sl = stlink_open_usb(0, connect, NULL, freq); - if (sl == NULL) { return(-1); } - sl->verbose = 0; - - if (stlink_current_mode(sl) == STLINK_DEV_DFU_MODE) { stlink_exit_dfu_mode(sl); } - - if (stlink_current_mode(sl) != STLINK_DEV_DEBUG_MODE) { stlink_enter_swd_mode(sl); } - if (strcmp(av[1], "--serial") == 0) { printf("%s\n", sl->serial); } else if (strcmp(av[1], "--flash") == 0) { @@ -124,7 +116,6 @@ static int print_data(int ac, char **av) { printf("0x%.4x\n", sl->chip_id); } else if (strcmp(av[1], "--descr") == 0) { const struct stlink_chipid_params *params = stlink_chipid_get_params(sl->chip_id); - if (params == NULL) { return(-1); } printf("%s\n", params->description); diff --git a/src/stlink-gui/gui.c b/src/stlink-gui/gui.c index 03e999b7f..653428735 100644 --- a/src/stlink-gui/gui.c +++ b/src/stlink-gui/gui.c @@ -495,24 +495,13 @@ static void connect_button_cb(GtkWidget *widget, gpointer data) { if (gui->sl != NULL) { return; } - gui->sl = stlink_v1_open(0, 1); // try version 1 then version 2 - - if (gui->sl == NULL) { gui->sl = stlink_open_usb(0, 1, NULL, 0); } + gui->sl = stlink_open_usb(0, 1, NULL, 0); if (gui->sl == NULL) { stlink_gui_set_info_error_message(gui, "Failed to connect to STLink."); return; } - // code below taken from flash/main.c, refactoring might be in order - if (stlink_current_mode(gui->sl) == STLINK_DEV_DFU_MODE) { - stlink_exit_dfu_mode(gui->sl); - } - - if (stlink_current_mode(gui->sl) != STLINK_DEV_DEBUG_MODE) { - stlink_enter_swd_mode(gui->sl); - } - stlink_gui_set_connected(gui); } diff --git a/src/stlink-lib/commands.h b/src/stlink-lib/commands.h index dac82b8e6..136adf80e 100644 --- a/src/stlink-lib/commands.h +++ b/src/stlink-lib/commands.h @@ -1,8 +1,17 @@ #ifndef STLINK_COMMANDS_H_ #define STLINK_COMMANDS_H_ +enum stlink_commands { + STLINK_GET_VERSION = 0xF1, + STLINK_DEBUG_COMMAND = 0xF2, + STLINK_DFU_COMMAND = 0xF3, + STLINK_GET_CURRENT_MODE = 0xF5, + STLINK_GET_TARGET_VOLTAGE = 0xF7, + STLINK_GET_VERSION_APIV3 = 0xFB +}; + enum stlink_debug_commands { - STLINK_DEBUG_ENTER_JTAG = 0x00, + STLINK_DEBUG_ENTER_JTAG_RESET = 0x00, STLINK_DEBUG_GETSTATUS = 0x01, STLINK_DEBUG_FORCEDEBUG = 0x02, STLINK_DEBUG_APIV1_RESETSYS = 0x03, @@ -29,11 +38,20 @@ enum stlink_debug_commands { STLINK_DEBUG_APIV2_READDEBUGREG = 0x36, STLINK_DEBUG_APIV2_READALLREGS = 0x3A, STLINK_DEBUG_APIV2_GETLASTRWSTATUS = 0x3B, + STLINK_DEBUG_APIV2_DRIVE_NRST = 0x3C, STLINK_DEBUG_APIV2_GETLASTRWSTATUS2 = 0x3E, STLINK_DEBUG_APIV2_START_TRACE_RX = 0x40, STLINK_DEBUG_APIV2_STOP_TRACE_RX = 0x41, STLINK_DEBUG_APIV2_GET_TRACE_NB = 0x42, - STLINK_DEBUG_ENTER_SWD = 0xa3 + STLINK_DEBUG_APIV2_SWD_SET_FREQ = 0x43, + STLINK_DEBUG_APIV3_SET_COM_FREQ = 0x61, + STLINK_DEBUG_APIV3_GET_COM_FREQ = 0x62, + STLINK_DEBUG_ENTER_SWD = 0xa3, + STLINK_DEBUG_ENTER_JTAG_NO_RESET = 0xa4, +}; + +enum stlink_dfu_commands { + STLINK_DFU_EXIT = 0x07 }; #endif // STLINK_COMMANDS_H_ diff --git a/src/stlink-lib/sg.c b/src/stlink-lib/sg.c index 07971284f..18792c89f 100644 --- a/src/stlink-lib/sg.c +++ b/src/stlink-lib/sg.c @@ -470,7 +470,7 @@ int _stlink_sg_enter_jtag_mode(stlink_t *sl) { DLOG("\n*** stlink_enter_jtag_mode ***\n"); clear_cdb(sg); sg->cdb_cmd_blk[1] = STLINK_DEBUG_APIV1_ENTER; - sg->cdb_cmd_blk[2] = STLINK_DEBUG_ENTER_JTAG; + sg->cdb_cmd_blk[2] = STLINK_DEBUG_ENTER_JTAG_RESET; sl->q_len = 0; return(stlink_q(sl)); } @@ -570,7 +570,7 @@ int _stlink_sg_reset(stlink_t *sl) { int _stlink_sg_jtag_reset(stlink_t *sl, int value) { struct stlink_libsg *sg = sl->backend_data; clear_cdb(sg); - sg->cdb_cmd_blk[1] = STLINK_JTAG_DRIVE_NRST; + sg->cdb_cmd_blk[1] = STLINK_DEBUG_APIV2_DRIVE_NRST; sg->cdb_cmd_blk[2] = (value) ? 0 : 1; sl->q_len = 3; sg->q_addr = 2; @@ -876,7 +876,7 @@ int _stlink_sg_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { int _stlink_sg_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data) { struct stlink_libsg *sg = sl->backend_data; clear_cdb(sg); - sg->cdb_cmd_blk[1] = STLINK_JTAG_WRITEDEBUG_32BIT; + sg->cdb_cmd_blk[1] = STLINK_DEBUG_APIV2_WRITEDEBUGREG; // 2-5: addr write_uint32(sg->cdb_cmd_blk + 2, addr); write_uint32(sg->cdb_cmd_blk + 6, data); @@ -888,7 +888,7 @@ int _stlink_sg_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data) { int _stlink_sg_read_debug32(stlink_t *sl, uint32_t addr, uint32_t *data) { struct stlink_libsg *sg = sl->backend_data; clear_cdb(sg); - sg->cdb_cmd_blk[1] = STLINK_JTAG_READDEBUG_32BIT; + sg->cdb_cmd_blk[1] = STLINK_DEBUG_APIV2_READDEBUGREG; // 2-5: addr write_uint32(sg->cdb_cmd_blk + 2, addr); sl->q_len = 8; diff --git a/src/stlink-lib/usb.c b/src/stlink-lib/usb.c index 1d26508eb..bbdc2c27b 100644 --- a/src/stlink-lib/usb.c +++ b/src/stlink-lib/usb.c @@ -158,30 +158,24 @@ int _stlink_usb_version(stlink_t *sl) { unsigned char* const data = sl->q_buf; unsigned char* const cmd = sl->c_buf; ssize_t size; - uint32_t rep_len = 6; - int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); - - cmd[i++] = STLINK_GET_VERSION; - - size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); - - if (size == -1) { - printf("[!] send_recv STLINK_GET_VERSION\n"); - return((int)size); - } + uint32_t rep_len; + int i; - /* STLINK-V3 requires a specific command */ if (sl->version.stlink_v == 3) { + // STLINK-V3 version is determined by another command rep_len = 12; i = fill_command(sl, SG_DXFER_FROM_DEV, 16); - cmd[i++] = STLINK_APIV3_GET_VERSION_EX; - - size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); + cmd[i++] = STLINK_GET_VERSION_APIV3; + } else { + rep_len = 6; + i = fill_command(sl, SG_DXFER_FROM_DEV, 6); + cmd[i++] = STLINK_GET_VERSION; + } - if (size != (ssize_t)rep_len) { - printf("[!] send_recv STLINK_APIV3_GET_VERSION_EX\n"); - return((int)size); - } + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); + if (size != (ssize_t)rep_len) { + printf("[!] send_recv STLINK_GET_VERSION\n"); + return((int)size); } return(0); @@ -225,12 +219,12 @@ int _stlink_usb_read_debug32(stlink_t *sl, uint32_t addr, uint32_t *data) { int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); cmd[i++] = STLINK_DEBUG_COMMAND; - cmd[i++] = STLINK_JTAG_READDEBUG_32BIT; + cmd[i++] = STLINK_DEBUG_APIV2_READDEBUGREG; write_uint32(&cmd[i], addr); size = send_recv(slu, 1, cmd, slu->cmd_len, rdata, rep_len); if (size == -1) { - printf("[!] send_recv STLINK_JTAG_READDEBUG_32BIT\n"); + printf("[!] send_recv STLINK_DEBUG_APIV2_READDEBUGREG\n"); return((int)size); } @@ -248,13 +242,13 @@ int _stlink_usb_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data) { int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); cmd[i++] = STLINK_DEBUG_COMMAND; - cmd[i++] = STLINK_JTAG_WRITEDEBUG_32BIT; + cmd[i++] = STLINK_DEBUG_APIV2_WRITEDEBUGREG; write_uint32(&cmd[i], addr); write_uint32(&cmd[i + 4], data); size = send_recv(slu, 1, cmd, slu->cmd_len, rdata, rep_len); if (size == -1) { - printf("[!] send_recv STLINK_JTAG_WRITEDEBUG_32BIT\n"); + printf("[!] send_recv STLINK_DEBUG_APIV2_WRITEDEBUGREG\n"); return((int)size); } @@ -543,12 +537,12 @@ int _stlink_usb_jtag_reset(stlink_t * sl, int value) { int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); cmd[i++] = STLINK_DEBUG_COMMAND; - cmd[i++] = STLINK_JTAG_DRIVE_NRST; + cmd[i++] = STLINK_DEBUG_APIV2_DRIVE_NRST; cmd[i++] = value; size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); if (size == -1) { - printf("[!] send_recv STLINK_JTAG_DRIVE_NRST\n"); + printf("[!] send_recv STLINK_DEBUG_APIV2_DRIVE_NRST\n"); return((int)size); } @@ -675,7 +669,7 @@ int _stlink_usb_set_swdclk(stlink_t* sl, int clk_freq) { i = fill_command(sl, SG_DXFER_FROM_DEV, 16); cmd[i++] = STLINK_DEBUG_COMMAND; - cmd[i++] = STLINK_APIV3_GET_COM_FREQ; + cmd[i++] = STLINK_DEBUG_APIV3_GET_COM_FREQ; cmd[i++] = 0; // SWD mode size = send_recv(slu, 1, cmd, slu->cmd_len, data, 52); @@ -694,13 +688,13 @@ int _stlink_usb_set_swdclk(stlink_t* sl, int clk_freq) { // Set to zero all the next entries for (i = speeds_size; i < STLINK_V3_MAX_FREQ_NB; i++) map[i] = 0; - if (!clk_freq) clk_freq = 1800; // set default frequency + if (!clk_freq) clk_freq = 1000; // set default frequency speed_index = _stlink_match_speed_map(map, STLINK_ARRAY_SIZE(map), clk_freq); i = fill_command(sl, SG_DXFER_FROM_DEV, 16); cmd[i++] = STLINK_DEBUG_COMMAND; - cmd[i++] = STLINK_APIV3_SET_COM_FREQ; + cmd[i++] = STLINK_DEBUG_APIV3_SET_COM_FREQ; cmd[i++] = 0; // SWD mode cmd[i++] = 0; cmd[i++] = (uint8_t)((map[speed_index] >> 0) & 0xFF); @@ -1180,10 +1174,9 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, enum connect_type connect, int config; sl = calloc(1, sizeof(stlink_t)); - slu = calloc(1, sizeof(struct stlink_libusb)); - if (sl == NULL) { goto on_malloc_error; } + slu = calloc(1, sizeof(struct stlink_libusb)); if (slu == NULL) { goto on_malloc_error; } ugly_init(verbose); @@ -1345,18 +1338,20 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, enum connect_type connect, int mode = stlink_current_mode(sl); if (mode == STLINK_DEV_DFU_MODE) { - // this seems to work, and is unnecessary information for the user. - // demoted to debug -- REW DLOG("-- exit_dfu_mode\n"); - stlink_exit_dfu_mode(sl); - } else if (mode == STLINK_DEV_DEBUG_MODE && - connect == CONNECT_UNDER_RESET) { + _stlink_usb_exit_dfu_mode(sl); + } + + if (connect == CONNECT_UNDER_RESET) { // for the connect under reset only // OpenOСD says (official documentation is not available) that // the NRST pin must be pull down before selecting the SWD/JTAG mode - WLOG("-- exit_debug_mode\n"); - stlink_exit_debug_mode(sl); - _stlink_usb_jtag_reset(sl, STLINK_JTAG_DRIVE_NRST_LOW); + if (mode == STLINK_DEV_DEBUG_MODE) { + DLOG("-- exit_debug_mode\n"); + _stlink_usb_exit_dfu_mode(sl); + } + + _stlink_usb_jtag_reset(sl, STLINK_DEBUG_APIV2_DRIVE_NRST_LOW); } sl->freq = freq; @@ -1364,7 +1359,7 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, enum connect_type connect, // should be done at this speed too // set the stlink clock speed (default is 1800kHz) DLOG("JTAG/SWD freq set to %d\n", freq); - stlink_set_swdclk(sl, freq); + _stlink_usb_set_swdclk(sl, freq); stlink_target_connect(sl, connect); return(sl); @@ -1374,13 +1369,10 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, enum connect_type connect, return(NULL); on_error: - if (slu->libusb_ctx) { libusb_exit(slu->libusb_ctx); } on_malloc_error: - if (sl != NULL) { free(sl); } - if (slu != NULL) { free(slu); } return(NULL); From ebba0f35e2ca971b929d8bd19484ec30cc54eabe Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 16 May 2021 18:26:52 +0200 Subject: [PATCH 263/503] General Project Update - [doc] Updated steps for release procedure - [doc] Removed outdated lists of supported devices - [doc] Updated list of supported OS - [doc] Updated version requirements - Cleanup for libusb installation routine on Windows - Updated list of contributors - Updated CHANGELOG.md - Updated README.md --- CHANGELOG.md | 7 ++ CMakeLists.txt | 2 +- README.md | 4 +- cmake/modules/Findlibusb.cmake | 22 ------ contributors.txt | 3 +- doc/devices_boards.md | 64 +----------------- doc/release.md | 8 ++- doc/version_support.md | 119 +++++++++++++++++++-------------- 8 files changed, 86 insertions(+), 143 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index 1b003d97e..b43d58da7 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -4,8 +4,15 @@ Release date: 2021-xx-xx +This release drops support for some older operating systems. Check project README for details. +Updated system requirements: Raised minimum version for `cmake` to 3.7.2. + Features: +- Support for writing option bytes on STM32F0/F1/F3 ([#346](https://github.com/stlink-org/stlink/pull/346), [#458](https://github.com/stlink-org/stlink/pull/458), [#808](https://github.com/stlink-org/stlink/pull/808), [#1084](https://github.com/stlink-org/stlink/pull/1084), [#1112](https://github.com/stlink-org/stlink/pull/1112)) +- Added chip-IDs for STM32G0B0/G0B1/G0C1/G050/G051/G061 ([#1140](https://github.com/stlink-org/stlink/pull/1140)) +- Added option byte info for STM32F411XX ([#1141](https://github.com/stlink-org/stlink/pull/1141)) + Updates & changes: - Added instructions for bug-reports and feature-requests to contribution guidelines ([#906](https://github.com/stlink-org/stlink/pull/906)) diff --git a/CMakeLists.txt b/CMakeLists.txt index 064aa06d5..4bd76ebfb 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -2,7 +2,7 @@ # General cmake settings ### -cmake_minimum_required(VERSION 3.4.2) +cmake_minimum_required(VERSION 3.7.2) cmake_policy(SET CMP0042 NEW) set(CMAKE_MODULE_PATH ${CMAKE_SOURCE_DIR}/cmake/modules) set(CMAKE_ARCHIVE_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}/lib) diff --git a/README.md b/README.md index acc2441f8..0b124d21d 100644 --- a/README.md +++ b/README.md @@ -53,9 +53,9 @@ The STlink toolset includes: ## Supported operating systems and hardware combinations -Currently known working combinations of programmers and targets are listed in [devices_boards.md](doc/devices_boards.md). +Currently known working MCU targets are listed in [devices_boards.md](doc/devices_boards.md). -Supported operating systems are listed in [version_support.md](doc/version_support.md). +A list of supported operating can be found in [version_support.md](doc/version_support.md). ## Tutorial & HOWTO diff --git a/cmake/modules/Findlibusb.cmake b/cmake/modules/Findlibusb.cmake index 257c682ce..d861bdd5f 100644 --- a/cmake/modules/Findlibusb.cmake +++ b/cmake/modules/Findlibusb.cmake @@ -54,28 +54,6 @@ elseif (WIN32 OR (EXISTS "/etc/debian_version" AND MINGW)) # Windows or MinGW-to endif () if (WIN32 AND NOT EXISTS "/etc/debian_version") # Skip this for Debian... - FIND_PATH( - LIBUSB_INCLUDE_DIR NAMES libusb.h - HINTS /usr /usr/local /opt - PATH_SUFFIXES libusb-1.0 - ) - - if (MINGW OR MSYS) - set(LIBUSB_NAME usb-1.0) - find_library( - LIBUSB_LIBRARY NAMES ${LIBUSB_NAME} - HINTS ${LIBUSB_WIN_OUTPUT_FOLDER}/MinGW${ARCH}/static - ) - else (MSVC) - set(LIBUSB_NAME libusb-1.0.lib) - find_library( - LIBUSB_LIBRARY NAMES ${LIBUSB_NAME} - HINTS ${LIBUSB_WIN_OUTPUT_FOLDER}/MS${ARCH}/dll - ) - endif () - endif () - - if (NOT LIBUSB_FOUND) # Preparations for installing libusb library set(LIBUSB_WIN_VERSION 1.0.23) # set libusb version set(LIBUSB_WIN_ARCHIVE libusb-${LIBUSB_WIN_VERSION}.7z) diff --git a/contributors.txt b/contributors.txt index 88f1f0c89..e7fc0f601 100644 --- a/contributors.txt +++ b/contributors.txt @@ -40,7 +40,7 @@ Fabien Chouteau [Fabien-Chouteau] Florian Hars Friedrich Beckmann Gabriel Górski [Glaeqen] -Geoffrey Brown +Geoffrey Brown [geoffreymbrown] George Talusan [gtalusan] Georg von Zengen Giuseppe Barba @@ -100,6 +100,7 @@ Peter Torelli [petertorelli] Peter Zotov Petteri Aimonen Piotr Haber +[RafaelLeeImg] Rene Hopf [rene-dev] Robin Kreis Roger Wolff [rewolff] diff --git a/doc/devices_boards.md b/doc/devices_boards.md index df4b5ed29..6548bc734 100644 --- a/doc/devices_boards.md +++ b/doc/devices_boards.md @@ -1,9 +1,7 @@ -# Boards supported by the STlink toolset +# MCUs supported by the STlink toolset The following devices are supported by the stlink toolset. -All Boards are expected to work with ST-LINK/V2 programmers. - **STM32F0 / ARM Cortex M0 / Core-ID: 0x0bb11477 (STM32F0_CORE_ID)** | Chip-ID | Product-Code | @@ -20,14 +18,6 @@ All Boards are expected to work with ST-LINK/V2 programmers. | 0x448 | STM32F0**72**xx | | 0x442 | STM32F0**9**xxx | -Tested boards [incl. STLINK programmers]: - -- Nucleo-F030R8 [v2-1] -- Nucleo-F072RB [v2-1] -- Nucleo-F091RC [v2-1] -- Nucleo-32 [v2-1] -- STM32F0-Discovery [v2] -- STM320518-EVAL **STM32F1 / ARM Cortex M3 / Core-ID: 0x1ba01477 (STM32F1_CORE_ID)** @@ -50,11 +40,8 @@ Tested boards [incl. STLINK programmers]: | 0x428 | High density Value | xC xD xE | F100 | | | | | | 0x430 | XL-Density | xF xG | | F101 | | F103 | | -Tested boards [incl. STLINK programmers]: +Tested non-official ST boards [incl. STLINK programmers]: -- STM32VL-Discovery (STM32F100RBT6) with STLINK/V1 [v1], [v2] -- STM32F103-Bluepill: C8Tx & R8xx [v2] -- Nucleo-F103RB [v2-1] - HY-STM32 (STM32F103VETx) [v1, v2] - DecaWave EVB1000 (STM32F105RCTx) [v1, v2] @@ -98,15 +85,6 @@ Tested boards [incl. STLINK programmers]: | 0x446 | _N/A_ | xD xE | | F302 | F303 | | | 0x446 | _N/A_ | - | | | | F398 | -Tested boards [incl. STLINK programmers]: - -- Nucleo-F302K8 [v2-1] -- Nucleo-F303K8 [v2-1] -- Nucleo-F303RE [v2-1] -- Nucleo-F334R8 [v2-1] -- STM32F303-Discovery [v2] -- STM32F3348-Discovery [v2-1] - **STM32F3 / ARM Cortex M4F / Core-ID: 0x2ba01477 (STM32F3c_CORE_ID)** | Product-Code | Chip-ID | STLINK
Programmer | Boards | @@ -134,16 +112,6 @@ Tested boards [incl. STLINK programmers]: | 0x463 | STM32F4**13**xx | | 0x463 | STM32F4**23**xx | -Tested boards [incl. STLINK programmers]: - -- Nucleo-F401RE [v2-1] -- Nucleo-F411RE [v2-1] -- STM32F407-Discovery [v2] -- STM32F411E-Discovery with gyro, audio [v2] -- STM32F413H-Discovery [v2-1] -- STM32F429I-Discovery with LCD [v2] -- STM32F439VIT6-Discovery [v2] (reseated MCU) - **STM32F7 / ARM Cortex M7F / Core-ID: 0x5ba02477 (STM32F7_CORE_ID)** | Chip-ID | Product-Code | @@ -155,23 +123,12 @@ Tested boards [incl. STLINK programmers]: | 0x451 | STM32F7**6**xxx | | 0x451 | STM32F7**7**xxx | -Tested boards [incl. STLINK programmers]: - -- Nucleo-F722ZE [v2-1] -- Nucleo-F746ZG [v2-1] -- STM32F756NGHx evaluation board [v2-1] -- STM32F769I-Discovery [v2-1] - **STM32H7 / ARM Cortex M7F / Core-ID: 0x6ba02477 (STM32H7_CORE_ID)** | Chip-ID | Product-Code | | ------- | -------------- | | 0x450 | STM32H74x/H75x | -Tested boards [incl. STLINK programmers]: - -- Nucleo-H745I-Q [v3] - **STM32G0 / ARM Cortex M0+ / Core-ID: 0x0bc11477 (STM32G0_CORE_ID)** | Chip-ID | Product-Code | @@ -203,10 +160,6 @@ Tested boards [incl. STLINK programmers]: | 0x447 | STM32L0**7**xxx | | 0x447 | STM32L0**8**xxx | -Tested boards [incl. STLINK programmers]: - -- Nucleo-L053R8 [v2-1] - **STM32L1 / ARM Cortex M3 / Core-ID: 0x2ba01477 (STM32L1_CORE_ID)** | Chip-ID | Product-Code | @@ -221,11 +174,6 @@ Tested boards [incl. STLINK programmers]: | 0x436 | STM32L1xxx**D** | | 0x437 | STM32L1xxx**E** | -Tested boards [incl. STLINK programmers]: - -- Nucleo-L152RE [v2-1] -- STM32L152C-Discovery [v2] - **STM32L4 / ARM Cortex M4F / Core-ID: 0x2ba01477 (STM32L4_CORE_ID)** | Chip-ID | Product-Code | @@ -245,14 +193,6 @@ Tested boards [incl. STLINK programmers]: | 0x471 | STM32L4**P5**xx | | 0x471 | STM32L4**Q5**xx | -Tested boards [incl. STLINK programmers]: - -- Nucleo-L432KC [v2-1] -- Nucleo-L452RE [v2-1] -- Nucleo-L476RG [v2-1] -- Nucleo-L496ZG [v2-1] -- STM32L4R9I-Discovery [v2-1] - **STM32W / ARM Cortex M3 / Core-ID: 0x2ba01477 (STM32W_CORE_ID)** | Chip-ID | Product-Code | diff --git a/doc/release.md b/doc/release.md index a67fcd743..6321e8ab2 100644 --- a/doc/release.md +++ b/doc/release.md @@ -6,6 +6,8 @@ This document describes the necessary steps for developers to create a release: 1. Update `CHANGELOG.md`, `cmake/packaging/deb/changelog` & `cmake/packaging/rpm/changelog` 2. Update `.version` with semantic version: `x.x.x` 3. Update `README.md` with semantic version `x.x.x` in commits badge -4. Create and push git tag and commits `git tag x.x.x` -5. Create binary packages (.rpm / .deb / .zip) with `make package && sh ./cmake/packaging/windows/generate_binaries.sh` -6. Upload packages to the [release page](https://github.com/stlink-org/stlink/releases) of this project +4. Merge `develop` into `master` +5. Create and push git tag and commits `git tag x.x.x` +6. Create binary packages (.rpm / .deb / .zip) with `make package && sh ./cmake/packaging/windows/generate_binaries.sh` +7. Upload packages to the [release page](https://github.com/stlink-org/stlink/releases) of this project +8. Merge `master` into `develop` diff --git a/doc/version_support.md b/doc/version_support.md index 5d2cdd375..6aafc8112 100644 --- a/doc/version_support.md +++ b/doc/version_support.md @@ -1,13 +1,11 @@ -_Source:_ pkgs.org - [libusb](https://pkgs.org/search/?q=libusb); [cmake](https://pkgs.org/search/?q=cmake); [gtk](https://pkgs.org/search/?q=gtk) (as of Apr 2020) +_Source:_ pkgs.org - [libusb](https://pkgs.org/search/?q=libusb); [cmake](https://pkgs.org/search/?q=cmake); [gtk](https://pkgs.org/search/?q=gtk) (as of May 2021) ## Supported Operating Systems ### Microsoft Windows -On Windows users should ensure that cmake 3.17.0 is installed.
-Up on compiling c-make will check **automatically**, whether `libusb` 1.0.20 or later is present.
-If this is not the case, the installation routine will download the latest version (1.0.23 at the time of writing).
-Thus no user interaction regarding libusb is necessary. +On Windows users should ensure that cmake 3.17.0 or any later version is installed.
+Up on compiling c-make will **automatically** download and install the latest compatible version of `libusb` (1.0.23 at the time of writing). - Windows 10 - Windows 8.1 @@ -23,55 +21,72 @@ NOTE: In order to use a STLINK/V1 programmer on macOS, versions 10.14 or 10.15 a ### Linux-/Unix-based: -| Operating System | libusb
version | cmake
version | gtk-3
version | Notes | -| -------------------------------- | ----------------------- | ------------------ | ----------------------------------------- | ----------------------------------------------------------------------------- | -| Alpine Edge | 1.0.23 | 3.17.0 | 3.99.0
gtk+3.0 | | -| ALT Linux Sisyphus | 1.0.23 | 3.17.0 | 3.24.18
libgtk+3 | | -| Arch Linux | 1.0.23 | 3.17.0 | 3.24.18
gtk3 | | -| Fedora Rawhide | 1.0.23 | 3.17.0 | 3.24.18
gtk3 | named `libusbx`, but
`libusb`-codebase is used | -| KaOS | 1.0.23 | 3.17.0 | 3.24.18
gtk3 | | -| OpenMandriva Cooker | 1.0.23 | 3.17.0 | 3.24.18
libgtk+3.0
lib64gtk+3.0 | | -| PCLinuxOS | 1.0.23
lib64usb1.0 | 3.17.0 | 3.24.18
lib64gtk+3.0 | | -| Slackware Current | 1.0.23 | 3.17.0 | 3.24.18
gtk+3 | | -| Solus | 1.0.23 | 3.16.5 | 3.24.16
libgtk-3 | | -| Debian Sid | 1.0.23 | 3.16.3 | 3.24.18
libgtk-3 | | -| OpenMandriva Lx 4.1 | 1.0.23 | 3.16.3 | 3.24.13
libgtk+3.0
lib64gtk+3.0 | | -| Ubuntu 20.04 LTS (Focal Fossa) | 1.0.23 | 3.16.3 | 3.24.17
libgtk-3 | | -| openSUSE Tumbleweed | 1.0.23 | 3.16.2 | 3.24.16
gtk3 | | -| Alpine 3.11 | 1.0.23 | 3.15.5 | 3.24.13
gtk+3.0 | | -| Ubuntu 19.10 (Eoan Ermine) | 1.0.23 | 3.13.4 | 3.24.12
libgtk-3 | | -| Mageia Cauldron | 1.0.22 | 3.17.0 | 3.24.18
libgtk+3.0
lib64gtk+3.0 | | -| NetBSD 9.0 | 1.0.22 | 3.16.1 | 3.24.12
gtk+3 | | -| NetBSD 8.1 | 1.0.22 | 3.16.1 | 3.24.12
gtk+3 | | -| NetBSD 7.2 | 1.0.22 | 3.16.1 | _N/A_ | | -| Alpine 3.10 | 1.0.22 | 3.14.5 | 3.24.8
gtk+3.0 | | -| Fedora 31 | 1.0.22 | 3.14.5 | 3.24.12
gtk3 | named `libusbx`, but
`libusb`-codebase is used | -| Mageia 7.1 | 1.0.22 | 3.14.3 | 3.24.8
libgtk+3.0
lib64gtk+3.0 | | -| Fedora 30 | 1.0.22 | 3.14.2 | 3.24.8
gtk3 | named `libusbx`, but
`libusb`-codebase is used | -| Debian 10 (Buster) | 1.0.22 | 3.13.4 | 3.24.5
libgtk-3 | | -| Alpine 3.9 | 1.0.22 | 3.13.0 | 3.24.1
gtk+3.0 | | -| CentOS 8 | 1.0.22 | 3.11.4 | 3.22.30
gtk3 | named `libusbx`, but
`libusb`-codebase is used | -| openSUSE Leap 15.2 | 1.0.21 | 3.15.5 | 3.24.14
gtk3 | | -| openSUSE Leap 15.1 | 1.0.21 | 3.10.2 | 3.22.30
gtk3 | | -| Ubuntu 18.04 LTS (Bionic Beaver) | 1.0.21 | 3.10.2 | 3.22.30
libgtk-3 | | -| Debian 9 (Stretch) | 1.0.21 | 3.7.2 | 3.22.11
libgtk-3 | | -| Slackware 14.2 | 1.0.20 | 3.5.2 | 3.18.9
gtk+3 | | -| Ubuntu 16.04 LTS (Xenial Xerus) | 1.0.20 | 3.5.1 | 3.18.9
libgtk-3 | | -| OpenMandriva Lx 3.0x | 1.0.20 | **3.4.2** | 3.18.9
libgtk+3.0
lib64gtk+3.0 | | -| FreeBSD 13 | **1.0.16 - 1.0.18** | 3.15.5 | 3.24.10
gtk3 | linux_libusb-13.0r358841
LIBUSB_API_VERSION 0x01000102
(integrated) | -| FreeBSD 12 | **1.0.16 - 1.0.18** | 3.15.5 | 3.24.10
gtk3 | linux_libusb-13.0r358841
LIBUSB_API_VERSION 0x01000102
(integrated) | -| FreeBSD 11 | **1.0.16 - 1.0.18** | 3.15.5 | 3.24.10
gtk3 | linux_libusb-13.0r358841
LIBUSB_API_VERSION 0x01000102
(integrated) | +| Operating System | libusb | cmake | gtk-3 | Notes | +| ------------------------- | ------------------ | --------- | ----------- | ----------------------------- | +| Arch Linux | 1.0.24 | 3.20.2 | 3.24.29 | | +| Fedora Rawhide [x64] | 1.0.24 (`libusbx`) | 3.20.2 | 3.24.29 | | +| KaOS [x64] | 1.0.24 | 3.20.2 | 3.24.29 | | +| Mageia Cauldron | 1.0.24 | 3.20.2 | 3.24.29 | | +| OpenMandriva Cooker | 1.0.24 | 3.20.2 | 3.24.29 | | +| OpenMandriva Rolling | 1.0.24 | 3.20.2 | 3.24.29 | | +| PCLinuxOS [x64] | 1.0.24 | 3.20.2 | 3.24.29 | | +| Slackware Current | 1.0.24 | 3.20.2 | 3.24.28 | | +| Solus [x64] | 1.0.24 | 3.20.2 | 3.24.29 | | +| openSUSE Tumbleweed [x64] | 1.0.24 | 3.20.1 | 3.24.29 | | +| ALT Linux Sisyphus | 1.0.24 | 3.19.7 | 3.24.29 | | +| Fedora 34 [x64] | 1.0.24 (`libusbx`) | 3.19.7 | 3.24.28 | | +| NetBSD 9.x | 1.0.24 | 3.19.7 | 3.24.27 | | +| NetBSD 8.x | 1.0.24 | 3.19.7 | 3.24.27 | | +| OpenMandriva Lx 4.2 | 1.0.24 | 3.19.3 | 3.24.24 | | +| Mageia 8 | 1.0.24 | 3.19.2 | 3.24.24 | | +| Alpine 3.13 | 1.0.24 | 3.18.4 | 3.24.23 | | +| Debian Sid | 1.0.24 | 3.18.4 | 3.24.24 | | +| Debian 11 (Bullseye) | 1.0.24 | 3.18.4 | 3.24.24 | | +| Ubuntu 21.04 (Hirsute) | 1.0.24 | 3.18.4 | 3.24.25 | | +| Fedora 33 [x64] | 1.0.23 (`libusbx`) | 3.18.3 | 3.24.23 | | +| CentOS 8 Stream [x64] | 1.0.23 (`libusbx`) | 3.18.2 | **3.22.30** | | +| Alpine 3.12 | 1.0.23 | 3.17.2 | 3.24.22 | | +| openSUSE Leap 15.3 [x64] | 1.0.**21** | 3.17.0 | 3.24.20 | | +| openSUSE Leap 15.2 [x64] | 1.0.**21** | 3.17.0 | 3.24.**14** | | +| Adélie 1.0 | 1.0.23 | 3.16.4 | 3.24.23 | | +| Ubuntu 20.04 LTS (Focal) | 1.0.23 | 3.16.3 | 3.24.**18** | | +| ALT Linux P9 | 1.0.**22** | 3.16.3 | 3.24.**11** | | +| Alpine 3.11 | 1.0.23 | 3.15.5 | 3.24.**13** | | +| Mageia 7.1 | 1.0.**22** | 3.14.3 | 3.24.**8** | | +| Debian 10 (Buster) | 1.0.**22** | 3.13.4 | 3.24.**5** | | +| AlmaLinux 8 | 1.0.23 (`libusbx`) | 3.11.4 | 3.24.32 | | +| CentOS 8 [x64] | 1.0.23 (`libusbx`) | 3.11.4 | **3.22.30** | | +| Ubuntu 18.04 LTS (Bionic) | 1.0.**21** | 3.10.2 | **3.22.30** | | +| Debian 9 (Stretch) | 1.0.**21** | **3.7.2** | **3.22.11** | | +| | | | | | +| FreeBSD 13.x | 1.0.**16 - 18** | 3.20.2 | 3.24.27 | LIBUSB_API_VERSION 0x01000102 | +| FreeBSD 12.x | 1.0.**16 - 18** | 3.19.6 | 3.24.27 | LIBUSB_API_VERSION 0x01000102 | +| FreeBSD 11.x | 1.0.**16 - 18** | 3.15.5 | 3.24.27 | LIBUSB_API_VERSION 0x01000102 | -## Unsupported Operating Systems (as of Release v1.6.1) +## Unsupported Operating Systems (as of Release v1.7.1) -| Operating System | libusb
version | cmake
version | End of
OS-Support | Notes | -| ------------------------------ | ------------------- | ------------------ | ---------------------- | --------------------------------------------------- | -| CentOS 7 | 1.0.21 | **2.8.12.2** | | named `libusbx`, but
`libusb`-codebase is used | -| Debian 8 (Jessie) | 1.0.19 | **3.0.2** | Jun 2020 | -| Ubuntu 14.04 LTS (Trusty Tahr) | 1.0.17 | **2.8.12.2** | Apr 2019 | -| CentOS 6 | 1.0.**9** | **2.8.12.2** | Dec 2020 | named `libusbx`, but
`libusb`-codebase is used | -| Slackware 14.1 | 1.0.**9** | **2.8.12** | | -| Slackware 14.0 | 1.0.**9** | **2.8.8** | | +Systems with highlighted versions remain compatible with this toolset. + +| Operating System | libusb | cmake | End of
OS-Support | +| ------------------------- | ---------------------- | ---------- | ---------------------- | +| Fedora 32 [x64] | **1.0.23** (`libusbx`) | **3.17.0** | May 2021 | +| Ubuntu 20.10 (Groovy) | **1.0.23** | **3.16.3** | Jul 2021 | +| NetBSD 7.x | **1.0.22** | **3.16.1** | Jun 2020 | +| Alpine 3.10 | **1.0.22** | **3.14.5** | May 2021 | +| Fedora 31 [x64] | **1.0.22** (`libusbx`) | **3.14.5** | Nov 2020 | +| Ubuntu 19.10 (Eoan) | **1.0.23** | **3.13.4** | Jul 2020 | +| Fedora 30 | **1.0.22** (`libusbx`) | **3.14.2** | May 2020 | +| Alpine 3.9 | **1.0.22** | **3.13.0** | Jan 2021 | +| openSUSE Leap 15.1 [x64] | **1.0.21** | **3.10.2** | Feb 2021 | +| Slackware 14.2 | 1.0.20 | 3.5.2 | | +| Ubuntu 16.04 LTS (Xenial) | 1.0.20 | 3.5.1 | Apr 2021 | +| OpenMandriva Lx 3.0x | 1.0.20 | 3.4.2 | | +| Debian 8 (Jessie) | 1.0.19 | 3.0.2 | Jun 2020 | +| CentOS 7 [x64] | 1.0.21 (`libusbx`) | 2.8.12.2 | | +| Ubuntu 14.04 LTS (Trusty) | 1.0.17 | 2.8.12.2 | Apr 2019 | +| CentOS 6 | 1.0.9 (`libusbx`) | 2.8.12.2 | Dec 2020 | +| Slackware 14.1 | 1.0.9 | 2.8.12 | | +| Slackware 14.0 | 1.0.9 | 2.8.8 | | _All other operating systems which are not listed are unsupported._ From 03ad4a434d4d6496a05885ddce9568b5884a2c2d Mon Sep 17 00:00:00 2001 From: anton Date: Mon, 17 May 2021 00:20:54 +0500 Subject: [PATCH 264/503] Added checking the command execution status --- inc/stlink.h | 13 +++ src/common.c | 23 +++-- src/stlink-lib/usb.c | 211 ++++++++++++++++++++++--------------------- 3 files changed, 132 insertions(+), 115 deletions(-) diff --git a/inc/stlink.h b/inc/stlink.h index 3bc518c87..69a4799f5 100644 --- a/inc/stlink.h +++ b/inc/stlink.h @@ -83,6 +83,19 @@ enum target_state { #define STLINK_F_HAS_DPBANKSEL (1 << 8) #define STLINK_F_HAS_RW8_512BYTES (1 << 9) +/* Error code */ +#define STLINK_DEBUG_ERR_OK 0x80 +#define STLINK_DEBUG_ERR_FAULT 0x81 +#define STLINK_DEBUG_ERR_AP_WAIT 0x10 +#define STLINK_DEBUG_ERR_AP_FAULT 0x11 +#define STLINK_DEBUG_ERR_AP_ERROR 0x12 +#define STLINK_DEBUG_ERR_DP_WAIT 0x14 +#define STLINK_DEBUG_ERR_DP_FAULT 0x15 +#define STLINK_DEBUG_ERR_DP_ERROR 0x16 + +#define CMD_NO_RETRY 0 +#define CMD_USE_RETRY 3 + #define C_BUF_LEN 32 enum stlink_flash_type { diff --git a/src/common.c b/src/common.c index ee91fa487..661ee34ec 100644 --- a/src/common.c +++ b/src/common.c @@ -1443,12 +1443,10 @@ void stlink_close(stlink_t *sl) { int stlink_exit_debug_mode(stlink_t *sl) { DLOG("*** stlink_exit_debug_mode ***\n"); - if (sl->flash_type != STLINK_FLASH_TYPE_UNKNOWN) { + if (sl->flash_type != STLINK_FLASH_TYPE_UNKNOWN && + sl->core_stat != TARGET_RESET) { // stop debugging if the target has been identified - int ret = stlink_write_debug32(sl, STLINK_REG_DHCSR, STLINK_REG_DHCSR_DBGKEY); - if (ret == -1) { - return (ret); - } + stlink_write_debug32(sl, STLINK_REG_DHCSR, STLINK_REG_DHCSR_DBGKEY); } return (sl->backend->exit_debug_mode(sl)); @@ -1684,7 +1682,7 @@ int stlink_load_device_params(stlink_t *sl) { } int stlink_jtag_reset(stlink_t *sl, int value) { - DLOG("*** stlink_jtag_reset ***\n"); + DLOG("*** stlink_jtag_reset %d ***\n", value); return (sl->backend->jtag_reset(sl, value)); } @@ -1768,6 +1766,8 @@ int stlink_reset(stlink_t *sl, enum reset_type type) { DLOG("*** stlink_reset ***\n"); + sl->core_stat = TARGET_RESET; + if (type == RESET_AUTO) { // clear S_RESET_ST in DHCSR register for reset state detection stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); @@ -1781,9 +1781,7 @@ int stlink_reset(stlink_t *sl, enum reset_type type) { usleep(100); stlink_jtag_reset(sl, STLINK_DEBUG_APIV2_DRIVE_NRST_HIGH); } - if (sl->backend->reset(sl)) { - return (-1); - } + sl->backend->reset(sl); usleep(10000); } @@ -1793,8 +1791,8 @@ int stlink_reset(stlink_t *sl, enum reset_type type) { * DDI0337E, p. 10-4, Debug Halting Control and Status Register */ dhcsr = 0; - stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); - if ((dhcsr & STLINK_REG_DHCSR_S_RESET_ST) == 0) { + int res = stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); + if ((dhcsr & STLINK_REG_DHCSR_S_RESET_ST) == 0 && !res) { // reset not done yet // try reset through AIRCR so that NRST does not need to be connected @@ -1808,8 +1806,9 @@ int stlink_reset(stlink_t *sl, enum reset_type type) { while (time_ms() < timeout) { dhcsr = STLINK_REG_DHCSR_S_RESET_ST; stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); - if ((dhcsr & STLINK_REG_DHCSR_S_RESET_ST) == 0) + if ((dhcsr & STLINK_REG_DHCSR_S_RESET_ST) == 0) { return (0); + } } return (-1); diff --git a/src/stlink-lib/usb.c b/src/stlink-lib/usb.c index bbdc2c27b..5e17189c6 100644 --- a/src/stlink-lib/usb.c +++ b/src/stlink-lib/usb.c @@ -84,50 +84,80 @@ void _stlink_usb_close(stlink_t* sl) { } ssize_t send_recv(struct stlink_libusb* handle, int terminate, - unsigned char* txbuf, size_t txsize, unsigned char* rxbuf, size_t rxsize) { + unsigned char* txbuf, size_t txsize, unsigned char* rxbuf, + size_t rxsize, bool check_error, int retry_cnt) { // Note: txbuf and rxbuf can point to the same area - int res = 0; - int t; + int res, t, retry = 0; + int cmd = read_uint16(txbuf, (handle->protocoll == 1)?15:0); - t = libusb_bulk_transfer(handle->usb_handle, handle->ep_req, txbuf, (int)txsize, &res, 3000); - - if (t) { - printf("[!] send_recv send request failed: %s\n", libusb_error_name(t)); - return(-1); - } else if ((size_t)res != txsize) { - printf("[!] send_recv send request wrote %u bytes (instead of %u).\n", - (unsigned int)res, (unsigned int)txsize); - } - - if (rxsize != 0) { - t = libusb_bulk_transfer(handle->usb_handle, handle->ep_rep, rxbuf, (int)rxsize, &res, 3000); + while (1) { + res = 0; + t = libusb_bulk_transfer(handle->usb_handle, handle->ep_req, txbuf, (int)txsize, &res, 3000); if (t) { - printf("[!] send_recv read reply failed: %s\n", libusb_error_name(t)); + ELOG("[!] send_recv send request failed: %s (command 0x%02X)\n", libusb_error_name(t), cmd); return(-1); + } else if ((size_t)res != txsize) { + ELOG("[!] send_recv send request wrote %u bytes, instead of %u (command 0x%02X)\n", + (unsigned int)res, (unsigned int)txsize, cmd); } - } - if ((handle->protocoll == 1) && terminate) { - // read the SG reply - unsigned char sg_buf[13]; - t = libusb_bulk_transfer(handle->usb_handle, handle->ep_rep, sg_buf, 13, &res, 3000); + if (rxsize != 0) { + t = libusb_bulk_transfer(handle->usb_handle, handle->ep_rep, rxbuf, (int)rxsize, &res, 3000); - if (t) { - printf("[!] send_recv read storage failed: %s\n", libusb_error_name(t)); - return(-1); + if (t) { + ELOG("[!] send_recv read reply failed: %s (command 0x%02X)\n", libusb_error_name(t), cmd); + return(-1); + } + + /* Checking the command execution status stored in the first byte of the response */ + if (handle->protocoll != 1 && check_error && + rxbuf[0] != STLINK_DEBUG_ERR_OK) { + switch(rxbuf[0]) { + case STLINK_DEBUG_ERR_AP_WAIT: + case STLINK_DEBUG_ERR_DP_WAIT: + if (retry < retry_cnt) { + unsigned int delay_us = (1<sg_transfer_idx++; - } + if ((handle->protocoll == 1) && terminate) { + // read the SG reply + unsigned char sg_buf[13]; + t = libusb_bulk_transfer(handle->usb_handle, handle->ep_rep, sg_buf, 13, &res, 3000); + + if (t) { + ELOG("[!] send_recv read storage failed: %s (command 0x%02X)\n", libusb_error_name(t), cmd); + return(-1); + } + + // The STLink doesn't seem to evaluate the sequence number. + handle->sg_transfer_idx++; + } - return(res); + return(res); + } } static inline int send_only(struct stlink_libusb* handle, int terminate, unsigned char* txbuf, size_t txsize) { - return((int)send_recv(handle, terminate, txbuf, txsize, NULL, 0)); + return((int)send_recv(handle, terminate, txbuf, txsize, NULL, 0, false, CMD_NO_RETRY)); } @@ -149,7 +179,6 @@ static int fill_command(stlink_t * sl, enum SCSI_Generic_Direction dir, uint32_t cmd[i++] = 0; // logical unit cmd[i++] = 0xa; // command length } - return(i); } @@ -172,9 +201,8 @@ int _stlink_usb_version(stlink_t *sl) { cmd[i++] = STLINK_GET_VERSION; } - size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, false, CMD_USE_RETRY); if (size != (ssize_t)rep_len) { - printf("[!] send_recv STLINK_GET_VERSION\n"); return((int)size); } @@ -193,10 +221,9 @@ int32_t _stlink_usb_target_voltage(stlink_t *sl) { cmd[i++] = STLINK_GET_TARGET_VOLTAGE; - size = send_recv(slu, 1, cmd, slu->cmd_len, rdata, rep_len); + size = send_recv(slu, 1, cmd, slu->cmd_len, rdata, rep_len, false, CMD_NO_RETRY); - if (size == -1) { - printf("[!] send_recv STLINK_GET_TARGET_VOLTAGE\n"); + if (size < 0) { return(-1); } else if (size != 8) { printf("[!] wrong length STLINK_GET_TARGET_VOLTAGE\n"); @@ -221,10 +248,9 @@ int _stlink_usb_read_debug32(stlink_t *sl, uint32_t addr, uint32_t *data) { cmd[i++] = STLINK_DEBUG_COMMAND; cmd[i++] = STLINK_DEBUG_APIV2_READDEBUGREG; write_uint32(&cmd[i], addr); - size = send_recv(slu, 1, cmd, slu->cmd_len, rdata, rep_len); + size = send_recv(slu, 1, cmd, slu->cmd_len, rdata, rep_len, true, CMD_USE_RETRY); - if (size == -1) { - printf("[!] send_recv STLINK_DEBUG_APIV2_READDEBUGREG\n"); + if (size < 0) { return((int)size); } @@ -245,10 +271,9 @@ int _stlink_usb_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data) { cmd[i++] = STLINK_DEBUG_APIV2_WRITEDEBUGREG; write_uint32(&cmd[i], addr); write_uint32(&cmd[i + 4], data); - size = send_recv(slu, 1, cmd, slu->cmd_len, rdata, rep_len); + size = send_recv(slu, 1, cmd, slu->cmd_len, rdata, rep_len, true, CMD_USE_RETRY); - if (size == -1) { - printf("[!] send_recv STLINK_DEBUG_APIV2_WRITEDEBUGREG\n"); + if (size < 0) { return((int)size); } @@ -269,10 +294,10 @@ int _stlink_usb_get_rw_status(stlink_t *sl) { if (sl->version.flags & STLINK_F_HAS_GETLASTRWSTATUS2) { cmd[i++] = STLINK_DEBUG_APIV2_GETLASTRWSTATUS2; - ret = send_recv(slu, 1, cmd, slu->cmd_len, rdata, 12); + ret = send_recv(slu, 1, cmd, slu->cmd_len, rdata, 12, true, CMD_NO_RETRY); } else { cmd[i++] = STLINK_DEBUG_APIV2_GETLASTRWSTATUS; - ret = send_recv(slu, 1, cmd, slu->cmd_len, rdata, 2); + ret = send_recv(slu, 1, cmd, slu->cmd_len, rdata, 2, true, CMD_NO_RETRY); } if (ret < 0) { return(-1); } @@ -334,10 +359,9 @@ int _stlink_usb_current_mode(stlink_t * sl) { int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); cmd[i++] = STLINK_GET_CURRENT_MODE; - size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, false, CMD_NO_RETRY); - if (size == -1) { - printf("[!] send_recv STLINK_GET_CURRENT_MODE\n"); + if (size < 0) { return(-1); } @@ -362,10 +386,9 @@ int _stlink_usb_core_id(stlink_t * sl) { offset = 4; } - size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, true, CMD_NO_RETRY); - if (size == -1) { - printf("[!] send_recv STLINK_DEBUG_READCOREID\n"); + if (size < 0) { return(-1); } @@ -408,10 +431,9 @@ int _stlink_usb_status(stlink_t * sl) { cmd[i++] = STLINK_DEBUG_COMMAND; cmd[i++] = STLINK_DEBUG_GETSTATUS; - size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, false, CMD_NO_RETRY); - if (size == -1) { - printf("[!] send_recv STLINK_DEBUG_GETSTATUS\n"); + if (size < 0) { return((int)size); } @@ -450,10 +472,9 @@ int _stlink_usb_force_debug(stlink_t *sl) { cmd[i++] = STLINK_DEBUG_COMMAND; cmd[i++] = STLINK_DEBUG_FORCEDEBUG; - size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, true, CMD_USE_RETRY); - if (size == -1) { - printf("[!] send_recv STLINK_DEBUG_FORCEDEBUG\n"); + if (size < 0) { return((int)size); } @@ -472,10 +493,9 @@ int _stlink_usb_enter_swd_mode(stlink_t * sl) { // select correct API-Version for entering SWD mode: V1 API (0x20) or V2 API (0x30). cmd[i++] = sl->version.jtag_api == STLINK_JTAG_API_V1 ? STLINK_DEBUG_APIV1_ENTER : STLINK_DEBUG_APIV2_ENTER; cmd[i++] = STLINK_DEBUG_ENTER_SWD; - size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, true, CMD_USE_RETRY); - if (size == -1) { - printf("[!] send_recv STLINK_DEBUG_ENTER\n"); + if (size < 0) { return((int)size); } @@ -518,10 +538,9 @@ int _stlink_usb_reset(stlink_t * sl) { cmd[i++] = STLINK_DEBUG_APIV2_RESETSYS; } - size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, true, CMD_USE_RETRY); - if (size == -1) { - printf("[!] send_recv STLINK_DEBUG_RESETSYS\n"); + if (size < 0) { return((int)size); } @@ -539,10 +558,9 @@ int _stlink_usb_jtag_reset(stlink_t * sl, int value) { cmd[i++] = STLINK_DEBUG_COMMAND; cmd[i++] = STLINK_DEBUG_APIV2_DRIVE_NRST; cmd[i++] = value; - size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, true, CMD_USE_RETRY); - if (size == -1) { - printf("[!] send_recv STLINK_DEBUG_APIV2_DRIVE_NRST\n"); + if (size < 0) { return((int)size); } @@ -571,10 +589,9 @@ int _stlink_usb_step(stlink_t* sl) { cmd[i++] = STLINK_DEBUG_COMMAND; cmd[i++] = STLINK_DEBUG_STEPCORE; - size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, true, CMD_USE_RETRY); - if (size == -1) { - printf("[!] send_recv STLINK_DEBUG_STEPCORE\n"); + if (size < 0) { return((int)size); } @@ -607,10 +624,9 @@ int _stlink_usb_run(stlink_t* sl, enum run_type type) { cmd[i++] = STLINK_DEBUG_COMMAND; cmd[i++] = STLINK_DEBUG_RUNCORE; - size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, true, CMD_USE_RETRY); - if (size == -1) { - printf("[!] send_recv STLINK_DEBUG_RUNCORE\n"); + if (size < 0) { return((int)size); } @@ -655,10 +671,9 @@ int _stlink_usb_set_swdclk(stlink_t* sl, int clk_freq) { cmd[i++] = STLINK_DEBUG_APIV2_SWD_SET_FREQ; cmd[i++] = clk_divisor & 0xFF; cmd[i++] = (clk_divisor >> 8) & 0xFF; - size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, true, CMD_USE_RETRY); - if (size == -1) { - printf("[!] send_recv STLINK_DEBUG_APIV2_SWD_SET_FREQ\n"); + if (size < 0) { return((int)size); } @@ -671,10 +686,9 @@ int _stlink_usb_set_swdclk(stlink_t* sl, int clk_freq) { cmd[i++] = STLINK_DEBUG_COMMAND; cmd[i++] = STLINK_DEBUG_APIV3_GET_COM_FREQ; cmd[i++] = 0; // SWD mode - size = send_recv(slu, 1, cmd, slu->cmd_len, data, 52); + size = send_recv(slu, 1, cmd, slu->cmd_len, data, 52, true, CMD_NO_RETRY); - if (size == -1) { - printf("[!] send_recv STLINK_APIV3_GET_COM_FREQ\n"); + if (size < 0) { return((int)size); } @@ -702,10 +716,9 @@ int _stlink_usb_set_swdclk(stlink_t* sl, int clk_freq) { cmd[i++] = (uint8_t)((map[speed_index] >> 16) & 0xFF); cmd[i++] = (uint8_t)((map[speed_index] >> 24) & 0xFF); - size = send_recv(slu, 1, cmd, slu->cmd_len, data, 8); + size = send_recv(slu, 1, cmd, slu->cmd_len, data, 8, true, CMD_NO_RETRY); - if (size == -1) { - printf("[!] send_recv STLINK_APIV3_SET_COM_FREQ\n"); + if (size < 0) { return((int)size); } @@ -747,10 +760,9 @@ int _stlink_usb_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { cmd[i++] = STLINK_DEBUG_READMEM_32BIT; write_uint32(&cmd[i], addr); write_uint16(&cmd[i + 4], len); - size = send_recv(slu, 1, cmd, slu->cmd_len, data, len); + size = send_recv(slu, 1, cmd, slu->cmd_len, data, len, false, CMD_NO_RETRY); - if (size == -1) { - printf("[!] send_recv STLINK_DEBUG_READMEM_32BIT\n"); + if (size < 0) { return((int)size); } @@ -776,10 +788,9 @@ int _stlink_usb_read_all_regs(stlink_t *sl, struct stlink_reg *regp) { cmd[i++] = STLINK_DEBUG_APIV2_READALLREGS; } - size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, true, CMD_NO_RETRY); - if (size == -1) { - printf("[!] send_recv STLINK_DEBUG_READALLREGS\n"); + if (size < 0) { return((int)size); } @@ -827,10 +838,9 @@ int _stlink_usb_read_reg(stlink_t *sl, int r_idx, struct stlink_reg *regp) { } cmd[i++] = (uint8_t)r_idx; - size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, true, CMD_USE_RETRY); - if (size == -1) { - printf("[!] send_recv STLINK_DEBUG_READREG\n"); + if (size < 0) { return((int)size); } @@ -994,10 +1004,9 @@ int _stlink_usb_write_reg(stlink_t *sl, uint32_t reg, int idx) { cmd[i++] = idx; write_uint32(&cmd[i], reg); - size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, true, CMD_USE_RETRY); - if (size == -1) { - printf("[!] send_recv STLINK_DEBUG_WRITEREG\n"); + if (size < 0) { return((int)size); } @@ -1020,10 +1029,9 @@ int _stlink_usb_enable_trace(stlink_t* sl, uint32_t frequency) { write_uint16(&cmd[i + 0], 2 * STLINK_TRACE_BUF_LEN); write_uint32(&cmd[i + 2], frequency); - size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, true, CMD_NO_RETRY); - if (size == -1) { - printf("[!] send_only STLINK_DEBUG_APIV2_START_TRACE_RX\n"); + if (size < 0) { return((int)size); } @@ -1044,10 +1052,9 @@ int _stlink_usb_disable_trace(stlink_t* sl) { cmd[i++] = STLINK_DEBUG_COMMAND; cmd[i++] = STLINK_DEBUG_APIV2_STOP_TRACE_RX; - size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, true, CMD_NO_RETRY); - if (size == -1) { - printf("[!] send_only STLINK_DEBUG_APIV2_STOP_TRACE_RX\n"); + if (size < 0) { return((int)size); } @@ -1066,14 +1073,12 @@ int _stlink_usb_read_trace(stlink_t* sl, uint8_t* buf, size_t size) { cmd[i++] = STLINK_DEBUG_COMMAND; cmd[i++] = STLINK_DEBUG_APIV2_GET_TRACE_NB; - ssize_t send_size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); + ssize_t send_size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, false, CMD_NO_RETRY); - if (send_size == -1) { - printf("[!] send_recv STLINK_DEBUG_APIV2_GET_TRACE_NB\n"); + if (send_size < 0) { return((int)send_size); - } - if (send_size != 2) { - printf("[!] send_recv STLINK_DEBUG_APIV2_GET_TRACE_NB %d\n", (int)send_size); + } else if (send_size != 2) { + ELOG("STLINK_DEBUG_APIV2_GET_TRACE_NB reply size %d\n", (int)send_size); return -1; } From 620b52995667e5c39e8260e579e76b8d6d1a4fc5 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 16 May 2021 22:27:14 +0200 Subject: [PATCH 265/503] Aligned naming scheme for chip-ID files --- config/chips/F04x.chip | 4 +- config/chips/F07x.chip | 4 +- config/chips/{F09X.chip => F09x.chip} | 6 +- config/chips/F0xx small.chip | 4 +- config/chips/F0xx.chip | 4 +- ...1xx XL-density.chip => F1 XL-density.chip} | 6 +- ...ty line.chip => F1 connectivity line.chip} | 6 +- ...High-density.chip => F1 high-density.chip} | 6 +- ...ensity device.chip => F1 low-density.chip} | 6 +- ...um-density.chip => F1 medium-density.chip} | 6 +- ...e.chip => F1 value line high-density.chip} | 6 +- ...1xx Value Line.chip => F1 value line.chip} | 6 +- config/chips/{F2xx.chip => F2.chip} | 6 +- config/chips/F303 high density.chip | 4 +- config/chips/F334 medium density.chip | 4 +- config/chips/{F3xx.chip => F37x.chip} | 6 +- config/chips/F3xx small.chip | 4 +- config/chips/F410.chip | 4 +- .../chips/{stm32f411re.chip => F411xx.chip} | 6 +- config/chips/F412.chip | 4 +- config/chips/F413.chip | 4 +- config/chips/F42x_F43x.chip | 4 +- config/chips/F446.chip | 4 +- config/chips/F46x_F47x.chip | 4 +- ...ncy).chip => F4xx dynamic efficiency.chip} | 6 +- ...x (low power).chip => F4xx low power.chip} | 6 +- config/chips/F4xx.chip | 4 +- config/chips/F72x_F73x.chip | 4 +- config/chips/F76xxx.chip | 4 +- config/chips/F7xx.chip | 4 +- config/chips/G030_G031_G041.chip | 4 +- config/chips/G070_G071_G081.chip | 4 +- .../{G4 Category-2.chip => G4 cat2.chip} | 6 +- .../{G4 Category-3.chip => G4 cat3.chip} | 6 +- config/chips/H72x_H73x.chip | 4 +- config/chips/H74x_H75x.chip | 4 +- config/chips/H7Ax_H7Bx.chip | 4 +- config/chips/L011.chip | 4 +- config/chips/L0x3.chip | 4 +- .../{L0xx Category 2.chip => L0xx cat2.chip} | 6 +- .../{L0xx Category 5.chip => L0xx cat5.chip} | 6 +- config/chips/L152RE.chip | 4 +- .../chips/{L1xx Cat.2.chip => L1xx cat2.chip} | 6 +- ...gh-density.chip => L1xx high-density.chip} | 6 +- ...-density.chip => L1xx medium-density.chip} | 6 +- ...ity.chip => L1xx medium-plus-density.chip} | 6 +- config/chips/L41x.chip | 4 +- config/chips/L43x_L44x.chip | 4 +- .../chips/{L45x_46x.chip => L45x_L46x.chip} | 6 +- config/chips/L496x_L4A6x.chip | 4 +- config/chips/L4Rx.chip | 4 +- config/chips/L4xx.chip | 4 +- config/chips/WB55.chip | 4 +- config/chips/unknown device.chip | 4 +- config/udev/rules.d/49-stlinkv1.rules | 2 +- config/udev/rules.d/49-stlinkv2-1.rules | 2 +- config/udev/rules.d/49-stlinkv2.rules | 2 +- doc/tutorial.md | 26 +-- src/common.c | 56 +++--- src/st-util/gdb-server.c | 10 +- src/stlink-lib/chipid.c | 177 +++++++++--------- src/stlink-lib/chipid.h | 66 ++++--- src/stlink-lib/flash_loader.c | 42 ++--- 63 files changed, 319 insertions(+), 324 deletions(-) rename config/chips/{F09X.chip => F09x.chip} (69%) rename config/chips/{F1xx XL-density.chip => F1 XL-density.chip} (62%) rename config/chips/{F1 Connectivity line.chip => F1 connectivity line.chip} (59%) rename config/chips/{F1xx High-density.chip => F1 high-density.chip} (60%) rename config/chips/{F1 Low-density device.chip => F1 low-density.chip} (58%) rename config/chips/{F1xx Medium-density.chip => F1 medium-density.chip} (59%) rename config/chips/{F1xx High-density value line.chip => F1 value line high-density.chip} (54%) rename config/chips/{F1xx Value Line.chip => F1 value line.chip} (62%) rename config/chips/{F2xx.chip => F2.chip} (71%) rename config/chips/{F3xx.chip => F37x.chip} (69%) rename config/chips/{stm32f411re.chip => F411xx.chip} (65%) rename config/chips/{F4xx (Dynamic Efficency).chip => F4xx dynamic efficiency.chip} (57%) rename config/chips/{F4xx (low power).chip => F4xx low power.chip} (61%) rename config/chips/{G4 Category-2.chip => G4 cat2.chip} (64%) rename config/chips/{G4 Category-3.chip => G4 cat3.chip} (64%) rename config/chips/{L0xx Category 2.chip => L0xx cat2.chip} (63%) rename config/chips/{L0xx Category 5.chip => L0xx cat5.chip} (63%) rename config/chips/{L1xx Cat.2.chip => L1xx cat2.chip} (65%) rename config/chips/{L1xx High-density.chip => L1xx high-density.chip} (62%) rename config/chips/{L1xx Medium-density.chip => L1xx medium-density.chip} (59%) rename config/chips/{L1xx Medium-Plus-density.chip => L1xx medium-plus-density.chip} (57%) rename config/chips/{L45x_46x.chip => L45x_L46x.chip} (66%) diff --git a/config/chips/F04x.chip b/config/chips/F04x.chip index 72db26f8c..059ae5bc6 100644 --- a/config/chips/F04x.chip +++ b/config/chips/F04x.chip @@ -1,8 +1,8 @@ -# Chipid file for F04x +# Chip-ID file for F04x # chip_id 445 description F04x -flash_type 1 +flash_type 1 flash_pagesize 400 sram_size 1800 bootrom_base 1fffec00 diff --git a/config/chips/F07x.chip b/config/chips/F07x.chip index cfedfa76f..ba839baed 100644 --- a/config/chips/F07x.chip +++ b/config/chips/F07x.chip @@ -1,8 +1,8 @@ -# Chipid file for F07x +# Chip-ID file for F07x # chip_id 448 description F07x -flash_type 1 +flash_type 1 flash_pagesize 800 sram_size 4000 bootrom_base 1fffc800 diff --git a/config/chips/F09X.chip b/config/chips/F09x.chip similarity index 69% rename from config/chips/F09X.chip rename to config/chips/F09x.chip index a622cf2f5..727fc1fa4 100644 --- a/config/chips/F09X.chip +++ b/config/chips/F09x.chip @@ -1,8 +1,8 @@ -# Chipid file for F09X +# Chip-ID file for F09x # chip_id 442 -description F09X -flash_type 1 +description F09x +flash_type 1 flash_pagesize 800 sram_size 8000 bootrom_base 1fffd800 diff --git a/config/chips/F0xx small.chip b/config/chips/F0xx small.chip index 65aea58ac..efa51c284 100644 --- a/config/chips/F0xx small.chip +++ b/config/chips/F0xx small.chip @@ -1,8 +1,8 @@ -# Chipid file for F0xx small +# Chip-ID file for F0xx small # chip_id 444 description F0xx small -flash_type 1 +flash_type 1 flash_pagesize 400 sram_size 1000 bootrom_base 1fffec00 diff --git a/config/chips/F0xx.chip b/config/chips/F0xx.chip index 5a5529412..9c0f60bd9 100644 --- a/config/chips/F0xx.chip +++ b/config/chips/F0xx.chip @@ -1,8 +1,8 @@ -# Chipid file for F0xx +# Chip-ID file for F0xx # chip_id 440 description F0xx -flash_type 1 +flash_type 1 flash_pagesize 400 sram_size 2000 bootrom_base 1fffec00 diff --git a/config/chips/F1xx XL-density.chip b/config/chips/F1 XL-density.chip similarity index 62% rename from config/chips/F1xx XL-density.chip rename to config/chips/F1 XL-density.chip index a7125a429..70cdfd3bb 100644 --- a/config/chips/F1xx XL-density.chip +++ b/config/chips/F1 XL-density.chip @@ -1,8 +1,8 @@ -# Chipid file for F1xx XL-density +# Chip-ID file for F1 XL-density # chip_id 430 -description F1xx XL-density -flash_type 2 +description F1 XL-density +flash_type 2 flash_pagesize 800 sram_size 18000 bootrom_base 1fffe000 diff --git a/config/chips/F1 Connectivity line.chip b/config/chips/F1 connectivity line.chip similarity index 59% rename from config/chips/F1 Connectivity line.chip rename to config/chips/F1 connectivity line.chip index 676fd1945..14678112d 100644 --- a/config/chips/F1 Connectivity line.chip +++ b/config/chips/F1 connectivity line.chip @@ -1,8 +1,8 @@ -# Chipid file for F1 Connectivity line +# Chip-ID file for F1 connectivity line # chip_id 418 -description F1 Connectivity line -flash_type 1 +description F1 connectivity line +flash_type 1 flash_pagesize 800 sram_size 10000 bootrom_base 1fffb000 diff --git a/config/chips/F1xx High-density.chip b/config/chips/F1 high-density.chip similarity index 60% rename from config/chips/F1xx High-density.chip rename to config/chips/F1 high-density.chip index ed02e691a..3d4cff724 100644 --- a/config/chips/F1xx High-density.chip +++ b/config/chips/F1 high-density.chip @@ -1,8 +1,8 @@ -# Chipid file for F1xx High-density +# Chip-ID file for F1 high-density # chip_id 414 -description F1xx High-density -flash_type 1 +description F1 high-density +flash_type 1 flash_pagesize 800 sram_size 10000 bootrom_base 1ffff000 diff --git a/config/chips/F1 Low-density device.chip b/config/chips/F1 low-density.chip similarity index 58% rename from config/chips/F1 Low-density device.chip rename to config/chips/F1 low-density.chip index dcb5e279e..9905ce405 100644 --- a/config/chips/F1 Low-density device.chip +++ b/config/chips/F1 low-density.chip @@ -1,8 +1,8 @@ -# Chipid file for F1 Low-density device +# Chip-ID file for F1 low-density # chip_id 412 -description F1 Low-density device -flash_type 1 +description F1 low-density +flash_type 1 flash_pagesize 400 sram_size 2800 bootrom_base 1ffff000 diff --git a/config/chips/F1xx Medium-density.chip b/config/chips/F1 medium-density.chip similarity index 59% rename from config/chips/F1xx Medium-density.chip rename to config/chips/F1 medium-density.chip index 32266b74e..00af4f18d 100644 --- a/config/chips/F1xx Medium-density.chip +++ b/config/chips/F1 medium-density.chip @@ -1,8 +1,8 @@ -# Chipid file for F1xx Medium-density +# Chip-ID file for F1 medium-density # chip_id 410 -description F1xx Medium-density -flash_type 1 +description F1 medium-density +flash_type 1 flash_pagesize 400 sram_size 5000 bootrom_base 1ffff000 diff --git a/config/chips/F1xx High-density value line.chip b/config/chips/F1 value line high-density.chip similarity index 54% rename from config/chips/F1xx High-density value line.chip rename to config/chips/F1 value line high-density.chip index f30014122..c076e284c 100644 --- a/config/chips/F1xx High-density value line.chip +++ b/config/chips/F1 value line high-density.chip @@ -1,8 +1,8 @@ -# Chipid file for F1xx High-density value line +# Chip-ID file for F1 value line high-density # chip_id 428 -description F1xx High-density value line -flash_type 1 +description F1 value line high-density +flash_type 1 flash_pagesize 800 sram_size 8000 bootrom_base 1ffff000 diff --git a/config/chips/F1xx Value Line.chip b/config/chips/F1 value line.chip similarity index 62% rename from config/chips/F1xx Value Line.chip rename to config/chips/F1 value line.chip index 929b95496..8356357b0 100644 --- a/config/chips/F1xx Value Line.chip +++ b/config/chips/F1 value line.chip @@ -1,8 +1,8 @@ -# Chipid file for F1xx Value Line +# Chip-ID file for F1 value line # chip_id 420 -description F1xx Value Line -flash_type 1 +description F1 value line +flash_type 1 flash_pagesize 400 sram_size 2000 bootrom_base 1ffff000 diff --git a/config/chips/F2xx.chip b/config/chips/F2.chip similarity index 71% rename from config/chips/F2xx.chip rename to config/chips/F2.chip index b31be46f3..8830363d2 100644 --- a/config/chips/F2xx.chip +++ b/config/chips/F2.chip @@ -1,8 +1,8 @@ -# Chipid file for F2xx +# Chip-ID file for F2 # chip_id 411 -description F2xx -flash_type 3 +description F2 +flash_type 3 flash_pagesize 20000 sram_size 20000 bootrom_base 1fff0000 diff --git a/config/chips/F303 high density.chip b/config/chips/F303 high density.chip index 716c37c1e..e8b57ee24 100644 --- a/config/chips/F303 high density.chip +++ b/config/chips/F303 high density.chip @@ -1,8 +1,8 @@ -# Chipid file for F303 high density +# Chip-ID file for F303 high density # chip_id 446 description F303 high density -flash_type 1 +flash_type 1 flash_pagesize 800 sram_size 10000 bootrom_base 1fffd800 diff --git a/config/chips/F334 medium density.chip b/config/chips/F334 medium density.chip index 424f1063c..460e22a67 100644 --- a/config/chips/F334 medium density.chip +++ b/config/chips/F334 medium density.chip @@ -1,8 +1,8 @@ -# Chipid file for F334 medium density +# Chip-ID file for F334 medium density # chip_id 438 description F334 medium density -flash_type 1 +flash_type 1 flash_pagesize 800 sram_size 3000 bootrom_base 1fffd800 diff --git a/config/chips/F3xx.chip b/config/chips/F37x.chip similarity index 69% rename from config/chips/F3xx.chip rename to config/chips/F37x.chip index 4195f9007..424209a03 100644 --- a/config/chips/F3xx.chip +++ b/config/chips/F37x.chip @@ -1,8 +1,8 @@ -# Chipid file for F3xx +# Chip-ID file for F37x # chip_id 432 -description F3xx -flash_type 1 +description F37x +flash_type 1 flash_pagesize 800 sram_size a000 bootrom_base 1ffff000 diff --git a/config/chips/F3xx small.chip b/config/chips/F3xx small.chip index 7f6f5159c..91722905c 100644 --- a/config/chips/F3xx small.chip +++ b/config/chips/F3xx small.chip @@ -1,8 +1,8 @@ -# Chipid file for F3xx small +# Chip-ID file for F3xx small # chip_id 439 description F3xx small -flash_type 1 +flash_type 1 flash_pagesize 800 sram_size a000 bootrom_base 1fffd800 diff --git a/config/chips/F410.chip b/config/chips/F410.chip index 3fb1b3d2a..53f01c669 100644 --- a/config/chips/F410.chip +++ b/config/chips/F410.chip @@ -1,8 +1,8 @@ -# Chipid file for F410 +# Chip-ID file for F410 # chip_id 458 description F410 -flash_type 3 +flash_type 3 flash_pagesize 4000 sram_size 8000 bootrom_base 1fff0000 diff --git a/config/chips/stm32f411re.chip b/config/chips/F411xx.chip similarity index 65% rename from config/chips/stm32f411re.chip rename to config/chips/F411xx.chip index ef889c139..26390d0e6 100644 --- a/config/chips/stm32f411re.chip +++ b/config/chips/F411xx.chip @@ -1,8 +1,8 @@ -# Chipid file for stm32f411re +# Chip-ID file for F411xx # chip_id 431 -description stm32f411re -flash_type 3 +description F411xx +flash_type 3 flash_pagesize 4000 sram_size 20000 bootrom_base 1fff0000 diff --git a/config/chips/F412.chip b/config/chips/F412.chip index 138e6c273..e78b81ee1 100644 --- a/config/chips/F412.chip +++ b/config/chips/F412.chip @@ -1,8 +1,8 @@ -# Chipid file for F412 +# Chip-ID file for F412 # chip_id 441 description F412 -flash_type 3 +flash_type 3 flash_pagesize 4000 sram_size 40000 bootrom_base 1fff0000 diff --git a/config/chips/F413.chip b/config/chips/F413.chip index 305a808dc..4ea974f2c 100644 --- a/config/chips/F413.chip +++ b/config/chips/F413.chip @@ -1,8 +1,8 @@ -# Chipid file for F413 +# Chip-ID file for F413 # chip_id 463 description F413 -flash_type 3 +flash_type 3 flash_pagesize 4000 sram_size 50000 bootrom_base 1fff0000 diff --git a/config/chips/F42x_F43x.chip b/config/chips/F42x_F43x.chip index c279a0e1d..2073486cf 100644 --- a/config/chips/F42x_F43x.chip +++ b/config/chips/F42x_F43x.chip @@ -1,8 +1,8 @@ -# Chipid file for F42x/F43x +# Chip-ID file for F42x/F43x # chip_id 419 description F42x/F43x -flash_type 3 +flash_type 3 flash_pagesize 4000 sram_size 40000 bootrom_base 1fff0000 diff --git a/config/chips/F446.chip b/config/chips/F446.chip index 6f372c067..7d2ded465 100644 --- a/config/chips/F446.chip +++ b/config/chips/F446.chip @@ -1,8 +1,8 @@ -# Chipid file for F446 +# Chip-ID file for F446 # chip_id 421 description F446 -flash_type 3 +flash_type 3 flash_pagesize 20000 sram_size 20000 bootrom_base 1fff0000 diff --git a/config/chips/F46x_F47x.chip b/config/chips/F46x_F47x.chip index 6d03bbea2..75e1ea045 100644 --- a/config/chips/F46x_F47x.chip +++ b/config/chips/F46x_F47x.chip @@ -1,8 +1,8 @@ -# Chipid file for F46x/F47x +# Chip-ID file for F46x/F47x # chip_id 434 description F46x/F47x -flash_type 3 +flash_type 3 flash_pagesize 4000 sram_size 40000 bootrom_base 1fff0000 diff --git a/config/chips/F4xx (Dynamic Efficency).chip b/config/chips/F4xx dynamic efficiency.chip similarity index 57% rename from config/chips/F4xx (Dynamic Efficency).chip rename to config/chips/F4xx dynamic efficiency.chip index fda012826..33bfa23c2 100644 --- a/config/chips/F4xx (Dynamic Efficency).chip +++ b/config/chips/F4xx dynamic efficiency.chip @@ -1,8 +1,8 @@ -# Chipid file for F4xx (Dynamic Efficency) +# Chip-ID file for F4xx dynamic efficiency # chip_id 433 -description F4xx (Dynamic Efficency) -flash_type 3 +description F4xx dynamic efficiency +flash_type 3 flash_pagesize 4000 sram_size 18000 bootrom_base 1fff0000 diff --git a/config/chips/F4xx (low power).chip b/config/chips/F4xx low power.chip similarity index 61% rename from config/chips/F4xx (low power).chip rename to config/chips/F4xx low power.chip index db9e99ffa..f52595d5d 100644 --- a/config/chips/F4xx (low power).chip +++ b/config/chips/F4xx low power.chip @@ -1,8 +1,8 @@ -# Chipid file for F4xx (low power) +# Chip-ID file for F4xx low power # chip_id 423 -description F4xx (low power) -flash_type 3 +description F4xx low power +flash_type 3 flash_pagesize 4000 sram_size 10000 bootrom_base 1fff0000 diff --git a/config/chips/F4xx.chip b/config/chips/F4xx.chip index a9dd110c5..70f298b79 100644 --- a/config/chips/F4xx.chip +++ b/config/chips/F4xx.chip @@ -1,8 +1,8 @@ -# Chipid file for F4xx +# Chip-ID file for F4xx # chip_id 413 description F4xx -flash_type 3 +flash_type 3 flash_pagesize 4000 sram_size 30000 bootrom_base 1fff0000 diff --git a/config/chips/F72x_F73x.chip b/config/chips/F72x_F73x.chip index a673b04f0..ba275bb0b 100644 --- a/config/chips/F72x_F73x.chip +++ b/config/chips/F72x_F73x.chip @@ -1,8 +1,8 @@ -# Chipid file for F72x/F73x +# Chip-ID file for F72x/F73x # chip_id 452 description F72x/F73x -flash_type 3 +flash_type 3 flash_pagesize 800 sram_size 40000 bootrom_base 100000 diff --git a/config/chips/F76xxx.chip b/config/chips/F76xxx.chip index c8f9ee108..7f8cfdaf0 100644 --- a/config/chips/F76xxx.chip +++ b/config/chips/F76xxx.chip @@ -1,8 +1,8 @@ -# Chipid file for F76xxx +# Chip-ID file for F76xxx # chip_id 451 description F76xxx -flash_type 4 +flash_type 4 flash_pagesize 800 sram_size 80000 bootrom_base 200000 diff --git a/config/chips/F7xx.chip b/config/chips/F7xx.chip index c704ce2e2..c031b5f4a 100644 --- a/config/chips/F7xx.chip +++ b/config/chips/F7xx.chip @@ -1,8 +1,8 @@ -# Chipid file for F7xx +# Chip-ID file for F7xx # chip_id 449 description F7xx -flash_type 3 +flash_type 3 flash_pagesize 800 sram_size 50000 bootrom_base 100000 diff --git a/config/chips/G030_G031_G041.chip b/config/chips/G030_G031_G041.chip index c6553904e..a1c42f58f 100644 --- a/config/chips/G030_G031_G041.chip +++ b/config/chips/G030_G031_G041.chip @@ -1,8 +1,8 @@ -# Chipid file for G030/G031/G041 +# Chip-ID file for G030/G031/G041 # chip_id 466 description G030/G031/G041 -flash_type 7 +flash_type 7 flash_pagesize 800 sram_size 2000 bootrom_base 1fff0000 diff --git a/config/chips/G070_G071_G081.chip b/config/chips/G070_G071_G081.chip index ab57bbd27..58eb16b16 100644 --- a/config/chips/G070_G071_G081.chip +++ b/config/chips/G070_G071_G081.chip @@ -1,8 +1,8 @@ -# Chipid file for G070/G071/G081 +# Chip-ID file for G070/G071/G081 # chip_id 460 description G070/G071/G081 -flash_type 7 +flash_type 7 flash_pagesize 800 sram_size 9000 bootrom_base 1fff0000 diff --git a/config/chips/G4 Category-2.chip b/config/chips/G4 cat2.chip similarity index 64% rename from config/chips/G4 Category-2.chip rename to config/chips/G4 cat2.chip index 400152cd6..309cbb83f 100644 --- a/config/chips/G4 Category-2.chip +++ b/config/chips/G4 cat2.chip @@ -1,8 +1,8 @@ -# Chipid file for G4 Category-2 +# Chip-ID file for G4 cat2 # chip_id 468 -description G4 Category-2 -flash_type 8 +description G4 cat2 +flash_type 8 flash_pagesize 800 sram_size 8000 bootrom_base 1fff0000 diff --git a/config/chips/G4 Category-3.chip b/config/chips/G4 cat3.chip similarity index 64% rename from config/chips/G4 Category-3.chip rename to config/chips/G4 cat3.chip index f8ea053f7..357522b31 100644 --- a/config/chips/G4 Category-3.chip +++ b/config/chips/G4 cat3.chip @@ -1,8 +1,8 @@ -# Chipid file for G4 Category-3 +# Chip-ID file for G4 cat3 # chip_id 469 -description G4 Category-3 -flash_type 8 +description G4 cat3 +flash_type 8 flash_pagesize 800 sram_size 18000 bootrom_base 1fff0000 diff --git a/config/chips/H72x_H73x.chip b/config/chips/H72x_H73x.chip index e63c855c8..43c8ae67b 100644 --- a/config/chips/H72x_H73x.chip +++ b/config/chips/H72x_H73x.chip @@ -1,8 +1,8 @@ -# Chipid file for H72x/H73x +# Chip-ID file for H72x/H73x # chip_id 483 description H72x/H73x -flash_type a +flash_type a flash_pagesize 20000 sram_size 20000 bootrom_base 1ff00000 diff --git a/config/chips/H74x_H75x.chip b/config/chips/H74x_H75x.chip index 24e85ff66..c4d374e60 100644 --- a/config/chips/H74x_H75x.chip +++ b/config/chips/H74x_H75x.chip @@ -1,8 +1,8 @@ -# Chipid file for H74x/H75x +# Chip-ID file for H74x/H75x # chip_id 450 description H74x/H75x -flash_type a +flash_type a flash_pagesize 20000 sram_size 20000 bootrom_base 1ff00000 diff --git a/config/chips/H7Ax_H7Bx.chip b/config/chips/H7Ax_H7Bx.chip index bffd23603..b17631385 100644 --- a/config/chips/H7Ax_H7Bx.chip +++ b/config/chips/H7Ax_H7Bx.chip @@ -1,8 +1,8 @@ -# Chipid file for H7Ax/H7Bx +# Chip-ID file for H7Ax/H7Bx # chip_id 480 description H7Ax/H7Bx -flash_type a +flash_type a flash_pagesize 2000 sram_size 20000 bootrom_base 1ff00000 diff --git a/config/chips/L011.chip b/config/chips/L011.chip index 02223ddcf..6d8298848 100644 --- a/config/chips/L011.chip +++ b/config/chips/L011.chip @@ -1,8 +1,8 @@ -# Chipid file for L011 +# Chip-ID file for L011 # chip_id 457 description L011 -flash_type 5 +flash_type 5 flash_pagesize 80 sram_size 2000 bootrom_base 1ff00000 diff --git a/config/chips/L0x3.chip b/config/chips/L0x3.chip index 60d75e863..4bfc318c0 100644 --- a/config/chips/L0x3.chip +++ b/config/chips/L0x3.chip @@ -1,8 +1,8 @@ -# Chipid file for L0x3 +# Chip-ID file for L0x3 # chip_id 417 description L0x3 -flash_type 5 +flash_type 5 flash_pagesize 80 sram_size 2000 bootrom_base 1ff0000 diff --git a/config/chips/L0xx Category 2.chip b/config/chips/L0xx cat2.chip similarity index 63% rename from config/chips/L0xx Category 2.chip rename to config/chips/L0xx cat2.chip index 1cb9e1307..8b24634cf 100644 --- a/config/chips/L0xx Category 2.chip +++ b/config/chips/L0xx cat2.chip @@ -1,8 +1,8 @@ -# Chipid file for L0xx Category 2 +# Chip-ID file for L0xx cat2 # chip_id 425 -description L0xx Category 2 -flash_type 5 +description L0xx cat2 +flash_type 5 flash_pagesize 80 sram_size 2000 bootrom_base 1ff0000 diff --git a/config/chips/L0xx Category 5.chip b/config/chips/L0xx cat5.chip similarity index 63% rename from config/chips/L0xx Category 5.chip rename to config/chips/L0xx cat5.chip index 35df2fb02..b52f97363 100644 --- a/config/chips/L0xx Category 5.chip +++ b/config/chips/L0xx cat5.chip @@ -1,8 +1,8 @@ -# Chipid file for L0xx Category 5 +# Chip-ID file for L0xx cat5 # chip_id 447 -description L0xx Category 5 -flash_type 5 +description L0xx cat5 +flash_type 5 flash_pagesize 80 sram_size 5000 bootrom_base 1ff0000 diff --git a/config/chips/L152RE.chip b/config/chips/L152RE.chip index ec9d24442..c073ade93 100644 --- a/config/chips/L152RE.chip +++ b/config/chips/L152RE.chip @@ -1,8 +1,8 @@ -# Chipid file for L152RE +# Chip-ID file for L152RE # chip_id 437 description L152RE -flash_type 5 +flash_type 5 flash_pagesize 100 sram_size 14000 bootrom_base 1ff00000 diff --git a/config/chips/L1xx Cat.2.chip b/config/chips/L1xx cat2.chip similarity index 65% rename from config/chips/L1xx Cat.2.chip rename to config/chips/L1xx cat2.chip index 7a3080c60..dd89c981c 100644 --- a/config/chips/L1xx Cat.2.chip +++ b/config/chips/L1xx cat2.chip @@ -1,8 +1,8 @@ -# Chipid file for L1xx Cat.2 +# Chip-ID file for L1xx cat2 # chip_id 429 -description L1xx Cat.2 -flash_type 5 +description L1xx cat2 +flash_type 5 flash_pagesize 100 sram_size 8000 bootrom_base 1ff00000 diff --git a/config/chips/L1xx High-density.chip b/config/chips/L1xx high-density.chip similarity index 62% rename from config/chips/L1xx High-density.chip rename to config/chips/L1xx high-density.chip index 4f6c85929..8e5b0cd44 100644 --- a/config/chips/L1xx High-density.chip +++ b/config/chips/L1xx high-density.chip @@ -1,8 +1,8 @@ -# Chipid file for L1xx High-density +# Chip-ID file for L1xx high-density # chip_id 436 -description L1xx High-density -flash_type 5 +description L1xx high-density +flash_type 5 flash_pagesize 100 sram_size c000 bootrom_base 1ff00000 diff --git a/config/chips/L1xx Medium-density.chip b/config/chips/L1xx medium-density.chip similarity index 59% rename from config/chips/L1xx Medium-density.chip rename to config/chips/L1xx medium-density.chip index a1817c5d6..feb53b846 100644 --- a/config/chips/L1xx Medium-density.chip +++ b/config/chips/L1xx medium-density.chip @@ -1,8 +1,8 @@ -# Chipid file for L1xx Medium-density +# Chip-ID file for L1xx medium-density # chip_id 416 -description L1xx Medium-density -flash_type 5 +description L1xx medium-density +flash_type 5 flash_pagesize 100 sram_size 4000 bootrom_base 1ff00000 diff --git a/config/chips/L1xx Medium-Plus-density.chip b/config/chips/L1xx medium-plus-density.chip similarity index 57% rename from config/chips/L1xx Medium-Plus-density.chip rename to config/chips/L1xx medium-plus-density.chip index 30ce11e92..bdce4adc2 100644 --- a/config/chips/L1xx Medium-Plus-density.chip +++ b/config/chips/L1xx medium-plus-density.chip @@ -1,8 +1,8 @@ -# Chipid file for L1xx Medium-Plus-density +# Chip-ID file for L1xx medium-plus-density # chip_id 427 -description L1xx Medium-Plus-density -flash_type 5 +description L1xx medium-plus-density +flash_type 5 flash_pagesize 100 sram_size 8000 bootrom_base 1ff00000 diff --git a/config/chips/L41x.chip b/config/chips/L41x.chip index 008c9bfa2..a05034af4 100644 --- a/config/chips/L41x.chip +++ b/config/chips/L41x.chip @@ -1,8 +1,8 @@ -# Chipid file for L41x +# Chip-ID file for L41x # chip_id 464 description L41x -flash_type 6 +flash_type 6 flash_pagesize 800 sram_size a000 bootrom_base 1fff0000 diff --git a/config/chips/L43x_L44x.chip b/config/chips/L43x_L44x.chip index 1d956c15e..4c41ac69b 100644 --- a/config/chips/L43x_L44x.chip +++ b/config/chips/L43x_L44x.chip @@ -1,8 +1,8 @@ -# Chipid file for L43x/L44x +# Chip-ID file for L43x/L44x # chip_id 435 description L43x/L44x -flash_type 6 +flash_type 6 flash_pagesize 800 sram_size c000 bootrom_base 1fff0000 diff --git a/config/chips/L45x_46x.chip b/config/chips/L45x_L46x.chip similarity index 66% rename from config/chips/L45x_46x.chip rename to config/chips/L45x_L46x.chip index 438821fcc..da1594995 100644 --- a/config/chips/L45x_46x.chip +++ b/config/chips/L45x_L46x.chip @@ -1,8 +1,8 @@ -# Chipid file for L45x/46x +# Chip-ID file for L45x/L46x # chip_id 462 -description L45x/46x -flash_type 6 +description L45x/L46x +flash_type 6 flash_pagesize 800 sram_size 20000 bootrom_base 1fff0000 diff --git a/config/chips/L496x_L4A6x.chip b/config/chips/L496x_L4A6x.chip index b607e18cc..9bfcdb366 100644 --- a/config/chips/L496x_L4A6x.chip +++ b/config/chips/L496x_L4A6x.chip @@ -1,8 +1,8 @@ -# Chipid file for L496x/L4A6x +# Chip-ID file for L496x/L4A6x # chip_id 461 description L496x/L4A6x -flash_type 6 +flash_type 6 flash_pagesize 800 sram_size 40000 bootrom_base 1fff0000 diff --git a/config/chips/L4Rx.chip b/config/chips/L4Rx.chip index e42aba017..a9b082128 100644 --- a/config/chips/L4Rx.chip +++ b/config/chips/L4Rx.chip @@ -1,8 +1,8 @@ -# Chipid file for L4Rx +# Chip-ID file for L4Rx # chip_id 470 description L4Rx -flash_type 6 +flash_type 6 flash_pagesize 1000 sram_size a0000 bootrom_base 1fff0000 diff --git a/config/chips/L4xx.chip b/config/chips/L4xx.chip index 10ec24455..b66df6b31 100644 --- a/config/chips/L4xx.chip +++ b/config/chips/L4xx.chip @@ -1,8 +1,8 @@ -# Chipid file for L4xx +# Chip-ID file for L4xx # chip_id 415 description L4xx -flash_type 6 +flash_type 6 flash_pagesize 800 sram_size 18000 bootrom_base 1fff0000 diff --git a/config/chips/WB55.chip b/config/chips/WB55.chip index bdc0d4449..4ad4d08d0 100644 --- a/config/chips/WB55.chip +++ b/config/chips/WB55.chip @@ -1,8 +1,8 @@ -# Chipid file for WB55 +# Chip-ID file for WB55 # chip_id 495 description WB55 -flash_type 9 +flash_type 9 flash_pagesize 1000 sram_size 40000 bootrom_base 1fff0000 diff --git a/config/chips/unknown device.chip b/config/chips/unknown device.chip index 63ba47a30..ea4fe5f02 100644 --- a/config/chips/unknown device.chip +++ b/config/chips/unknown device.chip @@ -1,8 +1,8 @@ -# Chipid file for unknown device +# Chip-ID file for unknown device # chip_id 0 description unknown device -flash_type 0 +flash_type 0 flash_pagesize 0 sram_size 0 bootrom_base 0 diff --git a/config/udev/rules.d/49-stlinkv1.rules b/config/udev/rules.d/49-stlinkv1.rules index d474d6a40..9b30f1f09 100644 --- a/config/udev/rules.d/49-stlinkv1.rules +++ b/config/udev/rules.d/49-stlinkv1.rules @@ -1,4 +1,4 @@ -# stm32 discovery boards, with onboard st/linkv1 +# STM32 discovery boards, with onboard st/linkv1 # ie, STM32VL SUBSYSTEMS=="usb", ATTRS{idVendor}=="0483", ATTRS{idProduct}=="3744", \ diff --git a/config/udev/rules.d/49-stlinkv2-1.rules b/config/udev/rules.d/49-stlinkv2-1.rules index b89b84012..ef51f4e88 100644 --- a/config/udev/rules.d/49-stlinkv2-1.rules +++ b/config/udev/rules.d/49-stlinkv2-1.rules @@ -1,4 +1,4 @@ -# stm32 nucleo boards, with onboard st/linkv2-1 +# STM32 nucleo boards, with onboard st/linkv2-1 # ie, STM32F0, STM32F4. # STM32VL has st/linkv1, which is quite different diff --git a/config/udev/rules.d/49-stlinkv2.rules b/config/udev/rules.d/49-stlinkv2.rules index a11215c57..b4c388464 100644 --- a/config/udev/rules.d/49-stlinkv2.rules +++ b/config/udev/rules.d/49-stlinkv2.rules @@ -1,4 +1,4 @@ -# stm32 discovery boards, with onboard st/linkv2 +# STM32 discovery boards, with onboard st/linkv2 # ie, STM32L, STM32F4. # STM32VL has st/linkv1, which is quite different diff --git a/doc/tutorial.md b/doc/tutorial.md index f8f0cbb05..7e0b3901b 100644 --- a/doc/tutorial.md +++ b/doc/tutorial.md @@ -2,18 +2,18 @@ ## Available tools and options -| Option | Tool | Description | Available
since | -| --------------------- | ---------------------------------- | ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ | -------------------- | +| Option | Tool | Description | Available
since | +| --------------------- | ---------------------------------- | --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | -------------------- | | --flash=n[k, M] | st-flash | One can specify `--flash=128k` for example, to override the default value of 64k for the STM32F103C8T6
to assume 128k of flash being present. This option accepts decimal (128k), octal 0200k, or hex 0x80k values.
Leaving the multiplier out is equally valid, e.g.: `--flash=0x20000`. The size may be followed by an optional
"k" or "M" to multiply the given value by 1k (1024) or 1M (1024 x 1024) respectively.
One can read arbitary addresses of memory out to a binary file with: `st-flash read out.bin 0x8000000 4096`.
In this example `4096 bytes` are read and subsequently written to `out.bin`.
Binary files (here: `in.bin`) are written into flash memory with: `st-flash write in.bin 0x8000000` | v1.4.0 | -| --format | st-flash | Specify file image format to read or write. Valid formats are `binary` and `ihex`. | v1.3.0 -| --freq=n[k, M] | st-info
st-flash
st-util | The frequency of the SWD/JTAG interface can be specified, to override the default 1800 kHz configuration.
This option solely accepts decimal values with the unit `Hz` being left out. Valid frequencies are:
`5k, 15k, 25k, 50k, 100k, 125k, 240k, 480k, 950k, 1200k (1.2M), 1800k (1.8M), 4000k (4M)`. | v1.6.1 | -| --opt | st-flash | Optimisation can be enabled in order to skip flashing empty (0x00 or 0xff) bytes at the end of binary file.
This may cause some garbage data left after a flash operation. This option was enabled by default in earlier releases. | v1.6.1 | -| --reset | st-flash | Trigger a reset after flashing. The default uses the hardware reset through `NRST` pin.
A software reset (via `AIRCR`; since v1.5.1) is used, if the hardware reset failed (`NRST` pin not connected). | v1.0.0 | -| --connect-under-reset | st-info
st-flash
st-util | Connect under reset. Option makes it possible to connect to the device before code execution. This is useful
when the target contains code that lets the device go to sleep, disables debug pins or other special code. | v1.6.1 | -| --hot-plug | st-info
st-flash
st-util | Connect to the target without reset. | v1.6.2 | -| --probe | st-info | Display hardware information about the connected programmer and target MCU. | v1.2.0 | -| --version | st-info
st-flash
st-util | Print version information. | v1.3.0 | -| --help | st-flash
st-util | Print list of available commands. | | +| --format | st-flash | Specify file image format to read or write. Valid formats are `binary` and `ihex`. | v1.3.0 | +| --freq=n[k, M] | st-info
st-flash
st-util | The frequency of the SWD/JTAG interface can be specified, to override the default 1800 kHz configuration.
This option solely accepts decimal values with the unit `Hz` being left out. Valid frequencies are:
`5k, 15k, 25k, 50k, 100k, 125k, 240k, 480k, 950k, 1200k (1.2M), 1800k (1.8M), 4000k (4M)`. | v1.6.1 | +| --opt | st-flash | Optimisation can be enabled in order to skip flashing empty (0x00 or 0xff) bytes at the end of binary file.
This may cause some garbage data left after a flash operation. This option was enabled by default in earlier releases. | v1.6.1 | +| --reset | st-flash | Trigger a reset after flashing. The default uses the hardware reset through `NRST` pin.
A software reset (via `AIRCR`; since v1.5.1) is used, if the hardware reset failed (`NRST` pin not connected). | v1.0.0 | +| --connect-under-reset | st-info
st-flash
st-util | Connect under reset. Option makes it possible to connect to the device before code execution. This is useful
when the target contains code that lets the device go to sleep, disables debug pins or other special code. | v1.6.1 | +| --hot-plug | st-info
st-flash
st-util | Connect to the target without reset. | v1.6.2 | +| --probe | st-info | Display hardware information about the connected programmer and target MCU. | v1.2.0 | +| --version | st-info
st-flash
st-util | Print version information. | v1.3.0 | +| --help | st-flash
st-util | Print list of available commands. | | ### Reading & Writing Option Bytes @@ -65,9 +65,9 @@ crw-rw-rw- 1 root root 189, 528 Jan 24 17:52 /dev/bus/usb/005/017 which is world writable (this is from the `MODE:="0666"` below). I have several files in my `/etc/udev/rules.d` directory. In this particular case, the `49-stlinkv2-1.rules` file contains the following: ``` -# stm32 nucleo boards, with onboard st/linkv2-1 +# STM32 nucleo boards, with onboard STLINK/V2-1 # ie, STM32F0, STM32F4. -# STM32VL has st/linkv1, which is quite different +# STM32VL has STLINK/V1, which is quite different SUBSYSTEMS=="usb", ATTRS{idVendor}=="0483", ATTRS{idProduct}=="374b", \ MODE:="0666", \ diff --git a/src/common.c b/src/common.c index 80190f756..49a048039 100644 --- a/src/common.c +++ b/src/common.c @@ -333,7 +333,7 @@ #define FLASH_H7_CR_SER 2 #define FLASH_H7_CR_BER 3 #define FLASH_H7_CR_PSIZE 4 -#define FLASH_H7_CR_START(chipid) (chipid == STLINK_CHIPID_STM32_H7AX ? 5 : 7) +#define FLASH_H7_CR_START(chipid) (chipid == STLINK_CHIPID_STM32_H7Ax ? 5 : 7) #define FLASH_H7_CR_SNB 8 #define FLASH_H7_CR_SNB_MASK 0x700 @@ -447,9 +447,9 @@ static uint32_t get_stm32l0_flash_base(stlink_t *sl) { return (STM32L0_FLASH_REGS_ADDR); case STLINK_CHIPID_STM32_L1_CAT2: - case STLINK_CHIPID_STM32_L1_MEDIUM: - case STLINK_CHIPID_STM32_L1_MEDIUM_PLUS: - case STLINK_CHIPID_STM32_L1_HIGH: + case STLINK_CHIPID_STM32_L1_MD: + case STLINK_CHIPID_STM32_L1_MD_PLUS: + case STLINK_CHIPID_STM32_L1_MD_PLUS_HD: return (STM32L1_FLASH_REGS_ADDR); default: @@ -1618,14 +1618,14 @@ int stlink_load_device_params(stlink_t *sl) { flash_size = flash_size & 0xffff; - if ((sl->chip_id == STLINK_CHIPID_STM32_L1_MEDIUM || - sl->chip_id == STLINK_CHIPID_STM32_F1_VL_MEDIUM_LOW || - sl->chip_id == STLINK_CHIPID_STM32_L1_MEDIUM_PLUS) && + if ((sl->chip_id == STLINK_CHIPID_STM32_L1_MD || + sl->chip_id == STLINK_CHIPID_STM32_F1_VL_MD_LD || + sl->chip_id == STLINK_CHIPID_STM32_L1_MD_PLUS) && (flash_size == 0)) { sl->flash_size = 128 * 1024; } else if (sl->chip_id == STLINK_CHIPID_STM32_L1_CAT2) { sl->flash_size = (flash_size & 0xff) * 1024; - } else if ((sl->chip_id & 0xFFF) == STLINK_CHIPID_STM32_L1_HIGH) { + } else if ((sl->chip_id & 0xFFF) == STLINK_CHIPID_STM32_L1_MD_PLUS_HD) { // 0 is 384k and 1 is 256k if (flash_size == 0) { sl->flash_size = 384 * 1024; @@ -1647,7 +1647,7 @@ int stlink_load_device_params(stlink_t *sl) { // medium and low devices have the same chipid. ram size depends on flash // size. STM32F100xx datasheet Doc ID 16455 Table 2 - if (sl->chip_id == STLINK_CHIPID_STM32_F1_VL_MEDIUM_LOW && + if (sl->chip_id == STLINK_CHIPID_STM32_F1_VL_MD_LD && sl->flash_size < 64 * 1024) { sl->sram_size = 0x1000; } @@ -2715,8 +2715,8 @@ uint32_t calculate_L4_page(stlink_t *sl, uint32_t flashaddr) { flashaddr -= STM32_FLASH_BASE; if (sl->chip_id == STLINK_CHIPID_STM32_L4 || - sl->chip_id == STLINK_CHIPID_STM32_L496X || - sl->chip_id == STLINK_CHIPID_STM32_L4RX) { + sl->chip_id == STLINK_CHIPID_STM32_L496x_L4A6x || + sl->chip_id == STLINK_CHIPID_STM32_L4Rx) { // this chip use dual banked flash if (flashopt & (uint32_t)(1lu << STM32L4_FLASH_OPTR_DUALBANK)) { uint32_t banksize = (uint32_t)sl->flash_size / 2; @@ -2739,10 +2739,10 @@ uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr) { (sl->chip_id == STLINK_CHIPID_STM32_F4_DE) || (sl->chip_id == STLINK_CHIPID_STM32_F4_LP) || (sl->chip_id == STLINK_CHIPID_STM32_F4_HD) || - (sl->chip_id == STLINK_CHIPID_STM32_F411XX) || + (sl->chip_id == STLINK_CHIPID_STM32_F411xx) || (sl->chip_id == STLINK_CHIPID_STM32_F446) || (sl->chip_id == STLINK_CHIPID_STM32_F4_DSI) || - (sl->chip_id == STLINK_CHIPID_STM32_F72XXX) || + (sl->chip_id == STLINK_CHIPID_STM32_F72xxx) || (sl->chip_id == STLINK_CHIPID_STM32_F412)) { uint32_t sector = calculate_F4_sectornum(flashaddr); @@ -2758,7 +2758,7 @@ uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr) { sl->flash_pgsz = 0x20000; } } else if (sl->chip_id == STLINK_CHIPID_STM32_F7 || - sl->chip_id == STLINK_CHIPID_STM32_F7XXXX) { + sl->chip_id == STLINK_CHIPID_STM32_F76xxx) { uint32_t sector = calculate_F7_sectornum(flashaddr); if (sector < 4) { @@ -2794,10 +2794,10 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { // select the page to erase if ((sl->chip_id == STLINK_CHIPID_STM32_L4) || - (sl->chip_id == STLINK_CHIPID_STM32_L43X) || - (sl->chip_id == STLINK_CHIPID_STM32_L46X) || - (sl->chip_id == STLINK_CHIPID_STM32_L496X) || - (sl->chip_id == STLINK_CHIPID_STM32_L4RX)) { + (sl->chip_id == STLINK_CHIPID_STM32_L43x_L44x) || + (sl->chip_id == STLINK_CHIPID_STM32_L45x_L46x) || + (sl->chip_id == STLINK_CHIPID_STM32_L496x_L4A6x) || + (sl->chip_id == STLINK_CHIPID_STM32_L4Rx)) { // calculate the actual bank+page from the address uint32_t page = calculate_L4_page(sl, flashaddr); @@ -2806,7 +2806,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { write_flash_cr_bker_pnb(sl, page); } else if (sl->chip_id == STLINK_CHIPID_STM32_F7 || - sl->chip_id == STLINK_CHIPID_STM32_F7XXXX) { + sl->chip_id == STLINK_CHIPID_STM32_F76xxx) { // calculate the actual page from the address uint32_t sector = calculate_F7_sectornum(flashaddr); @@ -2990,7 +2990,7 @@ int stlink_erase_flash_mass(stlink_t *sl) { unlock_flash_if(sl); if (sl->flash_type == STLINK_FLASH_TYPE_H7 && - sl->chip_id != STLINK_CHIPID_STM32_H7AX) { + sl->chip_id != STLINK_CHIPID_STM32_H7Ax) { // set parallelism write_flash_cr_psiz(sl, 3 /*64it*/, BANK_1); if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { @@ -3265,7 +3265,7 @@ int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { set_flash_cr_pg(sl, BANK_2); } - if (sl->chip_id != STLINK_CHIPID_STM32_H7AX) { + if (sl->chip_id != STLINK_CHIPID_STM32_H7Ax) { // set parallelism write_flash_cr_psiz(sl, 3 /*64it*/, BANK_1); if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { @@ -4383,7 +4383,7 @@ int stlink_read_option_bytes32(stlink_t *sl, uint32_t *option_byte) { case STLINK_CHIPID_STM32_F4: case STLINK_CHIPID_STM32_F446: return stlink_read_option_bytes_f4(sl, option_byte); - case STLINK_CHIPID_STM32_F7XXXX: + case STLINK_CHIPID_STM32_F76xxx: return stlink_read_option_bytes_f7(sl, option_byte); case STLINK_CHIPID_STM32_G0_CAT1: case STLINK_CHIPID_STM32_G0_CAT2: @@ -4632,12 +4632,12 @@ stlink_write_option_control_register_f0(stlink_t *sl, case 0x432: /* STM32F37x */ case 0x438: /* STM32F303x6/8 and STM32F328 */ case 0x446: /* STM32F303xD/E and STM32F398xE */ - case 0x439: /* stm32f302x6/8 */ - case 0x440: /* stm32f05x */ - case 0x444: /* stm32f03x */ - case 0x445: /* stm32f04x */ - case 0x448: /* stm32f07x */ - case 0x442: /* stm32f09x */ + case 0x439: /* STM32F302x6/8 */ + case 0x440: /* STM32F05x */ + case 0x444: /* STM32F03x */ + case 0x445: /* STM32F04x */ + case 0x448: /* STM32F07x */ + case 0x442: /* STM32F09x */ option_offset = 6; user_data_offset = 16; rdp = 0x55AA; diff --git a/src/st-util/gdb-server.c b/src/st-util/gdb-server.c index 87c6c77e1..27ed81da4 100644 --- a/src/st-util/gdb-server.c +++ b/src/st-util/gdb-server.c @@ -535,14 +535,14 @@ char* make_memory_map(stlink_t *sl) { if (sl->chip_id == STLINK_CHIPID_STM32_F4 || sl->chip_id == STLINK_CHIPID_STM32_F446 || - sl->chip_id == STLINK_CHIPID_STM32_F411XX) { + sl->chip_id == STLINK_CHIPID_STM32_F411xx) { strcpy(map, memory_map_template_F4); } else if (sl->chip_id == STLINK_CHIPID_STM32_F4_DE) { strcpy(map, memory_map_template_F4_DE); } else if (sl->core_id == STM32F7_CORE_ID) { snprintf(map, sz, memory_map_template_F7, (unsigned int)sl->sram_size); - } else if (sl->chip_id == STLINK_CHIPID_STM32_H74XXX) { + } else if (sl->chip_id == STLINK_CHIPID_STM32_H74xxx) { snprintf(map, sz, memory_map_template_H7, (unsigned int)sl->flash_size, (unsigned int)sl->flash_pgsz); @@ -556,12 +556,12 @@ char* make_memory_map(stlink_t *sl) { (unsigned int)sl->sys_base, (unsigned int)sl->sys_size); } else if ((sl->chip_id == STLINK_CHIPID_STM32_L4) || - (sl->chip_id == STLINK_CHIPID_STM32_L43X) || - (sl->chip_id == STLINK_CHIPID_STM32_L46X)) { + (sl->chip_id == STLINK_CHIPID_STM32_L43x_L44x) || + (sl->chip_id == STLINK_CHIPID_STM32_L45x_L46x)) { snprintf(map, sz, memory_map_template_L4, (unsigned int)sl->flash_size, (unsigned int)sl->flash_size); - } else if (sl->chip_id == STLINK_CHIPID_STM32_L496X) { + } else if (sl->chip_id == STLINK_CHIPID_STM32_L496x_L4A6x) { snprintf(map, sz, memory_map_template_L496, (unsigned int)sl->flash_size, (unsigned int)sl->flash_size); diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index 8ef6e17c2..a9f19a155 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -11,7 +11,7 @@ static struct stlink_chipid_params devices[] = { { // RM0410 document was used to find these paramaters - .chip_id = STLINK_CHIPID_STM32_F7XXXX, + .chip_id = STLINK_CHIPID_STM32_F76xxx, .description = "F76xxx", .flash_type = STLINK_FLASH_TYPE_F7, .flash_size_reg = 0x1ff0f442, // section 45.2 @@ -42,7 +42,7 @@ static struct stlink_chipid_params devices[] = { }, { // RM0431 and DS document was used to find these paramaters - .chip_id = STLINK_CHIPID_STM32_F72XXX, + .chip_id = STLINK_CHIPID_STM32_F72xxx, .description = "F72x/F73x", .flash_type = STLINK_FLASH_TYPE_F4, .flash_size_reg = 0x1ff07a22, // section 35.2 @@ -56,7 +56,7 @@ static struct stlink_chipid_params devices[] = { }, { // table 2, PM0063 - .chip_id = STLINK_CHIPID_STM32_F1_MEDIUM, + .chip_id = STLINK_CHIPID_STM32_F1_MD, .description = "F1xx Medium-density", .flash_type = STLINK_FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7e0, @@ -84,7 +84,7 @@ static struct stlink_chipid_params devices[] = { }, { // PM0063 - .chip_id = STLINK_CHIPID_STM32_F1_LOW, + .chip_id = STLINK_CHIPID_STM32_F1_LD, .description = "F1 Low-density device", .flash_type = STLINK_FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7e0, @@ -143,7 +143,7 @@ static struct stlink_chipid_params devices[] = { .flags = CHIP_F_HAS_SWO_TRACING, }, { - .chip_id = STLINK_CHIPID_STM32_F411XX, + .chip_id = STLINK_CHIPID_STM32_F411xx, .description = "STM32F411xC/E", .flash_type = STLINK_FLASH_TYPE_F4, .flash_size_reg = 0x1FFF7A22, @@ -167,7 +167,7 @@ static struct stlink_chipid_params devices[] = { .flags = CHIP_F_HAS_SWO_TRACING, }, { - .chip_id = STLINK_CHIPID_STM32_F1_HIGH, + .chip_id = STLINK_CHIPID_STM32_F1_HD, .description = "F1xx High-density", .flash_type = STLINK_FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7e0, @@ -182,7 +182,7 @@ static struct stlink_chipid_params devices[] = { { // This ignores the EEPROM! (and uses the page erase size, // not the sector write protection...) - .chip_id = STLINK_CHIPID_STM32_L1_MEDIUM, + .chip_id = STLINK_CHIPID_STM32_L1_MD, .description = "L1xx Medium-density", .flash_type = STLINK_FLASH_TYPE_L0, .flash_size_reg = 0x1ff8004c, @@ -204,7 +204,7 @@ static struct stlink_chipid_params devices[] = { .flags = CHIP_F_HAS_SWO_TRACING, }, { - .chip_id = STLINK_CHIPID_STM32_L1_MEDIUM_PLUS, + .chip_id = STLINK_CHIPID_STM32_L1_MD_PLUS, .description = "L1xx Medium-Plus-density", .flash_type = STLINK_FLASH_TYPE_L0, .flash_size_reg = 0x1ff800cc, @@ -215,7 +215,7 @@ static struct stlink_chipid_params devices[] = { .flags = CHIP_F_HAS_SWO_TRACING, }, { - .chip_id = STLINK_CHIPID_STM32_L1_HIGH, + .chip_id = STLINK_CHIPID_STM32_L1_MD_PLUS_HD, .description = "L1xx High-density", .flash_type = STLINK_FLASH_TYPE_L0, .flash_size_reg = 0x1ff800cc, @@ -253,7 +253,7 @@ static struct stlink_chipid_params devices[] = { }, { // Low and Medium density VL have same chipid. RM0041 25.6.1 - .chip_id = STLINK_CHIPID_STM32_F1_VL_MEDIUM_LOW, + .chip_id = STLINK_CHIPID_STM32_F1_VL_MD_LD, .description = "F1xx Value Line", .flash_type = STLINK_FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7e0, @@ -322,7 +322,7 @@ static struct stlink_chipid_params devices[] = { .flags = CHIP_F_HAS_SWO_TRACING, }, { - .chip_id = STLINK_CHIPID_STM32_F1_VL_HIGH, + .chip_id = STLINK_CHIPID_STM32_F1_VL_HD, .description = "F1xx High-density value line", .flash_type = STLINK_FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7e0, @@ -335,7 +335,7 @@ static struct stlink_chipid_params devices[] = { .flags = CHIP_F_HAS_SWO_TRACING, }, { - .chip_id = STLINK_CHIPID_STM32_F1_XL, + .chip_id = STLINK_CHIPID_STM32_F1_XLD, .description = "F1xx XL-density", .flash_type = STLINK_FLASH_TYPE_F1_XL, .flash_size_reg = 0x1ffff7e0, @@ -407,7 +407,7 @@ static struct stlink_chipid_params devices[] = { .flags = CHIP_F_HAS_SWO_TRACING, }, { - .chip_id = STLINK_CHIPID_STM32_F09X, + .chip_id = STLINK_CHIPID_STM32_F09x, .description = "F09X", .flash_type = STLINK_FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) @@ -437,7 +437,7 @@ static struct stlink_chipid_params devices[] = { { // Use this as an example for mapping future chips: // RM0091 document was used to find these paramaters - .chip_id = STLINK_CHIPID_STM32_F0_SMALL, + .chip_id = STLINK_CHIPID_STM32_F0xx_SMALL, .description = "F03x", .flash_type = STLINK_FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) @@ -451,7 +451,7 @@ static struct stlink_chipid_params devices[] = { }, { // STM32F30x - .chip_id = STLINK_CHIPID_STM32_F3_SMALL, + .chip_id = STLINK_CHIPID_STM32_F3xx_SMALL, .description = "F3xx small", .flash_type = STLINK_FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7cc, @@ -523,7 +523,7 @@ static struct stlink_chipid_params devices[] = { { // This is STK32F303RET6 device from STM32 F3 Nucelo board. // Support based on DM00043574.pdf (RM0316) document rev 5. - .chip_id = STLINK_CHIPID_STM32_F303_HIGH, + .chip_id = STLINK_CHIPID_STM32_F303_HD, .description = "F303 high density", .flash_type = STLINK_FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7cc, // 34.2.1 Flash size data register @@ -560,7 +560,7 @@ static struct stlink_chipid_params devices[] = { { // STM32L4RX // From DM00310109.pdf - .chip_id = STLINK_CHIPID_STM32_L4RX, + .chip_id = STLINK_CHIPID_STM32_L4Rx, .description = "L4Rx", .flash_type = STLINK_FLASH_TYPE_L4, .flash_size_reg = @@ -573,9 +573,9 @@ static struct stlink_chipid_params devices[] = { .flags = CHIP_F_HAS_SWO_TRACING, }, { - // STLINK_CHIPID_STM32_L41X + // STLINK_CHIPID_STM32_L41x_L42x // From RM0394 Rev 4 and DS12469 Rev 5 - .chip_id = STLINK_CHIPID_STM32_L41X, + .chip_id = STLINK_CHIPID_STM32_L41x_L42x, .description = "L41x", .flash_type = STLINK_FLASH_TYPE_L4, .flash_size_reg = 0x1fff75e0, // "Flash size data register" (RM0394, @@ -591,9 +591,9 @@ static struct stlink_chipid_params devices[] = { .flags = CHIP_F_HAS_SWO_TRACING, }, { - // STLINK_CHIPID_STM32_L43X + // STLINK_CHIPID_STM32_L43x_L44x // From RM0392. - .chip_id = STLINK_CHIPID_STM32_L43X, + .chip_id = STLINK_CHIPID_STM32_L43x_L44x, .description = "L43x/L44x", .flash_type = STLINK_FLASH_TYPE_L4, .flash_size_reg = @@ -613,9 +613,9 @@ static struct stlink_chipid_params devices[] = { .flags = CHIP_F_HAS_SWO_TRACING, }, { - // STLINK_CHIPID_STM32_L496X + // STLINK_CHIPID_STM32_L496x_L4A6x // Support based on en.DM00083560.pdf (RM0351) document rev 5. - .chip_id = STLINK_CHIPID_STM32_L496X, + .chip_id = STLINK_CHIPID_STM32_L496x_L4A6x, .description = "L496x/L4A6x", .flash_type = STLINK_FLASH_TYPE_L4, .flash_size_reg = @@ -632,9 +632,9 @@ static struct stlink_chipid_params devices[] = { .flags = CHIP_F_HAS_SWO_TRACING, }, { - // STLINK_CHIPID_STM32_L46X + // STLINK_CHIPID_STM32_L45x_L46x // From RM0394 (updated version of RM0392?). - .chip_id = STLINK_CHIPID_STM32_L46X, + .chip_id = STLINK_CHIPID_STM32_L45x_L46x, .description = "L45x/46x", .flash_type = STLINK_FLASH_TYPE_L4, .flash_size_reg = @@ -764,7 +764,7 @@ static struct stlink_chipid_params devices[] = { }, { // STM32H742/743/753 (from RM0433) - .chip_id = STLINK_CHIPID_STM32_H74XXX, + .chip_id = STLINK_CHIPID_STM32_H74xxx, .description = "H74x/H75x", .flash_type = STLINK_FLASH_TYPE_H7, .flash_size_reg = 0x1ff1e880, // "Flash size register" (pg3272) @@ -780,7 +780,7 @@ static struct stlink_chipid_params devices[] = { }, { // STM32H7A3/7B3 (from RM0455) - .chip_id = STLINK_CHIPID_STM32_H7AX, + .chip_id = STLINK_CHIPID_STM32_H7Ax, .description = "H7Ax/H7Bx", .flash_type = STLINK_FLASH_TYPE_H7, .flash_size_reg = 0x08FFF80C, // "Flash size register" (p.2949) @@ -796,7 +796,7 @@ static struct stlink_chipid_params devices[] = { }, { // STM32H72x/H73x (from RM0468) - .chip_id = STLINK_CHIPID_STM32_H72X, + .chip_id = STLINK_CHIPID_STM32_H72x, .description = "H72x/H73x", .flash_type = STLINK_FLASH_TYPE_H7, .flash_size_reg = 0x1FF1E880, // "Flash size register" (p.3286) @@ -840,18 +840,18 @@ static struct stlink_chipid_params *devicelist; void dump_a_chip (FILE *fp, struct stlink_chipid_params *dev) { - fprintf (fp, "# Chipid file for %s\n", dev->description); - fprintf (fp, "#\n"); - fprintf (fp, "chip_id %x\n", dev->chip_id); - fprintf (fp, "description %s\n", dev->description); - fprintf (fp, "flash_type %x\n", dev->flash_type); - fprintf (fp, "flash_pagesize %x\n", dev->flash_pagesize); - fprintf (fp, "sram_size %x\n", dev->sram_size); - fprintf (fp, "bootrom_base %x\n", dev->bootrom_base); - fprintf (fp, "bootrom_size %x\n", dev->bootrom_size); - fprintf (fp, "option_base %x\n", dev->option_base); - fprintf (fp, "option_size %x\n", dev->option_size); - fprintf (fp, "flags %x\n\n", dev->flags); + fprintf(fp, "# Chip-ID file for %s\n", dev->description); + fprintf(fp, "#\n"); + fprintf(fp, "chip_id %x\n", dev->chip_id); + fprintf(fp, "description %s\n", dev->description); + fprintf(fp, "flash_type %x\n", dev->flash_type); + fprintf(fp, "flash_pagesize %x\n", dev->flash_pagesize); + fprintf(fp, "sram_size %x\n", dev->sram_size); + fprintf(fp, "bootrom_base %x\n", dev->bootrom_base); + fprintf(fp, "bootrom_size %x\n", dev->bootrom_size); + fprintf(fp, "option_base %x\n", dev->option_base); + fprintf(fp, "option_size %x\n", dev->option_size); + fprintf(fp, "flags %x\n\n", dev->flags); } @@ -864,21 +864,21 @@ struct stlink_chipid_params *stlink_chipid_get_params(uint32_t chipid) { for (params = devicelist ; params != NULL ; params = params -> next) if (params->chip_id == chipid) break; - p2 = stlink_chipid_get_params_old (chipid); + p2 = stlink_chipid_get_params_old(chipid); - if (memcmp (p2, params, sizeof (struct stlink_chipid_params) - sizeof (struct stlink_chipid_params *)) != 0) { + if (memcmp(p2, params, sizeof (struct stlink_chipid_params) - sizeof (struct stlink_chipid_params *)) != 0) { //fprintf (stderr, "Error, chipid params not identical\n"); //return NULL; - fprintf (stderr, "---------- old ------------\n"); - dump_a_chip (stderr, p2); - fprintf (stderr, "---------- new ------------\n"); - dump_a_chip (stderr, params); + fprintf(stderr, "---------- old ------------\n"); + dump_a_chip(stderr, p2); + fprintf(stderr, "---------- new ------------\n"); + dump_a_chip(stderr, params); } return(params); } -void process_chipfile (char *fname) +void process_chipfile(char *fname) { FILE *fp; char *p, buf[1025]; @@ -887,44 +887,44 @@ void process_chipfile (char *fname) int nc; //fprintf (stderr, "processing chipfile %s.\n", fname); - fp = fopen (fname, "r"); + fp = fopen(fname, "r"); if (!fp) { - perror (fname); + perror(fname); return; } - ts = calloc (sizeof (struct stlink_chipid_params), 1); - while (fgets (buf, 1024, fp) != NULL) { + ts = calloc(sizeof (struct stlink_chipid_params), 1); + while (fgets(buf, 1024, fp) != NULL) { for (p=buf;isspace (*p);p++); if (!*p) continue; // we hit end-of-line wiht only whitespace if (*p == '#') continue; // ignore comments. - sscanf (p, "%s %s", word, value); - if (strcmp (word, "chip_id") == 0) { - sscanf (value, "%x", &ts->chip_id); + sscanf(p, "%s %s", word, value); + if (strcmp(word, "chip_id") == 0) { + sscanf(value, "%x", &ts->chip_id); } else if (strcmp (word, "description") == 0) { //ts->description = strdup (value); buf[strlen(p)-1] = 0; // chomp newline - sscanf (p, "%*s %n", &nc); - ts->description = strdup (p+nc); + sscanf(p, "%*s %n", &nc); + ts->description = strdup(p+nc); } else if (strcmp (word, "flash_type") == 0) { - sscanf (value, "%x", &ts->flash_type); + sscanf(value, "%x", &ts->flash_type); } else if (strcmp (word, "flash_size_reg") == 0) { - sscanf (value, "%x", &ts->flash_size_reg); + sscanf(value, "%x", &ts->flash_size_reg); } else if (strcmp (word, "flash_pagesize") == 0) { - sscanf (value, "%x", &ts->flash_pagesize); + sscanf(value, "%x", &ts->flash_pagesize); } else if (strcmp (word, "sram_size") == 0) { - sscanf (value, "%x", &ts->sram_size); + sscanf(value, "%x", &ts->sram_size); } else if (strcmp (word, "bootrom_base") == 0) { - sscanf (value, "%x", &ts->bootrom_base); + sscanf(value, "%x", &ts->bootrom_base); } else if (strcmp (word, "bootrom_size") == 0) { - sscanf (value, "%x", &ts->bootrom_size); + sscanf(value, "%x", &ts->bootrom_size); } else if (strcmp (word, "option_base") == 0) { - sscanf (value, "%x", &ts->option_base); + sscanf(value, "%x", &ts->option_base); } else if (strcmp (word, "option_size") == 0) { - sscanf (value, "%x", &ts->option_size); + sscanf(value, "%x", &ts->option_size); } else if (strcmp (word, "flags") == 0) { - sscanf (value, "%x", &ts->flags); + sscanf(value, "%x", &ts->flags); } else { fprintf (stderr, "Unknown keyword in %s: %s\n", fname, word); @@ -934,7 +934,6 @@ void process_chipfile (char *fname) devicelist = ts; } - void dump_chips (void) { struct stlink_chipid_params *ts; @@ -944,30 +943,28 @@ void dump_chips (void) for (size_t n = 0; n < STLINK_ARRAY_SIZE(devices); n++) { ts = &devices[n]; - strcpy (buf, ts->description); - while ((p = strchr (buf, '/'))) // change slashes to underscore. + strcpy(buf, ts->description); + while ((p = strchr(buf, '/'))) // change slashes to underscore. *p = '_'; - strcat (buf, ".chip"); - fp = fopen (buf, "w"); - fprintf (fp, "# Chipid file for %s\n", ts->description); - fprintf (fp, "#\n"); - fprintf (fp, "chip_id %x\n", ts->chip_id); - fprintf (fp, "description %s\n", ts->description); - fprintf (fp, "flash_type %x\n", ts->flash_type); - fprintf (fp, "flash_pagesize %x\n", ts->flash_pagesize); - fprintf (fp, "sram_size %x\n", ts->sram_size); - fprintf (fp, "bootrom_base %x\n", ts->bootrom_base); - fprintf (fp, "bootrom_size %x\n", ts->bootrom_size); - fprintf (fp, "option_base %x\n", ts->option_base); - fprintf (fp, "option_size %x\n", ts->option_size); - fprintf (fp, "flags %x\n\n", ts->flags); - fclose (fp); + strcat(buf, ".chip"); + fp = fopen(buf, "w"); + fprintf(fp, "# Chip-ID file for %s\n", ts->description); + fprintf(fp, "#\n"); + fprintf(fp, "chip_id %x\n", ts->chip_id); + fprintf(fp, "description %s\n", ts->description); + fprintf(fp, "flash_type %x\n", ts->flash_type); + fprintf(fp, "flash_pagesize %x\n", ts->flash_pagesize); + fprintf(fp, "sram_size %x\n", ts->sram_size); + fprintf(fp, "bootrom_base %x\n", ts->bootrom_base); + fprintf(fp, "bootrom_size %x\n", ts->bootrom_size); + fprintf(fp, "option_base %x\n", ts->option_base); + fprintf(fp, "option_size %x\n", ts->option_size); + fprintf(fp, "flags %x\n\n", ts->flags); + fclose(fp); } } - - -void init_chipids (char *dir_to_scan) +void init_chipids(char *dir_to_scan) { DIR *d; size_t nl; // namelen @@ -979,11 +976,11 @@ void init_chipids (char *dir_to_scan) d = opendir(dir_to_scan); if (d) { while ((dir = readdir(d)) != NULL) { - nl = strlen (dir->d_name); - if (strcmp (dir->d_name + nl - 5, ".chip") == 0) { + nl = strlen(dir->d_name); + if (strcmp(dir->d_name + nl - 5, ".chip") == 0) { char buf[1024]; - sprintf (buf, "%s/%s", dir_to_scan, dir->d_name); - process_chipfile (buf); + sprintf(buf, "%s/%s", dir_to_scan, dir->d_name); + process_chipfile(buf); } } closedir(d); diff --git a/src/stlink-lib/chipid.h b/src/stlink-lib/chipid.h index f80c06732..f1342dd61 100644 --- a/src/stlink-lib/chipid.h +++ b/src/stlink-lib/chipid.h @@ -13,68 +13,66 @@ extern "C" { enum stlink_stm32_chipids { STLINK_CHIPID_UNKNOWN = 0x000, - STLINK_CHIPID_STM32_F1_MEDIUM = 0x410, + STLINK_CHIPID_STM32_F1_MD = 0x410, /* medium density */ STLINK_CHIPID_STM32_F2 = 0x411, - STLINK_CHIPID_STM32_F1_LOW = 0x412, + STLINK_CHIPID_STM32_F1_LD = 0x412, /* low density */ STLINK_CHIPID_STM32_F4 = 0x413, - STLINK_CHIPID_STM32_F1_HIGH = 0x414, + STLINK_CHIPID_STM32_F1_HD = 0x414, /* high density */ STLINK_CHIPID_STM32_L4 = 0x415, - STLINK_CHIPID_STM32_L1_MEDIUM = 0x416, + STLINK_CHIPID_STM32_L1_MD = 0x416, /* medium density */ STLINK_CHIPID_STM32_L0 = 0x417, - STLINK_CHIPID_STM32_F1_CONN = 0x418, - STLINK_CHIPID_STM32_F4_HD = 0x419, - STLINK_CHIPID_STM32_F1_VL_MEDIUM_LOW = 0x420, + STLINK_CHIPID_STM32_F1_CONN = 0x418, /* connectivity line */ + STLINK_CHIPID_STM32_F4_HD = 0x419, /* high density */ + STLINK_CHIPID_STM32_F1_VL_MD_LD = 0x420, /* value line medium & low density */ STLINK_CHIPID_STM32_F446 = 0x421, STLINK_CHIPID_STM32_F3 = 0x422, STLINK_CHIPID_STM32_F4_LP = 0x423, STLINK_CHIPID_STM32_L0_CAT2 = 0x425, - STLINK_CHIPID_STM32_L1_MEDIUM_PLUS = 0x427, /* assigned to some L1 "Medium-plus" chips */ - STLINK_CHIPID_STM32_F1_VL_HIGH = 0x428, + STLINK_CHIPID_STM32_L1_MD_PLUS = 0x427, /* medium density plus */ + STLINK_CHIPID_STM32_F1_VL_HD = 0x428, /* value line high density */ STLINK_CHIPID_STM32_L1_CAT2 = 0x429, - STLINK_CHIPID_STM32_F1_XL = 0x430, - STLINK_CHIPID_STM32_F411XX = 0x431, + STLINK_CHIPID_STM32_F1_XLD = 0x430, /* extra low density plus */ + STLINK_CHIPID_STM32_F411xx = 0x431, STLINK_CHIPID_STM32_F37x = 0x432, STLINK_CHIPID_STM32_F4_DE = 0x433, STLINK_CHIPID_STM32_F4_DSI = 0x434, - STLINK_CHIPID_STM32_L43X = 0x435, /* covers STM32L43xxx and STM32L44xxx devices */ - STLINK_CHIPID_STM32_L496X = 0x461, /* covers STM32L496xx and STM32L4A6xx devices */ - STLINK_CHIPID_STM32_L46X = 0x462, /* covers STM32L45xxx and STM32L46xxx devices */ - STLINK_CHIPID_STM32_L41X = 0x464, /* covers STM32L41xxx and STM32L42xxx devices */ - STLINK_CHIPID_STM32_L1_HIGH = 0x436, /* assigned to some L1 "Medium-Plus" and "High" chips */ + STLINK_CHIPID_STM32_L43x_L44x = 0x435, + STLINK_CHIPID_STM32_L1_MD_PLUS_HD = 0x436, /* medium density plus & high density */ STLINK_CHIPID_STM32_L152_RE = 0x437, STLINK_CHIPID_STM32_F334 = 0x438, - STLINK_CHIPID_STM32_F3_SMALL = 0x439, + STLINK_CHIPID_STM32_F3xx_SMALL = 0x439, STLINK_CHIPID_STM32_F0 = 0x440, STLINK_CHIPID_STM32_F412 = 0x441, - STLINK_CHIPID_STM32_F09X = 0x442, - STLINK_CHIPID_STM32_F0_SMALL = 0x444, + STLINK_CHIPID_STM32_F09x = 0x442, + STLINK_CHIPID_STM32_F0xx_SMALL = 0x444, STLINK_CHIPID_STM32_F04 = 0x445, - STLINK_CHIPID_STM32_F303_HIGH = 0x446, + STLINK_CHIPID_STM32_F303_HD = 0x446, /* high density */ STLINK_CHIPID_STM32_L0_CAT5 = 0x447, STLINK_CHIPID_STM32_F0_CAN = 0x448, STLINK_CHIPID_STM32_F7 = 0x449, /* ID found on the NucleoF746ZG board */ - STLINK_CHIPID_STM32_H74XXX = 0x450, /* Found on page 3189 in the RM0433*/ - STLINK_CHIPID_STM32_F7XXXX = 0x451, - STLINK_CHIPID_STM32_F72XXX = 0x452, /* ID found on the NucleoF722ZE board */ - STLINK_CHIPID_STM32_G0_CAT4 = 0x456, /* G050/G051/G061 found on RM0444/RM0454 */ + STLINK_CHIPID_STM32_H74xxx = 0x450, /* RM0433, p.3189 */ + STLINK_CHIPID_STM32_F76xxx = 0x451, + STLINK_CHIPID_STM32_F72xxx = 0x452, /* ID found on the NucleoF722ZE board */ + STLINK_CHIPID_STM32_G0_CAT4 = 0x456, /* G050/G051/G061 found in RM0444/RM0454 */ STLINK_CHIPID_STM32_L011 = 0x457, STLINK_CHIPID_STM32_F410 = 0x458, STLINK_CHIPID_STM32_G0_CAT2 = 0x460, /* G070/G071/081 */ + STLINK_CHIPID_STM32_L496x_L4A6x = 0x461, + STLINK_CHIPID_STM32_L45x_L46x = 0x462, STLINK_CHIPID_STM32_F413 = 0x463, + STLINK_CHIPID_STM32_L41x_L42x = 0x464, STLINK_CHIPID_STM32_G0_CAT1 = 0x466, /* G030/G031/041 */ - STLINK_CHIPID_STM32_G0_CAT3 = 0x467, /* G0B0/G0B1/G0C1 found on RM0444/RM0454 */ - STLINK_CHIPID_STM32_G4_CAT2 = 0x468, /* See: RM 0440 s46.6.1 "MCU device ID code" */ + STLINK_CHIPID_STM32_G0_CAT3 = 0x467, /* G0B0/G0B1/G0C1 found in RM0444/RM0454 */ + STLINK_CHIPID_STM32_G4_CAT2 = 0x468, /* RM0440, s46.6.1 "MCU device ID code" */ STLINK_CHIPID_STM32_G4_CAT3 = 0x469, - STLINK_CHIPID_STM32_L4RX = 0x470, /* ID found on the STM32L4R9I-DISCO board */ - STLINK_CHIPID_STM32_H7AX = 0x480, /* RM0455, p. 2863 */ - STLINK_CHIPID_STM32_H72X = 0x483, /* RM0468, p. 3199 */ + STLINK_CHIPID_STM32_L4Rx = 0x470, /* ID found on the STM32L4R9I-DISCO board */ + STLINK_CHIPID_STM32_H7Ax = 0x480, /* RM0455, p.2863 */ + STLINK_CHIPID_STM32_H72x = 0x483, /* RM0468, p.3199 */ STLINK_CHIPID_STM32_WB55 = 0x495 }; - -#define CHIP_F_HAS_DUAL_BANK (1 << 0) -#define CHIP_F_HAS_SWO_TRACING (1 << 1) - +#define CHIP_F_HAS_DUAL_BANK (1 << 0) +#define CHIP_F_HAS_SWO_TRACING (1 << 1) /** Chipid parameters */ struct stlink_chipid_params { @@ -94,7 +92,7 @@ struct stlink_chipid_params { struct stlink_chipid_params *stlink_chipid_get_params(uint32_t chipid); - void init_chipids (char *dir_to_scan); + void init_chipids(char *dir_to_scan); #ifdef __cplusplus } diff --git a/src/stlink-lib/flash_loader.c b/src/stlink-lib/flash_loader.c index d492716db..9a1e86681 100644 --- a/src/stlink-lib/flash_loader.c +++ b/src/stlink-lib/flash_loader.c @@ -227,10 +227,10 @@ int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* const uint8_t* loader_code; size_t loader_size; - if (sl->chip_id == STLINK_CHIPID_STM32_L1_MEDIUM || + if (sl->chip_id == STLINK_CHIPID_STM32_L1_MD || sl->chip_id == STLINK_CHIPID_STM32_L1_CAT2 || - sl->chip_id == STLINK_CHIPID_STM32_L1_MEDIUM_PLUS || - sl->chip_id == STLINK_CHIPID_STM32_L1_HIGH || + sl->chip_id == STLINK_CHIPID_STM32_L1_MD_PLUS || + sl->chip_id == STLINK_CHIPID_STM32_L1_MD_PLUS_HD || sl->chip_id == STLINK_CHIPID_STM32_L152_RE || sl->chip_id == STLINK_CHIPID_STM32_L011 || sl->chip_id == STLINK_CHIPID_STM32_L0 || @@ -239,16 +239,16 @@ int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* loader_code = loader_code_stm32lx; loader_size = sizeof(loader_code_stm32lx); } else if (sl->core_id == STM32VL_CORE_ID || - sl->chip_id == STLINK_CHIPID_STM32_F1_MEDIUM || - sl->chip_id == STLINK_CHIPID_STM32_F1_HIGH || - sl->chip_id == STLINK_CHIPID_STM32_F1_LOW || - sl->chip_id == STLINK_CHIPID_STM32_F1_VL_MEDIUM_LOW || - sl->chip_id == STLINK_CHIPID_STM32_F1_VL_HIGH || - sl->chip_id == STLINK_CHIPID_STM32_F1_XL || + sl->chip_id == STLINK_CHIPID_STM32_F1_MD || + sl->chip_id == STLINK_CHIPID_STM32_F1_HD || + sl->chip_id == STLINK_CHIPID_STM32_F1_LD || + sl->chip_id == STLINK_CHIPID_STM32_F1_VL_MD_LD || + sl->chip_id == STLINK_CHIPID_STM32_F1_VL_HD || + sl->chip_id == STLINK_CHIPID_STM32_F1_XLD || sl->chip_id == STLINK_CHIPID_STM32_F1_CONN || sl->chip_id == STLINK_CHIPID_STM32_F3 || - sl->chip_id == STLINK_CHIPID_STM32_F3_SMALL || - sl->chip_id == STLINK_CHIPID_STM32_F303_HIGH || + sl->chip_id == STLINK_CHIPID_STM32_F3xx_SMALL || + sl->chip_id == STLINK_CHIPID_STM32_F303_HD || sl->chip_id == STLINK_CHIPID_STM32_F37x || sl->chip_id == STLINK_CHIPID_STM32_F334) { loader_code = loader_code_stm32vl; @@ -260,7 +260,7 @@ int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* sl->chip_id == STLINK_CHIPID_STM32_F4_HD || sl->chip_id == STLINK_CHIPID_STM32_F4_DSI || sl->chip_id == STLINK_CHIPID_STM32_F410 || - sl->chip_id == STLINK_CHIPID_STM32_F411XX || + sl->chip_id == STLINK_CHIPID_STM32_F411xx || sl->chip_id == STLINK_CHIPID_STM32_F412 || sl->chip_id == STLINK_CHIPID_STM32_F413 || sl->chip_id == STLINK_CHIPID_STM32_F446) { @@ -273,8 +273,8 @@ int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* if (retval == -1) { return(retval); } } else if (sl->core_id == STM32F7_CORE_ID || sl->chip_id == STLINK_CHIPID_STM32_F7 || - sl->chip_id == STLINK_CHIPID_STM32_F7XXXX || - sl->chip_id == STLINK_CHIPID_STM32_F72XXX) { + sl->chip_id == STLINK_CHIPID_STM32_F76xxx || + sl->chip_id == STLINK_CHIPID_STM32_F72xxx) { int retval; retval = loader_v_dependent_assignment(sl, &loader_code, &loader_size, @@ -285,16 +285,16 @@ int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* } else if (sl->chip_id == STLINK_CHIPID_STM32_F0 || sl->chip_id == STLINK_CHIPID_STM32_F04 || sl->chip_id == STLINK_CHIPID_STM32_F0_CAN || - sl->chip_id == STLINK_CHIPID_STM32_F0_SMALL || - sl->chip_id == STLINK_CHIPID_STM32_F09X) { + sl->chip_id == STLINK_CHIPID_STM32_F0xx_SMALL || + sl->chip_id == STLINK_CHIPID_STM32_F09x) { loader_code = loader_code_stm32f0; loader_size = sizeof(loader_code_stm32f0); } else if ((sl->chip_id == STLINK_CHIPID_STM32_L4) || - (sl->chip_id == STLINK_CHIPID_STM32_L41X) || - (sl->chip_id == STLINK_CHIPID_STM32_L43X) || - (sl->chip_id == STLINK_CHIPID_STM32_L46X) || - (sl->chip_id == STLINK_CHIPID_STM32_L4RX) || - (sl->chip_id == STLINK_CHIPID_STM32_L496X)) { + (sl->chip_id == STLINK_CHIPID_STM32_L41x_L42x) || + (sl->chip_id == STLINK_CHIPID_STM32_L43x_L44x) || + (sl->chip_id == STLINK_CHIPID_STM32_L45x_L46x) || + (sl->chip_id == STLINK_CHIPID_STM32_L4Rx) || + (sl->chip_id == STLINK_CHIPID_STM32_L496x_L4A6x)) { loader_code = loader_code_stm32l4; loader_size = sizeof(loader_code_stm32l4); } else { From 9d93531ac1a014eddd5efe3b1ca7bde8ec3bcc73 Mon Sep 17 00:00:00 2001 From: Biswapriyo Nath Date: Tue, 18 May 2021 19:46:45 +0530 Subject: [PATCH 266/503] cmake: Install shared libraries in proper directories. This fixes the installation of DLL file in mingw. --- CMakeLists.txt | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index 4bd76ebfb..43c5dbac1 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -194,8 +194,11 @@ else () target_link_libraries(${STLINK_LIB_SHARED} ${LIBUSB_LIBRARY} ${SSP_LIB}) endif () -install(TARGETS ${STLINK_LIB_SHARED} DESTINATION ${STLINK_LIBRARY_PATH}) - +install(TARGETS ${STLINK_LIB_SHARED} + ARCHIVE DESTINATION ${STLINK_LIBRARY_PATH} + LIBRARY DESTINATION ${STLINK_LIBRARY_PATH} + RUNTIME DESTINATION ${CMAKE_INSTALL_BINDIR} + ) ### # Static library From 553713d911e07fe6e02e907e2c9ab2b012f28d32 Mon Sep 17 00:00:00 2001 From: Biswapriyo Nath Date: Tue, 18 May 2021 19:47:33 +0530 Subject: [PATCH 267/503] win32: Fix socket fd type. --- src/win32/win32_socket.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/win32/win32_socket.c b/src/win32/win32_socket.c index 9138a7679..bfdcac5ce 100644 --- a/src/win32/win32_socket.c +++ b/src/win32/win32_socket.c @@ -70,7 +70,7 @@ int win32_poll(struct pollfd *fds, unsigned int nfds, int timo) { if (rc > 0) { for ( i = 0; i < nfds; ++i) { - int fd = fds[i].fd; + SOCKET fd = fds[i].fd; if (fds[i].events & (POLLIN | POLLPRI) && FD_ISSET(fd, &ifds)) { fds[i].revents |= POLLIN; From a9adf9cb29d90af9d53c8adef673bcdc7d2490ae Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Tue, 18 May 2021 22:53:33 +0200 Subject: [PATCH 268/503] General Project Update - Updated CHANGELOG.md - Updated CI configs for macOS 11 & 10.14 --- .travis.yml | 34 +++++++++++++++++++++++++++++----- CHANGELOG.md | 10 ++++++---- doc/version_support.md | 4 ++-- 3 files changed, 37 insertions(+), 11 deletions(-) diff --git a/.travis.yml b/.travis.yml index c54c0c6f4..469094892 100644 --- a/.travis.yml +++ b/.travis.yml @@ -30,7 +30,7 @@ jobs: - os: osx env: BADGE=osx - osx_image: xcode10.3 + osx_image: xcode10.3 # xcode11.3 to xcode11.3.1 fail to compile name: macOS 10.14.4 gcc compiler: gcc addons: @@ -42,7 +42,7 @@ jobs: - os: osx env: BADGE=osx - osx_image: xcode10.3 + osx_image: xcode10.3 # xcode11.3 to xcode11.3.1 fail to compile name: macOS 10.14.4 gcc 32-bit compiler: gcc addons: @@ -56,7 +56,7 @@ jobs: - os: osx env: BADGE=osx - osx_image: xcode10.3 + osx_image: xcode10.3 # xcode11.3 to xcode11.3.1 fail to compile name: macOS 10.14.4 clang compiler: clang addons: @@ -68,9 +68,9 @@ jobs: - os: osx env: BADGE=osx - osx_image: xcode10.3 + osx_image: xcode10.3 # xcode11.3 to xcode11.3.1 fail to compile name: macOS 10.14.4 clang 32-bit - compiler: gcc + compiler: clang addons: homebrew: packages: @@ -80,6 +80,30 @@ jobs: before_install: - CFLAGS="$CFLAGS -m32"; CXXFLAGS="$CXXFLAGS -m32"; LDFLAGS="$LDFLAGS -m32"; + - os: osx + env: BADGE=osx + osx_image: xcode12.5 + name: macOS 11.3 gcc + compiler: gcc + addons: + homebrew: + packages: + - gcc + - libusb + - gtk+3 + + - os: osx + env: BADGE=osx + osx_image: xcode12.5 + name: macOS 11.3 clang + compiler: clang + addons: + homebrew: + packages: + - clang + - libusb + - gtk+3 + script: - git fetch --tags - printenv diff --git a/CHANGELOG.md b/CHANGELOG.md index b43d58da7..5314ea912 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -16,8 +16,10 @@ Features: Updates & changes: - Added instructions for bug-reports and feature-requests to contribution guidelines ([#906](https://github.com/stlink-org/stlink/pull/906)) +- Added travis CI configuration for macOS 10.14 to maintain capability for 32-bit compilation ([#f5ada94](https://github.com/stlink-org/stlink/commit/f5ada9474cdb87ff37de0d4eb9e75622b5870646)) Fixes: +- cmake: Install shared libraries in proper directories ([#1142](https://github.com/stlink-org/stlink/pull/1142)) # v1.7.0 @@ -59,10 +61,10 @@ Updates & changes: Fixes: -- Improvements and fixes of the flash loaders, unification of the reset function ([#244](https://github.com/stlink-org/stlink/pull/244), [#382](https://github.com/stlink-org/stlink/pull/382), [#705](https://github.com/stlink-org/stlink/pull/705), [#980](https://github.com/stlink-org/stlink/pull/980), [#995](https://github.com/stlink-org/stlink/pull/995), [#1008](https://github.com/stlink-org/stlink/pull/1008), [#1115](https://github.com/stlink-org/stlink/pull/1115), [#1117](https://github.com/stlink-org/stlink/pull/1117), [#1122](https://github.com/stlink-org/stlink/pull/1122), [#1124](https://github.com/stlink-org/stlink/pull/1124)) -- Flash loader rework ([#356](https://github.com/stlink-org/stlink/pull/356), [#556](https://github.com/stlink-org/stlink/pull/556), [#593](https://github.com/stlink-org/stlink/pull/593), [#597](https://github.com/stlink-org/stlink/pull/597), [#607](https://github.com/stlink-org/stlink/pull/607), [#612](https://github.com/stlink-org/stlink/pull/612), [#638](https://github.com/stlink-org/stlink/pull/638), [#661](https://github.com/stlink-org/stlink/pull/661), [#690](https://github.com/stlink-org/stlink/pull/690), [#807](https://github.com/stlink-org/stlink/pull/807), [#817](https://github.com/stlink-org/stlink/pull/817), [#818](https://github.com/stlink-org/stlink/pull/818), [#854](https://github.com/stlink-org/stlink/pull/854), [#868](https://github.com/stlink-org/stlink/pull/868), [#967](https://github.com/stlink-org/stlink/pull/967), [#979](https://github.com/stlink-org/stlink/pull/979), [#1008](https://github.com/stlink-org/stlink/pull/1008), [#1043](https://github.com/stlink-org/stlink/pull/1043), [#1054](https://github.com/stlink-org/stlink/pull/1054), [#1092](https://github.com/stlink-org/stlink/pull/1092), [#1105](https://github.com/stlink-org/stlink/pull/1105), [#1113](https://github.com/stlink-org/stlink/pull/1113)) +- Improvements and fixes of the flash loaders, unification of the reset function ([#244](https://github.com/stlink-org/stlink/pull/244), [#382](https://github.com/stlink-org/stlink/pull/382), [#705](https://github.com/stlink-org/stlink/pull/705), [#724](https://github.com/stlink-org/stlink/pull/724), [#980](https://github.com/stlink-org/stlink/pull/980), [#995](https://github.com/stlink-org/stlink/pull/995), [#1008](https://github.com/stlink-org/stlink/pull/1008), [#1115](https://github.com/stlink-org/stlink/pull/1115), [#1117](https://github.com/stlink-org/stlink/pull/1117), [#1122](https://github.com/stlink-org/stlink/pull/1122), [#1124](https://github.com/stlink-org/stlink/pull/1124)) +- Flash loader rework ([#356](https://github.com/stlink-org/stlink/pull/356), [#556](https://github.com/stlink-org/stlink/pull/556), [#593](https://github.com/stlink-org/stlink/pull/593), [#597](https://github.com/stlink-org/stlink/pull/597), [#607](https://github.com/stlink-org/stlink/pull/607), [#612](https://github.com/stlink-org/stlink/pull/612), [#638](https://github.com/stlink-org/stlink/pull/638), [#661](https://github.com/stlink-org/stlink/pull/661), [#690](https://github.com/stlink-org/stlink/pull/690), [#724](https://github.com/stlink-org/stlink/pull/724), [#807](https://github.com/stlink-org/stlink/pull/807), [#817](https://github.com/stlink-org/stlink/pull/817), [#818](https://github.com/stlink-org/stlink/pull/818), [#854](https://github.com/stlink-org/stlink/pull/854), [#868](https://github.com/stlink-org/stlink/pull/868), [#967](https://github.com/stlink-org/stlink/pull/967), [#979](https://github.com/stlink-org/stlink/pull/979), [#1008](https://github.com/stlink-org/stlink/pull/1008), [#1043](https://github.com/stlink-org/stlink/pull/1043), [#1054](https://github.com/stlink-org/stlink/pull/1054), [#1092](https://github.com/stlink-org/stlink/pull/1092), [#1105](https://github.com/stlink-org/stlink/pull/1105), [#1113](https://github.com/stlink-org/stlink/pull/1113)) - Fixed old DFU serial number for STLINK programmers ([#417](https://github.com/stlink-org/stlink/pull/417), [#494](https://github.com/stlink-org/stlink/pull/494), [#1106](https://github.com/stlink-org/stlink/pull/1106), [#1121](https://github.com/stlink-org/stlink/pull/1121)) -- Use vl flashloader for all STM32F1 series ([#769](https://github.com/stlink-org/stlink/pull/769), [#1041](https://github.com/stlink-org/stlink/pull/1041), [#1044](https://github.com/stlink-org/stlink/pull/1044)) +- Use vl flashloader for all STM32F1 series ([#724](https://github.com/stlink-org/stlink/pull/724), [#769](https://github.com/stlink-org/stlink/pull/769), [#1041](https://github.com/stlink-org/stlink/pull/1041), [#1044](https://github.com/stlink-org/stlink/pull/1044)) - [regression] Changed timeout on flash write ([#787](https://github.com/stlink-org/stlink/pull/787), [#981](https://github.com/stlink-org/stlink/pull/981), [#987](https://github.com/stlink-org/stlink/pull/987)) - cmake compile failure with external `CMAKE_MODULE_PATH` set ([#962](https://github.com/stlink-org/stlink/pull/962)) - doc/man: Fixed installation directory ([#970](https://github.com/stlink-org/stlink/pull/970)) @@ -264,7 +266,7 @@ Updates and fixes: - Debian packaging, `cmake` and `README.md` fixes ([#682](https://github.com/stlink-org/stlink/pull/682), [#683](https://github.com/stlink-org/stlink/pull/683)) - Disabled static library installation by default ([#702](https://github.com/stlink-org/stlink/pull/702)) - Fix for `libusb` deprecation ([#703](https://github.com/stlink-org/stlink/pull/703), [#704](https://github.com/stlink-org/stlink/pull/704)) -- Renamed `STLINK_CHIPID_STM32_L4R9` to `STLINK_CHIPID_STM32_L4RX` ([#706](https://github.com/stlink-org/stlink/pull/706)) +- Renamed `STLINK_CHIPID_STM32_L4R9` to `STLINK_CHIPID_STM32_L4Rx` ([#706](https://github.com/stlink-org/stlink/pull/706)) - [regression] stlink installation under Linux (Debian 9) is broken since #695 ([#700](https://github.com/stlink-org/stlink/pull/700), [#701](https://github.com/stlink-org/stlink/pull/701), [#707](https://github.com/stlink-org/stlink/pull/707)) - Fixed flash memory map for STM32F72xxx target ([#711](https://github.com/stlink-org/stlink/pull/711)) - Proper flash page size calculation for STM32F412xx target ([#721](https://github.com/stlink-org/stlink/pull/721)) diff --git a/doc/version_support.md b/doc/version_support.md index 6aafc8112..408c1be85 100644 --- a/doc/version_support.md +++ b/doc/version_support.md @@ -14,8 +14,8 @@ Up on compiling c-make will **automatically** download and install the latest co | Package Repository | libusb
version | cmake
version | gtk-3
version | Supported macOS versions | | ------------------ | ------------------- | ------------------ | ------------------ | ------------------------ | -| homebrew | 1.0.23 | 3.17.0 | 3.24.18
gtk+3 | 10.9 - 10.15 | -| MacPorts | 1.0.23 | 3.17.0 | 3.24.18
gtk3 | 10.4 - 10.15 | +| homebrew | 1.0.23 | 3.17.0 | 3.24.18
gtk+3 | 10.9 - 11.x | +| MacPorts | 1.0.23 | 3.17.0 | 3.24.18
gtk3 | 10.4 - 11.x | NOTE: In order to use a STLINK/V1 programmer on macOS, versions 10.14 or 10.15 are required. From eafb4d17925296cf8c31f4309294c424d7174186 Mon Sep 17 00:00:00 2001 From: Jonathan Giles Date: Wed, 19 May 2021 10:40:40 -0400 Subject: [PATCH 269/503] Change description of chip id 0x0457 to L01x/L02x. --- src/stlink-lib/chipid.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index 13d065a27..711bf24b0 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -647,7 +647,7 @@ static const struct stlink_chipid_params devices[] = { { // STM32L011 .chip_id = STLINK_CHIPID_STM32_L011, - .description = "L011", + .description = "L01x/L02x", .flash_type = STLINK_FLASH_TYPE_L0, .flash_size_reg = 0x1ff8007c, .flash_pagesize = 0x80, From 69239406344fbfe14b80af1cad8b91c3dea01950 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Fri, 21 May 2021 14:50:11 +0200 Subject: [PATCH 270/503] Corrected CHANGELOG.md --- CHANGELOG.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index 5314ea912..57ed15e98 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -89,6 +89,7 @@ Fixes: - Fixed STM32WB55 reading DEBUG IDCODE from the wrong address ([#1100](https://github.com/stlink-org/stlink/pull/1100), [#1101](https://github.com/stlink-org/stlink/pull/1101)) - Applied missing changes to tests ([#1119](https://github.com/stlink-org/stlink/pull/1119)) - Improvements for Chip_ID read ([#1008](https://github.com/stlink-org/stlink/pull/1008), [#1120](https://github.com/stlink-org/stlink/pull/1120)) +- Fixed reading of chip ID on Cortex-M0+ core ([#1017](https://github.com/stlink-org/stlink/pull/1017), [#1125](https://github.com/stlink-org/stlink/pull/1125), [#1126](https://github.com/stlink-org/stlink/pull/1126), [#1133](https://github.com/stlink-org/stlink/pull/1133)) # v1.6.1 @@ -186,7 +187,6 @@ Fixes: - Set static link for `libssp` (stack-smashing protection) ([#960](https://github.com/stlink-org/stlink/pull/960), [#961](https://github.com/stlink-org/stlink/pull/961)) - Fixed udev rules installing to wrong directory ([#966](https://github.com/stlink-org/stlink/pull/966)) - Fixed formatting for options display in `st-flash` & `st-info` (commits [#c783d0e](https://github.com/stlink-org/stlink/commit/c783d0e777ccc83a7a8be26a4f4d3414e0478560) and [#562cd24](https://github.com/stlink-org/stlink/commit/562cd2496e696dbd22950925866aac662d81ee5f)) -- Fixed reading of chip ID on Cortex-M0+ core ([#1125](https://github.com/stlink-org/stlink/pull/1125), [#1126](https://github.com/stlink-org/stlink/pull/1126), [#1133](https://github.com/stlink-org/stlink/pull/1133)) # v1.6.0 From cab9fc4210ac090da6b7e45d91ffd300549a9436 Mon Sep 17 00:00:00 2001 From: anton Date: Sat, 22 May 2021 23:40:36 +0500 Subject: [PATCH 271/503] Improved command error messages --- inc/stlink.h | 8 +- src/common.c | 3 - src/stlink-lib/usb.c | 238 +++++++++++++++---------------------------- 3 files changed, 88 insertions(+), 161 deletions(-) diff --git a/inc/stlink.h b/inc/stlink.h index 69a4799f5..f70060b05 100644 --- a/inc/stlink.h +++ b/inc/stlink.h @@ -86,6 +86,8 @@ enum target_state { /* Error code */ #define STLINK_DEBUG_ERR_OK 0x80 #define STLINK_DEBUG_ERR_FAULT 0x81 +#define STLINK_DEBUG_ERR_WRITE 0x0c +#define STLINK_DEBUG_ERR_WRITE_VERIFY 0x0d #define STLINK_DEBUG_ERR_AP_WAIT 0x10 #define STLINK_DEBUG_ERR_AP_FAULT 0x11 #define STLINK_DEBUG_ERR_AP_ERROR 0x12 @@ -93,8 +95,10 @@ enum target_state { #define STLINK_DEBUG_ERR_DP_FAULT 0x15 #define STLINK_DEBUG_ERR_DP_ERROR 0x16 -#define CMD_NO_RETRY 0 -#define CMD_USE_RETRY 3 +#define CMD_CHECK_NO 0 +#define CMD_CHECK_REP_LEN 1 +#define CMD_CHECK_STATUS 2 +#define CMD_CHECK_RETRY 3 /* check status and retry if wait error */ #define C_BUF_LEN 32 diff --git a/src/common.c b/src/common.c index 661ee34ec..6333ff408 100644 --- a/src/common.c +++ b/src/common.c @@ -2301,9 +2301,6 @@ static void stlink_checksum(mapped_file_t *mp) { static void stlink_fwrite_finalize(stlink_t *sl, stm32_addr_t addr) { unsigned int val; - // set stack - stlink_read_debug32(sl, addr, &val); - stlink_write_reg(sl, val, 13); // set PC to the reset routine stlink_read_debug32(sl, addr + 4, &val); stlink_write_reg(sl, val, 15); diff --git a/src/stlink-lib/usb.c b/src/stlink-lib/usb.c index 5e17189c6..a58681702 100644 --- a/src/stlink-lib/usb.c +++ b/src/stlink-lib/usb.c @@ -85,56 +85,62 @@ void _stlink_usb_close(stlink_t* sl) { ssize_t send_recv(struct stlink_libusb* handle, int terminate, unsigned char* txbuf, size_t txsize, unsigned char* rxbuf, - size_t rxsize, bool check_error, int retry_cnt) { + size_t rxsize, int check_error, const char *cmd) { // Note: txbuf and rxbuf can point to the same area int res, t, retry = 0; - int cmd = read_uint16(txbuf, (handle->protocoll == 1)?15:0); while (1) { res = 0; t = libusb_bulk_transfer(handle->usb_handle, handle->ep_req, txbuf, (int)txsize, &res, 3000); if (t) { - ELOG("[!] send_recv send request failed: %s (command 0x%02X)\n", libusb_error_name(t), cmd); + ELOG("%s send request failed: %s\n", cmd, libusb_error_name(t)); return(-1); } else if ((size_t)res != txsize) { - ELOG("[!] send_recv send request wrote %u bytes, instead of %u (command 0x%02X)\n", - (unsigned int)res, (unsigned int)txsize, cmd); + ELOG("%s send request wrote %u bytes, instead of %u\n", + cmd, (unsigned int)res, (unsigned int)txsize); } if (rxsize != 0) { t = libusb_bulk_transfer(handle->usb_handle, handle->ep_rep, rxbuf, (int)rxsize, &res, 3000); if (t) { - ELOG("[!] send_recv read reply failed: %s (command 0x%02X)\n", libusb_error_name(t), cmd); + ELOG("%s read reply failed: %s\n", cmd, libusb_error_name(t)); return(-1); } /* Checking the command execution status stored in the first byte of the response */ - if (handle->protocoll != 1 && check_error && + if (handle->protocoll != 1 && check_error >= CMD_CHECK_STATUS && rxbuf[0] != STLINK_DEBUG_ERR_OK) { switch(rxbuf[0]) { case STLINK_DEBUG_ERR_AP_WAIT: case STLINK_DEBUG_ERR_DP_WAIT: - if (retry < retry_cnt) { + if (check_error == CMD_CHECK_RETRY && retry < 3) { unsigned int delay_us = (1<protocoll == 1) && terminate) { @@ -143,7 +149,7 @@ ssize_t send_recv(struct stlink_libusb* handle, int terminate, t = libusb_bulk_transfer(handle->usb_handle, handle->ep_rep, sg_buf, 13, &res, 3000); if (t) { - ELOG("[!] send_recv read storage failed: %s (command 0x%02X)\n", libusb_error_name(t), cmd); + ELOG("stlink: %s read storage failed: %s\n", cmd, libusb_error_name(t)); return(-1); } @@ -156,8 +162,9 @@ ssize_t send_recv(struct stlink_libusb* handle, int terminate, } static inline int send_only(struct stlink_libusb* handle, int terminate, - unsigned char* txbuf, size_t txsize) { - return((int)send_recv(handle, terminate, txbuf, txsize, NULL, 0, false, CMD_NO_RETRY)); + unsigned char* txbuf, size_t txsize, + const char *cmd) { + return((int)send_recv(handle, terminate, txbuf, txsize, NULL, 0, CMD_CHECK_NO, cmd)); } @@ -201,12 +208,9 @@ int _stlink_usb_version(stlink_t *sl) { cmd[i++] = STLINK_GET_VERSION; } - size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, false, CMD_USE_RETRY); - if (size != (ssize_t)rep_len) { - return((int)size); - } + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_REP_LEN, "GET_VERSION"); - return(0); + return(size<0?-1:0); } int32_t _stlink_usb_target_voltage(stlink_t *sl) { @@ -221,13 +225,10 @@ int32_t _stlink_usb_target_voltage(stlink_t *sl) { cmd[i++] = STLINK_GET_TARGET_VOLTAGE; - size = send_recv(slu, 1, cmd, slu->cmd_len, rdata, rep_len, false, CMD_NO_RETRY); + size = send_recv(slu, 1, cmd, slu->cmd_len, rdata, rep_len, CMD_CHECK_REP_LEN, "GET_TARGET_VOLTAGE"); if (size < 0) { return(-1); - } else if (size != 8) { - printf("[!] wrong length STLINK_GET_TARGET_VOLTAGE\n"); - return(-1); } factor = (rdata[3] << 24) | (rdata[2] << 16) | (rdata[1] << 8) | (rdata[0] << 0); @@ -248,10 +249,10 @@ int _stlink_usb_read_debug32(stlink_t *sl, uint32_t addr, uint32_t *data) { cmd[i++] = STLINK_DEBUG_COMMAND; cmd[i++] = STLINK_DEBUG_APIV2_READDEBUGREG; write_uint32(&cmd[i], addr); - size = send_recv(slu, 1, cmd, slu->cmd_len, rdata, rep_len, true, CMD_USE_RETRY); + size = send_recv(slu, 1, cmd, slu->cmd_len, rdata, rep_len, CMD_CHECK_RETRY, "READDEBUGREG"); if (size < 0) { - return((int)size); + return(-1); } *data = read_uint32(rdata, 4); @@ -271,13 +272,9 @@ int _stlink_usb_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data) { cmd[i++] = STLINK_DEBUG_APIV2_WRITEDEBUGREG; write_uint32(&cmd[i], addr); write_uint32(&cmd[i + 4], data); - size = send_recv(slu, 1, cmd, slu->cmd_len, rdata, rep_len, true, CMD_USE_RETRY); + size = send_recv(slu, 1, cmd, slu->cmd_len, rdata, rep_len, CMD_CHECK_RETRY, "WRITEDEBUGREG"); - if (size < 0) { - return((int)size); - } - - return(0); + return(size<0?-1:0); } int _stlink_usb_get_rw_status(stlink_t *sl) { @@ -294,15 +291,13 @@ int _stlink_usb_get_rw_status(stlink_t *sl) { if (sl->version.flags & STLINK_F_HAS_GETLASTRWSTATUS2) { cmd[i++] = STLINK_DEBUG_APIV2_GETLASTRWSTATUS2; - ret = send_recv(slu, 1, cmd, slu->cmd_len, rdata, 12, true, CMD_NO_RETRY); + ret = send_recv(slu, 1, cmd, slu->cmd_len, rdata, 12, CMD_CHECK_STATUS, "GETLASTRWSTATUS2"); } else { cmd[i++] = STLINK_DEBUG_APIV2_GETLASTRWSTATUS; - ret = send_recv(slu, 1, cmd, slu->cmd_len, rdata, 2, true, CMD_NO_RETRY); + ret = send_recv(slu, 1, cmd, slu->cmd_len, rdata, 2, CMD_CHECK_STATUS, "GETLASTRWSTATUS"); } - if (ret < 0) { return(-1); } - - return(0); + return(ret<0?-1:0); } int _stlink_usb_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { @@ -316,11 +311,11 @@ int _stlink_usb_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { cmd[i++] = STLINK_DEBUG_WRITEMEM_32BIT; write_uint32(&cmd[i], addr); write_uint16(&cmd[i + 4], len); - ret = send_only(slu, 0, cmd, slu->cmd_len); + ret = send_only(slu, 0, cmd, slu->cmd_len, "WRITEMEM_32BIT"); if (ret == -1) { return(ret); } - ret = send_only(slu, 1, data, len); + ret = send_only(slu, 1, data, len, "WRITEMEM_32BIT"); if (ret == -1) { return(ret); } @@ -338,11 +333,11 @@ int _stlink_usb_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len) { cmd[i++] = STLINK_DEBUG_WRITEMEM_8BIT; write_uint32(&cmd[i], addr); write_uint16(&cmd[i + 4], len); - ret = send_only(slu, 0, cmd, slu->cmd_len); + ret = send_only(slu, 0, cmd, slu->cmd_len, "WRITEMEM_32BIT"); if (ret == -1) { return(ret); } - ret = send_only(slu, 1, data, len); + ret = send_only(slu, 1, data, len, "WRITEMEM_32BIT"); if (ret == -1) { return(ret); } @@ -359,7 +354,7 @@ int _stlink_usb_current_mode(stlink_t * sl) { int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); cmd[i++] = STLINK_GET_CURRENT_MODE; - size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, false, CMD_NO_RETRY); + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_NO, "GET_CURRENT_MODE"); if (size < 0) { return(-1); @@ -386,7 +381,7 @@ int _stlink_usb_core_id(stlink_t * sl) { offset = 4; } - size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, true, CMD_NO_RETRY); + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_STATUS, "READ_IDCODES"); if (size < 0) { return(-1); @@ -431,15 +426,9 @@ int _stlink_usb_status(stlink_t * sl) { cmd[i++] = STLINK_DEBUG_COMMAND; cmd[i++] = STLINK_DEBUG_GETSTATUS; - size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, false, CMD_NO_RETRY); - - if (size < 0) { - return((int)size); - } - - sl->q_len = (int)size; + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_NO, "GETSTATUS"); - if (sl->q_len > 1) { + if (size > 1) { if (sl->q_buf[0] == STLINK_CORE_RUNNING) { sl->core_stat = TARGET_RUNNING; } else if (sl->q_buf[0] == STLINK_CORE_HALTED) { @@ -451,7 +440,7 @@ int _stlink_usb_status(stlink_t * sl) { sl->core_stat = TARGET_UNKNOWN; } - return(0); + return(size<0?-1:0); } int _stlink_usb_force_debug(stlink_t *sl) { @@ -472,13 +461,9 @@ int _stlink_usb_force_debug(stlink_t *sl) { cmd[i++] = STLINK_DEBUG_COMMAND; cmd[i++] = STLINK_DEBUG_FORCEDEBUG; - size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, true, CMD_USE_RETRY); - - if (size < 0) { - return((int)size); - } + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_RETRY, "FORCEDEBUG"); - return(0); + return(size<0?-1:0); } int _stlink_usb_enter_swd_mode(stlink_t * sl) { @@ -493,13 +478,9 @@ int _stlink_usb_enter_swd_mode(stlink_t * sl) { // select correct API-Version for entering SWD mode: V1 API (0x20) or V2 API (0x30). cmd[i++] = sl->version.jtag_api == STLINK_JTAG_API_V1 ? STLINK_DEBUG_APIV1_ENTER : STLINK_DEBUG_APIV2_ENTER; cmd[i++] = STLINK_DEBUG_ENTER_SWD; - size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, true, CMD_USE_RETRY); - - if (size < 0) { - return((int)size); - } + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_RETRY, "ENTER_SWD"); - return(0); + return(size<0?-1:0); } int _stlink_usb_exit_dfu_mode(stlink_t* sl) { @@ -510,14 +491,9 @@ int _stlink_usb_exit_dfu_mode(stlink_t* sl) { cmd[i++] = STLINK_DFU_COMMAND; cmd[i++] = STLINK_DFU_EXIT; - size = send_only(slu, 1, cmd, slu->cmd_len); + size = send_only(slu, 1, cmd, slu->cmd_len, "DFU_EXIT"); - if (size == -1) { - printf("[!] send_recv STLINK_DFU_EXIT\n"); - return((int)size); - } - - return(0); + return(size<0?-1:0); } @@ -538,13 +514,9 @@ int _stlink_usb_reset(stlink_t * sl) { cmd[i++] = STLINK_DEBUG_APIV2_RESETSYS; } - size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, true, CMD_USE_RETRY); - - if (size < 0) { - return((int)size); - } + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_RETRY, "RESETSYS"); - return(0); + return(size<0?-1:0); } int _stlink_usb_jtag_reset(stlink_t * sl, int value) { @@ -558,13 +530,9 @@ int _stlink_usb_jtag_reset(stlink_t * sl, int value) { cmd[i++] = STLINK_DEBUG_COMMAND; cmd[i++] = STLINK_DEBUG_APIV2_DRIVE_NRST; cmd[i++] = value; - size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, true, CMD_USE_RETRY); + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_RETRY, "DRIVE_NRST"); - if (size < 0) { - return((int)size); - } - - return(0); + return(size<0?-1:0); } @@ -589,13 +557,9 @@ int _stlink_usb_step(stlink_t* sl) { cmd[i++] = STLINK_DEBUG_COMMAND; cmd[i++] = STLINK_DEBUG_STEPCORE; - size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, true, CMD_USE_RETRY); + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_RETRY, "STEPCORE"); - if (size < 0) { - return((int)size); - } - - return(0); + return(size<0?-1:0); } /** @@ -624,13 +588,9 @@ int _stlink_usb_run(stlink_t* sl, enum run_type type) { cmd[i++] = STLINK_DEBUG_COMMAND; cmd[i++] = STLINK_DEBUG_RUNCORE; - size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, true, CMD_USE_RETRY); - - if (size < 0) { - return((int)size); - } + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_RETRY, "RUNCORE"); - return(0); + return(size<0?-1:0); } int _stlink_usb_set_swdclk(stlink_t* sl, int clk_freq) { @@ -671,13 +631,9 @@ int _stlink_usb_set_swdclk(stlink_t* sl, int clk_freq) { cmd[i++] = STLINK_DEBUG_APIV2_SWD_SET_FREQ; cmd[i++] = clk_divisor & 0xFF; cmd[i++] = (clk_divisor >> 8) & 0xFF; - size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, true, CMD_USE_RETRY); - - if (size < 0) { - return((int)size); - } + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_RETRY, "SWD_SET_FREQ"); - return(0); + return(size<0?-1:0); } else if (sl->version.stlink_v == 3) { int speed_index; uint32_t map[STLINK_V3_MAX_FREQ_NB]; @@ -686,10 +642,10 @@ int _stlink_usb_set_swdclk(stlink_t* sl, int clk_freq) { cmd[i++] = STLINK_DEBUG_COMMAND; cmd[i++] = STLINK_DEBUG_APIV3_GET_COM_FREQ; cmd[i++] = 0; // SWD mode - size = send_recv(slu, 1, cmd, slu->cmd_len, data, 52, true, CMD_NO_RETRY); + size = send_recv(slu, 1, cmd, slu->cmd_len, data, 52, CMD_CHECK_STATUS, "GET_COM_FREQ"); if (size < 0) { - return((int)size); + return(-1); } int speeds_size = data[8]; @@ -716,13 +672,9 @@ int _stlink_usb_set_swdclk(stlink_t* sl, int clk_freq) { cmd[i++] = (uint8_t)((map[speed_index] >> 16) & 0xFF); cmd[i++] = (uint8_t)((map[speed_index] >> 24) & 0xFF); - size = send_recv(slu, 1, cmd, slu->cmd_len, data, 8, true, CMD_NO_RETRY); - - if (size < 0) { - return((int)size); - } + size = send_recv(slu, 1, cmd, slu->cmd_len, data, 8, CMD_CHECK_STATUS, "SET_COM_FREQ"); - return(0); + return(size<0?-1:0); } else if (clk_freq) { WLOG("ST-Link firmware does not support frequency setup\n"); } @@ -739,14 +691,9 @@ int _stlink_usb_exit_debug_mode(stlink_t *sl) { cmd[i++] = STLINK_DEBUG_COMMAND; cmd[i++] = STLINK_DEBUG_EXIT; - size = send_only(slu, 1, cmd, slu->cmd_len); - - if (size == -1) { - printf("[!] send_only STLINK_DEBUG_EXIT\n"); - return((int)size); - } + size = send_only(slu, 1, cmd, slu->cmd_len, "DEBUG_EXIT"); - return(0); + return(size<0?-1:0); } int _stlink_usb_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { @@ -760,10 +707,10 @@ int _stlink_usb_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { cmd[i++] = STLINK_DEBUG_READMEM_32BIT; write_uint32(&cmd[i], addr); write_uint16(&cmd[i + 4], len); - size = send_recv(slu, 1, cmd, slu->cmd_len, data, len, false, CMD_NO_RETRY); + size = send_recv(slu, 1, cmd, slu->cmd_len, data, len, CMD_CHECK_NO, "READMEM_32BIT"); if (size < 0) { - return((int)size); + return(-1); } sl->q_len = (int)size; @@ -788,10 +735,10 @@ int _stlink_usb_read_all_regs(stlink_t *sl, struct stlink_reg *regp) { cmd[i++] = STLINK_DEBUG_APIV2_READALLREGS; } - size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, true, CMD_NO_RETRY); + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_STATUS, "READALLREGS"); if (size < 0) { - return((int)size); + return(-1); } /* V1: regs data from offset 0 */ @@ -838,10 +785,10 @@ int _stlink_usb_read_reg(stlink_t *sl, int r_idx, struct stlink_reg *regp) { } cmd[i++] = (uint8_t)r_idx; - size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, true, CMD_USE_RETRY); + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_RETRY, "READREG"); if (size < 0) { - return((int)size); + return(-1); } sl->q_len = (int)size; @@ -1004,16 +951,9 @@ int _stlink_usb_write_reg(stlink_t *sl, uint32_t reg, int idx) { cmd[i++] = idx; write_uint32(&cmd[i], reg); - size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, true, CMD_USE_RETRY); - - if (size < 0) { - return((int)size); - } + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_RETRY, "WRITEREG"); - sl->q_len = (int)size; - stlink_print_data(sl); - - return(0); + return(size<0?-1:0); } int _stlink_usb_enable_trace(stlink_t* sl, uint32_t frequency) { @@ -1029,16 +969,9 @@ int _stlink_usb_enable_trace(stlink_t* sl, uint32_t frequency) { write_uint16(&cmd[i + 0], 2 * STLINK_TRACE_BUF_LEN); write_uint32(&cmd[i + 2], frequency); - size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, true, CMD_NO_RETRY); + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_STATUS, "START_TRACE_RX"); - if (size < 0) { - return((int)size); - } - - sl->q_len = (int)size; - stlink_print_data(sl); - - return(0); + return(size<0?-1:0); } int _stlink_usb_disable_trace(stlink_t* sl) { @@ -1052,16 +985,9 @@ int _stlink_usb_disable_trace(stlink_t* sl) { cmd[i++] = STLINK_DEBUG_COMMAND; cmd[i++] = STLINK_DEBUG_APIV2_STOP_TRACE_RX; - size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, true, CMD_NO_RETRY); + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_STATUS, "STOP_TRACE_RX"); - if (size < 0) { - return((int)size); - } - - sl->q_len = (int)size; - stlink_print_data(sl); - - return(0); + return(size<0?-1:0); } int _stlink_usb_read_trace(stlink_t* sl, uint8_t* buf, size_t size) { @@ -1073,13 +999,13 @@ int _stlink_usb_read_trace(stlink_t* sl, uint8_t* buf, size_t size) { cmd[i++] = STLINK_DEBUG_COMMAND; cmd[i++] = STLINK_DEBUG_APIV2_GET_TRACE_NB; - ssize_t send_size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, false, CMD_NO_RETRY); + ssize_t send_size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_NO, "GET_TRACE_NB"); if (send_size < 0) { - return((int)send_size); + return(-1); } else if (send_size != 2) { ELOG("STLINK_DEBUG_APIV2_GET_TRACE_NB reply size %d\n", (int)send_size); - return -1; + return(-1); } uint16_t trace_count = read_uint16(sl->q_buf, 0); From 90887edb2eef946d3bd0bda7769a95c076667f7b Mon Sep 17 00:00:00 2001 From: "R.E. Wolff" Date: Sun, 23 May 2021 08:42:36 +0200 Subject: [PATCH 272/503] removed debug dump --- src/stlink-lib/chipid.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index 51da33322..02f117416 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -806,6 +806,7 @@ struct stlink_chipid_params *stlink_chipid_get_params(uint32_t chipid) { p2 = stlink_chipid_get_params_old (chipid); +#if 1 if (memcmp (p2, params, sizeof (struct stlink_chipid_params) - sizeof (struct stlink_chipid_params *)) != 0) { //fprintf (stderr, "Error, chipid params not identical\n"); //return NULL; @@ -814,6 +815,7 @@ struct stlink_chipid_params *stlink_chipid_get_params(uint32_t chipid) { fprintf (stderr, "---------- new ------------\n"); dump_a_chip (stderr, params); } +#endif return(params); } From d5b901b89957641a46ef4865620f989bf94e01d6 Mon Sep 17 00:00:00 2001 From: "R.E. Wolff" Date: Sun, 23 May 2021 08:52:36 +0200 Subject: [PATCH 273/503] removed filename-spaces --- config/chips/{F0xx small.chip => F0xx_small.chip} | 0 config/chips/{F1 XL-density.chip => F1_XL-density.chip} | 0 .../{F1 connectivity line.chip => F1_connectivity_line.chip} | 0 config/chips/{F1 high-density.chip => F1_high-density.chip} | 0 config/chips/{F1 low-density.chip => F1_low-density.chip} | 0 config/chips/{F1 medium-density.chip => F1_medium-density.chip} | 0 config/chips/{F1 value line.chip => F1_value_line.chip} | 0 ...lue line high-density.chip => F1_value_line_high-density.chip} | 0 config/chips/{F303 high density.chip => F303_high_density.chip} | 0 .../chips/{F334 medium density.chip => F334_medium_density.chip} | 0 ...{F4xx dynamic efficiency.chip => F4xx_dynamic_efficiency.chip} | 0 config/chips/{F4xx low power.chip => F4xx_low_power.chip} | 0 config/chips/{G4 cat2.chip => G4_cat2.chip} | 0 config/chips/{G4 cat3.chip => G4_cat3.chip} | 0 config/chips/{L0xx cat2.chip => L0xx_cat2.chip} | 0 config/chips/{L0xx cat5.chip => L0xx_cat5.chip} | 0 config/chips/{L1xx cat2.chip => L1xx_cat2.chip} | 0 config/chips/{L1xx high-density.chip => L1xx_high-density.chip} | 0 .../chips/{L1xx medium-density.chip => L1xx_medium-density.chip} | 0 ...1xx medium-plus-density.chip => L1xx_medium-plus-density.chip} | 0 config/chips/{unknown device.chip => unknown_device.chip} | 0 21 files changed, 0 insertions(+), 0 deletions(-) rename config/chips/{F0xx small.chip => F0xx_small.chip} (100%) rename config/chips/{F1 XL-density.chip => F1_XL-density.chip} (100%) rename config/chips/{F1 connectivity line.chip => F1_connectivity_line.chip} (100%) rename config/chips/{F1 high-density.chip => F1_high-density.chip} (100%) rename config/chips/{F1 low-density.chip => F1_low-density.chip} (100%) rename config/chips/{F1 medium-density.chip => F1_medium-density.chip} (100%) rename config/chips/{F1 value line.chip => F1_value_line.chip} (100%) rename config/chips/{F1 value line high-density.chip => F1_value_line_high-density.chip} (100%) rename config/chips/{F303 high density.chip => F303_high_density.chip} (100%) rename config/chips/{F334 medium density.chip => F334_medium_density.chip} (100%) rename config/chips/{F4xx dynamic efficiency.chip => F4xx_dynamic_efficiency.chip} (100%) rename config/chips/{F4xx low power.chip => F4xx_low_power.chip} (100%) rename config/chips/{G4 cat2.chip => G4_cat2.chip} (100%) rename config/chips/{G4 cat3.chip => G4_cat3.chip} (100%) rename config/chips/{L0xx cat2.chip => L0xx_cat2.chip} (100%) rename config/chips/{L0xx cat5.chip => L0xx_cat5.chip} (100%) rename config/chips/{L1xx cat2.chip => L1xx_cat2.chip} (100%) rename config/chips/{L1xx high-density.chip => L1xx_high-density.chip} (100%) rename config/chips/{L1xx medium-density.chip => L1xx_medium-density.chip} (100%) rename config/chips/{L1xx medium-plus-density.chip => L1xx_medium-plus-density.chip} (100%) rename config/chips/{unknown device.chip => unknown_device.chip} (100%) diff --git a/config/chips/F0xx small.chip b/config/chips/F0xx_small.chip similarity index 100% rename from config/chips/F0xx small.chip rename to config/chips/F0xx_small.chip diff --git a/config/chips/F1 XL-density.chip b/config/chips/F1_XL-density.chip similarity index 100% rename from config/chips/F1 XL-density.chip rename to config/chips/F1_XL-density.chip diff --git a/config/chips/F1 connectivity line.chip b/config/chips/F1_connectivity_line.chip similarity index 100% rename from config/chips/F1 connectivity line.chip rename to config/chips/F1_connectivity_line.chip diff --git a/config/chips/F1 high-density.chip b/config/chips/F1_high-density.chip similarity index 100% rename from config/chips/F1 high-density.chip rename to config/chips/F1_high-density.chip diff --git a/config/chips/F1 low-density.chip b/config/chips/F1_low-density.chip similarity index 100% rename from config/chips/F1 low-density.chip rename to config/chips/F1_low-density.chip diff --git a/config/chips/F1 medium-density.chip b/config/chips/F1_medium-density.chip similarity index 100% rename from config/chips/F1 medium-density.chip rename to config/chips/F1_medium-density.chip diff --git a/config/chips/F1 value line.chip b/config/chips/F1_value_line.chip similarity index 100% rename from config/chips/F1 value line.chip rename to config/chips/F1_value_line.chip diff --git a/config/chips/F1 value line high-density.chip b/config/chips/F1_value_line_high-density.chip similarity index 100% rename from config/chips/F1 value line high-density.chip rename to config/chips/F1_value_line_high-density.chip diff --git a/config/chips/F303 high density.chip b/config/chips/F303_high_density.chip similarity index 100% rename from config/chips/F303 high density.chip rename to config/chips/F303_high_density.chip diff --git a/config/chips/F334 medium density.chip b/config/chips/F334_medium_density.chip similarity index 100% rename from config/chips/F334 medium density.chip rename to config/chips/F334_medium_density.chip diff --git a/config/chips/F4xx dynamic efficiency.chip b/config/chips/F4xx_dynamic_efficiency.chip similarity index 100% rename from config/chips/F4xx dynamic efficiency.chip rename to config/chips/F4xx_dynamic_efficiency.chip diff --git a/config/chips/F4xx low power.chip b/config/chips/F4xx_low_power.chip similarity index 100% rename from config/chips/F4xx low power.chip rename to config/chips/F4xx_low_power.chip diff --git a/config/chips/G4 cat2.chip b/config/chips/G4_cat2.chip similarity index 100% rename from config/chips/G4 cat2.chip rename to config/chips/G4_cat2.chip diff --git a/config/chips/G4 cat3.chip b/config/chips/G4_cat3.chip similarity index 100% rename from config/chips/G4 cat3.chip rename to config/chips/G4_cat3.chip diff --git a/config/chips/L0xx cat2.chip b/config/chips/L0xx_cat2.chip similarity index 100% rename from config/chips/L0xx cat2.chip rename to config/chips/L0xx_cat2.chip diff --git a/config/chips/L0xx cat5.chip b/config/chips/L0xx_cat5.chip similarity index 100% rename from config/chips/L0xx cat5.chip rename to config/chips/L0xx_cat5.chip diff --git a/config/chips/L1xx cat2.chip b/config/chips/L1xx_cat2.chip similarity index 100% rename from config/chips/L1xx cat2.chip rename to config/chips/L1xx_cat2.chip diff --git a/config/chips/L1xx high-density.chip b/config/chips/L1xx_high-density.chip similarity index 100% rename from config/chips/L1xx high-density.chip rename to config/chips/L1xx_high-density.chip diff --git a/config/chips/L1xx medium-density.chip b/config/chips/L1xx_medium-density.chip similarity index 100% rename from config/chips/L1xx medium-density.chip rename to config/chips/L1xx_medium-density.chip diff --git a/config/chips/L1xx medium-plus-density.chip b/config/chips/L1xx_medium-plus-density.chip similarity index 100% rename from config/chips/L1xx medium-plus-density.chip rename to config/chips/L1xx_medium-plus-density.chip diff --git a/config/chips/unknown device.chip b/config/chips/unknown_device.chip similarity index 100% rename from config/chips/unknown device.chip rename to config/chips/unknown_device.chip From 157c587b93fb8e0f46696610b6f78d4a24609ef9 Mon Sep 17 00:00:00 2001 From: "R.E. Wolff" Date: Sun, 23 May 2021 10:50:43 +0200 Subject: [PATCH 274/503] cleanup integer handling in chipid and text flags --- config/chips/F04x.chip | 14 ++--- config/chips/F07x.chip | 14 ++--- config/chips/F09x.chip | 14 ++--- config/chips/F0xx.chip | 14 ++--- config/chips/F0xx_small.chip | 14 ++--- config/chips/F1_XL-density.chip | 14 ++--- config/chips/F1_connectivity_line.chip | 14 ++--- config/chips/F1_high-density.chip | 14 ++--- config/chips/F1_low-density.chip | 14 ++--- config/chips/F1_medium-density.chip | 14 ++--- config/chips/F1_value_line.chip | 14 ++--- config/chips/F1_value_line_high-density.chip | 14 ++--- config/chips/F2.chip | 14 ++--- config/chips/F303_high_density.chip | 14 ++--- config/chips/F334_medium_density.chip | 14 ++--- config/chips/F37x.chip | 14 ++--- config/chips/F3xx_small.chip | 14 ++--- config/chips/F410.chip | 14 ++--- config/chips/F411xx.chip | 14 ++--- config/chips/F412.chip | 14 ++--- config/chips/F413.chip | 14 ++--- config/chips/F42x_F43x.chip | 14 ++--- config/chips/F446.chip | 14 ++--- config/chips/F46x_F47x.chip | 14 ++--- config/chips/F4xx.chip | 14 ++--- config/chips/F4xx_dynamic_efficiency.chip | 14 ++--- config/chips/F4xx_low_power.chip | 14 ++--- config/chips/F72x_F73x.chip | 14 ++--- config/chips/F76xxx.chip | 14 ++--- config/chips/F7xx.chip | 14 ++--- config/chips/G030_G031_G041.chip | 14 ++--- config/chips/G070_G071_G081.chip | 14 ++--- config/chips/G4_cat2.chip | 14 ++--- config/chips/G4_cat3.chip | 14 ++--- config/chips/H72x_H73x.chip | 16 +++--- config/chips/H74x_H75x.chip | 16 +++--- config/chips/H7Ax_H7Bx.chip | 16 +++--- config/chips/L011.chip | 14 ++--- config/chips/L0x3.chip | 16 +++--- config/chips/L0xx_cat2.chip | 14 ++--- config/chips/L0xx_cat5.chip | 14 ++--- config/chips/L152RE.chip | 14 ++--- config/chips/L1xx_cat2.chip | 14 ++--- config/chips/L1xx_high-density.chip | 14 ++--- config/chips/L1xx_medium-density.chip | 14 ++--- config/chips/L1xx_medium-plus-density.chip | 14 ++--- config/chips/L41x.chip | 14 ++--- config/chips/L43x_L44x.chip | 14 ++--- config/chips/L45x_L46x.chip | 14 ++--- config/chips/L496x_L4A6x.chip | 14 ++--- config/chips/L4Rx.chip | 14 ++--- config/chips/L4xx.chip | 14 ++--- config/chips/WB55.chip | 14 ++--- config/chips/unknown_device.chip | 14 ++--- src/stlink-lib/chipid.c | 56 +++++++++++++------- 55 files changed, 418 insertions(+), 402 deletions(-) diff --git a/config/chips/F04x.chip b/config/chips/F04x.chip index 059ae5bc6..b42d420fa 100644 --- a/config/chips/F04x.chip +++ b/config/chips/F04x.chip @@ -1,13 +1,13 @@ # Chip-ID file for F04x # -chip_id 445 +chip_id 0x445 description F04x flash_type 1 flash_pagesize 400 -sram_size 1800 -bootrom_base 1fffec00 -bootrom_size c00 -option_base 0 -option_size 0 -flags 0 +sram_size 0x1800 +bootrom_base 0x1fffec00 +bootrom_size 0xc00 +option_base 0x0 +option_size 0x0 +flags none diff --git a/config/chips/F07x.chip b/config/chips/F07x.chip index ba839baed..d8c71f0ea 100644 --- a/config/chips/F07x.chip +++ b/config/chips/F07x.chip @@ -1,13 +1,13 @@ # Chip-ID file for F07x # -chip_id 448 +chip_id 0x448 description F07x flash_type 1 flash_pagesize 800 -sram_size 4000 -bootrom_base 1fffc800 -bootrom_size 3000 -option_base 0 -option_size 0 -flags 0 +sram_size 0x4000 +bootrom_base 0x1fffc800 +bootrom_size 0x3000 +option_base 0x0 +option_size 0x0 +flags none diff --git a/config/chips/F09x.chip b/config/chips/F09x.chip index 727fc1fa4..ca97d53e4 100644 --- a/config/chips/F09x.chip +++ b/config/chips/F09x.chip @@ -1,13 +1,13 @@ # Chip-ID file for F09x # -chip_id 442 +chip_id 0x442 description F09x flash_type 1 flash_pagesize 800 -sram_size 8000 -bootrom_base 1fffd800 -bootrom_size 2000 -option_base 0 -option_size 0 -flags 0 +sram_size 0x8000 +bootrom_base 0x1fffd800 +bootrom_size 0x2000 +option_base 0x0 +option_size 0x0 +flags none diff --git a/config/chips/F0xx.chip b/config/chips/F0xx.chip index 9c0f60bd9..a1700eef3 100644 --- a/config/chips/F0xx.chip +++ b/config/chips/F0xx.chip @@ -1,13 +1,13 @@ # Chip-ID file for F0xx # -chip_id 440 +chip_id 0x440 description F0xx flash_type 1 flash_pagesize 400 -sram_size 2000 -bootrom_base 1fffec00 -bootrom_size c00 -option_base 0 -option_size 0 -flags 0 +sram_size 0x2000 +bootrom_base 0x1fffec00 +bootrom_size 0xc00 +option_base 0x0 +option_size 0x0 +flags none diff --git a/config/chips/F0xx_small.chip b/config/chips/F0xx_small.chip index efa51c284..3ab256feb 100644 --- a/config/chips/F0xx_small.chip +++ b/config/chips/F0xx_small.chip @@ -1,13 +1,13 @@ # Chip-ID file for F0xx small # -chip_id 444 +chip_id 0x444 description F0xx small flash_type 1 flash_pagesize 400 -sram_size 1000 -bootrom_base 1fffec00 -bootrom_size c00 -option_base 0 -option_size 0 -flags 0 +sram_size 0x1000 +bootrom_base 0x1fffec00 +bootrom_size 0xc00 +option_base 0x0 +option_size 0x0 +flags none diff --git a/config/chips/F1_XL-density.chip b/config/chips/F1_XL-density.chip index 70cdfd3bb..97bb580e3 100644 --- a/config/chips/F1_XL-density.chip +++ b/config/chips/F1_XL-density.chip @@ -1,13 +1,13 @@ # Chip-ID file for F1 XL-density # -chip_id 430 +chip_id 0x430 description F1 XL-density flash_type 2 flash_pagesize 800 -sram_size 18000 -bootrom_base 1fffe000 -bootrom_size 1800 -option_base 0 -option_size 0 -flags 2 +sram_size 0x18000 +bootrom_base 0x1fffe000 +bootrom_size 0x1800 +option_base 0x0 +option_size 0x0 +flags swo diff --git a/config/chips/F1_connectivity_line.chip b/config/chips/F1_connectivity_line.chip index 14678112d..a030fd58d 100644 --- a/config/chips/F1_connectivity_line.chip +++ b/config/chips/F1_connectivity_line.chip @@ -1,13 +1,13 @@ # Chip-ID file for F1 connectivity line # -chip_id 418 +chip_id 0x418 description F1 connectivity line flash_type 1 flash_pagesize 800 -sram_size 10000 -bootrom_base 1fffb000 -bootrom_size 4800 -option_base 0 -option_size 0 -flags 2 +sram_size 0x10000 +bootrom_base 0x1fffb000 +bootrom_size 0x4800 +option_base 0x0 +option_size 0x0 +flags swo diff --git a/config/chips/F1_high-density.chip b/config/chips/F1_high-density.chip index 3d4cff724..00e4942b0 100644 --- a/config/chips/F1_high-density.chip +++ b/config/chips/F1_high-density.chip @@ -1,13 +1,13 @@ # Chip-ID file for F1 high-density # -chip_id 414 +chip_id 0x414 description F1 high-density flash_type 1 flash_pagesize 800 -sram_size 10000 -bootrom_base 1ffff000 -bootrom_size 800 -option_base 0 -option_size 0 -flags 2 +sram_size 0x10000 +bootrom_base 0x1ffff000 +bootrom_size 0x800 +option_base 0x0 +option_size 0x0 +flags swo diff --git a/config/chips/F1_low-density.chip b/config/chips/F1_low-density.chip index 9905ce405..1562c7589 100644 --- a/config/chips/F1_low-density.chip +++ b/config/chips/F1_low-density.chip @@ -1,13 +1,13 @@ # Chip-ID file for F1 low-density # -chip_id 412 +chip_id 0x412 description F1 low-density flash_type 1 flash_pagesize 400 -sram_size 2800 -bootrom_base 1ffff000 -bootrom_size 800 -option_base 0 -option_size 0 -flags 2 +sram_size 0x2800 +bootrom_base 0x1ffff000 +bootrom_size 0x800 +option_base 0x0 +option_size 0x0 +flags swo diff --git a/config/chips/F1_medium-density.chip b/config/chips/F1_medium-density.chip index 00af4f18d..1f3d89234 100644 --- a/config/chips/F1_medium-density.chip +++ b/config/chips/F1_medium-density.chip @@ -1,13 +1,13 @@ # Chip-ID file for F1 medium-density # -chip_id 410 +chip_id 0x410 description F1 medium-density flash_type 1 flash_pagesize 400 -sram_size 5000 -bootrom_base 1ffff000 -bootrom_size 800 -option_base 0 -option_size 0 -flags 2 +sram_size 0x5000 +bootrom_base 0x1ffff000 +bootrom_size 0x800 +option_base 0x0 +option_size 0x0 +flags swo diff --git a/config/chips/F1_value_line.chip b/config/chips/F1_value_line.chip index 8356357b0..d9f04f00a 100644 --- a/config/chips/F1_value_line.chip +++ b/config/chips/F1_value_line.chip @@ -1,13 +1,13 @@ # Chip-ID file for F1 value line # -chip_id 420 +chip_id 0x420 description F1 value line flash_type 1 flash_pagesize 400 -sram_size 2000 -bootrom_base 1ffff000 -bootrom_size 800 -option_base 0 -option_size 0 -flags 2 +sram_size 0x2000 +bootrom_base 0x1ffff000 +bootrom_size 0x800 +option_base 0x0 +option_size 0x0 +flags swo diff --git a/config/chips/F1_value_line_high-density.chip b/config/chips/F1_value_line_high-density.chip index c076e284c..2ecf6b4f5 100644 --- a/config/chips/F1_value_line_high-density.chip +++ b/config/chips/F1_value_line_high-density.chip @@ -1,13 +1,13 @@ # Chip-ID file for F1 value line high-density # -chip_id 428 +chip_id 0x428 description F1 value line high-density flash_type 1 flash_pagesize 800 -sram_size 8000 -bootrom_base 1ffff000 -bootrom_size 800 -option_base 0 -option_size 0 -flags 2 +sram_size 0x8000 +bootrom_base 0x1ffff000 +bootrom_size 0x800 +option_base 0x0 +option_size 0x0 +flags swo diff --git a/config/chips/F2.chip b/config/chips/F2.chip index 8830363d2..098ddc863 100644 --- a/config/chips/F2.chip +++ b/config/chips/F2.chip @@ -1,13 +1,13 @@ # Chip-ID file for F2 # -chip_id 411 +chip_id 0x411 description F2 flash_type 3 flash_pagesize 20000 -sram_size 20000 -bootrom_base 1fff0000 -bootrom_size 7800 -option_base 1fffc000 -option_size 4 -flags 2 +sram_size 0x20000 +bootrom_base 0x1fff0000 +bootrom_size 0x7800 +option_base 0x1fffc000 +option_size 0x4 +flags swo diff --git a/config/chips/F303_high_density.chip b/config/chips/F303_high_density.chip index e8b57ee24..19cc2ad2a 100644 --- a/config/chips/F303_high_density.chip +++ b/config/chips/F303_high_density.chip @@ -1,13 +1,13 @@ # Chip-ID file for F303 high density # -chip_id 446 +chip_id 0x446 description F303 high density flash_type 1 flash_pagesize 800 -sram_size 10000 -bootrom_base 1fffd800 -bootrom_size 2000 -option_base 0 -option_size 0 -flags 2 +sram_size 0x10000 +bootrom_base 0x1fffd800 +bootrom_size 0x2000 +option_base 0x0 +option_size 0x0 +flags swo diff --git a/config/chips/F334_medium_density.chip b/config/chips/F334_medium_density.chip index 460e22a67..ba4cf9688 100644 --- a/config/chips/F334_medium_density.chip +++ b/config/chips/F334_medium_density.chip @@ -1,13 +1,13 @@ # Chip-ID file for F334 medium density # -chip_id 438 +chip_id 0x438 description F334 medium density flash_type 1 flash_pagesize 800 -sram_size 3000 -bootrom_base 1fffd800 -bootrom_size 2000 -option_base 0 -option_size 0 -flags 2 +sram_size 0x3000 +bootrom_base 0x1fffd800 +bootrom_size 0x2000 +option_base 0x0 +option_size 0x0 +flags swo diff --git a/config/chips/F37x.chip b/config/chips/F37x.chip index 424209a03..d0081e68a 100644 --- a/config/chips/F37x.chip +++ b/config/chips/F37x.chip @@ -1,13 +1,13 @@ # Chip-ID file for F37x # -chip_id 432 +chip_id 0x432 description F37x flash_type 1 flash_pagesize 800 -sram_size a000 -bootrom_base 1ffff000 -bootrom_size 800 -option_base 0 -option_size 0 -flags 2 +sram_size 0xa000 +bootrom_base 0x1ffff000 +bootrom_size 0x800 +option_base 0x0 +option_size 0x0 +flags swo diff --git a/config/chips/F3xx_small.chip b/config/chips/F3xx_small.chip index 91722905c..34d1940ac 100644 --- a/config/chips/F3xx_small.chip +++ b/config/chips/F3xx_small.chip @@ -1,13 +1,13 @@ # Chip-ID file for F3xx small # -chip_id 439 +chip_id 0x439 description F3xx small flash_type 1 flash_pagesize 800 -sram_size a000 -bootrom_base 1fffd800 -bootrom_size 2000 -option_base 0 -option_size 0 -flags 2 +sram_size 0xa000 +bootrom_base 0x1fffd800 +bootrom_size 0x2000 +option_base 0x0 +option_size 0x0 +flags swo diff --git a/config/chips/F410.chip b/config/chips/F410.chip index 53f01c669..3cd382845 100644 --- a/config/chips/F410.chip +++ b/config/chips/F410.chip @@ -1,13 +1,13 @@ # Chip-ID file for F410 # -chip_id 458 +chip_id 0x458 description F410 flash_type 3 flash_pagesize 4000 -sram_size 8000 -bootrom_base 1fff0000 -bootrom_size 7800 -option_base 0 -option_size 0 -flags 2 +sram_size 0x8000 +bootrom_base 0x1fff0000 +bootrom_size 0x7800 +option_base 0x0 +option_size 0x0 +flags swo diff --git a/config/chips/F411xx.chip b/config/chips/F411xx.chip index 26390d0e6..301e6cb91 100644 --- a/config/chips/F411xx.chip +++ b/config/chips/F411xx.chip @@ -1,13 +1,13 @@ # Chip-ID file for F411xx # -chip_id 431 +chip_id 0x431 description F411xx flash_type 3 flash_pagesize 4000 -sram_size 20000 -bootrom_base 1fff0000 -bootrom_size 7800 -option_base 0 -option_size 0 -flags 2 +sram_size 0x20000 +bootrom_base 0x1fff0000 +bootrom_size 0x7800 +option_base 0x0 +option_size 0x0 +flags swo diff --git a/config/chips/F412.chip b/config/chips/F412.chip index e78b81ee1..186a43427 100644 --- a/config/chips/F412.chip +++ b/config/chips/F412.chip @@ -1,13 +1,13 @@ # Chip-ID file for F412 # -chip_id 441 +chip_id 0x441 description F412 flash_type 3 flash_pagesize 4000 -sram_size 40000 -bootrom_base 1fff0000 -bootrom_size 7800 -option_base 0 -option_size 0 -flags 2 +sram_size 0x40000 +bootrom_base 0x1fff0000 +bootrom_size 0x7800 +option_base 0x0 +option_size 0x0 +flags swo diff --git a/config/chips/F413.chip b/config/chips/F413.chip index 4ea974f2c..367344aaa 100644 --- a/config/chips/F413.chip +++ b/config/chips/F413.chip @@ -1,13 +1,13 @@ # Chip-ID file for F413 # -chip_id 463 +chip_id 0x463 description F413 flash_type 3 flash_pagesize 4000 -sram_size 50000 -bootrom_base 1fff0000 -bootrom_size 7800 -option_base 0 -option_size 0 -flags 2 +sram_size 0x50000 +bootrom_base 0x1fff0000 +bootrom_size 0x7800 +option_base 0x0 +option_size 0x0 +flags swo diff --git a/config/chips/F42x_F43x.chip b/config/chips/F42x_F43x.chip index 2073486cf..4557a731c 100644 --- a/config/chips/F42x_F43x.chip +++ b/config/chips/F42x_F43x.chip @@ -1,13 +1,13 @@ # Chip-ID file for F42x/F43x # -chip_id 419 +chip_id 0x419 description F42x/F43x flash_type 3 flash_pagesize 4000 -sram_size 40000 -bootrom_base 1fff0000 -bootrom_size 7800 -option_base 0 -option_size 0 -flags 2 +sram_size 0x40000 +bootrom_base 0x1fff0000 +bootrom_size 0x7800 +option_base 0x0 +option_size 0x0 +flags swo diff --git a/config/chips/F446.chip b/config/chips/F446.chip index 7d2ded465..9f7ae0bc5 100644 --- a/config/chips/F446.chip +++ b/config/chips/F446.chip @@ -1,13 +1,13 @@ # Chip-ID file for F446 # -chip_id 421 +chip_id 0x421 description F446 flash_type 3 flash_pagesize 20000 -sram_size 20000 -bootrom_base 1fff0000 -bootrom_size 7800 -option_base 1fffc000 -option_size 4 -flags 2 +sram_size 0x20000 +bootrom_base 0x1fff0000 +bootrom_size 0x7800 +option_base 0x1fffc000 +option_size 0x4 +flags swo diff --git a/config/chips/F46x_F47x.chip b/config/chips/F46x_F47x.chip index 75e1ea045..8ae43eb2e 100644 --- a/config/chips/F46x_F47x.chip +++ b/config/chips/F46x_F47x.chip @@ -1,13 +1,13 @@ # Chip-ID file for F46x/F47x # -chip_id 434 +chip_id 0x434 description F46x/F47x flash_type 3 flash_pagesize 4000 -sram_size 40000 -bootrom_base 1fff0000 -bootrom_size 7800 -option_base 0 -option_size 0 -flags 2 +sram_size 0x40000 +bootrom_base 0x1fff0000 +bootrom_size 0x7800 +option_base 0x0 +option_size 0x0 +flags swo diff --git a/config/chips/F4xx.chip b/config/chips/F4xx.chip index 70f298b79..17ec62d68 100644 --- a/config/chips/F4xx.chip +++ b/config/chips/F4xx.chip @@ -1,13 +1,13 @@ # Chip-ID file for F4xx # -chip_id 413 +chip_id 0x413 description F4xx flash_type 3 flash_pagesize 4000 -sram_size 30000 -bootrom_base 1fff0000 -bootrom_size 7800 -option_base 40023c14 -option_size 4 -flags 2 +sram_size 0x30000 +bootrom_base 0x1fff0000 +bootrom_size 0x7800 +option_base 0x40023c14 +option_size 0x4 +flags swo diff --git a/config/chips/F4xx_dynamic_efficiency.chip b/config/chips/F4xx_dynamic_efficiency.chip index 33bfa23c2..6d06bcb8e 100644 --- a/config/chips/F4xx_dynamic_efficiency.chip +++ b/config/chips/F4xx_dynamic_efficiency.chip @@ -1,13 +1,13 @@ # Chip-ID file for F4xx dynamic efficiency # -chip_id 433 +chip_id 0x433 description F4xx dynamic efficiency flash_type 3 flash_pagesize 4000 -sram_size 18000 -bootrom_base 1fff0000 -bootrom_size 7800 -option_base 0 -option_size 0 -flags 2 +sram_size 0x18000 +bootrom_base 0x1fff0000 +bootrom_size 0x7800 +option_base 0x0 +option_size 0x0 +flags swo diff --git a/config/chips/F4xx_low_power.chip b/config/chips/F4xx_low_power.chip index f52595d5d..ad8c3ce90 100644 --- a/config/chips/F4xx_low_power.chip +++ b/config/chips/F4xx_low_power.chip @@ -1,13 +1,13 @@ # Chip-ID file for F4xx low power # -chip_id 423 +chip_id 0x423 description F4xx low power flash_type 3 flash_pagesize 4000 -sram_size 10000 -bootrom_base 1fff0000 -bootrom_size 7800 -option_base 0 -option_size 0 -flags 2 +sram_size 0x10000 +bootrom_base 0x1fff0000 +bootrom_size 0x7800 +option_base 0x0 +option_size 0x0 +flags swo diff --git a/config/chips/F72x_F73x.chip b/config/chips/F72x_F73x.chip index ba275bb0b..b6f706994 100644 --- a/config/chips/F72x_F73x.chip +++ b/config/chips/F72x_F73x.chip @@ -1,13 +1,13 @@ # Chip-ID file for F72x/F73x # -chip_id 452 +chip_id 0x452 description F72x/F73x flash_type 3 flash_pagesize 800 -sram_size 40000 -bootrom_base 100000 -bootrom_size edc0 -option_base 0 -option_size 0 -flags 2 +sram_size 0x40000 +bootrom_base 0x100000 +bootrom_size 0xedc0 +option_base 0x0 +option_size 0x0 +flags swo diff --git a/config/chips/F76xxx.chip b/config/chips/F76xxx.chip index 7f8cfdaf0..49ac1ec21 100644 --- a/config/chips/F76xxx.chip +++ b/config/chips/F76xxx.chip @@ -1,13 +1,13 @@ # Chip-ID file for F76xxx # -chip_id 451 +chip_id 0x451 description F76xxx flash_type 4 flash_pagesize 800 -sram_size 80000 -bootrom_base 200000 -bootrom_size edc0 -option_base 1fff0000 -option_size 20 -flags 2 +sram_size 0x80000 +bootrom_base 0x200000 +bootrom_size 0xedc0 +option_base 0x1fff0000 +option_size 0x20 +flags swo diff --git a/config/chips/F7xx.chip b/config/chips/F7xx.chip index c031b5f4a..87420f2ab 100644 --- a/config/chips/F7xx.chip +++ b/config/chips/F7xx.chip @@ -1,13 +1,13 @@ # Chip-ID file for F7xx # -chip_id 449 +chip_id 0x449 description F7xx flash_type 3 flash_pagesize 800 -sram_size 50000 -bootrom_base 100000 -bootrom_size edc0 -option_base 0 -option_size 0 -flags 2 +sram_size 0x50000 +bootrom_base 0x100000 +bootrom_size 0xedc0 +option_base 0x0 +option_size 0x0 +flags swo diff --git a/config/chips/G030_G031_G041.chip b/config/chips/G030_G031_G041.chip index a1c42f58f..7d47e7aed 100644 --- a/config/chips/G030_G031_G041.chip +++ b/config/chips/G030_G031_G041.chip @@ -1,13 +1,13 @@ # Chip-ID file for G030/G031/G041 # -chip_id 466 +chip_id 0x466 description G030/G031/G041 flash_type 7 flash_pagesize 800 -sram_size 2000 -bootrom_base 1fff0000 -bootrom_size 2000 -option_base 1fff7800 -option_size 4 -flags 0 +sram_size 0x2000 +bootrom_base 0x1fff0000 +bootrom_size 0x2000 +option_base 0x1fff7800 +option_size 0x4 +flags none diff --git a/config/chips/G070_G071_G081.chip b/config/chips/G070_G071_G081.chip index 58eb16b16..9905fc682 100644 --- a/config/chips/G070_G071_G081.chip +++ b/config/chips/G070_G071_G081.chip @@ -1,13 +1,13 @@ # Chip-ID file for G070/G071/G081 # -chip_id 460 +chip_id 0x460 description G070/G071/G081 flash_type 7 flash_pagesize 800 -sram_size 9000 -bootrom_base 1fff0000 -bootrom_size 7000 -option_base 1fff7800 -option_size 4 -flags 0 +sram_size 0x9000 +bootrom_base 0x1fff0000 +bootrom_size 0x7000 +option_base 0x1fff7800 +option_size 0x4 +flags none diff --git a/config/chips/G4_cat2.chip b/config/chips/G4_cat2.chip index 309cbb83f..47745e715 100644 --- a/config/chips/G4_cat2.chip +++ b/config/chips/G4_cat2.chip @@ -1,13 +1,13 @@ # Chip-ID file for G4 cat2 # -chip_id 468 +chip_id 0x468 description G4 cat2 flash_type 8 flash_pagesize 800 -sram_size 8000 -bootrom_base 1fff0000 -bootrom_size 7000 -option_base 1ffff800 -option_size 4 -flags 2 +sram_size 0x8000 +bootrom_base 0x1fff0000 +bootrom_size 0x7000 +option_base 0x1ffff800 +option_size 0x4 +flags swo diff --git a/config/chips/G4_cat3.chip b/config/chips/G4_cat3.chip index 357522b31..f883b9176 100644 --- a/config/chips/G4_cat3.chip +++ b/config/chips/G4_cat3.chip @@ -1,13 +1,13 @@ # Chip-ID file for G4 cat3 # -chip_id 469 +chip_id 0x469 description G4 cat3 flash_type 8 flash_pagesize 800 -sram_size 18000 -bootrom_base 1fff0000 -bootrom_size 7000 -option_base 1ffff800 -option_size 4 -flags 3 +sram_size 0x18000 +bootrom_base 0x1fff0000 +bootrom_size 0x7000 +option_base 0x1ffff800 +option_size 0x4 +flags dualbank swo diff --git a/config/chips/H72x_H73x.chip b/config/chips/H72x_H73x.chip index 43c8ae67b..81c1b71c9 100644 --- a/config/chips/H72x_H73x.chip +++ b/config/chips/H72x_H73x.chip @@ -1,13 +1,13 @@ # Chip-ID file for H72x/H73x # -chip_id 483 +chip_id 0x483 description H72x/H73x -flash_type a +flash_type 10 flash_pagesize 20000 -sram_size 20000 -bootrom_base 1ff00000 -bootrom_size 20000 -option_base 5200201c -option_size 2c -flags 2 +sram_size 0x20000 +bootrom_base 0x1ff00000 +bootrom_size 0x20000 +option_base 0x5200201c +option_size 0x2c +flags swo diff --git a/config/chips/H74x_H75x.chip b/config/chips/H74x_H75x.chip index c4d374e60..7753cfe03 100644 --- a/config/chips/H74x_H75x.chip +++ b/config/chips/H74x_H75x.chip @@ -1,13 +1,13 @@ # Chip-ID file for H74x/H75x # -chip_id 450 +chip_id 0x450 description H74x/H75x -flash_type a +flash_type 10 flash_pagesize 20000 -sram_size 20000 -bootrom_base 1ff00000 -bootrom_size 20000 -option_base 5200201c -option_size 2c -flags 3 +sram_size 0x20000 +bootrom_base 0x1ff00000 +bootrom_size 0x20000 +option_base 0x5200201c +option_size 0x2c +flags dualbank swo diff --git a/config/chips/H7Ax_H7Bx.chip b/config/chips/H7Ax_H7Bx.chip index b17631385..df6c13726 100644 --- a/config/chips/H7Ax_H7Bx.chip +++ b/config/chips/H7Ax_H7Bx.chip @@ -1,13 +1,13 @@ # Chip-ID file for H7Ax/H7Bx # -chip_id 480 +chip_id 0x480 description H7Ax/H7Bx -flash_type a +flash_type 10 flash_pagesize 2000 -sram_size 20000 -bootrom_base 1ff00000 -bootrom_size 20000 -option_base 5200201c -option_size 2c -flags 3 +sram_size 0x20000 +bootrom_base 0x1ff00000 +bootrom_size 0x20000 +option_base 0x5200201c +option_size 0x2c +flags dualbank swo diff --git a/config/chips/L011.chip b/config/chips/L011.chip index 6d8298848..2f1fa7b56 100644 --- a/config/chips/L011.chip +++ b/config/chips/L011.chip @@ -1,13 +1,13 @@ # Chip-ID file for L011 # -chip_id 457 +chip_id 0x457 description L011 flash_type 5 flash_pagesize 80 -sram_size 2000 -bootrom_base 1ff00000 -bootrom_size 2000 -option_base 0 -option_size 0 -flags 0 +sram_size 0x2000 +bootrom_base 0x1ff00000 +bootrom_size 0x2000 +option_base 0x0 +option_size 0x0 +flags none diff --git a/config/chips/L0x3.chip b/config/chips/L0x3.chip index 4bfc318c0..cbdc6cace 100644 --- a/config/chips/L0x3.chip +++ b/config/chips/L0x3.chip @@ -1,13 +1,13 @@ # Chip-ID file for L0x3 # -chip_id 417 +chip_id 0x417 description L0x3 flash_type 5 -flash_pagesize 80 -sram_size 2000 -bootrom_base 1ff0000 -bootrom_size 1000 -option_base 1ff80000 -option_size 14 -flags 0 +flash_pagesize 0x80 +sram_size 0x2000 +bootrom_base 0x1ff0000 +bootrom_size 0x1000 +option_base 0x1ff80000 +option_size 0x14 +flags none diff --git a/config/chips/L0xx_cat2.chip b/config/chips/L0xx_cat2.chip index 8b24634cf..43a301b27 100644 --- a/config/chips/L0xx_cat2.chip +++ b/config/chips/L0xx_cat2.chip @@ -1,13 +1,13 @@ # Chip-ID file for L0xx cat2 # -chip_id 425 +chip_id 0x425 description L0xx cat2 flash_type 5 flash_pagesize 80 -sram_size 2000 -bootrom_base 1ff0000 -bootrom_size 1000 -option_base 1ff80000 -option_size 14 -flags 0 +sram_size 0x2000 +bootrom_base 0x1ff0000 +bootrom_size 0x1000 +option_base 0x1ff80000 +option_size 0x14 +flags none diff --git a/config/chips/L0xx_cat5.chip b/config/chips/L0xx_cat5.chip index b52f97363..8ab0a50f8 100644 --- a/config/chips/L0xx_cat5.chip +++ b/config/chips/L0xx_cat5.chip @@ -1,13 +1,13 @@ # Chip-ID file for L0xx cat5 # -chip_id 447 +chip_id 0x447 description L0xx cat5 flash_type 5 flash_pagesize 80 -sram_size 5000 -bootrom_base 1ff0000 -bootrom_size 2000 -option_base 1ff80000 -option_size 14 -flags 0 +sram_size 0x5000 +bootrom_base 0x1ff0000 +bootrom_size 0x2000 +option_base 0x1ff80000 +option_size 0x14 +flags none diff --git a/config/chips/L152RE.chip b/config/chips/L152RE.chip index c073ade93..ebe012c5a 100644 --- a/config/chips/L152RE.chip +++ b/config/chips/L152RE.chip @@ -1,13 +1,13 @@ # Chip-ID file for L152RE # -chip_id 437 +chip_id 0x437 description L152RE flash_type 5 flash_pagesize 100 -sram_size 14000 -bootrom_base 1ff00000 -bootrom_size 1000 -option_base 0 -option_size 0 -flags 2 +sram_size 0x14000 +bootrom_base 0x1ff00000 +bootrom_size 0x1000 +option_base 0x0 +option_size 0x0 +flags swo diff --git a/config/chips/L1xx_cat2.chip b/config/chips/L1xx_cat2.chip index dd89c981c..02012078a 100644 --- a/config/chips/L1xx_cat2.chip +++ b/config/chips/L1xx_cat2.chip @@ -1,13 +1,13 @@ # Chip-ID file for L1xx cat2 # -chip_id 429 +chip_id 0x429 description L1xx cat2 flash_type 5 flash_pagesize 100 -sram_size 8000 -bootrom_base 1ff00000 -bootrom_size 1000 -option_base 0 -option_size 0 -flags 2 +sram_size 0x8000 +bootrom_base 0x1ff00000 +bootrom_size 0x1000 +option_base 0x0 +option_size 0x0 +flags swo diff --git a/config/chips/L1xx_high-density.chip b/config/chips/L1xx_high-density.chip index 8e5b0cd44..130b4e456 100644 --- a/config/chips/L1xx_high-density.chip +++ b/config/chips/L1xx_high-density.chip @@ -1,13 +1,13 @@ # Chip-ID file for L1xx high-density # -chip_id 436 +chip_id 0x436 description L1xx high-density flash_type 5 flash_pagesize 100 -sram_size c000 -bootrom_base 1ff00000 -bootrom_size 1000 -option_base 1ff80000 -option_size 8 -flags 2 +sram_size 0xc000 +bootrom_base 0x1ff00000 +bootrom_size 0x1000 +option_base 0x1ff80000 +option_size 0x8 +flags swo diff --git a/config/chips/L1xx_medium-density.chip b/config/chips/L1xx_medium-density.chip index feb53b846..409b4dacc 100644 --- a/config/chips/L1xx_medium-density.chip +++ b/config/chips/L1xx_medium-density.chip @@ -1,13 +1,13 @@ # Chip-ID file for L1xx medium-density # -chip_id 416 +chip_id 0x416 description L1xx medium-density flash_type 5 flash_pagesize 100 -sram_size 4000 -bootrom_base 1ff00000 -bootrom_size 1000 -option_base 0 -option_size 0 -flags 2 +sram_size 0x4000 +bootrom_base 0x1ff00000 +bootrom_size 0x1000 +option_base 0x0 +option_size 0x0 +flags swo diff --git a/config/chips/L1xx_medium-plus-density.chip b/config/chips/L1xx_medium-plus-density.chip index bdce4adc2..374f2e914 100644 --- a/config/chips/L1xx_medium-plus-density.chip +++ b/config/chips/L1xx_medium-plus-density.chip @@ -1,13 +1,13 @@ # Chip-ID file for L1xx medium-plus-density # -chip_id 427 +chip_id 0x427 description L1xx medium-plus-density flash_type 5 flash_pagesize 100 -sram_size 8000 -bootrom_base 1ff00000 -bootrom_size 1000 -option_base 0 -option_size 0 -flags 2 +sram_size 0x8000 +bootrom_base 0x1ff00000 +bootrom_size 0x1000 +option_base 0x0 +option_size 0x0 +flags swo diff --git a/config/chips/L41x.chip b/config/chips/L41x.chip index a05034af4..cf51b4b02 100644 --- a/config/chips/L41x.chip +++ b/config/chips/L41x.chip @@ -1,13 +1,13 @@ # Chip-ID file for L41x # -chip_id 464 +chip_id 0x464 description L41x flash_type 6 flash_pagesize 800 -sram_size a000 -bootrom_base 1fff0000 -bootrom_size 7000 -option_base 0 -option_size 0 -flags 2 +sram_size 0xa000 +bootrom_base 0x1fff0000 +bootrom_size 0x7000 +option_base 0x0 +option_size 0x0 +flags swo diff --git a/config/chips/L43x_L44x.chip b/config/chips/L43x_L44x.chip index 4c41ac69b..1953a6a99 100644 --- a/config/chips/L43x_L44x.chip +++ b/config/chips/L43x_L44x.chip @@ -1,13 +1,13 @@ # Chip-ID file for L43x/L44x # -chip_id 435 +chip_id 0x435 description L43x/L44x flash_type 6 flash_pagesize 800 -sram_size c000 -bootrom_base 1fff0000 -bootrom_size 7000 -option_base 1fff7800 -option_size 4 -flags 2 +sram_size 0xc000 +bootrom_base 0x1fff0000 +bootrom_size 0x7000 +option_base 0x1fff7800 +option_size 0x4 +flags swo diff --git a/config/chips/L45x_L46x.chip b/config/chips/L45x_L46x.chip index da1594995..79a90fcac 100644 --- a/config/chips/L45x_L46x.chip +++ b/config/chips/L45x_L46x.chip @@ -1,13 +1,13 @@ # Chip-ID file for L45x/L46x # -chip_id 462 +chip_id 0x462 description L45x/L46x flash_type 6 flash_pagesize 800 -sram_size 20000 -bootrom_base 1fff0000 -bootrom_size 7000 -option_base 0 -option_size 0 -flags 2 +sram_size 0x20000 +bootrom_base 0x1fff0000 +bootrom_size 0x7000 +option_base 0x0 +option_size 0x0 +flags swo diff --git a/config/chips/L496x_L4A6x.chip b/config/chips/L496x_L4A6x.chip index 9bfcdb366..f94c0c582 100644 --- a/config/chips/L496x_L4A6x.chip +++ b/config/chips/L496x_L4A6x.chip @@ -1,13 +1,13 @@ # Chip-ID file for L496x/L4A6x # -chip_id 461 +chip_id 0x461 description L496x/L4A6x flash_type 6 flash_pagesize 800 -sram_size 40000 -bootrom_base 1fff0000 -bootrom_size 7000 -option_base 1fff7800 -option_size 4 -flags 2 +sram_size 0x40000 +bootrom_base 0x1fff0000 +bootrom_size 0x7000 +option_base 0x1fff7800 +option_size 0x4 +flags swo diff --git a/config/chips/L4Rx.chip b/config/chips/L4Rx.chip index a9b082128..355f22470 100644 --- a/config/chips/L4Rx.chip +++ b/config/chips/L4Rx.chip @@ -1,13 +1,13 @@ # Chip-ID file for L4Rx # -chip_id 470 +chip_id 0x470 description L4Rx flash_type 6 flash_pagesize 1000 -sram_size a0000 -bootrom_base 1fff0000 -bootrom_size 7000 -option_base 0 -option_size 0 -flags 2 +sram_size 0xa0000 +bootrom_base 0x1fff0000 +bootrom_size 0x7000 +option_base 0x0 +option_size 0x0 +flags swo diff --git a/config/chips/L4xx.chip b/config/chips/L4xx.chip index b66df6b31..3360a446e 100644 --- a/config/chips/L4xx.chip +++ b/config/chips/L4xx.chip @@ -1,13 +1,13 @@ # Chip-ID file for L4xx # -chip_id 415 +chip_id 0x415 description L4xx flash_type 6 flash_pagesize 800 -sram_size 18000 -bootrom_base 1fff0000 -bootrom_size 7000 -option_base 1fff7800 -option_size 4 -flags 2 +sram_size 0x18000 +bootrom_base 0x1fff0000 +bootrom_size 0x7000 +option_base 0x1fff7800 +option_size 0x4 +flags swo diff --git a/config/chips/WB55.chip b/config/chips/WB55.chip index 4ad4d08d0..9cf1d4380 100644 --- a/config/chips/WB55.chip +++ b/config/chips/WB55.chip @@ -1,13 +1,13 @@ # Chip-ID file for WB55 # -chip_id 495 +chip_id 0x495 description WB55 flash_type 9 flash_pagesize 1000 -sram_size 40000 -bootrom_base 1fff0000 -bootrom_size 7000 -option_base 0 -option_size 0 -flags 2 +sram_size 0x40000 +bootrom_base 0x1fff0000 +bootrom_size 0x7000 +option_base 0x0 +option_size 0x0 +flags swo diff --git a/config/chips/unknown_device.chip b/config/chips/unknown_device.chip index ea4fe5f02..2235d0072 100644 --- a/config/chips/unknown_device.chip +++ b/config/chips/unknown_device.chip @@ -1,13 +1,13 @@ # Chip-ID file for unknown device # -chip_id 0 +chip_id 0x0 description unknown device flash_type 0 flash_pagesize 0 -sram_size 0 -bootrom_base 0 -bootrom_size 0 -option_base 0 -option_size 0 -flags 0 +sram_size 0x0 +bootrom_base 0x0 +bootrom_size 0x0 +option_base 0x0 +option_size 0x0 +flags none diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index 1543041c2..772a722aa 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -8,6 +8,13 @@ #include #include +// This is the old chipid "database". +// It is kept here for now to be able to compare the +// result between the "old code" and the "new code". +// For now if you need to change something, please +// change it both here and in the corresponding +// config/chips/*.chip file. + static struct stlink_chipid_params devices[] = { { // RM0410 document was used to find these paramaters @@ -842,16 +849,16 @@ void dump_a_chip (FILE *fp, struct stlink_chipid_params *dev) { fprintf(fp, "# Chip-ID file for %s\n", dev->description); fprintf(fp, "#\n"); - fprintf(fp, "chip_id %x\n", dev->chip_id); + fprintf(fp, "chip_id 0x%x\n", dev->chip_id); fprintf(fp, "description %s\n", dev->description); - fprintf(fp, "flash_type %x\n", dev->flash_type); - fprintf(fp, "flash_pagesize %x\n", dev->flash_pagesize); - fprintf(fp, "sram_size %x\n", dev->sram_size); - fprintf(fp, "bootrom_base %x\n", dev->bootrom_base); - fprintf(fp, "bootrom_size %x\n", dev->bootrom_size); - fprintf(fp, "option_base %x\n", dev->option_base); - fprintf(fp, "option_size %x\n", dev->option_size); - fprintf(fp, "flags %x\n\n", dev->flags); + fprintf(fp, "flash_type %d\n", dev->flash_type); + fprintf(fp, "flash_pagesize 0x%x\n", dev->flash_pagesize); + fprintf(fp, "sram_size 0x%x\n", dev->sram_size); + fprintf(fp, "bootrom_base 0x%x\n", dev->bootrom_base); + fprintf(fp, "bootrom_size 0x%x\n", dev->bootrom_size); + fprintf(fp, "option_base 0x%x\n", dev->option_base); + fprintf(fp, "option_size 0x%x\n", dev->option_size); + fprintf(fp, "flags %d\n\n", dev->flags); } @@ -883,10 +890,10 @@ struct stlink_chipid_params *stlink_chipid_get_params(uint32_t chipid) { void process_chipfile(char *fname) { FILE *fp; - char *p, buf[1025]; + char *p, *pp, buf[1025]; char word[64], value[64]; struct stlink_chipid_params *ts; - int nc; + int nc, ival; //fprintf (stderr, "processing chipfile %s.\n", fname); fp = fopen(fname, "r"); @@ -902,30 +909,39 @@ void process_chipfile(char *fname) if (*p == '#') continue; // ignore comments. sscanf(p, "%s %s", word, value); + ival = atoi (value); if (strcmp(word, "chip_id") == 0) { - sscanf(value, "%x", &ts->chip_id); + ts->chip_id = ival; } else if (strcmp (word, "description") == 0) { //ts->description = strdup (value); buf[strlen(p)-1] = 0; // chomp newline sscanf(p, "%*s %n", &nc); ts->description = strdup(p+nc); } else if (strcmp (word, "flash_type") == 0) { - sscanf(value, "%x", &ts->flash_type); + ts->flash_type = ival; } else if (strcmp (word, "flash_size_reg") == 0) { - sscanf(value, "%x", &ts->flash_size_reg); + ts->flash_size_reg = ival; } else if (strcmp (word, "flash_pagesize") == 0) { - sscanf(value, "%x", &ts->flash_pagesize); + ts->flash_pagesize = ival; } else if (strcmp (word, "sram_size") == 0) { - sscanf(value, "%x", &ts->sram_size); + ts->sram_size = ival; } else if (strcmp (word, "bootrom_base") == 0) { - sscanf(value, "%x", &ts->bootrom_base); + ts->bootrom_base = ival; } else if (strcmp (word, "bootrom_size") == 0) { - sscanf(value, "%x", &ts->bootrom_size); + ts->bootrom_size = ival; } else if (strcmp (word, "option_base") == 0) { - sscanf(value, "%x", &ts->option_base); + ts->option_base = ival; } else if (strcmp (word, "option_size") == 0) { - sscanf(value, "%x", &ts->option_size); + ts->option_size = ival; } else if (strcmp (word, "flags") == 0) { + pp = strtok (p, " \t\n"); + while ((pp = strtok (NULL, " \t\n")) ) { + if (strcmp (pp, "none") == 0) ts->flags = 0; // not necessary: calloc did this already. + else if (strcmp (pp, "dualbank") == 0) ts->flags |= CHIP_F_HAS_DUAL_BANK; + else if (strcmp (pp, "swo") == 0) ts->flags |= CHIP_F_HAS_SWO_TRACING; + else fprintf (stderr, "Unknown flags word in %s: '%s'\n", + fname, pp); + } sscanf(value, "%x", &ts->flags); } else { fprintf (stderr, "Unknown keyword in %s: %s\n", From f88509130505748831ded417031a14cd033bdb63 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Mon, 24 May 2021 12:13:56 +0200 Subject: [PATCH 275/503] General Project Update - Updated CHANGELOG.md - Updated GitHub security policy - [doc] Updated steps for release procedure - [doc] Updated list of supported OS - Removed old clang_analyze script - Minor fix in travis build script --- .travis.sh | 6 +++--- CHANGELOG.md | 1 + SECURITY.md | 3 ++- doc/release.md | 1 + doc/version_support.md | 6 +++--- run_clang_analyze.sh | 9 --------- 6 files changed, 10 insertions(+), 16 deletions(-) delete mode 100755 run_clang_analyze.sh diff --git a/.travis.sh b/.travis.sh index a156db203..d8c5377de 100755 --- a/.travis.sh +++ b/.travis.sh @@ -23,12 +23,12 @@ elif [ "$TRAVIS_JOB_NAME" == "linux-mingw-32" ]; then make && rm -rf build-mingw-32 && cd - elif [ "$TRAVIS_OS_NAME" == "osx" ]; then - echo "--> Building Debug..." + echo "--> make debug..." mkdir -p build/Debug && cd build/Debug cmake -DCMAKE_BUILD_TYPE=Debug -DCMAKE_INSTALL_PREFIX=$PWD/install $DIR - make && cd - + make debug && cd - - echo "--> Building Release with package..." + echo "--> make package..." mkdir -p build/Release && cd build/Release cmake -DCMAKE_BUILD_TYPE=Release -DCMAKE_INSTALL_PREFIX=$PWD/install $DIR make package && cd - diff --git a/CHANGELOG.md b/CHANGELOG.md index 57ed15e98..b711f3890 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -17,6 +17,7 @@ Updates & changes: - Added instructions for bug-reports and feature-requests to contribution guidelines ([#906](https://github.com/stlink-org/stlink/pull/906)) - Added travis CI configuration for macOS 10.14 to maintain capability for 32-bit compilation ([#f5ada94](https://github.com/stlink-org/stlink/commit/f5ada9474cdb87ff37de0d4eb9e75622b5870646)) +- Updated description of chip id 0x0457 to L01x/L02x ([#1143](https://github.com/stlink-org/stlink/pull/1143), [#1144](https://github.com/stlink-org/stlink/pull/1144)) Fixes: - cmake: Install shared libraries in proper directories ([#1142](https://github.com/stlink-org/stlink/pull/1142)) diff --git a/SECURITY.md b/SECURITY.md index caa2740db..9ace47066 100644 --- a/SECURITY.md +++ b/SECURITY.md @@ -7,7 +7,8 @@ The following versions of the stlink toolset are currently being supported.
+On Windows users should ensure that cmake 3.20.2 or any later version is installed.
Up on compiling c-make will **automatically** download and install the latest compatible version of `libusb` (1.0.23 at the time of writing). - Windows 10 @@ -14,8 +14,8 @@ Up on compiling c-make will **automatically** download and install the latest co | Package Repository | libusb
version | cmake
version | gtk-3
version | Supported macOS versions | | ------------------ | ------------------- | ------------------ | ------------------ | ------------------------ | -| homebrew | 1.0.23 | 3.17.0 | 3.24.18
gtk+3 | 10.9 - 11.x | -| MacPorts | 1.0.23 | 3.17.0 | 3.24.18
gtk3 | 10.4 - 11.x | +| homebrew | 1.0.24 | 3.20.2 | 3.24.29
gtk+3 | 10.9 - 11.x | +| MacPorts | 1.0.24 | 3.20.2 | 3.24.29
gtk3 | 10.4 - 11.x | NOTE: In order to use a STLINK/V1 programmer on macOS, versions 10.14 or 10.15 are required. diff --git a/run_clang_analyze.sh b/run_clang_analyze.sh deleted file mode 100755 index fd1b78b55..000000000 --- a/run_clang_analyze.sh +++ /dev/null @@ -1,9 +0,0 @@ -#!/bin/bash -# Run this hacky script in project root directory to start clang static analysis. -# Adjust ccc-analyzer path if necessary - -CCC_ANALYZER=/usr/share/clang/scan-build-3.5/ccc-analyzer -mkdir -p build-clang-analyze/reports -cd build-clang-analyze -cmake -DCMAKE_C_COMPILER=${CCC_ANALYZER} $* .. -scan-build -o ./reports --keep-empty make From 9eb81e1e0adc6a5bf7a1c68cbbaf3fd35ec85be0 Mon Sep 17 00:00:00 2001 From: anton Date: Mon, 24 May 2021 21:35:02 +0500 Subject: [PATCH 276/503] Expanded and revised list of chips --- src/stlink-lib/chipid.c | 326 +++++++++++++++++++++++++--------------- src/stlink-lib/chipid.h | 18 ++- 2 files changed, 213 insertions(+), 131 deletions(-) diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index 711bf24b0..283f6faec 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -3,26 +3,28 @@ static const struct stlink_chipid_params devices[] = { { - // RM0410 document was used to find these paramaters + // STM32F76x/F77x + // RM0410 .chip_id = STLINK_CHIPID_STM32_F7XXXX, - .description = "F76xxx", + .description = "F76x/F77x", .flash_type = STLINK_FLASH_TYPE_F7, .flash_size_reg = 0x1ff0f442, // section 45.2 .flash_pagesize = 0x800, // No flash pages .sram_size = 0x80000, // "SRAM" byte size in hex from - .bootrom_base = 0x00200000, // ! "System memory" starting address from - .bootrom_size = 0xEDC0, // ! @todo "System memory" byte size in hex from + .bootrom_base = 0x00200000, // "System memory" starting address from + .bootrom_size = 0xEDC0, .option_base = STM32_F7_OPTION_BYTES_BASE, // Used for reading back the option // bytes, writing uses FLASH_F7_OPTCR // and FLASH_F7_OPTCR1 .option_size = 0x20, - .flags = CHIP_F_HAS_SWO_TRACING, + .flags = CHIP_F_HAS_DUAL_BANK | CHIP_F_HAS_SWO_TRACING, }, { - // RM0385 and DS10916 document was used to find these paramaters + // STM32F74x/F75x + // RM0385, DS10916 .chip_id = STLINK_CHIPID_STM32_F7, - .description = "F7xx", + .description = "F74x/F75x", .flash_type = STLINK_FLASH_TYPE_F4, .flash_size_reg = 0x1ff0f442, // section 41.2 .flash_pagesize = 0x800, // No flash pages @@ -34,7 +36,8 @@ static const struct stlink_chipid_params devices[] = { .flags = CHIP_F_HAS_SWO_TRACING, }, { - // RM0431 and DS document was used to find these paramaters + // STM32F72x/F73x + // RM0431 .chip_id = STLINK_CHIPID_STM32_F72XXX, .description = "F72x/F73x", .flash_type = STLINK_FLASH_TYPE_F4, @@ -48,25 +51,27 @@ static const struct stlink_chipid_params devices[] = { .flags = CHIP_F_HAS_SWO_TRACING, }, { - // table 2, PM0063 + // STM32F1xx medium-density devices + // RM0008 .chip_id = STLINK_CHIPID_STM32_F1_MEDIUM, - .description = "F1xx Medium-density", + .description = "F1xx MD", .flash_type = STLINK_FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7e0, .flash_pagesize = 0x400, .sram_size = 0x5000, - .bootrom_base = 0x1ffff000, + .bootrom_base = 0x1ffff000, // 2.3.3 "Embedded Flash memory" .bootrom_size = 0x800, .option_base = STM32_F0_OPTION_BYTES_BASE, .option_size = 16, .flags = CHIP_F_HAS_SWO_TRACING, }, { - // table 1, PM0059 + // STM32F205xx, STM32F207xx, STM32F215xx, STM32F217xx + // RM0033 (rev 5) .chip_id = STLINK_CHIPID_STM32_F2, .description = "F2xx", .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1fff7a22, // as in RM0033 Rev 5 + .flash_size_reg = 0x1fff7a22, .flash_pagesize = 0x20000, .sram_size = 0x20000, .bootrom_base = 0x1fff0000, @@ -76,9 +81,10 @@ static const struct stlink_chipid_params devices[] = { .flags = CHIP_F_HAS_SWO_TRACING, }, { - // PM0063 + // STM32F1xx low-density devices + // RM0008 .chip_id = STLINK_CHIPID_STM32_F1_LOW, - .description = "F1 Low-density device", + .description = "F1xx LD", .flash_type = STLINK_FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7e0, .flash_pagesize = 0x400, @@ -90,10 +96,12 @@ static const struct stlink_chipid_params devices[] = { .flags = CHIP_F_HAS_SWO_TRACING, }, { + // STM32F4x5/F4x7 + // RM0090 (rev 2) .chip_id = STLINK_CHIPID_STM32_F4, - .description = "F4xx", + .description = "F4x5/F4x7", .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1FFF7A22, // As in rm0090 since Rev 2 + .flash_size_reg = 0x1FFF7A22, .flash_pagesize = 0x4000, .sram_size = 0x30000, .bootrom_base = 0x1fff0000, @@ -103,10 +111,12 @@ static const struct stlink_chipid_params devices[] = { .flags = CHIP_F_HAS_SWO_TRACING, }, { + // STM32F46x/F47x + // RM0090 (rev 2) .chip_id = STLINK_CHIPID_STM32_F4_DSI, .description = "F46x/F47x", .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1FFF7A22, // As in rm0090 since Rev 2 + .flash_size_reg = 0x1FFF7A22, .flash_pagesize = 0x4000, .sram_size = 0x40000, .bootrom_base = 0x1fff0000, @@ -114,10 +124,12 @@ static const struct stlink_chipid_params devices[] = { .flags = CHIP_F_HAS_SWO_TRACING, }, { + // STM32F42x/F43x + // RM0090 (rev 2) .chip_id = STLINK_CHIPID_STM32_F4_HD, .description = "F42x/F43x", .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1FFF7A22, // As in rm0090 since Rev 2 + .flash_size_reg = 0x1FFF7A22, .flash_pagesize = 0x4000, .sram_size = 0x40000, .bootrom_base = 0x1fff0000, @@ -126,7 +138,7 @@ static const struct stlink_chipid_params devices[] = { }, { .chip_id = STLINK_CHIPID_STM32_F4_LP, - .description = "F4xx (low power)", + .description = "F401xB/C", .flash_type = STLINK_FLASH_TYPE_F4, .flash_size_reg = 0x1FFF7A22, .flash_pagesize = 0x4000, @@ -137,20 +149,18 @@ static const struct stlink_chipid_params devices[] = { }, { .chip_id = STLINK_CHIPID_STM32_F411XX, - .description = "STM32F411xC/E", + .description = "F411xC/E", .flash_type = STLINK_FLASH_TYPE_F4, .flash_size_reg = 0x1FFF7A22, .flash_pagesize = 0x4000, .sram_size = 0x20000, .bootrom_base = 0x1fff0000, .bootrom_size = 0x7800, - .option_base = STM32_F4_OPTION_BYTES_BASE, - .option_size = 4, .flags = CHIP_F_HAS_SWO_TRACING, }, { .chip_id = STLINK_CHIPID_STM32_F4_DE, - .description = "F4xx (Dynamic Efficency)", + .description = "F401xD/E", .flash_type = STLINK_FLASH_TYPE_F4, .flash_size_reg = 0x1FFF7A22, .flash_pagesize = 0x4000, @@ -160,8 +170,10 @@ static const struct stlink_chipid_params devices[] = { .flags = CHIP_F_HAS_SWO_TRACING, }, { + // STM32F1xx high-density devices + // RM0008 .chip_id = STLINK_CHIPID_STM32_F1_HIGH, - .description = "F1xx High-density", + .description = "F1xx HD", .flash_type = STLINK_FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7e0, .flash_pagesize = 0x800, @@ -173,47 +185,53 @@ static const struct stlink_chipid_params devices[] = { .flags = CHIP_F_HAS_SWO_TRACING, }, { - // This ignores the EEPROM! (and uses the page erase size, - // not the sector write protection...) + // STM32L100/L15x/L16x Cat.1 + // RM0038 .chip_id = STLINK_CHIPID_STM32_L1_MEDIUM, - .description = "L1xx Medium-density", + .description = "L1xx Cat.1", .flash_type = STLINK_FLASH_TYPE_L0, .flash_size_reg = 0x1ff8004c, .flash_pagesize = 0x100, - .sram_size = 0x4000, + .sram_size = 0x4000, // up to 16k .bootrom_base = 0x1ff00000, .bootrom_size = 0x1000, .flags = CHIP_F_HAS_SWO_TRACING, }, { + // STM32L100/L15x/L16x Cat.2 + // RM0038 .chip_id = STLINK_CHIPID_STM32_L1_CAT2, .description = "L1xx Cat.2", .flash_type = STLINK_FLASH_TYPE_L0, .flash_size_reg = 0x1ff8004c, .flash_pagesize = 0x100, - .sram_size = 0x8000, + .sram_size = 0x8000, // up to 32k .bootrom_base = 0x1ff00000, .bootrom_size = 0x1000, .flags = CHIP_F_HAS_SWO_TRACING, }, { + // STM32L100/L15x/L16x Cat.3 + // RM0038 .chip_id = STLINK_CHIPID_STM32_L1_MEDIUM_PLUS, - .description = "L1xx Medium-Plus-density", + .description = "L1xx Cat.3", .flash_type = STLINK_FLASH_TYPE_L0, .flash_size_reg = 0x1ff800cc, .flash_pagesize = 0x100, - .sram_size = 0x8000, // not completely clear if there are some with 48k + .sram_size = 0x8000, // up to 32k .bootrom_base = 0x1ff00000, .bootrom_size = 0x1000, .flags = CHIP_F_HAS_SWO_TRACING, }, { + // STM32L100/L15x/L16x Cat.4 + // RM0038 .chip_id = STLINK_CHIPID_STM32_L1_HIGH, - .description = "L1xx High-density", + .description = "L1xx Cat.4", .flash_type = STLINK_FLASH_TYPE_L0, .flash_size_reg = 0x1ff800cc, .flash_pagesize = 0x100, - .sram_size = 0xC000, // not completely clear if there are some with 32k + .sram_size = 0xC000, // up to 48k .bootrom_base = 0x1ff00000, .bootrom_size = 0x1000, .option_base = STM32_L1_OPTION_BYTES_BASE, @@ -221,19 +239,23 @@ static const struct stlink_chipid_params devices[] = { .flags = CHIP_F_HAS_SWO_TRACING, }, { + // STM32L100/L15x/L16x Cat.5 + // RM0038 .chip_id = STLINK_CHIPID_STM32_L152_RE, - .description = "L152RE", + .description = "L1xx Cat.5", .flash_type = STLINK_FLASH_TYPE_L0, .flash_size_reg = 0x1ff800cc, .flash_pagesize = 0x100, - .sram_size = 0x14000, // not completely clear if there are some with 32k + .sram_size = 0x14000, // up to 80k .bootrom_base = 0x1ff00000, .bootrom_size = 0x1000, .flags = CHIP_F_HAS_SWO_TRACING, }, { + // STM32F1xx connectivity devices + // RM0008 .chip_id = STLINK_CHIPID_STM32_F1_CONN, - .description = "F1 Connectivity line", + .description = "F1xx CL", .flash_type = STLINK_FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7e0, .flash_pagesize = 0x800, @@ -245,9 +267,10 @@ static const struct stlink_chipid_params devices[] = { .flags = CHIP_F_HAS_SWO_TRACING, }, { - // Low and Medium density VL have same chipid. RM0041 25.6.1 + // STM32F1xx low- and medium-density value line devices + // RM0041 .chip_id = STLINK_CHIPID_STM32_F1_VL_MEDIUM_LOW, - .description = "F1xx Value Line", + .description = "F1xx VL", .flash_type = STLINK_FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7e0, .flash_pagesize = 0x400, @@ -259,7 +282,8 @@ static const struct stlink_chipid_params devices[] = { .flags = CHIP_F_HAS_SWO_TRACING, }, { - // STM32F446x family. Support based on DM00135183.pdf (RM0390) document. + // STM32F446x family + // RM0390 .chip_id = STLINK_CHIPID_STM32_F446, .description = "F446", .flash_type = STLINK_FLASH_TYPE_F4, @@ -273,7 +297,8 @@ static const struct stlink_chipid_params devices[] = { .flags = CHIP_F_HAS_SWO_TRACING, }, { - // STM32F410 MCUs. Support based on DM00180366.pdf (RM0401) document. + // STM32F410 + // RM0401 .chip_id = STLINK_CHIPID_STM32_F410, .description = "F410", .flash_type = STLINK_FLASH_TYPE_F4, @@ -285,10 +310,10 @@ static const struct stlink_chipid_params devices[] = { .flags = CHIP_F_HAS_SWO_TRACING, }, { - // This is STK32F303VCT6 device from STM32 F3 Discovery board. - // Support based on DM00043574.pdf (RM0316) document. + // STM32F303xB/C, STM32F358, STM32F302xBxC + // RM0316, RM0365 .chip_id = STLINK_CHIPID_STM32_F3, - .description = "F3xx", + .description = "F302/F303/F358", .flash_type = STLINK_FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7cc, .flash_pagesize = 0x800, @@ -300,10 +325,10 @@ static const struct stlink_chipid_params devices[] = { .flags = CHIP_F_HAS_SWO_TRACING, }, { - // This is STK32F373VCT6 device from STM32 F373 eval board - // Support based on 303 above (37x and 30x have same memory map) + // STM32F373Cx/Rx/Vx, STM32F378Cx/Rx/Vx + // RM0313 .chip_id = STLINK_CHIPID_STM32_F37x, - .description = "F3xx", + .description = "F37x", .flash_type = STLINK_FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7cc, .flash_pagesize = 0x800, @@ -315,8 +340,10 @@ static const struct stlink_chipid_params devices[] = { .flags = CHIP_F_HAS_SWO_TRACING, }, { + // STM32F1xx high-density value line devices + // RM0041 .chip_id = STLINK_CHIPID_STM32_F1_VL_HIGH, - .description = "F1xx High-density value line", + .description = "F1xx HD VL", .flash_type = STLINK_FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7e0, .flash_pagesize = 0x800, @@ -328,8 +355,10 @@ static const struct stlink_chipid_params devices[] = { .flags = CHIP_F_HAS_SWO_TRACING, }, { + // STM32F1xx XL-density devices + // RM0008 .chip_id = STLINK_CHIPID_STM32_F1_XL, - .description = "F1xx XL-density", + .description = "F1xx XL", .flash_type = STLINK_FLASH_TYPE_F1_XL, .flash_size_reg = 0x1ffff7e0, .flash_pagesize = 0x800, @@ -339,8 +368,8 @@ static const struct stlink_chipid_params devices[] = { .flags = CHIP_F_HAS_SWO_TRACING, }, { - // Use this as an example for mapping future chips: - // RM0091 document was used to find these paramaters + // STM32F07x + // RM0091 .chip_id = STLINK_CHIPID_STM32_F0_CAN, .description = "F07x", .flash_type = STLINK_FLASH_TYPE_F0, @@ -354,8 +383,8 @@ static const struct stlink_chipid_params devices[] = { .option_size = 16, }, { - // Use this as an example for mapping future chips: - // RM0091 document was used to find these paramaters + // STM32F05x + // RM0091 .chip_id = STLINK_CHIPID_STM32_F0, .description = "F05x", .flash_type = STLINK_FLASH_TYPE_F0, @@ -369,8 +398,8 @@ static const struct stlink_chipid_params devices[] = { .option_size = 16, }, { - // RM0402 document was used to find these parameters - // Table 4. + // STM32F412 + // RM0402 .chip_id = STLINK_CHIPID_STM32_F412, .description = "F412", .flash_type = STLINK_FLASH_TYPE_F4, @@ -383,10 +412,10 @@ static const struct stlink_chipid_params devices[] = { .flags = CHIP_F_HAS_SWO_TRACING, }, { - // RM0430 DocID029473 Rev 2 document was used to find these parameters - // Figure 2, Table 4, Table 5, Section 35.2 + // STM32F413/F423 + // RM0430 (rev 2) .chip_id = STLINK_CHIPID_STM32_F413, - .description = "F413", + .description = "F413/F423", .flash_type = STLINK_FLASH_TYPE_F4, .flash_size_reg = 0x1FFF7A22, // "Flash size data register" Section 35.2 .flash_pagesize = @@ -400,8 +429,10 @@ static const struct stlink_chipid_params devices[] = { .flags = CHIP_F_HAS_SWO_TRACING, }, { + // STM32F09x + // RM0091 .chip_id = STLINK_CHIPID_STM32_F09X, - .description = "F09X", + .description = "F09x", .flash_type = STLINK_FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) .flash_pagesize = 0x800, // Page sizes listed in Table 4 (pg 56) @@ -413,8 +444,8 @@ static const struct stlink_chipid_params devices[] = { .option_size = 16, }, { - // Use this as an example for mapping future chips: - // RM0091 document was used to find these paramaters + // STM32F04x + // RM0091 .chip_id = STLINK_CHIPID_STM32_F04, .description = "F04x", .flash_type = STLINK_FLASH_TYPE_F0, @@ -428,8 +459,8 @@ static const struct stlink_chipid_params devices[] = { .option_size = 16, }, { - // Use this as an example for mapping future chips: - // RM0091 document was used to find these paramaters + // STM32F03x + // RM0091 .chip_id = STLINK_CHIPID_STM32_F0_SMALL, .description = "F03x", .flash_type = STLINK_FLASH_TYPE_F0, @@ -443,9 +474,10 @@ static const struct stlink_chipid_params devices[] = { .option_size = 16, }, { - // STM32F30x + // STM32F301x6/8, STM32F318x8, STM32F302x6x8 + // RM0366, RM0365 .chip_id = STLINK_CHIPID_STM32_F3_SMALL, - .description = "F3xx small", + .description = "F301/F302/F318", .flash_type = STLINK_FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7cc, .flash_pagesize = 0x800, @@ -457,10 +489,10 @@ static const struct stlink_chipid_params devices[] = { .flags = CHIP_F_HAS_SWO_TRACING, }, { - // STM32L0x - // RM0367,RM0377 documents was used to find these parameters + // STM32L0xx Category 3 + // RM0367, RM0377, RM0451 .chip_id = STLINK_CHIPID_STM32_L0, - .description = "L0x3", + .description = "L0xx Cat.3", .flash_type = STLINK_FLASH_TYPE_L0, .flash_size_reg = 0x1ff8007c, .flash_pagesize = 0x80, @@ -472,9 +504,9 @@ static const struct stlink_chipid_params devices[] = { }, { // STM32L0x Category 5 - // RM0367,RM0377 documents was used to find these parameters + // RM0367, RM0377, RM0451 .chip_id = STLINK_CHIPID_STM32_L0_CAT5, - .description = "L0xx Category 5", + .description = "L0xx Cat.5", .flash_type = STLINK_FLASH_TYPE_L0, .flash_size_reg = 0x1ff8007c, .flash_pagesize = 0x80, @@ -483,12 +515,13 @@ static const struct stlink_chipid_params devices[] = { .bootrom_size = 0x2000, .option_base = STM32_L0_OPTION_BYTES_BASE, .option_size = 20, + .flags = CHIP_F_HAS_DUAL_BANK, }, { // STM32L0x Category 2 - // RM0367,RM0377 documents was used to find these parameters + // RM0367, RM0377 .chip_id = STLINK_CHIPID_STM32_L0_CAT2, - .description = "L0xx Category 2", + .description = "L0xx Cat.2", .flash_type = STLINK_FLASH_TYPE_L0, .flash_size_reg = 0x1ff8007c, .flash_pagesize = 0x80, @@ -499,10 +532,10 @@ static const struct stlink_chipid_params devices[] = { .option_size = 20, }, { - // STM32F334, STM32F303x6/8, and STM32F328 - // From RM0364 and RM0316 + // STM32F334, STM32F303x6/8, STM32F328 + // RM0364, RM0316 .chip_id = STLINK_CHIPID_STM32_F334, - .description = "F334 medium density", // (RM0316 sec 33.6.1) + .description = "F303/F328/F334", // (RM0316 sec 33.6.1) .flash_type = STLINK_FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7cc, .flash_pagesize = 0x800, @@ -514,10 +547,10 @@ static const struct stlink_chipid_params devices[] = { .flags = CHIP_F_HAS_SWO_TRACING, }, { - // This is STK32F303RET6 device from STM32 F3 Nucelo board. - // Support based on DM00043574.pdf (RM0316) document rev 5. + // STM32F303xD/E, STM32F398xE, STM32F302xD/E + // RM0316 (rev 5), RM0365 .chip_id = STLINK_CHIPID_STM32_F303_HIGH, - .description = "F303 high density", + .description = "F302/F303/F398", .flash_type = STLINK_FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7cc, // 34.2.1 Flash size data register .flash_pagesize = 0x800, // 4.2.1 Flash memory organization @@ -529,10 +562,10 @@ static const struct stlink_chipid_params devices[] = { .flags = CHIP_F_HAS_SWO_TRACING, }, { - // STM32L4x6 - // From RM0351. + // STM32L47x/L48x + // RM0351 .chip_id = STLINK_CHIPID_STM32_L4, - .description = "L4xx", + .description = "L47x/L48x", .flash_type = STLINK_FLASH_TYPE_L4, .flash_size_reg = 0x1FFF75e0, // "Flash size data register" (sec 45.2, page 1671) @@ -552,24 +585,41 @@ static const struct stlink_chipid_params devices[] = { }, { // STM32L4RX - // From DM00310109.pdf + // RM0432 .chip_id = STLINK_CHIPID_STM32_L4RX, - .description = "L4Rx", + .description = "L4Rx/L4Sx", .flash_type = STLINK_FLASH_TYPE_L4, .flash_size_reg = - 0x1fff75e0, // "Flash size data register" (sec 52.2, page 2049) - .flash_pagesize = 0x1000, // 4k, section 3.3, pg 97 + 0x1fff75e0, // "Flash size data register" (sec 58.2, page 2274) + .flash_pagesize = 0x1000, // 4k, section 3.3, pg 117-120 + //TODO: flash_pagesize can be 8k depend on the dual-bank mode and flash size .sram_size = 0xa0000, // 192k (SRAM1) + 64k SRAM2 + 384k SRAM3 = 640k, or 0xA0000 - .bootrom_base = 0x1fff0000, // 3.3.1, pg 99 - .bootrom_size = 0x7000, // 28k (per bank), same source as base (pg 99) - .flags = CHIP_F_HAS_SWO_TRACING, + .bootrom_base = 0x1fff0000, // 3.3.1, pg 117 + .bootrom_size = 0x7000, // 28k (per bank), same source as base (pg 117) + .flags = CHIP_F_HAS_DUAL_BANK | CHIP_F_HAS_SWO_TRACING, + }, + { + // STM32L4PX + // RM0432 + .chip_id = STLINK_CHIPID_STM32_L4PX, + .description = "L4Px", + .flash_type = STLINK_FLASH_TYPE_L4, + .flash_size_reg = + 0x1fff75e0, // "Flash size data register" (sec 58.2, page 2274) + .flash_pagesize = 0x1000, // 4k, section 3.3, pg 117-120 + //TODO: flash_pagesize can be 8k depend on the dual-bank mode and flash size + .sram_size = + 0xa0000, // 192k (SRAM1) + 64k SRAM2 + 384k SRAM3 = 640k, or 0xA0000 + .bootrom_base = 0x1fff0000, // 3.3.1, pg 117 + .bootrom_size = 0x7000, // 28k (per bank), same source as base (pg 117) + .flags = CHIP_F_HAS_DUAL_BANK | CHIP_F_HAS_SWO_TRACING, }, { // STLINK_CHIPID_STM32_L41X - // From RM0394 Rev 4 and DS12469 Rev 5 + // RM0394 (rev 4), DS12469 (rev 5) .chip_id = STLINK_CHIPID_STM32_L41X, - .description = "L41x", + .description = "L41x/L42x", .flash_type = STLINK_FLASH_TYPE_L4, .flash_size_reg = 0x1fff75e0, // "Flash size data register" (RM0394, // sec 47.2, page 1586) @@ -585,7 +635,7 @@ static const struct stlink_chipid_params devices[] = { }, { // STLINK_CHIPID_STM32_L43X - // From RM0392. + // RM0392 .chip_id = STLINK_CHIPID_STM32_L43X, .description = "L43x/L44x", .flash_type = STLINK_FLASH_TYPE_L4, @@ -607,9 +657,9 @@ static const struct stlink_chipid_params devices[] = { }, { // STLINK_CHIPID_STM32_L496X - // Support based on en.DM00083560.pdf (RM0351) document rev 5. + // RM0351 (rev 5) .chip_id = STLINK_CHIPID_STM32_L496X, - .description = "L496x/L4A6x", + .description = "L49x/L4Ax", .flash_type = STLINK_FLASH_TYPE_L4, .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 49.2, page 1809) @@ -626,7 +676,7 @@ static const struct stlink_chipid_params devices[] = { }, { // STLINK_CHIPID_STM32_L46X - // From RM0394 (updated version of RM0392?). + // RM0394 (updated version of RM0392?) .chip_id = STLINK_CHIPID_STM32_L46X, .description = "L45x/46x", .flash_type = STLINK_FLASH_TYPE_L4, @@ -645,7 +695,8 @@ static const struct stlink_chipid_params devices[] = { .flags = CHIP_F_HAS_SWO_TRACING, }, { - // STM32L011 + // STM32L0xx Category 1 + // RM0451, RM0377 .chip_id = STLINK_CHIPID_STM32_L011, .description = "L01x/L02x", .flash_type = STLINK_FLASH_TYPE_L0, @@ -656,61 +707,67 @@ static const struct stlink_chipid_params devices[] = { .bootrom_size = 0x2000, }, { - // STM32G030/031/041 (from RM0454 & RM0444) + // STM32G030/031/041 + // RM0454, RM0444 .chip_id = STLINK_CHIPID_STM32_G0_CAT1, - .description = "G030/G031/G041", + .description = "G03x/G04x", .flash_type = STLINK_FLASH_TYPE_G0, .flash_size_reg = 0x1FFF75E0, // Section 38.2 .flash_pagesize = 0x800, // 2k (sec 3.2) .sram_size = 0x2000, // 8k (sec 2.3) .bootrom_base = 0x1fff0000, - .bootrom_size = 0x2000, // 8k (sec 2.2.2 table 5 on RM0444 & table 4 on RM0454) + .bootrom_size = 0x2000, // 8k (sec 2.2.2 table 3) .option_base = STM32_G0_OPTION_BYTES_BASE, .option_size = 4, }, { - // STM32G070/071/081 (from RM0454 & RM0444) + // STM32G071/081 + // RM0444 .chip_id = STLINK_CHIPID_STM32_G0_CAT2, - .description = "G070/G071/G081", + .description = "G07x/G08x", .flash_type = STLINK_FLASH_TYPE_G0, .flash_size_reg = 0x1FFF75E0, // Section 38.2 .flash_pagesize = 0x800, // 2k (sec 3.2) .sram_size = 0x9000, // 36k (sec 2.3) .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7000, // 28k (sec 2.2.2 table 3 on RM0444 & table 3 on RM0454) + .bootrom_size = 0x7000, // 28k (sec 2.2.2 table 2) .option_base = STM32_G0_OPTION_BYTES_BASE, .option_size = 4, - }, + }, { - // STM32G0B0/0B1/0C1 (from RM0454 & RM0444) + // STM32G0B1/G0C1 + // RM0444 .chip_id = STLINK_CHIPID_STM32_G0_CAT3, - .description = "G0B0/G0B1/G0C1", + .description = "G0Bx/G0Cx", .flash_type = STLINK_FLASH_TYPE_G0, - .flash_size_reg = 0x1FFF75E0, // Section 38.2 - .flash_pagesize = 0x800, // 2k (sec 3.2) - .sram_size = 0x24000, // 144k (sec 2.3) + .flash_size_reg = 0x1FFF75E0, // Section 38.2 + .flash_pagesize = 0x800, // 2k (sec 3.2) + .sram_size = 0x9000, // 36k (sec 2.3) .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7000, // 28k (sec 2.2.2 table 2 on RM0444 & table 2 on RM0454) + .bootrom_size = 0x7000, // 28k (sec 2.2.2 table 2) .option_base = STM32_G0_OPTION_BYTES_BASE, .option_size = 4, + .flags = CHIP_F_HAS_DUAL_BANK, }, { - // STM32G050/051/061 (from RM0454 & RM0444) + // STM32G051/G061 + // RM0444 .chip_id = STLINK_CHIPID_STM32_G0_CAT4, - .description = "G050/G051/G061", + .description = "G05x/G06x", .flash_type = STLINK_FLASH_TYPE_G0, - .flash_size_reg = 0x1FFF75E0, // Section 38.2 - .flash_pagesize = 0x800, // 2k (sec 3.2) - .sram_size = 0x4800, // 18k (sec 2.3) + .flash_size_reg = 0x1FFF75E0, // Section 38.2 + .flash_pagesize = 0x800, // 2k (sec 3.2) + .sram_size = 0x9000, // 36k (sec 2.3) .bootrom_base = 0x1fff0000, - .bootrom_size = 0x2000, // 8k (sec 2.2.2 table 4 on RM0444 & table 4 on RM0454) + .bootrom_size = 0x7000, // 28k (sec 2.2.2 table 2) .option_base = STM32_G0_OPTION_BYTES_BASE, .option_size = 4, }, { - // STM32G431/441 (from RM0440) + // STM32G431/441 + // RM0440 .chip_id = STLINK_CHIPID_STM32_G4_CAT2, - .description = "G4 Category-2", + .description = "G43x/G44x", .flash_type = STLINK_FLASH_TYPE_G4, .flash_size_reg = 0x1FFF75E0, // Section 47.2 .flash_pagesize = @@ -726,9 +783,10 @@ static const struct stlink_chipid_params devices[] = { .flags = CHIP_F_HAS_SWO_TRACING, }, { - // STM32G471/473/474/483/484 (from RM0440) + // STM32G471/473/474/483/484 + // RM0440 .chip_id = STLINK_CHIPID_STM32_G4_CAT3, - .description = "G4 Category-3", + .description = "G47x/G48x", .flash_type = STLINK_FLASH_TYPE_G4, .flash_size_reg = 0x1FFF75E0, // Section 47.2 .flash_pagesize = @@ -736,7 +794,7 @@ static const struct stlink_chipid_params devices[] = { // SRAM1 is 80k at 0x20000000 // SRAM2 is 16k at 0x20014000 // SRAM3/CCM is 32k at 0x10000000, aliased at 0x20018000 - .sram_size = 0x18000, // 128k (sec 2.4) + .sram_size = 0x20000, // 128k (sec 2.4) .bootrom_base = 0x1fff0000, .bootrom_size = 0x7000, // 28k (table 2) .option_base = STM32_G4_OPTION_BYTES_BASE, @@ -744,9 +802,29 @@ static const struct stlink_chipid_params devices[] = { .flags = CHIP_F_HAS_DUAL_BANK | CHIP_F_HAS_SWO_TRACING, }, { - // STM32WB55 (from RM0434) + // STM32G491/G4A1 + // RM0440 + .chip_id = STLINK_CHIPID_STM32_G4_CAT4, + .description = "G49x/G4Ax", + .flash_type = STLINK_FLASH_TYPE_G4, + .flash_size_reg = 0x1FFF75E0, // Section 47.2 + .flash_pagesize = + 0x800, // 2k (sec 3.3.1) + // SRAM1 is 80k at 0x20000000 + // SRAM2 is 16k at 0x20014000 + // SRAM3/CCM is 32k at 0x10000000, aliased at 0x20018000 + .sram_size = 0x1C000, // 112k (sec 2.4) + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x7000, // 28k (table 2) + .option_base = STM32_G4_OPTION_BYTES_BASE, + .option_size = 4, + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + // STM32WB55xx, STM32WB35xx, STM32WB50CG/30CE + // RM0434, RM0471 .chip_id = STLINK_CHIPID_STM32_WB55, - .description = "WB55", + .description = "WB5x/3x", .flash_type = STLINK_FLASH_TYPE_WB, .flash_size_reg = 0x1FFF75E0, .flash_pagesize = 0x1000, // 4k @@ -772,7 +850,8 @@ static const struct stlink_chipid_params devices[] = { .flags = CHIP_F_HAS_DUAL_BANK | CHIP_F_HAS_SWO_TRACING, }, { - // STM32H7A3/7B3 (from RM0455) + // STM32H7A3/7B3 + // RM0455 .chip_id = STLINK_CHIPID_STM32_H7AX, .description = "H7Ax/H7Bx", .flash_type = STLINK_FLASH_TYPE_H7, @@ -788,7 +867,8 @@ static const struct stlink_chipid_params devices[] = { .flags = CHIP_F_HAS_DUAL_BANK | CHIP_F_HAS_SWO_TRACING, }, { - // STM32H72x/H73x (from RM0468) + // STM32H72x/H73x + // RM0468 .chip_id = STLINK_CHIPID_STM32_H72X, .description = "H72x/H73x", .flash_type = STLINK_FLASH_TYPE_H7, diff --git a/src/stlink-lib/chipid.h b/src/stlink-lib/chipid.h index 16a6a5797..b240ecf72 100644 --- a/src/stlink-lib/chipid.h +++ b/src/stlink-lib/chipid.h @@ -37,9 +37,6 @@ enum stlink_stm32_chipids { STLINK_CHIPID_STM32_F4_DE = 0x433, STLINK_CHIPID_STM32_F4_DSI = 0x434, STLINK_CHIPID_STM32_L43X = 0x435, /* covers STM32L43xxx and STM32L44xxx devices */ - STLINK_CHIPID_STM32_L496X = 0x461, /* covers STM32L496xx and STM32L4A6xx devices */ - STLINK_CHIPID_STM32_L46X = 0x462, /* covers STM32L45xxx and STM32L46xxx devices */ - STLINK_CHIPID_STM32_L41X = 0x464, /* covers STM32L41xxx and STM32L42xxx devices */ STLINK_CHIPID_STM32_L1_HIGH = 0x436, /* assigned to some L1 "Medium-Plus" and "High" chips */ STLINK_CHIPID_STM32_L152_RE = 0x437, STLINK_CHIPID_STM32_F334 = 0x438, @@ -52,20 +49,25 @@ enum stlink_stm32_chipids { STLINK_CHIPID_STM32_F303_HIGH = 0x446, STLINK_CHIPID_STM32_L0_CAT5 = 0x447, STLINK_CHIPID_STM32_F0_CAN = 0x448, - STLINK_CHIPID_STM32_F7 = 0x449, /* ID found on the NucleoF746ZG board */ + STLINK_CHIPID_STM32_F7 = 0x449, STLINK_CHIPID_STM32_H74XXX = 0x450, /* Found on page 3189 in the RM0433*/ STLINK_CHIPID_STM32_F7XXXX = 0x451, - STLINK_CHIPID_STM32_F72XXX = 0x452, /* ID found on the NucleoF722ZE board */ - STLINK_CHIPID_STM32_G0_CAT4 = 0x456, /* G050/G051/G061 found on RM0444/RM0454 */ + STLINK_CHIPID_STM32_F72XXX = 0x452, + STLINK_CHIPID_STM32_G0_CAT4 = 0x456, /* G051/G061 */ STLINK_CHIPID_STM32_L011 = 0x457, STLINK_CHIPID_STM32_F410 = 0x458, STLINK_CHIPID_STM32_G0_CAT2 = 0x460, /* G070/G071/081 */ + STLINK_CHIPID_STM32_L496X = 0x461, /* covers STM32L496xx and STM32L4A6xx devices */ + STLINK_CHIPID_STM32_L46X = 0x462, /* covers STM32L45xxx and STM32L46xxx devices */ STLINK_CHIPID_STM32_F413 = 0x463, + STLINK_CHIPID_STM32_L41X = 0x464, /* covers STM32L41xxx and STM32L42xxx devices */ STLINK_CHIPID_STM32_G0_CAT1 = 0x466, /* G030/G031/041 */ - STLINK_CHIPID_STM32_G0_CAT3 = 0x467, /* G0B0/G0B1/G0C1 found on RM0444/RM0454 */ + STLINK_CHIPID_STM32_G0_CAT3 = 0x467, /* G0B1/G0C1 */ STLINK_CHIPID_STM32_G4_CAT2 = 0x468, /* See: RM 0440 s46.6.1 "MCU device ID code" */ STLINK_CHIPID_STM32_G4_CAT3 = 0x469, - STLINK_CHIPID_STM32_L4RX = 0x470, /* ID found on the STM32L4R9I-DISCO board */ + STLINK_CHIPID_STM32_L4RX = 0x470, /* RM0432, p. 2247 */ + STLINK_CHIPID_STM32_L4PX = 0x471, /* RM0432, p. 2247 */ + STLINK_CHIPID_STM32_G4_CAT4 = 0x479, STLINK_CHIPID_STM32_H7AX = 0x480, /* RM0455, p. 2863 */ STLINK_CHIPID_STM32_H72X = 0x483, /* RM0468, p. 3199 */ STLINK_CHIPID_STM32_WB55 = 0x495 From b93f8b220467247af799f6c094cc08972422ae3d Mon Sep 17 00:00:00 2001 From: anton Date: Mon, 24 May 2021 23:10:26 +0500 Subject: [PATCH 277/503] Added half page write fallback for stm32L0/L1 --- src/common.c | 55 ++++++++++++++++++++++++++------------------ src/stlink-lib/usb.c | 6 +++++ 2 files changed, 38 insertions(+), 23 deletions(-) diff --git a/src/common.c b/src/common.c index 6333ff408..2d200ba27 100644 --- a/src/common.c +++ b/src/common.c @@ -1994,13 +1994,6 @@ int stlink_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { int stlink_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len) { DLOG("*** stlink_write_mem8 ***\n"); - - if (len > 0x40) { // !!! never ever: Writing more then 0x40 bytes gives - // unexpected behaviour - ELOG("Data length > 64: +%d byte.\n", len); - return (-1); - } - return (sl->backend->write_mem8(sl, addr, len)); } @@ -3080,11 +3073,13 @@ int stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, int stm32l1_write_half_pages(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint32_t len, uint32_t pagesize) { - unsigned int count; + unsigned int count, size; unsigned int num_half_pages = len / pagesize; uint32_t val; uint32_t flash_regs_base = get_stm32l0_flash_base(sl); flash_loader_t fl; + bool use_loader = false; + int ret = 0; ILOG("Starting Half page flash write for STM32L core id\n"); @@ -3105,17 +3100,34 @@ int stm32l1_write_half_pages(stlink_t *sl, stm32_addr_t addr, uint8_t *base, wait_flash_busy(sl); for (count = 0; count < num_half_pages; count++) { - if (stlink_flash_loader_run(sl, &fl, addr + count * pagesize, - base + count * pagesize, pagesize) == -1) { + if (use_loader) { + ret = stlink_flash_loader_run(sl, &fl, addr + count * pagesize, + base + count * pagesize, pagesize); + if (ret && count == 0) { + /* It seems that stm32lx devices have a problem when it is blank */ + WLOG("Failed to use flash loader, fallback to soft write\n"); + use_loader = false; + } + } + if (!use_loader) { + if ((pagesize%64) != 0) { + ELOG("Page size not supported\n"); + break; + } + ret = 0; + for (size = 0; size < pagesize && !ret; size += 64) + { + memcpy(sl->q_buf, base + count * pagesize + size, 64); + ret = stlink_write_mem8(sl, addr + count * pagesize + size, 64); + } + } + + if (ret) { WLOG("l1_stlink_flash_loader_run(%#x) failed! == -1\n", addr + count * pagesize); - stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); - val &= ~((1 << FLASH_L1_FPRG) | (1 << FLASH_L1_PROG)); - stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); - return (-1); + break; } - // wait for sr.busy to be cleared if (sl->verbose >= 1) { // show progress; writing procedure is slow and previous errors are // misleading @@ -3123,16 +3135,14 @@ int stm32l1_write_half_pages(stlink_t *sl, stm32_addr_t addr, uint8_t *base, fflush(stdout); } + // wait for sr.busy to be cleared wait_flash_busy(sl); } stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); - val &= ~(1 << FLASH_L1_PROG); + val &= ~((1 << FLASH_L1_FPRG) | (1 << FLASH_L1_PROG)); stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); - stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); - val &= ~(1 << FLASH_L1_FPRG); - stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); - return (0); + return (ret); } int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { @@ -3341,9 +3351,8 @@ int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, off = 0; if (len > pagesize) { - if (stm32l1_write_half_pages(sl, addr, base, len, pagesize) == -1) { - // this may happen on a blank device! - WLOG("\nwrite_half_pages failed == -1\n"); + if (stm32l1_write_half_pages(sl, addr, base, len, pagesize)) { + return (-1); } else { off = (size_t)(len / pagesize) * pagesize; } diff --git a/src/stlink-lib/usb.c b/src/stlink-lib/usb.c index a58681702..1d50bb202 100644 --- a/src/stlink-lib/usb.c +++ b/src/stlink-lib/usb.c @@ -328,6 +328,12 @@ int _stlink_usb_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len) { unsigned char* const cmd = sl->c_buf; int i, ret; + if ((sl->version.jtag_api < STLINK_JTAG_API_V3 && len > 64) || + (sl->version.jtag_api >= STLINK_JTAG_API_V3 && len > 512)) { + ELOG("WRITEMEM_32BIT: bulk packet limits exceeded (data len %d byte)\n", len); + return (-1); + } + i = fill_command(sl, SG_DXFER_TO_DEV, 0); cmd[i++] = STLINK_DEBUG_COMMAND; cmd[i++] = STLINK_DEBUG_WRITEMEM_8BIT; From 293db13e1daa2c77295a3460a0d46d0ffbd7c82b Mon Sep 17 00:00:00 2001 From: anton Date: Tue, 25 May 2021 22:25:29 +0500 Subject: [PATCH 278/503] Changed the half page write fallback to 32 bit write mode --- src/common.c | 36 ++++++++++++++++-------------------- 1 file changed, 16 insertions(+), 20 deletions(-) diff --git a/src/common.c b/src/common.c index 2d200ba27..d2387d08b 100644 --- a/src/common.c +++ b/src/common.c @@ -3073,27 +3073,18 @@ int stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, int stm32l1_write_half_pages(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint32_t len, uint32_t pagesize) { - unsigned int count, size; + unsigned int count, off; unsigned int num_half_pages = len / pagesize; - uint32_t val; + uint32_t val, data; uint32_t flash_regs_base = get_stm32l0_flash_base(sl); flash_loader_t fl; - bool use_loader = false; + bool use_loader = true; int ret = 0; - ILOG("Starting Half page flash write for STM32L core id\n"); - - /* Flash loader initialisation */ - if (stlink_flash_loader_init(sl, &fl) == -1) { - WLOG("stlink_flash_loader_init() == -1\n"); - return (-1); - } - - // unlock already done + // enable half page write stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); val |= (1 << FLASH_L1_FPRG); stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); - val |= (1 << FLASH_L1_PROG); stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); @@ -3110,15 +3101,11 @@ int stm32l1_write_half_pages(stlink_t *sl, stm32_addr_t addr, uint8_t *base, } } if (!use_loader) { - if ((pagesize%64) != 0) { - ELOG("Page size not supported\n"); - break; - } ret = 0; - for (size = 0; size < pagesize && !ret; size += 64) + for (off = 0; off < pagesize && !ret; off += 4) { - memcpy(sl->q_buf, base + count * pagesize + size, 64); - ret = stlink_write_mem8(sl, addr + count * pagesize + size, 64); + write_uint32((unsigned char *)&data, *(uint32_t *)(base + count * pagesize + off)); + ret = stlink_write_debug32(sl, addr + count * pagesize + off, data); } } @@ -3139,6 +3126,7 @@ int stm32l1_write_half_pages(stlink_t *sl, stm32_addr_t addr, uint8_t *base, wait_flash_busy(sl); } + // disable half page write stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); val &= ~((1 << FLASH_L1_FPRG) | (1 << FLASH_L1_PROG)); stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); @@ -3246,6 +3234,12 @@ int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { ELOG("pecr.prglock not clear\n"); return (-1); } + + /* Flash loader initialisation */ + if (stlink_flash_loader_init(sl, fl) == -1) { + ELOG("stlink_flash_loader_init() == -1\n"); + return (-1); + } } else if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || (sl->flash_type == STLINK_FLASH_TYPE_F1_XL)) { ILOG("Starting Flash write for VL/F0/F3/F1_XL\n"); @@ -3348,6 +3342,8 @@ int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, pagesize = L1_WRITE_BLOCK_SIZE; } + DLOG("Starting %3u page write\r\n", (unsigned int)(len / sl->flash_pgsz)); + off = 0; if (len > pagesize) { From 9acf539c70e35643be2dc63b0789ff86d878615a Mon Sep 17 00:00:00 2001 From: anton Date: Wed, 26 May 2021 23:04:39 +0500 Subject: [PATCH 279/503] Optimizing the half page write fallback --- src/common.c | 23 ++++++++++++----------- src/stlink-lib/flash_loader.c | 10 +++++++--- src/stlink-lib/usb.c | 32 +++++++++++++++++++------------- 3 files changed, 38 insertions(+), 27 deletions(-) diff --git a/src/common.c b/src/common.c index d2387d08b..6d81bf743 100644 --- a/src/common.c +++ b/src/common.c @@ -2636,20 +2636,21 @@ int stlink_fread(stlink_t *sl, const char *path, bool is_ihex, int write_buffer_to_sram(stlink_t *sl, flash_loader_t *fl, const uint8_t *buf, size_t size) { // write the buffer right after the loader + int ret = 0; size_t chunk = size & ~0x3; size_t rem = size & 0x3; if (chunk) { memcpy(sl->q_buf, buf, chunk); - stlink_write_mem32(sl, fl->buf_addr, chunk); + ret = stlink_write_mem32(sl, fl->buf_addr, chunk); } - if (rem) { + if (rem && !ret) { memcpy(sl->q_buf, buf + chunk, rem); - stlink_write_mem8(sl, (fl->buf_addr) + (uint32_t)chunk, rem); + ret = stlink_write_mem8(sl, (fl->buf_addr) + (uint32_t)chunk, rem); } - return (0); + return (ret); } uint32_t calculate_F4_sectornum(uint32_t flashaddr) { @@ -3075,7 +3076,7 @@ int stm32l1_write_half_pages(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint32_t len, uint32_t pagesize) { unsigned int count, off; unsigned int num_half_pages = len / pagesize; - uint32_t val, data; + uint32_t val; uint32_t flash_regs_base = get_stm32l0_flash_base(sl); flash_loader_t fl; bool use_loader = true; @@ -3102,10 +3103,10 @@ int stm32l1_write_half_pages(stlink_t *sl, stm32_addr_t addr, uint8_t *base, } if (!use_loader) { ret = 0; - for (off = 0; off < pagesize && !ret; off += 4) - { - write_uint32((unsigned char *)&data, *(uint32_t *)(base + count * pagesize + off)); - ret = stlink_write_debug32(sl, addr + count * pagesize + off, data); + for (off = 0; off < pagesize && !ret; off += 64) { + size_t chunk = (pagesize - off > 64) ? 64 : pagesize - off; + memcpy(sl->q_buf, base + count * pagesize + off, chunk); + ret = stlink_write_mem32(sl, addr + count * pagesize + off, chunk); } } @@ -3237,8 +3238,8 @@ int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { /* Flash loader initialisation */ if (stlink_flash_loader_init(sl, fl) == -1) { - ELOG("stlink_flash_loader_init() == -1\n"); - return (-1); + // L0/L1 have fallback to soft write + WLOG("stlink_flash_loader_init() == -1\n"); } } else if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || (sl->flash_type == STLINK_FLASH_TYPE_F1_XL)) { diff --git a/src/stlink-lib/flash_loader.c b/src/stlink-lib/flash_loader.c index d492716db..355223146 100644 --- a/src/stlink-lib/flash_loader.c +++ b/src/stlink-lib/flash_loader.c @@ -14,7 +14,13 @@ #define STM32F0_WDG_KR_KEY_RELOAD 0xAAAA -/* DO NOT MODIFY SOURCECODE DIRECTLY, EDIT ASSEMBLY FILES INSTEAD */ +/* !!! + * !!! DO NOT MODIFY FLASH LOADERS DIRECTLY! + * !!! + * + * Edit assembly files in the '/flashloaders' instead. The sizes of binary + * flash loaders must be aligned by 4 (it's written by stlink_write_mem32) + */ /* flashloaders/stm32f0.s -- compiled with thumb2 */ static const uint8_t loader_code_stm32vl[] = { @@ -322,9 +328,7 @@ int stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t targe DLOG("Running flash loader, write address:%#x, size: %u\n", target, (unsigned int)size); - // TODO: This can never return -1 if (write_buffer_to_sram(sl, fl, buf, size) == -1) { - // IMPOSSIBLE! ELOG("write_buffer_to_sram() == -1\n"); return(-1); } diff --git a/src/stlink-lib/usb.c b/src/stlink-lib/usb.c index 1d50bb202..5e5f042d5 100644 --- a/src/stlink-lib/usb.c +++ b/src/stlink-lib/usb.c @@ -122,16 +122,16 @@ ssize_t send_recv(struct stlink_libusb* handle, int terminate, retry++; continue; } - WLOG("%s wait error (0x%02X)\n", cmd, rxbuf[0]); + DLOG("%s wait error (0x%02X)\n", cmd, rxbuf[0]); break; - case STLINK_DEBUG_ERR_FAULT: WLOG("%s response fault\n", cmd); break; - case STLINK_DEBUG_ERR_AP_FAULT: WLOG("%s access port fault\n", cmd); break; - case STLINK_DEBUG_ERR_DP_FAULT: WLOG("%s debug port fault\n", cmd); break; - case STLINK_DEBUG_ERR_AP_ERROR: WLOG("%s access port error\n", cmd); break; - case STLINK_DEBUG_ERR_DP_ERROR: WLOG("%s debug port error\n", cmd); break; - case STLINK_DEBUG_ERR_WRITE_VERIFY: WLOG("%s verification error\n", cmd); break; - case STLINK_DEBUG_ERR_WRITE: WLOG("%s write error\n", cmd); break; - default: WLOG("%s error (0x%02X)\n", cmd, rxbuf[0]); break; + case STLINK_DEBUG_ERR_FAULT: DLOG("%s response fault\n", cmd); break; + case STLINK_DEBUG_ERR_AP_FAULT: DLOG("%s access port fault\n", cmd); break; + case STLINK_DEBUG_ERR_DP_FAULT: DLOG("%s debug port fault\n", cmd); break; + case STLINK_DEBUG_ERR_AP_ERROR: DLOG("%s access port error\n", cmd); break; + case STLINK_DEBUG_ERR_DP_ERROR: DLOG("%s debug port error\n", cmd); break; + case STLINK_DEBUG_ERR_WRITE_VERIFY: DLOG("%s verification error\n", cmd); break; + case STLINK_DEBUG_ERR_WRITE: DLOG("%s write error\n", cmd); break; + default: DLOG("%s error (0x%02X)\n", cmd, rxbuf[0]); break; } return(-1); @@ -149,7 +149,7 @@ ssize_t send_recv(struct stlink_libusb* handle, int terminate, t = libusb_bulk_transfer(handle->usb_handle, handle->ep_rep, sg_buf, 13, &res, 3000); if (t) { - ELOG("stlink: %s read storage failed: %s\n", cmd, libusb_error_name(t)); + ELOG("%s read storage failed: %s\n", cmd, libusb_error_name(t)); return(-1); } @@ -306,6 +306,12 @@ int _stlink_usb_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { unsigned char* const cmd = sl->c_buf; int i, ret; + if ((sl->version.jtag_api < STLINK_JTAG_API_V3 && len > 64) || + (sl->version.jtag_api >= STLINK_JTAG_API_V3 && len > 512)) { + ELOG("WRITEMEM_32BIT: bulk packet limits exceeded (data len %d byte)\n", len); + return (-1); + } + i = fill_command(sl, SG_DXFER_TO_DEV, len); cmd[i++] = STLINK_DEBUG_COMMAND; cmd[i++] = STLINK_DEBUG_WRITEMEM_32BIT; @@ -330,7 +336,7 @@ int _stlink_usb_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len) { if ((sl->version.jtag_api < STLINK_JTAG_API_V3 && len > 64) || (sl->version.jtag_api >= STLINK_JTAG_API_V3 && len > 512)) { - ELOG("WRITEMEM_32BIT: bulk packet limits exceeded (data len %d byte)\n", len); + ELOG("WRITEMEM_8BIT: bulk packet limits exceeded (data len %d byte)\n", len); return (-1); } @@ -339,11 +345,11 @@ int _stlink_usb_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len) { cmd[i++] = STLINK_DEBUG_WRITEMEM_8BIT; write_uint32(&cmd[i], addr); write_uint16(&cmd[i + 4], len); - ret = send_only(slu, 0, cmd, slu->cmd_len, "WRITEMEM_32BIT"); + ret = send_only(slu, 0, cmd, slu->cmd_len, "WRITEMEM_8BIT"); if (ret == -1) { return(ret); } - ret = send_only(slu, 1, data, len, "WRITEMEM_32BIT"); + ret = send_only(slu, 1, data, len, "WRITEMEM_8BIT"); if (ret == -1) { return(ret); } From 1d35f95ae088472aad3d246800da34b01a7ed720 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Wed, 26 May 2021 23:16:59 +0200 Subject: [PATCH 280/503] Updated chip-id descriptions --- src/stlink-lib/chipid.h | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-) diff --git a/src/stlink-lib/chipid.h b/src/stlink-lib/chipid.h index f1342dd61..75288093a 100644 --- a/src/stlink-lib/chipid.h +++ b/src/stlink-lib/chipid.h @@ -49,23 +49,25 @@ enum stlink_stm32_chipids { STLINK_CHIPID_STM32_F303_HD = 0x446, /* high density */ STLINK_CHIPID_STM32_L0_CAT5 = 0x447, STLINK_CHIPID_STM32_F0_CAN = 0x448, - STLINK_CHIPID_STM32_F7 = 0x449, /* ID found on the NucleoF746ZG board */ + STLINK_CHIPID_STM32_F7 = 0x449, /* ID found on the Nucleo F746ZG board */ STLINK_CHIPID_STM32_H74xxx = 0x450, /* RM0433, p.3189 */ STLINK_CHIPID_STM32_F76xxx = 0x451, - STLINK_CHIPID_STM32_F72xxx = 0x452, /* ID found on the NucleoF722ZE board */ - STLINK_CHIPID_STM32_G0_CAT4 = 0x456, /* G050/G051/G061 found in RM0444/RM0454 */ + STLINK_CHIPID_STM32_F72xxx = 0x452, /* ID found on the Nucleo F722ZE board */ + STLINK_CHIPID_STM32_G0_CAT4 = 0x456, /* G051/G061 */ STLINK_CHIPID_STM32_L011 = 0x457, STLINK_CHIPID_STM32_F410 = 0x458, - STLINK_CHIPID_STM32_G0_CAT2 = 0x460, /* G070/G071/081 */ + STLINK_CHIPID_STM32_G0_CAT2 = 0x460, /* G070/G071/G081 */ STLINK_CHIPID_STM32_L496x_L4A6x = 0x461, STLINK_CHIPID_STM32_L45x_L46x = 0x462, STLINK_CHIPID_STM32_F413 = 0x463, STLINK_CHIPID_STM32_L41x_L42x = 0x464, - STLINK_CHIPID_STM32_G0_CAT1 = 0x466, /* G030/G031/041 */ - STLINK_CHIPID_STM32_G0_CAT3 = 0x467, /* G0B0/G0B1/G0C1 found in RM0444/RM0454 */ + STLINK_CHIPID_STM32_G0_CAT1 = 0x466, /* G030/G031/G041 */ + STLINK_CHIPID_STM32_G0_CAT3 = 0x467, /* G0B1/G0C1 */ STLINK_CHIPID_STM32_G4_CAT2 = 0x468, /* RM0440, s46.6.1 "MCU device ID code" */ STLINK_CHIPID_STM32_G4_CAT3 = 0x469, - STLINK_CHIPID_STM32_L4Rx = 0x470, /* ID found on the STM32L4R9I-DISCO board */ + STLINK_CHIPID_STM32_L4Rx = 0x470, /* RM0432, p. 2247, found on the STM32L4R9I-DISCO board */ + STLINK_CHIPID_STM32_L4PX = 0x471, /* RM0432, p. 2247 */ + STLINK_CHIPID_STM32_G4_CAT4 = 0x479, STLINK_CHIPID_STM32_H7Ax = 0x480, /* RM0455, p.2863 */ STLINK_CHIPID_STM32_H72x = 0x483, /* RM0468, p.3199 */ STLINK_CHIPID_STM32_WB55 = 0x495 From 4949c23771b8348d33719a4275e04861e5068135 Mon Sep 17 00:00:00 2001 From: Anton Date: Fri, 28 May 2021 09:04:57 +0500 Subject: [PATCH 281/503] Fixed clear the H7 dual bank flag --- src/common.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/common.c b/src/common.c index 80190f756..f347fbc46 100644 --- a/src/common.c +++ b/src/common.c @@ -1664,7 +1664,7 @@ int stlink_load_device_params(stlink_t *sl) { // H7 devices with small flash has one bank if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK && sl->flash_type == STLINK_FLASH_TYPE_H7) { - if ((flash_size / sl->flash_pgsz) <= 1) + if ((sl->flash_size / sl->flash_pgsz) <= 1) sl->chip_flags &= ~CHIP_F_HAS_DUAL_BANK; } From 2e6c909c3e1b32340bdc4f2d2fee4bcdfc0a15f1 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 30 May 2021 23:51:12 +0200 Subject: [PATCH 282/503] General Project Update - Removed GitHub-CI VE for Ubuntu 16.04 (deprecated) - Minor fixes for some comments --- .github/workflows/c-cpp.yml | 90 ----------------------------------- doc/devices_boards.md | 2 +- src/stlink-lib/flash_loader.c | 2 +- 3 files changed, 2 insertions(+), 92 deletions(-) diff --git a/.github/workflows/c-cpp.yml b/.github/workflows/c-cpp.yml index f68a9e53c..ee06d5469 100644 --- a/.github/workflows/c-cpp.yml +++ b/.github/workflows/c-cpp.yml @@ -9,96 +9,6 @@ on: jobs: # Linux - job_linux_16_04_64_gcc: - name: ubuntu-16.04 gcc - runs-on: ubuntu-16.04 - steps: - - uses: actions/checkout@v2 - - name: Install dependencies - run: sudo apt-get install gcc-5 libusb-1.0.0-dev libgtk-3-dev rpm - - name: make debug - run: sudo make clean && make debug - - name: make test - run: sudo make clean && make test - - name: make release - run: sudo make clean && make release - - name: sudo make install - run: sudo make clean && sudo make install - - name: sudo make package - run: sudo make package - - name: sudo make uninstall - run: sudo make uninstall && sudo make clean - - job_linux_16_04_32_gcc: - name: ubuntu-16.04 gcc 32-bit - runs-on: ubuntu-16.04 - steps: - - uses: actions/checkout@v2 - - name: Install dependencies - run: sudo apt-get install gcc-5 libusb-1.0.0-dev libgtk-3-dev rpm - - name: Set compiler flags - run: | - CFLAGS="$CFLAGS -m32" - CXXFLAGS="$CXXFLAGS -m32" - LDFLAGS="$LDFLAGS -m32" - - name: make debug - run: sudo make clean && make debug - - name: make test - run: sudo make clean && make test - - name: make release - run: sudo make clean && make release - - name: sudo make install - run: sudo make clean && sudo make install - - name: sudo make package - run: sudo make package - - name: sudo make uninstall - run: sudo make uninstall && sudo make clean - - job_linux_16_04_64_clang: - name: ubuntu-16.04 clang - runs-on: ubuntu-16.04 - steps: - - uses: actions/checkout@v2 - - name: Install dependencies - run: sudo apt-get install clang-3.5 libusb-1.0.0-dev libgtk-3-dev rpm - - name: make debug - run: sudo make clean && make debug - - name: make test - run: sudo make clean && make test - - name: make release - run: sudo make clean && make release - - name: sudo make install - run: sudo make clean && sudo make install - - name: sudo make package - run: sudo make package - - name: sudo make uninstall - run: sudo make uninstall && sudo make clean - - job_linux_16_04_32_clang: - name: ubuntu-16.04 clang 32-bit - runs-on: ubuntu-16.04 - steps: - - uses: actions/checkout@v2 - - name: Install dependencies - run: sudo apt-get install clang-3.5 libusb-1.0.0-dev libgtk-3-dev rpm - - name: Set compiler flags - run: | - CFLAGS="$CFLAGS -m32" - CXXFLAGS="$CXXFLAGS -m32" - LDFLAGS="$LDFLAGS -m32" - - name: make debug - run: sudo make clean && make debug - - name: make test - run: sudo make clean && make test - - name: make release - run: sudo make clean && make release - - name: sudo make install - run: sudo make clean && sudo make install - - name: sudo make package - run: sudo make package - - name: sudo make uninstall - run: sudo make uninstall && sudo make clean - job_linux_18_04_64_gcc: name: ubuntu-18.04 gcc runs-on: ubuntu-18.04 diff --git a/doc/devices_boards.md b/doc/devices_boards.md index 6548bc734..d93ec7a81 100644 --- a/doc/devices_boards.md +++ b/doc/devices_boards.md @@ -51,7 +51,7 @@ Tested non-official ST boards [incl. STLINK programmers]: | ------- | ------------ | ------------- | | 0x411 | STM32F2yyxx | (all devices) | -**STM32F1 / ARM Cortex M3 / Core-ID: 0x2ba01477 (STM3F1c_CORE_ID)** +**STM32F1 / ARM Cortex M3 / Core-ID: 0x2ba01477 (STM32F1c_CORE_ID)** | Product-Code | Chip-ID | STLink
Programmer | Boards | | ------------- | ------- | ---------------------- | ----------------------------------------------------------------------------------------------- | diff --git a/src/stlink-lib/flash_loader.c b/src/stlink-lib/flash_loader.c index d492716db..f013772e3 100644 --- a/src/stlink-lib/flash_loader.c +++ b/src/stlink-lib/flash_loader.c @@ -235,7 +235,7 @@ int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* sl->chip_id == STLINK_CHIPID_STM32_L011 || sl->chip_id == STLINK_CHIPID_STM32_L0 || sl->chip_id == STLINK_CHIPID_STM32_L0_CAT5 || - sl->chip_id == STLINK_CHIPID_STM32_L0_CAT2) { // STM32l + sl->chip_id == STLINK_CHIPID_STM32_L0_CAT2) { loader_code = loader_code_stm32lx; loader_size = sizeof(loader_code_stm32lx); } else if (sl->core_id == STM32VL_CORE_ID || From 007f39333e884b00c01939eb81757dd0d42c3507 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Mon, 31 May 2021 23:35:37 +0200 Subject: [PATCH 283/503] Corrected false character in some defines --- src/stlink-lib/chipid.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index 6fbfce696..8f8f91a9c 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -866,7 +866,7 @@ static struct stlink_chipid_params devices[] = { { // STM32H7A3/7B3 // RM0455 - .chip_id = STLINK_CHIPID_STM32_H7AX, + .chip_id = STLINK_CHIPID_STM32_H7Ax, .description = "H7Ax/H7Bx", .flash_type = STLINK_FLASH_TYPE_H7, .flash_size_reg = 0x08FFF80C, // "Flash size register" (p.2949) @@ -883,7 +883,7 @@ static struct stlink_chipid_params devices[] = { { // STM32H72x/H73x // RM0468 - .chip_id = STLINK_CHIPID_STM32_H72X, + .chip_id = STLINK_CHIPID_STM32_H72x, .description = "H72x/H73x", .flash_type = STLINK_FLASH_TYPE_H7, .flash_size_reg = 0x1FF1E880, // "Flash size register" (p.3286) From 93db93a0ad6ff058d45ef1cccd3a7ece800a5aa4 Mon Sep 17 00:00:00 2001 From: Gustavo Date: Sun, 6 Jun 2021 13:03:59 +0200 Subject: [PATCH 284/503] fix for 'libusb_devices were leaked' when no stlink was found --- src/stlink-lib/usb.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/stlink-lib/usb.c b/src/stlink-lib/usb.c index 2754db06f..68e6302b9 100644 --- a/src/stlink-lib/usb.c +++ b/src/stlink-lib/usb.c @@ -1273,6 +1273,7 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, enum connect_type connect, if (cnt < 0) { WLOG ("Couldn't find %s ST-Link devices\n", (devBus && devAddr) ? "matched" : "any"); + libusb_free_device_list(list, 1); goto on_error; } else { ret = libusb_open(list[cnt], &slu->usb_handle); From ca896108eedde4a1a4c1ce00a1917771757bf514 Mon Sep 17 00:00:00 2001 From: Gustavo Date: Tue, 15 Jun 2021 20:45:19 +0200 Subject: [PATCH 285/503] fix for when the device list was not initialized --- src/stlink-lib/usb.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/stlink-lib/usb.c b/src/stlink-lib/usb.c index 68e6302b9..9f83ace4a 100644 --- a/src/stlink-lib/usb.c +++ b/src/stlink-lib/usb.c @@ -1203,7 +1203,7 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, enum connect_type connect, libusb_set_option(slu->libusb_ctx, LIBUSB_OPTION_LOG_LEVEL, ugly_libusb_log_level(verbose)); #endif - libusb_device **list; + libusb_device **list = NULL; // TODO: We should use ssize_t and use it as a counter if > 0. // As per libusb API: ssize_t libusb_get_device_list (libusb_context *ctx, libusb_device ***list) int cnt = (int)libusb_get_device_list(slu->libusb_ctx, &list); @@ -1232,7 +1232,7 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, enum connect_type connect, ILOG("bus %03d dev %03d\n", devBus, devAddr); } - while (cnt--) { + while (cnt-- > 0) { struct libusb_device_handle *handle; libusb_get_device_descriptor(list[cnt], &desc); From aa70b89b6e33eac460b9e7d0a73231d8a438ee10 Mon Sep 17 00:00:00 2001 From: anton Date: Wed, 23 Jun 2021 22:06:16 +0500 Subject: [PATCH 286/503] WRITEMEM_32BIT: removed checks limit --- src/stlink-lib/usb.c | 6 ------ 1 file changed, 6 deletions(-) diff --git a/src/stlink-lib/usb.c b/src/stlink-lib/usb.c index 5e5f042d5..0a4cfb489 100644 --- a/src/stlink-lib/usb.c +++ b/src/stlink-lib/usb.c @@ -306,12 +306,6 @@ int _stlink_usb_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { unsigned char* const cmd = sl->c_buf; int i, ret; - if ((sl->version.jtag_api < STLINK_JTAG_API_V3 && len > 64) || - (sl->version.jtag_api >= STLINK_JTAG_API_V3 && len > 512)) { - ELOG("WRITEMEM_32BIT: bulk packet limits exceeded (data len %d byte)\n", len); - return (-1); - } - i = fill_command(sl, SG_DXFER_TO_DEV, len); cmd[i++] = STLINK_DEBUG_COMMAND; cmd[i++] = STLINK_DEBUG_WRITEMEM_32BIT; From 88398228a747a72831bcd7e515a965b84a13e79c Mon Sep 17 00:00:00 2001 From: c-grant <60671494+c-grant@users.noreply.github.com> Date: Tue, 13 Jul 2021 22:10:04 -0400 Subject: [PATCH 287/503] Update gdb-server.c --- src/st-util/gdb-server.c | 24 +++++++++++++++++++++++- 1 file changed, 23 insertions(+), 1 deletion(-) diff --git a/src/st-util/gdb-server.c b/src/st-util/gdb-server.c index 6b68c8143..10aaea93a 100644 --- a/src/st-util/gdb-server.c +++ b/src/st-util/gdb-server.c @@ -501,6 +501,24 @@ static const char* const memory_map_template_H7 = " " // bootrom ""; +static const char* const memory_map_template_H72X3X = + "" + "" + "" + " " // ITCMRAM 64kB + Optional remap + " " // DTCMRAM 128kB + " " // RAM D1 320kB + " " // RAM D2 23kB + " " // RAM D3 16kB + " " // Backup RAM 4kB + " " + " 0x%x" + " " + " " // peripheral regs + " " // cortex regs + " " // bootrom + ""; static const char* const memory_map_template_F4_DE = "" @@ -563,7 +581,11 @@ char* make_memory_map(stlink_t *sl) { snprintf(map, sz, memory_map_template_L496, (unsigned int)sl->flash_size, (unsigned int)sl->flash_size); - } else { + } else if (sl->chip_id == STLINK_CHIPID_STM32_H72X) { + snprintf(map, sz, memory_map_template_H72X3X, + (unsigned int)sl->flash_size, + (unsigned int)sl->flash_pgsz); + } else { snprintf(map, sz, memory_map_template, (unsigned int)sl->flash_size, (unsigned int)sl->sram_size, From 2a3c57747fd0caefca37f81f55be43ad175ffa2d Mon Sep 17 00:00:00 2001 From: Anton Date: Thu, 15 Jul 2021 15:59:35 +0500 Subject: [PATCH 288/503] Fixed get flash base address for STM32L152RE --- src/common.c | 43 +++++++++---------------------------------- 1 file changed, 9 insertions(+), 34 deletions(-) diff --git a/src/common.c b/src/common.c index f347fbc46..6cec3fde1 100644 --- a/src/common.c +++ b/src/common.c @@ -241,7 +241,6 @@ // STM32L0x flash register base and offsets RM0090 - DM00031020.pdf #define STM32L0_FLASH_REGS_ADDR ((uint32_t)0x40022000) -#define STM32L1_FLASH_REGS_ADDR ((uint32_t)0x40023c00) #define STM32L0_FLASH_PELOCK (0) #define STM32L0_FLASH_OPTLOCK (2) @@ -450,10 +449,11 @@ static uint32_t get_stm32l0_flash_base(stlink_t *sl) { case STLINK_CHIPID_STM32_L1_MEDIUM: case STLINK_CHIPID_STM32_L1_MEDIUM_PLUS: case STLINK_CHIPID_STM32_L1_HIGH: - return (STM32L1_FLASH_REGS_ADDR); + case STLINK_CHIPID_STM32_L152_RE: + return (STM32L_FLASH_REGS_ADDR); default: - WLOG("Flash base use default L0 address"); + WLOG("Flash base use default L0 address\n"); return (STM32L0_FLASH_REGS_ADDR); } } @@ -3204,15 +3204,7 @@ int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { ILOG("Starting Flash write for L0\n"); uint32_t val; - uint32_t flash_regs_base; - if (sl->chip_id == STLINK_CHIPID_STM32_L0 || - sl->chip_id == STLINK_CHIPID_STM32_L0_CAT5 || - sl->chip_id == STLINK_CHIPID_STM32_L0_CAT2 || - sl->chip_id == STLINK_CHIPID_STM32_L011) { - flash_regs_base = STM32L0_FLASH_REGS_ADDR; - } else { - flash_regs_base = STM32L_FLASH_REGS_ADDR; - } + uint32_t flash_regs_base = get_stm32l0_flash_base(sl); // disable pecr protection stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, @@ -3327,19 +3319,9 @@ int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, } } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { uint32_t val; - uint32_t flash_regs_base; - uint32_t pagesize; - - if (sl->chip_id == STLINK_CHIPID_STM32_L0 || - sl->chip_id == STLINK_CHIPID_STM32_L0_CAT5 || - sl->chip_id == STLINK_CHIPID_STM32_L0_CAT2 || - sl->chip_id == STLINK_CHIPID_STM32_L011) { - flash_regs_base = STM32L0_FLASH_REGS_ADDR; - pagesize = L0_WRITE_BLOCK_SIZE; - } else { - flash_regs_base = STM32L_FLASH_REGS_ADDR; - pagesize = L1_WRITE_BLOCK_SIZE; - } + uint32_t flash_regs_base = get_stm32l0_flash_base(sl); + uint32_t pagesize = (flash_regs_base==STM32L0_FLASH_REGS_ADDR)? + L0_WRITE_BLOCK_SIZE:L1_WRITE_BLOCK_SIZE; off = 0; @@ -3456,15 +3438,8 @@ int stlink_flashloader_stop(stlink_t *sl, flash_loader_t *fl) { lock_flash(sl); } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { uint32_t val; - uint32_t flash_regs_base; - if (sl->chip_id == STLINK_CHIPID_STM32_L0 || - sl->chip_id == STLINK_CHIPID_STM32_L0_CAT5 || - sl->chip_id == STLINK_CHIPID_STM32_L0_CAT2 || - sl->chip_id == STLINK_CHIPID_STM32_L011) { - flash_regs_base = STM32L0_FLASH_REGS_ADDR; - } else { - flash_regs_base = STM32L_FLASH_REGS_ADDR; - } + uint32_t flash_regs_base = get_stm32l0_flash_base(sl); + // reset lock bits stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); val |= (1 << 0) | (1 << 1) | (1 << 2); From 6e0dbfe97250b6ecba1f86c14d91d01c159b812c Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Wed, 16 Jun 2021 13:12:19 +0200 Subject: [PATCH 289/503] Removed Travis CI integration Free Trial plan is no longer usable as credits are used up. --- .travis.sh | 46 ---------------------- .travis.yml | 111 ---------------------------------------------------- 2 files changed, 157 deletions(-) delete mode 100755 .travis.sh delete mode 100644 .travis.yml diff --git a/.travis.sh b/.travis.sh deleted file mode 100755 index d8c5377de..000000000 --- a/.travis.sh +++ /dev/null @@ -1,46 +0,0 @@ -#!/bin/bash -echo "-- C compilers available" -ls -1 /usr/bin/gcc* -ls -1 /usr/bin/clang* -ls -1 /usr/bin/scan-build* -echo "----" - -echo "WORK DIR:$DIR" -DIR=$PWD - -if [ "$TRAVIS_JOB_NAME" == "linux-mingw-64" ]; then - echo "--> Building for Windows (x86-64) ..." - mkdir -p build-mingw && cd build-mingw-64 - cmake -DCMAKE_SYSTEM_NAME=Windows -DTOOLCHAIN_PREFIX=x86_64-w64-mingw32 \ - -DCMAKE_TOOLCHAIN_FILE=$PWD/../cmake/modules/set_toolchain.cmake -DCMAKE_INSTALL_PREFIX=$PWD/install $DIR - make && rm -rf build-mingw-64 && cd - - -elif [ "$TRAVIS_JOB_NAME" == "linux-mingw-32" ]; then - echo "--> Building for Windows (i686) ..." - mkdir -p build-mingw && cd build-mingw-32 - cmake -DCMAKE_SYSTEM_NAME=Windows -DTOOLCHAIN_PREFIX=i686-w64-mingw32 \ - -DCMAKE_TOOLCHAIN_FILE=$PWD/../cmake/modules/set_toolchain.cmake -DCMAKE_INSTALL_PREFIX=$PWD/install $DIR - make && rm -rf build-mingw-32 && cd - - -elif [ "$TRAVIS_OS_NAME" == "osx" ]; then - echo "--> make debug..." - mkdir -p build/Debug && cd build/Debug - cmake -DCMAKE_BUILD_TYPE=Debug -DCMAKE_INSTALL_PREFIX=$PWD/install $DIR - make debug && cd - - - echo "--> make package..." - mkdir -p build/Release && cd build/Release - cmake -DCMAKE_BUILD_TYPE=Release -DCMAKE_INSTALL_PREFIX=$PWD/install $DIR - make package && cd - - -else # local test-build - echo "--> Building Debug..." - mkdir -p build/Debug && cd build/Debug - cmake -DCMAKE_BUILD_TYPE=Debug -DCMAKE_INSTALL_PREFIX=$PWD/install ../../ - make && cd - - - echo "--> Building Release with package..." - mkdir -p build/Release && cd build/Release - cmake -DCMAKE_BUILD_TYPE=Release -DCMAKE_INSTALL_PREFIX=$PWD/install ../../ - make package && cd - -fi diff --git a/.travis.yml b/.travis.yml deleted file mode 100644 index 469094892..000000000 --- a/.travis.yml +++ /dev/null @@ -1,111 +0,0 @@ -language: c - -jobs: - include: - ### cross builds on AMD64 ### - - - os: linux - dist: focal - env: BADGE=linux-mingw-64 - name: linux-mingw - compiler: gcc-10 - addons: - apt: - sources: ["ubuntu-toolchain-r-test"] - packages: - ["gcc-10", "libusb-1.0.0-dev", "libgtk-3-dev", "rpm", "mingw-w64"] - - - os: linux - dist: focal - env: BADGE=linux-mingw-32 - name: linux-mingw - compiler: gcc-10 - addons: - apt: - sources: ["ubuntu-toolchain-r-test"] - packages: - ["gcc-10", "libusb-1.0.0-dev", "libgtk-3-dev", "rpm", "mingw-w64"] - - ### macOS ### - - - os: osx - env: BADGE=osx - osx_image: xcode10.3 # xcode11.3 to xcode11.3.1 fail to compile - name: macOS 10.14.4 gcc - compiler: gcc - addons: - homebrew: - packages: - - gcc - - libusb - - gtk+3 - - - os: osx - env: BADGE=osx - osx_image: xcode10.3 # xcode11.3 to xcode11.3.1 fail to compile - name: macOS 10.14.4 gcc 32-bit - compiler: gcc - addons: - homebrew: - packages: - - gcc - - libusb - - gtk+3 - before_install: - - CFLAGS="$CFLAGS -m32"; CXXFLAGS="$CXXFLAGS -m32"; LDFLAGS="$LDFLAGS -m32"; - - - os: osx - env: BADGE=osx - osx_image: xcode10.3 # xcode11.3 to xcode11.3.1 fail to compile - name: macOS 10.14.4 clang - compiler: clang - addons: - homebrew: - packages: - - clang - - libusb - - gtk+3 - - - os: osx - env: BADGE=osx - osx_image: xcode10.3 # xcode11.3 to xcode11.3.1 fail to compile - name: macOS 10.14.4 clang 32-bit - compiler: clang - addons: - homebrew: - packages: - - clang - - libusb - - gtk+3 - before_install: - - CFLAGS="$CFLAGS -m32"; CXXFLAGS="$CXXFLAGS -m32"; LDFLAGS="$LDFLAGS -m32"; - - - os: osx - env: BADGE=osx - osx_image: xcode12.5 - name: macOS 11.3 gcc - compiler: gcc - addons: - homebrew: - packages: - - gcc - - libusb - - gtk+3 - - - os: osx - env: BADGE=osx - osx_image: xcode12.5 - name: macOS 11.3 clang - compiler: clang - addons: - homebrew: - packages: - - clang - - libusb - - gtk+3 - -script: - - git fetch --tags - - printenv - - cmake --version - - if [[ "$TRAVIS_OS_NAME" == "linux" ]] || [[ "$TRAVIS_OS_NAME" == "osx" ]]; then ./.travis.sh; fi From a52e1bc5489e23f3c1071c6912820efacaa3b22c Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Fri, 16 Jul 2021 16:00:27 +0200 Subject: [PATCH 290/503] Minor bugfixes --- src/common.c | 2 +- src/st-util/gdb-server.c | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/common.c b/src/common.c index 354075d8d..1457d640c 100644 --- a/src/common.c +++ b/src/common.c @@ -449,7 +449,7 @@ static uint32_t get_stm32l0_flash_base(stlink_t *sl) { case STLINK_CHIPID_STM32_L1_MD: case STLINK_CHIPID_STM32_L1_MD_PLUS: case STLINK_CHIPID_STM32_L1_MD_PLUS_HD: - return (STM32L1_FLASH_REGS_ADDR); + return (STM32L_FLASH_REGS_ADDR); default: WLOG("Flash base use default L0 address\n"); diff --git a/src/st-util/gdb-server.c b/src/st-util/gdb-server.c index 2f5ff1143..653c7bcec 100644 --- a/src/st-util/gdb-server.c +++ b/src/st-util/gdb-server.c @@ -503,7 +503,7 @@ static const char* const memory_map_template_H7 = " " // bootrom ""; -static const char* const memory_map_template_H72X3X = +static const char* const memory_map_template_H72x3x = "" "" @@ -583,8 +583,8 @@ char* make_memory_map(stlink_t *sl) { snprintf(map, sz, memory_map_template_L496, (unsigned int)sl->flash_size, (unsigned int)sl->flash_size); - } else if (sl->chip_id == STLINK_CHIPID_STM32_H72X) { - snprintf(map, sz, memory_map_template_H72X3X, + } else if (sl->chip_id == STLINK_CHIPID_STM32_H72x) { + snprintf(map, sz, memory_map_template_H72x3x, (unsigned int)sl->flash_size, (unsigned int)sl->flash_pgsz); } else { From 1dd94a16a8090f17d9c595daf1e899d95c0511ab Mon Sep 17 00:00:00 2001 From: Grzegorz Szymaszek Date: Wed, 28 Jul 2021 16:26:33 +0200 Subject: [PATCH 291/503] Do not segfault if cannot find chip in config files stlink_chipid_get_params() used to segfault on memcmp() when struct stlink_chipid_params *params was NULL. This could happen if either: - there were no chip config files (*.chip), or - process_chipfile() failed to parse chip_id from the chip config files. The latter case is caused by the usage of atoi() to parse the chip id. Since the chip id is stored in hex, atoi() returns 0; such id cannot be matched to any actual chip. The segfault occurs on commit a52e1bc5489e23f3c1071c6912820efacaa3b22c, in file src/stlink-lib/chipid.c:957 (https://github.com/stlink-org/stlink/blob/a52e1bc5489e23f3c1071c6912820efacaa3b22c/src/stlink-lib/chipid.c#L957). Check if params is NULL, in such case, set it to p2, which should not be NULL as long as struct stlink_chipid_params devices[] exists. May fix (workaround) #1163. --- src/stlink-lib/chipid.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index 8f8f91a9c..ebc3f4e20 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -954,7 +954,9 @@ struct stlink_chipid_params *stlink_chipid_get_params(uint32_t chipid) { p2 = stlink_chipid_get_params_old(chipid); #if 1 - if (memcmp (p2, params, sizeof (struct stlink_chipid_params) - sizeof (struct stlink_chipid_params *)) != 0) { + if (params == NULL) { + params = p2; + } else if (memcmp (p2, params, sizeof (struct stlink_chipid_params) - sizeof (struct stlink_chipid_params *)) != 0) { //fprintf (stderr, "Error, chipid params not identical\n"); //return NULL; fprintf(stderr, "---------- old ------------\n"); From 35156b186d7915db52a7fef802d3d10be37bae0b Mon Sep 17 00:00:00 2001 From: Grzegorz Szymaszek Date: Wed, 28 Jul 2021 18:47:25 +0200 Subject: [PATCH 292/503] Drop execute bits from source code files --- src/stlink-lib/md5.c | 0 src/stlink-lib/md5.h | 0 2 files changed, 0 insertions(+), 0 deletions(-) mode change 100755 => 100644 src/stlink-lib/md5.c mode change 100755 => 100644 src/stlink-lib/md5.h diff --git a/src/stlink-lib/md5.c b/src/stlink-lib/md5.c old mode 100755 new mode 100644 diff --git a/src/stlink-lib/md5.h b/src/stlink-lib/md5.h old mode 100755 new mode 100644 From 26a63c11a4125b7c5b3a2677f342cf13c37f1244 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Wed, 28 Jul 2021 22:03:03 +0200 Subject: [PATCH 293/503] [doc] Updated list of devices & boards (Closes #1164) --- doc/devices_boards.md | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/doc/devices_boards.md b/doc/devices_boards.md index d93ec7a81..26bad9150 100644 --- a/doc/devices_boards.md +++ b/doc/devices_boards.md @@ -125,9 +125,12 @@ Tested non-official ST boards [incl. STLINK programmers]: **STM32H7 / ARM Cortex M7F / Core-ID: 0x6ba02477 (STM32H7_CORE_ID)** -| Chip-ID | Product-Code | -| ------- | -------------- | -| 0x450 | STM32H74x/H75x | +| Chip-ID | Product-Code | +| ------- | ------------- | +| 0x450 | STM32H7**4**x | +| 0x450 | STM32H7**5**x | +| 0x480 | STM32H7**A**x | +| 0x480 | STM32H7**B**x | **STM32G0 / ARM Cortex M0+ / Core-ID: 0x0bc11477 (STM32G0_CORE_ID)** @@ -146,6 +149,7 @@ Tested non-official ST boards [incl. STLINK programmers]: | 0x468 | STM32G4**41**xx | | 0x469 | STM32G4**7**xxx | | 0x469 | STM32G4**8**xxx | +| 0x479 | STM32G4**91**xx | **STM32L0 / ARM Cortex M0+ / Core-ID: 0x0bc11477 (STM32L0_CORE_ID)** From b4245eadd0877546a5287a0365211d2d5c24273f Mon Sep 17 00:00:00 2001 From: Grzegorz Szymaszek Date: Thu, 29 Jul 2021 15:46:53 +0200 Subject: [PATCH 294/503] Use proper Markdown headers for supported MCUs Use actual level 2 headers[1] instead of emulating them with bold/strong tags[2]. [1]: https://spec.commonmark.org/0.29/#atx-headings [2]: https://spec.commonmark.org/0.29/#emphasis-and-strong-emphasis --- doc/devices_boards.md | 30 +++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/doc/devices_boards.md b/doc/devices_boards.md index 26bad9150..a8a366448 100644 --- a/doc/devices_boards.md +++ b/doc/devices_boards.md @@ -2,7 +2,7 @@ The following devices are supported by the stlink toolset. -**STM32F0 / ARM Cortex M0 / Core-ID: 0x0bb11477 (STM32F0_CORE_ID)** +## STM32F0 / ARM Cortex M0 / Core-ID: 0x0bb11477 (STM32F0_CORE_ID) | Chip-ID | Product-Code | | ------- | ------------------- | @@ -19,7 +19,7 @@ The following devices are supported by the stlink toolset. | 0x442 | STM32F0**9**xxx | -**STM32F1 / ARM Cortex M3 / Core-ID: 0x1ba01477 (STM32F1_CORE_ID)** +## STM32F1 / ARM Cortex M3 / Core-ID: 0x1ba01477 (STM32F1_CORE_ID) | Product-Code | Product Line | | ----------------- | ----------------------- | @@ -45,20 +45,20 @@ Tested non-official ST boards [incl. STLINK programmers]: - HY-STM32 (STM32F103VETx) [v1, v2] - DecaWave EVB1000 (STM32F105RCTx) [v1, v2] -**STM32F2 / ARM Cortex M3 / Core-ID: 0x2ba01477 (STM32F2_CORE_ID)** +## STM32F2 / ARM Cortex M3 / Core-ID: 0x2ba01477 (STM32F2_CORE_ID) | Chip-ID | Product-Code | Product Line | | ------- | ------------ | ------------- | | 0x411 | STM32F2yyxx | (all devices) | -**STM32F1 / ARM Cortex M3 / Core-ID: 0x2ba01477 (STM32F1c_CORE_ID)** +## STM32F1 / ARM Cortex M3 / Core-ID: 0x2ba01477 (STM32F1c_CORE_ID) | Product-Code | Chip-ID | STLink
Programmer | Boards | | ------------- | ------- | ---------------------- | ----------------------------------------------------------------------------------------------- | | CKS32F103C8Tx | 0x410 | v2 | "STM32"-Bluepill ( _**Fake-Marking !**_ )
STM32F103C8T6 clone from China Key Systems (CKS) | | CKS32F103C8Tx | 0x410 | v2 | CKS32-Bluepill (Clone)
STM32F103C8T6 clone from China Key Systems (CKS) | -**STM32F3 / ARM Cortex M4F / Core-ID: 0x2ba01477 (STM32F3_CORE_ID)** +## STM32F3 / ARM Cortex M4F / Core-ID: 0x2ba01477 (STM32F3_CORE_ID) | Product-Code | Product Line | | ----------------- | ------------------------------------------------------------- | @@ -85,13 +85,13 @@ Tested non-official ST boards [incl. STLINK programmers]: | 0x446 | _N/A_ | xD xE | | F302 | F303 | | | 0x446 | _N/A_ | - | | | | F398 | -**STM32F3 / ARM Cortex M4F / Core-ID: 0x2ba01477 (STM32F3c_CORE_ID)** +## STM32F3 / ARM Cortex M4F / Core-ID: 0x2ba01477 (STM32F3c_CORE_ID) | Product-Code | Chip-ID | STLINK
Programmer | Boards | | ------------ | ------- | ---------------------- | ---------------------------------- | | GD32F303VGT6 | 0x430 | [v2] | STM32F303 clone from GigaDevice GD | -**STM32F4 / ARM Cortex M4F / Core-ID: 0x2ba01477 (STM32F4_CORE_ID)** +## STM32F4 / ARM Cortex M4F / Core-ID: 0x2ba01477 (STM32F4_CORE_ID) | Chip-ID | Product-Code | | ------- | ------------------- | @@ -112,7 +112,7 @@ Tested non-official ST boards [incl. STLINK programmers]: | 0x463 | STM32F4**13**xx | | 0x463 | STM32F4**23**xx | -**STM32F7 / ARM Cortex M7F / Core-ID: 0x5ba02477 (STM32F7_CORE_ID)** +## STM32F7 / ARM Cortex M7F / Core-ID: 0x5ba02477 (STM32F7_CORE_ID) | Chip-ID | Product-Code | | ------- | --------------- | @@ -123,7 +123,7 @@ Tested non-official ST boards [incl. STLINK programmers]: | 0x451 | STM32F7**6**xxx | | 0x451 | STM32F7**7**xxx | -**STM32H7 / ARM Cortex M7F / Core-ID: 0x6ba02477 (STM32H7_CORE_ID)** +## STM32H7 / ARM Cortex M7F / Core-ID: 0x6ba02477 (STM32H7_CORE_ID) | Chip-ID | Product-Code | | ------- | ------------- | @@ -132,7 +132,7 @@ Tested non-official ST boards [incl. STLINK programmers]: | 0x480 | STM32H7**A**x | | 0x480 | STM32H7**B**x | -**STM32G0 / ARM Cortex M0+ / Core-ID: 0x0bc11477 (STM32G0_CORE_ID)** +## STM32G0 / ARM Cortex M0+ / Core-ID: 0x0bc11477 (STM32G0_CORE_ID) | Chip-ID | Product-Code | | ------- | --------------- | @@ -141,7 +141,7 @@ Tested non-official ST boards [incl. STLINK programmers]: | 0x460 | STM32G0**7**xxx | | 0x460 | STM32G0**8**xxx | -**STM32G4 / ARM Cortex M4F / Core-ID: 0x2ba01477 (STM32G4_CORE_ID)** +## STM32G4 / ARM Cortex M4F / Core-ID: 0x2ba01477 (STM32G4_CORE_ID) | Chip-ID | Product-Code | | ------- | --------------- | @@ -151,7 +151,7 @@ Tested non-official ST boards [incl. STLINK programmers]: | 0x469 | STM32G4**8**xxx | | 0x479 | STM32G4**91**xx | -**STM32L0 / ARM Cortex M0+ / Core-ID: 0x0bc11477 (STM32L0_CORE_ID)** +## STM32L0 / ARM Cortex M0+ / Core-ID: 0x0bc11477 (STM32L0_CORE_ID) | Chip-ID | Product-Code | | ------- | --------------- | @@ -164,7 +164,7 @@ Tested non-official ST boards [incl. STLINK programmers]: | 0x447 | STM32L0**7**xxx | | 0x447 | STM32L0**8**xxx | -**STM32L1 / ARM Cortex M3 / Core-ID: 0x2ba01477 (STM32L1_CORE_ID)** +## STM32L1 / ARM Cortex M3 / Core-ID: 0x2ba01477 (STM32L1_CORE_ID) | Chip-ID | Product-Code | | ------- | ---------------- | @@ -178,7 +178,7 @@ Tested non-official ST boards [incl. STLINK programmers]: | 0x436 | STM32L1xxx**D** | | 0x437 | STM32L1xxx**E** | -**STM32L4 / ARM Cortex M4F / Core-ID: 0x2ba01477 (STM32L4_CORE_ID)** +## STM32L4 / ARM Cortex M4F / Core-ID: 0x2ba01477 (STM32L4_CORE_ID) | Chip-ID | Product-Code | | ------- | --------------- | @@ -197,7 +197,7 @@ Tested non-official ST boards [incl. STLINK programmers]: | 0x471 | STM32L4**P5**xx | | 0x471 | STM32L4**Q5**xx | -**STM32W / ARM Cortex M3 / Core-ID: 0x2ba01477 (STM32W_CORE_ID)** +## STM32W / ARM Cortex M3 / Core-ID: 0x2ba01477 (STM32W_CORE_ID) | Chip-ID | Product-Code | | ------- | --------------- | From e4b17475d179b37e60b686027d338891641effc1 Mon Sep 17 00:00:00 2001 From: Grzegorz Szymaszek Date: Thu, 29 Jul 2021 21:48:53 +0200 Subject: [PATCH 295/503] Fix parsing hex numbers in chip config files MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit process_chipfile() used to improperly parse hex numbers in chip config files (*.chip), because it used atoi(), which read all such numbers as 0. This resulted, among other issues, in chip_id being set to 0 for all read chips. Such chip id could not match any actual MCU. Replace the atoi() calls with sscanf(…, "%i", …), where %i should match integers in base 10, 8 and 16, depending on the number prefix. --- src/stlink-lib/chipid.c | 31 ++++++++++++++++++++----------- 1 file changed, 20 insertions(+), 11 deletions(-) diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index 8f8f91a9c..2e99c580e 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -973,7 +973,7 @@ void process_chipfile(char *fname) char *p, *pp, buf[1025]; char word[64], value[64]; struct stlink_chipid_params *ts; - int nc, ival; + int nc; //fprintf (stderr, "processing chipfile %s.\n", fname); fp = fopen(fname, "r"); @@ -989,30 +989,39 @@ void process_chipfile(char *fname) if (*p == '#') continue; // ignore comments. sscanf(p, "%s %s", word, value); - ival = atoi (value); if (strcmp(word, "chip_id") == 0) { - ts->chip_id = ival; + if (sscanf(value, "%i", &ts->chip_id) < 1) + fprintf(stderr, "Failed to parse chip id\n"); } else if (strcmp (word, "description") == 0) { //ts->description = strdup (value); buf[strlen(p)-1] = 0; // chomp newline sscanf(p, "%*s %n", &nc); ts->description = strdup(p+nc); } else if (strcmp (word, "flash_type") == 0) { - ts->flash_type = ival; + // may set invalid flash types (not defined in enum stlink_flash_type) + if (sscanf(value, "%i", (int *) &ts->flash_type) < 1) + fprintf(stderr, "Failed to parse flash type\n"); } else if (strcmp (word, "flash_size_reg") == 0) { - ts->flash_size_reg = ival; + if (sscanf(value, "%i", &ts->flash_size_reg) < 1) + fprintf(stderr, "Failed to parse flash size reg\n"); } else if (strcmp (word, "flash_pagesize") == 0) { - ts->flash_pagesize = ival; + if (sscanf(value, "%i", &ts->flash_pagesize) < 1) + fprintf(stderr, "Failed to parse flash page size\n"); } else if (strcmp (word, "sram_size") == 0) { - ts->sram_size = ival; + if (sscanf(value, "%i", &ts->sram_size) < 1) + fprintf(stderr, "Failed to parse SRAM size\n"); } else if (strcmp (word, "bootrom_base") == 0) { - ts->bootrom_base = ival; + if (sscanf(value, "%i", &ts->bootrom_base) < 1) + fprintf(stderr, "Failed to parse BootROM base\n"); } else if (strcmp (word, "bootrom_size") == 0) { - ts->bootrom_size = ival; + if (sscanf(value, "%i", &ts->bootrom_size) < 1) + fprintf(stderr, "Failed to parse BootROM size\n"); } else if (strcmp (word, "option_base") == 0) { - ts->option_base = ival; + if (sscanf(value, "%i", &ts->option_base) < 1) + fprintf(stderr, "Failed to parse option base\n"); } else if (strcmp (word, "option_size") == 0) { - ts->option_size = ival; + if (sscanf(value, "%i", &ts->option_size) < 1) + fprintf(stderr, "Failed to parse option size\n"); } else if (strcmp (word, "flags") == 0) { pp = strtok (p, " \t\n"); while ((pp = strtok (NULL, " \t\n")) ) { From 929af2b047b7dfc54750842100a285646fb4a417 Mon Sep 17 00:00:00 2001 From: Grzegorz Szymaszek Date: Fri, 30 Jul 2021 10:14:17 +0200 Subject: [PATCH 296/503] Add a constant for the valid flash types range Add a STLINK_FLASH_TYPE_MAX constant that can be used to check if a flash type (an integer) is in the range of valid enum stlink_flash_type values. --- inc/stlink.h | 1 + 1 file changed, 1 insertion(+) diff --git a/inc/stlink.h b/inc/stlink.h index f70060b05..81dc7902e 100644 --- a/inc/stlink.h +++ b/inc/stlink.h @@ -114,6 +114,7 @@ enum stlink_flash_type { STLINK_FLASH_TYPE_G4, STLINK_FLASH_TYPE_WB, STLINK_FLASH_TYPE_H7, + STLINK_FLASH_TYPE_MAX, }; struct stlink_reg { From ebac01c8d4e436f45afcc35c4452ffdb3750a13f Mon Sep 17 00:00:00 2001 From: Grzegorz Szymaszek Date: Fri, 30 Jul 2021 10:18:02 +0200 Subject: [PATCH 297/503] Warn if chip config file contains unrecognized flash type --- src/stlink-lib/chipid.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index 2e99c580e..5080ef756 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -998,9 +998,10 @@ void process_chipfile(char *fname) sscanf(p, "%*s %n", &nc); ts->description = strdup(p+nc); } else if (strcmp (word, "flash_type") == 0) { - // may set invalid flash types (not defined in enum stlink_flash_type) if (sscanf(value, "%i", (int *) &ts->flash_type) < 1) fprintf(stderr, "Failed to parse flash type\n"); + else if (ts->flash_type <= STLINK_FLASH_TYPE_UNKNOWN || ts->flash_type >= STLINK_FLASH_TYPE_MAX) + fprintf(stderr, "Unrecognized flash type\n"); } else if (strcmp (word, "flash_size_reg") == 0) { if (sscanf(value, "%i", &ts->flash_size_reg) < 1) fprintf(stderr, "Failed to parse flash size reg\n"); From 1e674cff1a3557969b9dd55db9d13d9d40c2de93 Mon Sep 17 00:00:00 2001 From: Sam Bazley Date: Sun, 1 Aug 2021 21:36:40 +0100 Subject: [PATCH 298/503] Correct flash_pagesize to use hex format --- config/chips/F04x.chip | 2 +- config/chips/F07x.chip | 2 +- config/chips/F09x.chip | 2 +- config/chips/F0xx.chip | 2 +- config/chips/F0xx_small.chip | 2 +- config/chips/F1_XL-density.chip | 2 +- config/chips/F1_connectivity_line.chip | 2 +- config/chips/F1_high-density.chip | 2 +- config/chips/F1_low-density.chip | 2 +- config/chips/F1_medium-density.chip | 2 +- config/chips/F1_value_line.chip | 2 +- config/chips/F1_value_line_high-density.chip | 2 +- config/chips/F2.chip | 2 +- config/chips/F303_high_density.chip | 2 +- config/chips/F334_medium_density.chip | 2 +- config/chips/F37x.chip | 2 +- config/chips/F3xx_small.chip | 2 +- config/chips/F410.chip | 2 +- config/chips/F411xx.chip | 2 +- config/chips/F412.chip | 2 +- config/chips/F413.chip | 2 +- config/chips/F42x_F43x.chip | 2 +- config/chips/F446.chip | 2 +- config/chips/F46x_F47x.chip | 2 +- config/chips/F4xx.chip | 2 +- config/chips/F4xx_dynamic_efficiency.chip | 2 +- config/chips/F4xx_low_power.chip | 2 +- config/chips/F72x_F73x.chip | 2 +- config/chips/F76xxx.chip | 2 +- config/chips/F7xx.chip | 2 +- config/chips/G030_G031_G041.chip | 2 +- config/chips/G070_G071_G081.chip | 2 +- config/chips/G4_cat2.chip | 2 +- config/chips/G4_cat3.chip | 2 +- config/chips/H72x_H73x.chip | 2 +- config/chips/H74x_H75x.chip | 2 +- config/chips/H7Ax_H7Bx.chip | 2 +- config/chips/L011.chip | 2 +- config/chips/L0xx_cat2.chip | 2 +- config/chips/L0xx_cat5.chip | 2 +- config/chips/L152RE.chip | 2 +- config/chips/L1xx_cat2.chip | 2 +- config/chips/L1xx_high-density.chip | 2 +- config/chips/L1xx_medium-density.chip | 2 +- config/chips/L1xx_medium-plus-density.chip | 2 +- config/chips/L41x.chip | 2 +- config/chips/L43x_L44x.chip | 2 +- config/chips/L45x_L46x.chip | 2 +- config/chips/L496x_L4A6x.chip | 2 +- config/chips/L4Rx.chip | 2 +- config/chips/L4xx.chip | 2 +- config/chips/WB55.chip | 2 +- config/chips/unknown_device.chip | 2 +- 53 files changed, 53 insertions(+), 53 deletions(-) diff --git a/config/chips/F04x.chip b/config/chips/F04x.chip index b42d420fa..033c034e2 100644 --- a/config/chips/F04x.chip +++ b/config/chips/F04x.chip @@ -3,7 +3,7 @@ chip_id 0x445 description F04x flash_type 1 -flash_pagesize 400 +flash_pagesize 0x400 sram_size 0x1800 bootrom_base 0x1fffec00 bootrom_size 0xc00 diff --git a/config/chips/F07x.chip b/config/chips/F07x.chip index d8c71f0ea..dd697af40 100644 --- a/config/chips/F07x.chip +++ b/config/chips/F07x.chip @@ -3,7 +3,7 @@ chip_id 0x448 description F07x flash_type 1 -flash_pagesize 800 +flash_pagesize 0x800 sram_size 0x4000 bootrom_base 0x1fffc800 bootrom_size 0x3000 diff --git a/config/chips/F09x.chip b/config/chips/F09x.chip index ca97d53e4..adb000030 100644 --- a/config/chips/F09x.chip +++ b/config/chips/F09x.chip @@ -3,7 +3,7 @@ chip_id 0x442 description F09x flash_type 1 -flash_pagesize 800 +flash_pagesize 0x800 sram_size 0x8000 bootrom_base 0x1fffd800 bootrom_size 0x2000 diff --git a/config/chips/F0xx.chip b/config/chips/F0xx.chip index a1700eef3..309bbee34 100644 --- a/config/chips/F0xx.chip +++ b/config/chips/F0xx.chip @@ -3,7 +3,7 @@ chip_id 0x440 description F0xx flash_type 1 -flash_pagesize 400 +flash_pagesize 0x400 sram_size 0x2000 bootrom_base 0x1fffec00 bootrom_size 0xc00 diff --git a/config/chips/F0xx_small.chip b/config/chips/F0xx_small.chip index 3ab256feb..0a8ec265e 100644 --- a/config/chips/F0xx_small.chip +++ b/config/chips/F0xx_small.chip @@ -3,7 +3,7 @@ chip_id 0x444 description F0xx small flash_type 1 -flash_pagesize 400 +flash_pagesize 0x400 sram_size 0x1000 bootrom_base 0x1fffec00 bootrom_size 0xc00 diff --git a/config/chips/F1_XL-density.chip b/config/chips/F1_XL-density.chip index 97bb580e3..3b3c95ab0 100644 --- a/config/chips/F1_XL-density.chip +++ b/config/chips/F1_XL-density.chip @@ -3,7 +3,7 @@ chip_id 0x430 description F1 XL-density flash_type 2 -flash_pagesize 800 +flash_pagesize 0x800 sram_size 0x18000 bootrom_base 0x1fffe000 bootrom_size 0x1800 diff --git a/config/chips/F1_connectivity_line.chip b/config/chips/F1_connectivity_line.chip index a030fd58d..b6fd9c93a 100644 --- a/config/chips/F1_connectivity_line.chip +++ b/config/chips/F1_connectivity_line.chip @@ -3,7 +3,7 @@ chip_id 0x418 description F1 connectivity line flash_type 1 -flash_pagesize 800 +flash_pagesize 0x800 sram_size 0x10000 bootrom_base 0x1fffb000 bootrom_size 0x4800 diff --git a/config/chips/F1_high-density.chip b/config/chips/F1_high-density.chip index 00e4942b0..f88413fc8 100644 --- a/config/chips/F1_high-density.chip +++ b/config/chips/F1_high-density.chip @@ -3,7 +3,7 @@ chip_id 0x414 description F1 high-density flash_type 1 -flash_pagesize 800 +flash_pagesize 0x800 sram_size 0x10000 bootrom_base 0x1ffff000 bootrom_size 0x800 diff --git a/config/chips/F1_low-density.chip b/config/chips/F1_low-density.chip index 1562c7589..3995cad96 100644 --- a/config/chips/F1_low-density.chip +++ b/config/chips/F1_low-density.chip @@ -3,7 +3,7 @@ chip_id 0x412 description F1 low-density flash_type 1 -flash_pagesize 400 +flash_pagesize 0x400 sram_size 0x2800 bootrom_base 0x1ffff000 bootrom_size 0x800 diff --git a/config/chips/F1_medium-density.chip b/config/chips/F1_medium-density.chip index 1f3d89234..25cbec2dc 100644 --- a/config/chips/F1_medium-density.chip +++ b/config/chips/F1_medium-density.chip @@ -3,7 +3,7 @@ chip_id 0x410 description F1 medium-density flash_type 1 -flash_pagesize 400 +flash_pagesize 0x400 sram_size 0x5000 bootrom_base 0x1ffff000 bootrom_size 0x800 diff --git a/config/chips/F1_value_line.chip b/config/chips/F1_value_line.chip index d9f04f00a..5515d9acd 100644 --- a/config/chips/F1_value_line.chip +++ b/config/chips/F1_value_line.chip @@ -3,7 +3,7 @@ chip_id 0x420 description F1 value line flash_type 1 -flash_pagesize 400 +flash_pagesize 0x400 sram_size 0x2000 bootrom_base 0x1ffff000 bootrom_size 0x800 diff --git a/config/chips/F1_value_line_high-density.chip b/config/chips/F1_value_line_high-density.chip index 2ecf6b4f5..6a49c2699 100644 --- a/config/chips/F1_value_line_high-density.chip +++ b/config/chips/F1_value_line_high-density.chip @@ -3,7 +3,7 @@ chip_id 0x428 description F1 value line high-density flash_type 1 -flash_pagesize 800 +flash_pagesize 0x800 sram_size 0x8000 bootrom_base 0x1ffff000 bootrom_size 0x800 diff --git a/config/chips/F2.chip b/config/chips/F2.chip index 098ddc863..31a4d34a8 100644 --- a/config/chips/F2.chip +++ b/config/chips/F2.chip @@ -3,7 +3,7 @@ chip_id 0x411 description F2 flash_type 3 -flash_pagesize 20000 +flash_pagesize 0x20000 sram_size 0x20000 bootrom_base 0x1fff0000 bootrom_size 0x7800 diff --git a/config/chips/F303_high_density.chip b/config/chips/F303_high_density.chip index 19cc2ad2a..afbdf63b5 100644 --- a/config/chips/F303_high_density.chip +++ b/config/chips/F303_high_density.chip @@ -3,7 +3,7 @@ chip_id 0x446 description F303 high density flash_type 1 -flash_pagesize 800 +flash_pagesize 0x800 sram_size 0x10000 bootrom_base 0x1fffd800 bootrom_size 0x2000 diff --git a/config/chips/F334_medium_density.chip b/config/chips/F334_medium_density.chip index ba4cf9688..365931a01 100644 --- a/config/chips/F334_medium_density.chip +++ b/config/chips/F334_medium_density.chip @@ -3,7 +3,7 @@ chip_id 0x438 description F334 medium density flash_type 1 -flash_pagesize 800 +flash_pagesize 0x800 sram_size 0x3000 bootrom_base 0x1fffd800 bootrom_size 0x2000 diff --git a/config/chips/F37x.chip b/config/chips/F37x.chip index d0081e68a..5d5723b14 100644 --- a/config/chips/F37x.chip +++ b/config/chips/F37x.chip @@ -3,7 +3,7 @@ chip_id 0x432 description F37x flash_type 1 -flash_pagesize 800 +flash_pagesize 0x800 sram_size 0xa000 bootrom_base 0x1ffff000 bootrom_size 0x800 diff --git a/config/chips/F3xx_small.chip b/config/chips/F3xx_small.chip index 34d1940ac..31fd136a8 100644 --- a/config/chips/F3xx_small.chip +++ b/config/chips/F3xx_small.chip @@ -3,7 +3,7 @@ chip_id 0x439 description F3xx small flash_type 1 -flash_pagesize 800 +flash_pagesize 0x800 sram_size 0xa000 bootrom_base 0x1fffd800 bootrom_size 0x2000 diff --git a/config/chips/F410.chip b/config/chips/F410.chip index 3cd382845..ae199d9c4 100644 --- a/config/chips/F410.chip +++ b/config/chips/F410.chip @@ -3,7 +3,7 @@ chip_id 0x458 description F410 flash_type 3 -flash_pagesize 4000 +flash_pagesize 0x4000 sram_size 0x8000 bootrom_base 0x1fff0000 bootrom_size 0x7800 diff --git a/config/chips/F411xx.chip b/config/chips/F411xx.chip index 301e6cb91..e41288de7 100644 --- a/config/chips/F411xx.chip +++ b/config/chips/F411xx.chip @@ -3,7 +3,7 @@ chip_id 0x431 description F411xx flash_type 3 -flash_pagesize 4000 +flash_pagesize 0x4000 sram_size 0x20000 bootrom_base 0x1fff0000 bootrom_size 0x7800 diff --git a/config/chips/F412.chip b/config/chips/F412.chip index 186a43427..3212a340c 100644 --- a/config/chips/F412.chip +++ b/config/chips/F412.chip @@ -3,7 +3,7 @@ chip_id 0x441 description F412 flash_type 3 -flash_pagesize 4000 +flash_pagesize 0x4000 sram_size 0x40000 bootrom_base 0x1fff0000 bootrom_size 0x7800 diff --git a/config/chips/F413.chip b/config/chips/F413.chip index 367344aaa..94813647f 100644 --- a/config/chips/F413.chip +++ b/config/chips/F413.chip @@ -3,7 +3,7 @@ chip_id 0x463 description F413 flash_type 3 -flash_pagesize 4000 +flash_pagesize 0x4000 sram_size 0x50000 bootrom_base 0x1fff0000 bootrom_size 0x7800 diff --git a/config/chips/F42x_F43x.chip b/config/chips/F42x_F43x.chip index 4557a731c..3184d0d4f 100644 --- a/config/chips/F42x_F43x.chip +++ b/config/chips/F42x_F43x.chip @@ -3,7 +3,7 @@ chip_id 0x419 description F42x/F43x flash_type 3 -flash_pagesize 4000 +flash_pagesize 0x4000 sram_size 0x40000 bootrom_base 0x1fff0000 bootrom_size 0x7800 diff --git a/config/chips/F446.chip b/config/chips/F446.chip index 9f7ae0bc5..86cee6a56 100644 --- a/config/chips/F446.chip +++ b/config/chips/F446.chip @@ -3,7 +3,7 @@ chip_id 0x421 description F446 flash_type 3 -flash_pagesize 20000 +flash_pagesize 0x20000 sram_size 0x20000 bootrom_base 0x1fff0000 bootrom_size 0x7800 diff --git a/config/chips/F46x_F47x.chip b/config/chips/F46x_F47x.chip index 8ae43eb2e..ee5f6a5a7 100644 --- a/config/chips/F46x_F47x.chip +++ b/config/chips/F46x_F47x.chip @@ -3,7 +3,7 @@ chip_id 0x434 description F46x/F47x flash_type 3 -flash_pagesize 4000 +flash_pagesize 0x4000 sram_size 0x40000 bootrom_base 0x1fff0000 bootrom_size 0x7800 diff --git a/config/chips/F4xx.chip b/config/chips/F4xx.chip index 17ec62d68..1c6d087a5 100644 --- a/config/chips/F4xx.chip +++ b/config/chips/F4xx.chip @@ -3,7 +3,7 @@ chip_id 0x413 description F4xx flash_type 3 -flash_pagesize 4000 +flash_pagesize 0x4000 sram_size 0x30000 bootrom_base 0x1fff0000 bootrom_size 0x7800 diff --git a/config/chips/F4xx_dynamic_efficiency.chip b/config/chips/F4xx_dynamic_efficiency.chip index 6d06bcb8e..02a886c26 100644 --- a/config/chips/F4xx_dynamic_efficiency.chip +++ b/config/chips/F4xx_dynamic_efficiency.chip @@ -3,7 +3,7 @@ chip_id 0x433 description F4xx dynamic efficiency flash_type 3 -flash_pagesize 4000 +flash_pagesize 0x4000 sram_size 0x18000 bootrom_base 0x1fff0000 bootrom_size 0x7800 diff --git a/config/chips/F4xx_low_power.chip b/config/chips/F4xx_low_power.chip index ad8c3ce90..7c1cc1243 100644 --- a/config/chips/F4xx_low_power.chip +++ b/config/chips/F4xx_low_power.chip @@ -3,7 +3,7 @@ chip_id 0x423 description F4xx low power flash_type 3 -flash_pagesize 4000 +flash_pagesize 0x4000 sram_size 0x10000 bootrom_base 0x1fff0000 bootrom_size 0x7800 diff --git a/config/chips/F72x_F73x.chip b/config/chips/F72x_F73x.chip index b6f706994..2836040ac 100644 --- a/config/chips/F72x_F73x.chip +++ b/config/chips/F72x_F73x.chip @@ -3,7 +3,7 @@ chip_id 0x452 description F72x/F73x flash_type 3 -flash_pagesize 800 +flash_pagesize 0x800 sram_size 0x40000 bootrom_base 0x100000 bootrom_size 0xedc0 diff --git a/config/chips/F76xxx.chip b/config/chips/F76xxx.chip index 49ac1ec21..ef17fc557 100644 --- a/config/chips/F76xxx.chip +++ b/config/chips/F76xxx.chip @@ -3,7 +3,7 @@ chip_id 0x451 description F76xxx flash_type 4 -flash_pagesize 800 +flash_pagesize 0x800 sram_size 0x80000 bootrom_base 0x200000 bootrom_size 0xedc0 diff --git a/config/chips/F7xx.chip b/config/chips/F7xx.chip index 87420f2ab..b6e3774f7 100644 --- a/config/chips/F7xx.chip +++ b/config/chips/F7xx.chip @@ -3,7 +3,7 @@ chip_id 0x449 description F7xx flash_type 3 -flash_pagesize 800 +flash_pagesize 0x800 sram_size 0x50000 bootrom_base 0x100000 bootrom_size 0xedc0 diff --git a/config/chips/G030_G031_G041.chip b/config/chips/G030_G031_G041.chip index 7d47e7aed..16a9a79ff 100644 --- a/config/chips/G030_G031_G041.chip +++ b/config/chips/G030_G031_G041.chip @@ -3,7 +3,7 @@ chip_id 0x466 description G030/G031/G041 flash_type 7 -flash_pagesize 800 +flash_pagesize 0x800 sram_size 0x2000 bootrom_base 0x1fff0000 bootrom_size 0x2000 diff --git a/config/chips/G070_G071_G081.chip b/config/chips/G070_G071_G081.chip index 9905fc682..7fb81eb1f 100644 --- a/config/chips/G070_G071_G081.chip +++ b/config/chips/G070_G071_G081.chip @@ -3,7 +3,7 @@ chip_id 0x460 description G070/G071/G081 flash_type 7 -flash_pagesize 800 +flash_pagesize 0x800 sram_size 0x9000 bootrom_base 0x1fff0000 bootrom_size 0x7000 diff --git a/config/chips/G4_cat2.chip b/config/chips/G4_cat2.chip index 47745e715..ea144114d 100644 --- a/config/chips/G4_cat2.chip +++ b/config/chips/G4_cat2.chip @@ -3,7 +3,7 @@ chip_id 0x468 description G4 cat2 flash_type 8 -flash_pagesize 800 +flash_pagesize 0x800 sram_size 0x8000 bootrom_base 0x1fff0000 bootrom_size 0x7000 diff --git a/config/chips/G4_cat3.chip b/config/chips/G4_cat3.chip index f883b9176..7e34e001c 100644 --- a/config/chips/G4_cat3.chip +++ b/config/chips/G4_cat3.chip @@ -3,7 +3,7 @@ chip_id 0x469 description G4 cat3 flash_type 8 -flash_pagesize 800 +flash_pagesize 0x800 sram_size 0x18000 bootrom_base 0x1fff0000 bootrom_size 0x7000 diff --git a/config/chips/H72x_H73x.chip b/config/chips/H72x_H73x.chip index 81c1b71c9..df20037d3 100644 --- a/config/chips/H72x_H73x.chip +++ b/config/chips/H72x_H73x.chip @@ -3,7 +3,7 @@ chip_id 0x483 description H72x/H73x flash_type 10 -flash_pagesize 20000 +flash_pagesize 0x20000 sram_size 0x20000 bootrom_base 0x1ff00000 bootrom_size 0x20000 diff --git a/config/chips/H74x_H75x.chip b/config/chips/H74x_H75x.chip index 7753cfe03..7a4bc86e3 100644 --- a/config/chips/H74x_H75x.chip +++ b/config/chips/H74x_H75x.chip @@ -3,7 +3,7 @@ chip_id 0x450 description H74x/H75x flash_type 10 -flash_pagesize 20000 +flash_pagesize 0x20000 sram_size 0x20000 bootrom_base 0x1ff00000 bootrom_size 0x20000 diff --git a/config/chips/H7Ax_H7Bx.chip b/config/chips/H7Ax_H7Bx.chip index df6c13726..b9202bd1a 100644 --- a/config/chips/H7Ax_H7Bx.chip +++ b/config/chips/H7Ax_H7Bx.chip @@ -3,7 +3,7 @@ chip_id 0x480 description H7Ax/H7Bx flash_type 10 -flash_pagesize 2000 +flash_pagesize 0x2000 sram_size 0x20000 bootrom_base 0x1ff00000 bootrom_size 0x20000 diff --git a/config/chips/L011.chip b/config/chips/L011.chip index 2f1fa7b56..719185558 100644 --- a/config/chips/L011.chip +++ b/config/chips/L011.chip @@ -3,7 +3,7 @@ chip_id 0x457 description L011 flash_type 5 -flash_pagesize 80 +flash_pagesize 0x80 sram_size 0x2000 bootrom_base 0x1ff00000 bootrom_size 0x2000 diff --git a/config/chips/L0xx_cat2.chip b/config/chips/L0xx_cat2.chip index 43a301b27..cdcff81cc 100644 --- a/config/chips/L0xx_cat2.chip +++ b/config/chips/L0xx_cat2.chip @@ -3,7 +3,7 @@ chip_id 0x425 description L0xx cat2 flash_type 5 -flash_pagesize 80 +flash_pagesize 0x80 sram_size 0x2000 bootrom_base 0x1ff0000 bootrom_size 0x1000 diff --git a/config/chips/L0xx_cat5.chip b/config/chips/L0xx_cat5.chip index 8ab0a50f8..2c755a0d8 100644 --- a/config/chips/L0xx_cat5.chip +++ b/config/chips/L0xx_cat5.chip @@ -3,7 +3,7 @@ chip_id 0x447 description L0xx cat5 flash_type 5 -flash_pagesize 80 +flash_pagesize 0x80 sram_size 0x5000 bootrom_base 0x1ff0000 bootrom_size 0x2000 diff --git a/config/chips/L152RE.chip b/config/chips/L152RE.chip index ebe012c5a..4d9658ee9 100644 --- a/config/chips/L152RE.chip +++ b/config/chips/L152RE.chip @@ -3,7 +3,7 @@ chip_id 0x437 description L152RE flash_type 5 -flash_pagesize 100 +flash_pagesize 0x100 sram_size 0x14000 bootrom_base 0x1ff00000 bootrom_size 0x1000 diff --git a/config/chips/L1xx_cat2.chip b/config/chips/L1xx_cat2.chip index 02012078a..7f949923e 100644 --- a/config/chips/L1xx_cat2.chip +++ b/config/chips/L1xx_cat2.chip @@ -3,7 +3,7 @@ chip_id 0x429 description L1xx cat2 flash_type 5 -flash_pagesize 100 +flash_pagesize 0x100 sram_size 0x8000 bootrom_base 0x1ff00000 bootrom_size 0x1000 diff --git a/config/chips/L1xx_high-density.chip b/config/chips/L1xx_high-density.chip index 130b4e456..409c04062 100644 --- a/config/chips/L1xx_high-density.chip +++ b/config/chips/L1xx_high-density.chip @@ -3,7 +3,7 @@ chip_id 0x436 description L1xx high-density flash_type 5 -flash_pagesize 100 +flash_pagesize 0x100 sram_size 0xc000 bootrom_base 0x1ff00000 bootrom_size 0x1000 diff --git a/config/chips/L1xx_medium-density.chip b/config/chips/L1xx_medium-density.chip index 409b4dacc..f77c19cac 100644 --- a/config/chips/L1xx_medium-density.chip +++ b/config/chips/L1xx_medium-density.chip @@ -3,7 +3,7 @@ chip_id 0x416 description L1xx medium-density flash_type 5 -flash_pagesize 100 +flash_pagesize 0x100 sram_size 0x4000 bootrom_base 0x1ff00000 bootrom_size 0x1000 diff --git a/config/chips/L1xx_medium-plus-density.chip b/config/chips/L1xx_medium-plus-density.chip index 374f2e914..da557e3c8 100644 --- a/config/chips/L1xx_medium-plus-density.chip +++ b/config/chips/L1xx_medium-plus-density.chip @@ -3,7 +3,7 @@ chip_id 0x427 description L1xx medium-plus-density flash_type 5 -flash_pagesize 100 +flash_pagesize 0x100 sram_size 0x8000 bootrom_base 0x1ff00000 bootrom_size 0x1000 diff --git a/config/chips/L41x.chip b/config/chips/L41x.chip index cf51b4b02..5b491ccd4 100644 --- a/config/chips/L41x.chip +++ b/config/chips/L41x.chip @@ -3,7 +3,7 @@ chip_id 0x464 description L41x flash_type 6 -flash_pagesize 800 +flash_pagesize 0x800 sram_size 0xa000 bootrom_base 0x1fff0000 bootrom_size 0x7000 diff --git a/config/chips/L43x_L44x.chip b/config/chips/L43x_L44x.chip index 1953a6a99..383c42f3f 100644 --- a/config/chips/L43x_L44x.chip +++ b/config/chips/L43x_L44x.chip @@ -3,7 +3,7 @@ chip_id 0x435 description L43x/L44x flash_type 6 -flash_pagesize 800 +flash_pagesize 0x800 sram_size 0xc000 bootrom_base 0x1fff0000 bootrom_size 0x7000 diff --git a/config/chips/L45x_L46x.chip b/config/chips/L45x_L46x.chip index 79a90fcac..8b5f91ec3 100644 --- a/config/chips/L45x_L46x.chip +++ b/config/chips/L45x_L46x.chip @@ -3,7 +3,7 @@ chip_id 0x462 description L45x/L46x flash_type 6 -flash_pagesize 800 +flash_pagesize 0x800 sram_size 0x20000 bootrom_base 0x1fff0000 bootrom_size 0x7000 diff --git a/config/chips/L496x_L4A6x.chip b/config/chips/L496x_L4A6x.chip index f94c0c582..57f539db3 100644 --- a/config/chips/L496x_L4A6x.chip +++ b/config/chips/L496x_L4A6x.chip @@ -3,7 +3,7 @@ chip_id 0x461 description L496x/L4A6x flash_type 6 -flash_pagesize 800 +flash_pagesize 0x800 sram_size 0x40000 bootrom_base 0x1fff0000 bootrom_size 0x7000 diff --git a/config/chips/L4Rx.chip b/config/chips/L4Rx.chip index 355f22470..11780ce27 100644 --- a/config/chips/L4Rx.chip +++ b/config/chips/L4Rx.chip @@ -3,7 +3,7 @@ chip_id 0x470 description L4Rx flash_type 6 -flash_pagesize 1000 +flash_pagesize 0x1000 sram_size 0xa0000 bootrom_base 0x1fff0000 bootrom_size 0x7000 diff --git a/config/chips/L4xx.chip b/config/chips/L4xx.chip index 3360a446e..c665c245f 100644 --- a/config/chips/L4xx.chip +++ b/config/chips/L4xx.chip @@ -3,7 +3,7 @@ chip_id 0x415 description L4xx flash_type 6 -flash_pagesize 800 +flash_pagesize 0x800 sram_size 0x18000 bootrom_base 0x1fff0000 bootrom_size 0x7000 diff --git a/config/chips/WB55.chip b/config/chips/WB55.chip index 9cf1d4380..585b576bc 100644 --- a/config/chips/WB55.chip +++ b/config/chips/WB55.chip @@ -3,7 +3,7 @@ chip_id 0x495 description WB55 flash_type 9 -flash_pagesize 1000 +flash_pagesize 0x1000 sram_size 0x40000 bootrom_base 0x1fff0000 bootrom_size 0x7000 diff --git a/config/chips/unknown_device.chip b/config/chips/unknown_device.chip index 2235d0072..c71206951 100644 --- a/config/chips/unknown_device.chip +++ b/config/chips/unknown_device.chip @@ -3,7 +3,7 @@ chip_id 0x0 description unknown device flash_type 0 -flash_pagesize 0 +flash_pagesize 0x0 sram_size 0x0 bootrom_base 0x0 bootrom_size 0x0 From fe48a98cb1802732edb117fe60cd9b2fa0689145 Mon Sep 17 00:00:00 2001 From: Sam Bazley Date: Sun, 1 Aug 2021 21:25:06 +0100 Subject: [PATCH 299/503] Add STM32WLEx support --- config/chips/WLE.chip | 13 +++++++++++++ src/stlink-lib/chipid.c | 12 ++++++++++++ src/stlink-lib/chipid.h | 3 ++- 3 files changed, 27 insertions(+), 1 deletion(-) create mode 100644 config/chips/WLE.chip diff --git a/config/chips/WLE.chip b/config/chips/WLE.chip new file mode 100644 index 000000000..dbdf66d59 --- /dev/null +++ b/config/chips/WLE.chip @@ -0,0 +1,13 @@ +# Chip-ID file for WLE +# +chip_id 0x497 +description WLE +flash_type 9 +flash_pagesize 0x800 +sram_size 0x10000 +bootrom_base 0x1fff0000 +bootrom_size 0x7000 +option_base 0x0 +option_size 0x0 +flags swo + diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index 212328f86..28e4e91e9 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -847,6 +847,18 @@ static struct stlink_chipid_params devices[] = { .bootrom_size = 0x7000, .flags = CHIP_F_HAS_SWO_TRACING, }, + { + // STM32WLEx + .chip_id = STLINK_CHIPID_STM32_WLE, + .description = "WLEx", + .flash_type = STLINK_FLASH_TYPE_WB, + .flash_size_reg = 0x1FFF75E0, + .flash_pagesize = 0x800, // 2k + .sram_size = 0x10000, + .bootrom_base = 0x1fff0000, // see the memory map + .bootrom_size = 0x7000, + .flags = CHIP_F_HAS_SWO_TRACING, + }, { // STM32H742/743/753 (from RM0433) .chip_id = STLINK_CHIPID_STM32_H74xxx, diff --git a/src/stlink-lib/chipid.h b/src/stlink-lib/chipid.h index 75288093a..20cfcf52d 100644 --- a/src/stlink-lib/chipid.h +++ b/src/stlink-lib/chipid.h @@ -70,7 +70,8 @@ enum stlink_stm32_chipids { STLINK_CHIPID_STM32_G4_CAT4 = 0x479, STLINK_CHIPID_STM32_H7Ax = 0x480, /* RM0455, p.2863 */ STLINK_CHIPID_STM32_H72x = 0x483, /* RM0468, p.3199 */ - STLINK_CHIPID_STM32_WB55 = 0x495 + STLINK_CHIPID_STM32_WB55 = 0x495, + STLINK_CHIPID_STM32_WLE = 0x497 }; #define CHIP_F_HAS_DUAL_BANK (1 << 0) From 41d7ca710eace2b52b5e224a9f238be151477004 Mon Sep 17 00:00:00 2001 From: Oleksiy Slyshyk Date: Fri, 13 Aug 2021 20:02:26 +0300 Subject: [PATCH 300/503] fix compilation for MSVC --- CMakeLists.txt | 5 +++++ src/common.c | 2 +- src/stlink-lib/chipid.c | 45 ++++++++++++++++++++++++++++++++++++----- 3 files changed, 46 insertions(+), 6 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index 09e0a1bac..5c8aaa60c 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -75,6 +75,11 @@ if (STLINK_HAVE_UNISTD_H) add_definitions(-DSTLINK_HAVE_UNISTD_H) endif () +CHECK_INCLUDE_FILE(dirent.h STLINK_HAVE_DIRENT_H) +if (STLINK_HAVE_DIRENT_H) + add_definitions(-DSTLINK_HAVE_DIRENT_H) +endif () + if (MSVC) # Use string.h rather than strings.h and disable annoying warnings add_definitions(-DHAVE_STRING_H -D_CRT_SECURE_NO_WARNINGS -D_CRT_NONSTDC_NO_WARNINGS /wd4710) diff --git a/src/common.c b/src/common.c index 1457d640c..af96b70b8 100644 --- a/src/common.c +++ b/src/common.c @@ -1541,7 +1541,7 @@ int stlink_chip_id(stlink_t *sl, uint32_t *chip_id) { if (ret || !(*chip_id)) { *chip_id = 0; - ret = ret?:-1; + ret = ret?ret:-1; ELOG("Could not find chip id!\n"); } else { *chip_id = (*chip_id) & 0xfff; diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index 28e4e91e9..0ed774218 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -1,7 +1,6 @@ #include #include "chipid.h" -#include #include #include #include @@ -962,7 +961,7 @@ struct stlink_chipid_params *stlink_chipid_get_params(uint32_t chipid) { // fprintf (stderr, "getparams: %x\n", chipid); for (params = devicelist ; params != NULL ; params = params -> next) if (params->chip_id == chipid) break; - + p2 = stlink_chipid_get_params_old(chipid); #if 1 @@ -1061,7 +1060,7 @@ void dump_chips (void) struct stlink_chipid_params *ts; char *p, buf[100]; FILE *fp; - + for (size_t n = 0; n < STLINK_ARRAY_SIZE(devices); n++) { ts = &devices[n]; @@ -1086,7 +1085,9 @@ void dump_chips (void) } } -void init_chipids(char *dir_to_scan) +#if defined(STLINK_HAVE_DIRENT_H) +#include +void init_chipids(char *dir_to_scan) { DIR *d; size_t nl; // namelen @@ -1121,11 +1122,45 @@ void init_chipids(char *dir_to_scan) dump_a_chip (stderr, op); fprintf (stderr, "---------- new ------------\n"); dump_a_chip (stderr, p); - + } } #endif } +#endif //STLINK_HAVE_DIRENT_H + +#if defined(_WIN32) && !defined(STLINK_HAVE_DIRENT_H) +#include +#include +void init_chipids(char *dir_to_scan) +{ + HANDLE hFind = INVALID_HANDLE_VALUE; + WIN32_FIND_DATAA ffd; + char file_pattern[MAX_PATH] = {0}; + char filepath[MAX_PATH] = {0}; + StringCchCopyA(file_pattern, STLINK_ARRAY_SIZE(file_pattern), dir_to_scan); + if (FAILED(StringCchCatA(file_pattern, STLINK_ARRAY_SIZE(file_pattern), "\\*.chip"))) { + ELOG("Path to chips's dir too long.\n"); + return; + }; + hFind = FindFirstFileA(file_pattern, &ffd); + if (INVALID_HANDLE_VALUE == hFind){ + ELOG("Can't find any chip description file in %s.\n", file_pattern); + return; + } + + do { + memset(filepath, 0, STLINK_ARRAY_SIZE(filepath)); + StringCchCopyA(filepath, STLINK_ARRAY_SIZE(filepath), dir_to_scan); + StringCchCatA(filepath, STLINK_ARRAY_SIZE(file_pattern), "\\"); + StringCchCatA(filepath, STLINK_ARRAY_SIZE(file_pattern), ffd.cFileName); + process_chipfile(filepath); + } while(FindNextFileA(hFind, &ffd) != 0); + + FindClose(hFind); +} +#endif //defined(_WIN32) && !defined(STLINK_HAVE_DIRENT_H) + From af384e96930f09e5032f79afca03155d86e9759a Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Fri, 13 Aug 2021 21:23:00 +0200 Subject: [PATCH 301/503] Update src/stlink-lib/chipid.c Co-authored-by: Grzegorz Szymaszek --- src/stlink-lib/chipid.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index 0ed774218..bd5a7b9e2 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -1155,7 +1155,7 @@ void init_chipids(char *dir_to_scan) StringCchCatA(filepath, STLINK_ARRAY_SIZE(file_pattern), "\\"); StringCchCatA(filepath, STLINK_ARRAY_SIZE(file_pattern), ffd.cFileName); process_chipfile(filepath); - } while(FindNextFileA(hFind, &ffd) != 0); + } while (FindNextFileA(hFind, &ffd) != 0); FindClose(hFind); } From 274be86616801d65cdc0e1f1bf380c98a7aa5b85 Mon Sep 17 00:00:00 2001 From: Oleksiy Slyshyk Date: Fri, 13 Aug 2021 22:40:24 +0300 Subject: [PATCH 302/503] Update src/stlink-lib/chipid.c Co-authored-by: Grzegorz Szymaszek --- src/stlink-lib/chipid.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index bd5a7b9e2..d7e7f1328 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -1144,7 +1144,7 @@ void init_chipids(char *dir_to_scan) return; }; hFind = FindFirstFileA(file_pattern, &ffd); - if (INVALID_HANDLE_VALUE == hFind){ + if (INVALID_HANDLE_VALUE == hFind) { ELOG("Can't find any chip description file in %s.\n", file_pattern); return; } From 9ec951c008b84f89debd69929a0aba6d1e4f4a22 Mon Sep 17 00:00:00 2001 From: Oleksiy Slyshyk Date: Fri, 13 Aug 2021 23:18:46 +0300 Subject: [PATCH 303/503] uncrustify chipid.c --- src/stlink-lib/chipid.c | 554 ++++++++++++++++++++-------------------- 1 file changed, 276 insertions(+), 278 deletions(-) diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index d7e7f1328..dcf677909 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -1,18 +1,18 @@ #include #include "chipid.h" -#include -#include +#include +#include #include #include #include -// This is the old chipid "database". +// This is the old chipid "database". // It is kept here for now to be able to compare the -// result between the "old code" and the "new code". -// For now if you need to change something, please -// change it both here and in the corresponding -// config/chips/*.chip file. +// result between the "old code" and the "new code". +// For now if you need to change something, please +// change it both here and in the corresponding +// config/chips/*.chip file. static struct stlink_chipid_params devices[] = { { @@ -26,10 +26,9 @@ static struct stlink_chipid_params devices[] = { .sram_size = 0x80000, // "SRAM" byte size in hex from .bootrom_base = 0x00200000, // "System memory" starting address from .bootrom_size = 0xEDC0, - .option_base = - STM32_F7_OPTION_BYTES_BASE, // Used for reading back the option - // bytes, writing uses FLASH_F7_OPTCR - // and FLASH_F7_OPTCR1 + .option_base = STM32_F7_OPTION_BYTES_BASE, /* Used for reading back the option + bytes, writing uses FLASH_F7_OPTCR + and FLASH_F7_OPTCR1 */ .option_size = 0x20, .flags = CHIP_F_HAS_DUAL_BANK | CHIP_F_HAS_SWO_TRACING, }, @@ -42,10 +41,8 @@ static struct stlink_chipid_params devices[] = { .flash_size_reg = 0x1ff0f442, // section 41.2 .flash_pagesize = 0x800, // No flash pages .sram_size = 0x50000, // "SRAM" byte size in hex from DS Fig 18 - .bootrom_base = - 0x00100000, // "System memory" starting address from DS Fig 18 - .bootrom_size = - 0xEDC0, // "System memory" byte size in hex from DS Fig 18 + .bootrom_base = 0x00100000, // "System memory" starting address from DS Fig 18 + .bootrom_size = 0xEDC0, // "System memory" byte size in hex from DS Fig 18 .flags = CHIP_F_HAS_SWO_TRACING, }, { @@ -57,10 +54,8 @@ static struct stlink_chipid_params devices[] = { .flash_size_reg = 0x1ff07a22, // section 35.2 .flash_pagesize = 0x800, // No flash pages .sram_size = 0x40000, // "SRAM" byte size in hex from DS Fig 24 - .bootrom_base = - 0x00100000, // "System memory" starting address from DS Fig 24 - .bootrom_size = - 0xEDC0, // "System memory" byte size in hex from DS Fig 24 + .bootrom_base = 0x00100000, // "System memory" starting address from DS Fig 24 + .bootrom_size = 0xEDC0, // "System memory" byte size in hex from DS Fig 24 .flags = CHIP_F_HAS_SWO_TRACING, }, { @@ -323,7 +318,7 @@ static struct stlink_chipid_params devices[] = { .flags = CHIP_F_HAS_SWO_TRACING, }, { - // STM32F303xB/C, STM32F358, STM32F302xBxC + // STM32F303xB/C, STM32F358, STM32F302xBxC // RM0316, RM0365 .chip_id = STLINK_CHIPID_STM32_F3, .description = "F302/F303/F358", @@ -389,8 +384,7 @@ static struct stlink_chipid_params devices[] = { .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) .flash_pagesize = 0x800, // Page sizes listed in Table 4 .sram_size = 0x4000, // "SRAM" byte size in hex from Table 2 - .bootrom_base = - 0x1fffC800, // "System memory" starting address from Table 2 + .bootrom_base = 0x1fffC800, // "System memory" starting address from Table 2 .bootrom_size = 0x3000, // "System memory" byte size in hex from Table 2 .option_base = STM32_F0_OPTION_BYTES_BASE, .option_size = 16, @@ -404,8 +398,7 @@ static struct stlink_chipid_params devices[] = { .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) .flash_pagesize = 0x400, // Page sizes listed in Table 4 .sram_size = 0x2000, // "SRAM" byte size in hex from Table 2 - .bootrom_base = - 0x1fffec00, // "System memory" starting address from Table 2 + .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2 .bootrom_size = 0xC00, // "System memory" byte size in hex from Table 2 .option_base = STM32_F0_OPTION_BYTES_BASE, .option_size = 16, @@ -419,8 +412,7 @@ static struct stlink_chipid_params devices[] = { .flash_size_reg = 0x1FFF7A22, // "Flash size data register" (pg1135) .flash_pagesize = 0x4000, // Table 5. Flash module organization ? .sram_size = 0x40000, // "SRAM" byte size in hex from Table 4 - .bootrom_base = - 0x1FFF0000, // "System memory" starting address from Table 4 + .bootrom_base = 0x1FFF0000, // "System memory" starting address from Table 4 .bootrom_size = 0x7800, // "System memory" byte size in hex from Table 4 .flags = CHIP_F_HAS_SWO_TRACING, }, @@ -431,13 +423,11 @@ static struct stlink_chipid_params devices[] = { .description = "F413/F423", .flash_type = STLINK_FLASH_TYPE_F4, .flash_size_reg = 0x1FFF7A22, // "Flash size data register" Section 35.2 - .flash_pagesize = - 0x4000, // Table 5. Flash module organization (variable sector - // sizes, but 0x4000 is smallest) + .flash_pagesize = 0x4000, // Table 5. Flash module organization (variable sector + // sizes, but 0x4000 is smallest) .sram_size = 0x50000, // "SRAM" byte size in hex from Figure 2 (Table 4 // only says 0x40000) - .bootrom_base = - 0x1FFF0000, // "System memory" starting address from Table 4 + .bootrom_base = 0x1FFF0000, // "System memory" starting address from Table 4 .bootrom_size = 0x7800, // "System memory" byte size in hex from Table 4 .flags = CHIP_F_HAS_SWO_TRACING, }, @@ -450,8 +440,7 @@ static struct stlink_chipid_params devices[] = { .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) .flash_pagesize = 0x800, // Page sizes listed in Table 4 (pg 56) .sram_size = 0x8000, // "SRAM" byte size in hex from Table 2 (pg 50) - .bootrom_base = - 0x1fffd800, // "System memory" starting address from Table 2 + .bootrom_base = 0x1fffd800, // "System memory" starting address from Table 2 .bootrom_size = 0x2000, // "System memory" byte size in hex from Table 2 .option_base = STM32_F0_OPTION_BYTES_BASE, .option_size = 16, @@ -465,8 +454,7 @@ static struct stlink_chipid_params devices[] = { .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) .flash_pagesize = 0x400, // Page sizes listed in Table 4 .sram_size = 0x1800, // "SRAM" byte size in hex from Table 2 - .bootrom_base = - 0x1fffec00, // "System memory" starting address from Table 2 + .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2 .bootrom_size = 0xC00, // "System memory" byte size in hex from Table 2 .option_base = STM32_F0_OPTION_BYTES_BASE, .option_size = 16, @@ -480,8 +468,7 @@ static struct stlink_chipid_params devices[] = { .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) .flash_pagesize = 0x400, // Page sizes listed in Table 4 .sram_size = 0x1000, // "SRAM" byte size in hex from Table 2 - .bootrom_base = - 0x1fffec00, // "System memory" starting address from Table 2 + .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2 .bootrom_size = 0xC00, // "System memory" byte size in hex from Table 2 .option_base = STM32_F0_OPTION_BYTES_BASE, .option_size = 16, @@ -580,17 +567,14 @@ static struct stlink_chipid_params devices[] = { .chip_id = STLINK_CHIPID_STM32_L4, .description = "L47x/L48x", .flash_type = STLINK_FLASH_TYPE_L4, - .flash_size_reg = - 0x1FFF75e0, // "Flash size data register" (sec 45.2, page 1671) - .flash_pagesize = - 0x800, // 2k (sec 3.2, page 78; also appears in sec 3.3.1 + .flash_size_reg = 0x1FFF75e0, // "Flash size data register" (sec 45.2, page 1671) + .flash_pagesize = 0x800, // 2k (sec 3.2, page 78; also appears in sec 3.3.1 // and tables 4-6 on pages 79-81) // SRAM1 is "up to" 96k in the standard Cortex-M memory map; // SRAM2 is 32k mapped at at 0x10000000 (sec 2.3, page 73 for // sizes; table 2, page 74 for SRAM2 location) .sram_size = 0x18000, - .bootrom_base = - 0x1fff0000, // Tables 4-6, pages 80-81 (Bank 1 system memory) + .bootrom_base = 0x1fff0000, // Tables 4-6, pages 80-81 (Bank 1 system memory) .bootrom_size = 0x7000, // 28k (per bank), same source as base .option_base = STM32_L4_OPTION_BYTES_BASE, .option_size = 4, @@ -602,12 +586,10 @@ static struct stlink_chipid_params devices[] = { .chip_id = STLINK_CHIPID_STM32_L4Rx, .description = "L4Rx", .flash_type = STLINK_FLASH_TYPE_L4, - .flash_size_reg = - 0x1fff75e0, // "Flash size data register" (sec 58.2, page 2274) + .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 58.2, page 2274) .flash_pagesize = 0x1000, // 4k, section 3.3, pg 117-120 - //TODO: flash_pagesize can be 8k depend on the dual-bank mode and flash size - .sram_size = - 0xa0000, // 192k (SRAM1) + 64k SRAM2 + 384k SRAM3 = 640k, or 0xA0000 + // TODO: flash_pagesize can be 8k depend on the dual-bank mode and flash size + .sram_size = 0xa0000, // 192k (SRAM1) + 64k SRAM2 + 384k SRAM3 = 640k, or 0xA0000 .bootrom_base = 0x1fff0000, // 3.3.1, pg 117 .bootrom_size = 0x7000, // 28k (per bank), same source as base (pg 117) .flags = CHIP_F_HAS_DUAL_BANK | CHIP_F_HAS_SWO_TRACING, @@ -618,12 +600,10 @@ static struct stlink_chipid_params devices[] = { .chip_id = STLINK_CHIPID_STM32_L4PX, .description = "L4Px", .flash_type = STLINK_FLASH_TYPE_L4, - .flash_size_reg = - 0x1fff75e0, // "Flash size data register" (sec 58.2, page 2274) + .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 58.2, page 2274) .flash_pagesize = 0x1000, // 4k, section 3.3, pg 117-120 - //TODO: flash_pagesize can be 8k depend on the dual-bank mode and flash size - .sram_size = - 0xa0000, // 192k (SRAM1) + 64k SRAM2 + 384k SRAM3 = 640k, or 0xA0000 + // TODO: flash_pagesize can be 8k depend on the dual-bank mode and flash size + .sram_size = 0xa0000, // 192k (SRAM1) + 64k SRAM2 + 384k SRAM3 = 640k, or 0xA0000 .bootrom_base = 0x1fff0000, // 3.3.1, pg 117 .bootrom_size = 0x7000, // 28k (per bank), same source as base (pg 117) .flags = CHIP_F_HAS_DUAL_BANK | CHIP_F_HAS_SWO_TRACING, @@ -638,11 +618,10 @@ static struct stlink_chipid_params devices[] = { // sec 47.2, page 1586) .flash_pagesize = 0x800, // 2k (DS12469, sec 3.4, page 17) // SRAM1 is 32k at 0x20000000 - // SRAM2 is 8k at 0x10000000 and 0x20008000 - // (DS12469, sec 3.5, page 18) + // SRAM2 is 8k at 0x10000000 and 0x20008000 + // (DS12469, sec 3.5, page 18) .sram_size = 0xa000, // 40k (DS12469, sec 3.5, page 18) - .bootrom_base = - 0x1fff0000, // System Memory (RM0394, sec 3.3.1, table 8) + .bootrom_base = 0x1fff0000, // System Memory (RM0394, sec 3.3.1, table 8) .bootrom_size = 0x7000, // 28k, same source as base .flags = CHIP_F_HAS_SWO_TRACING, }, @@ -652,17 +631,14 @@ static struct stlink_chipid_params devices[] = { .chip_id = STLINK_CHIPID_STM32_L43x_L44x, .description = "L43x/L44x", .flash_type = STLINK_FLASH_TYPE_L4, - .flash_size_reg = - 0x1fff75e0, // "Flash size data register" (sec 43.2, page 1410) - .flash_pagesize = - 0x800, // 2k (sec 3.2, page 74; also appears in sec 3.3.1 + .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 43.2, page 1410) + .flash_pagesize = 0x800, // 2k (sec 3.2, page 74; also appears in sec 3.3.1 // and tables 7-8 on pages 75-76) // SRAM1 is "up to" 64k in the standard Cortex-M memory map; // SRAM2 is 16k mapped at 0x10000000 (sec 2.3, page 73 for // sizes; table 2, page 74 for SRAM2 location) .sram_size = 0xc000, - .bootrom_base = - 0x1fff0000, // Tables 4-6, pages 80-81 (Bank 1 system memory) + .bootrom_base = 0x1fff0000, // Tables 4-6, pages 80-81 (Bank 1 system memory) .bootrom_size = 0x7000, // 28k (per bank), same source as base .option_base = STM32_L4_OPTION_BYTES_BASE, .option_size = 4, @@ -674,10 +650,8 @@ static struct stlink_chipid_params devices[] = { .chip_id = STLINK_CHIPID_STM32_L496x_L4A6x, .description = "L496x/L4A6x", .flash_type = STLINK_FLASH_TYPE_L4, - .flash_size_reg = - 0x1fff75e0, // "Flash size data register" (sec 49.2, page 1809) - .flash_pagesize = - 0x800, // Page erase (2 Kbyte) (sec 3.2, page 93) + .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 49.2, page 1809) + .flash_pagesize = 0x800, // Page erase (2 Kbyte) (sec 3.2, page 93) // SRAM1 is 256k at 0x20000000 // SRAM2 is 64k at 0x20040000 (sec 2.2.1, fig 2, page 74) .sram_size = 0x40000, // Embedded SRAM (sec 2.4, page 84) @@ -693,10 +667,8 @@ static struct stlink_chipid_params devices[] = { .chip_id = STLINK_CHIPID_STM32_L45x_L46x, .description = "L45x/46x", .flash_type = STLINK_FLASH_TYPE_L4, - .flash_size_reg = - 0x1fff75e0, // "Flash size data register" (sec 45.2, page 1463) - .flash_pagesize = - 0x800, // 2k (sec 3.2, page 73; also appears in sec 3.3.1 + .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 45.2, page 1463) + .flash_pagesize = 0x800, // 2k (sec 3.2, page 73; also appears in sec 3.3.1 // and tables 7 on pages 73-74) // SRAM1 is 128k at 0x20000000; // SRAM2 is 32k mapped at 0x10000000 (sec 2.4.2, table 3-4, @@ -783,8 +755,7 @@ static struct stlink_chipid_params devices[] = { .description = "G43x/G44x", .flash_type = STLINK_FLASH_TYPE_G4, .flash_size_reg = 0x1FFF75E0, // Section 47.2 - .flash_pagesize = - 0x800, // 2k (sec 3.3.1) + .flash_pagesize = 0x800, // 2k (sec 3.3.1) // SRAM1 is 16k at 0x20000000 // SRAM2 is 6k at 0x20014000 // SRAM3/CCM is 10k at 0x10000000, aliased at 0x20018000 @@ -802,8 +773,7 @@ static struct stlink_chipid_params devices[] = { .description = "G47x/G48x", .flash_type = STLINK_FLASH_TYPE_G4, .flash_size_reg = 0x1FFF75E0, // Section 47.2 - .flash_pagesize = - 0x800, // 2k (sec 3.3.1) + .flash_pagesize = 0x800, // 2k (sec 3.3.1) // SRAM1 is 80k at 0x20000000 // SRAM2 is 16k at 0x20014000 // SRAM3/CCM is 32k at 0x10000000, aliased at 0x20018000 @@ -821,8 +791,7 @@ static struct stlink_chipid_params devices[] = { .description = "G49x/G4Ax", .flash_type = STLINK_FLASH_TYPE_G4, .flash_size_reg = 0x1FFF75E0, // Section 47.2 - .flash_pagesize = - 0x800, // 2k (sec 3.3.1) + .flash_pagesize = 0x800, // 2k (sec 3.3.1) // SRAM1 is 80k at 0x20000000 // SRAM2 is 16k at 0x20014000 // SRAM3/CCM is 32k at 0x10000000, aliased at 0x20018000 @@ -866,10 +835,8 @@ static struct stlink_chipid_params devices[] = { .flash_size_reg = 0x1ff1e880, // "Flash size register" (pg3272) .flash_pagesize = 0x20000, // 128k sector (pg147) .sram_size = 0x20000, // 128k "DTCM" from Table 7 - .bootrom_base = - 0x1ff00000, // "System memory" starting address from Table 7 - .bootrom_size = - 0x20000, // "System memory" byte size in hex from Table 7 + .bootrom_base = 0x1ff00000, // "System memory" starting address from Table 7 + .bootrom_size = 0x20000, // "System memory" byte size in hex from Table 7 .option_base = STM32_H7_OPTION_BYTES_BASE, .option_size = 44, // FLASH_OPTSR_CUR to FLASH_BOOT_PRGR from Table 28 .flags = CHIP_F_HAS_DUAL_BANK | CHIP_F_HAS_SWO_TRACING, @@ -883,8 +850,7 @@ static struct stlink_chipid_params devices[] = { .flash_size_reg = 0x08FFF80C, // "Flash size register" (p.2949) .flash_pagesize = 0x2000, // 8k sector (p.146) .sram_size = 0x20000, // 128k "DTCM" (Figure 1) - .bootrom_base = - 0x1FF00000, // "System memory" starting address (Table 12-14) + .bootrom_base = 0x1FF00000, // "System memory" starting address (Table 12-14) .bootrom_size = 0x20000, // "System memory" byte size in hex splitted to // two banks (Table 12-14) .option_base = STM32_H7_OPTION_BYTES_BASE, @@ -900,8 +866,7 @@ static struct stlink_chipid_params devices[] = { .flash_size_reg = 0x1FF1E880, // "Flash size register" (p.3286) .flash_pagesize = 0x20000, // 128k sector (p.152) .sram_size = 0x20000, // 128k "DTCM" (Figure 1) - .bootrom_base = - 0x1FF00000, // "System memory" starting address (Table 6) + .bootrom_base = 0x1FF00000, // "System memory" starting address (Table 6) .bootrom_size = 0x20000, // "System memory" byte size in hex (Table 6) .option_base = STM32_H7_OPTION_BYTES_BASE, .option_size = 44, @@ -922,209 +887,239 @@ static struct stlink_chipid_params devices[] = { }; struct stlink_chipid_params *stlink_chipid_get_params_old(uint32_t chipid) { - struct stlink_chipid_params *params = NULL; + struct stlink_chipid_params *params = NULL; - for (size_t n = 0; n < STLINK_ARRAY_SIZE(devices); n++) - if (devices[n].chip_id == chipid) { - params = &devices[n]; - break; - } + for (size_t n = 0; n < STLINK_ARRAY_SIZE(devices); n++) + if (devices[n].chip_id == chipid) { + params = &devices[n]; + break; + } - return (params); + return (params); } static struct stlink_chipid_params *devicelist; - -void dump_a_chip (FILE *fp, struct stlink_chipid_params *dev) -{ - fprintf(fp, "# Chip-ID file for %s\n", dev->description); - fprintf(fp, "#\n"); - fprintf(fp, "chip_id 0x%x\n", dev->chip_id); - fprintf(fp, "description %s\n", dev->description); - fprintf(fp, "flash_type %d\n", dev->flash_type); - fprintf(fp, "flash_pagesize 0x%x\n", dev->flash_pagesize); - fprintf(fp, "sram_size 0x%x\n", dev->sram_size); - fprintf(fp, "bootrom_base 0x%x\n", dev->bootrom_base); - fprintf(fp, "bootrom_size 0x%x\n", dev->bootrom_size); - fprintf(fp, "option_base 0x%x\n", dev->option_base); - fprintf(fp, "option_size 0x%x\n", dev->option_size); - fprintf(fp, "flags %d\n\n", dev->flags); +void dump_a_chip (FILE *fp, struct stlink_chipid_params *dev) { + fprintf(fp, "# Chip-ID file for %s\n", dev->description); + fprintf(fp, "#\n"); + fprintf(fp, "chip_id 0x%x\n", dev->chip_id); + fprintf(fp, "description %s\n", dev->description); + fprintf(fp, "flash_type %d\n", dev->flash_type); + fprintf(fp, "flash_pagesize 0x%x\n", dev->flash_pagesize); + fprintf(fp, "sram_size 0x%x\n", dev->sram_size); + fprintf(fp, "bootrom_base 0x%x\n", dev->bootrom_base); + fprintf(fp, "bootrom_size 0x%x\n", dev->bootrom_size); + fprintf(fp, "option_base 0x%x\n", dev->option_base); + fprintf(fp, "option_size 0x%x\n", dev->option_size); + fprintf(fp, "flags %d\n\n", dev->flags); } - - struct stlink_chipid_params *stlink_chipid_get_params(uint32_t chipid) { - struct stlink_chipid_params *params = NULL; - struct stlink_chipid_params *p2; + struct stlink_chipid_params *params = NULL; + struct stlink_chipid_params *p2; - // fprintf (stderr, "getparams: %x\n", chipid); - for (params = devicelist ; params != NULL ; params = params -> next) - if (params->chip_id == chipid) break; + //fprintf (stderr, "getparams: %x\n", chipid); + for (params = devicelist; params != NULL; params = params->next) + if (params->chip_id == chipid) { + break; + } - p2 = stlink_chipid_get_params_old(chipid); + p2 = stlink_chipid_get_params_old(chipid); #if 1 - if (params == NULL) { - params = p2; - } else if (memcmp (p2, params, sizeof (struct stlink_chipid_params) - sizeof (struct stlink_chipid_params *)) != 0) { - //fprintf (stderr, "Error, chipid params not identical\n"); - //return NULL; - fprintf(stderr, "---------- old ------------\n"); - dump_a_chip(stderr, p2); - fprintf(stderr, "---------- new ------------\n"); - dump_a_chip(stderr, params); - } + if (params == NULL) { + params = p2; + } else if (memcmp (p2, params, sizeof(struct stlink_chipid_params) - sizeof(struct stlink_chipid_params *)) != 0) { + // fprintf (stderr, "Error, chipid params not identical\n"); + // return NULL; + fprintf(stderr, "---------- old ------------\n"); + dump_a_chip(stderr, p2); + fprintf(stderr, "---------- new ------------\n"); + dump_a_chip(stderr, params); + } #endif - return(params); + return(params); } +void process_chipfile(char *fname) { + FILE *fp; + char *p, *pp, buf[1025]; + char word[64], value[64]; + struct stlink_chipid_params *ts; + int nc; + + // fprintf (stderr, "processing chipfile %s.\n", fname); + fp = fopen(fname, "r"); -void process_chipfile(char *fname) -{ - FILE *fp; - char *p, *pp, buf[1025]; - char word[64], value[64]; - struct stlink_chipid_params *ts; - int nc; + if (!fp) { + perror(fname); + return; + } - //fprintf (stderr, "processing chipfile %s.\n", fname); - fp = fopen(fname, "r"); - if (!fp) { - perror(fname); - return; - } + ts = calloc(sizeof(struct stlink_chipid_params), 1); - ts = calloc(sizeof (struct stlink_chipid_params), 1); - while (fgets(buf, 1024, fp) != NULL) { - for (p=buf;isspace (*p);p++); - if (!*p) continue; // we hit end-of-line wiht only whitespace - if (*p == '#') continue; // ignore comments. + while (fgets(buf, 1024, fp) != NULL) { + for (p = buf; isspace (*p); p++); - sscanf(p, "%s %s", word, value); - if (strcmp(word, "chip_id") == 0) { - if (sscanf(value, "%i", &ts->chip_id) < 1) - fprintf(stderr, "Failed to parse chip id\n"); - } else if (strcmp (word, "description") == 0) { - //ts->description = strdup (value); - buf[strlen(p)-1] = 0; // chomp newline - sscanf(p, "%*s %n", &nc); - ts->description = strdup(p+nc); - } else if (strcmp (word, "flash_type") == 0) { - if (sscanf(value, "%i", (int *) &ts->flash_type) < 1) - fprintf(stderr, "Failed to parse flash type\n"); - else if (ts->flash_type <= STLINK_FLASH_TYPE_UNKNOWN || ts->flash_type >= STLINK_FLASH_TYPE_MAX) - fprintf(stderr, "Unrecognized flash type\n"); - } else if (strcmp (word, "flash_size_reg") == 0) { - if (sscanf(value, "%i", &ts->flash_size_reg) < 1) - fprintf(stderr, "Failed to parse flash size reg\n"); - } else if (strcmp (word, "flash_pagesize") == 0) { - if (sscanf(value, "%i", &ts->flash_pagesize) < 1) - fprintf(stderr, "Failed to parse flash page size\n"); - } else if (strcmp (word, "sram_size") == 0) { - if (sscanf(value, "%i", &ts->sram_size) < 1) - fprintf(stderr, "Failed to parse SRAM size\n"); - } else if (strcmp (word, "bootrom_base") == 0) { - if (sscanf(value, "%i", &ts->bootrom_base) < 1) - fprintf(stderr, "Failed to parse BootROM base\n"); - } else if (strcmp (word, "bootrom_size") == 0) { - if (sscanf(value, "%i", &ts->bootrom_size) < 1) - fprintf(stderr, "Failed to parse BootROM size\n"); - } else if (strcmp (word, "option_base") == 0) { - if (sscanf(value, "%i", &ts->option_base) < 1) - fprintf(stderr, "Failed to parse option base\n"); - } else if (strcmp (word, "option_size") == 0) { - if (sscanf(value, "%i", &ts->option_size) < 1) - fprintf(stderr, "Failed to parse option size\n"); - } else if (strcmp (word, "flags") == 0) { - pp = strtok (p, " \t\n"); - while ((pp = strtok (NULL, " \t\n")) ) { - if (strcmp (pp, "none") == 0) ts->flags = 0; // not necessary: calloc did this already. - else if (strcmp (pp, "dualbank") == 0) ts->flags |= CHIP_F_HAS_DUAL_BANK; - else if (strcmp (pp, "swo") == 0) ts->flags |= CHIP_F_HAS_SWO_TRACING; - else fprintf (stderr, "Unknown flags word in %s: '%s'\n", - fname, pp); - } - sscanf(value, "%x", &ts->flags); - } else { - fprintf (stderr, "Unknown keyword in %s: %s\n", - fname, word); + if (!*p) { + continue; // we hit end-of-line wiht only whitespace + } + + if (*p == '#') { + continue; // ignore comments. + } + + sscanf(p, "%s %s", word, value); + + if (strcmp(word, "chip_id") == 0) { + if (sscanf(value, "%i", &ts->chip_id) < 1) { + fprintf(stderr, "Failed to parse chip id\n"); + } + } else if (strcmp (word, "description") == 0) { + // ts->description = strdup (value); + buf[strlen(p) - 1] = 0; // chomp newline + sscanf(p, "%*s %n", &nc); + ts->description = strdup(p + nc); + } else if (strcmp (word, "flash_type") == 0) { + if (sscanf(value, "%i", (int *)&ts->flash_type) < 1) { + fprintf(stderr, "Failed to parse flash type\n"); + } else if (ts->flash_type <= STLINK_FLASH_TYPE_UNKNOWN || ts->flash_type >= STLINK_FLASH_TYPE_MAX) { + fprintf(stderr, "Unrecognized flash type\n"); + } + } else if (strcmp (word, "flash_size_reg") == 0) { + if (sscanf(value, "%i", &ts->flash_size_reg) < 1) { + fprintf(stderr, "Failed to parse flash size reg\n"); + } + } else if (strcmp (word, "flash_pagesize") == 0) { + if (sscanf(value, "%i", &ts->flash_pagesize) < 1) { + fprintf(stderr, "Failed to parse flash page size\n"); + } + } else if (strcmp (word, "sram_size") == 0) { + if (sscanf(value, "%i", &ts->sram_size) < 1) { + fprintf(stderr, "Failed to parse SRAM size\n"); + } + } else if (strcmp (word, "bootrom_base") == 0) { + if (sscanf(value, "%i", &ts->bootrom_base) < 1) { + fprintf(stderr, "Failed to parse BootROM base\n"); + } + } else if (strcmp (word, "bootrom_size") == 0) { + if (sscanf(value, "%i", &ts->bootrom_size) < 1) { + fprintf(stderr, "Failed to parse BootROM size\n"); + } + } else if (strcmp (word, "option_base") == 0) { + if (sscanf(value, "%i", &ts->option_base) < 1) { + fprintf(stderr, "Failed to parse option base\n"); + } + } else if (strcmp (word, "option_size") == 0) { + if (sscanf(value, "%i", &ts->option_size) < 1) { + fprintf(stderr, "Failed to parse option size\n"); + } + } else if (strcmp (word, "flags") == 0) { + pp = strtok (p, " \t\n"); + + while ((pp = strtok (NULL, " \t\n"))) { + if (strcmp (pp, "none") == 0) { + ts->flags = 0; // not necessary: calloc did this already. + } else if (strcmp (pp, "dualbank") == 0) { + ts->flags |= CHIP_F_HAS_DUAL_BANK; + } else if (strcmp (pp, "swo") == 0) { + ts->flags |= CHIP_F_HAS_SWO_TRACING; + } else { + fprintf (stderr, "Unknown flags word in %s: '%s'\n", + fname, pp); + } + } + + sscanf(value, "%x", &ts->flags); + } else { + fprintf (stderr, "Unknown keyword in %s: %s\n", + fname, word); + } } - } - ts->next = devicelist; - devicelist = ts; + + ts->next = devicelist; + devicelist = ts; } -void dump_chips (void) -{ - struct stlink_chipid_params *ts; - char *p, buf[100]; - FILE *fp; +void dump_chips (void) { + struct stlink_chipid_params *ts; + char *p, buf[100]; + FILE *fp; - for (size_t n = 0; n < STLINK_ARRAY_SIZE(devices); n++) { - ts = &devices[n]; + for (size_t n = 0; n < STLINK_ARRAY_SIZE(devices); n++) { + ts = &devices[n]; - strcpy(buf, ts->description); - while ((p = strchr(buf, '/'))) // change slashes to underscore. - *p = '_'; - strcat(buf, ".chip"); - fp = fopen(buf, "w"); - fprintf(fp, "# Chip-ID file for %s\n", ts->description); - fprintf(fp, "#\n"); - fprintf(fp, "chip_id %x\n", ts->chip_id); - fprintf(fp, "description %s\n", ts->description); - fprintf(fp, "flash_type %x\n", ts->flash_type); - fprintf(fp, "flash_pagesize %x\n", ts->flash_pagesize); - fprintf(fp, "sram_size %x\n", ts->sram_size); - fprintf(fp, "bootrom_base %x\n", ts->bootrom_base); - fprintf(fp, "bootrom_size %x\n", ts->bootrom_size); - fprintf(fp, "option_base %x\n", ts->option_base); - fprintf(fp, "option_size %x\n", ts->option_size); - fprintf(fp, "flags %x\n\n", ts->flags); - fclose(fp); - } + strcpy(buf, ts->description); + + while ((p = strchr(buf, '/'))) // change slashes to underscore. + *p = '_'; + + strcat(buf, ".chip"); + fp = fopen(buf, "w"); + fprintf(fp, "# Chip-ID file for %s\n", ts->description); + fprintf(fp, "#\n"); + fprintf(fp, "chip_id %x\n", ts->chip_id); + fprintf(fp, "description %s\n", ts->description); + fprintf(fp, "flash_type %x\n", ts->flash_type); + fprintf(fp, "flash_pagesize %x\n", ts->flash_pagesize); + fprintf(fp, "sram_size %x\n", ts->sram_size); + fprintf(fp, "bootrom_base %x\n", ts->bootrom_base); + fprintf(fp, "bootrom_size %x\n", ts->bootrom_size); + fprintf(fp, "option_base %x\n", ts->option_base); + fprintf(fp, "option_size %x\n", ts->option_size); + fprintf(fp, "flags %x\n\n", ts->flags); + fclose(fp); + } } #if defined(STLINK_HAVE_DIRENT_H) #include -void init_chipids(char *dir_to_scan) -{ - DIR *d; - size_t nl; // namelen - struct dirent *dir; - if (!dir_to_scan) dir_to_scan = "./"; +void init_chipids(char *dir_to_scan) { + DIR *d; + size_t nl; // namelen + struct dirent *dir; + + if (!dir_to_scan) { + dir_to_scan = "./"; + } - devicelist = NULL; - //dump_chips (); - d = opendir(dir_to_scan); - if (d) { - while ((dir = readdir(d)) != NULL) { - nl = strlen(dir->d_name); - if (strcmp(dir->d_name + nl - 5, ".chip") == 0) { - char buf[1024]; - sprintf(buf, "%s/%s", dir_to_scan, dir->d_name); - process_chipfile(buf); - } + devicelist = NULL; + // dump_chips (); + d = opendir(dir_to_scan); + + if (d) { + while ((dir = readdir(d)) != NULL) { + nl = strlen(dir->d_name); + + if (strcmp(dir->d_name + nl - 5, ".chip") == 0) { + char buf[1024]; + sprintf(buf, "%s/%s", dir_to_scan, dir->d_name); + process_chipfile(buf); + } + } + + closedir(d); + } else { + perror (dir_to_scan); + return; // XXX } - closedir(d); - } else { - perror (dir_to_scan); - return; // XXX - } + #if 0 - { - struct stlink_chipid_params *p, *op; - int i; - p = devicelist; - for (i=0;i<5;i++, p = p->next) { - op = stlink_chipid_get_params_old (p->chip_id); - fprintf (stderr, "---------- old ------------\n"); - dump_a_chip (stderr, op); - fprintf (stderr, "---------- new ------------\n"); - dump_a_chip (stderr, p); + { + struct stlink_chipid_params *p, *op; + int i; + p = devicelist; + for (i = 0; i < 5; i++, p = p->next) { + op = stlink_chipid_get_params_old (p->chip_id); + fprintf (stderr, "---------- old ------------\n"); + dump_a_chip (stderr, op); + fprintf (stderr, "---------- new ------------\n"); + dump_a_chip (stderr, p); + + } } - } #endif } #endif //STLINK_HAVE_DIRENT_H @@ -1132,32 +1127,35 @@ void init_chipids(char *dir_to_scan) #if defined(_WIN32) && !defined(STLINK_HAVE_DIRENT_H) #include #include -void init_chipids(char *dir_to_scan) -{ - HANDLE hFind = INVALID_HANDLE_VALUE; - WIN32_FIND_DATAA ffd; - char file_pattern[MAX_PATH] = {0}; - char filepath[MAX_PATH] = {0}; - StringCchCopyA(file_pattern, STLINK_ARRAY_SIZE(file_pattern), dir_to_scan); - if (FAILED(StringCchCatA(file_pattern, STLINK_ARRAY_SIZE(file_pattern), "\\*.chip"))) { - ELOG("Path to chips's dir too long.\n"); - return; - }; - hFind = FindFirstFileA(file_pattern, &ffd); - if (INVALID_HANDLE_VALUE == hFind) { - ELOG("Can't find any chip description file in %s.\n", file_pattern); - return; - } +void init_chipids(char *dir_to_scan) { + HANDLE hFind = INVALID_HANDLE_VALUE; + WIN32_FIND_DATAA ffd; + char file_pattern[MAX_PATH] = {0}; + char filepath[MAX_PATH] = {0}; + StringCchCopyA(file_pattern, STLINK_ARRAY_SIZE(file_pattern), dir_to_scan); + + if (FAILED(StringCchCatA(file_pattern, STLINK_ARRAY_SIZE(file_pattern), "\\*.chip"))) { + ELOG("Path to chips's dir too long.\n"); + return; + } + + ; + hFind = FindFirstFileA(file_pattern, &ffd); + + if (INVALID_HANDLE_VALUE == hFind) { + ELOG("Can't find any chip description file in %s.\n", file_pattern); + return; + } - do { - memset(filepath, 0, STLINK_ARRAY_SIZE(filepath)); - StringCchCopyA(filepath, STLINK_ARRAY_SIZE(filepath), dir_to_scan); - StringCchCatA(filepath, STLINK_ARRAY_SIZE(file_pattern), "\\"); - StringCchCatA(filepath, STLINK_ARRAY_SIZE(file_pattern), ffd.cFileName); - process_chipfile(filepath); - } while (FindNextFileA(hFind, &ffd) != 0); + do { + memset(filepath, 0, STLINK_ARRAY_SIZE(filepath)); + StringCchCopyA(filepath, STLINK_ARRAY_SIZE(filepath), dir_to_scan); + StringCchCatA(filepath, STLINK_ARRAY_SIZE(file_pattern), "\\"); + StringCchCatA(filepath, STLINK_ARRAY_SIZE(file_pattern), ffd.cFileName); + process_chipfile(filepath); + } while (FindNextFileA(hFind, &ffd) != 0); - FindClose(hFind); + FindClose(hFind); } #endif //defined(_WIN32) && !defined(STLINK_HAVE_DIRENT_H) From e5152c45c3f9b27116be9d9d07250e6088d85c5a Mon Sep 17 00:00:00 2001 From: Oleksiy Slyshyk Date: Fri, 13 Aug 2021 23:22:50 +0300 Subject: [PATCH 304/503] chipid.c: drop empty lines at end --- src/stlink-lib/chipid.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index dcf677909..42e4e92ae 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -1158,7 +1158,3 @@ void init_chipids(char *dir_to_scan) { FindClose(hFind); } #endif //defined(_WIN32) && !defined(STLINK_HAVE_DIRENT_H) - - - - From 03153d083c46d33295e5bd905d08c35472a21048 Mon Sep 17 00:00:00 2001 From: Oleksiy Slyshyk Date: Sat, 14 Aug 2021 10:57:13 +0300 Subject: [PATCH 305/503] removed redundant array --- src/stlink-lib/chipid.c | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-) diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index 42e4e92ae..d51a0edcb 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -1130,28 +1130,26 @@ void init_chipids(char *dir_to_scan) { void init_chipids(char *dir_to_scan) { HANDLE hFind = INVALID_HANDLE_VALUE; WIN32_FIND_DATAA ffd; - char file_pattern[MAX_PATH] = {0}; char filepath[MAX_PATH] = {0}; - StringCchCopyA(file_pattern, STLINK_ARRAY_SIZE(file_pattern), dir_to_scan); + StringCchCopyA(filepath, STLINK_ARRAY_SIZE(filepath), dir_to_scan); - if (FAILED(StringCchCatA(file_pattern, STLINK_ARRAY_SIZE(file_pattern), "\\*.chip"))) { + if (FAILED(StringCchCatA(filepath, STLINK_ARRAY_SIZE(filepath), "\\*.chip"))) { ELOG("Path to chips's dir too long.\n"); return; } - ; - hFind = FindFirstFileA(file_pattern, &ffd); + hFind = FindFirstFileA(filepath, &ffd); if (INVALID_HANDLE_VALUE == hFind) { - ELOG("Can't find any chip description file in %s.\n", file_pattern); + ELOG("Can't find any chip description file in %s.\n", filepath); return; } do { memset(filepath, 0, STLINK_ARRAY_SIZE(filepath)); StringCchCopyA(filepath, STLINK_ARRAY_SIZE(filepath), dir_to_scan); - StringCchCatA(filepath, STLINK_ARRAY_SIZE(file_pattern), "\\"); - StringCchCatA(filepath, STLINK_ARRAY_SIZE(file_pattern), ffd.cFileName); + StringCchCatA(filepath, STLINK_ARRAY_SIZE(filepath), "\\"); + StringCchCatA(filepath, STLINK_ARRAY_SIZE(filepath), ffd.cFileName); process_chipfile(filepath); } while (FindNextFileA(hFind, &ffd) != 0); From bef3321ea45e939003ef7802bdd2d3368f57b676 Mon Sep 17 00:00:00 2001 From: Oleksiy Slyshyk Date: Sun, 15 Aug 2021 12:18:46 +0300 Subject: [PATCH 306/503] Fixes few warnings for msvc about type conversion with possible lost data. --- src/common.c | 28 ++++++++++++++-------------- src/st-flash/flash.c | 10 +++++----- src/st-util/gdb-server.c | 22 +++++++++++----------- src/stlink-lib/flash_loader.c | 14 +++++++------- 4 files changed, 37 insertions(+), 37 deletions(-) diff --git a/src/common.c b/src/common.c index af96b70b8..601fac0b6 100644 --- a/src/common.c +++ b/src/common.c @@ -424,8 +424,8 @@ void write_uint32(unsigned char *buf, uint32_t ui) { } void write_uint16(unsigned char *buf, uint16_t ui) { - buf[0] = ui; - buf[1] = ui >> 8; + buf[0] = (uint8_t)ui; + buf[1] = (uint8_t)(ui >> 8); } uint32_t read_uint32(const unsigned char *c, const int pt) { @@ -1274,7 +1274,7 @@ static void stop_wdg_in_debug(stlink_t *sl) { case STLINK_FLASH_TYPE_F1_XL: case STLINK_FLASH_TYPE_G4: dbgmcu_cr = STM32F0_DBGMCU_CR; - set = (1 << STM32F0_DBGMCU_CR_IWDG_STOP) | + set = (1 << STM32F0_DBGMCU_CR_IWDG_STOP) | (1 << STM32F0_DBGMCU_CR_WWDG_STOP); break; case STLINK_FLASH_TYPE_F4: @@ -1442,7 +1442,7 @@ void stlink_close(stlink_t *sl) { int stlink_exit_debug_mode(stlink_t *sl) { DLOG("*** stlink_exit_debug_mode ***\n"); - if (sl->flash_type != STLINK_FLASH_TYPE_UNKNOWN && + if (sl->flash_type != STLINK_FLASH_TYPE_UNKNOWN && sl->core_stat != TARGET_RESET) { // stop debugging if the target has been identified stlink_write_debug32(sl, STLINK_REG_DHCSR, STLINK_REG_DHCSR_DBGKEY); @@ -2253,7 +2253,7 @@ static int check_file(stlink_t *sl, mapped_file_t *mf, stm32_addr_t addr) { aligned_size = (cmp_size + 4) & ~(4 - 1); } - stlink_read_mem32(sl, addr + (uint32_t)off, aligned_size); + stlink_read_mem32(sl, addr + (uint32_t)off, (uint16_t)aligned_size); if (memcmp(sl->q_buf, mf->base + off, cmp_size)) { return (-1); @@ -2342,12 +2342,12 @@ int stlink_mwrite_sram(stlink_t *sl, uint8_t *data, uint32_t length, size += 2; } // round size if needed - stlink_write_mem32(sl, addr + (uint32_t)off, size); + stlink_write_mem32(sl, addr + (uint32_t)off, (uint16_t)size); } if (length > len) { memcpy(sl->q_buf, data + len, length - len); - stlink_write_mem8(sl, addr + (uint32_t)len, length - len); + stlink_write_mem8(sl, addr + (uint32_t)len, (uint16_t)(length - len)); } error = 0; // success @@ -2409,12 +2409,12 @@ int stlink_fwrite_sram(stlink_t *sl, const char *path, stm32_addr_t addr) { size += 2; } // round size if needed - stlink_write_mem32(sl, addr + (uint32_t)off, size); + stlink_write_mem32(sl, addr + (uint32_t)off, (uint16_t)size); } if (mf.len > len) { memcpy(sl->q_buf, mf.base + len, mf.len - len); - stlink_write_mem8(sl, addr + (uint32_t)len, mf.len - len); + stlink_write_mem8(sl, addr + (uint32_t)len, (uint16_t)(mf.len - len)); } // check the file has been written @@ -2462,7 +2462,7 @@ static int stlink_read(stlink_t *sl, stm32_addr_t addr, size_t size, aligned_size = (cmp_size + 4) & ~(4 - 1); } - stlink_read_mem32(sl, addr + (uint32_t)off, aligned_size); + stlink_read_mem32(sl, addr + (uint32_t)off, (uint16_t)aligned_size); if (!fn(fn_arg, sl->q_buf, aligned_size)) { goto on_error; @@ -2641,12 +2641,12 @@ int write_buffer_to_sram(stlink_t *sl, flash_loader_t *fl, const uint8_t *buf, if (chunk) { memcpy(sl->q_buf, buf, chunk); - ret = stlink_write_mem32(sl, fl->buf_addr, chunk); + ret = stlink_write_mem32(sl, fl->buf_addr, (uint16_t)chunk); } if (rem && !ret) { memcpy(sl->q_buf, buf + chunk, rem); - ret = stlink_write_mem8(sl, (fl->buf_addr) + (uint32_t)chunk, rem); + ret = stlink_write_mem8(sl, (fl->buf_addr) + (uint32_t)chunk, (uint16_t)rem); } return (ret); @@ -3059,7 +3059,7 @@ int stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, aligned_size = (cmp_size + 4) & ~(4 - 1); } - stlink_read_mem32(sl, address + (uint32_t)off, aligned_size); + stlink_read_mem32(sl, address + (uint32_t)off, (uint16_t)aligned_size); if (memcmp(sl->q_buf, data + off, cmp_size)) { ELOG("Verification of flash failed at offset: %u\n", (unsigned int)off); @@ -3105,7 +3105,7 @@ int stm32l1_write_half_pages(stlink_t *sl, stm32_addr_t addr, uint8_t *base, for (off = 0; off < pagesize && !ret; off += 64) { size_t chunk = (pagesize - off > 64) ? 64 : pagesize - off; memcpy(sl->q_buf, base + count * pagesize + off, chunk); - ret = stlink_write_mem32(sl, addr + count * pagesize + off, chunk); + ret = stlink_write_mem32(sl, addr + count * pagesize + off, (uint16_t)chunk); } } diff --git a/src/st-flash/flash.c b/src/st-flash/flash.c index 814c981b4..ef184239f 100644 --- a/src/st-flash/flash.c +++ b/src/st-flash/flash.c @@ -152,15 +152,15 @@ int main(int ac, char** av) { } } else if (o.area == FLASH_OPTCR) { DLOG("@@@@ Write %d (%0#10x) to option control register\n", o.val, o.val); - + err = stlink_write_option_control_register32(sl, o.val); } else if (o.area == FLASH_OPTCR1) { DLOG("@@@@ Write %d (%0#10x) to option control register 1\n", o.val, o.val); - + err = stlink_write_option_control_register1_32(sl, o.val); } else if (o.area == FLASH_OPTION_BYTES_BOOT_ADD) { DLOG("@@@@ Write %d (%0#10x) to option bytes boot address\n", o.val, o.val); - + err = stlink_write_option_bytes_boot_add32(sl, o.val); } else { err = -1; @@ -194,9 +194,9 @@ int main(int ac, char** av) { goto on_error; } } else if (o.area == FLASH_OPTION_BYTES) { - uint8_t remaining_option_length = sl->option_size / 4; + size_t remaining_option_length = sl->option_size / 4; DLOG("@@@@ Read %d (%#x) option bytes from %#10x\n", remaining_option_length, remaining_option_length, sl->option_base); - + if (NULL != o.filename) { if (0 == o.size) { o.size = sl->option_size; diff --git a/src/st-util/gdb-server.c b/src/st-util/gdb-server.c index 653c7bcec..a651014c0 100644 --- a/src/st-util/gdb-server.c +++ b/src/st-util/gdb-server.c @@ -124,7 +124,7 @@ int parse_options(int argc, char** argv, st_state_t *st) { " -n, --no-reset, --hot-plug\n" "\t\t\tDo not reset board on connection.\n" " -u, --connect-under-reset\n" - "\t\t\tConnect to the board before executing any instructions.\n" + "\t\t\tConnect to the board before executing any instructions.\n" " -F 1800k, --freq=1M\n" "\t\t\tSet the frequency of the SWD/JTAG interface.\n" " --semihosting\n" @@ -167,7 +167,7 @@ int parse_options(int argc, char** argv, st_state_t *st) { st->listen_port = q; break; - + case 'm': st->persistent = true; break; @@ -586,7 +586,7 @@ char* make_memory_map(stlink_t *sl) { } else if (sl->chip_id == STLINK_CHIPID_STM32_H72x) { snprintf(map, sz, memory_map_template_H72x3x, (unsigned int)sl->flash_size, - (unsigned int)sl->flash_pgsz); + (unsigned int)sl->flash_pgsz); } else { snprintf(map, sz, memory_map_template, (unsigned int)sl->flash_size, @@ -726,7 +726,7 @@ static void init_code_breakpoints(stlink_t *sl) { // IHI0029D, p. 48, Lock Access Register stlink_write_debug32(sl, STLINK_REG_CM7_FP_LAR, STLINK_REG_CM7_FP_LAR_KEY); } - + for (int i = 0; i < code_break_num; i++) { code_breaks[i].type = 0; stlink_write_debug32(sl, STLINK_REG_CM3_FP_COMPn(i), 0); @@ -757,7 +757,7 @@ static int update_code_breakpoint(stlink_t *sl, stm32_addr_t addr, int set) { type = CODE_BREAK_REMAP; fpb_addr = addr; } - + int id = -1; for (int i = 0; i < code_break_num; i++) if (fpb_addr == code_breaks[i].addr || (set && code_breaks[i].type == 0)) { @@ -778,7 +778,7 @@ static int update_code_breakpoint(stlink_t *sl, stm32_addr_t addr, int set) { bp->type |= type; else bp->type &= ~type; - + // DDI0403E, p. 759, FP_COMPn register description mask = ((bp->type&0x03) << 30) | bp->addr | 1; @@ -936,7 +936,7 @@ struct cache_level_desc { struct cache_desc_t { unsigned used; - + // minimal line size in bytes unsigned int dminline; unsigned int iminline; @@ -988,7 +988,7 @@ static void init_cache (stlink_t *sl) { cache_desc.used = 1; cache_desc.dminline = 4 << ((ctr >> 16) & 0x0f); cache_desc.iminline = 4 << (ctr & 0x0f); - + stlink_read_debug32(sl, STLINK_REG_CM7_CLIDR, &clidr); cache_desc.louu = (clidr >> 27) & 7; @@ -1698,7 +1698,7 @@ int serve(stlink_t *sl, st_state_t *st) { for (unsigned int i = 0; i < align_count; i++) { char hextmp[3] = { hexdata[i * 2], hexdata[i * 2 + 1], 0 }; - uint8_t byte = strtoul(hextmp, NULL, 16); + uint8_t byte = (uint8_t)strtoul(hextmp, NULL, 16); sl->q_buf[i] = byte; } @@ -1714,7 +1714,7 @@ int serve(stlink_t *sl, st_state_t *st) { for (unsigned int i = 0; i < aligned_count; i++) { char hextmp[3] = { hexdata[i * 2], hexdata[i * 2 + 1], 0 }; - uint8_t byte = strtoul(hextmp, NULL, 16); + uint8_t byte = (uint8_t)strtoul(hextmp, NULL, 16); sl->q_buf[i] = byte; } @@ -1728,7 +1728,7 @@ int serve(stlink_t *sl, st_state_t *st) { if (count) { for (unsigned int i = 0; i < count; i++) { char hextmp[3] = { hexdata[i * 2], hexdata[i * 2 + 1], 0 }; - uint8_t byte = strtoul(hextmp, NULL, 16); + uint8_t byte = (uint8_t)strtoul(hextmp, NULL, 16); sl->q_buf[i] = byte; } diff --git a/src/stlink-lib/flash_loader.c b/src/stlink-lib/flash_loader.c index d2bf32563..f683c4d65 100644 --- a/src/stlink-lib/flash_loader.c +++ b/src/stlink-lib/flash_loader.c @@ -17,8 +17,8 @@ /* !!! * !!! DO NOT MODIFY FLASH LOADERS DIRECTLY! * !!! - * - * Edit assembly files in the '/flashloaders' instead. The sizes of binary + * + * Edit assembly files in the '/flashloaders' instead. The sizes of binary * flash loaders must be aligned by 4 (it's written by stlink_write_mem32) */ @@ -310,7 +310,7 @@ int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* } memcpy(sl->q_buf, loader_code, loader_size); - int ret = stlink_write_mem32(sl, sl->sram_base, loader_size); + int ret = stlink_write_mem32(sl, sl->sram_base, (uint16_t)loader_size); if (ret) { return(ret); } @@ -382,10 +382,10 @@ int stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t targe // check written byte count stlink_read_reg(sl, 2, &rr); - /* The chunk size for loading is not rounded. The flash loader - * subtracts the size of the written block (1-8 bytes) from - * the remaining size each time. A negative value may mean that - * several bytes garbage has been written due to the unaligned + /* The chunk size for loading is not rounded. The flash loader + * subtracts the size of the written block (1-8 bytes) from + * the remaining size each time. A negative value may mean that + * several bytes garbage has been written due to the unaligned * firmware size. */ if ((int32_t)rr.r[2] > 0 || (int32_t)rr.r[2] < -7) { From 698b97bbddd4505c3fa4e0af366484e29b2739e4 Mon Sep 17 00:00:00 2001 From: Oleksiy Slyshyk Date: Sun, 15 Aug 2021 12:30:09 +0300 Subject: [PATCH 307/503] fixes printf format formating --- src/st-flash/flash.c | 5 ++++- src/stlink-lib/flash_loader.c | 2 +- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/src/st-flash/flash.c b/src/st-flash/flash.c index ef184239f..51702b683 100644 --- a/src/st-flash/flash.c +++ b/src/st-flash/flash.c @@ -195,7 +195,10 @@ int main(int ac, char** av) { } } else if (o.area == FLASH_OPTION_BYTES) { size_t remaining_option_length = sl->option_size / 4; - DLOG("@@@@ Read %d (%#x) option bytes from %#10x\n", remaining_option_length, remaining_option_length, sl->option_base); + DLOG("@@@@ Read %u (%#x) option bytes from %#10x\n", + (unsigned)remaining_option_length, + (unsigned)remaining_option_length, + sl->option_base); if (NULL != o.filename) { if (0 == o.size) { diff --git a/src/stlink-lib/flash_loader.c b/src/stlink-lib/flash_loader.c index f683c4d65..7076a2cfa 100644 --- a/src/stlink-lib/flash_loader.c +++ b/src/stlink-lib/flash_loader.c @@ -280,7 +280,7 @@ int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* } else if (sl->core_id == STM32F7_CORE_ID || sl->chip_id == STLINK_CHIPID_STM32_F7 || sl->chip_id == STLINK_CHIPID_STM32_F76xxx || - sl->chip_id == STLINK_CHIPID_STM32_F72xxx) { + sl->chip_id == STLINK_CHIPID_STM32_F72xxx) { int retval; retval = loader_v_dependent_assignment(sl, &loader_code, &loader_size, From e768f737cd9f97097370cedbc3061aaf606bd700 Mon Sep 17 00:00:00 2001 From: Luca Boccassi Date: Sun, 15 Aug 2021 14:10:49 +0100 Subject: [PATCH 308/503] Bump Standards-Version to 4.5.1, no changes --- debian/control | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/debian/control b/debian/control index 3ac6af91f..e28f7c5b5 100644 --- a/debian/control +++ b/debian/control @@ -2,7 +2,7 @@ Source: stlink Priority: optional Maintainer: Luca Boccassi Build-Depends: debhelper-compat (= 12), cmake (>= 3.4.2), libusb-1.0-0-dev, libgtk-3-dev -Standards-Version: 4.5.0 +Standards-Version: 4.5.1 Rules-Requires-Root: no Section: electronics Homepage: https://github.com/stlink-org/stlink From 1fab90289ffabcda7c3123ee7106cc032c2c619e Mon Sep 17 00:00:00 2001 From: Luca Boccassi Date: Sun, 15 Aug 2021 14:11:09 +0100 Subject: [PATCH 309/503] Bump debhelper-compat to 13, no changes --- debian/control | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/debian/control b/debian/control index e28f7c5b5..faed0302c 100644 --- a/debian/control +++ b/debian/control @@ -1,7 +1,7 @@ Source: stlink Priority: optional Maintainer: Luca Boccassi -Build-Depends: debhelper-compat (= 12), cmake (>= 3.4.2), libusb-1.0-0-dev, libgtk-3-dev +Build-Depends: debhelper-compat (= 13), cmake (>= 3.4.2), libusb-1.0-0-dev, libgtk-3-dev Standards-Version: 4.5.1 Rules-Requires-Root: no Section: electronics From 607d1d3b854b0dc3fb84455f6efa21dffc578fe4 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 15 Aug 2021 15:14:45 +0200 Subject: [PATCH 310/503] General Project Update - Updated CHANGELOG.md - Updated list of contributors --- CHANGELOG.md | 18 +++++++++++++++++- contributors.txt | 1 + 2 files changed, 18 insertions(+), 1 deletion(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index b711f3890..9bbb41a98 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -12,15 +12,31 @@ Features: - Support for writing option bytes on STM32F0/F1/F3 ([#346](https://github.com/stlink-org/stlink/pull/346), [#458](https://github.com/stlink-org/stlink/pull/458), [#808](https://github.com/stlink-org/stlink/pull/808), [#1084](https://github.com/stlink-org/stlink/pull/1084), [#1112](https://github.com/stlink-org/stlink/pull/1112)) - Added chip-IDs for STM32G0B0/G0B1/G0C1/G050/G051/G061 ([#1140](https://github.com/stlink-org/stlink/pull/1140)) - Added option byte info for STM32F411XX ([#1141](https://github.com/stlink-org/stlink/pull/1141)) +- Expanded and revised list of chips ([#1145](https://github.com/stlink-org/stlink/pull/1145), [#1164](https://github.com/stlink-org/stlink/pull/1164)) +- [STM32H72X/3X]: Added full access to all device memory ([#1158](https://github.com/stlink-org/stlink/pull/1158), [#1159](https://github.com/stlink-org/stlink/pull/1159)) +- Added support for STM32WLEx ([#1173](https://github.com/stlink-org/stlink/pull/1173)) Updates & changes: +- [refactoring] Moved chip-specific parameters into separate files ([#237](https://github.com/stlink-org/stlink/pull/237), [#1129](https://github.com/stlink-org/stlink/pull/1129)) - Added instructions for bug-reports and feature-requests to contribution guidelines ([#906](https://github.com/stlink-org/stlink/pull/906)) - Added travis CI configuration for macOS 10.14 to maintain capability for 32-bit compilation ([#f5ada94](https://github.com/stlink-org/stlink/commit/f5ada9474cdb87ff37de0d4eb9e75622b5870646)) - Updated description of chip id 0x0457 to L01x/L02x ([#1143](https://github.com/stlink-org/stlink/pull/1143), [#1144](https://github.com/stlink-org/stlink/pull/1144)) +- Drop execute bits from source code files ([#1167](https://github.com/stlink-org/stlink/pull/1167)) +- Use proper Markdown headers for supported MCUs ([#1168](https://github.com/stlink-org/stlink/pull/1168)) +- Removed redundant array ([#1178](https://github.com/stlink-org/stlink/pull/1178)) Fixes: - cmake: Install shared libraries in proper directories ([#1142](https://github.com/stlink-org/stlink/pull/1142)) +- Fixed clearance of the H7 dual bank flag ([#1146](https://github.com/stlink-org/stlink/pull/1146), [#1147](https://github.com/stlink-org/stlink/pull/1147)) +- Fix for 'libusb_devices were leaked' when no ST-LINK programmer was found ([#1150](https://github.com/stlink-org/stlink/pull/1150)) +- Set of fixes and improvements ([#1154](https://github.com/stlink-org/stlink/pull/1154)) +- Removed limit check for WRITEMEM_32BIT ([#1157](https://github.com/stlink-org/stlink/pull/1157)) +- Fixed get_stm32l0_flash_base address for STM32L152RE ([#1161](https://github.com/stlink-org/stlink/pull/1161), [#1162](https://github.com/stlink-org/stlink/pull/1162)) +- Fixed segfault if chip was not found in chip config files ([#1138](https://github.com/stlink-org/stlink/pull/1138), [#1163](https://github.com/stlink-org/stlink/pull/1163), [#1165](https://github.com/stlink-org/stlink/pull/1165), [#1166](https://github.com/stlink-org/stlink/pull/1166), [#1170](https://github.com/stlink-org/stlink/pull/1170)) +- Fixed parsing hex numbers in chip config files ([#1169](https://github.com/stlink-org/stlink/pull/1169)) +- Corrected flash_pagesize to use hex format ([#1172](https://github.com/stlink-org/stlink/pull/1172)) +- Fixed compilation for MSVC ([#1176](https://github.com/stlink-org/stlink/pull/1176)) # v1.7.0 @@ -65,6 +81,7 @@ Fixes: - Improvements and fixes of the flash loaders, unification of the reset function ([#244](https://github.com/stlink-org/stlink/pull/244), [#382](https://github.com/stlink-org/stlink/pull/382), [#705](https://github.com/stlink-org/stlink/pull/705), [#724](https://github.com/stlink-org/stlink/pull/724), [#980](https://github.com/stlink-org/stlink/pull/980), [#995](https://github.com/stlink-org/stlink/pull/995), [#1008](https://github.com/stlink-org/stlink/pull/1008), [#1115](https://github.com/stlink-org/stlink/pull/1115), [#1117](https://github.com/stlink-org/stlink/pull/1117), [#1122](https://github.com/stlink-org/stlink/pull/1122), [#1124](https://github.com/stlink-org/stlink/pull/1124)) - Flash loader rework ([#356](https://github.com/stlink-org/stlink/pull/356), [#556](https://github.com/stlink-org/stlink/pull/556), [#593](https://github.com/stlink-org/stlink/pull/593), [#597](https://github.com/stlink-org/stlink/pull/597), [#607](https://github.com/stlink-org/stlink/pull/607), [#612](https://github.com/stlink-org/stlink/pull/612), [#638](https://github.com/stlink-org/stlink/pull/638), [#661](https://github.com/stlink-org/stlink/pull/661), [#690](https://github.com/stlink-org/stlink/pull/690), [#724](https://github.com/stlink-org/stlink/pull/724), [#807](https://github.com/stlink-org/stlink/pull/807), [#817](https://github.com/stlink-org/stlink/pull/817), [#818](https://github.com/stlink-org/stlink/pull/818), [#854](https://github.com/stlink-org/stlink/pull/854), [#868](https://github.com/stlink-org/stlink/pull/868), [#967](https://github.com/stlink-org/stlink/pull/967), [#979](https://github.com/stlink-org/stlink/pull/979), [#1008](https://github.com/stlink-org/stlink/pull/1008), [#1043](https://github.com/stlink-org/stlink/pull/1043), [#1054](https://github.com/stlink-org/stlink/pull/1054), [#1092](https://github.com/stlink-org/stlink/pull/1092), [#1105](https://github.com/stlink-org/stlink/pull/1105), [#1113](https://github.com/stlink-org/stlink/pull/1113)) - Fixed old DFU serial number for STLINK programmers ([#417](https://github.com/stlink-org/stlink/pull/417), [#494](https://github.com/stlink-org/stlink/pull/494), [#1106](https://github.com/stlink-org/stlink/pull/1106), [#1121](https://github.com/stlink-org/stlink/pull/1121)) +- Improvements for Chip_ID read ([#620](https://github.com/stlink-org/stlink/pull/620), [#1008](https://github.com/stlink-org/stlink/pull/1008), [#1120](https://github.com/stlink-org/stlink/pull/1120)) - Use vl flashloader for all STM32F1 series ([#724](https://github.com/stlink-org/stlink/pull/724), [#769](https://github.com/stlink-org/stlink/pull/769), [#1041](https://github.com/stlink-org/stlink/pull/1041), [#1044](https://github.com/stlink-org/stlink/pull/1044)) - [regression] Changed timeout on flash write ([#787](https://github.com/stlink-org/stlink/pull/787), [#981](https://github.com/stlink-org/stlink/pull/981), [#987](https://github.com/stlink-org/stlink/pull/987)) - cmake compile failure with external `CMAKE_MODULE_PATH` set ([#962](https://github.com/stlink-org/stlink/pull/962)) @@ -89,7 +106,6 @@ Fixes: - [doc] Corrected spelling mistake in bug report template ([#1103](https://github.com/stlink-org/stlink/pull/1103)) - Fixed STM32WB55 reading DEBUG IDCODE from the wrong address ([#1100](https://github.com/stlink-org/stlink/pull/1100), [#1101](https://github.com/stlink-org/stlink/pull/1101)) - Applied missing changes to tests ([#1119](https://github.com/stlink-org/stlink/pull/1119)) -- Improvements for Chip_ID read ([#1008](https://github.com/stlink-org/stlink/pull/1008), [#1120](https://github.com/stlink-org/stlink/pull/1120)) - Fixed reading of chip ID on Cortex-M0+ core ([#1017](https://github.com/stlink-org/stlink/pull/1017), [#1125](https://github.com/stlink-org/stlink/pull/1125), [#1126](https://github.com/stlink-org/stlink/pull/1126), [#1133](https://github.com/stlink-org/stlink/pull/1133)) # v1.6.1 diff --git a/contributors.txt b/contributors.txt index e7fc0f601..bcaa0b538 100644 --- a/contributors.txt +++ b/contributors.txt @@ -46,6 +46,7 @@ Georg von Zengen Giuseppe Barba Greg Alexander [galexander1] Greg Meiste [meisteg] +Grzegorz Szymaszek [gszy] Guillaume Revaillot [grevaillot] Hakkavélin Halt Hammerzeit From 30396b2803697617e2087c4f4b2a66187b58902c Mon Sep 17 00:00:00 2001 From: Luca Boccassi Date: Sun, 15 Aug 2021 14:31:09 +0100 Subject: [PATCH 311/503] Drop guipath.patch and refresh cross.patch for v1.7.0 --- debian/patches/cross.patch | 12 ++++++------ debian/patches/guipath.patch | 11 ----------- debian/patches/series | 1 - 3 files changed, 6 insertions(+), 18 deletions(-) delete mode 100644 debian/patches/guipath.patch diff --git a/debian/patches/cross.patch b/debian/patches/cross.patch index 8d927ba4b..d55e9f9d2 100644 --- a/debian/patches/cross.patch +++ b/debian/patches/cross.patch @@ -1,11 +1,11 @@ ---- stlink-1.6.1+ds.orig/CMakeLists.txt -+++ stlink-1.6.1+ds/CMakeLists.txt -@@ -48,7 +48,7 @@ - find_package(libusb REQUIRED) +--- a/src/stlink-gui/CMakeLists.txt ++++ b/src/stlink-gui/CMakeLists.txt +@@ -2,7 +2,7 @@ + # Build GUI + ### - ## Package configuration (pkg-config) on unix-based systems -if (NOT WIN32 AND NOT CMAKE_CROSSCOMPILING) +if (NOT WIN32) - #add_subdirectory(cmake/pkgconfig) find_package(PkgConfig) pkg_check_modules(GTK3 gtk+-3.0) + diff --git a/debian/patches/guipath.patch b/debian/patches/guipath.patch deleted file mode 100644 index d3effc92b..000000000 --- a/debian/patches/guipath.patch +++ /dev/null @@ -1,11 +0,0 @@ ---- a/src/stlink-gui/CMakeLists.txt -+++ b/src/stlink-gui/CMakeLists.txt -@@ -32,7 +32,7 @@ - add_executable(stlink-gui ${GUI_SOURCES}) - install(FILES stlink-gui.ui DESTINATION ${CMAKE_INSTALL_BINDIR}) - set_target_properties(stlink-gui PROPERTIES -- COMPILE_DEFINITIONS STLINK_UI_DIR="${CMAKE_INSTALL_PREFIX}/bin") -+ COMPILE_DEFINITIONS STLINK_UI_DIR="/usr/share/stlink") - target_link_libraries(stlink-gui ${STLINK_LIB_SHARED} ${SSP_LIB} ${GTK3_LDFLAGS}) - install(TARGETS stlink-gui DESTINATION ${CMAKE_INSTALL_BINDIR}) - diff --git a/debian/patches/series b/debian/patches/series index b3c28e7e1..def274a02 100644 --- a/debian/patches/series +++ b/debian/patches/series @@ -1,2 +1 @@ -guipath.patch cross.patch From 78b510ee3da0087033529956f5bc2d81359bc121 Mon Sep 17 00:00:00 2001 From: Luca Boccassi Date: Sun, 15 Aug 2021 14:38:00 +0100 Subject: [PATCH 312/503] Update install files, paths have been fixed upstream --- debian/stlink-gui.install | 6 +++--- debian/stlink-tools.manpages | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/debian/stlink-gui.install b/debian/stlink-gui.install index 5620a25e5..1474d7f8c 100644 --- a/debian/stlink-gui.install +++ b/debian/stlink-gui.install @@ -1,4 +1,4 @@ /usr/bin/stlink-gui -/usr/bin/stlink-gui.ui /usr/share/stlink/ -/usr/share/stlink/applications/stlink-gui.desktop /usr/share/applications/ -/usr/share/stlink/icons/hicolor/scalable/apps/stlink-gui.svg /usr/share/icons/hicolor/scalable/apps/stlink-gui.svg +/usr/share/applications/stlink-gui.desktop +/usr/share/icons/hicolor/scalable/apps/stlink-gui.svg +/usr/share/stlink/stlink-gui.ui diff --git a/debian/stlink-tools.manpages b/debian/stlink-tools.manpages index 049509abe..68112ddf2 100644 --- a/debian/stlink-tools.manpages +++ b/debian/stlink-tools.manpages @@ -1,3 +1,3 @@ -usr/share/stlink/man/man1/st-flash.1 -usr/share/stlink/man/man1/st-info.1 -usr/share/stlink/man/man1/st-util.1 +usr/share/man/man1/st-flash.1 +usr/share/man/man1/st-info.1 +usr/share/man/man1/st-util.1 From 9e3fac499e4a7c854f3cb691d29d10f7f8091eb5 Mon Sep 17 00:00:00 2001 From: Luca Boccassi Date: Sun, 15 Aug 2021 14:43:43 +0100 Subject: [PATCH 313/503] Update symbols file for 1.7.0 --- debian/libstlink1.symbols | 30 +++++++++++++++++++++++++++++- 1 file changed, 29 insertions(+), 1 deletion(-) diff --git a/debian/libstlink1.symbols b/debian/libstlink1.symbols index 159f27d0f..bc4e62f0e 100644 --- a/debian/libstlink1.symbols +++ b/debian/libstlink1.symbols @@ -29,6 +29,8 @@ libstlink.so.1 libstlink1 #MINVER# _stlink_usb_close@Base 1.5.0 _stlink_usb_core_id@Base 1.5.0 _stlink_usb_current_mode@Base 1.5.0 + _stlink_usb_disable_trace@Base 1.7.0 + _stlink_usb_enable_trace@Base 1.7.0 _stlink_usb_enter_swd_mode@Base 1.5.0 _stlink_usb_exit_debug_mode@Base 1.5.0 _stlink_usb_exit_dfu_mode@Base 1.5.0 @@ -40,6 +42,7 @@ libstlink.so.1 libstlink1 #MINVER# _stlink_usb_read_debug32@Base 1.5.0 _stlink_usb_read_mem32@Base 1.5.0 _stlink_usb_read_reg@Base 1.5.0 + _stlink_usb_read_trace@Base 1.7.0 _stlink_usb_read_unsupported_reg@Base 1.5.0 _stlink_usb_reset@Base 1.5.0 _stlink_usb_run@Base 1.5.0 @@ -54,10 +57,12 @@ libstlink.so.1 libstlink1 #MINVER# _stlink_usb_write_mem8@Base 1.5.0 _stlink_usb_write_reg@Base 1.5.0 _stlink_usb_write_unsupported_reg@Base 1.5.0 + arg_parse_freq@Base 1.7.0 calculate_F4_sectornum@Base 1.5.0 calculate_F7_sectornum@Base 1.5.0 + calculate_H7_sectornum@Base 1.7.0 calculate_L4_page@Base 1.5.0 - is_bigendian@Base 1.5.0 +#MISSING: 1.7.0# is_bigendian@Base 1.5.0 read_uint16@Base 1.5.0 read_uint32@Base 1.5.0 send_recv@Base 1.5.0 @@ -81,6 +86,9 @@ libstlink.so.1 libstlink1 #MINVER# stlink_flash_loader_init@Base 1.5.0 stlink_flash_loader_run@Base 1.5.0 stlink_flash_loader_write_to_sram@Base 1.5.0 + stlink_flashloader_start@Base 1.7.0 + stlink_flashloader_stop@Base 1.7.0 + stlink_flashloader_write@Base 1.7.0 stlink_force_debug@Base 1.5.0 stlink_fread@Base 1.5.0 stlink_fwrite_flash@Base 1.5.0 @@ -105,20 +113,36 @@ libstlink.so.1 libstlink1 #MINVER# stlink_read_mem32@Base 1.5.0 stlink_read_option_bytes32@Base 1.6.1 stlink_read_option_bytes_Gx@Base 1.6.1 + stlink_read_option_bytes_boot_add32@Base 1.7.0 + stlink_read_option_bytes_boot_add_f7@Base 1.7.0 stlink_read_option_bytes_f2@Base 1.6.0 stlink_read_option_bytes_f4@Base 1.6.0 + stlink_read_option_bytes_f7@Base 1.7.0 stlink_read_option_bytes_generic@Base 1.6.1 + stlink_read_option_control_register1_32@Base 1.7.0 + stlink_read_option_control_register1_f7@Base 1.7.0 + stlink_read_option_control_register32@Base 1.7.0 + stlink_read_option_control_register_Gx@Base 1.7.0 + stlink_read_option_control_register_f2@Base 1.7.0 + stlink_read_option_control_register_f4@Base 1.7.0 + stlink_read_option_control_register_f7@Base 1.7.0 stlink_read_reg@Base 1.5.0 stlink_read_unsupported_reg@Base 1.5.0 stlink_reset@Base 1.5.0 stlink_run@Base 1.5.0 stlink_run_at@Base 1.5.0 + stlink_serial@Base 1.7.0 stlink_set_hw_bp@Base 1.5.0 stlink_set_swdclk@Base 1.5.0 + stlink_soft_reset@Base 1.7.0 stlink_stat@Base 1.5.0 stlink_status@Base 1.5.0 stlink_step@Base 1.5.0 + stlink_target_connect@Base 1.7.0 stlink_target_voltage@Base 1.5.0 + stlink_trace_disable@Base 1.7.0 + stlink_trace_enable@Base 1.7.0 + stlink_trace_read@Base 1.7.0 stlink_v1_open@Base 1.5.0 stlink_v1_open_inner@Base 1.5.0 stlink_verify_write_flash@Base 1.5.0 @@ -130,9 +154,13 @@ libstlink.so.1 libstlink1 #MINVER# stlink_write_mem8@Base 1.5.0 stlink_write_option_bytes32@Base 1.6.1 stlink_write_option_bytes@Base 1.6.0 + stlink_write_option_bytes_boot_add32@Base 1.7.0 + stlink_write_option_control_register1_32@Base 1.7.0 + stlink_write_option_control_register32@Base 1.7.0 stlink_write_reg@Base 1.5.0 stlink_write_unsupported_reg@Base 1.5.0 stm32l1_write_half_pages@Base 1.5.0 + time_ms@Base 1.7.0 ugly_init@Base 1.5.0 ugly_libusb_log_level@Base 1.6.1 ugly_log@Base 1.5.0 From 4f40a424567e7f114753ac3ef56ba7e8b4d644a0 Mon Sep 17 00:00:00 2001 From: Luca Boccassi Date: Sun, 15 Aug 2021 14:24:44 +0100 Subject: [PATCH 314/503] Update changelog for 1.7.0+ds-1 --- debian/changelog | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/debian/changelog b/debian/changelog index ac046a5f4..7a7b4e54a 100644 --- a/debian/changelog +++ b/debian/changelog @@ -1,3 +1,13 @@ +stlink (1.7.0+ds-1) unstable; urgency=medium + + * Merge tag 'v1.7.0' into debian. (Closes: #984356) + * Bump Standards-Version to 4.5.1, no changes. + * Bump debhelper-compat to 13, no changes. + * Update install files, paths have been fixed upstream. + * Update symbols file for 1.7.0. + + -- Luca Boccassi Sun, 15 Aug 2021 14:23:25 +0100 + stlink (1.6.1+ds-3) unstable; urgency=medium * Add cross.patch to fix cross-compilation. Thanks Helmut! (Closes: From e662da00ca294c874655c65cffae3edde97343e5 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 22 Aug 2021 12:44:01 +0200 Subject: [PATCH 315/503] Updated debian pkg config for distribution --- debian/.gitignore | 4 +- debian/control | 36 +++-- debian/copyright | 128 +----------------- debian/patches/cross.patch | 11 -- debian/patches/series | 1 - ...ink-dev.install => stlink-lib-dev.install} | 0 ...{libstlink1.install => stlink-lib.install} | 0 ...{libstlink1.symbols => stlink-lib.symbols} | 2 +- debian/stlink.pc.in | 2 +- src/stlink-gui/CMakeLists.txt | 2 +- 10 files changed, 28 insertions(+), 158 deletions(-) delete mode 100644 debian/patches/cross.patch delete mode 100644 debian/patches/series rename debian/{libstlink-dev.install => stlink-lib-dev.install} (100%) rename debian/{libstlink1.install => stlink-lib.install} (100%) rename debian/{libstlink1.symbols => stlink-lib.symbols} (99%) diff --git a/debian/.gitignore b/debian/.gitignore index 7624d1c9b..6531851ff 100644 --- a/debian/.gitignore +++ b/debian/.gitignore @@ -1,8 +1,8 @@ .debhelper -files -debhelper-build-stamp *.log *.substvars +debhelper-build-stamp +files libstlink-dev libstlink stlink-gui diff --git a/debian/control b/debian/control index faed0302c..c3e654ec5 100644 --- a/debian/control +++ b/debian/control @@ -9,44 +9,40 @@ Homepage: https://github.com/stlink-org/stlink Vcs-Git: https://github.com/bluca/stlink.git -b debian Vcs-Browser: https://github.com/bluca/stlink -Package: libstlink-dev +Package: stlink-lib-dev Section: libdevel Architecture: linux-any Multi-Arch: same -Depends: libstlink1 (= ${binary:Version}), ${misc:Depends} -Description: OpenSource ST-Link tools replacement. - Flashing tools for STMicroelectronics STM32VL and STM32L. The transport layers - STLINKv1 and STLINKv2 are supported. +Depends: stlink-lib (= ${binary:Version}), ${misc:Depends} +Replaces: libstlink-dev (<< 1.7.0+ds-1) +Breaks: libstlink-dev (<< 1.7.0+ds-1) +Description: Open source version of the STMicroelectronics STLINK Tools . - This package contains the development files for stlink. + This package contains development files for stlink. -Package: libstlink1 +Package: stlink-lib Section: libs Architecture: linux-any Multi-Arch: same Depends: ${shlibs:Depends}, ${misc:Depends} -Description: OpenSource ST-Link tools replacement. - Flashing tools for STMicroelectronics STM32VL and STM32L. The transport layers - STLINKv1 and STLINKv2 are supported. +Replaces: libstlink1 (<< 1.7.0+ds-1) +Breaks: libstlink1 (<< 1.7.0+ds-1) +Description: Open source version of the STMicroelectronics STLINK Tools . This package contains the shared library for stlink. Package: stlink-tools Architecture: linux-any -Depends: libstlink1 (= ${binary:Version}), ${shlibs:Depends}, ${misc:Depends} -Description: OpenSource ST-Link tools replacement. - Flashing tools for STMicroelectronics STM32VL and STM32L. The transport layers - STLINKv1 and STLINKv2 are supported. +Depends: stlink-lib (= ${binary:Version}), ${shlibs:Depends}, ${misc:Depends} +Description: Open source version of the STMicroelectronics STLINK Tools . - This package contains commandline utilities for stlink, and modprobe and - udev rules. + This package contains commandline utilities for stlink, as well as modprobe + and udev rules. Package: stlink-gui Architecture: linux-any -Depends: libstlink1 (= ${binary:Version}), stlink-tools (= ${binary:Version}), +Depends: stlink-lib (= ${binary:Version}), stlink-tools (= ${binary:Version}), ${shlibs:Depends}, ${misc:Depends} -Description: OpenSource ST-Link tools replacement. - Flashing tools for STMicroelectronics STM32VL and STM32L. The transport layers - STLINKv1 and STLINKv2 are supported. +Description: Open source version of the STMicroelectronics STLINK Tools . This package contains a GUI tool for stlink. diff --git a/debian/copyright b/debian/copyright index 1a0febd9c..b7f9c3106 100644 --- a/debian/copyright +++ b/debian/copyright @@ -1,132 +1,18 @@ Format: https://www.debian.org/doc/packaging-manuals/copyright-format/1.0/ Upstream-Name: stlink -Upstream-Contact: Andrew 'Necromant' Andrianov +Upstream-Contact: Nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Source: https://github.com/stlink-org/stlink Comment: Upstream tarball has been repackaged to remove binary OSX kernel drivers that are of unknown license and of no use to Debian. Files-Excluded: stlinkv1_macos_driver Files: * -Copyright: 2011-2018 agpanarin - 2011-2018 Alexey Cherevatenko - 2011-2018 Anatoli - 2011-2018 Andrea Mucignat - 2011-2018 Andrew 'Necromant' Andrianov - 2011-2018 Andrey Yurovsky - 2011-2018 Andy Isaacson - 2011-2018 Áron RADICS - 2011-2018 A Sheaff - 2011-2018 Björn Hauffe - 2011-2018 bob - 2011-2018 Breton M. Saunders - 2011-2018 Bruno Dal Bo - 2011-2018 Burns - 2011-2018 Chris Dew - 2011-2018 Chris Hiszpanski - 2011-2018 Chris Li - 2011-2018 Chris Samuelson - 2011-2018 Christophe Levantis - 2011-2018 Craig Lilley - 2011-2018 dandev37 - 2011-2018 Dan Hepler - 2011-2018 Daniel Campoverde [alx741] - 2011-2018 Daniel O'Connor - 2011-2018 Dave Flogeras - 2011-2018 Dave Murphy - 2011-2018 Dave Vandervies - 2011-2018 Denis Fokin - 2011-2018 Denis Osterland - 2011-2018 Dmitry Bravikov - 2011-2018 Efe Can İçöz - 2011-2018 Ethan Zonca - 2011-2018 Fabien Chouteau - 2011-2018 Fabien Le Mentec - 2011-2018 fhars - 2011-2018 Friedrich Beckmann - 2011-2018 Geoffrey Brown - 2011-2018 George Talusan - 2011-2018 Georg von Zengen - 2011-2018 giuseppe barba - 2011-2018 Greg Alexander - 2011-2018 Greg Meiste - 2011-2018 Hakkavélin - 2011-2018 htk - 2011-2018 Ian Griffiths <6thimage@gmail.com> - 2011-2018 Jack Peel - 2011-2018 Jakub Tyszkowski - 2011-2018 Jan Sarenik - 2011-2018 Jean-Luc Béchennec - 2011-2018 Jean-Marie Lemetayer - 2011-2018 Jeff Kent - 2011-2018 Jeffrey Nelson - 2011-2018 Jens Hoffmann - 2011-2018 Jerome Lambourg - 2011-2018 Jerry Jacobs - 2011-2018 Jim Paris - 2011-2018 Jiří Netolický - 2011-2018 jnosky - 2011-2018 jnosky - 2011-2018 JohannesTaelman - 2011-2018 Jonas Danielsson - 2011-2018 Jonas Norling - 2011-2018 Josh Bialkowski - 2011-2018 Karl Palsson - 2011-2018 kevin - 2011-2018 Kyle Manna - 2011-2018 Lari Lehtomäki - 2011-2018 le mentec fabien - 2011-2018 Martin Nowak - 2011-2018 Matteo Collina - 2011-2018 Max Chen - 2011-2018 Maxime Coquelin - 2011-2018 Maxime Vincent - 2011-2018 Michael Pratt - 2011-2018 Michael Sparmann - 2011-2018 Mike Szczys - 2011-2018 mlundinse - 2011-2018 mux - 2011-2018 Ned Konz - 2011-2018 Nic McDonald - 2011-2018 Nicolas Schodet - 2011-2018 Nikolay - 2011-2018 nullsub - 2011-2018 Olivier Croquette - 2011-2018 Olivier Gay - 2011-2018 Onno Kortmann - 2011-2018 orangeudav - 2011-2018 Pavel Kirienko - 2011-2018 Pekka Nikander - 2011-2018 Pete - 2011-2018 Peter Zotov - 2011-2018 Petteri Aimonen - 2011-2018 Piotr Haber - 2011-2018 Rene Hopf - 2011-2018 Robin Kreis - 2011-2018 Rob Spanton - 2011-2018 Rytis Karpuska - 2011-2018 Sean Simmons - 2011-2018 Sergey Alirzaev - 2011-2018 Simon Wright - 2011-2018 Stany MARCEL - 2011-2018 Stefan Misik - 2011-2018 Sven Wegener - 2011-2018 Tectu - 2011-2018 tekaikko - 2011-2018 texane - 2011-2018 Theodore A. Roth - 2011-2018 Thomas Gärtner - 2011-2018 Tobias Badertscher - 2011-2018 Tom de Boer - 2011-2018 Tristan Gingold - 2011-2018 Uli Köhler - 2011-2018 Uwe Bonnes - 2011-2018 Vadim Kaushan - 2011-2018 Vegard Storheil Eriksen - 2011-2018 Viacheslav Dobromyslov - 2011-2018 Victor Mayoral Vilches - 2011-2018 Wojciech A. Koszek - 2011-2018 Woodrow Douglass - 2011-2018 The "Capt'ns Missing Link" Authors. +Copyright: 2011-2021 The stlink project maintainers + Martin Capitanio + Fabien Lementec + Jerry Jacobs + Nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> + and many other contributors... License: BSD-3-clause Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions diff --git a/debian/patches/cross.patch b/debian/patches/cross.patch deleted file mode 100644 index d55e9f9d2..000000000 --- a/debian/patches/cross.patch +++ /dev/null @@ -1,11 +0,0 @@ ---- a/src/stlink-gui/CMakeLists.txt -+++ b/src/stlink-gui/CMakeLists.txt -@@ -2,7 +2,7 @@ - # Build GUI - ### - --if (NOT WIN32 AND NOT CMAKE_CROSSCOMPILING) -+if (NOT WIN32) - find_package(PkgConfig) - pkg_check_modules(GTK3 gtk+-3.0) - diff --git a/debian/patches/series b/debian/patches/series deleted file mode 100644 index def274a02..000000000 --- a/debian/patches/series +++ /dev/null @@ -1 +0,0 @@ -cross.patch diff --git a/debian/libstlink-dev.install b/debian/stlink-lib-dev.install similarity index 100% rename from debian/libstlink-dev.install rename to debian/stlink-lib-dev.install diff --git a/debian/libstlink1.install b/debian/stlink-lib.install similarity index 100% rename from debian/libstlink1.install rename to debian/stlink-lib.install diff --git a/debian/libstlink1.symbols b/debian/stlink-lib.symbols similarity index 99% rename from debian/libstlink1.symbols rename to debian/stlink-lib.symbols index bc4e62f0e..9fb371d64 100644 --- a/debian/libstlink1.symbols +++ b/debian/stlink-lib.symbols @@ -1,4 +1,4 @@ -libstlink.so.1 libstlink1 #MINVER# +stlink-lib.so.1 stlink-lib #MINVER# Md5Calculate@Base 1.6.1 Md5Finalise@Base 1.6.1 Md5Initialise@Base 1.6.1 diff --git a/debian/stlink.pc.in b/debian/stlink.pc.in index 7fde2d968..b5f994bad 100644 --- a/debian/stlink.pc.in +++ b/debian/stlink.pc.in @@ -3,7 +3,7 @@ includedir=${prefix}/include/stlink libdir=${prefix}/lib/@DEB_HOST_MULTIARCH@ Name: stlink -Description: Open source version of the STMicroelectronics Stlink Tools +Description: Open source version of the STMicroelectronics STLINK Tools Version: @VERSION@ Requires: libusb-1.0 Libs: -L${libdir} -lstlink diff --git a/src/stlink-gui/CMakeLists.txt b/src/stlink-gui/CMakeLists.txt index 22a22f59d..80e3762c3 100644 --- a/src/stlink-gui/CMakeLists.txt +++ b/src/stlink-gui/CMakeLists.txt @@ -2,7 +2,7 @@ # Build GUI ### -if (NOT WIN32 AND NOT CMAKE_CROSSCOMPILING) +if (NOT WIN32) find_package(PkgConfig) pkg_check_modules(GTK3 gtk+-3.0) From c8fc6561fead79ad49c09d82bab864745086792c Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 29 Aug 2021 15:08:54 +0200 Subject: [PATCH 316/503] Bugfixes - Corrected paths for chip-id files (Closes #1180) - Fixed 32-bit build (Closes #985) (Closes #1175) - Patch for GitHub Actions Workflow (Ubuntu) --- .github/workflows/c-cpp.yml | 106 ++------------------------ .github/workflows/codeql-analysis.yml | 2 +- CMakeLists.txt | 13 ++-- src/common.c | 4 +- 4 files changed, 18 insertions(+), 107 deletions(-) diff --git a/.github/workflows/c-cpp.yml b/.github/workflows/c-cpp.yml index ee06d5469..442b3ba43 100644 --- a/.github/workflows/c-cpp.yml +++ b/.github/workflows/c-cpp.yml @@ -15,7 +15,7 @@ jobs: steps: - uses: actions/checkout@v2 - name: install dependencies - run: sudo apt-get install gcc-6 libusb-1.0.0-dev libgtk-3-dev rpm + run: sudo apt update && sudo apt-get install gcc-6 libusb-1.0.0-dev libgtk-3-dev rpm - name: make debug run: sudo make clean && make debug - name: make test @@ -35,7 +35,7 @@ jobs: steps: - uses: actions/checkout@v2 - name: install dependencies - run: sudo apt-get install gcc-6 libusb-1.0.0-dev libgtk-3-dev rpm + run: sudo apt update && sudo apt-get install gcc-6 libusb-1.0.0-dev libgtk-3-dev rpm - name: Set compiler flags run: | CFLAGS="$CFLAGS -m32" @@ -60,7 +60,7 @@ jobs: steps: - uses: actions/checkout@v2 - name: install dependencies - run: sudo apt-get install clang-10 libusb-1.0.0-dev libgtk-3-dev rpm + run: sudo apt update && sudo apt-get install clang-10 libusb-1.0.0-dev libgtk-3-dev rpm - name: make debug run: sudo make clean && make debug - name: make test @@ -80,7 +80,7 @@ jobs: steps: - uses: actions/checkout@v2 - name: Install dependencies - run: sudo apt-get install clang-10 libusb-1.0.0-dev libgtk-3-dev rpm + run: sudo apt update && sudo apt-get install clang-10 libusb-1.0.0-dev libgtk-3-dev rpm - name: Set compiler flags run: | CFLAGS="$CFLAGS -m32" @@ -105,7 +105,7 @@ jobs: steps: - uses: actions/checkout@v2 - name: Install dependencies - run: sudo apt-get install gcc-10 libusb-1.0.0-dev libgtk-3-dev rpm + run: sudo apt update && sudo apt-get install gcc-10 libusb-1.0.0-dev libgtk-3-dev rpm - name: make debug run: sudo make clean && make debug - name: make test @@ -125,7 +125,7 @@ jobs: steps: - uses: actions/checkout@v2 - name: Install dependencies - run: sudo apt-get install gcc-10 libusb-1.0.0-dev libgtk-3-dev rpm + run: sudo apt update && sudo apt-get install gcc-10 libusb-1.0.0-dev libgtk-3-dev rpm - name: Set compiler flags run: | CFLAGS="$CFLAGS -m32" @@ -150,7 +150,7 @@ jobs: steps: - uses: actions/checkout@v2 - name: Install dependencies - run: sudo apt-get install clang-10 libusb-1.0.0-dev libgtk-3-dev rpm + run: sudo apt update && sudo apt-get install clang-10 libusb-1.0.0-dev libgtk-3-dev rpm - name: make debug run: sudo make clean && make debug - name: make test @@ -170,7 +170,7 @@ jobs: steps: - uses: actions/checkout@v2 - name: Install dependencies - run: sudo apt-get install clang-10 libusb-1.0.0-dev libgtk-3-dev rpm + run: sudo apt update && sudo apt-get install clang-10 libusb-1.0.0-dev libgtk-3-dev rpm - name: Set compiler flags run: | CFLAGS="$CFLAGS -m32" @@ -191,96 +191,6 @@ jobs: # macOS - # job_macos_10_14_64_gcc: - # name: macos-10.14 gcc - # runs-on: macos-10.14 - # steps: - # - uses: actions/checkout@v2 - # - name: Install dependencies - # run: brew install gcc libusb gtk+3 - # - name: make debug - # run: sudo make clean && make debug - # - name: make test - # run: sudo make clean && make test - # - name: make release - # run: sudo make clean && make release - # - name: sudo make install - # run: sudo make clean && sudo make install - # - name: sudo make package - # run: sudo make package - # - name: sudo make uninstall - # run: sudo make uninstall && sudo make clean - - # job_macos_10_14_32_gcc: - # name: macos-10.14 gcc 32-bit - # runs-on: macos-10.14 - # steps: - # - uses: actions/checkout@v2 - # - name: Install dependencies - # run: brew install gcc libusb gtk+3 - # - name: Set compiler flags - # run: | - # CFLAGS="$CFLAGS -m32" - # CXXFLAGS="$CXXFLAGS -m32" - # LDFLAGS="$LDFLAGS -m32" - # - name: make debug - # run: sudo make clean && make debug - # - name: make test - # run: sudo make clean && make test - # - name: make release - # run: sudo make clean && make release - # - name: sudo make install - # run: sudo make clean && sudo make install - # - name: sudo make package - # run: sudo make package - # - name: sudo make uninstall - # run: sudo make uninstall && sudo make clean - - # job_macos_10_14_64_clang: - # name: macos-10.14 clang - # runs-on: macos-10.14 - # steps: - # - uses: actions/checkout@v2 - # - name: Install dependencies - # run: brew install llvm libusb gtk+3 - # - name: make debug - # run: sudo make clean && make debug - # - name: make test - # run: sudo make clean && make test - # - name: make release - # run: sudo make clean && make release - # - name: sudo make install - # run: sudo make clean && sudo make install - # - name: sudo make package - # run: sudo make package - # - name: sudo make uninstall - # run: sudo make uninstall && sudo make clean - - # job_macos_10_14_32_clang: - # name: macos-10.14 clang 32-bit - # runs-on: macos-10.14 - # steps: - # - uses: actions/checkout@v2 - # - name: Install dependencies - # run: brew install llvm libusb gtk+3 - # - name: Set compiler flags - # run: | - # CFLAGS="$CFLAGS -m32" - # CXXFLAGS="$CXXFLAGS -m32" - # LDFLAGS="$LDFLAGS -m32" - # - name: make debug - # run: sudo make clean && make debug - # - name: make test - # run: sudo make clean && make test - # - name: make release - # run: sudo make clean && make release - # - name: sudo make install - # run: sudo make clean && sudo make install - # - name: sudo make package - # run: sudo make package - # - name: sudo make uninstall - # run: sudo make uninstall && sudo make clean - job_macos_10_15_gcc: name: macos-10.15 gcc runs-on: macos-10.15 diff --git a/.github/workflows/codeql-analysis.yml b/.github/workflows/codeql-analysis.yml index 26313ecb5..55a21294f 100644 --- a/.github/workflows/codeql-analysis.yml +++ b/.github/workflows/codeql-analysis.yml @@ -35,7 +35,7 @@ jobs: steps: - name: Install dependencies - run: sudo apt-get install gcc-10 libusb-1.0.0-dev libgtk-3-dev rpm + run: sudo apt update && sudo apt-get install gcc-10 libusb-1.0.0-dev libgtk-3-dev rpm - name: Checkout repository uses: actions/checkout@v2 diff --git a/CMakeLists.txt b/CMakeLists.txt index 5c8aaa60c..fd17d47cc 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -9,11 +9,6 @@ set(CMAKE_ARCHIVE_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}/lib) set(CMAKE_LIBRARY_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}/lib) set(CMAKE_RUNTIME_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}/bin) -set(CMAKE_STLINK_ETC_DIR etc) -set(CMAKE_ETC_CHIPS_DIR ${CMAKE_STLINK_ETC_DIR}/stlink/chips) -set(CMAKE_ETC_CHIPS_DIR_ABS ${CMAKE_INSTALL_PREFIX}/${CMAKE_ETC_CHIPS_DIR}) -add_definitions( -DETC_STLINK_DIR="${CMAKE_ETC_CHIPS_DIR_ABS}" ) - ### # General project settings @@ -23,6 +18,11 @@ project(stlink C) set(PROJECT_DESCRIPTION "Open source version of the STMicroelectronics ST-LINK Tools") include(GNUInstallDirs) # Define GNU standard installation directories +## MCU configuration files +set(CMAKE_CHIPS_SUBDIR stlink/chips) +set(CMAKE_CHIPS_DIR ${CMAKE_INSTALL_PREFIX}/${CMAKE_CHIPS_SUBDIR}) +add_definitions( -DETC_STLINK_DIR="${CMAKE_CHIPS_DIR}" ) + ## Determine project version include(${CMAKE_MODULE_PATH}/get_version.cmake) @@ -287,8 +287,9 @@ install(TARGETS st-info DESTINATION ${CMAKE_INSTALL_BINDIR}) install(TARGETS st-util DESTINATION ${CMAKE_INSTALL_BINDIR}) install(TARGETS st-trace DESTINATION ${CMAKE_INSTALL_BINDIR}) +# Install MCU configuration files file(GLOB CHIP_FILES ${CMAKE_SOURCE_DIR}/config/chips/*.chip) -install(FILES ${CHIP_FILES} DESTINATION ${CMAKE_ETC_CHIPS_DIR}) +install(FILES ${CHIP_FILES} DESTINATION ${CMAKE_CHIPS_DIR}) ### diff --git a/src/common.c b/src/common.c index 601fac0b6..c40f6aa79 100644 --- a/src/common.c +++ b/src/common.c @@ -2199,7 +2199,7 @@ static int map_file(mapped_file_t *mf, const char *path) { if (sizeof(st.st_size) != sizeof(size_t)) { // on 32 bit systems, check if there is an overflow - if (st.st_size > (off_t)INT32_MAX) { + if (st.st_size > (off_t)SSIZE_MAX) { fprintf(stderr, "mmap() size_t overflow for file %s\n", path); goto on_error; } @@ -2213,7 +2213,7 @@ static int map_file(mapped_file_t *mf, const char *path) { goto on_error; } - mf->len = st.st_size; + mf->len = (size_t)st.st_size; error = 0; // success on_error: From e51309f8428c4f1eea3ef1840c4fd5116c64279c Mon Sep 17 00:00:00 2001 From: Grzegorz Szymaszek Date: Sat, 21 Aug 2021 16:43:26 +0200 Subject: [PATCH 317/503] Update chip config files from the library structs In general, the chip config files should be kept in sync with the old library structs. Regenerate the files (using an ad hoc script) from the current library. The file name is generated from the chip description, all non-alphanumeric characters are replaced with underscores. It turns out some files have to have their names changed. --- config/chips/{F0xx_small.chip => F03x.chip} | 8 ++++---- config/chips/F04x.chip | 4 ++-- config/chips/{F0xx.chip => F05x.chip} | 8 ++++---- config/chips/F07x.chip | 4 ++-- config/chips/F09x.chip | 4 ++-- ..._low-density.chip => F1_Low_density_device.chip} | 8 ++++---- config/chips/F1_value_line_high-density.chip | 13 ------------- .../{F1_connectivity_line.chip => F1xx_CL.chip} | 8 ++++---- ...{F1_high-density.chip => F1xx_High_density.chip} | 8 ++++---- config/chips/F1xx_High_density_value_line.chip | 13 +++++++++++++ ...medium-density.chip => F1xx_Medium_density.chip} | 8 ++++---- .../{F1_value_line.chip => F1xx_Value_Line.chip} | 8 ++++---- .../{F1_XL-density.chip => F1xx_XL_density.chip} | 4 ++-- config/chips/{F2.chip => F2xx.chip} | 4 ++-- .../chips/{F3xx_small.chip => F301_F302_F318.chip} | 8 ++++---- config/chips/F302_F303_F358.chip | 13 +++++++++++++ ...F334_medium_density.chip => F303_F328_F334.chip} | 8 ++++---- config/chips/F303_high_density.chip | 4 ++-- config/chips/F37x.chip | 4 ++-- config/chips/{F4xx_low_power.chip => F401xB_C.chip} | 4 ++-- .../{F4xx_dynamic_efficiency.chip => F401xD_E.chip} | 4 ++-- config/chips/{F411xx.chip => F411xC_E.chip} | 4 ++-- config/chips/{F413.chip => F413_F423.chip} | 4 ++-- config/chips/{F4xx.chip => F4x5_F4x7.chip} | 4 ++-- config/chips/{F7xx.chip => F74x_F75x.chip} | 4 ++-- config/chips/{F76xxx.chip => F76x_F77x.chip} | 6 +++--- .../chips/{G030_G031_G041.chip => G03x_G04x.chip} | 4 ++-- config/chips/G05x_G06x.chip | 13 +++++++++++++ .../chips/{G070_G071_G081.chip => G07x_G08x.chip} | 4 ++-- config/chips/G0Bx_G0Cx.chip | 13 +++++++++++++ config/chips/{G4_cat2.chip => G43x_G44x.chip} | 4 ++-- config/chips/{G4_cat3.chip => G47x_G48x.chip} | 6 +++--- config/chips/G49x_G4Ax.chip | 13 +++++++++++++ config/chips/{L011.chip => L01x_L02x.chip} | 4 ++-- config/chips/{L0xx_cat2.chip => L0xx_Cat_2.chip} | 4 ++-- config/chips/{L0x3.chip => L0xx_Cat_3.chip} | 4 ++-- config/chips/{L0xx_cat5.chip => L0xx_Cat_5.chip} | 6 +++--- .../{L1xx_medium-density.chip => L1xx_Cat_1.chip} | 4 ++-- config/chips/{L1xx_cat2.chip => L1xx_Cat_2.chip} | 4 ++-- ...1xx_medium-plus-density.chip => L1xx_Cat_3.chip} | 4 ++-- .../{L1xx_high-density.chip => L1xx_Cat_4.chip} | 4 ++-- config/chips/{L152RE.chip => L1xx_Cat_5.chip} | 4 ++-- config/chips/{L41x.chip => L41x_L42x.chip} | 4 ++-- config/chips/{L45x_L46x.chip => L45x_46x.chip} | 4 ++-- config/chips/{L4xx.chip => L47x_L48x.chip} | 4 ++-- config/chips/L4Px.chip | 13 +++++++++++++ config/chips/L4Rx.chip | 2 +- config/chips/{WB55.chip => WB5x_3x.chip} | 4 ++-- config/chips/{WLE.chip => WLEx.chip} | 4 ++-- 49 files changed, 182 insertions(+), 117 deletions(-) rename config/chips/{F0xx_small.chip => F03x.chip} (58%) rename config/chips/{F0xx.chip => F05x.chip} (60%) rename config/chips/{F1_low-density.chip => F1_Low_density_device.chip} (51%) delete mode 100644 config/chips/F1_value_line_high-density.chip rename config/chips/{F1_connectivity_line.chip => F1xx_CL.chip} (53%) rename config/chips/{F1_high-density.chip => F1xx_High_density.chip} (53%) create mode 100644 config/chips/F1xx_High_density_value_line.chip rename config/chips/{F1_medium-density.chip => F1xx_Medium_density.chip} (52%) rename config/chips/{F1_value_line.chip => F1xx_Value_Line.chip} (54%) rename config/chips/{F1_XL-density.chip => F1xx_XL_density.chip} (71%) rename config/chips/{F2.chip => F2xx.chip} (80%) rename config/chips/{F3xx_small.chip => F301_F302_F318.chip} (54%) create mode 100644 config/chips/F302_F303_F358.chip rename config/chips/{F334_medium_density.chip => F303_F328_F334.chip} (54%) rename config/chips/{F4xx_low_power.chip => F401xB_C.chip} (71%) rename config/chips/{F4xx_dynamic_efficiency.chip => F401xD_E.chip} (66%) rename config/chips/{F411xx.chip => F411xC_E.chip} (76%) rename config/chips/{F413.chip => F413_F423.chip} (75%) rename config/chips/{F4xx.chip => F4x5_F4x7.chip} (76%) rename config/chips/{F7xx.chip => F74x_F75x.chip} (75%) rename config/chips/{F76xxx.chip => F76x_F77x.chip} (68%) rename config/chips/{G030_G031_G041.chip => G03x_G04x.chip} (72%) create mode 100644 config/chips/G05x_G06x.chip rename config/chips/{G070_G071_G081.chip => G07x_G08x.chip} (72%) create mode 100644 config/chips/G0Bx_G0Cx.chip rename config/chips/{G4_cat2.chip => G43x_G44x.chip} (75%) rename config/chips/{G4_cat3.chip => G47x_G48x.chip} (68%) create mode 100644 config/chips/G49x_G4Ax.chip rename config/chips/{L011.chip => L01x_L02x.chip} (75%) rename config/chips/{L0xx_cat2.chip => L0xx_Cat_2.chip} (75%) rename config/chips/{L0x3.chip => L0xx_Cat_3.chip} (75%) rename config/chips/{L0xx_cat5.chip => L0xx_Cat_5.chip} (68%) rename config/chips/{L1xx_medium-density.chip => L1xx_Cat_1.chip} (68%) rename config/chips/{L1xx_cat2.chip => L1xx_Cat_2.chip} (74%) rename config/chips/{L1xx_medium-plus-density.chip => L1xx_Cat_3.chip} (65%) rename config/chips/{L1xx_high-density.chip => L1xx_Cat_4.chip} (70%) rename config/chips/{L152RE.chip => L1xx_Cat_5.chip} (74%) rename config/chips/{L41x.chip => L41x_L42x.chip} (75%) rename config/chips/{L45x_L46x.chip => L45x_46x.chip} (75%) rename config/chips/{L4xx.chip => L47x_L48x.chip} (76%) create mode 100644 config/chips/L4Px.chip rename config/chips/{WB55.chip => WB5x_3x.chip} (76%) rename config/chips/{WLE.chip => WLEx.chip} (79%) diff --git a/config/chips/F0xx_small.chip b/config/chips/F03x.chip similarity index 58% rename from config/chips/F0xx_small.chip rename to config/chips/F03x.chip index 0a8ec265e..eed78e4e2 100644 --- a/config/chips/F0xx_small.chip +++ b/config/chips/F03x.chip @@ -1,13 +1,13 @@ -# Chip-ID file for F0xx small +# Chip-ID file for F03x # chip_id 0x444 -description F0xx small +description F03x flash_type 1 flash_pagesize 0x400 sram_size 0x1000 bootrom_base 0x1fffec00 bootrom_size 0xc00 -option_base 0x0 -option_size 0x0 +option_base 0x1ffff800 +option_size 0x10 flags none diff --git a/config/chips/F04x.chip b/config/chips/F04x.chip index 033c034e2..1f2a2043e 100644 --- a/config/chips/F04x.chip +++ b/config/chips/F04x.chip @@ -7,7 +7,7 @@ flash_pagesize 0x400 sram_size 0x1800 bootrom_base 0x1fffec00 bootrom_size 0xc00 -option_base 0x0 -option_size 0x0 +option_base 0x1ffff800 +option_size 0x10 flags none diff --git a/config/chips/F0xx.chip b/config/chips/F05x.chip similarity index 60% rename from config/chips/F0xx.chip rename to config/chips/F05x.chip index 309bbee34..787adb6bf 100644 --- a/config/chips/F0xx.chip +++ b/config/chips/F05x.chip @@ -1,13 +1,13 @@ -# Chip-ID file for F0xx +# Chip-ID file for F05x # chip_id 0x440 -description F0xx +description F05x flash_type 1 flash_pagesize 0x400 sram_size 0x2000 bootrom_base 0x1fffec00 bootrom_size 0xc00 -option_base 0x0 -option_size 0x0 +option_base 0x1ffff800 +option_size 0x10 flags none diff --git a/config/chips/F07x.chip b/config/chips/F07x.chip index dd697af40..e893a5457 100644 --- a/config/chips/F07x.chip +++ b/config/chips/F07x.chip @@ -7,7 +7,7 @@ flash_pagesize 0x800 sram_size 0x4000 bootrom_base 0x1fffc800 bootrom_size 0x3000 -option_base 0x0 -option_size 0x0 +option_base 0x1ffff800 +option_size 0x10 flags none diff --git a/config/chips/F09x.chip b/config/chips/F09x.chip index adb000030..267a2612f 100644 --- a/config/chips/F09x.chip +++ b/config/chips/F09x.chip @@ -7,7 +7,7 @@ flash_pagesize 0x800 sram_size 0x8000 bootrom_base 0x1fffd800 bootrom_size 0x2000 -option_base 0x0 -option_size 0x0 +option_base 0x1ffff800 +option_size 0x10 flags none diff --git a/config/chips/F1_low-density.chip b/config/chips/F1_Low_density_device.chip similarity index 51% rename from config/chips/F1_low-density.chip rename to config/chips/F1_Low_density_device.chip index 3995cad96..33fa03e1b 100644 --- a/config/chips/F1_low-density.chip +++ b/config/chips/F1_Low_density_device.chip @@ -1,13 +1,13 @@ -# Chip-ID file for F1 low-density +# Chip-ID file for F1 Low-density device # chip_id 0x412 -description F1 low-density +description F1 Low-density device flash_type 1 flash_pagesize 0x400 sram_size 0x2800 bootrom_base 0x1ffff000 bootrom_size 0x800 -option_base 0x0 -option_size 0x0 +option_base 0x1ffff800 +option_size 0x10 flags swo diff --git a/config/chips/F1_value_line_high-density.chip b/config/chips/F1_value_line_high-density.chip deleted file mode 100644 index 6a49c2699..000000000 --- a/config/chips/F1_value_line_high-density.chip +++ /dev/null @@ -1,13 +0,0 @@ -# Chip-ID file for F1 value line high-density -# -chip_id 0x428 -description F1 value line high-density -flash_type 1 -flash_pagesize 0x800 -sram_size 0x8000 -bootrom_base 0x1ffff000 -bootrom_size 0x800 -option_base 0x0 -option_size 0x0 -flags swo - diff --git a/config/chips/F1_connectivity_line.chip b/config/chips/F1xx_CL.chip similarity index 53% rename from config/chips/F1_connectivity_line.chip rename to config/chips/F1xx_CL.chip index b6fd9c93a..c2a3b2e69 100644 --- a/config/chips/F1_connectivity_line.chip +++ b/config/chips/F1xx_CL.chip @@ -1,13 +1,13 @@ -# Chip-ID file for F1 connectivity line +# Chip-ID file for F1xx CL # chip_id 0x418 -description F1 connectivity line +description F1xx CL flash_type 1 flash_pagesize 0x800 sram_size 0x10000 bootrom_base 0x1fffb000 bootrom_size 0x4800 -option_base 0x0 -option_size 0x0 +option_base 0x1ffff800 +option_size 0x10 flags swo diff --git a/config/chips/F1_high-density.chip b/config/chips/F1xx_High_density.chip similarity index 53% rename from config/chips/F1_high-density.chip rename to config/chips/F1xx_High_density.chip index f88413fc8..1deb5f01b 100644 --- a/config/chips/F1_high-density.chip +++ b/config/chips/F1xx_High_density.chip @@ -1,13 +1,13 @@ -# Chip-ID file for F1 high-density +# Chip-ID file for F1xx High-density # chip_id 0x414 -description F1 high-density +description F1xx High-density flash_type 1 flash_pagesize 0x800 sram_size 0x10000 bootrom_base 0x1ffff000 bootrom_size 0x800 -option_base 0x0 -option_size 0x0 +option_base 0x1ffff800 +option_size 0x10 flags swo diff --git a/config/chips/F1xx_High_density_value_line.chip b/config/chips/F1xx_High_density_value_line.chip new file mode 100644 index 000000000..9e467c9d7 --- /dev/null +++ b/config/chips/F1xx_High_density_value_line.chip @@ -0,0 +1,13 @@ +# Chip-ID file for F1xx High-density value line +# +chip_id 0x428 +description F1xx High-density value line +flash_type 1 +flash_pagesize 0x800 +sram_size 0x8000 +bootrom_base 0x1ffff000 +bootrom_size 0x800 +option_base 0x1ffff800 +option_size 0x10 +flags swo + diff --git a/config/chips/F1_medium-density.chip b/config/chips/F1xx_Medium_density.chip similarity index 52% rename from config/chips/F1_medium-density.chip rename to config/chips/F1xx_Medium_density.chip index 25cbec2dc..a6d81d6f6 100644 --- a/config/chips/F1_medium-density.chip +++ b/config/chips/F1xx_Medium_density.chip @@ -1,13 +1,13 @@ -# Chip-ID file for F1 medium-density +# Chip-ID file for F1xx Medium-density # chip_id 0x410 -description F1 medium-density +description F1xx Medium-density flash_type 1 flash_pagesize 0x400 sram_size 0x5000 bootrom_base 0x1ffff000 bootrom_size 0x800 -option_base 0x0 -option_size 0x0 +option_base 0x1ffff800 +option_size 0x10 flags swo diff --git a/config/chips/F1_value_line.chip b/config/chips/F1xx_Value_Line.chip similarity index 54% rename from config/chips/F1_value_line.chip rename to config/chips/F1xx_Value_Line.chip index 5515d9acd..463cc2d9c 100644 --- a/config/chips/F1_value_line.chip +++ b/config/chips/F1xx_Value_Line.chip @@ -1,13 +1,13 @@ -# Chip-ID file for F1 value line +# Chip-ID file for F1xx Value Line # chip_id 0x420 -description F1 value line +description F1xx Value Line flash_type 1 flash_pagesize 0x400 sram_size 0x2000 bootrom_base 0x1ffff000 bootrom_size 0x800 -option_base 0x0 -option_size 0x0 +option_base 0x1ffff800 +option_size 0x10 flags swo diff --git a/config/chips/F1_XL-density.chip b/config/chips/F1xx_XL_density.chip similarity index 71% rename from config/chips/F1_XL-density.chip rename to config/chips/F1xx_XL_density.chip index 3b3c95ab0..318efbff0 100644 --- a/config/chips/F1_XL-density.chip +++ b/config/chips/F1xx_XL_density.chip @@ -1,7 +1,7 @@ -# Chip-ID file for F1 XL-density +# Chip-ID file for F1xx XL-density # chip_id 0x430 -description F1 XL-density +description F1xx XL-density flash_type 2 flash_pagesize 0x800 sram_size 0x18000 diff --git a/config/chips/F2.chip b/config/chips/F2xx.chip similarity index 80% rename from config/chips/F2.chip rename to config/chips/F2xx.chip index 31a4d34a8..30808f1aa 100644 --- a/config/chips/F2.chip +++ b/config/chips/F2xx.chip @@ -1,7 +1,7 @@ -# Chip-ID file for F2 +# Chip-ID file for F2xx # chip_id 0x411 -description F2 +description F2xx flash_type 3 flash_pagesize 0x20000 sram_size 0x20000 diff --git a/config/chips/F3xx_small.chip b/config/chips/F301_F302_F318.chip similarity index 54% rename from config/chips/F3xx_small.chip rename to config/chips/F301_F302_F318.chip index 31fd136a8..429c836b4 100644 --- a/config/chips/F3xx_small.chip +++ b/config/chips/F301_F302_F318.chip @@ -1,13 +1,13 @@ -# Chip-ID file for F3xx small +# Chip-ID file for F301/F302/F318 # chip_id 0x439 -description F3xx small +description F301/F302/F318 flash_type 1 flash_pagesize 0x800 sram_size 0xa000 bootrom_base 0x1fffd800 bootrom_size 0x2000 -option_base 0x0 -option_size 0x0 +option_base 0x1ffff800 +option_size 0x10 flags swo diff --git a/config/chips/F302_F303_F358.chip b/config/chips/F302_F303_F358.chip new file mode 100644 index 000000000..ffd1491ff --- /dev/null +++ b/config/chips/F302_F303_F358.chip @@ -0,0 +1,13 @@ +# Chip-ID file for F302/F303/F358 +# +chip_id 0x422 +description F302/F303/F358 +flash_type 1 +flash_pagesize 0x800 +sram_size 0xa000 +bootrom_base 0x1ffff000 +bootrom_size 0x800 +option_base 0x1ffff800 +option_size 0x10 +flags swo + diff --git a/config/chips/F334_medium_density.chip b/config/chips/F303_F328_F334.chip similarity index 54% rename from config/chips/F334_medium_density.chip rename to config/chips/F303_F328_F334.chip index 365931a01..5df2a9bbb 100644 --- a/config/chips/F334_medium_density.chip +++ b/config/chips/F303_F328_F334.chip @@ -1,13 +1,13 @@ -# Chip-ID file for F334 medium density +# Chip-ID file for F303/F328/F334 # chip_id 0x438 -description F334 medium density +description F303/F328/F334 flash_type 1 flash_pagesize 0x800 sram_size 0x3000 bootrom_base 0x1fffd800 bootrom_size 0x2000 -option_base 0x0 -option_size 0x0 +option_base 0x1ffff800 +option_size 0x10 flags swo diff --git a/config/chips/F303_high_density.chip b/config/chips/F303_high_density.chip index afbdf63b5..748c27cbc 100644 --- a/config/chips/F303_high_density.chip +++ b/config/chips/F303_high_density.chip @@ -7,7 +7,7 @@ flash_pagesize 0x800 sram_size 0x10000 bootrom_base 0x1fffd800 bootrom_size 0x2000 -option_base 0x0 -option_size 0x0 +option_base 0x1ffff800 +option_size 0x10 flags swo diff --git a/config/chips/F37x.chip b/config/chips/F37x.chip index 5d5723b14..92201657d 100644 --- a/config/chips/F37x.chip +++ b/config/chips/F37x.chip @@ -7,7 +7,7 @@ flash_pagesize 0x800 sram_size 0xa000 bootrom_base 0x1ffff000 bootrom_size 0x800 -option_base 0x0 -option_size 0x0 +option_base 0x1ffff800 +option_size 0x10 flags swo diff --git a/config/chips/F4xx_low_power.chip b/config/chips/F401xB_C.chip similarity index 71% rename from config/chips/F4xx_low_power.chip rename to config/chips/F401xB_C.chip index 7c1cc1243..09e998dba 100644 --- a/config/chips/F4xx_low_power.chip +++ b/config/chips/F401xB_C.chip @@ -1,7 +1,7 @@ -# Chip-ID file for F4xx low power +# Chip-ID file for F401xB/C # chip_id 0x423 -description F4xx low power +description F401xB/C flash_type 3 flash_pagesize 0x4000 sram_size 0x10000 diff --git a/config/chips/F4xx_dynamic_efficiency.chip b/config/chips/F401xD_E.chip similarity index 66% rename from config/chips/F4xx_dynamic_efficiency.chip rename to config/chips/F401xD_E.chip index 02a886c26..5b70d7d86 100644 --- a/config/chips/F4xx_dynamic_efficiency.chip +++ b/config/chips/F401xD_E.chip @@ -1,7 +1,7 @@ -# Chip-ID file for F4xx dynamic efficiency +# Chip-ID file for F401xD/E # chip_id 0x433 -description F4xx dynamic efficiency +description F401xD/E flash_type 3 flash_pagesize 0x4000 sram_size 0x18000 diff --git a/config/chips/F411xx.chip b/config/chips/F411xC_E.chip similarity index 76% rename from config/chips/F411xx.chip rename to config/chips/F411xC_E.chip index e41288de7..d344489c5 100644 --- a/config/chips/F411xx.chip +++ b/config/chips/F411xC_E.chip @@ -1,7 +1,7 @@ -# Chip-ID file for F411xx +# Chip-ID file for F411xC/E # chip_id 0x431 -description F411xx +description F411xC/E flash_type 3 flash_pagesize 0x4000 sram_size 0x20000 diff --git a/config/chips/F413.chip b/config/chips/F413_F423.chip similarity index 75% rename from config/chips/F413.chip rename to config/chips/F413_F423.chip index 94813647f..647775eeb 100644 --- a/config/chips/F413.chip +++ b/config/chips/F413_F423.chip @@ -1,7 +1,7 @@ -# Chip-ID file for F413 +# Chip-ID file for F413/F423 # chip_id 0x463 -description F413 +description F413/F423 flash_type 3 flash_pagesize 0x4000 sram_size 0x50000 diff --git a/config/chips/F4xx.chip b/config/chips/F4x5_F4x7.chip similarity index 76% rename from config/chips/F4xx.chip rename to config/chips/F4x5_F4x7.chip index 1c6d087a5..b19e4a5b3 100644 --- a/config/chips/F4xx.chip +++ b/config/chips/F4x5_F4x7.chip @@ -1,7 +1,7 @@ -# Chip-ID file for F4xx +# Chip-ID file for F4x5/F4x7 # chip_id 0x413 -description F4xx +description F4x5/F4x7 flash_type 3 flash_pagesize 0x4000 sram_size 0x30000 diff --git a/config/chips/F7xx.chip b/config/chips/F74x_F75x.chip similarity index 75% rename from config/chips/F7xx.chip rename to config/chips/F74x_F75x.chip index b6e3774f7..0604b299d 100644 --- a/config/chips/F7xx.chip +++ b/config/chips/F74x_F75x.chip @@ -1,7 +1,7 @@ -# Chip-ID file for F7xx +# Chip-ID file for F74x/F75x # chip_id 0x449 -description F7xx +description F74x/F75x flash_type 3 flash_pagesize 0x800 sram_size 0x50000 diff --git a/config/chips/F76xxx.chip b/config/chips/F76x_F77x.chip similarity index 68% rename from config/chips/F76xxx.chip rename to config/chips/F76x_F77x.chip index ef17fc557..304c99191 100644 --- a/config/chips/F76xxx.chip +++ b/config/chips/F76x_F77x.chip @@ -1,7 +1,7 @@ -# Chip-ID file for F76xxx +# Chip-ID file for F76x/F77x # chip_id 0x451 -description F76xxx +description F76x/F77x flash_type 4 flash_pagesize 0x800 sram_size 0x80000 @@ -9,5 +9,5 @@ bootrom_base 0x200000 bootrom_size 0xedc0 option_base 0x1fff0000 option_size 0x20 -flags swo +flags dualbank swo diff --git a/config/chips/G030_G031_G041.chip b/config/chips/G03x_G04x.chip similarity index 72% rename from config/chips/G030_G031_G041.chip rename to config/chips/G03x_G04x.chip index 16a9a79ff..7c5a00c58 100644 --- a/config/chips/G030_G031_G041.chip +++ b/config/chips/G03x_G04x.chip @@ -1,7 +1,7 @@ -# Chip-ID file for G030/G031/G041 +# Chip-ID file for G03x/G04x # chip_id 0x466 -description G030/G031/G041 +description G03x/G04x flash_type 7 flash_pagesize 0x800 sram_size 0x2000 diff --git a/config/chips/G05x_G06x.chip b/config/chips/G05x_G06x.chip new file mode 100644 index 000000000..45295ec6e --- /dev/null +++ b/config/chips/G05x_G06x.chip @@ -0,0 +1,13 @@ +# Chip-ID file for G05x/G06x +# +chip_id 0x456 +description G05x/G06x +flash_type 7 +flash_pagesize 0x800 +sram_size 0x9000 +bootrom_base 0x1fff0000 +bootrom_size 0x7000 +option_base 0x1fff7800 +option_size 0x4 +flags none + diff --git a/config/chips/G070_G071_G081.chip b/config/chips/G07x_G08x.chip similarity index 72% rename from config/chips/G070_G071_G081.chip rename to config/chips/G07x_G08x.chip index 7fb81eb1f..7bddcd82c 100644 --- a/config/chips/G070_G071_G081.chip +++ b/config/chips/G07x_G08x.chip @@ -1,7 +1,7 @@ -# Chip-ID file for G070/G071/G081 +# Chip-ID file for G07x/G08x # chip_id 0x460 -description G070/G071/G081 +description G07x/G08x flash_type 7 flash_pagesize 0x800 sram_size 0x9000 diff --git a/config/chips/G0Bx_G0Cx.chip b/config/chips/G0Bx_G0Cx.chip new file mode 100644 index 000000000..98e503569 --- /dev/null +++ b/config/chips/G0Bx_G0Cx.chip @@ -0,0 +1,13 @@ +# Chip-ID file for G0Bx/G0Cx +# +chip_id 0x467 +description G0Bx/G0Cx +flash_type 7 +flash_pagesize 0x800 +sram_size 0x9000 +bootrom_base 0x1fff0000 +bootrom_size 0x7000 +option_base 0x1fff7800 +option_size 0x4 +flags dualbank + diff --git a/config/chips/G4_cat2.chip b/config/chips/G43x_G44x.chip similarity index 75% rename from config/chips/G4_cat2.chip rename to config/chips/G43x_G44x.chip index ea144114d..033f1dd80 100644 --- a/config/chips/G4_cat2.chip +++ b/config/chips/G43x_G44x.chip @@ -1,7 +1,7 @@ -# Chip-ID file for G4 cat2 +# Chip-ID file for G43x/G44x # chip_id 0x468 -description G4 cat2 +description G43x/G44x flash_type 8 flash_pagesize 0x800 sram_size 0x8000 diff --git a/config/chips/G4_cat3.chip b/config/chips/G47x_G48x.chip similarity index 68% rename from config/chips/G4_cat3.chip rename to config/chips/G47x_G48x.chip index 7e34e001c..fa331650f 100644 --- a/config/chips/G4_cat3.chip +++ b/config/chips/G47x_G48x.chip @@ -1,10 +1,10 @@ -# Chip-ID file for G4 cat3 +# Chip-ID file for G47x/G48x # chip_id 0x469 -description G4 cat3 +description G47x/G48x flash_type 8 flash_pagesize 0x800 -sram_size 0x18000 +sram_size 0x20000 bootrom_base 0x1fff0000 bootrom_size 0x7000 option_base 0x1ffff800 diff --git a/config/chips/G49x_G4Ax.chip b/config/chips/G49x_G4Ax.chip new file mode 100644 index 000000000..b764572db --- /dev/null +++ b/config/chips/G49x_G4Ax.chip @@ -0,0 +1,13 @@ +# Chip-ID file for G49x/G4Ax +# +chip_id 0x479 +description G49x/G4Ax +flash_type 8 +flash_pagesize 0x800 +sram_size 0x1c000 +bootrom_base 0x1fff0000 +bootrom_size 0x7000 +option_base 0x1ffff800 +option_size 0x4 +flags swo + diff --git a/config/chips/L011.chip b/config/chips/L01x_L02x.chip similarity index 75% rename from config/chips/L011.chip rename to config/chips/L01x_L02x.chip index 719185558..c3d2074b9 100644 --- a/config/chips/L011.chip +++ b/config/chips/L01x_L02x.chip @@ -1,7 +1,7 @@ -# Chip-ID file for L011 +# Chip-ID file for L01x/L02x # chip_id 0x457 -description L011 +description L01x/L02x flash_type 5 flash_pagesize 0x80 sram_size 0x2000 diff --git a/config/chips/L0xx_cat2.chip b/config/chips/L0xx_Cat_2.chip similarity index 75% rename from config/chips/L0xx_cat2.chip rename to config/chips/L0xx_Cat_2.chip index cdcff81cc..47183b8ef 100644 --- a/config/chips/L0xx_cat2.chip +++ b/config/chips/L0xx_Cat_2.chip @@ -1,7 +1,7 @@ -# Chip-ID file for L0xx cat2 +# Chip-ID file for L0xx Cat.2 # chip_id 0x425 -description L0xx cat2 +description L0xx Cat.2 flash_type 5 flash_pagesize 0x80 sram_size 0x2000 diff --git a/config/chips/L0x3.chip b/config/chips/L0xx_Cat_3.chip similarity index 75% rename from config/chips/L0x3.chip rename to config/chips/L0xx_Cat_3.chip index cbdc6cace..6d9fcc105 100644 --- a/config/chips/L0x3.chip +++ b/config/chips/L0xx_Cat_3.chip @@ -1,7 +1,7 @@ -# Chip-ID file for L0x3 +# Chip-ID file for L0xx Cat.3 # chip_id 0x417 -description L0x3 +description L0xx Cat.3 flash_type 5 flash_pagesize 0x80 sram_size 0x2000 diff --git a/config/chips/L0xx_cat5.chip b/config/chips/L0xx_Cat_5.chip similarity index 68% rename from config/chips/L0xx_cat5.chip rename to config/chips/L0xx_Cat_5.chip index 2c755a0d8..545c1c2ef 100644 --- a/config/chips/L0xx_cat5.chip +++ b/config/chips/L0xx_Cat_5.chip @@ -1,7 +1,7 @@ -# Chip-ID file for L0xx cat5 +# Chip-ID file for L0xx Cat.5 # chip_id 0x447 -description L0xx cat5 +description L0xx Cat.5 flash_type 5 flash_pagesize 0x80 sram_size 0x5000 @@ -9,5 +9,5 @@ bootrom_base 0x1ff0000 bootrom_size 0x2000 option_base 0x1ff80000 option_size 0x14 -flags none +flags dualbank diff --git a/config/chips/L1xx_medium-density.chip b/config/chips/L1xx_Cat_1.chip similarity index 68% rename from config/chips/L1xx_medium-density.chip rename to config/chips/L1xx_Cat_1.chip index f77c19cac..6c8b211c4 100644 --- a/config/chips/L1xx_medium-density.chip +++ b/config/chips/L1xx_Cat_1.chip @@ -1,7 +1,7 @@ -# Chip-ID file for L1xx medium-density +# Chip-ID file for L1xx Cat.1 # chip_id 0x416 -description L1xx medium-density +description L1xx Cat.1 flash_type 5 flash_pagesize 0x100 sram_size 0x4000 diff --git a/config/chips/L1xx_cat2.chip b/config/chips/L1xx_Cat_2.chip similarity index 74% rename from config/chips/L1xx_cat2.chip rename to config/chips/L1xx_Cat_2.chip index 7f949923e..1ff71edef 100644 --- a/config/chips/L1xx_cat2.chip +++ b/config/chips/L1xx_Cat_2.chip @@ -1,7 +1,7 @@ -# Chip-ID file for L1xx cat2 +# Chip-ID file for L1xx Cat.2 # chip_id 0x429 -description L1xx cat2 +description L1xx Cat.2 flash_type 5 flash_pagesize 0x100 sram_size 0x8000 diff --git a/config/chips/L1xx_medium-plus-density.chip b/config/chips/L1xx_Cat_3.chip similarity index 65% rename from config/chips/L1xx_medium-plus-density.chip rename to config/chips/L1xx_Cat_3.chip index da557e3c8..f417e07f9 100644 --- a/config/chips/L1xx_medium-plus-density.chip +++ b/config/chips/L1xx_Cat_3.chip @@ -1,7 +1,7 @@ -# Chip-ID file for L1xx medium-plus-density +# Chip-ID file for L1xx Cat.3 # chip_id 0x427 -description L1xx medium-plus-density +description L1xx Cat.3 flash_type 5 flash_pagesize 0x100 sram_size 0x8000 diff --git a/config/chips/L1xx_high-density.chip b/config/chips/L1xx_Cat_4.chip similarity index 70% rename from config/chips/L1xx_high-density.chip rename to config/chips/L1xx_Cat_4.chip index 409c04062..dbf7869ad 100644 --- a/config/chips/L1xx_high-density.chip +++ b/config/chips/L1xx_Cat_4.chip @@ -1,7 +1,7 @@ -# Chip-ID file for L1xx high-density +# Chip-ID file for L1xx Cat.4 # chip_id 0x436 -description L1xx high-density +description L1xx Cat.4 flash_type 5 flash_pagesize 0x100 sram_size 0xc000 diff --git a/config/chips/L152RE.chip b/config/chips/L1xx_Cat_5.chip similarity index 74% rename from config/chips/L152RE.chip rename to config/chips/L1xx_Cat_5.chip index 4d9658ee9..12342d14f 100644 --- a/config/chips/L152RE.chip +++ b/config/chips/L1xx_Cat_5.chip @@ -1,7 +1,7 @@ -# Chip-ID file for L152RE +# Chip-ID file for L1xx Cat.5 # chip_id 0x437 -description L152RE +description L1xx Cat.5 flash_type 5 flash_pagesize 0x100 sram_size 0x14000 diff --git a/config/chips/L41x.chip b/config/chips/L41x_L42x.chip similarity index 75% rename from config/chips/L41x.chip rename to config/chips/L41x_L42x.chip index 5b491ccd4..3e086e159 100644 --- a/config/chips/L41x.chip +++ b/config/chips/L41x_L42x.chip @@ -1,7 +1,7 @@ -# Chip-ID file for L41x +# Chip-ID file for L41x/L42x # chip_id 0x464 -description L41x +description L41x/L42x flash_type 6 flash_pagesize 0x800 sram_size 0xa000 diff --git a/config/chips/L45x_L46x.chip b/config/chips/L45x_46x.chip similarity index 75% rename from config/chips/L45x_L46x.chip rename to config/chips/L45x_46x.chip index 8b5f91ec3..943b275d5 100644 --- a/config/chips/L45x_L46x.chip +++ b/config/chips/L45x_46x.chip @@ -1,7 +1,7 @@ -# Chip-ID file for L45x/L46x +# Chip-ID file for L45x/46x # chip_id 0x462 -description L45x/L46x +description L45x/46x flash_type 6 flash_pagesize 0x800 sram_size 0x20000 diff --git a/config/chips/L4xx.chip b/config/chips/L47x_L48x.chip similarity index 76% rename from config/chips/L4xx.chip rename to config/chips/L47x_L48x.chip index c665c245f..7069229f3 100644 --- a/config/chips/L4xx.chip +++ b/config/chips/L47x_L48x.chip @@ -1,7 +1,7 @@ -# Chip-ID file for L4xx +# Chip-ID file for L47x/L48x # chip_id 0x415 -description L4xx +description L47x/L48x flash_type 6 flash_pagesize 0x800 sram_size 0x18000 diff --git a/config/chips/L4Px.chip b/config/chips/L4Px.chip new file mode 100644 index 000000000..3e0fbea50 --- /dev/null +++ b/config/chips/L4Px.chip @@ -0,0 +1,13 @@ +# Chip-ID file for L4Px +# +chip_id 0x471 +description L4Px +flash_type 6 +flash_pagesize 0x1000 +sram_size 0xa0000 +bootrom_base 0x1fff0000 +bootrom_size 0x7000 +option_base 0x0 +option_size 0x0 +flags dualbank swo + diff --git a/config/chips/L4Rx.chip b/config/chips/L4Rx.chip index 11780ce27..a9a26f419 100644 --- a/config/chips/L4Rx.chip +++ b/config/chips/L4Rx.chip @@ -9,5 +9,5 @@ bootrom_base 0x1fff0000 bootrom_size 0x7000 option_base 0x0 option_size 0x0 -flags swo +flags dualbank swo diff --git a/config/chips/WB55.chip b/config/chips/WB5x_3x.chip similarity index 76% rename from config/chips/WB55.chip rename to config/chips/WB5x_3x.chip index 585b576bc..0627bdeec 100644 --- a/config/chips/WB55.chip +++ b/config/chips/WB5x_3x.chip @@ -1,7 +1,7 @@ -# Chip-ID file for WB55 +# Chip-ID file for WB5x/3x # chip_id 0x495 -description WB55 +description WB5x/3x flash_type 9 flash_pagesize 0x1000 sram_size 0x40000 diff --git a/config/chips/WLE.chip b/config/chips/WLEx.chip similarity index 79% rename from config/chips/WLE.chip rename to config/chips/WLEx.chip index dbdf66d59..19d0678e5 100644 --- a/config/chips/WLE.chip +++ b/config/chips/WLEx.chip @@ -1,7 +1,7 @@ -# Chip-ID file for WLE +# Chip-ID file for WLEx # chip_id 0x497 -description WLE +description WLEx flash_type 9 flash_pagesize 0x800 sram_size 0x10000 From 0489af7d4d40ae32413fb449d064dad49ba227ee Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 29 Aug 2021 18:08:18 +0200 Subject: [PATCH 318/503] General Project Update - [doc] Updated version requirements - Updated CHANGELOG.md --- CHANGELOG.md | 4 ++ doc/version_support.md | 95 ++++++++++++++++++++++-------------------- 2 files changed, 54 insertions(+), 45 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index 9bbb41a98..06f995d21 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -25,6 +25,7 @@ Updates & changes: - Drop execute bits from source code files ([#1167](https://github.com/stlink-org/stlink/pull/1167)) - Use proper Markdown headers for supported MCUs ([#1168](https://github.com/stlink-org/stlink/pull/1168)) - Removed redundant array ([#1178](https://github.com/stlink-org/stlink/pull/1178)) +- Updated chip config files from the library structs ([#1181](https://github.com/stlink-org/stlink/pull/1181)) Fixes: - cmake: Install shared libraries in proper directories ([#1142](https://github.com/stlink-org/stlink/pull/1142)) @@ -37,6 +38,9 @@ Fixes: - Fixed parsing hex numbers in chip config files ([#1169](https://github.com/stlink-org/stlink/pull/1169)) - Corrected flash_pagesize to use hex format ([#1172](https://github.com/stlink-org/stlink/pull/1172)) - Fixed compilation for MSVC ([#1176](https://github.com/stlink-org/stlink/pull/1176)) +- Fixed few warnings for msvc about type conversion with possible lost data ([#1179](https://github.com/stlink-org/stlink/pull/1179)) +- st-flash and other utilities search for chip files in the wrong directory ([#1180](https://github.com/stlink-org/stlink/pull/1180), commit [#c8fc656](https://github.com/stlink-org/stlink/commit/c8fc6561fead79ad49c09d82bab864745086792c)) +- Fixed broken build on 32 bit systems ([#985](https://github.com/stlink-org/stlink/pull/985), [#1175](https://github.com/stlink-org/stlink/pull/1175), commit [#c8fc656](https://github.com/stlink-org/stlink/commit/c8fc6561fead79ad49c09d82bab864745086792c)) # v1.7.0 diff --git a/doc/version_support.md b/doc/version_support.md index bf4bc1e5e..2c5df7461 100644 --- a/doc/version_support.md +++ b/doc/version_support.md @@ -21,47 +21,51 @@ NOTE: In order to use a STLINK/V1 programmer on macOS, versions 10.14 or 10.15 a ### Linux-/Unix-based: -| Operating System | libusb | cmake | gtk-3 | Notes | -| ------------------------- | ------------------ | --------- | ----------- | ----------------------------- | -| Arch Linux | 1.0.24 | 3.20.2 | 3.24.29 | | -| Fedora Rawhide [x64] | 1.0.24 (`libusbx`) | 3.20.2 | 3.24.29 | | -| KaOS [x64] | 1.0.24 | 3.20.2 | 3.24.29 | | -| Mageia Cauldron | 1.0.24 | 3.20.2 | 3.24.29 | | -| OpenMandriva Cooker | 1.0.24 | 3.20.2 | 3.24.29 | | -| OpenMandriva Rolling | 1.0.24 | 3.20.2 | 3.24.29 | | -| PCLinuxOS [x64] | 1.0.24 | 3.20.2 | 3.24.29 | | -| Slackware Current | 1.0.24 | 3.20.2 | 3.24.28 | | -| Solus [x64] | 1.0.24 | 3.20.2 | 3.24.29 | | -| openSUSE Tumbleweed [x64] | 1.0.24 | 3.20.1 | 3.24.29 | | -| ALT Linux Sisyphus | 1.0.24 | 3.19.7 | 3.24.29 | | -| Fedora 34 [x64] | 1.0.24 (`libusbx`) | 3.19.7 | 3.24.28 | | -| NetBSD 9.x | 1.0.24 | 3.19.7 | 3.24.27 | | -| NetBSD 8.x | 1.0.24 | 3.19.7 | 3.24.27 | | -| OpenMandriva Lx 4.2 | 1.0.24 | 3.19.3 | 3.24.24 | | -| Mageia 8 | 1.0.24 | 3.19.2 | 3.24.24 | | -| Alpine 3.13 | 1.0.24 | 3.18.4 | 3.24.23 | | -| Debian Sid | 1.0.24 | 3.18.4 | 3.24.24 | | -| Debian 11 (Bullseye) | 1.0.24 | 3.18.4 | 3.24.24 | | -| Ubuntu 21.04 (Hirsute) | 1.0.24 | 3.18.4 | 3.24.25 | | -| Fedora 33 [x64] | 1.0.23 (`libusbx`) | 3.18.3 | 3.24.23 | | -| CentOS 8 Stream [x64] | 1.0.23 (`libusbx`) | 3.18.2 | **3.22.30** | | -| Alpine 3.12 | 1.0.23 | 3.17.2 | 3.24.22 | | -| openSUSE Leap 15.3 [x64] | 1.0.**21** | 3.17.0 | 3.24.20 | | -| openSUSE Leap 15.2 [x64] | 1.0.**21** | 3.17.0 | 3.24.**14** | | -| Adélie 1.0 | 1.0.23 | 3.16.4 | 3.24.23 | | -| Ubuntu 20.04 LTS (Focal) | 1.0.23 | 3.16.3 | 3.24.**18** | | -| ALT Linux P9 | 1.0.**22** | 3.16.3 | 3.24.**11** | | -| Alpine 3.11 | 1.0.23 | 3.15.5 | 3.24.**13** | | -| Mageia 7.1 | 1.0.**22** | 3.14.3 | 3.24.**8** | | -| Debian 10 (Buster) | 1.0.**22** | 3.13.4 | 3.24.**5** | | -| AlmaLinux 8 | 1.0.23 (`libusbx`) | 3.11.4 | 3.24.32 | | -| CentOS 8 [x64] | 1.0.23 (`libusbx`) | 3.11.4 | **3.22.30** | | -| Ubuntu 18.04 LTS (Bionic) | 1.0.**21** | 3.10.2 | **3.22.30** | | -| Debian 9 (Stretch) | 1.0.**21** | **3.7.2** | **3.22.11** | | -| | | | | | -| FreeBSD 13.x | 1.0.**16 - 18** | 3.20.2 | 3.24.27 | LIBUSB_API_VERSION 0x01000102 | -| FreeBSD 12.x | 1.0.**16 - 18** | 3.19.6 | 3.24.27 | LIBUSB_API_VERSION 0x01000102 | -| FreeBSD 11.x | 1.0.**16 - 18** | 3.15.5 | 3.24.27 | LIBUSB_API_VERSION 0x01000102 | +| Operating System | libusb | cmake | gtk-3 | Notes | +| ------------------------- | -------------------------------- | --------- | ----------- | ------------------------ | +| Debian Sid | 1.0.24 | 3.18.4 | 3.24.24 | | +| Debian 11 (Bullseye) | 1.0.24 | 3.18.4 | 3.24.24 | | +| Debian 10 (Buster) | 1.0.**22** | 3.13.4 | 3.24.**5** | | +| Debian 9 (Stretch) | 1.0.**21** | **3.7.2** | **3.22.11** | End of Support: Jun 2022 | +| | | | | | +| Ubuntu 21.04 (Hirsute) | 1.0.24 | 3.18.4 | 3.24.25 | End of Support: Jan 2022 | +| Ubuntu 20.04 LTS (Focal) | 1.0.23 | 3.16.3 | 3.24.**18** | | +| Ubuntu 18.04 LTS (Bionic) | 1.0.**21** | 3.10.2 | **3.22.30** | End of Support: Apr 2023 | +| | | | | | +| Fedora Rawhide [x64] | 1.0.24 (`libusbx`) | 3.20.2 | 3.24.29 | | +| Fedora 34 [x64] | 1.0.24 (`libusbx`) | 3.19.7 | 3.24.28 | | +| Fedora 33 [x64] | 1.0.23 (`libusbx`) | 3.18.3 | 3.24.23 | | +| | | | | | +| openSUSE Tumbleweed [x64] | 1.0.24 | 3.20.1 | 3.24.29 | | +| openSUSE Leap 15.3 [x64] | 1.0.**21** | 3.17.0 | 3.24.20 | | +| openSUSE Leap 15.2 [x64] | 1.0.**21** | 3.17.0 | 3.24.**14** | End of Support: Dec 2021 | +| | | | | | +| Alpine 3.14 | 1.0.24 | 3.20.3 | 4.2.1 | | +| Alpine 3.13 | 1.0.24 | 3.18.4 | 3.24.23 | End of Support: Nov 2022 | +| Alpine 3.12 | 1.0.23 | 3.17.2 | 3.24.22 | End of Support: May 2022 | +| Alpine 3.11 | 1.0.23 | 3.15.5 | 3.24.**13** | End of Support: Nov 2021 | +| | | | | | +| FreeBSD 13.x | 1.0.**16 - 18** (API 0x01000102) | 3.20.2 | 3.24.27 | | +| FreeBSD 12.x | 1.0.**16 - 18** (API 0x01000102) | 3.19.6 | 3.24.27 | | +| FreeBSD 11.x | 1.0.**16 - 18** (API 0x01000102) | 3.15.5 | 3.24.27 | End of Support: Sep 2021 | +| | | | | | +| Arch Linux | 1.0.24 | 3.20.2 | 3.24.29 | | +| KaOS [x64] | 1.0.24 | 3.20.2 | 3.24.29 | | +| Mageia Cauldron | 1.0.24 | 3.20.2 | 3.24.29 | | +| OpenMandriva Cooker | 1.0.24 | 3.20.2 | 3.24.29 | | +| PCLinuxOS [x64] | 1.0.24 | 3.20.2 | 3.24.29 | | +| Slackware Current | 1.0.24 | 3.20.2 | 3.24.28 | | +| Solus [x64] | 1.0.24 | 3.20.2 | 3.24.29 | | +| ALT Linux Sisyphus | 1.0.24 | 3.19.7 | 3.24.29 | | +| NetBSD 9.x | 1.0.24 | 3.19.7 | 3.24.27 | | +| NetBSD 8.x | 1.0.24 | 3.19.7 | 3.24.27 | | +| OpenMandriva Lx 4.2 | 1.0.24 | 3.19.3 | 3.24.24 | | +| Mageia 8 | 1.0.24 | 3.19.2 | 3.24.24 | End of Support: Aug 2022 | +| CentOS 8 Stream [x64] | 1.0.23 (`libusbx`) | 3.18.2 | **3.22.30** | | +| Adélie 1.0 | 1.0.23 | 3.16.4 | 3.24.23 | | +| ALT Linux P9 | 1.0.**22** | 3.16.3 | 3.24.**11** | | +| AlmaLinux 8 | 1.0.23 (`libusbx`) | 3.11.4 | 3.24.32 | | +| CentOS 8 [x64] | 1.0.23 (`libusbx`) | 3.11.4 | **3.22.30** | End of Support: Dec 2021 | ## Unsupported Operating Systems (as of Release v1.7.1) @@ -74,17 +78,18 @@ Systems with highlighted versions remain compatible with this toolset. | NetBSD 7.x | **1.0.22** | **3.16.1** | Jun 2020 | | Alpine 3.10 | **1.0.22** | **3.14.5** | May 2021 | | Fedora 31 [x64] | **1.0.22** (`libusbx`) | **3.14.5** | Nov 2020 | -| Ubuntu 19.10 (Eoan) | **1.0.23** | **3.13.4** | Jul 2020 | +| Mageia 7.1 | **1.0.22** | **3.14.3** | Jun 2021 | | Fedora 30 | **1.0.22** (`libusbx`) | **3.14.2** | May 2020 | +| Ubuntu 19.10 (Eoan) | **1.0.23** | **3.13.4** | Jul 2020 | | Alpine 3.9 | **1.0.22** | **3.13.0** | Jan 2021 | -| openSUSE Leap 15.1 [x64] | **1.0.21** | **3.10.2** | Feb 2021 | +| openSUSE Leap 15.1 [x64] | **1.0.21** | **3.10.2** | Jan 2021 | | Slackware 14.2 | 1.0.20 | 3.5.2 | | | Ubuntu 16.04 LTS (Xenial) | 1.0.20 | 3.5.1 | Apr 2021 | | OpenMandriva Lx 3.0x | 1.0.20 | 3.4.2 | | | Debian 8 (Jessie) | 1.0.19 | 3.0.2 | Jun 2020 | -| CentOS 7 [x64] | 1.0.21 (`libusbx`) | 2.8.12.2 | | +| CentOS 7 [x64] | 1.0.21 (`libusbx`) | 2.8.12.2 | Jun 2024 | | Ubuntu 14.04 LTS (Trusty) | 1.0.17 | 2.8.12.2 | Apr 2019 | -| CentOS 6 | 1.0.9 (`libusbx`) | 2.8.12.2 | Dec 2020 | +| CentOS 6 | 1.0.9 (`libusbx`) | 2.8.12.2 | Nov 2020 | | Slackware 14.1 | 1.0.9 | 2.8.12 | | | Slackware 14.0 | 1.0.9 | 2.8.8 | | From 7c582b75260fc2af16541d6b1c762ecc5817c906 Mon Sep 17 00:00:00 2001 From: Oleksiy Slyshyk Date: Wed, 1 Sep 2021 07:55:26 +0300 Subject: [PATCH 319/503] define SSIZE_MAX if not defined --- src/win32/unistd/unistd.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/win32/unistd/unistd.h b/src/win32/unistd/unistd.h index ac9d0add3..389c44664 100644 --- a/src/win32/unistd/unistd.h +++ b/src/win32/unistd/unistd.h @@ -51,6 +51,9 @@ */ #define ssize_t int +#ifndef SSIZE_MAX +#define SSIZE_MAX ((sizeof(ssize_t) == 4) ? 2147483647 : 9223372036854775807) +#endif #define STDIN_FILENO 0 #define STDOUT_FILENO 1 From 95ccd02207f7ba9b3323726bf16478879d956de1 Mon Sep 17 00:00:00 2001 From: Andreas Sandberg Date: Tue, 7 Sep 2021 23:12:46 +0100 Subject: [PATCH 320/503] Add support for V3 devices with no MSD Add support for ST-Link V3 devices without MSD that identify using USB PID 0x3754. This PID has been observed on a Nucleo board where MSD was disabled. --- src/stlink-lib/usb.c | 3 ++- src/stlink-lib/usb.h | 4 +++- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/src/stlink-lib/usb.c b/src/stlink-lib/usb.c index 58a07f1a6..e07918800 100644 --- a/src/stlink-lib/usb.c +++ b/src/stlink-lib/usb.c @@ -1260,7 +1260,8 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, enum connect_type connect, desc.idProduct == STLINK_USB_PID_STLINK_V3_USBLOADER || desc.idProduct == STLINK_USB_PID_STLINK_V3E_PID || desc.idProduct == STLINK_USB_PID_STLINK_V3S_PID || - desc.idProduct == STLINK_USB_PID_STLINK_V3_2VCP_PID) { + desc.idProduct == STLINK_USB_PID_STLINK_V3_2VCP_PID || + desc.idProduct == STLINK_USB_PID_STLINK_V3_NO_MSD_PID) { slu->ep_req = 1 /* ep req */ | LIBUSB_ENDPOINT_OUT; slu->ep_trace = 2 | LIBUSB_ENDPOINT_IN; } else { diff --git a/src/stlink-lib/usb.h b/src/stlink-lib/usb.h index 27de32700..c6b71ba4e 100644 --- a/src/stlink-lib/usb.h +++ b/src/stlink-lib/usb.h @@ -26,6 +26,7 @@ extern "C" { #define STLINK_USB_PID_STLINK_V3E_PID 0x374e #define STLINK_USB_PID_STLINK_V3S_PID 0x374f #define STLINK_USB_PID_STLINK_V3_2VCP_PID 0x3753 +#define STLINK_USB_PID_STLINK_V3_NO_MSD_PID 0x3754 #define STLINK_V1_USB_PID(pid) ((pid) == STLINK_USB_PID_STLINK) @@ -38,7 +39,8 @@ extern "C" { #define STLINK_V3_USB_PID(pid) ((pid) == STLINK_USB_PID_STLINK_V3_USBLOADER || \ (pid) == STLINK_USB_PID_STLINK_V3E_PID || \ (pid) == STLINK_USB_PID_STLINK_V3S_PID || \ - (pid) == STLINK_USB_PID_STLINK_V3_2VCP_PID) + (pid) == STLINK_USB_PID_STLINK_V3_2VCP_PID || \ + (pid) == STLINK_USB_PID_STLINK_V3_NO_MSD_PID) #define STLINK_SUPPORTED_USB_PID(pid) (STLINK_V1_USB_PID(pid) || \ STLINK_V2_USB_PID(pid) || \ From 6471a60460a4659134cf80d8864a022dc09b8447 Mon Sep 17 00:00:00 2001 From: pcnorden <7767295+pcnorden@users.noreply.github.com> Date: Wed, 8 Sep 2021 17:20:58 +0200 Subject: [PATCH 321/503] Changed broken link to new address of udev rules Changed and checked that it should work with the new link. Also changed the number of files to 4 since there are 4 udev rule files in the directory. --- doc/tutorial.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/doc/tutorial.md b/doc/tutorial.md index 7e0b3901b..955f85611 100644 --- a/doc/tutorial.md +++ b/doc/tutorial.md @@ -81,7 +81,7 @@ SUBSYSTEMS=="usb", ATTRS{idVendor}=="0483", ATTRS{idProduct}=="374b", \ and the `idVendor` of `0483` and `idProduct` of `374b` matches the vendor id from the `lsusb` output. -Make sure that you have all 3 files from here: https://github.com/stlink-org/stlink/tree/master/etc/udev/rules.d in your `/etc/udev/rules.d` directory. After copying new files or editing excisting files in `/etc/udev/ruled.d` you should run the following: +Make sure that you have all 4 files from here: https://github.com/stlink-org/stlink/tree/master/config/udev/rules.d in your `/etc/udev/rules.d` directory. After copying new files or editing excisting files in `/etc/udev/ruled.d` you should run the following: ``` sudo udevadm control --reload-rules From 478cf82aed3463566ba34399b8a283f7e57b3fcc Mon Sep 17 00:00:00 2001 From: Andreas Sandberg Date: Wed, 8 Sep 2021 22:09:24 +0100 Subject: [PATCH 322/503] Include flash_size_reg in chipid params dumps --- src/stlink-lib/chipid.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index d51a0edcb..0fc1270a2 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -906,6 +906,7 @@ void dump_a_chip (FILE *fp, struct stlink_chipid_params *dev) { fprintf(fp, "chip_id 0x%x\n", dev->chip_id); fprintf(fp, "description %s\n", dev->description); fprintf(fp, "flash_type %d\n", dev->flash_type); + fprintf(fp, "flash_size_reg 0x%x\n", dev->flash_size_reg); fprintf(fp, "flash_pagesize 0x%x\n", dev->flash_pagesize); fprintf(fp, "sram_size 0x%x\n", dev->sram_size); fprintf(fp, "bootrom_base 0x%x\n", dev->bootrom_base); From c676779988c65658cf3e67a60f46f767dfa4421a Mon Sep 17 00:00:00 2001 From: Andreas Sandberg Date: Wed, 8 Sep 2021 22:10:25 +0100 Subject: [PATCH 323/503] Fix incorrect chipid params comparison The current chipid params comparison code is based on a simple memcmp. This doesn't work since the structure contains a string pointer. Replace it with a simple field-by-field comparison. --- src/stlink-lib/chipid.c | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index 0fc1270a2..3e89ec0c1 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -916,6 +916,22 @@ void dump_a_chip (FILE *fp, struct stlink_chipid_params *dev) { fprintf(fp, "flags %d\n\n", dev->flags); } +static int chipid_params_eq(struct stlink_chipid_params *p1, struct stlink_chipid_params *p2) +{ + return p1->chip_id == p2->chip_id && + p1->description && p2->description && + strcmp(p1->description, p2->description) == 0 && + p1->flash_type == p2->flash_type && + p1->flash_size_reg == p2->flash_size_reg && + p1->flash_pagesize == p2->flash_pagesize && + p1->sram_size == p2->sram_size && + p1->bootrom_base == p2->bootrom_base && + p1->bootrom_size == p2->bootrom_size && + p1->option_base == p2->option_base && + p1->option_size == p2->option_size && + p1->flags == p2->flags; +} + struct stlink_chipid_params *stlink_chipid_get_params(uint32_t chipid) { struct stlink_chipid_params *params = NULL; struct stlink_chipid_params *p2; @@ -931,7 +947,7 @@ struct stlink_chipid_params *stlink_chipid_get_params(uint32_t chipid) { #if 1 if (params == NULL) { params = p2; - } else if (memcmp (p2, params, sizeof(struct stlink_chipid_params) - sizeof(struct stlink_chipid_params *)) != 0) { + } else if (!chipid_params_eq(params, p2)) { // fprintf (stderr, "Error, chipid params not identical\n"); // return NULL; fprintf(stderr, "---------- old ------------\n"); From b29a740b15df4c44258db4e3ae8bfba6676b851d Mon Sep 17 00:00:00 2001 From: Andreas Sandberg Date: Wed, 8 Sep 2021 22:11:59 +0100 Subject: [PATCH 324/503] Silence warning chipid files with STLINK_FLASH_TYPE_UNKNOWN The chipid configuration parser currently emits a warning when it encounters a file with the flash type set to STLINK_FLASH_TYPE_UNKNOWN. In practice, this means that the warning will always be printed since 'unknown_device.chip' uses this value. Make STLINK_FLASH_TYPE_UNKNOWN a permitted value in the config file parser. --- src/stlink-lib/chipid.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index 3e89ec0c1..74e1a1647 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -1001,7 +1001,7 @@ void process_chipfile(char *fname) { } else if (strcmp (word, "flash_type") == 0) { if (sscanf(value, "%i", (int *)&ts->flash_type) < 1) { fprintf(stderr, "Failed to parse flash type\n"); - } else if (ts->flash_type <= STLINK_FLASH_TYPE_UNKNOWN || ts->flash_type >= STLINK_FLASH_TYPE_MAX) { + } else if (ts->flash_type < STLINK_FLASH_TYPE_UNKNOWN || ts->flash_type >= STLINK_FLASH_TYPE_MAX) { fprintf(stderr, "Unrecognized flash type\n"); } } else if (strcmp (word, "flash_size_reg") == 0) { From 4d556ce150e4048beb6fb6e886b29e2f8962e690 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Thu, 16 Sep 2021 00:57:54 +0200 Subject: [PATCH 325/503] Update src/stlink-lib/chipid.c Co-authored-by: Grzegorz Szymaszek --- src/stlink-lib/chipid.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index 74e1a1647..43a55a495 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -916,7 +916,7 @@ void dump_a_chip (FILE *fp, struct stlink_chipid_params *dev) { fprintf(fp, "flags %d\n\n", dev->flags); } -static int chipid_params_eq(struct stlink_chipid_params *p1, struct stlink_chipid_params *p2) +static int chipid_params_eq(const struct stlink_chipid_params *p1, const struct stlink_chipid_params *p2) { return p1->chip_id == p2->chip_id && p1->description && p2->description && From ce8e1c4942eace3d7d84e770a9401a21b41f72af Mon Sep 17 00:00:00 2001 From: c-grant <60671494+c-grant@users.noreply.github.com> Date: Thu, 4 Nov 2021 21:50:12 -0400 Subject: [PATCH 326/503] Update gdb-server.c --- src/st-util/gdb-server.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/st-util/gdb-server.c b/src/st-util/gdb-server.c index a651014c0..ad39ab14a 100644 --- a/src/st-util/gdb-server.c +++ b/src/st-util/gdb-server.c @@ -518,6 +518,8 @@ static const char* const memory_map_template_H72x3x = " 0x%x" " " " " // peripheral regs + " " // External Memory + " " // External device " " // cortex regs " " // bootrom ""; From e94b5db1b474268785a856e0859d21d6e2967a79 Mon Sep 17 00:00:00 2001 From: c-grant <60671494+c-grant@users.noreply.github.com> Date: Fri, 5 Nov 2021 23:45:52 -0400 Subject: [PATCH 327/503] Update gdb-server.c --- src/st-util/gdb-server.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/st-util/gdb-server.c b/src/st-util/gdb-server.c index ad39ab14a..81c0aa83a 100644 --- a/src/st-util/gdb-server.c +++ b/src/st-util/gdb-server.c @@ -513,13 +513,13 @@ static const char* const memory_map_template_H72x3x = " " // RAM D1 320kB " " // RAM D2 23kB " " // RAM D3 16kB - " " // Backup RAM 4kB + " " // Backup RAM 4kB " " " 0x%x" " " " " // peripheral regs " " // External Memory - " " // External device + " " // External device " " // cortex regs " " // bootrom ""; From f95aec79944c9963daa932a2af51838e396ff77c Mon Sep 17 00:00:00 2001 From: Jan Bramkamp Date: Wed, 24 Nov 2021 01:45:24 +0100 Subject: [PATCH 328/503] Teach cmake to find libusb-1.0 port/pkg on OpenBSD On OpenBSD libusb is provided by the libusb1 port/package. --- cmake/modules/Findlibusb.cmake | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/cmake/modules/Findlibusb.cmake b/cmake/modules/Findlibusb.cmake index d861bdd5f..cd52026f5 100644 --- a/cmake/modules/Findlibusb.cmake +++ b/cmake/modules/Findlibusb.cmake @@ -43,6 +43,23 @@ elseif (CMAKE_SYSTEM_NAME STREQUAL "FreeBSD") # FreeBSD; libusb is message(FATAL_ERROR "Expected libusb library not found on your system! Verify your system integrity.") endif () +elseif (CMAKE_SYSTEM_NAME STREQUAL "OpenBSD") # OpenBSD; libusb-1.0 is available from ports + FIND_PATH( + LIBUSB_INCLUDE_DIR NAMES libusb.h + HINTS /usr/local/include + PATH_SUFFIXES libusb-1.0 + ) + set(LIBUSB_NAME usb-1.0) + find_library( + LIBUSB_LIBRARY NAMES ${LIBUSB_NAME} + HINTS /usr/local + ) + FIND_PACKAGE_HANDLE_STANDARD_ARGS(libusb DEFAULT_MSG LIBUSB_LIBRARY LIBUSB_INCLUDE_DIR) + mark_as_advanced(LIBUSB_INCLUDE_DIR LIBUSB_LIBRARY) + if (NOT LIBUSB_FOUND) + message(FATAL_ERROR "No libusb-1.0 library found on your system! Install libusb-1.0 from ports or packages.") + endif () + elseif (WIN32 OR (EXISTS "/etc/debian_version" AND MINGW)) # Windows or MinGW-toolchain on Debian # MinGW/MSYS/MSVC: 64-bit or 32-bit? if (CMAKE_SIZEOF_VOID_P EQUAL 8) From 8dfebbe5898f4245b044c72330d3f2e2adf5177a Mon Sep 17 00:00:00 2001 From: Jan Bramkamp Date: Wed, 24 Nov 2021 01:48:12 +0100 Subject: [PATCH 329/503] Define the MINIMUM_API_LEVEL for OpenBSD Every platform has to declare the minimum libusb API level required by libstlink on it. --- src/stlink-lib/libusb_settings.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/stlink-lib/libusb_settings.h b/src/stlink-lib/libusb_settings.h index fea28237b..a2dfc6d26 100644 --- a/src/stlink-lib/libusb_settings.h +++ b/src/stlink-lib/libusb_settings.h @@ -31,6 +31,8 @@ #if defined (__FreeBSD__) #define MINIMAL_API_VERSION 0x01000102 // v1.0.16 +#elif defined (__OpenBSD__) + #define MINIMAL_API_VERSION 0x01000104 // v1.0.20 #elif defined (__linux__) #define MINIMAL_API_VERSION 0x01000104 // v1.0.20 #elif defined (__APPLE__) From 60edcf811b89f9eef9aac431095582f9b8fa6be4 Mon Sep 17 00:00:00 2001 From: Crest da Zoltral Date: Thu, 23 Dec 2021 20:27:38 +0100 Subject: [PATCH 330/503] Include SSIZE_MAX from limits.h The existing includes don't pull in limits.h on FreeBSD breaking the build on FreeBSD. --- src/common.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/common.c b/src/common.c index c40f6aa79..bdd6f5bab 100644 --- a/src/common.c +++ b/src/common.c @@ -7,6 +7,7 @@ #include #include +#include #include #include #include From 2b106912c9b06e4c434f2c20b7897953e70dc5d3 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sat, 1 Jan 2022 20:24:59 +0100 Subject: [PATCH 331/503] Added user review to README.md --- README.md | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/README.md b/README.md index 0b124d21d..7f797a7d9 100644 --- a/README.md +++ b/README.md @@ -110,3 +110,9 @@ When there is no executable available for your platform or you need the latest ( - Please start new forks from the develop branch, as pull requests will go into this branch as well. Please also refer to our [Contribution Guidelines](CONTRIBUTING.md). + +## User Reviews + +*I hope it's not to out of topic, but I've been so frustrated with AVR related things on OpenBSD, the fact that stlink built out of the box without needing to touch anything was so relieving. Literally made my whole weekend better! +I take it's thanks to @Crest and also to the stlink-org team (@Nightwalker-87 and @xor-gate it seems) to have made a software that's not unfriendly to the "fringe" OSes. +Thank you <3"* - nbonfils, 11.12.2021 \ No newline at end of file From 0d02a46a8f013d4f4d6ce9f163a0625710ff27c2 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 2 Jan 2022 22:51:30 +0100 Subject: [PATCH 332/503] [refactoring] Clean-up for chipid files - Spelling fix in tutorial.md - REN param description --> dev_type - ADD param ref_manual_id - CHNG stlink_chipid_params - MV old chipids to chipid_db_old.h - Updated chipid files (F1, F2, WB, WLE) --- config/chips/F1_Low_density_device.chip | 13 - config/chips/F1xx_CL.chip | 14 +- config/chips/F1xx_HD.chip | 14 + config/chips/F1xx_High_density.chip | 13 - .../chips/F1xx_High_density_value_line.chip | 13 - config/chips/F1xx_LD.chip | 14 + config/chips/F1xx_MD.chip | 14 + config/chips/F1xx_Medium_density.chip | 13 - config/chips/F1xx_VL_HD.chip | 14 + config/chips/F1xx_VL_MD_LD.chip | 14 + config/chips/F1xx_Value_Line.chip | 13 - config/chips/F1xx_XLD.chip | 14 + config/chips/F1xx_XL_density.chip | 13 - config/chips/F2xx.chip | 15 +- config/chips/WB5x_3x.chip | 13 - config/chips/WBx5_WBx0.chip | 14 + config/chips/WLEx.chip | 13 +- config/chips/unknown_device.chip | 9 +- doc/tutorial.md | 2 +- src/common.c | 2 +- src/st-info/info.c | 4 +- src/st-trace/trace.c | 2 +- src/stlink-gui/gui.c | 2 +- src/stlink-lib/chipid.c | 936 +----------------- src/stlink-lib/chipid.h | 4 +- src/stlink-lib/chipid_db_old.h | 879 ++++++++++++++++ 26 files changed, 1037 insertions(+), 1034 deletions(-) delete mode 100644 config/chips/F1_Low_density_device.chip create mode 100644 config/chips/F1xx_HD.chip delete mode 100644 config/chips/F1xx_High_density.chip delete mode 100644 config/chips/F1xx_High_density_value_line.chip create mode 100644 config/chips/F1xx_LD.chip create mode 100644 config/chips/F1xx_MD.chip delete mode 100644 config/chips/F1xx_Medium_density.chip create mode 100644 config/chips/F1xx_VL_HD.chip create mode 100644 config/chips/F1xx_VL_MD_LD.chip delete mode 100644 config/chips/F1xx_Value_Line.chip create mode 100644 config/chips/F1xx_XLD.chip delete mode 100644 config/chips/F1xx_XL_density.chip delete mode 100644 config/chips/WB5x_3x.chip create mode 100644 config/chips/WBx5_WBx0.chip create mode 100644 src/stlink-lib/chipid_db_old.h diff --git a/config/chips/F1_Low_density_device.chip b/config/chips/F1_Low_density_device.chip deleted file mode 100644 index 33fa03e1b..000000000 --- a/config/chips/F1_Low_density_device.chip +++ /dev/null @@ -1,13 +0,0 @@ -# Chip-ID file for F1 Low-density device -# -chip_id 0x412 -description F1 Low-density device -flash_type 1 -flash_pagesize 0x400 -sram_size 0x2800 -bootrom_base 0x1ffff000 -bootrom_size 0x800 -option_base 0x1ffff800 -option_size 0x10 -flags swo - diff --git a/config/chips/F1xx_CL.chip b/config/chips/F1xx_CL.chip index c2a3b2e69..6282bc2ee 100644 --- a/config/chips/F1xx_CL.chip +++ b/config/chips/F1xx_CL.chip @@ -1,13 +1,15 @@ -# Chip-ID file for F1xx CL +# Chip-ID file for STM32F1xx CL device # -chip_id 0x418 -description F1xx CL -flash_type 1 +dev_type STM32F1xx Connectivity Line device +ref_manual_id 0008 +chip_id 0x418 // STLINK_CHIPID_STM32_F1_CONN +flash_type 1 // STLINK_FLASH_TYPE_F0 +flash_size_reg 0x1ffff7e0 flash_pagesize 0x800 sram_size 0x10000 bootrom_base 0x1fffb000 bootrom_size 0x4800 -option_base 0x1ffff800 -option_size 0x10 +option_base 0x1ffff800 // STM32_F0_OPTION_BYTES_BASE +option_size 0x10 // 16 flags swo diff --git a/config/chips/F1xx_HD.chip b/config/chips/F1xx_HD.chip new file mode 100644 index 000000000..72ad9fa75 --- /dev/null +++ b/config/chips/F1xx_HD.chip @@ -0,0 +1,14 @@ +# Chip-ID file for STM32F1xx high density device +# +dev_type F1xx high density device +ref_manual_id 0008 +chip_id 0x414 // STLINK_CHIPID_STM32_F1_HD +flash_type 1 // STLINK_FLASH_TYPE_F0 +flash_size_reg 0x1ffff7e0 +flash_pagesize 0x800 +sram_size 0x10000 +bootrom_base 0x1ffff000 +bootrom_size 0x800 +option_base 0x1ffff800 // STM32_F0_OPTION_BYTES_BASE +option_size 0x10 // 16 +flags swo diff --git a/config/chips/F1xx_High_density.chip b/config/chips/F1xx_High_density.chip deleted file mode 100644 index 1deb5f01b..000000000 --- a/config/chips/F1xx_High_density.chip +++ /dev/null @@ -1,13 +0,0 @@ -# Chip-ID file for F1xx High-density -# -chip_id 0x414 -description F1xx High-density -flash_type 1 -flash_pagesize 0x800 -sram_size 0x10000 -bootrom_base 0x1ffff000 -bootrom_size 0x800 -option_base 0x1ffff800 -option_size 0x10 -flags swo - diff --git a/config/chips/F1xx_High_density_value_line.chip b/config/chips/F1xx_High_density_value_line.chip deleted file mode 100644 index 9e467c9d7..000000000 --- a/config/chips/F1xx_High_density_value_line.chip +++ /dev/null @@ -1,13 +0,0 @@ -# Chip-ID file for F1xx High-density value line -# -chip_id 0x428 -description F1xx High-density value line -flash_type 1 -flash_pagesize 0x800 -sram_size 0x8000 -bootrom_base 0x1ffff000 -bootrom_size 0x800 -option_base 0x1ffff800 -option_size 0x10 -flags swo - diff --git a/config/chips/F1xx_LD.chip b/config/chips/F1xx_LD.chip new file mode 100644 index 000000000..8a3682755 --- /dev/null +++ b/config/chips/F1xx_LD.chip @@ -0,0 +1,14 @@ +# Chip-ID file for STM32F1 low density device +# +dev_type STM32F1xx low density device +ref_manual_id 0008 +chip_id 0x412 // STLINK_CHIPID_STM32_F1_LD +flash_type 1 // STLINK_FLASH_TYPE_F0 +flash_size_reg 0x1ffff7e0 +flash_pagesize 0x400 +sram_size 0x2800 +bootrom_base 0x1ffff000 +bootrom_size 0x800 +option_base 0x1ffff800 // STM32_F0_OPTION_BYTES_BASE +option_size 0x10 // 16 +flags swo diff --git a/config/chips/F1xx_MD.chip b/config/chips/F1xx_MD.chip new file mode 100644 index 000000000..f3da99493 --- /dev/null +++ b/config/chips/F1xx_MD.chip @@ -0,0 +1,14 @@ +# Chip-ID file for STM32F1xx medium density device +# +dev_type STM32F1xx medium density device +ref_manual_id 0008 +chip_id 0x410 // STLINK_CHIPID_STM32_F1_MD +flash_type 1 // STLINK_FLASH_TYPE_F0 +flash_size_reg 0x1ffff7e0 +flash_pagesize 0x400 +sram_size 0x5000 +bootrom_base 0x1ffff000 // Section 2.3.3 "Embedded Flash memory" +bootrom_size 0x800 +option_base 0x1ffff800 // STM32_F0_OPTION_BYTES_BASE +option_size 0x10 // 16 +flags swo diff --git a/config/chips/F1xx_Medium_density.chip b/config/chips/F1xx_Medium_density.chip deleted file mode 100644 index a6d81d6f6..000000000 --- a/config/chips/F1xx_Medium_density.chip +++ /dev/null @@ -1,13 +0,0 @@ -# Chip-ID file for F1xx Medium-density -# -chip_id 0x410 -description F1xx Medium-density -flash_type 1 -flash_pagesize 0x400 -sram_size 0x5000 -bootrom_base 0x1ffff000 -bootrom_size 0x800 -option_base 0x1ffff800 -option_size 0x10 -flags swo - diff --git a/config/chips/F1xx_VL_HD.chip b/config/chips/F1xx_VL_HD.chip new file mode 100644 index 000000000..f46945a94 --- /dev/null +++ b/config/chips/F1xx_VL_HD.chip @@ -0,0 +1,14 @@ +# Chip-ID file for STM32F1xx high density Value Line device +# +dev_type STM32F1xx Value Line high density device +ref_manual_id 0041 +chip_id 0x428 // STLINK_CHIPID_STM32_F1_VL_HD +flash_type 1 // STLINK_FLASH_TYPE_F0 +flash_size_reg 0x1ffff7e0 +flash_pagesize 0x800 +sram_size 0x8000 +bootrom_base 0x1ffff000 +bootrom_size 0x800 +option_base 0x1ffff800 // STM32_F0_OPTION_BYTES_BASE +option_size 0x10 // 16 +flags swo diff --git a/config/chips/F1xx_VL_MD_LD.chip b/config/chips/F1xx_VL_MD_LD.chip new file mode 100644 index 000000000..2bff05b82 --- /dev/null +++ b/config/chips/F1xx_VL_MD_LD.chip @@ -0,0 +1,14 @@ +# Chip-ID file for STMF1xx Value Line medium & low density device +# +dev_type STM32F1xx Value Line medium & low density device +ref_manual_id 0041 +chip_id 0x420 // STLINK_CHIPID_STM32_F1_VL_MD_LD +flash_type 1 // STLINK_FLASH_TYPE_F0 +flash_size_reg 0x1ffff7e0 +flash_pagesize 0x400 +sram_size 0x2000 // 0x1000 for low density devices +bootrom_base 0x1ffff000 +bootrom_size 0x800 +option_base 0x1ffff800 // STM32_F0_OPTION_BYTES_BASE +option_size 0x10 // 16 +flags swo diff --git a/config/chips/F1xx_Value_Line.chip b/config/chips/F1xx_Value_Line.chip deleted file mode 100644 index 463cc2d9c..000000000 --- a/config/chips/F1xx_Value_Line.chip +++ /dev/null @@ -1,13 +0,0 @@ -# Chip-ID file for F1xx Value Line -# -chip_id 0x420 -description F1xx Value Line -flash_type 1 -flash_pagesize 0x400 -sram_size 0x2000 -bootrom_base 0x1ffff000 -bootrom_size 0x800 -option_base 0x1ffff800 -option_size 0x10 -flags swo - diff --git a/config/chips/F1xx_XLD.chip b/config/chips/F1xx_XLD.chip new file mode 100644 index 000000000..90264ce0f --- /dev/null +++ b/config/chips/F1xx_XLD.chip @@ -0,0 +1,14 @@ +# Chip-ID file for STM32F1xx XL density device +# +dev_type STM32F1xx XL density device +ref_manual_id 0008 +chip_id 0x430 // STLINK_CHIPID_STM32_F1_XLD +flash_type 2 // STLINK_FLASH_TYPE_F1_XL +flash_size_reg 0x1ffff7e0 +flash_pagesize 0x800 +sram_size 0x18000 +bootrom_base 0x1fffe000 +bootrom_size 0x1800 +option_base 0x0 +option_size 0x0 +flags swo diff --git a/config/chips/F1xx_XL_density.chip b/config/chips/F1xx_XL_density.chip deleted file mode 100644 index 318efbff0..000000000 --- a/config/chips/F1xx_XL_density.chip +++ /dev/null @@ -1,13 +0,0 @@ -# Chip-ID file for F1xx XL-density -# -chip_id 0x430 -description F1xx XL-density -flash_type 2 -flash_pagesize 0x800 -sram_size 0x18000 -bootrom_base 0x1fffe000 -bootrom_size 0x1800 -option_base 0x0 -option_size 0x0 -flags swo - diff --git a/config/chips/F2xx.chip b/config/chips/F2xx.chip index 30808f1aa..ce2e9e698 100644 --- a/config/chips/F2xx.chip +++ b/config/chips/F2xx.chip @@ -1,13 +1,14 @@ -# Chip-ID file for F2xx +# Chip-ID file for STM32F2xx device (STM32F205xx, STM32F207xx, STM32F215xx, STM32F217xx) # -chip_id 0x411 -description F2xx -flash_type 3 +dev_type STM32F2xx device +ref_manual_id 0033 +chip_id 0x411 // STLINK_CHIPID_STM32_F2 +flash_type 3 // STLINK_FLASH_TYPE_F4 +flash_size_reg 0x1fff7a22 flash_pagesize 0x20000 sram_size 0x20000 bootrom_base 0x1fff0000 bootrom_size 0x7800 -option_base 0x1fffc000 -option_size 0x4 +option_base 0x1fffc000 // STM32_F2_OPTION_BYTES_BASE +option_size 0x4 // 4 flags swo - diff --git a/config/chips/WB5x_3x.chip b/config/chips/WB5x_3x.chip deleted file mode 100644 index 0627bdeec..000000000 --- a/config/chips/WB5x_3x.chip +++ /dev/null @@ -1,13 +0,0 @@ -# Chip-ID file for WB5x/3x -# -chip_id 0x495 -description WB5x/3x -flash_type 9 -flash_pagesize 0x1000 -sram_size 0x40000 -bootrom_base 0x1fff0000 -bootrom_size 0x7000 -option_base 0x0 -option_size 0x0 -flags swo - diff --git a/config/chips/WBx5_WBx0.chip b/config/chips/WBx5_WBx0.chip new file mode 100644 index 000000000..5bd2501e6 --- /dev/null +++ b/config/chips/WBx5_WBx0.chip @@ -0,0 +1,14 @@ +# Chip-ID file for STM32WBx0 device (STM32WB55xx, STM32WB35xx, STM32WB50CG, STM32WB30CE) +# +dev_type STM32WBx0 device +ref_manual_id 0434 // also RM0471 +chip_id 0x495 // STLINK_CHIPID_STM32_WB55 +flash_type 9 // STLINK_FLASH_TYPE_WB +flash_size_reg 0x1fff75e0 +flash_pagesize 0x1000 // 4k +sram_size 0x40000 +bootrom_base 0x1fff0000 +bootrom_size 0x7000 +option_base 0x0 +option_size 0x0 +flags swo diff --git a/config/chips/WLEx.chip b/config/chips/WLEx.chip index 19d0678e5..e9b6248f6 100644 --- a/config/chips/WLEx.chip +++ b/config/chips/WLEx.chip @@ -1,13 +1,14 @@ -# Chip-ID file for WLEx +# Chip-ID file for STM32WLEx device # -chip_id 0x497 -description WLEx -flash_type 9 -flash_pagesize 0x800 +dev_type STM32WLEx device +ref_manual_id 0033 +chip_id 0x497 // STLINK_CHIPID_STM32_WLE +flash_type 9 // STLINK_FLASH_TYPE_WB +flash_size_reg 0x1fff75e0 +flash_pagesize 0x800 // 2k sram_size 0x10000 bootrom_base 0x1fff0000 bootrom_size 0x7000 option_base 0x0 option_size 0x0 flags swo - diff --git a/config/chips/unknown_device.chip b/config/chips/unknown_device.chip index c71206951..8f3772e53 100644 --- a/config/chips/unknown_device.chip +++ b/config/chips/unknown_device.chip @@ -1,8 +1,10 @@ # Chip-ID file for unknown device # -chip_id 0x0 -description unknown device -flash_type 0 +dev_type unknown device +ref_manual_id 0000 +chip_id 0x0 // STLINK_CHIPID_UNKNOWN +flash_type 0 // STLINK_FLASH_TYPE_UNKNOWN +flash_size_reg 0x0 flash_pagesize 0x0 sram_size 0x0 bootrom_base 0x0 @@ -10,4 +12,3 @@ bootrom_size 0x0 option_base 0x0 option_size 0x0 flags none - diff --git a/doc/tutorial.md b/doc/tutorial.md index 7e0b3901b..9ca6bef5b 100644 --- a/doc/tutorial.md +++ b/doc/tutorial.md @@ -81,7 +81,7 @@ SUBSYSTEMS=="usb", ATTRS{idVendor}=="0483", ATTRS{idProduct}=="374b", \ and the `idVendor` of `0483` and `idProduct` of `374b` matches the vendor id from the `lsusb` output. -Make sure that you have all 3 files from here: https://github.com/stlink-org/stlink/tree/master/etc/udev/rules.d in your `/etc/udev/rules.d` directory. After copying new files or editing excisting files in `/etc/udev/ruled.d` you should run the following: +Make sure that you have all 3 files from here: https://github.com/stlink-org/stlink/tree/master/etc/udev/rules.d in your `/etc/udev/rules.d` directory. After copying new files or editing existing files in `/etc/udev/ruled.d` you should run the following: ``` sudo udevadm control --reload-rules diff --git a/src/common.c b/src/common.c index c40f6aa79..9bfbfc52b 100644 --- a/src/common.c +++ b/src/common.c @@ -1671,7 +1671,7 @@ int stlink_load_device_params(stlink_t *sl) { } ILOG("%s: %u KiB SRAM, %u KiB flash in at least %u %s pages.\n", - params->description, (unsigned)(sl->sram_size / 1024), + params->dev_type, (unsigned)(sl->sram_size / 1024), (unsigned)(sl->flash_size / 1024), (sl->flash_pgsz < 1024) ? (unsigned)(sl->flash_pgsz) : (unsigned)(sl->flash_pgsz / 1024), diff --git a/src/st-info/info.c b/src/st-info/info.c index ceb406cda..416d27f56 100644 --- a/src/st-info/info.c +++ b/src/st-info/info.c @@ -42,7 +42,7 @@ static void stlink_print_info(stlink_t *sl) { printf(" chipid: 0x%.4x\n", sl->chip_id); params = stlink_chipid_get_params(sl->chip_id); - if (params) { printf(" descr: %s\n", params->description); } + if (params) { printf(" dev-type: %s\n", params->dev_type); } } static void stlink_probe(enum connect_type connect, int freq) { @@ -118,7 +118,7 @@ static int print_data(int ac, char **av) { const struct stlink_chipid_params *params = stlink_chipid_get_params(sl->chip_id); if (params == NULL) { return(-1); } - printf("%s\n", params->description); + printf("%s\n", params->dev_type); } if (sl) { diff --git a/src/st-trace/trace.c b/src/st-trace/trace.c index 754a55c72..46304d7d9 100644 --- a/src/st-trace/trace.c +++ b/src/st-trace/trace.c @@ -555,7 +555,7 @@ int main(int argc, char **argv) { if (!(stlink->chip_flags & CHIP_F_HAS_SWO_TRACING)) { const struct stlink_chipid_params *params = stlink_chipid_get_params(stlink->chip_id); - ELOG("We do not support SWO output for device '%s'\n", params->description); + ELOG("We do not support SWO output for device '%s'\n", params->dev_type); if (!settings.force) return APP_RESULT_STLINK_UNSUPPORTED_DEVICE; } diff --git a/src/stlink-gui/gui.c b/src/stlink-gui/gui.c index f9de46f37..387d3ac68 100644 --- a/src/stlink-gui/gui.c +++ b/src/stlink-gui/gui.c @@ -429,7 +429,7 @@ static gchar *dev_format_chip_id(guint32 chip_id) { if (!params) { return(g_strdup_printf("0x%x", chip_id)); } - return(g_strdup(params->description)); + return(g_strdup(params->dev_type)); } static gchar *dev_format_mem_size(gsize flash_size) { diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index d51a0edcb..a991e0921 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -1,5 +1,6 @@ #include #include "chipid.h" +#include "chipid_db_old.h" #include #include @@ -7,884 +8,6 @@ #include #include -// This is the old chipid "database". -// It is kept here for now to be able to compare the -// result between the "old code" and the "new code". -// For now if you need to change something, please -// change it both here and in the corresponding -// config/chips/*.chip file. - -static struct stlink_chipid_params devices[] = { - { - // STM32F76x/F77x - // RM0410 - .chip_id = STLINK_CHIPID_STM32_F76xxx, - .description = "F76x/F77x", - .flash_type = STLINK_FLASH_TYPE_F7, - .flash_size_reg = 0x1ff0f442, // section 45.2 - .flash_pagesize = 0x800, // No flash pages - .sram_size = 0x80000, // "SRAM" byte size in hex from - .bootrom_base = 0x00200000, // "System memory" starting address from - .bootrom_size = 0xEDC0, - .option_base = STM32_F7_OPTION_BYTES_BASE, /* Used for reading back the option - bytes, writing uses FLASH_F7_OPTCR - and FLASH_F7_OPTCR1 */ - .option_size = 0x20, - .flags = CHIP_F_HAS_DUAL_BANK | CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32F74x/F75x - // RM0385, DS10916 - .chip_id = STLINK_CHIPID_STM32_F7, - .description = "F74x/F75x", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1ff0f442, // section 41.2 - .flash_pagesize = 0x800, // No flash pages - .sram_size = 0x50000, // "SRAM" byte size in hex from DS Fig 18 - .bootrom_base = 0x00100000, // "System memory" starting address from DS Fig 18 - .bootrom_size = 0xEDC0, // "System memory" byte size in hex from DS Fig 18 - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32F72x/F73x - // RM0431 - .chip_id = STLINK_CHIPID_STM32_F72xxx, - .description = "F72x/F73x", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1ff07a22, // section 35.2 - .flash_pagesize = 0x800, // No flash pages - .sram_size = 0x40000, // "SRAM" byte size in hex from DS Fig 24 - .bootrom_base = 0x00100000, // "System memory" starting address from DS Fig 24 - .bootrom_size = 0xEDC0, // "System memory" byte size in hex from DS Fig 24 - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32F1xx medium-density devices - // RM0008 - .chip_id = STLINK_CHIPID_STM32_F1_MD, - .description = "F1xx Medium-density", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7e0, - .flash_pagesize = 0x400, - .sram_size = 0x5000, - .bootrom_base = 0x1ffff000, // 2.3.3 "Embedded Flash memory" - .bootrom_size = 0x800, - .option_base = STM32_F0_OPTION_BYTES_BASE, - .option_size = 16, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32F205xx, STM32F207xx, STM32F215xx, STM32F217xx - // RM0033 (rev 5) - .chip_id = STLINK_CHIPID_STM32_F2, - .description = "F2xx", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1fff7a22, - .flash_pagesize = 0x20000, - .sram_size = 0x20000, - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7800, - .option_base = 0x1FFFC000, - .option_size = 4, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32F1xx low-density devices - // RM0008 - .chip_id = STLINK_CHIPID_STM32_F1_LD, - .description = "F1 Low-density device", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7e0, - .flash_pagesize = 0x400, - .sram_size = 0x2800, - .bootrom_base = 0x1ffff000, - .bootrom_size = 0x800, - .option_base = STM32_F0_OPTION_BYTES_BASE, - .option_size = 16, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32F4x5/F4x7 - // RM0090 (rev 2) - .chip_id = STLINK_CHIPID_STM32_F4, - .description = "F4x5/F4x7", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1FFF7A22, - .flash_pagesize = 0x4000, - .sram_size = 0x30000, - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7800, - .option_base = STM32_F4_OPTION_BYTES_BASE, - .option_size = 4, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32F46x/F47x - // RM0090 (rev 2) - .chip_id = STLINK_CHIPID_STM32_F4_DSI, - .description = "F46x/F47x", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1FFF7A22, - .flash_pagesize = 0x4000, - .sram_size = 0x40000, - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7800, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32F42x/F43x - // RM0090 (rev 2) - .chip_id = STLINK_CHIPID_STM32_F4_HD, - .description = "F42x/F43x", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1FFF7A22, - .flash_pagesize = 0x4000, - .sram_size = 0x40000, - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7800, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - .chip_id = STLINK_CHIPID_STM32_F4_LP, - .description = "F401xB/C", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1FFF7A22, - .flash_pagesize = 0x4000, - .sram_size = 0x10000, - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7800, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - .chip_id = STLINK_CHIPID_STM32_F411xx, - .description = "F411xC/E", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1FFF7A22, - .flash_pagesize = 0x4000, - .sram_size = 0x20000, - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7800, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - .chip_id = STLINK_CHIPID_STM32_F4_DE, - .description = "F401xD/E", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1FFF7A22, - .flash_pagesize = 0x4000, - .sram_size = 0x18000, - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7800, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32F1xx high-density devices - // RM0008 - .chip_id = STLINK_CHIPID_STM32_F1_HD, - .description = "F1xx High-density", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7e0, - .flash_pagesize = 0x800, - .sram_size = 0x10000, - .bootrom_base = 0x1ffff000, - .bootrom_size = 0x800, - .option_base = STM32_F0_OPTION_BYTES_BASE, - .option_size = 16, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32L100/L15x/L16x Cat.1 - // RM0038 - .chip_id = STLINK_CHIPID_STM32_L1_MD, - .description = "L1xx Cat.1", - .flash_type = STLINK_FLASH_TYPE_L0, - .flash_size_reg = 0x1ff8004c, - .flash_pagesize = 0x100, - .sram_size = 0x4000, // up to 16k - .bootrom_base = 0x1ff00000, - .bootrom_size = 0x1000, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32L100/L15x/L16x Cat.2 - // RM0038 - .chip_id = STLINK_CHIPID_STM32_L1_CAT2, - .description = "L1xx Cat.2", - .flash_type = STLINK_FLASH_TYPE_L0, - .flash_size_reg = 0x1ff8004c, - .flash_pagesize = 0x100, - .sram_size = 0x8000, // up to 32k - .bootrom_base = 0x1ff00000, - .bootrom_size = 0x1000, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32L100/L15x/L16x Cat.3 - // RM0038 - .chip_id = STLINK_CHIPID_STM32_L1_MD_PLUS, - .description = "L1xx Cat.3", - .flash_type = STLINK_FLASH_TYPE_L0, - .flash_size_reg = 0x1ff800cc, - .flash_pagesize = 0x100, - .sram_size = 0x8000, // up to 32k - .bootrom_base = 0x1ff00000, - .bootrom_size = 0x1000, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32L100/L15x/L16x Cat.4 - // RM0038 - .chip_id = STLINK_CHIPID_STM32_L1_MD_PLUS_HD, - .description = "L1xx Cat.4", - .flash_type = STLINK_FLASH_TYPE_L0, - .flash_size_reg = 0x1ff800cc, - .flash_pagesize = 0x100, - .sram_size = 0xC000, // up to 48k - .bootrom_base = 0x1ff00000, - .bootrom_size = 0x1000, - .option_base = STM32_L1_OPTION_BYTES_BASE, - .option_size = 8, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32L100/L15x/L16x Cat.5 - // RM0038 - .chip_id = STLINK_CHIPID_STM32_L152_RE, - .description = "L1xx Cat.5", - .flash_type = STLINK_FLASH_TYPE_L0, - .flash_size_reg = 0x1ff800cc, - .flash_pagesize = 0x100, - .sram_size = 0x14000, // up to 80k - .bootrom_base = 0x1ff00000, - .bootrom_size = 0x1000, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32F1xx connectivity devices - // RM0008 - .chip_id = STLINK_CHIPID_STM32_F1_CONN, - .description = "F1xx CL", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7e0, - .flash_pagesize = 0x800, - .sram_size = 0x10000, - .bootrom_base = 0x1fffb000, - .bootrom_size = 0x4800, - .option_base = STM32_F0_OPTION_BYTES_BASE, - .option_size = 16, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32F1xx low- and medium-density value line devices - // RM0041 - .chip_id = STLINK_CHIPID_STM32_F1_VL_MD_LD, - .description = "F1xx Value Line", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7e0, - .flash_pagesize = 0x400, - .sram_size = 0x2000, // 0x1000 for low density devices - .bootrom_base = 0x1ffff000, - .bootrom_size = 0x800, - .option_base = STM32_F0_OPTION_BYTES_BASE, - .option_size = 16, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32F446x family - // RM0390 - .chip_id = STLINK_CHIPID_STM32_F446, - .description = "F446", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1fff7a22, - .flash_pagesize = 0x20000, - .sram_size = 0x20000, - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7800, - .option_base = 0x1FFFC000, - .option_size = 4, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32F410 - // RM0401 - .chip_id = STLINK_CHIPID_STM32_F410, - .description = "F410", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1fff7a22, - .flash_pagesize = 0x4000, - .sram_size = 0x8000, - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7800, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32F303xB/C, STM32F358, STM32F302xBxC - // RM0316, RM0365 - .chip_id = STLINK_CHIPID_STM32_F3, - .description = "F302/F303/F358", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7cc, - .flash_pagesize = 0x800, - .sram_size = 0xa000, - .bootrom_base = 0x1ffff000, - .bootrom_size = 0x800, - .option_base = STM32_F0_OPTION_BYTES_BASE, - .option_size = 16, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32F373Cx/Rx/Vx, STM32F378Cx/Rx/Vx - // RM0313 - .chip_id = STLINK_CHIPID_STM32_F37x, - .description = "F37x", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7cc, - .flash_pagesize = 0x800, - .sram_size = 0xa000, - .bootrom_base = 0x1ffff000, - .bootrom_size = 0x800, - .option_base = STM32_F0_OPTION_BYTES_BASE, - .option_size = 16, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32F1xx high-density value line devices - // RM0041 - .chip_id = STLINK_CHIPID_STM32_F1_VL_HD, - .description = "F1xx High-density value line", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7e0, - .flash_pagesize = 0x800, - .sram_size = 0x8000, - .bootrom_base = 0x1ffff000, - .bootrom_size = 0x800, - .option_base = STM32_F0_OPTION_BYTES_BASE, - .option_size = 16, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32F1xx XL-density devices - // RM0008 - .chip_id = STLINK_CHIPID_STM32_F1_XLD, - .description = "F1xx XL-density", - .flash_type = STLINK_FLASH_TYPE_F1_XL, - .flash_size_reg = 0x1ffff7e0, - .flash_pagesize = 0x800, - .sram_size = 0x18000, - .bootrom_base = 0x1fffe000, - .bootrom_size = 0x1800, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32F07x - // RM0091 - .chip_id = STLINK_CHIPID_STM32_F0_CAN, - .description = "F07x", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) - .flash_pagesize = 0x800, // Page sizes listed in Table 4 - .sram_size = 0x4000, // "SRAM" byte size in hex from Table 2 - .bootrom_base = 0x1fffC800, // "System memory" starting address from Table 2 - .bootrom_size = 0x3000, // "System memory" byte size in hex from Table 2 - .option_base = STM32_F0_OPTION_BYTES_BASE, - .option_size = 16, - }, - { - // STM32F05x - // RM0091 - .chip_id = STLINK_CHIPID_STM32_F0, - .description = "F05x", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) - .flash_pagesize = 0x400, // Page sizes listed in Table 4 - .sram_size = 0x2000, // "SRAM" byte size in hex from Table 2 - .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2 - .bootrom_size = 0xC00, // "System memory" byte size in hex from Table 2 - .option_base = STM32_F0_OPTION_BYTES_BASE, - .option_size = 16, - }, - { - // STM32F412 - // RM0402 - .chip_id = STLINK_CHIPID_STM32_F412, - .description = "F412", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1FFF7A22, // "Flash size data register" (pg1135) - .flash_pagesize = 0x4000, // Table 5. Flash module organization ? - .sram_size = 0x40000, // "SRAM" byte size in hex from Table 4 - .bootrom_base = 0x1FFF0000, // "System memory" starting address from Table 4 - .bootrom_size = 0x7800, // "System memory" byte size in hex from Table 4 - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32F413/F423 - // RM0430 (rev 2) - .chip_id = STLINK_CHIPID_STM32_F413, - .description = "F413/F423", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1FFF7A22, // "Flash size data register" Section 35.2 - .flash_pagesize = 0x4000, // Table 5. Flash module organization (variable sector - // sizes, but 0x4000 is smallest) - .sram_size = 0x50000, // "SRAM" byte size in hex from Figure 2 (Table 4 - // only says 0x40000) - .bootrom_base = 0x1FFF0000, // "System memory" starting address from Table 4 - .bootrom_size = 0x7800, // "System memory" byte size in hex from Table 4 - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32F09x - // RM0091 - .chip_id = STLINK_CHIPID_STM32_F09x, - .description = "F09x", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) - .flash_pagesize = 0x800, // Page sizes listed in Table 4 (pg 56) - .sram_size = 0x8000, // "SRAM" byte size in hex from Table 2 (pg 50) - .bootrom_base = 0x1fffd800, // "System memory" starting address from Table 2 - .bootrom_size = 0x2000, // "System memory" byte size in hex from Table 2 - .option_base = STM32_F0_OPTION_BYTES_BASE, - .option_size = 16, - }, - { - // STM32F04x - // RM0091 - .chip_id = STLINK_CHIPID_STM32_F04, - .description = "F04x", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) - .flash_pagesize = 0x400, // Page sizes listed in Table 4 - .sram_size = 0x1800, // "SRAM" byte size in hex from Table 2 - .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2 - .bootrom_size = 0xC00, // "System memory" byte size in hex from Table 2 - .option_base = STM32_F0_OPTION_BYTES_BASE, - .option_size = 16, - }, - { - // STM32F03x - // RM0091 - .chip_id = STLINK_CHIPID_STM32_F0xx_SMALL, - .description = "F03x", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) - .flash_pagesize = 0x400, // Page sizes listed in Table 4 - .sram_size = 0x1000, // "SRAM" byte size in hex from Table 2 - .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2 - .bootrom_size = 0xC00, // "System memory" byte size in hex from Table 2 - .option_base = STM32_F0_OPTION_BYTES_BASE, - .option_size = 16, - }, - { - // STM32F301x6/8, STM32F302x6x8, STM32F318x8 - // RM0366, RM0365 - .chip_id = STLINK_CHIPID_STM32_F3xx_SMALL, - .description = "F301/F302/F318", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7cc, - .flash_pagesize = 0x800, - .sram_size = 0xa000, - .bootrom_base = 0x1fffd800, - .bootrom_size = 0x2000, - .option_base = STM32_F0_OPTION_BYTES_BASE, - .option_size = 16, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32L0xx Category 3 - // RM0367, RM0377, RM0451 - .chip_id = STLINK_CHIPID_STM32_L0, - .description = "L0xx Cat.3", - .flash_type = STLINK_FLASH_TYPE_L0, - .flash_size_reg = 0x1ff8007c, - .flash_pagesize = 0x80, - .sram_size = 0x2000, - .bootrom_base = 0x1ff0000, - .bootrom_size = 0x1000, - .option_base = STM32_L0_OPTION_BYTES_BASE, - .option_size = 20, - }, - { - // STM32L0x Category 5 - // RM0367, RM0377, RM0451 - .chip_id = STLINK_CHIPID_STM32_L0_CAT5, - .description = "L0xx Cat.5", - .flash_type = STLINK_FLASH_TYPE_L0, - .flash_size_reg = 0x1ff8007c, - .flash_pagesize = 0x80, - .sram_size = 0x5000, - .bootrom_base = 0x1ff0000, - .bootrom_size = 0x2000, - .option_base = STM32_L0_OPTION_BYTES_BASE, - .option_size = 20, - .flags = CHIP_F_HAS_DUAL_BANK, - }, - { - // STM32L0x Category 2 - // RM0367, RM0377 - .chip_id = STLINK_CHIPID_STM32_L0_CAT2, - .description = "L0xx Cat.2", - .flash_type = STLINK_FLASH_TYPE_L0, - .flash_size_reg = 0x1ff8007c, - .flash_pagesize = 0x80, - .sram_size = 0x2000, - .bootrom_base = 0x1ff0000, - .bootrom_size = 0x1000, - .option_base = STM32_L0_OPTION_BYTES_BASE, - .option_size = 20, - }, - { - // STM32F334, STM32F303x6/8, STM32F328 - // RM0364, RM0316 - .chip_id = STLINK_CHIPID_STM32_F334, - .description = "F303/F328/F334", // (RM0316 sec 33.6.1) - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7cc, - .flash_pagesize = 0x800, - .sram_size = 0x3000, - .bootrom_base = 0x1fffd800, - .bootrom_size = 0x2000, - .option_base = STM32_F0_OPTION_BYTES_BASE, - .option_size = 16, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32F303xD/E, STM32F398xE, STM32F302xD/E - // RM0316 (rev 5), RM0365 - .chip_id = STLINK_CHIPID_STM32_F303_HD, - .description = "F303 high density", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7cc, // 34.2.1 Flash size data register - .flash_pagesize = 0x800, // 4.2.1 Flash memory organization - .sram_size = 0x10000, // 3.3 Embedded SRAM - .bootrom_base = 0x1fffd800, // 3.3.2 / Table 4 System Memory - .bootrom_size = 0x2000, - .option_base = STM32_F0_OPTION_BYTES_BASE, - .option_size = 16, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32L47x/L48x - // RM0351 - .chip_id = STLINK_CHIPID_STM32_L4, - .description = "L47x/L48x", - .flash_type = STLINK_FLASH_TYPE_L4, - .flash_size_reg = 0x1FFF75e0, // "Flash size data register" (sec 45.2, page 1671) - .flash_pagesize = 0x800, // 2k (sec 3.2, page 78; also appears in sec 3.3.1 - // and tables 4-6 on pages 79-81) - // SRAM1 is "up to" 96k in the standard Cortex-M memory map; - // SRAM2 is 32k mapped at at 0x10000000 (sec 2.3, page 73 for - // sizes; table 2, page 74 for SRAM2 location) - .sram_size = 0x18000, - .bootrom_base = 0x1fff0000, // Tables 4-6, pages 80-81 (Bank 1 system memory) - .bootrom_size = 0x7000, // 28k (per bank), same source as base - .option_base = STM32_L4_OPTION_BYTES_BASE, - .option_size = 4, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32L4RX - // RM0432 - .chip_id = STLINK_CHIPID_STM32_L4Rx, - .description = "L4Rx", - .flash_type = STLINK_FLASH_TYPE_L4, - .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 58.2, page 2274) - .flash_pagesize = 0x1000, // 4k, section 3.3, pg 117-120 - // TODO: flash_pagesize can be 8k depend on the dual-bank mode and flash size - .sram_size = 0xa0000, // 192k (SRAM1) + 64k SRAM2 + 384k SRAM3 = 640k, or 0xA0000 - .bootrom_base = 0x1fff0000, // 3.3.1, pg 117 - .bootrom_size = 0x7000, // 28k (per bank), same source as base (pg 117) - .flags = CHIP_F_HAS_DUAL_BANK | CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32L4PX - // RM0432 - .chip_id = STLINK_CHIPID_STM32_L4PX, - .description = "L4Px", - .flash_type = STLINK_FLASH_TYPE_L4, - .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 58.2, page 2274) - .flash_pagesize = 0x1000, // 4k, section 3.3, pg 117-120 - // TODO: flash_pagesize can be 8k depend on the dual-bank mode and flash size - .sram_size = 0xa0000, // 192k (SRAM1) + 64k SRAM2 + 384k SRAM3 = 640k, or 0xA0000 - .bootrom_base = 0x1fff0000, // 3.3.1, pg 117 - .bootrom_size = 0x7000, // 28k (per bank), same source as base (pg 117) - .flags = CHIP_F_HAS_DUAL_BANK | CHIP_F_HAS_SWO_TRACING, - }, - { - // STLINK_CHIPID_STM32_L41x_L42x - // RM0394 (rev 4), DS12469 (rev 5) - .chip_id = STLINK_CHIPID_STM32_L41x_L42x, - .description = "L41x/L42x", - .flash_type = STLINK_FLASH_TYPE_L4, - .flash_size_reg = 0x1fff75e0, // "Flash size data register" (RM0394, - // sec 47.2, page 1586) - .flash_pagesize = 0x800, // 2k (DS12469, sec 3.4, page 17) - // SRAM1 is 32k at 0x20000000 - // SRAM2 is 8k at 0x10000000 and 0x20008000 - // (DS12469, sec 3.5, page 18) - .sram_size = 0xa000, // 40k (DS12469, sec 3.5, page 18) - .bootrom_base = 0x1fff0000, // System Memory (RM0394, sec 3.3.1, table 8) - .bootrom_size = 0x7000, // 28k, same source as base - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STLINK_CHIPID_STM32_L43x_L44x - // RM0392 - .chip_id = STLINK_CHIPID_STM32_L43x_L44x, - .description = "L43x/L44x", - .flash_type = STLINK_FLASH_TYPE_L4, - .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 43.2, page 1410) - .flash_pagesize = 0x800, // 2k (sec 3.2, page 74; also appears in sec 3.3.1 - // and tables 7-8 on pages 75-76) - // SRAM1 is "up to" 64k in the standard Cortex-M memory map; - // SRAM2 is 16k mapped at 0x10000000 (sec 2.3, page 73 for - // sizes; table 2, page 74 for SRAM2 location) - .sram_size = 0xc000, - .bootrom_base = 0x1fff0000, // Tables 4-6, pages 80-81 (Bank 1 system memory) - .bootrom_size = 0x7000, // 28k (per bank), same source as base - .option_base = STM32_L4_OPTION_BYTES_BASE, - .option_size = 4, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STLINK_CHIPID_STM32_L496x_L4A6x - // RM0351 (rev 5) - .chip_id = STLINK_CHIPID_STM32_L496x_L4A6x, - .description = "L496x/L4A6x", - .flash_type = STLINK_FLASH_TYPE_L4, - .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 49.2, page 1809) - .flash_pagesize = 0x800, // Page erase (2 Kbyte) (sec 3.2, page 93) - // SRAM1 is 256k at 0x20000000 - // SRAM2 is 64k at 0x20040000 (sec 2.2.1, fig 2, page 74) - .sram_size = 0x40000, // Embedded SRAM (sec 2.4, page 84) - .bootrom_base = 0x1fff0000, // System Memory (Bank 1) (sec 3.3.1) - .bootrom_size = 0x7000, // 28k (per bank), same source as base - .option_base = STM32_L4_OPTION_BYTES_BASE, - .option_size = 4, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STLINK_CHIPID_STM32_L45x_L46x - // RM0394 (updated version of RM0392?) - .chip_id = STLINK_CHIPID_STM32_L45x_L46x, - .description = "L45x/46x", - .flash_type = STLINK_FLASH_TYPE_L4, - .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 45.2, page 1463) - .flash_pagesize = 0x800, // 2k (sec 3.2, page 73; also appears in sec 3.3.1 - // and tables 7 on pages 73-74) - // SRAM1 is 128k at 0x20000000; - // SRAM2 is 32k mapped at 0x10000000 (sec 2.4.2, table 3-4, - // page 68, also fig 2 on page 63) - .sram_size = 0x20000, - .bootrom_base = 0x1fff0000, // Tables 6, pages 71-72 (Bank 1 system - // memory, also fig 2 on page 63) - .bootrom_size = 0x7000, // 28k (per bank), same source as base - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32L0xx Category 1 - // RM0451, RM0377 - .chip_id = STLINK_CHIPID_STM32_L011, - .description = "L01x/L02x", - .flash_type = STLINK_FLASH_TYPE_L0, - .flash_size_reg = 0x1ff8007c, - .flash_pagesize = 0x80, - .sram_size = 0x2000, - .bootrom_base = 0x1ff00000, - .bootrom_size = 0x2000, - }, - { - // STM32G030/031/041 - // RM0454, RM0444 - .chip_id = STLINK_CHIPID_STM32_G0_CAT1, - .description = "G03x/G04x", - .flash_type = STLINK_FLASH_TYPE_G0, - .flash_size_reg = 0x1FFF75E0, // Section 38.2 - .flash_pagesize = 0x800, // 2k (sec 3.2) - .sram_size = 0x2000, // 8k (sec 2.3) - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x2000, // 8k (sec 2.2.2 table 3) - .option_base = STM32_G0_OPTION_BYTES_BASE, - .option_size = 4, - }, - { - // STM32G071/081 - // RM0444 - .chip_id = STLINK_CHIPID_STM32_G0_CAT2, - .description = "G07x/G08x", - .flash_type = STLINK_FLASH_TYPE_G0, - .flash_size_reg = 0x1FFF75E0, // Section 38.2 - .flash_pagesize = 0x800, // 2k (sec 3.2) - .sram_size = 0x9000, // 36k (sec 2.3) - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7000, // 28k (sec 2.2.2 table 2) - .option_base = STM32_G0_OPTION_BYTES_BASE, - .option_size = 4, - }, - { - // STM32G0B1/G0C1 - // RM0444 - .chip_id = STLINK_CHIPID_STM32_G0_CAT3, - .description = "G0Bx/G0Cx", - .flash_type = STLINK_FLASH_TYPE_G0, - .flash_size_reg = 0x1FFF75E0, // Section 38.2 - .flash_pagesize = 0x800, // 2k (sec 3.2) - .sram_size = 0x9000, // 36k (sec 2.3) - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7000, // 28k (sec 2.2.2 table 2) - .option_base = STM32_G0_OPTION_BYTES_BASE, - .option_size = 4, - .flags = CHIP_F_HAS_DUAL_BANK, - }, - { - // STM32G051/G061 - // RM0444 - .chip_id = STLINK_CHIPID_STM32_G0_CAT4, - .description = "G05x/G06x", - .flash_type = STLINK_FLASH_TYPE_G0, - .flash_size_reg = 0x1FFF75E0, // Section 38.2 - .flash_pagesize = 0x800, // 2k (sec 3.2) - .sram_size = 0x9000, // 36k (sec 2.3) - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7000, // 28k (sec 2.2.2 table 2) - .option_base = STM32_G0_OPTION_BYTES_BASE, - .option_size = 4, - }, - { - // STM32G431/441 - // RM0440 - .chip_id = STLINK_CHIPID_STM32_G4_CAT2, - .description = "G43x/G44x", - .flash_type = STLINK_FLASH_TYPE_G4, - .flash_size_reg = 0x1FFF75E0, // Section 47.2 - .flash_pagesize = 0x800, // 2k (sec 3.3.1) - // SRAM1 is 16k at 0x20000000 - // SRAM2 is 6k at 0x20014000 - // SRAM3/CCM is 10k at 0x10000000, aliased at 0x20018000 - .sram_size = 0x8000, // 32k (sec 2.4) - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7000, // 28k (table 2) - .option_base = STM32_G4_OPTION_BYTES_BASE, - .option_size = 4, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32G471/473/474/483/484 - // RM0440 - .chip_id = STLINK_CHIPID_STM32_G4_CAT3, - .description = "G47x/G48x", - .flash_type = STLINK_FLASH_TYPE_G4, - .flash_size_reg = 0x1FFF75E0, // Section 47.2 - .flash_pagesize = 0x800, // 2k (sec 3.3.1) - // SRAM1 is 80k at 0x20000000 - // SRAM2 is 16k at 0x20014000 - // SRAM3/CCM is 32k at 0x10000000, aliased at 0x20018000 - .sram_size = 0x20000, // 128k (sec 2.4) - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7000, // 28k (table 2) - .option_base = STM32_G4_OPTION_BYTES_BASE, - .option_size = 4, - .flags = CHIP_F_HAS_DUAL_BANK | CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32G491/G4A1 - // RM0440 - .chip_id = STLINK_CHIPID_STM32_G4_CAT4, - .description = "G49x/G4Ax", - .flash_type = STLINK_FLASH_TYPE_G4, - .flash_size_reg = 0x1FFF75E0, // Section 47.2 - .flash_pagesize = 0x800, // 2k (sec 3.3.1) - // SRAM1 is 80k at 0x20000000 - // SRAM2 is 16k at 0x20014000 - // SRAM3/CCM is 32k at 0x10000000, aliased at 0x20018000 - .sram_size = 0x1C000, // 112k (sec 2.4) - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7000, // 28k (table 2) - .option_base = STM32_G4_OPTION_BYTES_BASE, - .option_size = 4, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32WB55xx, STM32WB35xx, STM32WB50CG/30CE - // RM0434, RM0471 - .chip_id = STLINK_CHIPID_STM32_WB55, - .description = "WB5x/3x", - .flash_type = STLINK_FLASH_TYPE_WB, - .flash_size_reg = 0x1FFF75E0, - .flash_pagesize = 0x1000, // 4k - .sram_size = 0x40000, - .bootrom_base = 0x1fff0000, // see the memory map - .bootrom_size = 0x7000, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32WLEx - .chip_id = STLINK_CHIPID_STM32_WLE, - .description = "WLEx", - .flash_type = STLINK_FLASH_TYPE_WB, - .flash_size_reg = 0x1FFF75E0, - .flash_pagesize = 0x800, // 2k - .sram_size = 0x10000, - .bootrom_base = 0x1fff0000, // see the memory map - .bootrom_size = 0x7000, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32H742/743/753 (from RM0433) - .chip_id = STLINK_CHIPID_STM32_H74xxx, - .description = "H74x/H75x", - .flash_type = STLINK_FLASH_TYPE_H7, - .flash_size_reg = 0x1ff1e880, // "Flash size register" (pg3272) - .flash_pagesize = 0x20000, // 128k sector (pg147) - .sram_size = 0x20000, // 128k "DTCM" from Table 7 - .bootrom_base = 0x1ff00000, // "System memory" starting address from Table 7 - .bootrom_size = 0x20000, // "System memory" byte size in hex from Table 7 - .option_base = STM32_H7_OPTION_BYTES_BASE, - .option_size = 44, // FLASH_OPTSR_CUR to FLASH_BOOT_PRGR from Table 28 - .flags = CHIP_F_HAS_DUAL_BANK | CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32H7A3/7B3 - // RM0455 - .chip_id = STLINK_CHIPID_STM32_H7Ax, - .description = "H7Ax/H7Bx", - .flash_type = STLINK_FLASH_TYPE_H7, - .flash_size_reg = 0x08FFF80C, // "Flash size register" (p.2949) - .flash_pagesize = 0x2000, // 8k sector (p.146) - .sram_size = 0x20000, // 128k "DTCM" (Figure 1) - .bootrom_base = 0x1FF00000, // "System memory" starting address (Table 12-14) - .bootrom_size = 0x20000, // "System memory" byte size in hex splitted to - // two banks (Table 12-14) - .option_base = STM32_H7_OPTION_BYTES_BASE, - .option_size = 44, - .flags = CHIP_F_HAS_DUAL_BANK | CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32H72x/H73x - // RM0468 - .chip_id = STLINK_CHIPID_STM32_H72x, - .description = "H72x/H73x", - .flash_type = STLINK_FLASH_TYPE_H7, - .flash_size_reg = 0x1FF1E880, // "Flash size register" (p.3286) - .flash_pagesize = 0x20000, // 128k sector (p.152) - .sram_size = 0x20000, // 128k "DTCM" (Figure 1) - .bootrom_base = 0x1FF00000, // "System memory" starting address (Table 6) - .bootrom_size = 0x20000, // "System memory" byte size in hex (Table 6) - .option_base = STM32_H7_OPTION_BYTES_BASE, - .option_size = 44, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - - { - // unknown - .chip_id = STLINK_CHIPID_UNKNOWN, - .description = "unknown device", - .flash_type = STLINK_FLASH_TYPE_UNKNOWN, - .flash_size_reg = 0x0, - .flash_pagesize = 0x0, - .sram_size = 0x0, - .bootrom_base = 0x0, - .bootrom_size = 0x0, - }, -}; struct stlink_chipid_params *stlink_chipid_get_params_old(uint32_t chipid) { struct stlink_chipid_params *params = NULL; @@ -901,11 +24,12 @@ struct stlink_chipid_params *stlink_chipid_get_params_old(uint32_t chipid) { static struct stlink_chipid_params *devicelist; void dump_a_chip (FILE *fp, struct stlink_chipid_params *dev) { - fprintf(fp, "# Chip-ID file for %s\n", dev->description); + fprintf(fp, "# Device Type: %s\n", dev->dev_type); + fprintf(fp, "# Reference Manual: RM%s\n", dev->ref_manual_id); fprintf(fp, "#\n"); fprintf(fp, "chip_id 0x%x\n", dev->chip_id); - fprintf(fp, "description %s\n", dev->description); fprintf(fp, "flash_type %d\n", dev->flash_type); + fprintf(fp, "flash_size_reg %x\n", dev->flash_size_reg); fprintf(fp, "flash_pagesize 0x%x\n", dev->flash_pagesize); fprintf(fp, "sram_size 0x%x\n", dev->sram_size); fprintf(fp, "bootrom_base 0x%x\n", dev->bootrom_base); @@ -919,7 +43,6 @@ struct stlink_chipid_params *stlink_chipid_get_params(uint32_t chipid) { struct stlink_chipid_params *params = NULL; struct stlink_chipid_params *p2; - //fprintf (stderr, "getparams: %x\n", chipid); for (params = devicelist; params != NULL; params = params->next) if (params->chip_id == chipid) { break; @@ -949,7 +72,7 @@ void process_chipfile(char *fname) { struct stlink_chipid_params *ts; int nc; - // fprintf (stderr, "processing chipfile %s.\n", fname); + // fprintf (stderr, "processing chip-id file %s.\n", fname); fp = fopen(fname, "r"); if (!fp) { @@ -963,28 +86,33 @@ void process_chipfile(char *fname) { for (p = buf; isspace (*p); p++); if (!*p) { - continue; // we hit end-of-line wiht only whitespace + continue; // we hit end-of-line with only whitespace } if (*p == '#') { - continue; // ignore comments. + continue; // ignore comments } sscanf(p, "%s %s", word, value); - if (strcmp(word, "chip_id") == 0) { - if (sscanf(value, "%i", &ts->chip_id) < 1) { - fprintf(stderr, "Failed to parse chip id\n"); - } - } else if (strcmp (word, "description") == 0) { - // ts->description = strdup (value); + if (strcmp (word, "dev_type") == 0) { + // ts->dev_type = strdup (value); buf[strlen(p) - 1] = 0; // chomp newline sscanf(p, "%*s %n", &nc); - ts->description = strdup(p + nc); + ts->dev_type = strdup(p + nc); + } else if (strcmp (word, "ref_manual_id") == 0) { + // ts->ref_manual_id = strdup (value); + buf[strlen(p) - 1] = 0; // chomp newline + sscanf(p, "%*s %n", &nc); + ts->ref_manual_id = strdup(p + nc); + } else if (strcmp(word, "chip_id") == 0) { + if (sscanf(value, "%i", &ts->chip_id) < 1) { + fprintf(stderr, "Failed to parse chip-id\n"); + } } else if (strcmp (word, "flash_type") == 0) { if (sscanf(value, "%i", (int *)&ts->flash_type) < 1) { fprintf(stderr, "Failed to parse flash type\n"); - } else if (ts->flash_type <= STLINK_FLASH_TYPE_UNKNOWN || ts->flash_type >= STLINK_FLASH_TYPE_MAX) { + } else if ((ts->flash_type < STLINK_FLASH_TYPE_UNKNOWN) || (ts->flash_type >= STLINK_FLASH_TYPE_MAX)) { fprintf(stderr, "Unrecognized flash type\n"); } } else if (strcmp (word, "flash_size_reg") == 0) { @@ -1050,18 +178,19 @@ void dump_chips (void) { for (size_t n = 0; n < STLINK_ARRAY_SIZE(devices); n++) { ts = &devices[n]; - strcpy(buf, ts->description); + strcpy(buf, ts->dev_type); while ((p = strchr(buf, '/'))) // change slashes to underscore. *p = '_'; strcat(buf, ".chip"); fp = fopen(buf, "w"); - fprintf(fp, "# Chip-ID file for %s\n", ts->description); + fprintf(fp, "# Device Type: %s\n", ts->dev_type); + fprintf(fp, "# Reference Manual: RM%s\n", ts->ref_manual_id); fprintf(fp, "#\n"); fprintf(fp, "chip_id %x\n", ts->chip_id); - fprintf(fp, "description %s\n", ts->description); fprintf(fp, "flash_type %x\n", ts->flash_type); + fprintf(fp, "flash_size_reg %x\n", ts->flash_size_reg); fprintf(fp, "flash_pagesize %x\n", ts->flash_pagesize); fprintf(fp, "sram_size %x\n", ts->sram_size); fprintf(fp, "bootrom_base %x\n", ts->bootrom_base); @@ -1104,23 +233,6 @@ void init_chipids(char *dir_to_scan) { perror (dir_to_scan); return; // XXX } - -#if 0 - { - struct stlink_chipid_params *p, *op; - int i; - p = devicelist; - - for (i = 0; i < 5; i++, p = p->next) { - op = stlink_chipid_get_params_old (p->chip_id); - fprintf (stderr, "---------- old ------------\n"); - dump_a_chip (stderr, op); - fprintf (stderr, "---------- new ------------\n"); - dump_a_chip (stderr, p); - - } - } -#endif } #endif //STLINK_HAVE_DIRENT_H diff --git a/src/stlink-lib/chipid.h b/src/stlink-lib/chipid.h index 20cfcf52d..426c22428 100644 --- a/src/stlink-lib/chipid.h +++ b/src/stlink-lib/chipid.h @@ -79,8 +79,9 @@ enum stlink_stm32_chipids { /** Chipid parameters */ struct stlink_chipid_params { + char *dev_type; + char *ref_manual_id; uint32_t chip_id; - char *description; enum stlink_flash_type flash_type; uint32_t flash_size_reg; uint32_t flash_pagesize; @@ -93,7 +94,6 @@ struct stlink_chipid_params { struct stlink_chipid_params * next; }; - struct stlink_chipid_params *stlink_chipid_get_params(uint32_t chipid); void init_chipids(char *dir_to_scan); diff --git a/src/stlink-lib/chipid_db_old.h b/src/stlink-lib/chipid_db_old.h new file mode 100644 index 000000000..bc6491ad4 --- /dev/null +++ b/src/stlink-lib/chipid_db_old.h @@ -0,0 +1,879 @@ +// This is the old chipid "database". +// It is kept here for now to be able to compare the +// result between the "old code" and the "new code". +// For now if you need to change something, please +// change it both here and in the corresponding +// config/chips/*.chip file. + +static struct stlink_chipid_params devices[] = { + { + // STM32F76x/F77x + // RM0410 + .chip_id = STLINK_CHIPID_STM32_F76xxx, + .dev_type = "F76x/F77x", + .flash_type = STLINK_FLASH_TYPE_F7, + .flash_size_reg = 0x1ff0f442, // section 45.2 + .flash_pagesize = 0x800, // No flash pages + .sram_size = 0x80000, // "SRAM" byte size in hex from + .bootrom_base = 0x00200000, // "System memory" starting address from + .bootrom_size = 0xEDC0, + .option_base = STM32_F7_OPTION_BYTES_BASE, /* Used for reading back the option + bytes, writing uses FLASH_F7_OPTCR + and FLASH_F7_OPTCR1 */ + .option_size = 0x20, + .flags = CHIP_F_HAS_DUAL_BANK | CHIP_F_HAS_SWO_TRACING, + }, + { + // STM32F74x/F75x + // RM0385, DS10916 + .chip_id = STLINK_CHIPID_STM32_F7, + .dev_type = "F74x/F75x", + .flash_type = STLINK_FLASH_TYPE_F4, + .flash_size_reg = 0x1ff0f442, // section 41.2 + .flash_pagesize = 0x800, // No flash pages + .sram_size = 0x50000, // "SRAM" byte size in hex from DS Fig 18 + .bootrom_base = 0x00100000, // "System memory" starting address from DS Fig 18 + .bootrom_size = 0xEDC0, // "System memory" byte size in hex from DS Fig 18 + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + // STM32F72x/F73x + // RM0431 + .chip_id = STLINK_CHIPID_STM32_F72xxx, + .dev_type = "F72x/F73x", + .flash_type = STLINK_FLASH_TYPE_F4, + .flash_size_reg = 0x1ff07a22, // section 35.2 + .flash_pagesize = 0x800, // No flash pages + .sram_size = 0x40000, // "SRAM" byte size in hex from DS Fig 24 + .bootrom_base = 0x00100000, // "System memory" starting address from DS Fig 24 + .bootrom_size = 0xEDC0, // "System memory" byte size in hex from DS Fig 24 + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + // STM32F4x5/F4x7 + // RM0090 (rev 2) + .chip_id = STLINK_CHIPID_STM32_F4, + .dev_type = "F4x5/F4x7", + .flash_type = STLINK_FLASH_TYPE_F4, + .flash_size_reg = 0x1FFF7A22, + .flash_pagesize = 0x4000, + .sram_size = 0x30000, + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x7800, + .option_base = STM32_F4_OPTION_BYTES_BASE, + .option_size = 4, + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + // STM32F46x/F47x + // RM0090 (rev 2) + .chip_id = STLINK_CHIPID_STM32_F4_DSI, + .dev_type = "F46x/F47x", + .flash_type = STLINK_FLASH_TYPE_F4, + .flash_size_reg = 0x1FFF7A22, + .flash_pagesize = 0x4000, + .sram_size = 0x40000, + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x7800, + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + // STM32F42x/F43x + // RM0090 (rev 2) + .chip_id = STLINK_CHIPID_STM32_F4_HD, + .dev_type = "F42x/F43x", + .flash_type = STLINK_FLASH_TYPE_F4, + .flash_size_reg = 0x1FFF7A22, + .flash_pagesize = 0x4000, + .sram_size = 0x40000, + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x7800, + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + .chip_id = STLINK_CHIPID_STM32_F4_LP, + .dev_type = "F401xB/C", + .flash_type = STLINK_FLASH_TYPE_F4, + .flash_size_reg = 0x1FFF7A22, + .flash_pagesize = 0x4000, + .sram_size = 0x10000, + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x7800, + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + .chip_id = STLINK_CHIPID_STM32_F411xx, + .dev_type = "F411xC/E", + .flash_type = STLINK_FLASH_TYPE_F4, + .flash_size_reg = 0x1FFF7A22, + .flash_pagesize = 0x4000, + .sram_size = 0x20000, + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x7800, + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + .chip_id = STLINK_CHIPID_STM32_F4_DE, + .dev_type = "F401xD/E", + .flash_type = STLINK_FLASH_TYPE_F4, + .flash_size_reg = 0x1FFF7A22, + .flash_pagesize = 0x4000, + .sram_size = 0x18000, + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x7800, + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + // STM32L100/L15x/L16x Cat.1 + // RM0038 + .chip_id = STLINK_CHIPID_STM32_L1_MD, + .dev_type = "L1xx Cat.1", + .flash_type = STLINK_FLASH_TYPE_L0, + .flash_size_reg = 0x1ff8004c, + .flash_pagesize = 0x100, + .sram_size = 0x4000, // up to 16k + .bootrom_base = 0x1ff00000, + .bootrom_size = 0x1000, + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + // STM32L100/L15x/L16x Cat.2 + // RM0038 + .chip_id = STLINK_CHIPID_STM32_L1_CAT2, + .dev_type = "L1xx Cat.2", + .flash_type = STLINK_FLASH_TYPE_L0, + .flash_size_reg = 0x1ff8004c, + .flash_pagesize = 0x100, + .sram_size = 0x8000, // up to 32k + .bootrom_base = 0x1ff00000, + .bootrom_size = 0x1000, + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + // STM32L100/L15x/L16x Cat.3 + // RM0038 + .chip_id = STLINK_CHIPID_STM32_L1_MD_PLUS, + .dev_type = "L1xx Cat.3", + .flash_type = STLINK_FLASH_TYPE_L0, + .flash_size_reg = 0x1ff800cc, + .flash_pagesize = 0x100, + .sram_size = 0x8000, // up to 32k + .bootrom_base = 0x1ff00000, + .bootrom_size = 0x1000, + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + // STM32L100/L15x/L16x Cat.4 + // RM0038 + .chip_id = STLINK_CHIPID_STM32_L1_MD_PLUS_HD, + .dev_type = "L1xx Cat.4", + .flash_type = STLINK_FLASH_TYPE_L0, + .flash_size_reg = 0x1ff800cc, + .flash_pagesize = 0x100, + .sram_size = 0xC000, // up to 48k + .bootrom_base = 0x1ff00000, + .bootrom_size = 0x1000, + .option_base = STM32_L1_OPTION_BYTES_BASE, + .option_size = 8, + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + // STM32L100/L15x/L16x Cat.5 + // RM0038 + .chip_id = STLINK_CHIPID_STM32_L152_RE, + .dev_type = "L1xx Cat.5", + .flash_type = STLINK_FLASH_TYPE_L0, + .flash_size_reg = 0x1ff800cc, + .flash_pagesize = 0x100, + .sram_size = 0x14000, // up to 80k + .bootrom_base = 0x1ff00000, + .bootrom_size = 0x1000, + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + // STM32F446x family + // RM0390 + .chip_id = STLINK_CHIPID_STM32_F446, + .dev_type = "F446", + .flash_type = STLINK_FLASH_TYPE_F4, + .flash_size_reg = 0x1fff7a22, + .flash_pagesize = 0x20000, + .sram_size = 0x20000, + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x7800, + .option_base = 0x1FFFC000, + .option_size = 4, + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + // STM32F410 + // RM0401 + .chip_id = STLINK_CHIPID_STM32_F410, + .dev_type = "F410", + .flash_type = STLINK_FLASH_TYPE_F4, + .flash_size_reg = 0x1fff7a22, + .flash_pagesize = 0x4000, + .sram_size = 0x8000, + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x7800, + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + // STM32F303xB/C, STM32F358, STM32F302xBxC + // RM0316, RM0365 + .chip_id = STLINK_CHIPID_STM32_F3, + .dev_type = "F302/F303/F358", + .flash_type = STLINK_FLASH_TYPE_F0, + .flash_size_reg = 0x1ffff7cc, + .flash_pagesize = 0x800, + .sram_size = 0xa000, + .bootrom_base = 0x1ffff000, + .bootrom_size = 0x800, + .option_base = STM32_F0_OPTION_BYTES_BASE, + .option_size = 16, + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + // STM32F373Cx/Rx/Vx, STM32F378Cx/Rx/Vx + // RM0313 + .chip_id = STLINK_CHIPID_STM32_F37x, + .dev_type = "F37x", + .flash_type = STLINK_FLASH_TYPE_F0, + .flash_size_reg = 0x1ffff7cc, + .flash_pagesize = 0x800, + .sram_size = 0xa000, + .bootrom_base = 0x1ffff000, + .bootrom_size = 0x800, + .option_base = STM32_F0_OPTION_BYTES_BASE, + .option_size = 16, + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + // STM32F07x + // RM0091 + .chip_id = STLINK_CHIPID_STM32_F0_CAN, + .dev_type = "F07x", + .flash_type = STLINK_FLASH_TYPE_F0, + .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) + .flash_pagesize = 0x800, // Page sizes listed in Table 4 + .sram_size = 0x4000, // "SRAM" byte size in hex from Table 2 + .bootrom_base = 0x1fffC800, // "System memory" starting address from Table 2 + .bootrom_size = 0x3000, // "System memory" byte size in hex from Table 2 + .option_base = STM32_F0_OPTION_BYTES_BASE, + .option_size = 16, + }, + { + // STM32F05x + // RM0091 + .chip_id = STLINK_CHIPID_STM32_F0, + .dev_type = "F05x", + .flash_type = STLINK_FLASH_TYPE_F0, + .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) + .flash_pagesize = 0x400, // Page sizes listed in Table 4 + .sram_size = 0x2000, // "SRAM" byte size in hex from Table 2 + .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2 + .bootrom_size = 0xC00, // "System memory" byte size in hex from Table 2 + .option_base = STM32_F0_OPTION_BYTES_BASE, + .option_size = 16, + }, + { + // STM32F412 + // RM0402 + .chip_id = STLINK_CHIPID_STM32_F412, + .dev_type = "F412", + .flash_type = STLINK_FLASH_TYPE_F4, + .flash_size_reg = 0x1FFF7A22, // "Flash size data register" (pg1135) + .flash_pagesize = 0x4000, // Table 5. Flash module organization ? + .sram_size = 0x40000, // "SRAM" byte size in hex from Table 4 + .bootrom_base = 0x1FFF0000, // "System memory" starting address from Table 4 + .bootrom_size = 0x7800, // "System memory" byte size in hex from Table 4 + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + // STM32F413/F423 + // RM0430 (rev 2) + .chip_id = STLINK_CHIPID_STM32_F413, + .dev_type = "F413/F423", + .flash_type = STLINK_FLASH_TYPE_F4, + .flash_size_reg = 0x1FFF7A22, // "Flash size data register" Section 35.2 + .flash_pagesize = 0x4000, // Table 5. Flash module organization (variable sector + // sizes, but 0x4000 is smallest) + .sram_size = 0x50000, // "SRAM" byte size in hex from Figure 2 (Table 4 + // only says 0x40000) + .bootrom_base = 0x1FFF0000, // "System memory" starting address from Table 4 + .bootrom_size = 0x7800, // "System memory" byte size in hex from Table 4 + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + // STM32F09x + // RM0091 + .chip_id = STLINK_CHIPID_STM32_F09x, + .dev_type = "F09x", + .flash_type = STLINK_FLASH_TYPE_F0, + .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) + .flash_pagesize = 0x800, // Page sizes listed in Table 4 (pg 56) + .sram_size = 0x8000, // "SRAM" byte size in hex from Table 2 (pg 50) + .bootrom_base = 0x1fffd800, // "System memory" starting address from Table 2 + .bootrom_size = 0x2000, // "System memory" byte size in hex from Table 2 + .option_base = STM32_F0_OPTION_BYTES_BASE, + .option_size = 16, + }, + { + // STM32F04x + // RM0091 + .chip_id = STLINK_CHIPID_STM32_F04, + .dev_type = "F04x", + .flash_type = STLINK_FLASH_TYPE_F0, + .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) + .flash_pagesize = 0x400, // Page sizes listed in Table 4 + .sram_size = 0x1800, // "SRAM" byte size in hex from Table 2 + .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2 + .bootrom_size = 0xC00, // "System memory" byte size in hex from Table 2 + .option_base = STM32_F0_OPTION_BYTES_BASE, + .option_size = 16, + }, + { + // STM32F03x + // RM0091 + .chip_id = STLINK_CHIPID_STM32_F0xx_SMALL, + .dev_type = "F03x", + .flash_type = STLINK_FLASH_TYPE_F0, + .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) + .flash_pagesize = 0x400, // Page sizes listed in Table 4 + .sram_size = 0x1000, // "SRAM" byte size in hex from Table 2 + .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2 + .bootrom_size = 0xC00, // "System memory" byte size in hex from Table 2 + .option_base = STM32_F0_OPTION_BYTES_BASE, + .option_size = 16, + }, + { + // STM32F301x6/8, STM32F302x6x8, STM32F318x8 + // RM0366, RM0365 + .chip_id = STLINK_CHIPID_STM32_F3xx_SMALL, + .dev_type = "F301/F302/F318", + .flash_type = STLINK_FLASH_TYPE_F0, + .flash_size_reg = 0x1ffff7cc, + .flash_pagesize = 0x800, + .sram_size = 0xa000, + .bootrom_base = 0x1fffd800, + .bootrom_size = 0x2000, + .option_base = STM32_F0_OPTION_BYTES_BASE, + .option_size = 16, + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + // STM32L0xx Category 3 + // RM0367, RM0377, RM0451 + .chip_id = STLINK_CHIPID_STM32_L0, + .dev_type = "L0xx Cat.3", + .flash_type = STLINK_FLASH_TYPE_L0, + .flash_size_reg = 0x1ff8007c, + .flash_pagesize = 0x80, + .sram_size = 0x2000, + .bootrom_base = 0x1ff0000, + .bootrom_size = 0x1000, + .option_base = STM32_L0_OPTION_BYTES_BASE, + .option_size = 20, + }, + { + // STM32L0x Category 5 + // RM0367, RM0377, RM0451 + .chip_id = STLINK_CHIPID_STM32_L0_CAT5, + .dev_type = "L0xx Cat.5", + .flash_type = STLINK_FLASH_TYPE_L0, + .flash_size_reg = 0x1ff8007c, + .flash_pagesize = 0x80, + .sram_size = 0x5000, + .bootrom_base = 0x1ff0000, + .bootrom_size = 0x2000, + .option_base = STM32_L0_OPTION_BYTES_BASE, + .option_size = 20, + .flags = CHIP_F_HAS_DUAL_BANK, + }, + { + // STM32L0x Category 2 + // RM0367, RM0377 + .chip_id = STLINK_CHIPID_STM32_L0_CAT2, + .dev_type = "L0xx Cat.2", + .flash_type = STLINK_FLASH_TYPE_L0, + .flash_size_reg = 0x1ff8007c, + .flash_pagesize = 0x80, + .sram_size = 0x2000, + .bootrom_base = 0x1ff0000, + .bootrom_size = 0x1000, + .option_base = STM32_L0_OPTION_BYTES_BASE, + .option_size = 20, + }, + { + // STM32F334, STM32F303x6/8, STM32F328 + // RM0364, RM0316 + .chip_id = STLINK_CHIPID_STM32_F334, + .dev_type = "F303/F328/F334", // (RM0316 sec 33.6.1) + .flash_type = STLINK_FLASH_TYPE_F0, + .flash_size_reg = 0x1ffff7cc, + .flash_pagesize = 0x800, + .sram_size = 0x3000, + .bootrom_base = 0x1fffd800, + .bootrom_size = 0x2000, + .option_base = STM32_F0_OPTION_BYTES_BASE, + .option_size = 16, + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + // STM32F303xD/E, STM32F398xE, STM32F302xD/E + // RM0316 (rev 5), RM0365 + .chip_id = STLINK_CHIPID_STM32_F303_HD, + .dev_type = "F303 high density", + .flash_type = STLINK_FLASH_TYPE_F0, + .flash_size_reg = 0x1ffff7cc, // 34.2.1 Flash size data register + .flash_pagesize = 0x800, // 4.2.1 Flash memory organization + .sram_size = 0x10000, // 3.3 Embedded SRAM + .bootrom_base = 0x1fffd800, // 3.3.2 / Table 4 System Memory + .bootrom_size = 0x2000, + .option_base = STM32_F0_OPTION_BYTES_BASE, + .option_size = 16, + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + // STM32L47x/L48x + // RM0351 + .chip_id = STLINK_CHIPID_STM32_L4, + .dev_type = "L47x/L48x", + .flash_type = STLINK_FLASH_TYPE_L4, + .flash_size_reg = 0x1FFF75e0, // "Flash size data register" (sec 45.2, page 1671) + .flash_pagesize = 0x800, // 2k (sec 3.2, page 78; also appears in sec 3.3.1 + // and tables 4-6 on pages 79-81) + // SRAM1 is "up to" 96k in the standard Cortex-M memory map; + // SRAM2 is 32k mapped at at 0x10000000 (sec 2.3, page 73 for + // sizes; table 2, page 74 for SRAM2 location) + .sram_size = 0x18000, + .bootrom_base = 0x1fff0000, // Tables 4-6, pages 80-81 (Bank 1 system memory) + .bootrom_size = 0x7000, // 28k (per bank), same source as base + .option_base = STM32_L4_OPTION_BYTES_BASE, + .option_size = 4, + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + // STM32L4RX + // RM0432 + .chip_id = STLINK_CHIPID_STM32_L4Rx, + .dev_type = "L4Rx", + .flash_type = STLINK_FLASH_TYPE_L4, + .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 58.2, page 2274) + .flash_pagesize = 0x1000, // 4k, section 3.3, pg 117-120 + // TODO: flash_pagesize can be 8k depend on the dual-bank mode and flash size + .sram_size = 0xa0000, // 192k (SRAM1) + 64k SRAM2 + 384k SRAM3 = 640k, or 0xA0000 + .bootrom_base = 0x1fff0000, // 3.3.1, pg 117 + .bootrom_size = 0x7000, // 28k (per bank), same source as base (pg 117) + .flags = CHIP_F_HAS_DUAL_BANK | CHIP_F_HAS_SWO_TRACING, + }, + { + // STM32L4PX + // RM0432 + .chip_id = STLINK_CHIPID_STM32_L4PX, + .dev_type = "L4Px", + .flash_type = STLINK_FLASH_TYPE_L4, + .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 58.2, page 2274) + .flash_pagesize = 0x1000, // 4k, section 3.3, pg 117-120 + // TODO: flash_pagesize can be 8k depend on the dual-bank mode and flash size + .sram_size = 0xa0000, // 192k (SRAM1) + 64k SRAM2 + 384k SRAM3 = 640k, or 0xA0000 + .bootrom_base = 0x1fff0000, // 3.3.1, pg 117 + .bootrom_size = 0x7000, // 28k (per bank), same source as base (pg 117) + .flags = CHIP_F_HAS_DUAL_BANK | CHIP_F_HAS_SWO_TRACING, + }, + { + // STLINK_CHIPID_STM32_L41x_L42x + // RM0394 (rev 4), DS12469 (rev 5) + .chip_id = STLINK_CHIPID_STM32_L41x_L42x, + .dev_type = "L41x/L42x", + .flash_type = STLINK_FLASH_TYPE_L4, + .flash_size_reg = 0x1fff75e0, // "Flash size data register" (RM0394, + // sec 47.2, page 1586) + .flash_pagesize = 0x800, // 2k (DS12469, sec 3.4, page 17) + // SRAM1 is 32k at 0x20000000 + // SRAM2 is 8k at 0x10000000 and 0x20008000 + // (DS12469, sec 3.5, page 18) + .sram_size = 0xa000, // 40k (DS12469, sec 3.5, page 18) + .bootrom_base = 0x1fff0000, // System Memory (RM0394, sec 3.3.1, table 8) + .bootrom_size = 0x7000, // 28k, same source as base + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + // STLINK_CHIPID_STM32_L43x_L44x + // RM0392 + .chip_id = STLINK_CHIPID_STM32_L43x_L44x, + .dev_type = "L43x/L44x", + .flash_type = STLINK_FLASH_TYPE_L4, + .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 43.2, page 1410) + .flash_pagesize = 0x800, // 2k (sec 3.2, page 74; also appears in sec 3.3.1 + // and tables 7-8 on pages 75-76) + // SRAM1 is "up to" 64k in the standard Cortex-M memory map; + // SRAM2 is 16k mapped at 0x10000000 (sec 2.3, page 73 for + // sizes; table 2, page 74 for SRAM2 location) + .sram_size = 0xc000, + .bootrom_base = 0x1fff0000, // Tables 4-6, pages 80-81 (Bank 1 system memory) + .bootrom_size = 0x7000, // 28k (per bank), same source as base + .option_base = STM32_L4_OPTION_BYTES_BASE, + .option_size = 4, + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + // STLINK_CHIPID_STM32_L496x_L4A6x + // RM0351 (rev 5) + .chip_id = STLINK_CHIPID_STM32_L496x_L4A6x, + .dev_type = "L496x/L4A6x", + .flash_type = STLINK_FLASH_TYPE_L4, + .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 49.2, page 1809) + .flash_pagesize = 0x800, // Page erase (2 Kbyte) (sec 3.2, page 93) + // SRAM1 is 256k at 0x20000000 + // SRAM2 is 64k at 0x20040000 (sec 2.2.1, fig 2, page 74) + .sram_size = 0x40000, // Embedded SRAM (sec 2.4, page 84) + .bootrom_base = 0x1fff0000, // System Memory (Bank 1) (sec 3.3.1) + .bootrom_size = 0x7000, // 28k (per bank), same source as base + .option_base = STM32_L4_OPTION_BYTES_BASE, + .option_size = 4, + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + // STLINK_CHIPID_STM32_L45x_L46x + // RM0394 (updated version of RM0392?) + .chip_id = STLINK_CHIPID_STM32_L45x_L46x, + .dev_type = "L45x/46x", + .flash_type = STLINK_FLASH_TYPE_L4, + .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 45.2, page 1463) + .flash_pagesize = 0x800, // 2k (sec 3.2, page 73; also appears in sec 3.3.1 + // and tables 7 on pages 73-74) + // SRAM1 is 128k at 0x20000000; + // SRAM2 is 32k mapped at 0x10000000 (sec 2.4.2, table 3-4, + // page 68, also fig 2 on page 63) + .sram_size = 0x20000, + .bootrom_base = 0x1fff0000, // Tables 6, pages 71-72 (Bank 1 system + // memory, also fig 2 on page 63) + .bootrom_size = 0x7000, // 28k (per bank), same source as base + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + // STM32L0xx Category 1 + // RM0451, RM0377 + .chip_id = STLINK_CHIPID_STM32_L011, + .dev_type = "L01x/L02x", + .flash_type = STLINK_FLASH_TYPE_L0, + .flash_size_reg = 0x1ff8007c, + .flash_pagesize = 0x80, + .sram_size = 0x2000, + .bootrom_base = 0x1ff00000, + .bootrom_size = 0x2000, + }, + { + // STM32G030/031/041 + // RM0454, RM0444 + .chip_id = STLINK_CHIPID_STM32_G0_CAT1, + .dev_type = "G03x/G04x", + .flash_type = STLINK_FLASH_TYPE_G0, + .flash_size_reg = 0x1FFF75E0, // Section 38.2 + .flash_pagesize = 0x800, // 2k (sec 3.2) + .sram_size = 0x2000, // 8k (sec 2.3) + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x2000, // 8k (sec 2.2.2 table 3) + .option_base = STM32_G0_OPTION_BYTES_BASE, + .option_size = 4, + }, + { + // STM32G071/081 + // RM0444 + .chip_id = STLINK_CHIPID_STM32_G0_CAT2, + .dev_type = "G07x/G08x", + .flash_type = STLINK_FLASH_TYPE_G0, + .flash_size_reg = 0x1FFF75E0, // Section 38.2 + .flash_pagesize = 0x800, // 2k (sec 3.2) + .sram_size = 0x9000, // 36k (sec 2.3) + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x7000, // 28k (sec 2.2.2 table 2) + .option_base = STM32_G0_OPTION_BYTES_BASE, + .option_size = 4, + }, + { + // STM32G0B1/G0C1 + // RM0444 + .chip_id = STLINK_CHIPID_STM32_G0_CAT3, + .dev_type = "G0Bx/G0Cx", + .flash_type = STLINK_FLASH_TYPE_G0, + .flash_size_reg = 0x1FFF75E0, // Section 38.2 + .flash_pagesize = 0x800, // 2k (sec 3.2) + .sram_size = 0x9000, // 36k (sec 2.3) + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x7000, // 28k (sec 2.2.2 table 2) + .option_base = STM32_G0_OPTION_BYTES_BASE, + .option_size = 4, + .flags = CHIP_F_HAS_DUAL_BANK, + }, + { + // STM32G051/G061 + // RM0444 + .chip_id = STLINK_CHIPID_STM32_G0_CAT4, + .dev_type = "G05x/G06x", + .flash_type = STLINK_FLASH_TYPE_G0, + .flash_size_reg = 0x1FFF75E0, // Section 38.2 + .flash_pagesize = 0x800, // 2k (sec 3.2) + .sram_size = 0x9000, // 36k (sec 2.3) + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x7000, // 28k (sec 2.2.2 table 2) + .option_base = STM32_G0_OPTION_BYTES_BASE, + .option_size = 4, + }, + { + // STM32G431/441 + // RM0440 + .chip_id = STLINK_CHIPID_STM32_G4_CAT2, + .dev_type = "G43x/G44x", + .flash_type = STLINK_FLASH_TYPE_G4, + .flash_size_reg = 0x1FFF75E0, // Section 47.2 + .flash_pagesize = 0x800, // 2k (sec 3.3.1) + // SRAM1 is 16k at 0x20000000 + // SRAM2 is 6k at 0x20014000 + // SRAM3/CCM is 10k at 0x10000000, aliased at 0x20018000 + .sram_size = 0x8000, // 32k (sec 2.4) + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x7000, // 28k (table 2) + .option_base = STM32_G4_OPTION_BYTES_BASE, + .option_size = 4, + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + // STM32G471/473/474/483/484 + // RM0440 + .chip_id = STLINK_CHIPID_STM32_G4_CAT3, + .dev_type = "G47x/G48x", + .flash_type = STLINK_FLASH_TYPE_G4, + .flash_size_reg = 0x1FFF75E0, // Section 47.2 + .flash_pagesize = 0x800, // 2k (sec 3.3.1) + // SRAM1 is 80k at 0x20000000 + // SRAM2 is 16k at 0x20014000 + // SRAM3/CCM is 32k at 0x10000000, aliased at 0x20018000 + .sram_size = 0x20000, // 128k (sec 2.4) + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x7000, // 28k (table 2) + .option_base = STM32_G4_OPTION_BYTES_BASE, + .option_size = 4, + .flags = CHIP_F_HAS_DUAL_BANK | CHIP_F_HAS_SWO_TRACING, + }, + { + // STM32G491/G4A1 + // RM0440 + .chip_id = STLINK_CHIPID_STM32_G4_CAT4, + .dev_type = "G49x/G4Ax", + .flash_type = STLINK_FLASH_TYPE_G4, + .flash_size_reg = 0x1FFF75E0, // Section 47.2 + .flash_pagesize = 0x800, // 2k (sec 3.3.1) + // SRAM1 is 80k at 0x20000000 + // SRAM2 is 16k at 0x20014000 + // SRAM3/CCM is 32k at 0x10000000, aliased at 0x20018000 + .sram_size = 0x1C000, // 112k (sec 2.4) + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x7000, // 28k (table 2) + .option_base = STM32_G4_OPTION_BYTES_BASE, + .option_size = 4, + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + // STM32H742/743/753 (from RM0433) + .chip_id = STLINK_CHIPID_STM32_H74xxx, + .dev_type = "H74x/H75x", + .flash_type = STLINK_FLASH_TYPE_H7, + .flash_size_reg = 0x1ff1e880, // "Flash size register" (pg3272) + .flash_pagesize = 0x20000, // 128k sector (pg147) + .sram_size = 0x20000, // 128k "DTCM" from Table 7 + .bootrom_base = 0x1ff00000, // "System memory" starting address from Table 7 + .bootrom_size = 0x20000, // "System memory" byte size in hex from Table 7 + .option_base = STM32_H7_OPTION_BYTES_BASE, + .option_size = 44, // FLASH_OPTSR_CUR to FLASH_BOOT_PRGR from Table 28 + .flags = CHIP_F_HAS_DUAL_BANK | CHIP_F_HAS_SWO_TRACING, + }, + { + // STM32H7A3/7B3 + // RM0455 + .chip_id = STLINK_CHIPID_STM32_H7Ax, + .dev_type = "H7Ax/H7Bx", + .flash_type = STLINK_FLASH_TYPE_H7, + .flash_size_reg = 0x08FFF80C, // "Flash size register" (p.2949) + .flash_pagesize = 0x2000, // 8k sector (p.146) + .sram_size = 0x20000, // 128k "DTCM" (Figure 1) + .bootrom_base = 0x1FF00000, // "System memory" starting address (Table 12-14) + .bootrom_size = 0x20000, // "System memory" byte size in hex splitted to + // two banks (Table 12-14) + .option_base = STM32_H7_OPTION_BYTES_BASE, + .option_size = 44, + .flags = CHIP_F_HAS_DUAL_BANK | CHIP_F_HAS_SWO_TRACING, + }, + { + // STM32H72x/H73x + // RM0468 + .chip_id = STLINK_CHIPID_STM32_H72x, + .dev_type = "H72x/H73x", + .flash_type = STLINK_FLASH_TYPE_H7, + .flash_size_reg = 0x1FF1E880, // "Flash size register" (p.3286) + .flash_pagesize = 0x20000, // 128k sector (p.152) + .sram_size = 0x20000, // 128k "DTCM" (Figure 1) + .bootrom_base = 0x1FF00000, // "System memory" starting address (Table 6) + .bootrom_size = 0x20000, // "System memory" byte size in hex (Table 6) + .option_base = STM32_H7_OPTION_BYTES_BASE, + .option_size = 44, + .flags = CHIP_F_HAS_SWO_TRACING, + }, + + + { + // STM32F1xx medium-density devices + // RM0008 + .chip_id = STLINK_CHIPID_STM32_F1_MD, + .dev_type = "F1xx Medium-density", + .flash_type = STLINK_FLASH_TYPE_F0, + .flash_size_reg = 0x1ffff7e0, + .flash_pagesize = 0x400, + .sram_size = 0x5000, + .bootrom_base = 0x1ffff000, // 2.3.3 "Embedded Flash memory" + .bootrom_size = 0x800, + .option_base = STM32_F0_OPTION_BYTES_BASE, + .option_size = 16, + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + // STM32F205xx, STM32F207xx, STM32F215xx, STM32F217xx + // RM0033 (rev 5) + .chip_id = STLINK_CHIPID_STM32_F2, + .dev_type = "F2xx", + .flash_type = STLINK_FLASH_TYPE_F4, + .flash_size_reg = 0x1fff7a22, + .flash_pagesize = 0x20000, + .sram_size = 0x20000, + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x7800, + .option_base = 0x1FFFC000, + .option_size = 4, + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + // STM32F1xx low-density devices + // RM0008 + .chip_id = STLINK_CHIPID_STM32_F1_LD, + .dev_type = "F1 Low-density device", + .flash_type = STLINK_FLASH_TYPE_F0, + .flash_size_reg = 0x1ffff7e0, + .flash_pagesize = 0x400, + .sram_size = 0x2800, + .bootrom_base = 0x1ffff000, + .bootrom_size = 0x800, + .option_base = STM32_F0_OPTION_BYTES_BASE, + .option_size = 16, + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + // STM32F1xx high-density devices + // RM0008 + .chip_id = STLINK_CHIPID_STM32_F1_HD, + .dev_type = "F1xx High-density", + .flash_type = STLINK_FLASH_TYPE_F0, + .flash_size_reg = 0x1ffff7e0, + .flash_pagesize = 0x800, + .sram_size = 0x10000, + .bootrom_base = 0x1ffff000, + .bootrom_size = 0x800, + .option_base = STM32_F0_OPTION_BYTES_BASE, + .option_size = 16, + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + // STM32F1xx connectivity devices + // RM0008 + .chip_id = STLINK_CHIPID_STM32_F1_CONN, + .dev_type = "F1xx CL", + .flash_type = STLINK_FLASH_TYPE_F0, + .flash_size_reg = 0x1ffff7e0, + .flash_pagesize = 0x800, + .sram_size = 0x10000, + .bootrom_base = 0x1fffb000, + .bootrom_size = 0x4800, + .option_base = STM32_F0_OPTION_BYTES_BASE, + .option_size = 16, + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + // STM32F1xx low- and medium-density value line devices + // RM0041 + .chip_id = STLINK_CHIPID_STM32_F1_VL_MD_LD, + .dev_type = "F1xx Value Line", + .flash_type = STLINK_FLASH_TYPE_F0, + .flash_size_reg = 0x1ffff7e0, + .flash_pagesize = 0x400, + .sram_size = 0x2000, // 0x1000 for low density devices + .bootrom_base = 0x1ffff000, + .bootrom_size = 0x800, + .option_base = STM32_F0_OPTION_BYTES_BASE, + .option_size = 16, + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + // STM32F1xx high-density value line devices + // RM0041 + .chip_id = STLINK_CHIPID_STM32_F1_VL_HD, + .dev_type = "F1xx High-density value line", + .flash_type = STLINK_FLASH_TYPE_F0, + .flash_size_reg = 0x1ffff7e0, + .flash_pagesize = 0x800, + .sram_size = 0x8000, + .bootrom_base = 0x1ffff000, + .bootrom_size = 0x800, + .option_base = STM32_F0_OPTION_BYTES_BASE, + .option_size = 16, + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + // STM32F1xx XL-density devices + // RM0008 + .chip_id = STLINK_CHIPID_STM32_F1_XLD, + .dev_type = "F1xx XL-density", + .flash_type = STLINK_FLASH_TYPE_F1_XL, + .flash_size_reg = 0x1ffff7e0, + .flash_pagesize = 0x800, + .sram_size = 0x18000, + .bootrom_base = 0x1fffe000, + .bootrom_size = 0x1800, + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + // STM32WB55xx, STM32WB35xx, STM32WB50CG/30CE + // RM0434, RM0471 + .chip_id = STLINK_CHIPID_STM32_WB55, + .dev_type = "WB5x/3x", + .flash_type = STLINK_FLASH_TYPE_WB, + .flash_size_reg = 0x1FFF75E0, + .flash_pagesize = 0x1000, // 4k + .sram_size = 0x40000, + .bootrom_base = 0x1fff0000, // see the memory map + .bootrom_size = 0x7000, + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + // STM32WLEx + .chip_id = STLINK_CHIPID_STM32_WLE, + .dev_type = "WLEx", + .flash_type = STLINK_FLASH_TYPE_WB, + .flash_size_reg = 0x1FFF75E0, + .flash_pagesize = 0x800, // 2k + .sram_size = 0x10000, + .bootrom_base = 0x1fff0000, // see the memory map + .bootrom_size = 0x7000, + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + // unknown + .chip_id = STLINK_CHIPID_UNKNOWN, + .dev_type = "unknown device", + .flash_type = STLINK_FLASH_TYPE_UNKNOWN, + .flash_size_reg = 0x0, + .flash_pagesize = 0x0, + .sram_size = 0x0, + .bootrom_base = 0x0, + .bootrom_size = 0x0, + }, +}; \ No newline at end of file From 89f54e088417cacdf937f92e7a5e5f55728e03c7 Mon Sep 17 00:00:00 2001 From: hydroconstructor Date: Wed, 5 Jan 2022 13:51:47 +0400 Subject: [PATCH 333/503] Update usb.c --- src/stlink-lib/usb.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/stlink-lib/usb.c b/src/stlink-lib/usb.c index e07918800..793a1f68d 100644 --- a/src/stlink-lib/usb.c +++ b/src/stlink-lib/usb.c @@ -1221,6 +1221,8 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, enum connect_type connect, libusb_free_device_list(list, 1); +// libusb_kernel_driver_active is not available on Windows. +#if !defined(_WIN32) if (libusb_kernel_driver_active(slu->usb_handle, 0) == 1) { ret = libusb_detach_kernel_driver(slu->usb_handle, 0); @@ -1229,6 +1231,7 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, enum connect_type connect, goto on_libusb_error; } } +#endif if (libusb_get_configuration(slu->usb_handle, &config)) { // this may fail for a previous configured device From ab5c47b6cec32a3f0b80708cc8f2d7a1821dd512 Mon Sep 17 00:00:00 2001 From: hydroconstructor Date: Thu, 6 Jan 2022 20:19:01 +0400 Subject: [PATCH 334/503] Update usb.c (correct typo) There are 2 calls _stlink_usb_exit_dfu_mode In usb.c (at lines 1284 and 1293) and no single call _stlink_usb_exit_debug_mode. Apparently typo on line 1293 --- src/stlink-lib/usb.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/stlink-lib/usb.c b/src/stlink-lib/usb.c index 793a1f68d..65e8f4e25 100644 --- a/src/stlink-lib/usb.c +++ b/src/stlink-lib/usb.c @@ -1290,7 +1290,7 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, enum connect_type connect, // the NRST pin must be pull down before selecting the SWD/JTAG mode if (mode == STLINK_DEV_DEBUG_MODE) { DLOG("-- exit_debug_mode\n"); - _stlink_usb_exit_dfu_mode(sl); + _stlink_usb_exit_debug_mode(sl); } _stlink_usb_jtag_reset(sl, STLINK_DEBUG_APIV2_DRIVE_NRST_LOW); From e62b9e1f2a1b6dea7e9ccb053c14c2c6ad0b57d7 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Thu, 6 Jan 2022 19:30:49 +0100 Subject: [PATCH 335/503] [refactoring] Clean-up & update for chipid files - F0, F1, F2, F3, F4, F7 - G0, G4 - H7 - L0, L5, U5 - WB, WL --- config/chips/F03x.chip | 21 +- config/chips/F04x.chip | 21 +- config/chips/F05x.chip | 21 +- config/chips/F07x.chip | 21 +- config/chips/F09x.chip | 20 +- config/chips/F1xx_CL.chip | 12 +- config/chips/F1xx_HD.chip | 10 +- config/chips/F1xx_LD.chip | 10 +- config/chips/F1xx_MD.chip | 12 +- config/chips/F1xx_VL_HD.chip | 10 +- config/chips/F1xx_VL_MD_LD.chip | 10 +- config/chips/F1xx_XLD.chip | 12 +- config/chips/F2xx.chip | 12 +- config/chips/F301_F302_F318.chip | 21 +- config/chips/F302_F303_F358.chip | 21 +- config/chips/F302_F303_F398_HD.chip | 14 + config/chips/F303_F328_F334.chip | 21 +- config/chips/F303_high_density.chip | 13 - config/chips/F37x.chip | 21 +- config/chips/F401xB_C.chip | 13 - config/chips/F401xB_xC.chip | 14 + config/chips/F401xD_E.chip | 13 - config/chips/F401xD_xE.chip | 14 + config/chips/F410.chip | 17 +- config/chips/F411xC_E.chip | 13 - config/chips/F411xC_xE.chip | 14 + config/chips/F412.chip | 17 +- config/chips/F413_F423.chip | 17 +- config/chips/F42x_F43x.chip | 17 +- config/chips/F446.chip | 21 +- config/chips/F46x_F47x.chip | 17 +- config/chips/F4x5_F4x7.chip | 21 +- config/chips/F72x_F73x.chip | 21 +- config/chips/F74x_F75x.chip | 21 +- config/chips/F76x_F77x.chip | 23 +- config/chips/G03x_G04x.chip | 21 +- config/chips/G05x_G06x.chip | 21 +- config/chips/G07x_G08x.chip | 21 +- config/chips/G0Bx_G0Cx.chip | 21 +- config/chips/G43x_G44x.chip | 21 +- config/chips/G47x_G48x.chip | 23 +- config/chips/G49x_G4Ax.chip | 21 +- config/chips/H72x_H73x.chip | 21 +- config/chips/H74x_H75x.chip | 23 +- config/chips/H7Ax_H7Bx.chip | 23 +- config/chips/L01x_L02x.chip | 13 - config/chips/L0xx_Cat_2.chip | 13 - config/chips/L0xx_Cat_3.chip | 13 - config/chips/L0xx_Cat_5.chip | 13 - config/chips/L0xxx_Cat_1.chip | 14 + config/chips/L0xxx_Cat_2.chip | 14 + config/chips/L0xxx_Cat_3.chip | 14 + config/chips/L0xxx_Cat_5.chip | 14 + config/chips/L5x5.chip | 15 + config/chips/U5x5.chip | 15 + config/chips/WBx0_WBx5.chip | 14 + config/chips/WBx5_WBx0.chip | 14 - config/chips/{WLEx.chip => WLx5.chip} | 12 +- config/chips/unknown_device.chip | 2 +- inc/stm32.h | 13 +- src/stlink-lib/chipid.c | 12 +- src/stlink-lib/chipid_db_old.h | 1023 +++++++++++++------------ 62 files changed, 1047 insertions(+), 973 deletions(-) create mode 100644 config/chips/F302_F303_F398_HD.chip delete mode 100644 config/chips/F303_high_density.chip delete mode 100644 config/chips/F401xB_C.chip create mode 100644 config/chips/F401xB_xC.chip delete mode 100644 config/chips/F401xD_E.chip create mode 100644 config/chips/F401xD_xE.chip delete mode 100644 config/chips/F411xC_E.chip create mode 100644 config/chips/F411xC_xE.chip delete mode 100644 config/chips/L01x_L02x.chip delete mode 100644 config/chips/L0xx_Cat_2.chip delete mode 100644 config/chips/L0xx_Cat_3.chip delete mode 100644 config/chips/L0xx_Cat_5.chip create mode 100644 config/chips/L0xxx_Cat_1.chip create mode 100644 config/chips/L0xxx_Cat_2.chip create mode 100644 config/chips/L0xxx_Cat_3.chip create mode 100644 config/chips/L0xxx_Cat_5.chip create mode 100644 config/chips/L5x5.chip create mode 100644 config/chips/U5x5.chip create mode 100644 config/chips/WBx0_WBx5.chip delete mode 100644 config/chips/WBx5_WBx0.chip rename config/chips/{WLEx.chip => WLx5.chip} (54%) diff --git a/config/chips/F03x.chip b/config/chips/F03x.chip index eed78e4e2..ea7fdb9e2 100644 --- a/config/chips/F03x.chip +++ b/config/chips/F03x.chip @@ -1,13 +1,14 @@ -# Chip-ID file for F03x +# Chip-ID file for STM32F03x device # -chip_id 0x444 -description F03x -flash_type 1 -flash_pagesize 0x400 -sram_size 0x1000 +dev_type STM32F03x +ref_manual_id 0091 +chip_id 0x444 // STLINK_CHIPID_STM32_F0xx_SMALL +flash_type 1 // STLINK_FLASH_TYPE_F0 +flash_size_reg 0x1ffff7cc +flash_pagesize 0x400 // 1 KB +sram_size 0x1000 // 4 KB bootrom_base 0x1fffec00 -bootrom_size 0xc00 -option_base 0x1ffff800 -option_size 0x10 +bootrom_size 0xc00 // 3 KB +option_base 0x1ffff800 // STM32_F0_OPTION_BYTES_BASE +option_size 0x10 // 16 B flags none - diff --git a/config/chips/F04x.chip b/config/chips/F04x.chip index 1f2a2043e..3e702585b 100644 --- a/config/chips/F04x.chip +++ b/config/chips/F04x.chip @@ -1,13 +1,14 @@ -# Chip-ID file for F04x +# Chip-ID file for STM32F04x device # -chip_id 0x445 -description F04x -flash_type 1 -flash_pagesize 0x400 -sram_size 0x1800 +dev_type STM32F04x +ref_manual_id 0091 +chip_id 0x445 // STLINK_CHIPID_STM32_F04 +flash_type 1 // STLINK_FLASH_TYPE_F0 +flash_size_reg 0x1ffff7cc +flash_pagesize 0x400 // 1 KB +sram_size 0x1800 // 6 KB bootrom_base 0x1fffec00 -bootrom_size 0xc00 -option_base 0x1ffff800 -option_size 0x10 +bootrom_size 0xc00 // 3 KB +option_base 0x1ffff800 // STM32_F0_OPTION_BYTES_BASE +option_size 0x10 // 16 B flags none - diff --git a/config/chips/F05x.chip b/config/chips/F05x.chip index 787adb6bf..1a4f61386 100644 --- a/config/chips/F05x.chip +++ b/config/chips/F05x.chip @@ -1,13 +1,14 @@ -# Chip-ID file for F05x +# Chip-ID file for STM32F05x device # -chip_id 0x440 -description F05x -flash_type 1 -flash_pagesize 0x400 -sram_size 0x2000 +dev_type STM32F05x +ref_manual_id 0091 +chip_id 0x440 // STLINK_CHIPID_STM32_F0 +flash_type 1 // STLINK_FLASH_TYPE_F0 +flash_size_reg 0x1ffff7cc +flash_pagesize 0x400 // 1 KB +sram_size 0x2000 // 8 KB bootrom_base 0x1fffec00 -bootrom_size 0xc00 -option_base 0x1ffff800 -option_size 0x10 +bootrom_size 0xc00 // 3 KB +option_base 0x1ffff800 // STM32_F0_OPTION_BYTES_BASE +option_size 0x10 // 16 B flags none - diff --git a/config/chips/F07x.chip b/config/chips/F07x.chip index e893a5457..2a577b7b4 100644 --- a/config/chips/F07x.chip +++ b/config/chips/F07x.chip @@ -1,13 +1,14 @@ -# Chip-ID file for F07x +# Chip-ID file for STM32F07x device # -chip_id 0x448 -description F07x -flash_type 1 -flash_pagesize 0x800 -sram_size 0x4000 +dev_type STM32F07x +ref_manual_id 0091 +chip_id 0x448 // STLINK_CHIPID_STM32_F0_CAN +flash_type 1 // STLINK_FLASH_TYPE_F0 +flash_size_reg 0x1ffff7cc +flash_pagesize 0x800 // 2 KB +sram_size 0x4000 // 16 KB bootrom_base 0x1fffc800 -bootrom_size 0x3000 -option_base 0x1ffff800 -option_size 0x10 +bootrom_size 0x3000 // 12 KB +option_base 0x1ffff800 // STM32_F0_OPTION_BYTES_BASE +option_size 0x10 // 16 B flags none - diff --git a/config/chips/F09x.chip b/config/chips/F09x.chip index 267a2612f..9f419893e 100644 --- a/config/chips/F09x.chip +++ b/config/chips/F09x.chip @@ -1,13 +1,15 @@ -# Chip-ID file for F09x +# Chip-ID file for STM32F09x device # -chip_id 0x442 -description F09x -flash_type 1 -flash_pagesize 0x800 -sram_size 0x8000 +dev_type STM32F09x +ref_manual_id 0091 +chip_id 0x442 // STLINK_CHIPID_STM32_F09x +flash_type 1 // STLINK_FLASH_TYPE_F0 +flash_size_reg 0x1ffff7cc +flash_pagesize 0x800 // 2 KB +sram_size 0x8000 // 32 KB bootrom_base 0x1fffd800 -bootrom_size 0x2000 -option_base 0x1ffff800 -option_size 0x10 +bootrom_size 0x2000 // 8 KB +option_base 0x1ffff800 // STM32_F0_OPTION_BYTES_BASE +option_size 0x10 // 16 B flags none diff --git a/config/chips/F1xx_CL.chip b/config/chips/F1xx_CL.chip index 6282bc2ee..4c8bb0b8d 100644 --- a/config/chips/F1xx_CL.chip +++ b/config/chips/F1xx_CL.chip @@ -1,15 +1,15 @@ -# Chip-ID file for STM32F1xx CL device +# Chip-ID file for STM32F1xx Connectivity Line device # -dev_type STM32F1xx Connectivity Line device +dev_type STM32F1xx_CL ref_manual_id 0008 chip_id 0x418 // STLINK_CHIPID_STM32_F1_CONN flash_type 1 // STLINK_FLASH_TYPE_F0 flash_size_reg 0x1ffff7e0 -flash_pagesize 0x800 -sram_size 0x10000 +flash_pagesize 0x800 // 2 KB +sram_size 0x10000 // 64 KB bootrom_base 0x1fffb000 -bootrom_size 0x4800 +bootrom_size 0x4800 // 18 KB option_base 0x1ffff800 // STM32_F0_OPTION_BYTES_BASE -option_size 0x10 // 16 +option_size 0x10 // 16 B flags swo diff --git a/config/chips/F1xx_HD.chip b/config/chips/F1xx_HD.chip index 72ad9fa75..18757029a 100644 --- a/config/chips/F1xx_HD.chip +++ b/config/chips/F1xx_HD.chip @@ -1,14 +1,14 @@ # Chip-ID file for STM32F1xx high density device # -dev_type F1xx high density device +dev_type F1xx_HD ref_manual_id 0008 chip_id 0x414 // STLINK_CHIPID_STM32_F1_HD flash_type 1 // STLINK_FLASH_TYPE_F0 flash_size_reg 0x1ffff7e0 -flash_pagesize 0x800 -sram_size 0x10000 +flash_pagesize 0x800 // 2 KB +sram_size 0x10000 // 64 KB bootrom_base 0x1ffff000 -bootrom_size 0x800 +bootrom_size 0x800 // 2 KB option_base 0x1ffff800 // STM32_F0_OPTION_BYTES_BASE -option_size 0x10 // 16 +option_size 0x10 // 16 B flags swo diff --git a/config/chips/F1xx_LD.chip b/config/chips/F1xx_LD.chip index 8a3682755..8a8f5867d 100644 --- a/config/chips/F1xx_LD.chip +++ b/config/chips/F1xx_LD.chip @@ -1,14 +1,14 @@ # Chip-ID file for STM32F1 low density device # -dev_type STM32F1xx low density device +dev_type STM32F1xx_LD ref_manual_id 0008 chip_id 0x412 // STLINK_CHIPID_STM32_F1_LD flash_type 1 // STLINK_FLASH_TYPE_F0 flash_size_reg 0x1ffff7e0 -flash_pagesize 0x400 -sram_size 0x2800 +flash_pagesize 0x400 // 1 KB +sram_size 0x2800 // 10 KB bootrom_base 0x1ffff000 -bootrom_size 0x800 +bootrom_size 0x800 // 2 KB option_base 0x1ffff800 // STM32_F0_OPTION_BYTES_BASE -option_size 0x10 // 16 +option_size 0x10 // 16 B flags swo diff --git a/config/chips/F1xx_MD.chip b/config/chips/F1xx_MD.chip index f3da99493..be492f54a 100644 --- a/config/chips/F1xx_MD.chip +++ b/config/chips/F1xx_MD.chip @@ -1,14 +1,14 @@ # Chip-ID file for STM32F1xx medium density device # -dev_type STM32F1xx medium density device +dev_type STM32F1xx_MD ref_manual_id 0008 chip_id 0x410 // STLINK_CHIPID_STM32_F1_MD flash_type 1 // STLINK_FLASH_TYPE_F0 flash_size_reg 0x1ffff7e0 -flash_pagesize 0x400 -sram_size 0x5000 -bootrom_base 0x1ffff000 // Section 2.3.3 "Embedded Flash memory" -bootrom_size 0x800 +flash_pagesize 0x400 // 1 KB +sram_size 0x5000 // 20 KB +bootrom_base 0x1ffff000 +bootrom_size 0x800 // 2 KB option_base 0x1ffff800 // STM32_F0_OPTION_BYTES_BASE -option_size 0x10 // 16 +option_size 0x10 // 16 B flags swo diff --git a/config/chips/F1xx_VL_HD.chip b/config/chips/F1xx_VL_HD.chip index f46945a94..f5ca6b023 100644 --- a/config/chips/F1xx_VL_HD.chip +++ b/config/chips/F1xx_VL_HD.chip @@ -1,14 +1,14 @@ # Chip-ID file for STM32F1xx high density Value Line device # -dev_type STM32F1xx Value Line high density device +dev_type STM32F1xx_VL_HD ref_manual_id 0041 chip_id 0x428 // STLINK_CHIPID_STM32_F1_VL_HD flash_type 1 // STLINK_FLASH_TYPE_F0 flash_size_reg 0x1ffff7e0 -flash_pagesize 0x800 -sram_size 0x8000 +flash_pagesize 0x800 // 2 KB +sram_size 0x8000 // 32 KB bootrom_base 0x1ffff000 -bootrom_size 0x800 +bootrom_size 0x800 // 2 KB option_base 0x1ffff800 // STM32_F0_OPTION_BYTES_BASE -option_size 0x10 // 16 +option_size 0x10 // 16 B flags swo diff --git a/config/chips/F1xx_VL_MD_LD.chip b/config/chips/F1xx_VL_MD_LD.chip index 2bff05b82..e79668c70 100644 --- a/config/chips/F1xx_VL_MD_LD.chip +++ b/config/chips/F1xx_VL_MD_LD.chip @@ -1,14 +1,14 @@ # Chip-ID file for STMF1xx Value Line medium & low density device # -dev_type STM32F1xx Value Line medium & low density device +dev_type STM32F1xx_VL_MD_LD ref_manual_id 0041 chip_id 0x420 // STLINK_CHIPID_STM32_F1_VL_MD_LD flash_type 1 // STLINK_FLASH_TYPE_F0 flash_size_reg 0x1ffff7e0 -flash_pagesize 0x400 -sram_size 0x2000 // 0x1000 for low density devices +flash_pagesize 0x400 // 1 KB +sram_size 0x2000 // 8 KB /* 0x1000 for low density devices */ bootrom_base 0x1ffff000 -bootrom_size 0x800 +bootrom_size 0x800 // 2 KB option_base 0x1ffff800 // STM32_F0_OPTION_BYTES_BASE -option_size 0x10 // 16 +option_size 0x10 // 16 B flags swo diff --git a/config/chips/F1xx_XLD.chip b/config/chips/F1xx_XLD.chip index 90264ce0f..d7d8cf2b7 100644 --- a/config/chips/F1xx_XLD.chip +++ b/config/chips/F1xx_XLD.chip @@ -1,14 +1,14 @@ # Chip-ID file for STM32F1xx XL density device # -dev_type STM32F1xx XL density device +dev_type STM32F1xx_XLD ref_manual_id 0008 -chip_id 0x430 // STLINK_CHIPID_STM32_F1_XLD -flash_type 2 // STLINK_FLASH_TYPE_F1_XL +chip_id 0x430 // STLINK_CHIPID_STM32_F1_XLD +flash_type 2 // STLINK_FLASH_TYPE_F1_XL flash_size_reg 0x1ffff7e0 -flash_pagesize 0x800 -sram_size 0x18000 +flash_pagesize 0x800 // 2 KB +sram_size 0x18000 // 96 KB bootrom_base 0x1fffe000 -bootrom_size 0x1800 +bootrom_size 0x1800 // 6 KB option_base 0x0 option_size 0x0 flags swo diff --git a/config/chips/F2xx.chip b/config/chips/F2xx.chip index ce2e9e698..67c225af5 100644 --- a/config/chips/F2xx.chip +++ b/config/chips/F2xx.chip @@ -1,14 +1,14 @@ -# Chip-ID file for STM32F2xx device (STM32F205xx, STM32F207xx, STM32F215xx, STM32F217xx) +# Chip-ID file for STM32F2xx device # -dev_type STM32F2xx device +dev_type STM32F2xx ref_manual_id 0033 chip_id 0x411 // STLINK_CHIPID_STM32_F2 flash_type 3 // STLINK_FLASH_TYPE_F4 flash_size_reg 0x1fff7a22 -flash_pagesize 0x20000 -sram_size 0x20000 +flash_pagesize 0x20000 // 128 KB +sram_size 0x20000 // 128 KB bootrom_base 0x1fff0000 -bootrom_size 0x7800 +bootrom_size 0x7800 // 30 KB option_base 0x1fffc000 // STM32_F2_OPTION_BYTES_BASE -option_size 0x4 // 4 +option_size 0x4 // 4 B flags swo diff --git a/config/chips/F301_F302_F318.chip b/config/chips/F301_F302_F318.chip index 429c836b4..ee71dfe90 100644 --- a/config/chips/F301_F302_F318.chip +++ b/config/chips/F301_F302_F318.chip @@ -1,13 +1,14 @@ -# Chip-ID file for F301/F302/F318 +# Chip-ID file for STM32F3xx device (F301x6/8, F302x6x8, F318x8) # -chip_id 0x439 -description F301/F302/F318 -flash_type 1 -flash_pagesize 0x800 -sram_size 0xa000 +dev_type STM32F301_F302_F318 +ref_manual_id 0365 // also RM0366 +chip_id 0x439 // STLINK_CHIPID_STM32_F3xx_SMALL +flash_type 1 // STLINK_FLASH_TYPE_F0 +flash_size_reg 0x1ffff7cc +flash_pagesize 0x800 // 2 KB +sram_size 0xa000 // 40 KB bootrom_base 0x1fffd800 -bootrom_size 0x2000 -option_base 0x1ffff800 -option_size 0x10 +bootrom_size 0x2000 // 8 KB +option_base 0x1ffff800 // STM32_F0_OPTION_BYTES_BASE +option_size 0x10 // 16 B flags swo - diff --git a/config/chips/F302_F303_F358.chip b/config/chips/F302_F303_F358.chip index ffd1491ff..64d0651f2 100644 --- a/config/chips/F302_F303_F358.chip +++ b/config/chips/F302_F303_F358.chip @@ -1,13 +1,14 @@ -# Chip-ID file for F302/F303/F358 +# Chip-ID file for STM32F3xx device (F302xBxC, F303xB/C, F358) # -chip_id 0x422 -description F302/F303/F358 -flash_type 1 -flash_pagesize 0x800 -sram_size 0xa000 +dev_type STM32F302_F303_358 +ref_manual_id 0365 // also RM0316 +chip_id 0x422 // STLINK_CHIPID_STM32_F3 +flash_type 1 // STLINK_FLASH_TYPE_F0 +flash_size_reg 0x1ffff7cc +flash_pagesize 0x800 // 2 KB +sram_size 0xa000 // 40 KB bootrom_base 0x1ffff000 -bootrom_size 0x800 -option_base 0x1ffff800 -option_size 0x10 +bootrom_size 0x800 // 2 KB +option_base 0x1ffff800 // STM32_F0_OPTION_BYTES_BASE +option_size 0x10 // 16 B flags swo - diff --git a/config/chips/F302_F303_F398_HD.chip b/config/chips/F302_F303_F398_HD.chip new file mode 100644 index 000000000..eaf36b74c --- /dev/null +++ b/config/chips/F302_F303_F398_HD.chip @@ -0,0 +1,14 @@ +# Chip-ID file for STM32F3xx high density device (F302xD/E, F303xD/E, F398xE) +# +dev_type STM32F302_F303_F398_HD +ref_manual_id 0365 // also RM0316 (Rev 5) +chip_id 0x446 // STLINK_CHIPID_STM32_F303_HD +flash_type 1 // STLINK_FLASH_TYPE_F0 +flash_size_reg 0x1ffff7cc +flash_pagesize 0x800 // 2 KB +sram_size 0x10000 // 64 KB +bootrom_base 0x1fffd800 +bootrom_size 0x2000 // 8 KB +option_base 0x1ffff800 // STM32_F0_OPTION_BYTES_BASE +option_size 0x10 // 16 B +flags swo diff --git a/config/chips/F303_F328_F334.chip b/config/chips/F303_F328_F334.chip index 5df2a9bbb..2ecdbfb71 100644 --- a/config/chips/F303_F328_F334.chip +++ b/config/chips/F303_F328_F334.chip @@ -1,13 +1,14 @@ -# Chip-ID file for F303/F328/F334 +# Chip-ID file for STM32F3xx device (F303x6/8, F328, F334) # -chip_id 0x438 -description F303/F328/F334 -flash_type 1 -flash_pagesize 0x800 -sram_size 0x3000 +dev_type STM32F303_F328_F334 +ref_manual_id 0364 // also RM0316 +chip_id 0x438 // STLINK_CHIPID_STM32_F334 +flash_type 1 // STLINK_FLASH_TYPE_F0 +flash_size_reg 0x1ffff7cc +flash_pagesize 0x800 // 2 KB +sram_size 0x3000 // 12 KB bootrom_base 0x1fffd800 -bootrom_size 0x2000 -option_base 0x1ffff800 -option_size 0x10 +bootrom_size 0x2000 // 8 KB +option_base 0x1ffff800 // STM32_F0_OPTION_BYTES_BASE +option_size 0x10 // 16 B flags swo - diff --git a/config/chips/F303_high_density.chip b/config/chips/F303_high_density.chip deleted file mode 100644 index 748c27cbc..000000000 --- a/config/chips/F303_high_density.chip +++ /dev/null @@ -1,13 +0,0 @@ -# Chip-ID file for F303 high density -# -chip_id 0x446 -description F303 high density -flash_type 1 -flash_pagesize 0x800 -sram_size 0x10000 -bootrom_base 0x1fffd800 -bootrom_size 0x2000 -option_base 0x1ffff800 -option_size 0x10 -flags swo - diff --git a/config/chips/F37x.chip b/config/chips/F37x.chip index 92201657d..1bd7ac421 100644 --- a/config/chips/F37x.chip +++ b/config/chips/F37x.chip @@ -1,13 +1,14 @@ -# Chip-ID file for F37x +# Chip-ID file for STM32F37x device # -chip_id 0x432 -description F37x -flash_type 1 -flash_pagesize 0x800 -sram_size 0xa000 +dev_type STM32F37x +ref_manual_id 0313 +chip_id 0x432 // STLINK_CHIPID_STM32_F37x +flash_type 1 // STLINK_FLASH_TYPE_F0 +flash_size_reg 0x1ffff7cc +flash_pagesize 0x800 // 2 KB +sram_size 0xa000 // 40 KB bootrom_base 0x1ffff000 -bootrom_size 0x800 -option_base 0x1ffff800 -option_size 0x10 +bootrom_size 0x800 // 2 KB +option_base 0x1ffff800 // STM32_F0_OPTION_BYTES_BASE +option_size 0x10 // 16 B flags swo - diff --git a/config/chips/F401xB_C.chip b/config/chips/F401xB_C.chip deleted file mode 100644 index 09e998dba..000000000 --- a/config/chips/F401xB_C.chip +++ /dev/null @@ -1,13 +0,0 @@ -# Chip-ID file for F401xB/C -# -chip_id 0x423 -description F401xB/C -flash_type 3 -flash_pagesize 0x4000 -sram_size 0x10000 -bootrom_base 0x1fff0000 -bootrom_size 0x7800 -option_base 0x0 -option_size 0x0 -flags swo - diff --git a/config/chips/F401xB_xC.chip b/config/chips/F401xB_xC.chip new file mode 100644 index 000000000..fc93c2f1a --- /dev/null +++ b/config/chips/F401xB_xC.chip @@ -0,0 +1,14 @@ +# Chip-ID file for STM32F401xB/xC device +# +dev_type STM32F401xB_xC +ref_manual_id 0368 +chip_id 0x423 // STLINK_CHIPID_STM32_F4_LP +flash_type 3 // STLINK_FLASH_TYPE_F4 +flash_size_reg 0x1fff7a22 +flash_pagesize 0x4000 // 16 KB +sram_size 0x10000 // 64 KB +bootrom_base 0x1fff0000 +bootrom_size 0x7800 // 30 KB +option_base 0x0 +option_size 0x0 +flags swo diff --git a/config/chips/F401xD_E.chip b/config/chips/F401xD_E.chip deleted file mode 100644 index 5b70d7d86..000000000 --- a/config/chips/F401xD_E.chip +++ /dev/null @@ -1,13 +0,0 @@ -# Chip-ID file for F401xD/E -# -chip_id 0x433 -description F401xD/E -flash_type 3 -flash_pagesize 0x4000 -sram_size 0x18000 -bootrom_base 0x1fff0000 -bootrom_size 0x7800 -option_base 0x0 -option_size 0x0 -flags swo - diff --git a/config/chips/F401xD_xE.chip b/config/chips/F401xD_xE.chip new file mode 100644 index 000000000..e31d5eace --- /dev/null +++ b/config/chips/F401xD_xE.chip @@ -0,0 +1,14 @@ +# Chip-ID file for STM32F401xD/xE device +# +dev_type STM32F401xD_xE +ref_manual_id 0368 +chip_id 0x433 // STLINK_CHIPID_STM32_F4_DE +flash_type 3 // STLINK_FLASH_TYPE_F4 +flash_size_reg 0x1fff7a22 +flash_pagesize 0x4000 // 16 KB +sram_size 0x18000 // 96 KB +bootrom_base 0x1fff0000 +bootrom_size 0x7800 // 30 KB +option_base 0x0 +option_size 0x0 +flags swo diff --git a/config/chips/F410.chip b/config/chips/F410.chip index ae199d9c4..a8a7fbad0 100644 --- a/config/chips/F410.chip +++ b/config/chips/F410.chip @@ -1,13 +1,14 @@ -# Chip-ID file for F410 +# Chip-ID file for STM32F410 device # -chip_id 0x458 -description F410 -flash_type 3 -flash_pagesize 0x4000 -sram_size 0x8000 +dev_type STM32F410 +ref_manual_id 0401 +chip_id 0x458 // STLINK_CHIPID_STM32_F410 +flash_type 3 // STLINK_FLASH_TYPE_F4 +flash_size_reg 0x1fff7a22 +flash_pagesize 0x4000 // 16 KB +sram_size 0x8000 // 32 KB bootrom_base 0x1fff0000 -bootrom_size 0x7800 +bootrom_size 0x7800 // 30 KB option_base 0x0 option_size 0x0 flags swo - diff --git a/config/chips/F411xC_E.chip b/config/chips/F411xC_E.chip deleted file mode 100644 index d344489c5..000000000 --- a/config/chips/F411xC_E.chip +++ /dev/null @@ -1,13 +0,0 @@ -# Chip-ID file for F411xC/E -# -chip_id 0x431 -description F411xC/E -flash_type 3 -flash_pagesize 0x4000 -sram_size 0x20000 -bootrom_base 0x1fff0000 -bootrom_size 0x7800 -option_base 0x0 -option_size 0x0 -flags swo - diff --git a/config/chips/F411xC_xE.chip b/config/chips/F411xC_xE.chip new file mode 100644 index 000000000..cf2cbd2c1 --- /dev/null +++ b/config/chips/F411xC_xE.chip @@ -0,0 +1,14 @@ +# Chip-ID file for STM32F411xC/xE device +# +dev_type STM32F411xC_xE +ref_manual_id 0383 +chip_id 0x431 // STLINK_CHIPID_STM32_F411xx +flash_type 3 // STLINK_FLASH_TYPE_F4 +flash_size_reg 0x1fff7a22 +flash_pagesize 0x4000 // 16 KB +sram_size 0x20000 // 128 KB +bootrom_base 0x1fff0000 +bootrom_size 0x7800 // 30 KB +option_base 0x0 +option_size 0x0 +flags swo diff --git a/config/chips/F412.chip b/config/chips/F412.chip index 3212a340c..4c866a3c5 100644 --- a/config/chips/F412.chip +++ b/config/chips/F412.chip @@ -1,13 +1,14 @@ -# Chip-ID file for F412 +# Chip-ID file for STM32F412 device # -chip_id 0x441 -description F412 -flash_type 3 -flash_pagesize 0x4000 -sram_size 0x40000 +dev_type STM32F412 +ref_manual_id 0402 +chip_id 0x441 // STLINK_CHIPID_STM32_F412 +flash_type 3 // STLINK_FLASH_TYPE_F4 +flash_size_reg 0x1fff7a22 +flash_pagesize 0x4000 // 16 KB +sram_size 0x40000 // 256 KB bootrom_base 0x1fff0000 -bootrom_size 0x7800 +bootrom_size 0x7800 // 30 KB option_base 0x0 option_size 0x0 flags swo - diff --git a/config/chips/F413_F423.chip b/config/chips/F413_F423.chip index 647775eeb..81ca585f6 100644 --- a/config/chips/F413_F423.chip +++ b/config/chips/F413_F423.chip @@ -1,13 +1,14 @@ -# Chip-ID file for F413/F423 +# Chip-ID file for STM32F413 / STM32F423 device # -chip_id 0x463 -description F413/F423 -flash_type 3 -flash_pagesize 0x4000 -sram_size 0x50000 +dev_type STM32F413_F423 +ref_manual_id 0430 // RM0430 (Rev 2) +chip_id 0x463 // STLINK_CHIPID_STM32_F413 +flash_type 3 // STLINK_FLASH_TYPE_F4 +flash_size_reg 0x1fff7a22 +flash_pagesize 0x4000 // 16 KB +sram_size 0x50000 // 320 KB bootrom_base 0x1fff0000 -bootrom_size 0x7800 +bootrom_size 0x7800 // 30 KB option_base 0x0 option_size 0x0 flags swo - diff --git a/config/chips/F42x_F43x.chip b/config/chips/F42x_F43x.chip index 3184d0d4f..2ec8fb8e8 100644 --- a/config/chips/F42x_F43x.chip +++ b/config/chips/F42x_F43x.chip @@ -1,13 +1,14 @@ -# Chip-ID file for F42x/F43x +# Chip-ID file for STM32F42x / STM32F43x device # -chip_id 0x419 -description F42x/F43x -flash_type 3 -flash_pagesize 0x4000 -sram_size 0x40000 +dev_type STM32F42x_F43x +ref_manual_id 0090 // RM0090 (Rev. 2) +chip_id 0x463 // STLINK_CHIPID_STM32_F4_HD +flash_type 3 // STLINK_FLASH_TYPE_F4 +flash_size_reg 0x1fff7a22 +flash_pagesize 0x4000 // 16 KB +sram_size 0x40000 // 256 KB bootrom_base 0x1fff0000 -bootrom_size 0x7800 +bootrom_size 0x7800 // 30 KB option_base 0x0 option_size 0x0 flags swo - diff --git a/config/chips/F446.chip b/config/chips/F446.chip index 86cee6a56..8cebe358e 100644 --- a/config/chips/F446.chip +++ b/config/chips/F446.chip @@ -1,13 +1,14 @@ -# Chip-ID file for F446 +# Chip-ID file for STM32F446 device # -chip_id 0x421 -description F446 -flash_type 3 -flash_pagesize 0x20000 -sram_size 0x20000 +dev_type STM32F446 +ref_manual_id 0390 +chip_id 0x421 // STLINK_CHIPID_STM32_F446 +flash_type 3 // STLINK_FLASH_TYPE_F4 +flash_size_reg 0x1fff7a22 +flash_pagesize 0x20000 // 128 KB +sram_size 0x20000 // 128 KB bootrom_base 0x1fff0000 -bootrom_size 0x7800 -option_base 0x1fffc000 -option_size 0x4 +bootrom_size 0x7800 // 30 KB +option_base 0x40023c14 // STM32_F4_OPTION_BYTES_BASE +option_size 0x4 // 4 B flags swo - diff --git a/config/chips/F46x_F47x.chip b/config/chips/F46x_F47x.chip index ee5f6a5a7..2e4055f2c 100644 --- a/config/chips/F46x_F47x.chip +++ b/config/chips/F46x_F47x.chip @@ -1,13 +1,14 @@ -# Chip-ID file for F46x/F47x +# Chip-ID file for STM32F46x / STM32F47x device # -chip_id 0x434 -description F46x/F47x -flash_type 3 -flash_pagesize 0x4000 -sram_size 0x40000 +dev_type STM32F46x_F47x +ref_manual_id 0090 // RM0090 (Rev. 2) +chip_id 0x434 // STLINK_CHIPID_STM32_F4_DSI +flash_type 3 // STLINK_FLASH_TYPE_F4 +flash_size_reg 0x1fff7a22 +flash_pagesize 0x4000 // 16 KB +sram_size 0x40000 // 256 KB bootrom_base 0x1fff0000 -bootrom_size 0x7800 +bootrom_size 0x7800 // 30 KB option_base 0x0 option_size 0x0 flags swo - diff --git a/config/chips/F4x5_F4x7.chip b/config/chips/F4x5_F4x7.chip index b19e4a5b3..9313c8ae1 100644 --- a/config/chips/F4x5_F4x7.chip +++ b/config/chips/F4x5_F4x7.chip @@ -1,13 +1,14 @@ -# Chip-ID file for F4x5/F4x7 +# Chip-ID file for STM32F4x5 / STM32F4x7 device # -chip_id 0x413 -description F4x5/F4x7 -flash_type 3 -flash_pagesize 0x4000 -sram_size 0x30000 +dev_type STM32F4x5_F4x7 +ref_manual_id 0090 // RM0090 (Rev. 2) +chip_id 0x413 // STLINK_CHIPID_STM32_F4 +flash_type 3 // STLINK_FLASH_TYPE_F4 +flash_size_reg 0x1fff7a22 +flash_pagesize 0x4000 // 16 KB +sram_size 0x30000 // 192 KB bootrom_base 0x1fff0000 -bootrom_size 0x7800 -option_base 0x40023c14 -option_size 0x4 +bootrom_size 0x7800 // 30 KB +option_base 0x40023c14 // STM32_F4_OPTION_BYTES_BASE +option_size 0x4 // 4 B flags swo - diff --git a/config/chips/F72x_F73x.chip b/config/chips/F72x_F73x.chip index 2836040ac..37dcd1234 100644 --- a/config/chips/F72x_F73x.chip +++ b/config/chips/F72x_F73x.chip @@ -1,13 +1,14 @@ -# Chip-ID file for F72x/F73x +# Chip-ID file for STM32F72x / STM32F73x device # -chip_id 0x452 -description F72x/F73x -flash_type 3 -flash_pagesize 0x800 -sram_size 0x40000 +dev_type STM32F72x_F73x +ref_manual_id 0431 +chip_id 0x452 // STLINK_CHIPID_STM32_F72xxx +flash_type 3 // STLINK_FLASH_TYPE_F4 +flash_size_reg 0x1ff07a22 +flash_pagesize 0x800 // 2 KB +sram_size 0x40000 // 256 KB bootrom_base 0x100000 -bootrom_size 0xedc0 -option_base 0x0 -option_size 0x0 +bootrom_size 0xedc0 // 59.4375 KB +option_base 0x1fff0000 // STM32_F7_OPTION_BYTES_BASE +option_size 0x20 // 32 B flags swo - diff --git a/config/chips/F74x_F75x.chip b/config/chips/F74x_F75x.chip index 0604b299d..96cc95217 100644 --- a/config/chips/F74x_F75x.chip +++ b/config/chips/F74x_F75x.chip @@ -1,13 +1,14 @@ -# Chip-ID file for F74x/F75x +# Chip-ID file for STM32F74x / STM32F75x device # -chip_id 0x449 -description F74x/F75x -flash_type 3 -flash_pagesize 0x800 -sram_size 0x50000 +dev_type STM32F74x_F75x +ref_manual_id 0385 +chip_id 0x449 // STLINK_CHIPID_STM32_F7 +flash_type 3 // STLINK_FLASH_TYPE_F4 +flash_size_reg 0x1ff0f442 +flash_pagesize 0x800 // 2 KB +sram_size 0x50000 // 320 KB bootrom_base 0x100000 -bootrom_size 0xedc0 -option_base 0x0 -option_size 0x0 +bootrom_size 0xedc0 // 59.4375 KB +option_base 0x1fff0000 // STM32_F7_OPTION_BYTES_BASE +option_size 0x20 // 32 B flags swo - diff --git a/config/chips/F76x_F77x.chip b/config/chips/F76x_F77x.chip index 304c99191..a93aba2be 100644 --- a/config/chips/F76x_F77x.chip +++ b/config/chips/F76x_F77x.chip @@ -1,13 +1,14 @@ -# Chip-ID file for F76x/F77x +# Chip-ID file for STM32F76x / STM32F77x device # -chip_id 0x451 -description F76x/F77x -flash_type 4 -flash_pagesize 0x800 -sram_size 0x80000 +dev_type STM32F76x_F77x +ref_manual_id 0410 +chip_id 0x451 // STLINK_CHIPID_STM32_F76xxx +flash_type 4 // STLINK_FLASH_TYPE_F7 +flash_size_reg 0x1ff0f442 +flash_pagesize 0x800 // 2 KB +sram_size 0x80000 // 512 KB bootrom_base 0x200000 -bootrom_size 0xedc0 -option_base 0x1fff0000 -option_size 0x20 -flags dualbank swo - +bootrom_size 0xedc0 // 59.4375 KB +option_base 0x1fff0000 // STM32_F7_OPTION_BYTES_BASE /* Used for reading back option bytes, writing uses FLASH_F7_OPTCR and FLASH_F7_OPTCR1 */ +option_size 0x20 // 32 B +flags swo dualbank diff --git a/config/chips/G03x_G04x.chip b/config/chips/G03x_G04x.chip index 7c5a00c58..a21a9898f 100644 --- a/config/chips/G03x_G04x.chip +++ b/config/chips/G03x_G04x.chip @@ -1,13 +1,14 @@ -# Chip-ID file for G03x/G04x +# Chip-ID file for STM32G030 / STM32G031 / STM32G041 device # -chip_id 0x466 -description G03x/G04x -flash_type 7 -flash_pagesize 0x800 -sram_size 0x2000 +dev_type STM32G03x_G04x +ref_manual_id 0444 // also RM454 +chip_id 0x466 // STLINK_CHIPID_STM32_G0_CAT1 +flash_type 7 // STLINK_FLASH_TYPE_G0 +flash_size_reg 0x1fff75e0 +flash_pagesize 0x800 // 2 KB +sram_size 0x2000 // 8 KB bootrom_base 0x1fff0000 -bootrom_size 0x2000 -option_base 0x1fff7800 -option_size 0x4 +bootrom_size 0x2000 // 8 KB +option_base 0x1fff7800 // STM32_G0_OPTION_BYTES_BASE +option_size 0x4 // 4 B flags none - diff --git a/config/chips/G05x_G06x.chip b/config/chips/G05x_G06x.chip index 45295ec6e..89af0825c 100644 --- a/config/chips/G05x_G06x.chip +++ b/config/chips/G05x_G06x.chip @@ -1,13 +1,14 @@ -# Chip-ID file for G05x/G06x +# Chip-ID file for STM32G05x / STM32G06x device # -chip_id 0x456 -description G05x/G06x -flash_type 7 -flash_pagesize 0x800 -sram_size 0x9000 +dev_type STM32G05x_G06x +ref_manual_id 0444 +chip_id 0x456 // STLINK_CHIPID_STM32_G0_CAT4 +flash_type 7 // STLINK_FLASH_TYPE_G0 +flash_size_reg 0x1fff75e0 +flash_pagesize 0x800 // 2 KB +sram_size 0x9000 // 36 KB bootrom_base 0x1fff0000 -bootrom_size 0x7000 -option_base 0x1fff7800 -option_size 0x4 +bootrom_size 0x7000 // 28 KB +option_base 0x1fff7800 // STM32_G0_OPTION_BYTES_BASE +option_size 0x4 // 4 B flags none - diff --git a/config/chips/G07x_G08x.chip b/config/chips/G07x_G08x.chip index 7bddcd82c..c54de398f 100644 --- a/config/chips/G07x_G08x.chip +++ b/config/chips/G07x_G08x.chip @@ -1,13 +1,14 @@ -# Chip-ID file for G07x/G08x +# Chip-ID file for STM32G07x / STM32G08x device # -chip_id 0x460 -description G07x/G08x -flash_type 7 -flash_pagesize 0x800 -sram_size 0x9000 +dev_type STM32G07x_G08x +ref_manual_id 0444 +chip_id 0x460 // STLINK_CHIPID_STM32_G0_CAT2 +flash_type 7 // STLINK_FLASH_TYPE_G0 +flash_size_reg 0x1fff75e0 +flash_pagesize 0x800 // 2 KB +sram_size 0x9000 // 36 KB bootrom_base 0x1fff0000 -bootrom_size 0x7000 -option_base 0x1fff7800 -option_size 0x4 +bootrom_size 0x7000 // 28 KB +option_base 0x1fff7800 // STM32_G0_OPTION_BYTES_BASE +option_size 0x4 // 4 B flags none - diff --git a/config/chips/G0Bx_G0Cx.chip b/config/chips/G0Bx_G0Cx.chip index 98e503569..d8e0eb042 100644 --- a/config/chips/G0Bx_G0Cx.chip +++ b/config/chips/G0Bx_G0Cx.chip @@ -1,13 +1,14 @@ -# Chip-ID file for G0Bx/G0Cx +# Chip-ID file for STM32G0Bx / STM32G0Cx device # -chip_id 0x467 -description G0Bx/G0Cx -flash_type 7 -flash_pagesize 0x800 -sram_size 0x9000 +dev_type STM32G0Bx_G0Cx +ref_manual_id 0444 +chip_id 0x467 // STLINK_CHIPID_STM32_G0_CAT3 +flash_type 7 // STLINK_FLASH_TYPE_G0 +flash_size_reg 0x1fff75e0 +flash_pagesize 0x800 // 2 KB +sram_size 0x9000 // 36 KB bootrom_base 0x1fff0000 -bootrom_size 0x7000 -option_base 0x1fff7800 -option_size 0x4 +bootrom_size 0x7000 // 28 KB +option_base 0x1fff7800 // STM32_G0_OPTION_BYTES_BASE +option_size 0x4 // 4 B flags dualbank - diff --git a/config/chips/G43x_G44x.chip b/config/chips/G43x_G44x.chip index 033f1dd80..455d65b8c 100644 --- a/config/chips/G43x_G44x.chip +++ b/config/chips/G43x_G44x.chip @@ -1,13 +1,14 @@ -# Chip-ID file for G43x/G44x +# Chip-ID file for STM32G43x / STM32G44x device # -chip_id 0x468 -description G43x/G44x -flash_type 8 -flash_pagesize 0x800 -sram_size 0x8000 +dev_type STM32G43x_G44x +ref_manual_id 0440 +chip_id 0x468 // STLINK_CHIPID_STM32_G4_CAT2 +flash_type 8 // STLINK_FLASH_TYPE_G4 +flash_size_reg 0x1fff75e0 +flash_pagesize 0x800 // 2 KB +sram_size 0x8000 // 32 KB bootrom_base 0x1fff0000 -bootrom_size 0x7000 -option_base 0x1ffff800 -option_size 0x4 +bootrom_size 0x7000 // 28 KB +option_base 0x1ffff800 // STM32_G4_OPTION_BYTES_BASE +option_size 0x4 // 4 B flags swo - diff --git a/config/chips/G47x_G48x.chip b/config/chips/G47x_G48x.chip index fa331650f..250905c68 100644 --- a/config/chips/G47x_G48x.chip +++ b/config/chips/G47x_G48x.chip @@ -1,13 +1,14 @@ -# Chip-ID file for G47x/G48x +# Chip-ID file for STM32G47x / STM32G48x device # -chip_id 0x469 -description G47x/G48x -flash_type 8 -flash_pagesize 0x800 -sram_size 0x20000 +dev_type STM32G47x_G48x +ref_manual_id 0440 +chip_id 0x469 // STLINK_CHIPID_STM32_G4_CAT3 +flash_type 8 // STLINK_FLASH_TYPE_G4 +flash_size_reg 0x1fff75e0 +flash_pagesize 0x800 // 2 KB +sram_size 0x20000 // 128 KB bootrom_base 0x1fff0000 -bootrom_size 0x7000 -option_base 0x1ffff800 -option_size 0x4 -flags dualbank swo - +bootrom_size 0x7000 // 28 KB +option_base 0x1ffff800 // STM32_G4_OPTION_BYTES_BASE +option_size 0x4 // 4 B +flags swo dualbank diff --git a/config/chips/G49x_G4Ax.chip b/config/chips/G49x_G4Ax.chip index b764572db..9702541a8 100644 --- a/config/chips/G49x_G4Ax.chip +++ b/config/chips/G49x_G4Ax.chip @@ -1,13 +1,14 @@ -# Chip-ID file for G49x/G4Ax +# Chip-ID file for STM32G49x / STM32G4Ax device # -chip_id 0x479 -description G49x/G4Ax -flash_type 8 -flash_pagesize 0x800 -sram_size 0x1c000 +dev_type STM32G49x_G4Ax +ref_manual_id 0440 +chip_id 0x479 // STLINK_CHIPID_STM32_G4_CAT4 +flash_type 8 // STLINK_FLASH_TYPE_G4 +flash_size_reg 0x1fff75e0 +flash_pagesize 0x800 // 2 KB +sram_size 0x1c000 // 112 KB bootrom_base 0x1fff0000 -bootrom_size 0x7000 -option_base 0x1ffff800 -option_size 0x4 +bootrom_size 0x7000 // 28 KB +option_base 0x1ffff800 // STM32_G4_OPTION_BYTES_BASE +option_size 0x4 // 4 B flags swo - diff --git a/config/chips/H72x_H73x.chip b/config/chips/H72x_H73x.chip index df20037d3..183c7d197 100644 --- a/config/chips/H72x_H73x.chip +++ b/config/chips/H72x_H73x.chip @@ -1,13 +1,14 @@ -# Chip-ID file for H72x/H73x +# Chip-ID file for STM32H72x / STM32H73x device # -chip_id 0x483 -description H72x/H73x -flash_type 10 -flash_pagesize 0x20000 -sram_size 0x20000 +dev_type STM32H72x_H73x +ref_manual_id 0468 +chip_id 0x483 // STLINK_CHIPID_STM32_H72x +flash_type 10 // STLINK_FLASH_TYPE_H7 +flash_size_reg 0x1ff1e880 +flash_pagesize 0x20000 // 128 KB +sram_size 0x20000 // 128 KB "DTCM" bootrom_base 0x1ff00000 -bootrom_size 0x20000 -option_base 0x5200201c -option_size 0x2c +bootrom_size 0x20000 // 128 KB +option_base 0x5200201c // STM32_H7_OPTION_BYTES_BASE +option_size 0x2c // 44 B flags swo - diff --git a/config/chips/H74x_H75x.chip b/config/chips/H74x_H75x.chip index 7a4bc86e3..2e543b197 100644 --- a/config/chips/H74x_H75x.chip +++ b/config/chips/H74x_H75x.chip @@ -1,13 +1,14 @@ -# Chip-ID file for H74x/H75x +# Chip-ID file for STM32H74x / STM32H75x device # -chip_id 0x450 -description H74x/H75x -flash_type 10 -flash_pagesize 0x20000 -sram_size 0x20000 +dev_type STM32H74x_H75x +ref_manual_id 0433 +chip_id 0x450 // STLINK_CHIPID_STM32_H74xxx +flash_type 10 // STLINK_FLASH_TYPE_H7 +flash_size_reg 0x1ff1e880 +flash_pagesize 0x20000 // 128 KB +sram_size 0x20000 // 128 KB "DTCM" bootrom_base 0x1ff00000 -bootrom_size 0x20000 -option_base 0x5200201c -option_size 0x2c -flags dualbank swo - +bootrom_size 0x20000 // 128 KB +option_base 0x5200201c // STM32_H7_OPTION_BYTES_BASE +option_size 0x2c // 44 B /* FLASH_OPTSR_CUR to FLASH_BOOT_PRGR */ +flags swo dualbank diff --git a/config/chips/H7Ax_H7Bx.chip b/config/chips/H7Ax_H7Bx.chip index b9202bd1a..b5fe72119 100644 --- a/config/chips/H7Ax_H7Bx.chip +++ b/config/chips/H7Ax_H7Bx.chip @@ -1,13 +1,14 @@ -# Chip-ID file for H7Ax/H7Bx +# Chip-ID file for STM32H7Ax / STM32H7Bx device # -chip_id 0x480 -description H7Ax/H7Bx -flash_type 10 -flash_pagesize 0x2000 -sram_size 0x20000 +dev_type STM32H7Ax_H7Bx +ref_manual_id 0455 +chip_id 0x480 // STLINK_CHIPID_STM32_H7Ax +flash_type 10 // STLINK_FLASH_TYPE_H7 +flash_size_reg 0x08fff80c +flash_pagesize 0x2000 // 8 KB +sram_size 0x20000 // 128 KB "DTCM" bootrom_base 0x1ff00000 -bootrom_size 0x20000 -option_base 0x5200201c -option_size 0x2c -flags dualbank swo - +bootrom_size 0x20000 // 128 KB +option_base 0x5200201c // STM32_H7_OPTION_BYTES_BASE +option_size 0x2c // 44 B +flags swo dualbank diff --git a/config/chips/L01x_L02x.chip b/config/chips/L01x_L02x.chip deleted file mode 100644 index c3d2074b9..000000000 --- a/config/chips/L01x_L02x.chip +++ /dev/null @@ -1,13 +0,0 @@ -# Chip-ID file for L01x/L02x -# -chip_id 0x457 -description L01x/L02x -flash_type 5 -flash_pagesize 0x80 -sram_size 0x2000 -bootrom_base 0x1ff00000 -bootrom_size 0x2000 -option_base 0x0 -option_size 0x0 -flags none - diff --git a/config/chips/L0xx_Cat_2.chip b/config/chips/L0xx_Cat_2.chip deleted file mode 100644 index 47183b8ef..000000000 --- a/config/chips/L0xx_Cat_2.chip +++ /dev/null @@ -1,13 +0,0 @@ -# Chip-ID file for L0xx Cat.2 -# -chip_id 0x425 -description L0xx Cat.2 -flash_type 5 -flash_pagesize 0x80 -sram_size 0x2000 -bootrom_base 0x1ff0000 -bootrom_size 0x1000 -option_base 0x1ff80000 -option_size 0x14 -flags none - diff --git a/config/chips/L0xx_Cat_3.chip b/config/chips/L0xx_Cat_3.chip deleted file mode 100644 index 6d9fcc105..000000000 --- a/config/chips/L0xx_Cat_3.chip +++ /dev/null @@ -1,13 +0,0 @@ -# Chip-ID file for L0xx Cat.3 -# -chip_id 0x417 -description L0xx Cat.3 -flash_type 5 -flash_pagesize 0x80 -sram_size 0x2000 -bootrom_base 0x1ff0000 -bootrom_size 0x1000 -option_base 0x1ff80000 -option_size 0x14 -flags none - diff --git a/config/chips/L0xx_Cat_5.chip b/config/chips/L0xx_Cat_5.chip deleted file mode 100644 index 545c1c2ef..000000000 --- a/config/chips/L0xx_Cat_5.chip +++ /dev/null @@ -1,13 +0,0 @@ -# Chip-ID file for L0xx Cat.5 -# -chip_id 0x447 -description L0xx Cat.5 -flash_type 5 -flash_pagesize 0x80 -sram_size 0x5000 -bootrom_base 0x1ff0000 -bootrom_size 0x2000 -option_base 0x1ff80000 -option_size 0x14 -flags dualbank - diff --git a/config/chips/L0xxx_Cat_1.chip b/config/chips/L0xxx_Cat_1.chip new file mode 100644 index 000000000..1dd8a1acb --- /dev/null +++ b/config/chips/L0xxx_Cat_1.chip @@ -0,0 +1,14 @@ +# Chip-ID file for STM32L0xxx (Cat.1) device (L010x3 / L010x4 / L011x / L021x) +# +dev_type STM32L0xxx_Cat_1 +ref_manual_id 0451 // also RM0377 +chip_id 0x457 // STLINK_CHIPID_STM32_L011 +flash_type 5 // STLINK_FLASH_TYPE_L0 +flash_size_reg 0x1ff8007c +flash_pagesize 0x80 // 128 B +sram_size 0x2000 // 8 KB +bootrom_base 0x1ff00000 +bootrom_size 0x2000 // 8 KB +option_base 0x1ff80000 // STM32_L0_OPTION_BYTES_BASE +option_size 0x20 // 32 B +flags none diff --git a/config/chips/L0xxx_Cat_2.chip b/config/chips/L0xxx_Cat_2.chip new file mode 100644 index 000000000..58d6439ba --- /dev/null +++ b/config/chips/L0xxx_Cat_2.chip @@ -0,0 +1,14 @@ +# Chip-ID file for STM32L0xxx (Cat.2) device (L010x6 / L031x / L041x) +# +dev_type STM32L0xxx_Cat_2 +ref_manual_id 0451 // also RM0377 +chip_id 0x425 // STLINK_CHIPID_STM32_L0_CAT2 +flash_type 5 // STLINK_FLASH_TYPE_L0 +flash_size_reg 0x1ff8007c +flash_pagesize 0x80 // 128 B +sram_size 0x2000 // 8 KB +bootrom_base 0x1ff00000 +bootrom_size 0x1000 // 4 KB +option_base 0x1ff80000 // STM32_L0_OPTION_BYTES_BASE +option_size 0x20 // 32 B +flags none diff --git a/config/chips/L0xxx_Cat_3.chip b/config/chips/L0xxx_Cat_3.chip new file mode 100644 index 000000000..406c1a037 --- /dev/null +++ b/config/chips/L0xxx_Cat_3.chip @@ -0,0 +1,14 @@ +# Chip-ID file for STM32L0xxx (Cat.3) device (L010x8 / L051x / L053x / L063x) +# +dev_type STM32L0xxx_Cat_3 +ref_manual_id 0451 // also RM0367 & RM0377 +chip_id 0x417 // STLINK_CHIPID_STM32_L0 +flash_type 5 // STLINK_FLASH_TYPE_L0 +flash_size_reg 0x1ff8007c +flash_pagesize 0x80 // 128 B +sram_size 0x2000 // 8 KB +bootrom_base 0x1ff00000 +bootrom_size 0x1000 // 4 KB +option_base 0x1ff80000 // STM32_L0_OPTION_BYTES_BASE +option_size 0x20 // 32 B +flags none diff --git a/config/chips/L0xxx_Cat_5.chip b/config/chips/L0xxx_Cat_5.chip new file mode 100644 index 000000000..1a0c387a7 --- /dev/null +++ b/config/chips/L0xxx_Cat_5.chip @@ -0,0 +1,14 @@ +# Chip-ID file for STM32L0xxx (Cat.5) device (L010xB / L071x / L081x / L073x / L083x) +# +dev_type STM32L0xxx_Cat_5 +ref_manual_id 0451 // also RM0367 & RM0377 +chip_id 0x447 // STLINK_CHIPID_STM32_L0_CAT5 +flash_type 5 // STLINK_FLASH_TYPE_L0 +flash_size_reg 0x1ff8007c +flash_pagesize 0x80 // 128 B +sram_size 0x5000 // 20 KB +bootrom_base 0x1ff00000 +bootrom_size 0x2000 // 8 KB +option_base 0x1ff80000 // STM32_L0_OPTION_BYTES_BASE +option_size 0x20 // 32 B +flags dualbank diff --git a/config/chips/L5x5.chip b/config/chips/L5x5.chip new file mode 100644 index 000000000..ce268148b --- /dev/null +++ b/config/chips/L5x5.chip @@ -0,0 +1,15 @@ +# Chip-ID file for STM32L5x2 device +# +dev_type STM32L5x2 +ref_manual_id 0438 +chip_id 0x0 // (temporary setting only!) +flash_type 0 // (temporary setting only!) +flash_size_reg 0x0bfa07a0 +flash_pagesize 0x2000 // 8 KB +sram_size 0x40000 // 256 KB +bootrom_base 0x0bf90000 +bootrom_size 0x8000 // 32 KB +option_base 0x0 +option_size 0x0 +flags none + diff --git a/config/chips/U5x5.chip b/config/chips/U5x5.chip new file mode 100644 index 000000000..177359cc3 --- /dev/null +++ b/config/chips/U5x5.chip @@ -0,0 +1,15 @@ +# Chip-ID file for STM32U5x5 device +# +dev_type STM32U5x5 +ref_manual_id 0456 +chip_id 0x0 // (temporary setting only!) +flash_type 0 // (temporary setting only!) +flash_size_reg 0x0bfa07a0 +flash_pagesize 0x2000 // 8 KB +sram_size 0xc4800 // 786 KB +bootrom_base 0x0bf90000 +bootrom_size 0x8000 // 32 KB +option_base 0x0 +option_size 0x0 +flags none + diff --git a/config/chips/WBx0_WBx5.chip b/config/chips/WBx0_WBx5.chip new file mode 100644 index 000000000..ba5fee778 --- /dev/null +++ b/config/chips/WBx0_WBx5.chip @@ -0,0 +1,14 @@ +# Chip-ID file for STM32WBx0 / STM32WBx5 device +# +dev_type STM32WBx0_WBx5 +ref_manual_id 0434 // also RM0471 +chip_id 0x495 // STLINK_CHIPID_STM32_WB55 +flash_type 9 // STLINK_FLASH_TYPE_WB +flash_size_reg 0x1fff75e0 +flash_pagesize 0x1000 // 4 KB +sram_size 0x40000 // 256 KB +bootrom_base 0x1fff0000 +bootrom_size 0x7000 // 28 KB +option_base 0x1fff8000 +option_size 0x80 // 128 B +flags swo diff --git a/config/chips/WBx5_WBx0.chip b/config/chips/WBx5_WBx0.chip deleted file mode 100644 index 5bd2501e6..000000000 --- a/config/chips/WBx5_WBx0.chip +++ /dev/null @@ -1,14 +0,0 @@ -# Chip-ID file for STM32WBx0 device (STM32WB55xx, STM32WB35xx, STM32WB50CG, STM32WB30CE) -# -dev_type STM32WBx0 device -ref_manual_id 0434 // also RM0471 -chip_id 0x495 // STLINK_CHIPID_STM32_WB55 -flash_type 9 // STLINK_FLASH_TYPE_WB -flash_size_reg 0x1fff75e0 -flash_pagesize 0x1000 // 4k -sram_size 0x40000 -bootrom_base 0x1fff0000 -bootrom_size 0x7000 -option_base 0x0 -option_size 0x0 -flags swo diff --git a/config/chips/WLEx.chip b/config/chips/WLx5.chip similarity index 54% rename from config/chips/WLEx.chip rename to config/chips/WLx5.chip index e9b6248f6..2dc9ce648 100644 --- a/config/chips/WLEx.chip +++ b/config/chips/WLx5.chip @@ -1,14 +1,14 @@ # Chip-ID file for STM32WLEx device # -dev_type STM32WLEx device +dev_type STM32WLEx ref_manual_id 0033 chip_id 0x497 // STLINK_CHIPID_STM32_WLE flash_type 9 // STLINK_FLASH_TYPE_WB flash_size_reg 0x1fff75e0 -flash_pagesize 0x800 // 2k -sram_size 0x10000 +flash_pagesize 0x800 // 2 KB +sram_size 0x10000 // 64 KB bootrom_base 0x1fff0000 -bootrom_size 0x7000 -option_base 0x0 -option_size 0x0 +bootrom_size 0x7000 // 28 KB +option_base 0x1fffc000 +option_size 0x10 // 16 B flags swo diff --git a/config/chips/unknown_device.chip b/config/chips/unknown_device.chip index 8f3772e53..1b74f22fa 100644 --- a/config/chips/unknown_device.chip +++ b/config/chips/unknown_device.chip @@ -1,6 +1,6 @@ # Chip-ID file for unknown device # -dev_type unknown device +dev_type unknown ref_manual_id 0000 chip_id 0x0 // STLINK_CHIPID_UNKNOWN flash_type 0 // STLINK_FLASH_TYPE_UNKNOWN diff --git a/inc/stm32.h b/inc/stm32.h index 21da2f563..15e0ff147 100644 --- a/inc/stm32.h +++ b/inc/stm32.h @@ -16,19 +16,24 @@ /* Constant STM32 memory map figures */ #define STM32_SRAM_BASE ((uint32_t)0x20000000) #define STM32_FLASH_BASE ((uint32_t)0x08000000) + #define STM32_F1_FLASH_BANK2_BASE ((uint32_t)0x08080000) + #define STM32_H7_FLASH_BANK2_BASE ((uint32_t)0x08100000) -#define STM32_F2_OPTION_BYTES_BASE ((uint32_t)0x1FFFC000) #define STM32_F4_OPTION_BYTES_BASE ((uint32_t)0x40023C14) -#define STM32_F7_OPTION_BYTES_BASE ((uint32_t)0x1FFF0000) + #define STM32_H7_OPTION_BYTES_BASE ((uint32_t)0x5200201C) +#define STM32_L0_OPTION_BYTES_BASE ((uint32_t)0x1FF80000) +#define STM32_L1_OPTION_BYTES_BASE ((uint32_t)0x1FF80000) + +#define STM32_F7_OPTION_BYTES_BASE ((uint32_t)0x1FFF0000) + #define STM32_G0_OPTION_BYTES_BASE ((uint32_t)0x1FFF7800) #define STM32_L4_OPTION_BYTES_BASE ((uint32_t)0x1FFF7800) -#define STM32_L0_OPTION_BYTES_BASE ((uint32_t)0x1FF80000) -#define STM32_L1_OPTION_BYTES_BASE ((uint32_t)0x1FF80000) +#define STM32_F2_OPTION_BYTES_BASE ((uint32_t)0x1FFFC000) #define STM32_F0_OPTION_BYTES_BASE ((uint32_t)0x1FFFF800) #define STM32_F1_OPTION_BYTES_BASE ((uint32_t)0x1FFFF800) diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index 3dd82a1b2..213d43f8c 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -28,8 +28,8 @@ void dump_a_chip (FILE *fp, struct stlink_chipid_params *dev) { fprintf(fp, "# Reference Manual: RM%s\n", dev->ref_manual_id); fprintf(fp, "#\n"); fprintf(fp, "chip_id 0x%x\n", dev->chip_id); - fprintf(fp, "flash_type %d\n", dev->flash_type); - fprintf(fp, "flash_size_reg %x\n", dev->flash_size_reg); + fprintf(fp, "flash_type %d\n", dev->flash_type); + fprintf(fp, "flash_size_reg 0x%x\n", dev->flash_size_reg); fprintf(fp, "flash_pagesize 0x%x\n", dev->flash_pagesize); fprintf(fp, "sram_size 0x%x\n", dev->sram_size); fprintf(fp, "bootrom_base 0x%x\n", dev->bootrom_base); @@ -42,8 +42,8 @@ void dump_a_chip (FILE *fp, struct stlink_chipid_params *dev) { static int chipid_params_eq(const struct stlink_chipid_params *p1, const struct stlink_chipid_params *p2) { return p1->chip_id == p2->chip_id && - p1->description && p2->description && - strcmp(p1->description, p2->description) == 0 && + p1->dev_type && p2->dev_type && + strcmp(p1->dev_type, p2->dev_type) == 0 && p1->flash_type == p2->flash_type && p1->flash_size_reg == p2->flash_size_reg && p1->flash_pagesize == p2->flash_pagesize && @@ -205,8 +205,8 @@ void dump_chips (void) { fprintf(fp, "# Reference Manual: RM%s\n", ts->ref_manual_id); fprintf(fp, "#\n"); fprintf(fp, "chip_id %x\n", ts->chip_id); - fprintf(fp, "flash_type %x\n", ts->flash_type); - fprintf(fp, "flash_size_reg %x\n", ts->flash_size_reg); + fprintf(fp, "flash_type %x\n", ts->flash_type); + fprintf(fp, "flash_size_reg %x\n", ts->flash_size_reg); fprintf(fp, "flash_pagesize %x\n", ts->flash_pagesize); fprintf(fp, "sram_size %x\n", ts->sram_size); fprintf(fp, "bootrom_base %x\n", ts->bootrom_base); diff --git a/src/stlink-lib/chipid_db_old.h b/src/stlink-lib/chipid_db_old.h index bc6491ad4..b86b13289 100644 --- a/src/stlink-lib/chipid_db_old.h +++ b/src/stlink-lib/chipid_db_old.h @@ -6,123 +6,6 @@ // config/chips/*.chip file. static struct stlink_chipid_params devices[] = { - { - // STM32F76x/F77x - // RM0410 - .chip_id = STLINK_CHIPID_STM32_F76xxx, - .dev_type = "F76x/F77x", - .flash_type = STLINK_FLASH_TYPE_F7, - .flash_size_reg = 0x1ff0f442, // section 45.2 - .flash_pagesize = 0x800, // No flash pages - .sram_size = 0x80000, // "SRAM" byte size in hex from - .bootrom_base = 0x00200000, // "System memory" starting address from - .bootrom_size = 0xEDC0, - .option_base = STM32_F7_OPTION_BYTES_BASE, /* Used for reading back the option - bytes, writing uses FLASH_F7_OPTCR - and FLASH_F7_OPTCR1 */ - .option_size = 0x20, - .flags = CHIP_F_HAS_DUAL_BANK | CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32F74x/F75x - // RM0385, DS10916 - .chip_id = STLINK_CHIPID_STM32_F7, - .dev_type = "F74x/F75x", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1ff0f442, // section 41.2 - .flash_pagesize = 0x800, // No flash pages - .sram_size = 0x50000, // "SRAM" byte size in hex from DS Fig 18 - .bootrom_base = 0x00100000, // "System memory" starting address from DS Fig 18 - .bootrom_size = 0xEDC0, // "System memory" byte size in hex from DS Fig 18 - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32F72x/F73x - // RM0431 - .chip_id = STLINK_CHIPID_STM32_F72xxx, - .dev_type = "F72x/F73x", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1ff07a22, // section 35.2 - .flash_pagesize = 0x800, // No flash pages - .sram_size = 0x40000, // "SRAM" byte size in hex from DS Fig 24 - .bootrom_base = 0x00100000, // "System memory" starting address from DS Fig 24 - .bootrom_size = 0xEDC0, // "System memory" byte size in hex from DS Fig 24 - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32F4x5/F4x7 - // RM0090 (rev 2) - .chip_id = STLINK_CHIPID_STM32_F4, - .dev_type = "F4x5/F4x7", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1FFF7A22, - .flash_pagesize = 0x4000, - .sram_size = 0x30000, - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7800, - .option_base = STM32_F4_OPTION_BYTES_BASE, - .option_size = 4, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32F46x/F47x - // RM0090 (rev 2) - .chip_id = STLINK_CHIPID_STM32_F4_DSI, - .dev_type = "F46x/F47x", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1FFF7A22, - .flash_pagesize = 0x4000, - .sram_size = 0x40000, - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7800, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32F42x/F43x - // RM0090 (rev 2) - .chip_id = STLINK_CHIPID_STM32_F4_HD, - .dev_type = "F42x/F43x", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1FFF7A22, - .flash_pagesize = 0x4000, - .sram_size = 0x40000, - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7800, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - .chip_id = STLINK_CHIPID_STM32_F4_LP, - .dev_type = "F401xB/C", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1FFF7A22, - .flash_pagesize = 0x4000, - .sram_size = 0x10000, - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7800, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - .chip_id = STLINK_CHIPID_STM32_F411xx, - .dev_type = "F411xC/E", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1FFF7A22, - .flash_pagesize = 0x4000, - .sram_size = 0x20000, - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7800, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - .chip_id = STLINK_CHIPID_STM32_F4_DE, - .dev_type = "F401xD/E", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1FFF7A22, - .flash_pagesize = 0x4000, - .sram_size = 0x18000, - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7800, - .flags = CHIP_F_HAS_SWO_TRACING, - }, { // STM32L100/L15x/L16x Cat.1 // RM0038 @@ -191,130 +74,137 @@ static struct stlink_chipid_params devices[] = { .flags = CHIP_F_HAS_SWO_TRACING, }, { - // STM32F446x family - // RM0390 - .chip_id = STLINK_CHIPID_STM32_F446, - .dev_type = "F446", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1fff7a22, - .flash_pagesize = 0x20000, - .sram_size = 0x20000, - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7800, - .option_base = 0x1FFFC000, + // STM32L47x/L48x + // RM0351 + .chip_id = STLINK_CHIPID_STM32_L4, + .dev_type = "L47x/L48x", + .flash_type = STLINK_FLASH_TYPE_L4, + .flash_size_reg = 0x1FFF75e0, // "Flash size data register" (sec 45.2, page 1671) + .flash_pagesize = 0x800, // 2k (sec 3.2, page 78; also appears in sec 3.3.1 + // and tables 4-6 on pages 79-81) + // SRAM1 is "up to" 96k in the standard Cortex-M memory map; + // SRAM2 is 32k mapped at at 0x10000000 (sec 2.3, page 73 for + // sizes; table 2, page 74 for SRAM2 location) + .sram_size = 0x18000, + .bootrom_base = 0x1fff0000, // Tables 4-6, pages 80-81 (Bank 1 system memory) + .bootrom_size = 0x7000, // 28k (per bank), same source as base + .option_base = STM32_L4_OPTION_BYTES_BASE, .option_size = 4, .flags = CHIP_F_HAS_SWO_TRACING, }, { - // STM32F410 - // RM0401 - .chip_id = STLINK_CHIPID_STM32_F410, - .dev_type = "F410", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1fff7a22, - .flash_pagesize = 0x4000, - .sram_size = 0x8000, - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7800, - .flags = CHIP_F_HAS_SWO_TRACING, + // STM32L4RX + // RM0432 + .chip_id = STLINK_CHIPID_STM32_L4Rx, + .dev_type = "L4Rx", + .flash_type = STLINK_FLASH_TYPE_L4, + .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 58.2, page 2274) + .flash_pagesize = 0x1000, // 4k, section 3.3, pg 117-120 + // TODO: flash_pagesize can be 8k depend on the dual-bank mode and flash size + .sram_size = 0xa0000, // 192k (SRAM1) + 64k SRAM2 + 384k SRAM3 = 640k, or 0xA0000 + .bootrom_base = 0x1fff0000, // 3.3.1, pg 117 + .bootrom_size = 0x7000, // 28k (per bank), same source as base (pg 117) + .flags = CHIP_F_HAS_DUAL_BANK | CHIP_F_HAS_SWO_TRACING, }, { - // STM32F303xB/C, STM32F358, STM32F302xBxC - // RM0316, RM0365 - .chip_id = STLINK_CHIPID_STM32_F3, - .dev_type = "F302/F303/F358", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7cc, - .flash_pagesize = 0x800, - .sram_size = 0xa000, - .bootrom_base = 0x1ffff000, - .bootrom_size = 0x800, - .option_base = STM32_F0_OPTION_BYTES_BASE, - .option_size = 16, - .flags = CHIP_F_HAS_SWO_TRACING, + // STM32L4PX + // RM0432 + .chip_id = STLINK_CHIPID_STM32_L4PX, + .dev_type = "L4Px", + .flash_type = STLINK_FLASH_TYPE_L4, + .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 58.2, page 2274) + .flash_pagesize = 0x1000, // 4k, section 3.3, pg 117-120 + // TODO: flash_pagesize can be 8k depend on the dual-bank mode and flash size + .sram_size = 0xa0000, // 192k (SRAM1) + 64k SRAM2 + 384k SRAM3 = 640k, or 0xA0000 + .bootrom_base = 0x1fff0000, // 3.3.1, pg 117 + .bootrom_size = 0x7000, // 28k (per bank), same source as base (pg 117) + .flags = CHIP_F_HAS_DUAL_BANK | CHIP_F_HAS_SWO_TRACING, }, { - // STM32F373Cx/Rx/Vx, STM32F378Cx/Rx/Vx - // RM0313 - .chip_id = STLINK_CHIPID_STM32_F37x, - .dev_type = "F37x", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7cc, - .flash_pagesize = 0x800, - .sram_size = 0xa000, - .bootrom_base = 0x1ffff000, - .bootrom_size = 0x800, - .option_base = STM32_F0_OPTION_BYTES_BASE, - .option_size = 16, + // STLINK_CHIPID_STM32_L41x_L42x + // RM0394 (rev 4), DS12469 (rev 5) + .chip_id = STLINK_CHIPID_STM32_L41x_L42x, + .dev_type = "L41x/L42x", + .flash_type = STLINK_FLASH_TYPE_L4, + .flash_size_reg = 0x1fff75e0, // "Flash size data register" (RM0394, + // sec 47.2, page 1586) + .flash_pagesize = 0x800, // 2k (DS12469, sec 3.4, page 17) + // SRAM1 is 32k at 0x20000000 + // SRAM2 is 8k at 0x10000000 and 0x20008000 + // (DS12469, sec 3.5, page 18) + .sram_size = 0xa000, // 40k (DS12469, sec 3.5, page 18) + .bootrom_base = 0x1fff0000, // System Memory (RM0394, sec 3.3.1, table 8) + .bootrom_size = 0x7000, // 28k, same source as base .flags = CHIP_F_HAS_SWO_TRACING, }, { - // STM32F07x - // RM0091 - .chip_id = STLINK_CHIPID_STM32_F0_CAN, - .dev_type = "F07x", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) - .flash_pagesize = 0x800, // Page sizes listed in Table 4 - .sram_size = 0x4000, // "SRAM" byte size in hex from Table 2 - .bootrom_base = 0x1fffC800, // "System memory" starting address from Table 2 - .bootrom_size = 0x3000, // "System memory" byte size in hex from Table 2 - .option_base = STM32_F0_OPTION_BYTES_BASE, - .option_size = 16, + // STLINK_CHIPID_STM32_L43x_L44x + // RM0392 + .chip_id = STLINK_CHIPID_STM32_L43x_L44x, + .dev_type = "L43x/L44x", + .flash_type = STLINK_FLASH_TYPE_L4, + .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 43.2, page 1410) + .flash_pagesize = 0x800, // 2k (sec 3.2, page 74; also appears in sec 3.3.1 + // and tables 7-8 on pages 75-76) + // SRAM1 is "up to" 64k in the standard Cortex-M memory map; + // SRAM2 is 16k mapped at 0x10000000 (sec 2.3, page 73 for + // sizes; table 2, page 74 for SRAM2 location) + .sram_size = 0xc000, + .bootrom_base = 0x1fff0000, // Tables 4-6, pages 80-81 (Bank 1 system memory) + .bootrom_size = 0x7000, // 28k (per bank), same source as base + .option_base = STM32_L4_OPTION_BYTES_BASE, + .option_size = 4, + .flags = CHIP_F_HAS_SWO_TRACING, }, { - // STM32F05x - // RM0091 - .chip_id = STLINK_CHIPID_STM32_F0, - .dev_type = "F05x", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) - .flash_pagesize = 0x400, // Page sizes listed in Table 4 - .sram_size = 0x2000, // "SRAM" byte size in hex from Table 2 - .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2 - .bootrom_size = 0xC00, // "System memory" byte size in hex from Table 2 - .option_base = STM32_F0_OPTION_BYTES_BASE, - .option_size = 16, - }, - { - // STM32F412 - // RM0402 - .chip_id = STLINK_CHIPID_STM32_F412, - .dev_type = "F412", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1FFF7A22, // "Flash size data register" (pg1135) - .flash_pagesize = 0x4000, // Table 5. Flash module organization ? - .sram_size = 0x40000, // "SRAM" byte size in hex from Table 4 - .bootrom_base = 0x1FFF0000, // "System memory" starting address from Table 4 - .bootrom_size = 0x7800, // "System memory" byte size in hex from Table 4 + // STLINK_CHIPID_STM32_L496x_L4A6x + // RM0351 (rev 5) + .chip_id = STLINK_CHIPID_STM32_L496x_L4A6x, + .dev_type = "L496x/L4A6x", + .flash_type = STLINK_FLASH_TYPE_L4, + .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 49.2, page 1809) + .flash_pagesize = 0x800, // Page erase (2 Kbyte) (sec 3.2, page 93) + // SRAM1 is 256k at 0x20000000 + // SRAM2 is 64k at 0x20040000 (sec 2.2.1, fig 2, page 74) + .sram_size = 0x40000, // Embedded SRAM (sec 2.4, page 84) + .bootrom_base = 0x1fff0000, // System Memory (Bank 1) (sec 3.3.1) + .bootrom_size = 0x7000, // 28k (per bank), same source as base + .option_base = STM32_L4_OPTION_BYTES_BASE, + .option_size = 4, .flags = CHIP_F_HAS_SWO_TRACING, }, { - // STM32F413/F423 - // RM0430 (rev 2) - .chip_id = STLINK_CHIPID_STM32_F413, - .dev_type = "F413/F423", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1FFF7A22, // "Flash size data register" Section 35.2 - .flash_pagesize = 0x4000, // Table 5. Flash module organization (variable sector - // sizes, but 0x4000 is smallest) - .sram_size = 0x50000, // "SRAM" byte size in hex from Figure 2 (Table 4 - // only says 0x40000) - .bootrom_base = 0x1FFF0000, // "System memory" starting address from Table 4 - .bootrom_size = 0x7800, // "System memory" byte size in hex from Table 4 + // STLINK_CHIPID_STM32_L45x_L46x + // RM0394 (updated version of RM0392?) + .chip_id = STLINK_CHIPID_STM32_L45x_L46x, + .dev_type = "L45x/46x", + .flash_type = STLINK_FLASH_TYPE_L4, + .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 45.2, page 1463) + .flash_pagesize = 0x800, // 2k (sec 3.2, page 73; also appears in sec 3.3.1 + // and tables 7 on pages 73-74) + // SRAM1 is 128k at 0x20000000; + // SRAM2 is 32k mapped at 0x10000000 (sec 2.4.2, table 3-4, + // page 68, also fig 2 on page 63) + .sram_size = 0x20000, + .bootrom_base = 0x1fff0000, // Tables 6, pages 71-72 (Bank 1 system + // memory, also fig 2 on page 63) + .bootrom_size = 0x7000, // 28k (per bank), same source as base .flags = CHIP_F_HAS_SWO_TRACING, }, +// ######################################################################## +// ######################################################################## +// ######################################################################## { - // STM32F09x + // STM32F03x // RM0091 - .chip_id = STLINK_CHIPID_STM32_F09x, - .dev_type = "F09x", + .chip_id = STLINK_CHIPID_STM32_F0xx_SMALL, + .dev_type = "F03x", .flash_type = STLINK_FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) - .flash_pagesize = 0x800, // Page sizes listed in Table 4 (pg 56) - .sram_size = 0x8000, // "SRAM" byte size in hex from Table 2 (pg 50) - .bootrom_base = 0x1fffd800, // "System memory" starting address from Table 2 - .bootrom_size = 0x2000, // "System memory" byte size in hex from Table 2 + .flash_pagesize = 0x400, // Page sizes listed in Table 4 + .sram_size = 0x1000, // "SRAM" byte size in hex from Table 2 + .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2 + .bootrom_size = 0xC00, // "System memory" byte size in hex from Table 2 .option_base = STM32_F0_OPTION_BYTES_BASE, .option_size = 16, }, @@ -333,19 +223,165 @@ static struct stlink_chipid_params devices[] = { .option_size = 16, }, { - // STM32F03x + // STM32F05x // RM0091 - .chip_id = STLINK_CHIPID_STM32_F0xx_SMALL, - .dev_type = "F03x", + .chip_id = STLINK_CHIPID_STM32_F0, + .dev_type = "F05x", .flash_type = STLINK_FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) .flash_pagesize = 0x400, // Page sizes listed in Table 4 - .sram_size = 0x1000, // "SRAM" byte size in hex from Table 2 + .sram_size = 0x2000, // "SRAM" byte size in hex from Table 2 .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2 .bootrom_size = 0xC00, // "System memory" byte size in hex from Table 2 .option_base = STM32_F0_OPTION_BYTES_BASE, .option_size = 16, }, + { + // STM32F07x + // RM0091 + .chip_id = STLINK_CHIPID_STM32_F0_CAN, + .dev_type = "F07x", + .flash_type = STLINK_FLASH_TYPE_F0, + .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) + .flash_pagesize = 0x800, // Page sizes listed in Table 4 + .sram_size = 0x4000, // "SRAM" byte size in hex from Table 2 + .bootrom_base = 0x1fffC800, // "System memory" starting address from Table 2 + .bootrom_size = 0x3000, // "System memory" byte size in hex from Table 2 + .option_base = STM32_F0_OPTION_BYTES_BASE, + .option_size = 16, + }, + { + // STM32F09x + // RM0091 + .chip_id = STLINK_CHIPID_STM32_F09x, + .dev_type = "F09x", + .flash_type = STLINK_FLASH_TYPE_F0, + .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) + .flash_pagesize = 0x800, // Page sizes listed in Table 4 (pg 56) + .sram_size = 0x8000, // "SRAM" byte size in hex from Table 2 (pg 50) + .bootrom_base = 0x1fffd800, // "System memory" starting address from Table 2 + .bootrom_size = 0x2000, // "System memory" byte size in hex from Table 2 + .option_base = STM32_F0_OPTION_BYTES_BASE, + .option_size = 16, + }, + { + // STM32F1xx low- and medium-density value line devices + // RM0041 + .chip_id = STLINK_CHIPID_STM32_F1_VL_MD_LD, + .dev_type = "F1xx Value Line", + .flash_type = STLINK_FLASH_TYPE_F0, + .flash_size_reg = 0x1ffff7e0, + .flash_pagesize = 0x400, + .sram_size = 0x2000, // 0x1000 for low density devices + .bootrom_base = 0x1ffff000, + .bootrom_size = 0x800, + .option_base = STM32_F0_OPTION_BYTES_BASE, + .option_size = 16, + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + // STM32F1xx high-density value line devices + // RM0041 + .chip_id = STLINK_CHIPID_STM32_F1_VL_HD, + .dev_type = "F1xx High-density value line", + .flash_type = STLINK_FLASH_TYPE_F0, + .flash_size_reg = 0x1ffff7e0, + .flash_pagesize = 0x800, + .sram_size = 0x8000, + .bootrom_base = 0x1ffff000, + .bootrom_size = 0x800, + .option_base = STM32_F0_OPTION_BYTES_BASE, + .option_size = 16, + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + // STM32F1xx low-density devices + // RM0008 + .chip_id = STLINK_CHIPID_STM32_F1_LD, + .dev_type = "F1 Low-density device", + .flash_type = STLINK_FLASH_TYPE_F0, + .flash_size_reg = 0x1ffff7e0, + .flash_pagesize = 0x400, + .sram_size = 0x2800, + .bootrom_base = 0x1ffff000, + .bootrom_size = 0x800, + .option_base = STM32_F0_OPTION_BYTES_BASE, + .option_size = 16, + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + // STM32F1xx medium-density devices + // RM0008 + .chip_id = STLINK_CHIPID_STM32_F1_MD, + .dev_type = "F1xx Medium-density", + .flash_type = STLINK_FLASH_TYPE_F0, + .flash_size_reg = 0x1ffff7e0, + .flash_pagesize = 0x400, + .sram_size = 0x5000, + .bootrom_base = 0x1ffff000, // 2.3.3 "Embedded Flash memory" + .bootrom_size = 0x800, + .option_base = STM32_F0_OPTION_BYTES_BASE, + .option_size = 16, + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + // STM32F1xx high-density devices + // RM0008 + .chip_id = STLINK_CHIPID_STM32_F1_HD, + .dev_type = "F1xx High-density", + .flash_type = STLINK_FLASH_TYPE_F0, + .flash_size_reg = 0x1ffff7e0, + .flash_pagesize = 0x800, + .sram_size = 0x10000, + .bootrom_base = 0x1ffff000, + .bootrom_size = 0x800, + .option_base = STM32_F0_OPTION_BYTES_BASE, + .option_size = 16, + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + // STM32F1xx XL-density devices + // RM0008 + .chip_id = STLINK_CHIPID_STM32_F1_XLD, + .dev_type = "F1xx XL-density", + .flash_type = STLINK_FLASH_TYPE_F1_XL, + .flash_size_reg = 0x1ffff7e0, + .flash_pagesize = 0x800, + .sram_size = 0x18000, + .bootrom_base = 0x1fffe000, + .bootrom_size = 0x1800, + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + // STM32F1xx connectivity devices + // RM0008 + .chip_id = STLINK_CHIPID_STM32_F1_CONN, + .dev_type = "F1xx CL", + .flash_type = STLINK_FLASH_TYPE_F0, + .flash_size_reg = 0x1ffff7e0, + .flash_pagesize = 0x800, + .sram_size = 0x10000, + .bootrom_base = 0x1fffb000, + .bootrom_size = 0x4800, + .option_base = STM32_F0_OPTION_BYTES_BASE, + .option_size = 16, + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + // STM32F205xx, STM32F207xx, STM32F215xx, STM32F217xx + // RM0033 (rev 5) + .chip_id = STLINK_CHIPID_STM32_F2, + .dev_type = "F2xx", + .flash_type = STLINK_FLASH_TYPE_F4, + .flash_size_reg = 0x1fff7a22, + .flash_pagesize = 0x20000, + .sram_size = 0x20000, + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x7800, + .option_base = 0x1FFFC000, + .option_size = 4, + .flags = CHIP_F_HAS_SWO_TRACING, + }, { // STM32F301x6/8, STM32F302x6x8, STM32F318x8 // RM0366, RM0365 @@ -362,50 +398,37 @@ static struct stlink_chipid_params devices[] = { .flags = CHIP_F_HAS_SWO_TRACING, }, { - // STM32L0xx Category 3 - // RM0367, RM0377, RM0451 - .chip_id = STLINK_CHIPID_STM32_L0, - .dev_type = "L0xx Cat.3", - .flash_type = STLINK_FLASH_TYPE_L0, - .flash_size_reg = 0x1ff8007c, - .flash_pagesize = 0x80, - .sram_size = 0x2000, - .bootrom_base = 0x1ff0000, - .bootrom_size = 0x1000, - .option_base = STM32_L0_OPTION_BYTES_BASE, - .option_size = 20, + // STM32F302xBxC, STM32F303xB/C, STM32F358 + // RM0316, RM0365 + .chip_id = STLINK_CHIPID_STM32_F3, + .dev_type = "F302/F303/F358", + .flash_type = STLINK_FLASH_TYPE_F0, + .flash_size_reg = 0x1ffff7cc, + .flash_pagesize = 0x800, + .sram_size = 0xa000, + .bootrom_base = 0x1ffff000, + .bootrom_size = 0x800, + .option_base = STM32_F0_OPTION_BYTES_BASE, + .option_size = 16, + .flags = CHIP_F_HAS_SWO_TRACING, }, { - // STM32L0x Category 5 - // RM0367, RM0377, RM0451 - .chip_id = STLINK_CHIPID_STM32_L0_CAT5, - .dev_type = "L0xx Cat.5", - .flash_type = STLINK_FLASH_TYPE_L0, - .flash_size_reg = 0x1ff8007c, - .flash_pagesize = 0x80, - .sram_size = 0x5000, - .bootrom_base = 0x1ff0000, + // STM32F302xD/E, STM32F303xD/E, STM32F398xE, + // RM0316 (rev 5), RM0365 + .chip_id = STLINK_CHIPID_STM32_F303_HD, + .dev_type = "F303 high density", + .flash_type = STLINK_FLASH_TYPE_F0, + .flash_size_reg = 0x1ffff7cc, // 34.2.1 Flash size data register + .flash_pagesize = 0x800, // 4.2.1 Flash memory organization + .sram_size = 0x10000, // 3.3 Embedded SRAM + .bootrom_base = 0x1fffd800, // 3.3.2 / Table 4 System Memory .bootrom_size = 0x2000, - .option_base = STM32_L0_OPTION_BYTES_BASE, - .option_size = 20, - .flags = CHIP_F_HAS_DUAL_BANK, - }, - { - // STM32L0x Category 2 - // RM0367, RM0377 - .chip_id = STLINK_CHIPID_STM32_L0_CAT2, - .dev_type = "L0xx Cat.2", - .flash_type = STLINK_FLASH_TYPE_L0, - .flash_size_reg = 0x1ff8007c, - .flash_pagesize = 0x80, - .sram_size = 0x2000, - .bootrom_base = 0x1ff0000, - .bootrom_size = 0x1000, - .option_base = STM32_L0_OPTION_BYTES_BASE, - .option_size = 20, + .option_base = STM32_F0_OPTION_BYTES_BASE, + .option_size = 16, + .flags = CHIP_F_HAS_SWO_TRACING, }, { - // STM32F334, STM32F303x6/8, STM32F328 + // STM32F303x6/8, STM32F328, STM32F334 // RM0364, RM0316 .chip_id = STLINK_CHIPID_STM32_F334, .dev_type = "F303/F328/F334", // (RM0316 sec 33.6.1) @@ -420,149 +443,192 @@ static struct stlink_chipid_params devices[] = { .flags = CHIP_F_HAS_SWO_TRACING, }, { - // STM32F303xD/E, STM32F398xE, STM32F302xD/E - // RM0316 (rev 5), RM0365 - .chip_id = STLINK_CHIPID_STM32_F303_HD, - .dev_type = "F303 high density", + // STM32F373Cx/Rx/Vx, STM32F378Cx/Rx/Vx + // RM0313 + .chip_id = STLINK_CHIPID_STM32_F37x, + .dev_type = "F37x", .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7cc, // 34.2.1 Flash size data register - .flash_pagesize = 0x800, // 4.2.1 Flash memory organization - .sram_size = 0x10000, // 3.3 Embedded SRAM - .bootrom_base = 0x1fffd800, // 3.3.2 / Table 4 System Memory - .bootrom_size = 0x2000, + .flash_size_reg = 0x1ffff7cc, + .flash_pagesize = 0x800, + .sram_size = 0xa000, + .bootrom_base = 0x1ffff000, + .bootrom_size = 0x800, .option_base = STM32_F0_OPTION_BYTES_BASE, .option_size = 16, .flags = CHIP_F_HAS_SWO_TRACING, }, { - // STM32L47x/L48x - // RM0351 - .chip_id = STLINK_CHIPID_STM32_L4, - .dev_type = "L47x/L48x", - .flash_type = STLINK_FLASH_TYPE_L4, - .flash_size_reg = 0x1FFF75e0, // "Flash size data register" (sec 45.2, page 1671) - .flash_pagesize = 0x800, // 2k (sec 3.2, page 78; also appears in sec 3.3.1 - // and tables 4-6 on pages 79-81) - // SRAM1 is "up to" 96k in the standard Cortex-M memory map; - // SRAM2 is 32k mapped at at 0x10000000 (sec 2.3, page 73 for - // sizes; table 2, page 74 for SRAM2 location) + .chip_id = STLINK_CHIPID_STM32_F4_LP, + .dev_type = "F401xB/C", + .flash_type = STLINK_FLASH_TYPE_F4, + .flash_size_reg = 0x1FFF7A22, + .flash_pagesize = 0x4000, + .sram_size = 0x10000, + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x7800, + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + .chip_id = STLINK_CHIPID_STM32_F4_DE, + .dev_type = "F401xD/E", + .flash_type = STLINK_FLASH_TYPE_F4, + .flash_size_reg = 0x1FFF7A22, + .flash_pagesize = 0x4000, .sram_size = 0x18000, - .bootrom_base = 0x1fff0000, // Tables 4-6, pages 80-81 (Bank 1 system memory) - .bootrom_size = 0x7000, // 28k (per bank), same source as base - .option_base = STM32_L4_OPTION_BYTES_BASE, - .option_size = 4, + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x7800, .flags = CHIP_F_HAS_SWO_TRACING, }, { - // STM32L4RX - // RM0432 - .chip_id = STLINK_CHIPID_STM32_L4Rx, - .dev_type = "L4Rx", - .flash_type = STLINK_FLASH_TYPE_L4, - .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 58.2, page 2274) - .flash_pagesize = 0x1000, // 4k, section 3.3, pg 117-120 - // TODO: flash_pagesize can be 8k depend on the dual-bank mode and flash size - .sram_size = 0xa0000, // 192k (SRAM1) + 64k SRAM2 + 384k SRAM3 = 640k, or 0xA0000 - .bootrom_base = 0x1fff0000, // 3.3.1, pg 117 - .bootrom_size = 0x7000, // 28k (per bank), same source as base (pg 117) - .flags = CHIP_F_HAS_DUAL_BANK | CHIP_F_HAS_SWO_TRACING, + // STM32F410 + // RM0401 + .chip_id = STLINK_CHIPID_STM32_F410, + .dev_type = "F410", + .flash_type = STLINK_FLASH_TYPE_F4, + .flash_size_reg = 0x1fff7a22, + .flash_pagesize = 0x4000, + .sram_size = 0x8000, + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x7800, + .flags = CHIP_F_HAS_SWO_TRACING, }, { - // STM32L4PX - // RM0432 - .chip_id = STLINK_CHIPID_STM32_L4PX, - .dev_type = "L4Px", - .flash_type = STLINK_FLASH_TYPE_L4, - .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 58.2, page 2274) - .flash_pagesize = 0x1000, // 4k, section 3.3, pg 117-120 - // TODO: flash_pagesize can be 8k depend on the dual-bank mode and flash size - .sram_size = 0xa0000, // 192k (SRAM1) + 64k SRAM2 + 384k SRAM3 = 640k, or 0xA0000 - .bootrom_base = 0x1fff0000, // 3.3.1, pg 117 - .bootrom_size = 0x7000, // 28k (per bank), same source as base (pg 117) - .flags = CHIP_F_HAS_DUAL_BANK | CHIP_F_HAS_SWO_TRACING, + .chip_id = STLINK_CHIPID_STM32_F411xx, + .dev_type = "F411xC/E", + .flash_type = STLINK_FLASH_TYPE_F4, + .flash_size_reg = 0x1FFF7A22, + .flash_pagesize = 0x4000, + .sram_size = 0x20000, + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x7800, + .flags = CHIP_F_HAS_SWO_TRACING, }, { - // STLINK_CHIPID_STM32_L41x_L42x - // RM0394 (rev 4), DS12469 (rev 5) - .chip_id = STLINK_CHIPID_STM32_L41x_L42x, - .dev_type = "L41x/L42x", - .flash_type = STLINK_FLASH_TYPE_L4, - .flash_size_reg = 0x1fff75e0, // "Flash size data register" (RM0394, - // sec 47.2, page 1586) - .flash_pagesize = 0x800, // 2k (DS12469, sec 3.4, page 17) - // SRAM1 is 32k at 0x20000000 - // SRAM2 is 8k at 0x10000000 and 0x20008000 - // (DS12469, sec 3.5, page 18) - .sram_size = 0xa000, // 40k (DS12469, sec 3.5, page 18) - .bootrom_base = 0x1fff0000, // System Memory (RM0394, sec 3.3.1, table 8) - .bootrom_size = 0x7000, // 28k, same source as base + // STM32F412 + // RM0402 + .chip_id = STLINK_CHIPID_STM32_F412, + .dev_type = "F412", + .flash_type = STLINK_FLASH_TYPE_F4, + .flash_size_reg = 0x1FFF7A22, // "Flash size data register" (pg1135) + .flash_pagesize = 0x4000, // Table 5. Flash module organization ? + .sram_size = 0x40000, // "SRAM" byte size in hex from Table 4 + .bootrom_base = 0x1FFF0000, // "System memory" starting address from Table 4 + .bootrom_size = 0x7800, // "System memory" byte size in hex from Table 4 .flags = CHIP_F_HAS_SWO_TRACING, }, { - // STLINK_CHIPID_STM32_L43x_L44x - // RM0392 - .chip_id = STLINK_CHIPID_STM32_L43x_L44x, - .dev_type = "L43x/L44x", - .flash_type = STLINK_FLASH_TYPE_L4, - .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 43.2, page 1410) - .flash_pagesize = 0x800, // 2k (sec 3.2, page 74; also appears in sec 3.3.1 - // and tables 7-8 on pages 75-76) - // SRAM1 is "up to" 64k in the standard Cortex-M memory map; - // SRAM2 is 16k mapped at 0x10000000 (sec 2.3, page 73 for - // sizes; table 2, page 74 for SRAM2 location) - .sram_size = 0xc000, - .bootrom_base = 0x1fff0000, // Tables 4-6, pages 80-81 (Bank 1 system memory) - .bootrom_size = 0x7000, // 28k (per bank), same source as base - .option_base = STM32_L4_OPTION_BYTES_BASE, + // STM32F413/F423 + // RM0430 (rev 2) + .chip_id = STLINK_CHIPID_STM32_F413, + .dev_type = "F413/F423", + .flash_type = STLINK_FLASH_TYPE_F4, + .flash_size_reg = 0x1FFF7A22, // "Flash size data register" Section 35.2 + .flash_pagesize = 0x4000, // Table 5. Flash module organization (variable sector + // sizes, but 0x4000 is smallest) + .sram_size = 0x50000, // "SRAM" byte size in hex from Figure 2 (Table 4 + // only says 0x40000) + .bootrom_base = 0x1FFF0000, // "System memory" starting address from Table 4 + .bootrom_size = 0x7800, // "System memory" byte size in hex from Table 4 + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + // STM32F42x/F43x + // RM0090 (rev 2) + .chip_id = STLINK_CHIPID_STM32_F4_HD, + .dev_type = "F42x/F43x", + .flash_type = STLINK_FLASH_TYPE_F4, + .flash_size_reg = 0x1FFF7A22, + .flash_pagesize = 0x4000, + .sram_size = 0x40000, + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x7800, + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + // STM32F446x family + // RM0390 + .chip_id = STLINK_CHIPID_STM32_F446, + .dev_type = "F446", + .flash_type = STLINK_FLASH_TYPE_F4, + .flash_size_reg = 0x1fff7a22, + .flash_pagesize = 0x20000, + .sram_size = 0x20000, + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x7800, + .option_base = 0x1FFFC000, .option_size = 4, .flags = CHIP_F_HAS_SWO_TRACING, }, { - // STLINK_CHIPID_STM32_L496x_L4A6x - // RM0351 (rev 5) - .chip_id = STLINK_CHIPID_STM32_L496x_L4A6x, - .dev_type = "L496x/L4A6x", - .flash_type = STLINK_FLASH_TYPE_L4, - .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 49.2, page 1809) - .flash_pagesize = 0x800, // Page erase (2 Kbyte) (sec 3.2, page 93) - // SRAM1 is 256k at 0x20000000 - // SRAM2 is 64k at 0x20040000 (sec 2.2.1, fig 2, page 74) - .sram_size = 0x40000, // Embedded SRAM (sec 2.4, page 84) - .bootrom_base = 0x1fff0000, // System Memory (Bank 1) (sec 3.3.1) - .bootrom_size = 0x7000, // 28k (per bank), same source as base - .option_base = STM32_L4_OPTION_BYTES_BASE, + // STM32F46x/F47x + // RM0090 (rev 2) + .chip_id = STLINK_CHIPID_STM32_F4_DSI, + .dev_type = "F46x/F47x", + .flash_type = STLINK_FLASH_TYPE_F4, + .flash_size_reg = 0x1FFF7A22, + .flash_pagesize = 0x4000, + .sram_size = 0x40000, + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x7800, + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + // STM32F4x5/F4x7 + // RM0090 (rev 2) + .chip_id = STLINK_CHIPID_STM32_F4, + .dev_type = "F4x5/F4x7", + .flash_type = STLINK_FLASH_TYPE_F4, + .flash_size_reg = 0x1FFF7A22, + .flash_pagesize = 0x4000, + .sram_size = 0x30000, + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x7800, + .option_base = STM32_F4_OPTION_BYTES_BASE, .option_size = 4, .flags = CHIP_F_HAS_SWO_TRACING, }, { - // STLINK_CHIPID_STM32_L45x_L46x - // RM0394 (updated version of RM0392?) - .chip_id = STLINK_CHIPID_STM32_L45x_L46x, - .dev_type = "L45x/46x", - .flash_type = STLINK_FLASH_TYPE_L4, - .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 45.2, page 1463) - .flash_pagesize = 0x800, // 2k (sec 3.2, page 73; also appears in sec 3.3.1 - // and tables 7 on pages 73-74) - // SRAM1 is 128k at 0x20000000; - // SRAM2 is 32k mapped at 0x10000000 (sec 2.4.2, table 3-4, - // page 68, also fig 2 on page 63) - .sram_size = 0x20000, - .bootrom_base = 0x1fff0000, // Tables 6, pages 71-72 (Bank 1 system - // memory, also fig 2 on page 63) - .bootrom_size = 0x7000, // 28k (per bank), same source as base + // STM32F72x/F73x + // RM0431 + .chip_id = STLINK_CHIPID_STM32_F72xxx, + .dev_type = "F72x/F73x", + .flash_type = STLINK_FLASH_TYPE_F4, + .flash_size_reg = 0x1ff07a22, // section 35.2 + .flash_pagesize = 0x800, // No flash pages + .sram_size = 0x40000, // "SRAM" byte size in hex from DS Fig 24 + .bootrom_base = 0x00100000, // "System memory" starting address from DS Fig 24 + .bootrom_size = 0xEDC0, // "System memory" byte size in hex from DS Fig 24 + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + // STM32F74x/F75x + // RM0385, DS10916 + .chip_id = STLINK_CHIPID_STM32_F7, + .dev_type = "F74x/F75x", + .flash_type = STLINK_FLASH_TYPE_F4, + .flash_size_reg = 0x1ff0f442, // section 41.2 + .flash_pagesize = 0x800, // No flash pages + .sram_size = 0x50000, // "SRAM" byte size in hex from DS Fig 18 + .bootrom_base = 0x00100000, // "System memory" starting address from DS Fig 18 + .bootrom_size = 0xEDC0, // "System memory" byte size in hex from DS Fig 18 .flags = CHIP_F_HAS_SWO_TRACING, }, { - // STM32L0xx Category 1 - // RM0451, RM0377 - .chip_id = STLINK_CHIPID_STM32_L011, - .dev_type = "L01x/L02x", - .flash_type = STLINK_FLASH_TYPE_L0, - .flash_size_reg = 0x1ff8007c, - .flash_pagesize = 0x80, - .sram_size = 0x2000, - .bootrom_base = 0x1ff00000, - .bootrom_size = 0x2000, + // STM32F76x/F77x + // RM0410 + .chip_id = STLINK_CHIPID_STM32_F76xxx, + .dev_type = "F76x/F77x", + .flash_type = STLINK_FLASH_TYPE_F7, + .flash_size_reg = 0x1ff0f442, // section 45.2 + .flash_pagesize = 0x800, // No flash pages + .sram_size = 0x80000, // "SRAM" byte size in hex from + .bootrom_base = 0x00200000, // "System memory" starting address from + .bootrom_size = 0xEDC0, + .option_base = STM32_F7_OPTION_BYTES_BASE, /* Used for reading back the option + bytes, writing uses FLASH_F7_OPTCR + and FLASH_F7_OPTCR1 */ + .option_size = 0x20, + .flags = CHIP_F_HAS_DUAL_BANK | CHIP_F_HAS_SWO_TRACING, }, { // STM32G030/031/041 @@ -579,10 +645,10 @@ static struct stlink_chipid_params devices[] = { .option_size = 4, }, { - // STM32G071/081 + // STM32G051/G061 // RM0444 - .chip_id = STLINK_CHIPID_STM32_G0_CAT2, - .dev_type = "G07x/G08x", + .chip_id = STLINK_CHIPID_STM32_G0_CAT4, + .dev_type = "G05x/G06x", .flash_type = STLINK_FLASH_TYPE_G0, .flash_size_reg = 0x1FFF75E0, // Section 38.2 .flash_pagesize = 0x800, // 2k (sec 3.2) @@ -593,10 +659,10 @@ static struct stlink_chipid_params devices[] = { .option_size = 4, }, { - // STM32G0B1/G0C1 + // STM32G071/081 // RM0444 - .chip_id = STLINK_CHIPID_STM32_G0_CAT3, - .dev_type = "G0Bx/G0Cx", + .chip_id = STLINK_CHIPID_STM32_G0_CAT2, + .dev_type = "G07x/G08x", .flash_type = STLINK_FLASH_TYPE_G0, .flash_size_reg = 0x1FFF75E0, // Section 38.2 .flash_pagesize = 0x800, // 2k (sec 3.2) @@ -605,13 +671,12 @@ static struct stlink_chipid_params devices[] = { .bootrom_size = 0x7000, // 28k (sec 2.2.2 table 2) .option_base = STM32_G0_OPTION_BYTES_BASE, .option_size = 4, - .flags = CHIP_F_HAS_DUAL_BANK, }, { - // STM32G051/G061 + // STM32G0B1/G0C1 // RM0444 - .chip_id = STLINK_CHIPID_STM32_G0_CAT4, - .dev_type = "G05x/G06x", + .chip_id = STLINK_CHIPID_STM32_G0_CAT3, + .dev_type = "G0Bx/G0Cx", .flash_type = STLINK_FLASH_TYPE_G0, .flash_size_reg = 0x1FFF75E0, // Section 38.2 .flash_pagesize = 0x800, // 2k (sec 3.2) @@ -620,6 +685,7 @@ static struct stlink_chipid_params devices[] = { .bootrom_size = 0x7000, // 28k (sec 2.2.2 table 2) .option_base = STM32_G0_OPTION_BYTES_BASE, .option_size = 4, + .flags = CHIP_F_HAS_DUAL_BANK, }, { // STM32G431/441 @@ -675,20 +741,6 @@ static struct stlink_chipid_params devices[] = { .option_size = 4, .flags = CHIP_F_HAS_SWO_TRACING, }, - { - // STM32H742/743/753 (from RM0433) - .chip_id = STLINK_CHIPID_STM32_H74xxx, - .dev_type = "H74x/H75x", - .flash_type = STLINK_FLASH_TYPE_H7, - .flash_size_reg = 0x1ff1e880, // "Flash size register" (pg3272) - .flash_pagesize = 0x20000, // 128k sector (pg147) - .sram_size = 0x20000, // 128k "DTCM" from Table 7 - .bootrom_base = 0x1ff00000, // "System memory" starting address from Table 7 - .bootrom_size = 0x20000, // "System memory" byte size in hex from Table 7 - .option_base = STM32_H7_OPTION_BYTES_BASE, - .option_size = 44, // FLASH_OPTSR_CUR to FLASH_BOOT_PRGR from Table 28 - .flags = CHIP_F_HAS_DUAL_BANK | CHIP_F_HAS_SWO_TRACING, - }, { // STM32H7A3/7B3 // RM0455 @@ -720,125 +772,74 @@ static struct stlink_chipid_params devices[] = { .option_size = 44, .flags = CHIP_F_HAS_SWO_TRACING, }, - - - { - // STM32F1xx medium-density devices - // RM0008 - .chip_id = STLINK_CHIPID_STM32_F1_MD, - .dev_type = "F1xx Medium-density", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7e0, - .flash_pagesize = 0x400, - .sram_size = 0x5000, - .bootrom_base = 0x1ffff000, // 2.3.3 "Embedded Flash memory" - .bootrom_size = 0x800, - .option_base = STM32_F0_OPTION_BYTES_BASE, - .option_size = 16, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32F205xx, STM32F207xx, STM32F215xx, STM32F217xx - // RM0033 (rev 5) - .chip_id = STLINK_CHIPID_STM32_F2, - .dev_type = "F2xx", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1fff7a22, - .flash_pagesize = 0x20000, - .sram_size = 0x20000, - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7800, - .option_base = 0x1FFFC000, - .option_size = 4, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32F1xx low-density devices - // RM0008 - .chip_id = STLINK_CHIPID_STM32_F1_LD, - .dev_type = "F1 Low-density device", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7e0, - .flash_pagesize = 0x400, - .sram_size = 0x2800, - .bootrom_base = 0x1ffff000, - .bootrom_size = 0x800, - .option_base = STM32_F0_OPTION_BYTES_BASE, - .option_size = 16, - .flags = CHIP_F_HAS_SWO_TRACING, - }, { - // STM32F1xx high-density devices - // RM0008 - .chip_id = STLINK_CHIPID_STM32_F1_HD, - .dev_type = "F1xx High-density", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7e0, - .flash_pagesize = 0x800, - .sram_size = 0x10000, - .bootrom_base = 0x1ffff000, - .bootrom_size = 0x800, - .option_base = STM32_F0_OPTION_BYTES_BASE, - .option_size = 16, - .flags = CHIP_F_HAS_SWO_TRACING, + // STM32H742/743/753 (from RM0433) + .chip_id = STLINK_CHIPID_STM32_H74xxx, + .dev_type = "H74x/H75x", + .flash_type = STLINK_FLASH_TYPE_H7, + .flash_size_reg = 0x1ff1e880, // "Flash size register" (pg3272) + .flash_pagesize = 0x20000, // 128k sector (pg147) + .sram_size = 0x20000, // 128k "DTCM" from Table 7 + .bootrom_base = 0x1ff00000, // "System memory" starting address from Table 7 + .bootrom_size = 0x20000, // "System memory" byte size in hex from Table 7 + .option_base = STM32_H7_OPTION_BYTES_BASE, + .option_size = 44, // FLASH_OPTSR_CUR to FLASH_BOOT_PRGR from Table 28 + .flags = CHIP_F_HAS_DUAL_BANK | CHIP_F_HAS_SWO_TRACING, }, { - // STM32F1xx connectivity devices - // RM0008 - .chip_id = STLINK_CHIPID_STM32_F1_CONN, - .dev_type = "F1xx CL", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7e0, - .flash_pagesize = 0x800, - .sram_size = 0x10000, - .bootrom_base = 0x1fffb000, - .bootrom_size = 0x4800, - .option_base = STM32_F0_OPTION_BYTES_BASE, - .option_size = 16, - .flags = CHIP_F_HAS_SWO_TRACING, + // STM32L0xx Category 1 + // RM0451, RM0377 + .chip_id = STLINK_CHIPID_STM32_L011, + .dev_type = "L01x/L02x", + .flash_type = STLINK_FLASH_TYPE_L0, + .flash_size_reg = 0x1ff8007c, + .flash_pagesize = 0x80, + .sram_size = 0x2000, + .bootrom_base = 0x1ff00000, + .bootrom_size = 0x2000, }, { - // STM32F1xx low- and medium-density value line devices - // RM0041 - .chip_id = STLINK_CHIPID_STM32_F1_VL_MD_LD, - .dev_type = "F1xx Value Line", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7e0, - .flash_pagesize = 0x400, - .sram_size = 0x2000, // 0x1000 for low density devices - .bootrom_base = 0x1ffff000, - .bootrom_size = 0x800, - .option_base = STM32_F0_OPTION_BYTES_BASE, - .option_size = 16, - .flags = CHIP_F_HAS_SWO_TRACING, + // STM32L0x Category 2 + // RM0367, RM0377 + .chip_id = STLINK_CHIPID_STM32_L0_CAT2, + .dev_type = "L0xx Cat.2", + .flash_type = STLINK_FLASH_TYPE_L0, + .flash_size_reg = 0x1ff8007c, + .flash_pagesize = 0x80, + .sram_size = 0x2000, + .bootrom_base = 0x1ff0000, + .bootrom_size = 0x1000, + .option_base = STM32_L0_OPTION_BYTES_BASE, + .option_size = 20, }, { - // STM32F1xx high-density value line devices - // RM0041 - .chip_id = STLINK_CHIPID_STM32_F1_VL_HD, - .dev_type = "F1xx High-density value line", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7e0, - .flash_pagesize = 0x800, - .sram_size = 0x8000, - .bootrom_base = 0x1ffff000, - .bootrom_size = 0x800, - .option_base = STM32_F0_OPTION_BYTES_BASE, - .option_size = 16, - .flags = CHIP_F_HAS_SWO_TRACING, + // STM32L0xx Category 3 + // RM0367, RM0377, RM0451 + .chip_id = STLINK_CHIPID_STM32_L0, + .dev_type = "L0xx Cat.3", + .flash_type = STLINK_FLASH_TYPE_L0, + .flash_size_reg = 0x1ff8007c, + .flash_pagesize = 0x80, + .sram_size = 0x2000, + .bootrom_base = 0x1ff0000, + .bootrom_size = 0x1000, + .option_base = STM32_L0_OPTION_BYTES_BASE, + .option_size = 20, }, { - // STM32F1xx XL-density devices - // RM0008 - .chip_id = STLINK_CHIPID_STM32_F1_XLD, - .dev_type = "F1xx XL-density", - .flash_type = STLINK_FLASH_TYPE_F1_XL, - .flash_size_reg = 0x1ffff7e0, - .flash_pagesize = 0x800, - .sram_size = 0x18000, - .bootrom_base = 0x1fffe000, - .bootrom_size = 0x1800, - .flags = CHIP_F_HAS_SWO_TRACING, + // STM32L0x Category 5 + // RM0367, RM0377, RM0451 + .chip_id = STLINK_CHIPID_STM32_L0_CAT5, + .dev_type = "L0xx Cat.5", + .flash_type = STLINK_FLASH_TYPE_L0, + .flash_size_reg = 0x1ff8007c, + .flash_pagesize = 0x80, + .sram_size = 0x5000, + .bootrom_base = 0x1ff0000, + .bootrom_size = 0x2000, + .option_base = STM32_L0_OPTION_BYTES_BASE, + .option_size = 20, + .flags = CHIP_F_HAS_DUAL_BANK, }, { // STM32WB55xx, STM32WB35xx, STM32WB50CG/30CE From f55dd8d08f5cd414b9569b8d16a0f7841cec6db9 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Thu, 6 Jan 2022 21:24:29 +0100 Subject: [PATCH 336/503] [refactoring] Clean-up for chipid files (L1, L4) --- config/chips/L1xx_Cat_1.chip | 17 +- config/chips/L1xx_Cat_2.chip | 17 +- config/chips/L1xx_Cat_3.chip | 17 +- config/chips/L1xx_Cat_4.chip | 21 +- config/chips/L1xx_Cat_5.chip | 17 +- config/chips/L41x_L42x.chip | 17 +- config/chips/L43x_L44x.chip | 21 +- config/chips/L45x_46x.chip | 13 -- config/chips/L45x_L46x.chip | 14 ++ config/chips/L47x_L48x.chip | 21 +- config/chips/L496x_L4A6x.chip | 21 +- config/chips/L4Px.chip | 19 +- config/chips/L4Rx.chip | 19 +- src/stlink-lib/chipid_db_old.h | 373 ++++++++++++++++----------------- 14 files changed, 308 insertions(+), 299 deletions(-) delete mode 100644 config/chips/L45x_46x.chip create mode 100644 config/chips/L45x_L46x.chip diff --git a/config/chips/L1xx_Cat_1.chip b/config/chips/L1xx_Cat_1.chip index 6c8b211c4..1d0b9282f 100644 --- a/config/chips/L1xx_Cat_1.chip +++ b/config/chips/L1xx_Cat_1.chip @@ -1,13 +1,14 @@ -# Chip-ID file for L1xx Cat.1 +# Chip-ID file for STM32L1xx (Cat.1) device (L100C6 / L100R8 / L100RB) # -chip_id 0x416 -description L1xx Cat.1 -flash_type 5 -flash_pagesize 0x100 -sram_size 0x4000 +dev_type STM32L1xx_Cat_1 +ref_manual_id 0038 +chip_id 0x416 // STLINK_CHIPID_STM32_L1_MD +flash_type 5 // STLINK_FLASH_TYPE_L0 +flash_size_reg 0x1ff8004c +flash_pagesize 0x100 // 128 B +sram_size 0x4000 // 16 KB bootrom_base 0x1ff00000 -bootrom_size 0x1000 +bootrom_size 0x1000 // 4 KB option_base 0x0 option_size 0x0 flags swo - diff --git a/config/chips/L1xx_Cat_2.chip b/config/chips/L1xx_Cat_2.chip index 1ff71edef..f311e702c 100644 --- a/config/chips/L1xx_Cat_2.chip +++ b/config/chips/L1xx_Cat_2.chip @@ -1,13 +1,14 @@ -# Chip-ID file for L1xx Cat.2 +# Chip-ID file for STM32L1xx (Cat.2) device (L100C6-A / L100R8-A / L100RB-A) # -chip_id 0x429 -description L1xx Cat.2 -flash_type 5 -flash_pagesize 0x100 -sram_size 0x8000 +dev_type STM32L1xx_Cat_2 +ref_manual_id 0038 +chip_id 0x429 // STLINK_CHIPID_STM32_L1_CAT2 +flash_type 5 // STLINK_FLASH_TYPE_L0 +flash_size_reg 0x1ff8004c +flash_pagesize 0x100 // 128 B +sram_size 0x8000 // 32 KB bootrom_base 0x1ff00000 -bootrom_size 0x1000 +bootrom_size 0x1000 // 4 KB option_base 0x0 option_size 0x0 flags swo - diff --git a/config/chips/L1xx_Cat_3.chip b/config/chips/L1xx_Cat_3.chip index f417e07f9..e6ecaf49e 100644 --- a/config/chips/L1xx_Cat_3.chip +++ b/config/chips/L1xx_Cat_3.chip @@ -1,13 +1,14 @@ -# Chip-ID file for L1xx Cat.3 +# Chip-ID file for STM32L1xx (Cat.3) device (L100RC / L15xxC) # -chip_id 0x427 -description L1xx Cat.3 -flash_type 5 -flash_pagesize 0x100 -sram_size 0x8000 +dev_type STM32L1xx_Cat_3 +ref_manual_id 0038 +chip_id 0x427 // STLINK_CHIPID_STM32_L1_MD_PLUS +flash_type 5 // STLINK_FLASH_TYPE_L0 +flash_size_reg 0x1ff800cc +flash_pagesize 0x100 // 128 B +sram_size 0x8000 // 32 KB bootrom_base 0x1ff00000 -bootrom_size 0x1000 +bootrom_size 0x1000 // 4 KB option_base 0x0 option_size 0x0 flags swo - diff --git a/config/chips/L1xx_Cat_4.chip b/config/chips/L1xx_Cat_4.chip index dbf7869ad..8ed0e004a 100644 --- a/config/chips/L1xx_Cat_4.chip +++ b/config/chips/L1xx_Cat_4.chip @@ -1,13 +1,14 @@ -# Chip-ID file for L1xx Cat.4 +# Chip-ID file for STM32L1xx (Cat.4) device (L15xxD / L162xD) # -chip_id 0x436 -description L1xx Cat.4 -flash_type 5 -flash_pagesize 0x100 -sram_size 0xc000 +dev_type STM32L1xx_Cat_4 +ref_manual_id 0038 +chip_id 0x436 // STLINK_CHIPID_STM32_L1_MD_PLUS_HD +flash_type 5 // STLINK_FLASH_TYPE_L0 +flash_size_reg 0x1ff800cc +flash_pagesize 0x100 // 128 B +sram_size 0xc000 // 48 KB bootrom_base 0x1ff00000 -bootrom_size 0x1000 -option_base 0x1ff80000 -option_size 0x8 +bootrom_size 0x1000 // 4 KB +option_base 0x1ff80000 // STM32_L1_OPTION_BYTES_BASE +option_size 0x8 // 8 B flags swo - diff --git a/config/chips/L1xx_Cat_5.chip b/config/chips/L1xx_Cat_5.chip index 12342d14f..75cebd94c 100644 --- a/config/chips/L1xx_Cat_5.chip +++ b/config/chips/L1xx_Cat_5.chip @@ -1,13 +1,14 @@ -# Chip-ID file for L1xx Cat.5 +# Chip-ID file for STM32L1xx (Cat.5) device (L15xxE / L162xE) # -chip_id 0x437 -description L1xx Cat.5 -flash_type 5 -flash_pagesize 0x100 -sram_size 0x14000 +dev_type STM32L1xx_Cat_5 +ref_manual_id 0038 +chip_id 0x437 // STLINK_CHIPID_STM32_L152_RE +flash_type 5 // STLINK_FLASH_TYPE_L0 +flash_size_reg 0x1ff800cc +flash_pagesize 0x100 // 128 B +sram_size 0x14000 // 80 KB bootrom_base 0x1ff00000 -bootrom_size 0x1000 +bootrom_size 0x1000 // 4 KB option_base 0x0 option_size 0x0 flags swo - diff --git a/config/chips/L41x_L42x.chip b/config/chips/L41x_L42x.chip index 3e086e159..97d0939ab 100644 --- a/config/chips/L41x_L42x.chip +++ b/config/chips/L41x_L42x.chip @@ -1,13 +1,14 @@ -# Chip-ID file for L41x/L42x +# Chip-ID file for STM32L41x / STM32L42x device # -chip_id 0x464 -description L41x/L42x -flash_type 6 -flash_pagesize 0x800 -sram_size 0xa000 +dev_type STM32L41x_L42x +ref_manual_id 0394 +chip_id 0x464 // STLINK_CHIPID_STM32_L41x_L42x +flash_type 6 // STLINK_FLASH_TYPE_L4 +flash_size_reg 0x1fff75e0 +flash_pagesize 0x800 // 2 KB +sram_size 0xa000 // 40 KB bootrom_base 0x1fff0000 -bootrom_size 0x7000 +bootrom_size 0x7000 // 28 KB option_base 0x0 option_size 0x0 flags swo - diff --git a/config/chips/L43x_L44x.chip b/config/chips/L43x_L44x.chip index 383c42f3f..369fdfa1e 100644 --- a/config/chips/L43x_L44x.chip +++ b/config/chips/L43x_L44x.chip @@ -1,13 +1,14 @@ -# Chip-ID file for L43x/L44x +# Chip-ID file for STM32L43x / STM32L44x device # -chip_id 0x435 -description L43x/L44x -flash_type 6 -flash_pagesize 0x800 -sram_size 0xc000 +dev_type STM32L41x_L42x +ref_manual_id 0392 +chip_id 0x435 // STLINK_CHIPID_STM32_L43x_L44x +flash_type 6 // STLINK_FLASH_TYPE_L4 +flash_size_reg 0x1fff75e0 +flash_pagesize 0x800 // 2 KB +sram_size 0xc000 // 48 KB bootrom_base 0x1fff0000 -bootrom_size 0x7000 -option_base 0x1fff7800 -option_size 0x4 +bootrom_size 0x7000 // 28 KB +option_base 0x1fff7800 // STM32_L4_OPTION_BYTES_BASE +option_size 0x4 // 4 B flags swo - diff --git a/config/chips/L45x_46x.chip b/config/chips/L45x_46x.chip deleted file mode 100644 index 943b275d5..000000000 --- a/config/chips/L45x_46x.chip +++ /dev/null @@ -1,13 +0,0 @@ -# Chip-ID file for L45x/46x -# -chip_id 0x462 -description L45x/46x -flash_type 6 -flash_pagesize 0x800 -sram_size 0x20000 -bootrom_base 0x1fff0000 -bootrom_size 0x7000 -option_base 0x0 -option_size 0x0 -flags swo - diff --git a/config/chips/L45x_L46x.chip b/config/chips/L45x_L46x.chip new file mode 100644 index 000000000..2d1cda441 --- /dev/null +++ b/config/chips/L45x_L46x.chip @@ -0,0 +1,14 @@ +# Chip-ID file for STM32L45x / STM32L46x device +# +dev_type STM32L45x_L46x +ref_manual_id 0394 +chip_id 0x462 // STLINK_CHIPID_STM32_L45x_L46x +flash_type 6 // STLINK_FLASH_TYPE_L4 +flash_size_reg 0x1fff75e0 +flash_pagesize 0x800 // 2 KB +sram_size 0x20000 // 128 KB +bootrom_base 0x1fff0000 +bootrom_size 0x7000 // 28 KB +option_base 0x0 +option_size 0x0 +flags swo diff --git a/config/chips/L47x_L48x.chip b/config/chips/L47x_L48x.chip index 7069229f3..4af25cf5c 100644 --- a/config/chips/L47x_L48x.chip +++ b/config/chips/L47x_L48x.chip @@ -1,13 +1,14 @@ -# Chip-ID file for L47x/L48x +# Chip-ID file for STM32L47x / STM32L48x device # -chip_id 0x415 -description L47x/L48x -flash_type 6 -flash_pagesize 0x800 -sram_size 0x18000 +dev_type STM32L47x_L48x +ref_manual_id 0351 +chip_id 0x415 // STLINK_CHIPID_STM32_L4 +flash_type 6 // STLINK_FLASH_TYPE_L4 +flash_size_reg 0x1fff75e0 +flash_pagesize 0x800 // 2 KB +sram_size 0x18000 // 96 KB bootrom_base 0x1fff0000 -bootrom_size 0x7000 -option_base 0x1fff7800 -option_size 0x4 +bootrom_size 0x7000 // 28 KB +option_base 0x1fff7800 // STM32_L4_OPTION_BYTES_BASE +option_size 0x4 // 4 B flags swo - diff --git a/config/chips/L496x_L4A6x.chip b/config/chips/L496x_L4A6x.chip index 57f539db3..822914c96 100644 --- a/config/chips/L496x_L4A6x.chip +++ b/config/chips/L496x_L4A6x.chip @@ -1,13 +1,14 @@ -# Chip-ID file for L496x/L4A6x +# Chip-ID file for STM32L496x / STM32L4A6x device # -chip_id 0x461 -description L496x/L4A6x -flash_type 6 -flash_pagesize 0x800 -sram_size 0x40000 +dev_type STM32L496x_L4A6x +ref_manual_id 0351 +chip_id 0x461 // STLINK_CHIPID_STM32_L496x_L4A6x +flash_type 6 // STLINK_FLASH_TYPE_L4 +flash_size_reg 0x1fff75e0 +flash_pagesize 0x800 // 2 KB +sram_size 0x40000 // 256 KB bootrom_base 0x1fff0000 -bootrom_size 0x7000 -option_base 0x1fff7800 -option_size 0x4 +bootrom_size 0x7000 // 28 KB +option_base 0x1fff7800 // STM32_L4_OPTION_BYTES_BASE +option_size 0x4 // 4 B flags swo - diff --git a/config/chips/L4Px.chip b/config/chips/L4Px.chip index 3e0fbea50..8366621e2 100644 --- a/config/chips/L4Px.chip +++ b/config/chips/L4Px.chip @@ -1,13 +1,14 @@ -# Chip-ID file for L4Px +# Chip-ID file for STM32L4Px device # -chip_id 0x471 -description L4Px -flash_type 6 -flash_pagesize 0x1000 -sram_size 0xa0000 +dev_type STM32L4Px +ref_manual_id 0432 +chip_id 0x471 // STLINK_CHIPID_STM32_L4PX +flash_type 6 // STLINK_FLASH_TYPE_L4 +flash_size_reg 0x1fff75e0 +flash_pagesize 0x1000 // 4 KB +sram_size 0xa0000 // 640 KB bootrom_base 0x1fff0000 -bootrom_size 0x7000 +bootrom_size 0x7000 // 28 KB option_base 0x0 option_size 0x0 -flags dualbank swo - +flags swo diff --git a/config/chips/L4Rx.chip b/config/chips/L4Rx.chip index a9a26f419..734f39199 100644 --- a/config/chips/L4Rx.chip +++ b/config/chips/L4Rx.chip @@ -1,13 +1,14 @@ -# Chip-ID file for L4Rx +# Chip-ID file for STM32L4Rx device # -chip_id 0x470 -description L4Rx -flash_type 6 -flash_pagesize 0x1000 -sram_size 0xa0000 +dev_type STM32L4Rx +ref_manual_id 0432 +chip_id 0x470 // STLINK_CHIPID_STM32_L4RX +flash_type 6 // STLINK_FLASH_TYPE_L4 +flash_size_reg 0x1fff75e0 +flash_pagesize 0x1000 // 4 KB +sram_size 0xa0000 // 640 KB bootrom_base 0x1fff0000 -bootrom_size 0x7000 +bootrom_size 0x7000 // 28 KB option_base 0x0 option_size 0x0 -flags dualbank swo - +flags swo diff --git a/src/stlink-lib/chipid_db_old.h b/src/stlink-lib/chipid_db_old.h index b86b13289..7acfef409 100644 --- a/src/stlink-lib/chipid_db_old.h +++ b/src/stlink-lib/chipid_db_old.h @@ -6,194 +6,6 @@ // config/chips/*.chip file. static struct stlink_chipid_params devices[] = { - { - // STM32L100/L15x/L16x Cat.1 - // RM0038 - .chip_id = STLINK_CHIPID_STM32_L1_MD, - .dev_type = "L1xx Cat.1", - .flash_type = STLINK_FLASH_TYPE_L0, - .flash_size_reg = 0x1ff8004c, - .flash_pagesize = 0x100, - .sram_size = 0x4000, // up to 16k - .bootrom_base = 0x1ff00000, - .bootrom_size = 0x1000, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32L100/L15x/L16x Cat.2 - // RM0038 - .chip_id = STLINK_CHIPID_STM32_L1_CAT2, - .dev_type = "L1xx Cat.2", - .flash_type = STLINK_FLASH_TYPE_L0, - .flash_size_reg = 0x1ff8004c, - .flash_pagesize = 0x100, - .sram_size = 0x8000, // up to 32k - .bootrom_base = 0x1ff00000, - .bootrom_size = 0x1000, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32L100/L15x/L16x Cat.3 - // RM0038 - .chip_id = STLINK_CHIPID_STM32_L1_MD_PLUS, - .dev_type = "L1xx Cat.3", - .flash_type = STLINK_FLASH_TYPE_L0, - .flash_size_reg = 0x1ff800cc, - .flash_pagesize = 0x100, - .sram_size = 0x8000, // up to 32k - .bootrom_base = 0x1ff00000, - .bootrom_size = 0x1000, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32L100/L15x/L16x Cat.4 - // RM0038 - .chip_id = STLINK_CHIPID_STM32_L1_MD_PLUS_HD, - .dev_type = "L1xx Cat.4", - .flash_type = STLINK_FLASH_TYPE_L0, - .flash_size_reg = 0x1ff800cc, - .flash_pagesize = 0x100, - .sram_size = 0xC000, // up to 48k - .bootrom_base = 0x1ff00000, - .bootrom_size = 0x1000, - .option_base = STM32_L1_OPTION_BYTES_BASE, - .option_size = 8, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32L100/L15x/L16x Cat.5 - // RM0038 - .chip_id = STLINK_CHIPID_STM32_L152_RE, - .dev_type = "L1xx Cat.5", - .flash_type = STLINK_FLASH_TYPE_L0, - .flash_size_reg = 0x1ff800cc, - .flash_pagesize = 0x100, - .sram_size = 0x14000, // up to 80k - .bootrom_base = 0x1ff00000, - .bootrom_size = 0x1000, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32L47x/L48x - // RM0351 - .chip_id = STLINK_CHIPID_STM32_L4, - .dev_type = "L47x/L48x", - .flash_type = STLINK_FLASH_TYPE_L4, - .flash_size_reg = 0x1FFF75e0, // "Flash size data register" (sec 45.2, page 1671) - .flash_pagesize = 0x800, // 2k (sec 3.2, page 78; also appears in sec 3.3.1 - // and tables 4-6 on pages 79-81) - // SRAM1 is "up to" 96k in the standard Cortex-M memory map; - // SRAM2 is 32k mapped at at 0x10000000 (sec 2.3, page 73 for - // sizes; table 2, page 74 for SRAM2 location) - .sram_size = 0x18000, - .bootrom_base = 0x1fff0000, // Tables 4-6, pages 80-81 (Bank 1 system memory) - .bootrom_size = 0x7000, // 28k (per bank), same source as base - .option_base = STM32_L4_OPTION_BYTES_BASE, - .option_size = 4, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32L4RX - // RM0432 - .chip_id = STLINK_CHIPID_STM32_L4Rx, - .dev_type = "L4Rx", - .flash_type = STLINK_FLASH_TYPE_L4, - .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 58.2, page 2274) - .flash_pagesize = 0x1000, // 4k, section 3.3, pg 117-120 - // TODO: flash_pagesize can be 8k depend on the dual-bank mode and flash size - .sram_size = 0xa0000, // 192k (SRAM1) + 64k SRAM2 + 384k SRAM3 = 640k, or 0xA0000 - .bootrom_base = 0x1fff0000, // 3.3.1, pg 117 - .bootrom_size = 0x7000, // 28k (per bank), same source as base (pg 117) - .flags = CHIP_F_HAS_DUAL_BANK | CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32L4PX - // RM0432 - .chip_id = STLINK_CHIPID_STM32_L4PX, - .dev_type = "L4Px", - .flash_type = STLINK_FLASH_TYPE_L4, - .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 58.2, page 2274) - .flash_pagesize = 0x1000, // 4k, section 3.3, pg 117-120 - // TODO: flash_pagesize can be 8k depend on the dual-bank mode and flash size - .sram_size = 0xa0000, // 192k (SRAM1) + 64k SRAM2 + 384k SRAM3 = 640k, or 0xA0000 - .bootrom_base = 0x1fff0000, // 3.3.1, pg 117 - .bootrom_size = 0x7000, // 28k (per bank), same source as base (pg 117) - .flags = CHIP_F_HAS_DUAL_BANK | CHIP_F_HAS_SWO_TRACING, - }, - { - // STLINK_CHIPID_STM32_L41x_L42x - // RM0394 (rev 4), DS12469 (rev 5) - .chip_id = STLINK_CHIPID_STM32_L41x_L42x, - .dev_type = "L41x/L42x", - .flash_type = STLINK_FLASH_TYPE_L4, - .flash_size_reg = 0x1fff75e0, // "Flash size data register" (RM0394, - // sec 47.2, page 1586) - .flash_pagesize = 0x800, // 2k (DS12469, sec 3.4, page 17) - // SRAM1 is 32k at 0x20000000 - // SRAM2 is 8k at 0x10000000 and 0x20008000 - // (DS12469, sec 3.5, page 18) - .sram_size = 0xa000, // 40k (DS12469, sec 3.5, page 18) - .bootrom_base = 0x1fff0000, // System Memory (RM0394, sec 3.3.1, table 8) - .bootrom_size = 0x7000, // 28k, same source as base - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STLINK_CHIPID_STM32_L43x_L44x - // RM0392 - .chip_id = STLINK_CHIPID_STM32_L43x_L44x, - .dev_type = "L43x/L44x", - .flash_type = STLINK_FLASH_TYPE_L4, - .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 43.2, page 1410) - .flash_pagesize = 0x800, // 2k (sec 3.2, page 74; also appears in sec 3.3.1 - // and tables 7-8 on pages 75-76) - // SRAM1 is "up to" 64k in the standard Cortex-M memory map; - // SRAM2 is 16k mapped at 0x10000000 (sec 2.3, page 73 for - // sizes; table 2, page 74 for SRAM2 location) - .sram_size = 0xc000, - .bootrom_base = 0x1fff0000, // Tables 4-6, pages 80-81 (Bank 1 system memory) - .bootrom_size = 0x7000, // 28k (per bank), same source as base - .option_base = STM32_L4_OPTION_BYTES_BASE, - .option_size = 4, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STLINK_CHIPID_STM32_L496x_L4A6x - // RM0351 (rev 5) - .chip_id = STLINK_CHIPID_STM32_L496x_L4A6x, - .dev_type = "L496x/L4A6x", - .flash_type = STLINK_FLASH_TYPE_L4, - .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 49.2, page 1809) - .flash_pagesize = 0x800, // Page erase (2 Kbyte) (sec 3.2, page 93) - // SRAM1 is 256k at 0x20000000 - // SRAM2 is 64k at 0x20040000 (sec 2.2.1, fig 2, page 74) - .sram_size = 0x40000, // Embedded SRAM (sec 2.4, page 84) - .bootrom_base = 0x1fff0000, // System Memory (Bank 1) (sec 3.3.1) - .bootrom_size = 0x7000, // 28k (per bank), same source as base - .option_base = STM32_L4_OPTION_BYTES_BASE, - .option_size = 4, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STLINK_CHIPID_STM32_L45x_L46x - // RM0394 (updated version of RM0392?) - .chip_id = STLINK_CHIPID_STM32_L45x_L46x, - .dev_type = "L45x/46x", - .flash_type = STLINK_FLASH_TYPE_L4, - .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 45.2, page 1463) - .flash_pagesize = 0x800, // 2k (sec 3.2, page 73; also appears in sec 3.3.1 - // and tables 7 on pages 73-74) - // SRAM1 is 128k at 0x20000000; - // SRAM2 is 32k mapped at 0x10000000 (sec 2.4.2, table 3-4, - // page 68, also fig 2 on page 63) - .sram_size = 0x20000, - .bootrom_base = 0x1fff0000, // Tables 6, pages 71-72 (Bank 1 system - // memory, also fig 2 on page 63) - .bootrom_size = 0x7000, // 28k (per bank), same source as base - .flags = CHIP_F_HAS_SWO_TRACING, - }, -// ######################################################################## -// ######################################################################## -// ######################################################################## { // STM32F03x // RM0091 @@ -841,6 +653,191 @@ static struct stlink_chipid_params devices[] = { .option_size = 20, .flags = CHIP_F_HAS_DUAL_BANK, }, + { + // STM32L100/L15x/L16x Cat.1 + // RM0038 + .chip_id = STLINK_CHIPID_STM32_L1_MD, + .dev_type = "L1xx Cat.1", + .flash_type = STLINK_FLASH_TYPE_L0, + .flash_size_reg = 0x1ff8004c, + .flash_pagesize = 0x100, + .sram_size = 0x4000, // up to 16k + .bootrom_base = 0x1ff00000, + .bootrom_size = 0x1000, + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + // STM32L100/L15x/L16x Cat.2 + // RM0038 + .chip_id = STLINK_CHIPID_STM32_L1_CAT2, + .dev_type = "L1xx Cat.2", + .flash_type = STLINK_FLASH_TYPE_L0, + .flash_size_reg = 0x1ff8004c, + .flash_pagesize = 0x100, + .sram_size = 0x8000, // up to 32k + .bootrom_base = 0x1ff00000, + .bootrom_size = 0x1000, + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + // STM32L100/L15x/L16x Cat.3 + // RM0038 + .chip_id = STLINK_CHIPID_STM32_L1_MD_PLUS, + .dev_type = "L1xx Cat.3", + .flash_type = STLINK_FLASH_TYPE_L0, + .flash_size_reg = 0x1ff800cc, + .flash_pagesize = 0x100, + .sram_size = 0x8000, // up to 32k + .bootrom_base = 0x1ff00000, + .bootrom_size = 0x1000, + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + // STM32L100/L15x/L16x Cat.4 + // RM0038 + .chip_id = STLINK_CHIPID_STM32_L1_MD_PLUS_HD, + .dev_type = "L1xx Cat.4", + .flash_type = STLINK_FLASH_TYPE_L0, + .flash_size_reg = 0x1ff800cc, + .flash_pagesize = 0x100, + .sram_size = 0xC000, // up to 48k + .bootrom_base = 0x1ff00000, + .bootrom_size = 0x1000, + .option_base = STM32_L1_OPTION_BYTES_BASE, + .option_size = 8, + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + // STM32L100/L15x/L16x Cat.5 + // RM0038 + .chip_id = STLINK_CHIPID_STM32_L152_RE, + .dev_type = "L1xx Cat.5", + .flash_type = STLINK_FLASH_TYPE_L0, + .flash_size_reg = 0x1ff800cc, + .flash_pagesize = 0x100, + .sram_size = 0x14000, // up to 80k + .bootrom_base = 0x1ff00000, + .bootrom_size = 0x1000, + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + // STLINK_CHIPID_STM32_L41x_L42x + // RM0394 (rev 4), DS12469 (rev 5) + .chip_id = STLINK_CHIPID_STM32_L41x_L42x, + .dev_type = "L41x/L42x", + .flash_type = STLINK_FLASH_TYPE_L4, + .flash_size_reg = 0x1fff75e0, // "Flash size data register" (RM0394, + // sec 47.2, page 1586) + .flash_pagesize = 0x800, // 2k (DS12469, sec 3.4, page 17) + // SRAM1 is 32k at 0x20000000 + // SRAM2 is 8k at 0x10000000 and 0x20008000 + // (DS12469, sec 3.5, page 18) + .sram_size = 0xa000, // 40k (DS12469, sec 3.5, page 18) + .bootrom_base = 0x1fff0000, // System Memory (RM0394, sec 3.3.1, table 8) + .bootrom_size = 0x7000, // 28k, same source as base + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + // STLINK_CHIPID_STM32_L43x_L44x + // RM0392 + .chip_id = STLINK_CHIPID_STM32_L43x_L44x, + .dev_type = "L43x/L44x", + .flash_type = STLINK_FLASH_TYPE_L4, + .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 43.2, page 1410) + .flash_pagesize = 0x800, // 2k (sec 3.2, page 74; also appears in sec 3.3.1 + // and tables 7-8 on pages 75-76) + // SRAM1 is "up to" 64k in the standard Cortex-M memory map; + // SRAM2 is 16k mapped at 0x10000000 (sec 2.3, page 73 for + // sizes; table 2, page 74 for SRAM2 location) + .sram_size = 0xc000, + .bootrom_base = 0x1fff0000, // Tables 4-6, pages 80-81 (Bank 1 system memory) + .bootrom_size = 0x7000, // 28k (per bank), same source as base + .option_base = STM32_L4_OPTION_BYTES_BASE, + .option_size = 4, + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + // STLINK_CHIPID_STM32_L45x_L46x + // RM0394 (updated version of RM0392?) + .chip_id = STLINK_CHIPID_STM32_L45x_L46x, + .dev_type = "L45x/46x", + .flash_type = STLINK_FLASH_TYPE_L4, + .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 45.2, page 1463) + .flash_pagesize = 0x800, // 2k (sec 3.2, page 73; also appears in sec 3.3.1 + // and tables 7 on pages 73-74) + // SRAM1 is 128k at 0x20000000; + // SRAM2 is 32k mapped at 0x10000000 (sec 2.4.2, table 3-4, + // page 68, also fig 2 on page 63) + .sram_size = 0x20000, + .bootrom_base = 0x1fff0000, // Tables 6, pages 71-72 (Bank 1 system + // memory, also fig 2 on page 63) + .bootrom_size = 0x7000, // 28k (per bank), same source as base + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + // STM32L47x/L48x + // RM0351 + .chip_id = STLINK_CHIPID_STM32_L4, + .dev_type = "L47x/L48x", + .flash_type = STLINK_FLASH_TYPE_L4, + .flash_size_reg = 0x1FFF75e0, // "Flash size data register" (sec 45.2, page 1671) + .flash_pagesize = 0x800, // 2k (sec 3.2, page 78; also appears in sec 3.3.1 + // and tables 4-6 on pages 79-81) + // SRAM1 is "up to" 96k in the standard Cortex-M memory map; + // SRAM2 is 32k mapped at at 0x10000000 (sec 2.3, page 73 for + // sizes; table 2, page 74 for SRAM2 location) + .sram_size = 0x18000, + .bootrom_base = 0x1fff0000, // Tables 4-6, pages 80-81 (Bank 1 system memory) + .bootrom_size = 0x7000, // 28k (per bank), same source as base + .option_base = STM32_L4_OPTION_BYTES_BASE, + .option_size = 4, + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + // STLINK_CHIPID_STM32_L496x_L4A6x + // RM0351 (rev 5) + .chip_id = STLINK_CHIPID_STM32_L496x_L4A6x, + .dev_type = "L496x/L4A6x", + .flash_type = STLINK_FLASH_TYPE_L4, + .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 49.2, page 1809) + .flash_pagesize = 0x800, // Page erase (2 Kbyte) (sec 3.2, page 93) + // SRAM1 is 256k at 0x20000000 + // SRAM2 is 64k at 0x20040000 (sec 2.2.1, fig 2, page 74) + .sram_size = 0x40000, // Embedded SRAM (sec 2.4, page 84) + .bootrom_base = 0x1fff0000, // System Memory (Bank 1) (sec 3.3.1) + .bootrom_size = 0x7000, // 28k (per bank), same source as base + .option_base = STM32_L4_OPTION_BYTES_BASE, + .option_size = 4, + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + // STM32L4PX + // RM0432 + .chip_id = STLINK_CHIPID_STM32_L4PX, + .dev_type = "L4Px", + .flash_type = STLINK_FLASH_TYPE_L4, + .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 58.2, page 2274) + .flash_pagesize = 0x1000, // 4k, section 3.3, pg 117-120 + // TODO: flash_pagesize can be 8k depend on the dual-bank mode and flash size + .sram_size = 0xa0000, // 192k (SRAM1) + 64k SRAM2 + 384k SRAM3 = 640k, or 0xA0000 + .bootrom_base = 0x1fff0000, // 3.3.1, pg 117 + .bootrom_size = 0x7000, // 28k (per bank), same source as base (pg 117) + .flags = CHIP_F_HAS_DUAL_BANK | CHIP_F_HAS_SWO_TRACING, + }, + { + // STM32L4RX + // RM0432 + .chip_id = STLINK_CHIPID_STM32_L4Rx, + .dev_type = "L4Rx", + .flash_type = STLINK_FLASH_TYPE_L4, + .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 58.2, page 2274) + .flash_pagesize = 0x1000, // 4k, section 3.3, pg 117-120 + // TODO: flash_pagesize can be 8k depend on the dual-bank mode and flash size + .sram_size = 0xa0000, // 192k (SRAM1) + 64k SRAM2 + 384k SRAM3 = 640k, or 0xA0000 + .bootrom_base = 0x1fff0000, // 3.3.1, pg 117 + .bootrom_size = 0x7000, // 28k (per bank), same source as base (pg 117) + .flags = CHIP_F_HAS_DUAL_BANK | CHIP_F_HAS_SWO_TRACING, + }, { // STM32WB55xx, STM32WB35xx, STM32WB50CG/30CE // RM0434, RM0471 From 4132973ddfcf48abb3046d0f15c2ec4321a43891 Mon Sep 17 00:00:00 2001 From: hydroconstructor Date: Fri, 7 Jan 2022 00:45:25 +0400 Subject: [PATCH 337/503] usb.c refactoring request: remove getenv("STLINK_DEVICE") There is no enironment variable "STLINK_DEVICE" in user system, and program do not set it. So I removed all code which works with it. --- src/stlink-lib/usb.c | 36 ++---------------------------------- 1 file changed, 2 insertions(+), 34 deletions(-) diff --git a/src/stlink-lib/usb.c b/src/stlink-lib/usb.c index 65e8f4e25..2e99e82be 100644 --- a/src/stlink-lib/usb.c +++ b/src/stlink-lib/usb.c @@ -1134,33 +1134,8 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, enum connect_type connect, #endif libusb_device **list = NULL; - // TODO: We should use ssize_t and use it as a counter if > 0. - // As per libusb API: ssize_t libusb_get_device_list (libusb_context *ctx, libusb_device ***list) - int cnt = (int)libusb_get_device_list(slu->libusb_ctx, &list); + ssize_t cnt = libusb_get_device_list(slu->libusb_ctx, &list); struct libusb_device_descriptor desc; - int devBus = 0; - int devAddr = 0; - - // TODO: Reading a environment variable in a usb open function is not very nice, this should - // be refactored and moved into the CLI tools, and instead of giving USB_BUS:USB_ADDR a real - // stlink serial string should be passed to this function. Probably people are using this - // but this is very odd because as programmer can change to multiple busses and it is better - // to detect them based on serial. - char *device = getenv("STLINK_DEVICE"); - - if (device) { - char *c = strchr(device, ':'); - - if (c == NULL) { - WLOG("STLINK_DEVICE must be : format\n"); - goto on_error; - } - - devBus = atoi(device); - *c++ = 0; - devAddr = atoi(c); - ILOG("bus %03d dev %03d\n", devBus, devAddr); - } while (cnt-- > 0) { struct libusb_device_handle *handle; @@ -1169,13 +1144,6 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, enum connect_type connect, if (desc.idVendor != STLINK_USB_VID_ST) { continue; } - if (devBus && devAddr) { - if ((libusb_get_bus_number(list[cnt]) != devBus) || - (libusb_get_device_address(list[cnt]) != devAddr)) { - continue; - } - } - ret = libusb_open(list[cnt], &handle); if (ret) { continue; } // could not open device @@ -1202,7 +1170,7 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, enum connect_type connect, } if (cnt < 0) { - WLOG ("Couldn't find %s ST-Link devices\n", (devBus && devAddr) ? "matched" : "any"); + WLOG ("Couldn't find any ST-Link devices\n"); libusb_free_device_list(list, 1); goto on_error; } else { From 42790f3f169e10d51dfe4bb982d64b24389a62ab Mon Sep 17 00:00:00 2001 From: Antoine Faure Date: Tue, 21 Dec 2021 09:48:10 +1300 Subject: [PATCH 338/503] st-flash erase addr size --- inc/stlink.h | 1 + src/common.c | 24 +++++++++++++++--------- src/st-flash/flash.c | 7 +++++-- src/st-flash/flash_opts.c | 19 ++++++++++++++++++- 4 files changed, 39 insertions(+), 12 deletions(-) diff --git a/inc/stlink.h b/inc/stlink.h index 81dc7902e..852e95e42 100644 --- a/inc/stlink.h +++ b/inc/stlink.h @@ -274,6 +274,7 @@ int stlink_trace_enable(stlink_t* sl, uint32_t frequency); int stlink_trace_disable(stlink_t* sl); int stlink_trace_read(stlink_t* sl, uint8_t* buf, size_t size); int stlink_erase_flash_mass(stlink_t* sl); +int stlink_erase_flash_section(stlink_t *sl, stm32_addr_t base_addr, size_t size); int stlink_write_flash(stlink_t* sl, stm32_addr_t address, uint8_t* data, uint32_t length, uint8_t eraseonly); int stlink_parse_ihex(const char* path, uint8_t erased_pattern, uint8_t * * mem, size_t * size, uint32_t * begin); uint8_t stlink_get_erased_pattern(stlink_t *sl); diff --git a/src/common.c b/src/common.c index bdd6f5bab..fb5e431fa 100644 --- a/src/common.c +++ b/src/common.c @@ -2951,19 +2951,13 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { return check_flash_error(sl); } -int stlink_erase_flash_mass(stlink_t *sl) { - int err = 0; - - // TODO: User MER bit to mass-erase WB series. - if (sl->flash_type == STLINK_FLASH_TYPE_L0 || - sl->flash_type == STLINK_FLASH_TYPE_WB) { +int stlink_erase_flash_section(stlink_t *sl, stm32_addr_t base_addr, size_t size) { // erase each page - int i = 0, num_pages = (int)(sl->flash_size / sl->flash_pgsz); - + int i = 0, num_pages = (int)(size / sl->flash_pgsz); for (i = 0; i < num_pages; i++) { // addr must be an addr inside the page stm32_addr_t addr = - (stm32_addr_t)sl->flash_base + i * (stm32_addr_t)sl->flash_pgsz; + (stm32_addr_t)base_addr + i * (stm32_addr_t)sl->flash_pgsz; if (stlink_erase_flash_page(sl, addr)) { WLOG("Failed to erase_flash_page(%#x) == -1\n", addr); @@ -2975,6 +2969,18 @@ int stlink_erase_flash_mass(stlink_t *sl) { } fprintf(stdout, "\n"); + return 0; +} + +int stlink_erase_flash_mass(stlink_t *sl) { + int err = 0; + + // TODO: User MER bit to mass-erase WB series. + if (sl->flash_type == STLINK_FLASH_TYPE_L0 || + sl->flash_type == STLINK_FLASH_TYPE_WB) { + + stlink_erase_flash_section(sl, sl->flash_base, sl->flash_size); + } else { wait_flash_busy(sl); clear_flash_error(sl); diff --git a/src/st-flash/flash.c b/src/st-flash/flash.c index 51702b683..b4b596cfc 100644 --- a/src/st-flash/flash.c +++ b/src/st-flash/flash.c @@ -27,7 +27,7 @@ static void cleanup(int signum) { static void usage(void) { puts("command line: ./st-flash [--debug] [--reset] [--connect-under-reset] [--hot-plug] [--opt] [--serial ] [--format ] [--flash=] [--freq=] [--area=] {read|write} [path] [addr] [size]"); - puts("command line: ./st-flash [--debug] [--connect-under-reset] [--hot-plug] [--freq=] [--serial ] erase"); + puts("command line: ./st-flash [--debug] [--connect-under-reset] [--hot-plug] [--freq=] [--serial ] erase [addr] [size]"); puts("command line: ./st-flash [--debug] [--freq=] [--serial ] reset"); puts(" , and : Use hex format."); puts(" : Use decimal, octal or hex (prefix 0xXXX) format, optionally followed by k=KB, or m=MB (eg. --flash=128k)"); @@ -168,7 +168,10 @@ int main(int ac, char** av) { goto on_error; } } else if (o.cmd == FLASH_CMD_ERASE) { - err = stlink_erase_flash_mass(sl); + if (o.size != 0 && o.addr >= sl->flash_base && (o.addr + o.size) <= (sl->flash_base + sl->flash_size)) + err = stlink_erase_flash_section(sl, o.addr, o.size); + else + err = stlink_erase_flash_mass(sl); if (err == -1) { printf("stlink_erase_flash_mass() == -1\n"); diff --git a/src/st-flash/flash_opts.c b/src/st-flash/flash_opts.c index 172a24468..984156aa3 100644 --- a/src/st-flash/flash_opts.c +++ b/src/st-flash/flash_opts.c @@ -234,7 +234,24 @@ int flash_get_opts(struct flash_opts* o, int ac, char** av) { return(-1); case FLASH_CMD_ERASE: // no more arguments expected - if (ac != 0) { return(-1); } + if (ac != 0 && ac != 2) { return(-1); } + if (ac == 2) { + uint32_t address; + result = get_integer_from_char_array(av[0], &address); + if (result != 0) { + return bad_arg ("addr"); + } else { + o->addr = (stm32_addr_t) address; + } + + uint32_t size; + result = get_integer_from_char_array(av[1], &size); + if (result != 0) { + return bad_arg ("size"); + } else { + o->size = (size_t) size; + } + } break; From b519c63e500de3d146132ffafb67d058d9ecf974 Mon Sep 17 00:00:00 2001 From: hydroconstructor Date: Sun, 9 Jan 2022 19:02:22 +0400 Subject: [PATCH 339/503] #1214 issue fix Error in file size comparizon. Due to type casting, instead of compare file size with max. singed int value, it compares with -1. Then function returns with error message. --- src/common.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/src/common.c b/src/common.c index bdd6f5bab..99fdde325 100644 --- a/src/common.c +++ b/src/common.c @@ -27,6 +27,10 @@ #define O_BINARY 0 #endif +#ifndef MAX_FILE_SIZE +#define MAX_FILE_SIZE (1<<20) // signed long int max value +#endif + #ifdef _MSC_VER #define __attribute__(x) #endif @@ -2200,8 +2204,9 @@ static int map_file(mapped_file_t *mf, const char *path) { if (sizeof(st.st_size) != sizeof(size_t)) { // on 32 bit systems, check if there is an overflow - if (st.st_size > (off_t)SSIZE_MAX) { - fprintf(stderr, "mmap() size_t overflow for file %s\n", path); + if (st.st_size > (off_t)MAX_FILE_SIZE /*1 GB*/ ) { + // limit file size to 1 GB + fprintf(stderr, "mmap() file %s too big\n", path); goto on_error; } } From 14498bb3c011c70d5ba66f26de2a8c11eed68b8d Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 9 Jan 2022 16:39:54 +0100 Subject: [PATCH 340/503] Restructuring of STM32 definitions - Moved enum stlink_stm32_chipids to stm32.h - Moved additional MCU defines to stlink.h - Minor formatting improvements - Commented comparison for old/new chipid db --- inc/stlink.h | 4 ++ inc/stm32.h | 118 ++++++++++++++++++++++++++++++++-------- src/stlink-lib/chipid.c | 69 +++++++++++------------ src/stlink-lib/chipid.h | 77 ++------------------------ 4 files changed, 139 insertions(+), 129 deletions(-) diff --git a/inc/stlink.h b/inc/stlink.h index 81dc7902e..d7cc0006e 100644 --- a/inc/stlink.h +++ b/inc/stlink.h @@ -83,6 +83,10 @@ enum target_state { #define STLINK_F_HAS_DPBANKSEL (1 << 8) #define STLINK_F_HAS_RW8_512BYTES (1 << 9) +/* Additional MCU features */ +#define CHIP_F_HAS_DUAL_BANK (1 << 0) +#define CHIP_F_HAS_SWO_TRACING (1 << 1) + /* Error code */ #define STLINK_DEBUG_ERR_OK 0x80 #define STLINK_DEBUG_ERR_FAULT 0x81 diff --git a/inc/stm32.h b/inc/stm32.h index 15e0ff147..7a5e983a4 100644 --- a/inc/stm32.h +++ b/inc/stm32.h @@ -7,37 +7,111 @@ #ifndef STM32_H #define STM32_H -/* Cortex core ids */ -#define STM32VL_CORE_ID 0x1ba01477 -#define STM32F7_CORE_ID 0x5ba02477 -#define STM32H7_CORE_ID 0x6ba02477 // STM32H7 SWD ID Code -#define STM32H7_CORE_ID_JTAG 0x6ba00477 // STM32H7 JTAG ID Code (RM0433 pg3065) +/* Cortex-M core ids */ +#define STM32VL_CORE_ID 0x1ba01477 +#define STM32F7_CORE_ID 0x5ba02477 +#define STM32H7_CORE_ID 0x6ba02477 // STM32H7 SWD ID Code +#define STM32H7_CORE_ID_JTAG 0x6ba00477 // STM32H7 JTAG ID Code (RM0433 p.3065) -/* Constant STM32 memory map figures */ -#define STM32_SRAM_BASE ((uint32_t)0x20000000) -#define STM32_FLASH_BASE ((uint32_t)0x08000000) -#define STM32_F1_FLASH_BANK2_BASE ((uint32_t)0x08080000) +/* Constant STM32 memory address */ +#define STM32_SRAM_BASE ((uint32_t)0x20000000) +#define STM32_FLASH_BASE ((uint32_t)0x08000000) -#define STM32_H7_FLASH_BANK2_BASE ((uint32_t)0x08100000) +#define STM32_F1_FLASH_BANK2_BASE ((uint32_t)0x08080000) +#define STM32_H7_FLASH_BANK2_BASE ((uint32_t)0x08100000) -#define STM32_F4_OPTION_BYTES_BASE ((uint32_t)0x40023C14) -#define STM32_H7_OPTION_BYTES_BASE ((uint32_t)0x5200201C) +/* Constant STM32 option bytes base memory address */ +#define STM32_F4_OPTION_BYTES_BASE ((uint32_t)0x40023c14) -#define STM32_L0_OPTION_BYTES_BASE ((uint32_t)0x1FF80000) -#define STM32_L1_OPTION_BYTES_BASE ((uint32_t)0x1FF80000) +#define STM32_H7_OPTION_BYTES_BASE ((uint32_t)0x5200201c) -#define STM32_F7_OPTION_BYTES_BASE ((uint32_t)0x1FFF0000) +#define STM32_L0_OPTION_BYTES_BASE ((uint32_t)0x1ff80000) +#define STM32_L1_OPTION_BYTES_BASE ((uint32_t)0x1ff80000) -#define STM32_G0_OPTION_BYTES_BASE ((uint32_t)0x1FFF7800) -#define STM32_L4_OPTION_BYTES_BASE ((uint32_t)0x1FFF7800) +#define STM32_F7_OPTION_BYTES_BASE ((uint32_t)0x1fff0000) -#define STM32_F2_OPTION_BYTES_BASE ((uint32_t)0x1FFFC000) +#define STM32_G0_OPTION_BYTES_BASE ((uint32_t)0x1fff7800) +#define STM32_L4_OPTION_BYTES_BASE ((uint32_t)0x1fff7800) -#define STM32_F0_OPTION_BYTES_BASE ((uint32_t)0x1FFFF800) -#define STM32_F1_OPTION_BYTES_BASE ((uint32_t)0x1FFFF800) -#define STM32_F3_OPTION_BYTES_BASE ((uint32_t)0x1FFFF800) -#define STM32_G4_OPTION_BYTES_BASE ((uint32_t)0x1FFFF800) +#define STM32_F2_OPTION_BYTES_BASE ((uint32_t)0x1fffc000) + +#define STM32_F0_OPTION_BYTES_BASE ((uint32_t)0x1ffff800) +#define STM32_F1_OPTION_BYTES_BASE ((uint32_t)0x1ffff800) +#define STM32_F3_OPTION_BYTES_BASE ((uint32_t)0x1ffff800) +#define STM32_G4_OPTION_BYTES_BASE ((uint32_t)0x1ffff800) + + +/* + * Chip IDs + * See DBGMCU_IDCODE register (0xE0042000) in appropriate programming manual + */ + +// stm32 chipids, only lower 12 bits... + +enum stlink_stm32_chipids { + STLINK_CHIPID_UNKNOWN = 0x000, + + STLINK_CHIPID_STM32_F1_MD = 0x410, /* medium density */ + STLINK_CHIPID_STM32_F2 = 0x411, + STLINK_CHIPID_STM32_F1_LD = 0x412, /* low density */ + STLINK_CHIPID_STM32_F4 = 0x413, + STLINK_CHIPID_STM32_F1_HD = 0x414, /* high density */ + STLINK_CHIPID_STM32_L4 = 0x415, + STLINK_CHIPID_STM32_L1_MD = 0x416, /* medium density */ + STLINK_CHIPID_STM32_L0 = 0x417, + STLINK_CHIPID_STM32_F1_CONN = 0x418, /* connectivity line */ + STLINK_CHIPID_STM32_F4_HD = 0x419, /* high density */ + STLINK_CHIPID_STM32_F1_VL_MD_LD = 0x420, /* value line medium & low density */ + STLINK_CHIPID_STM32_F446 = 0x421, + STLINK_CHIPID_STM32_F3 = 0x422, + STLINK_CHIPID_STM32_F4_LP = 0x423, + STLINK_CHIPID_STM32_L0_CAT2 = 0x425, + STLINK_CHIPID_STM32_L1_MD_PLUS = 0x427, /* medium density plus */ + STLINK_CHIPID_STM32_F1_VL_HD = 0x428, /* value line high density */ + STLINK_CHIPID_STM32_L1_CAT2 = 0x429, + STLINK_CHIPID_STM32_F1_XLD = 0x430, /* extra low density plus */ + STLINK_CHIPID_STM32_F411xx = 0x431, + STLINK_CHIPID_STM32_F37x = 0x432, + STLINK_CHIPID_STM32_F4_DE = 0x433, + STLINK_CHIPID_STM32_F4_DSI = 0x434, + STLINK_CHIPID_STM32_L43x_L44x = 0x435, + STLINK_CHIPID_STM32_L1_MD_PLUS_HD = 0x436, /* medium density plus & high density */ + STLINK_CHIPID_STM32_L152_RE = 0x437, + STLINK_CHIPID_STM32_F334 = 0x438, + STLINK_CHIPID_STM32_F3xx_SMALL = 0x439, + STLINK_CHIPID_STM32_F0 = 0x440, + STLINK_CHIPID_STM32_F412 = 0x441, + STLINK_CHIPID_STM32_F09x = 0x442, + STLINK_CHIPID_STM32_F0xx_SMALL = 0x444, + STLINK_CHIPID_STM32_F04 = 0x445, + STLINK_CHIPID_STM32_F303_HD = 0x446, /* high density */ + STLINK_CHIPID_STM32_L0_CAT5 = 0x447, + STLINK_CHIPID_STM32_F0_CAN = 0x448, + STLINK_CHIPID_STM32_F7 = 0x449, /* Nucleo F746ZG board */ + STLINK_CHIPID_STM32_H74xxx = 0x450, /* RM0433, p.3189 */ + STLINK_CHIPID_STM32_F76xxx = 0x451, + STLINK_CHIPID_STM32_F72xxx = 0x452, /* Nucleo F722ZE board */ + STLINK_CHIPID_STM32_G0_CAT4 = 0x456, /* G051/G061 */ + STLINK_CHIPID_STM32_L011 = 0x457, + STLINK_CHIPID_STM32_F410 = 0x458, + STLINK_CHIPID_STM32_G0_CAT2 = 0x460, /* G070/G071/G081 */ + STLINK_CHIPID_STM32_L496x_L4A6x = 0x461, + STLINK_CHIPID_STM32_L45x_L46x = 0x462, + STLINK_CHIPID_STM32_F413 = 0x463, + STLINK_CHIPID_STM32_L41x_L42x = 0x464, + STLINK_CHIPID_STM32_G0_CAT1 = 0x466, /* G030/G031/G041 */ + STLINK_CHIPID_STM32_G0_CAT3 = 0x467, /* G0B1/G0C1 */ + STLINK_CHIPID_STM32_G4_CAT2 = 0x468, /* RM0440, section 46.6.1 "MCU device ID code" */ + STLINK_CHIPID_STM32_G4_CAT3 = 0x469, + STLINK_CHIPID_STM32_L4Rx = 0x470, /* RM0432, p.2247, found on the STM32L4R9I-DISCO board */ + STLINK_CHIPID_STM32_L4PX = 0x471, /* RM0432, p.2247 */ + STLINK_CHIPID_STM32_G4_CAT4 = 0x479, + STLINK_CHIPID_STM32_H7Ax = 0x480, /* RM0455, p.2863 */ + STLINK_CHIPID_STM32_H72x = 0x483, /* RM0468, p.3199 */ + STLINK_CHIPID_STM32_WB55 = 0x495, + STLINK_CHIPID_STM32_WLE = 0x497, +}; #endif // STM32_H diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index 213d43f8c..e3556ca57 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -39,45 +39,46 @@ void dump_a_chip (FILE *fp, struct stlink_chipid_params *dev) { fprintf(fp, "flags %d\n\n", dev->flags); } -static int chipid_params_eq(const struct stlink_chipid_params *p1, const struct stlink_chipid_params *p2) -{ - return p1->chip_id == p2->chip_id && - p1->dev_type && p2->dev_type && - strcmp(p1->dev_type, p2->dev_type) == 0 && - p1->flash_type == p2->flash_type && - p1->flash_size_reg == p2->flash_size_reg && - p1->flash_pagesize == p2->flash_pagesize && - p1->sram_size == p2->sram_size && - p1->bootrom_base == p2->bootrom_base && - p1->bootrom_size == p2->bootrom_size && - p1->option_base == p2->option_base && - p1->option_size == p2->option_size && - p1->flags == p2->flags; -} - -struct stlink_chipid_params *stlink_chipid_get_params(uint32_t chipid) { +// static int chipid_params_eq(const struct stlink_chipid_params *p1, const struct stlink_chipid_params *p2) +// { +// return p1->chip_id == p2->chip_id && +// p1->dev_type && p2->dev_type && +// strcmp(p1->dev_type, p2->dev_type) == 0 && +// p1->flash_type == p2->flash_type && +// p1->flash_size_reg == p2->flash_size_reg && +// p1->flash_pagesize == p2->flash_pagesize && +// p1->sram_size == p2->sram_size && +// p1->bootrom_base == p2->bootrom_base && +// p1->bootrom_size == p2->bootrom_size && +// p1->option_base == p2->option_base && +// p1->option_size == p2->option_size && +// p1->flags == p2->flags; +// } + +struct stlink_chipid_params *stlink_chipid_get_params(uint32_t chip_id) { struct stlink_chipid_params *params = NULL; - struct stlink_chipid_params *p2; - +// struct stlink_chipid_params *p2; for (params = devicelist; params != NULL; params = params->next) - if (params->chip_id == chipid) { + if (params->chip_id == chip_id) { + fprintf(stderr, "\ndetected chip_id parametres\n\n"); + dump_a_chip(stderr, params); break; } - p2 = stlink_chipid_get_params_old(chipid); - -#if 1 - if (params == NULL) { - params = p2; - } else if (!chipid_params_eq(params, p2)) { - // fprintf (stderr, "Error, chipid params not identical\n"); - // return NULL; - fprintf(stderr, "---------- old ------------\n"); - dump_a_chip(stderr, p2); - fprintf(stderr, "---------- new ------------\n"); - dump_a_chip(stderr, params); - } -#endif +// p2 = stlink_chipid_get_params_old(chipid); + +// #if 1 +// if (params == NULL) { +// params = p2; +// } else if (!chipid_params_eq(params, p2)) { +// // fprintf (stderr, "Error, chipid params not identical\n"); +// // return NULL; +// fprintf(stderr, "---------- old ------------\n"); +// dump_a_chip(stderr, p2); +// fprintf(stderr, "---------- new ------------\n"); +// dump_a_chip(stderr, params); +// } +// #endif return(params); } diff --git a/src/stlink-lib/chipid.h b/src/stlink-lib/chipid.h index 426c22428..e821f0b57 100644 --- a/src/stlink-lib/chipid.h +++ b/src/stlink-lib/chipid.h @@ -1,83 +1,14 @@ #ifndef STLINK_CHIPID_H_ #define STLINK_CHIPID_H_ +#include +#include + #ifdef __cplusplus extern "C" { #endif -/** - * Chip IDs are explained in the appropriate programming manual for the - * DBGMCU_IDCODE register (0xE0042000) - * stm32 chipids, only lower 12 bits... - */ -enum stlink_stm32_chipids { - STLINK_CHIPID_UNKNOWN = 0x000, - - STLINK_CHIPID_STM32_F1_MD = 0x410, /* medium density */ - STLINK_CHIPID_STM32_F2 = 0x411, - STLINK_CHIPID_STM32_F1_LD = 0x412, /* low density */ - STLINK_CHIPID_STM32_F4 = 0x413, - STLINK_CHIPID_STM32_F1_HD = 0x414, /* high density */ - STLINK_CHIPID_STM32_L4 = 0x415, - STLINK_CHIPID_STM32_L1_MD = 0x416, /* medium density */ - STLINK_CHIPID_STM32_L0 = 0x417, - STLINK_CHIPID_STM32_F1_CONN = 0x418, /* connectivity line */ - STLINK_CHIPID_STM32_F4_HD = 0x419, /* high density */ - STLINK_CHIPID_STM32_F1_VL_MD_LD = 0x420, /* value line medium & low density */ - STLINK_CHIPID_STM32_F446 = 0x421, - STLINK_CHIPID_STM32_F3 = 0x422, - STLINK_CHIPID_STM32_F4_LP = 0x423, - STLINK_CHIPID_STM32_L0_CAT2 = 0x425, - STLINK_CHIPID_STM32_L1_MD_PLUS = 0x427, /* medium density plus */ - STLINK_CHIPID_STM32_F1_VL_HD = 0x428, /* value line high density */ - STLINK_CHIPID_STM32_L1_CAT2 = 0x429, - STLINK_CHIPID_STM32_F1_XLD = 0x430, /* extra low density plus */ - STLINK_CHIPID_STM32_F411xx = 0x431, - STLINK_CHIPID_STM32_F37x = 0x432, - STLINK_CHIPID_STM32_F4_DE = 0x433, - STLINK_CHIPID_STM32_F4_DSI = 0x434, - STLINK_CHIPID_STM32_L43x_L44x = 0x435, - STLINK_CHIPID_STM32_L1_MD_PLUS_HD = 0x436, /* medium density plus & high density */ - STLINK_CHIPID_STM32_L152_RE = 0x437, - STLINK_CHIPID_STM32_F334 = 0x438, - STLINK_CHIPID_STM32_F3xx_SMALL = 0x439, - STLINK_CHIPID_STM32_F0 = 0x440, - STLINK_CHIPID_STM32_F412 = 0x441, - STLINK_CHIPID_STM32_F09x = 0x442, - STLINK_CHIPID_STM32_F0xx_SMALL = 0x444, - STLINK_CHIPID_STM32_F04 = 0x445, - STLINK_CHIPID_STM32_F303_HD = 0x446, /* high density */ - STLINK_CHIPID_STM32_L0_CAT5 = 0x447, - STLINK_CHIPID_STM32_F0_CAN = 0x448, - STLINK_CHIPID_STM32_F7 = 0x449, /* ID found on the Nucleo F746ZG board */ - STLINK_CHIPID_STM32_H74xxx = 0x450, /* RM0433, p.3189 */ - STLINK_CHIPID_STM32_F76xxx = 0x451, - STLINK_CHIPID_STM32_F72xxx = 0x452, /* ID found on the Nucleo F722ZE board */ - STLINK_CHIPID_STM32_G0_CAT4 = 0x456, /* G051/G061 */ - STLINK_CHIPID_STM32_L011 = 0x457, - STLINK_CHIPID_STM32_F410 = 0x458, - STLINK_CHIPID_STM32_G0_CAT2 = 0x460, /* G070/G071/G081 */ - STLINK_CHIPID_STM32_L496x_L4A6x = 0x461, - STLINK_CHIPID_STM32_L45x_L46x = 0x462, - STLINK_CHIPID_STM32_F413 = 0x463, - STLINK_CHIPID_STM32_L41x_L42x = 0x464, - STLINK_CHIPID_STM32_G0_CAT1 = 0x466, /* G030/G031/G041 */ - STLINK_CHIPID_STM32_G0_CAT3 = 0x467, /* G0B1/G0C1 */ - STLINK_CHIPID_STM32_G4_CAT2 = 0x468, /* RM0440, s46.6.1 "MCU device ID code" */ - STLINK_CHIPID_STM32_G4_CAT3 = 0x469, - STLINK_CHIPID_STM32_L4Rx = 0x470, /* RM0432, p. 2247, found on the STM32L4R9I-DISCO board */ - STLINK_CHIPID_STM32_L4PX = 0x471, /* RM0432, p. 2247 */ - STLINK_CHIPID_STM32_G4_CAT4 = 0x479, - STLINK_CHIPID_STM32_H7Ax = 0x480, /* RM0455, p.2863 */ - STLINK_CHIPID_STM32_H72x = 0x483, /* RM0468, p.3199 */ - STLINK_CHIPID_STM32_WB55 = 0x495, - STLINK_CHIPID_STM32_WLE = 0x497 -}; - -#define CHIP_F_HAS_DUAL_BANK (1 << 0) -#define CHIP_F_HAS_SWO_TRACING (1 << 1) - -/** Chipid parameters */ +/** Chipid parametres */ struct stlink_chipid_params { char *dev_type; char *ref_manual_id; From 5cde863c0382d92ca0d6ea027a7a3b24926a44e0 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 9 Jan 2022 21:52:55 +0100 Subject: [PATCH 341/503] Switch-over to new chip-files --- inc/stlink.h | 26 +++++----- src/stlink-lib/chipid.c | 86 +++++++++++++++++----------------- src/stlink-lib/chipid_db_old.h | 4 +- 3 files changed, 59 insertions(+), 57 deletions(-) diff --git a/inc/stlink.h b/inc/stlink.h index d7cc0006e..0c1ca73a4 100644 --- a/inc/stlink.h +++ b/inc/stlink.h @@ -106,19 +106,21 @@ enum target_state { #define C_BUF_LEN 32 +/* Old flash type definitions */ +// TODO: Transition to the new defines in stm32.h enum stlink_flash_type { - STLINK_FLASH_TYPE_UNKNOWN = 0, - STLINK_FLASH_TYPE_F0, // used by f0, f1 (except f1xl),f3. */ - STLINK_FLASH_TYPE_F1_XL, // f0 flash with dual bank, apparently */ - STLINK_FLASH_TYPE_F4, // used by f2, f4 */ - STLINK_FLASH_TYPE_F7, - STLINK_FLASH_TYPE_L0, // l0, l1 */ - STLINK_FLASH_TYPE_L4, // l4, l4+ */ - STLINK_FLASH_TYPE_G0, - STLINK_FLASH_TYPE_G4, - STLINK_FLASH_TYPE_WB, - STLINK_FLASH_TYPE_H7, - STLINK_FLASH_TYPE_MAX, + /* 0 */ STLINK_FLASH_TYPE_UNKNOWN = 0, + /* 1 */ STLINK_FLASH_TYPE_F0, // used by f0, f1 (except f1xl),f3. */ + /* 2 */ STLINK_FLASH_TYPE_F1_XL, // f0 flash with dual bank */ + /* 3 */ STLINK_FLASH_TYPE_F4, // used by f2, f4 */ + /* 4 */ STLINK_FLASH_TYPE_F7, + /* 5 */ STLINK_FLASH_TYPE_L0, // l0, l1 */ + /* 6 */ STLINK_FLASH_TYPE_L4, // l4, l4+ */ + /* 7 */ STLINK_FLASH_TYPE_G0, + /* 8 */ STLINK_FLASH_TYPE_G4, + /* 9 */ STLINK_FLASH_TYPE_WB, + /* 10 */ STLINK_FLASH_TYPE_H7, + /* 11 */ STLINK_FLASH_TYPE_MAX, }; struct stlink_reg { diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index e3556ca57..4ab83ba3d 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -1,6 +1,6 @@ #include #include "chipid.h" -#include "chipid_db_old.h" +//#include "chipid_db_old.h" #include #include @@ -9,17 +9,17 @@ #include -struct stlink_chipid_params *stlink_chipid_get_params_old(uint32_t chipid) { - struct stlink_chipid_params *params = NULL; +// struct stlink_chipid_params *stlink_chipid_get_params_old(uint32_t chipid) { +// struct stlink_chipid_params *params = NULL; - for (size_t n = 0; n < STLINK_ARRAY_SIZE(devices); n++) - if (devices[n].chip_id == chipid) { - params = &devices[n]; - break; - } +// for (size_t n = 0; n < STLINK_ARRAY_SIZE(devices); n++) +// if (devices[n].chip_id == chipid) { +// params = &devices[n]; +// break; +// } - return (params); -} +// return (params); +// } static struct stlink_chipid_params *devicelist; @@ -165,7 +165,7 @@ void process_chipfile(char *fname) { while ((pp = strtok (NULL, " \t\n"))) { if (strcmp (pp, "none") == 0) { - ts->flags = 0; // not necessary: calloc did this already. + // NOP } else if (strcmp (pp, "dualbank") == 0) { ts->flags |= CHIP_F_HAS_DUAL_BANK; } else if (strcmp (pp, "swo") == 0) { @@ -187,37 +187,37 @@ void process_chipfile(char *fname) { devicelist = ts; } -void dump_chips (void) { - struct stlink_chipid_params *ts; - char *p, buf[100]; - FILE *fp; - - for (size_t n = 0; n < STLINK_ARRAY_SIZE(devices); n++) { - ts = &devices[n]; - - strcpy(buf, ts->dev_type); - - while ((p = strchr(buf, '/'))) // change slashes to underscore. - *p = '_'; - - strcat(buf, ".chip"); - fp = fopen(buf, "w"); - fprintf(fp, "# Device Type: %s\n", ts->dev_type); - fprintf(fp, "# Reference Manual: RM%s\n", ts->ref_manual_id); - fprintf(fp, "#\n"); - fprintf(fp, "chip_id %x\n", ts->chip_id); - fprintf(fp, "flash_type %x\n", ts->flash_type); - fprintf(fp, "flash_size_reg %x\n", ts->flash_size_reg); - fprintf(fp, "flash_pagesize %x\n", ts->flash_pagesize); - fprintf(fp, "sram_size %x\n", ts->sram_size); - fprintf(fp, "bootrom_base %x\n", ts->bootrom_base); - fprintf(fp, "bootrom_size %x\n", ts->bootrom_size); - fprintf(fp, "option_base %x\n", ts->option_base); - fprintf(fp, "option_size %x\n", ts->option_size); - fprintf(fp, "flags %x\n\n", ts->flags); - fclose(fp); - } -} +// void dump_chips (void) { +// struct stlink_chipid_params *ts; +// char *p, buf[100]; +// FILE *fp; + +// for (size_t n = 0; n < STLINK_ARRAY_SIZE(devices); n++) { +// ts = &devices[n]; + +// strcpy(buf, ts->dev_type); + +// while ((p = strchr(buf, '/'))) // change slashes to underscore. +// *p = '_'; + +// strcat(buf, ".chip"); +// fp = fopen(buf, "w"); +// fprintf(fp, "# Device Type: %s\n", ts->dev_type); +// fprintf(fp, "# Reference Manual: RM%s\n", ts->ref_manual_id); +// fprintf(fp, "#\n"); +// fprintf(fp, "chip_id %x\n", ts->chip_id); +// fprintf(fp, "flash_type %x\n", ts->flash_type); +// fprintf(fp, "flash_size_reg %x\n", ts->flash_size_reg); +// fprintf(fp, "flash_pagesize %x\n", ts->flash_pagesize); +// fprintf(fp, "sram_size %x\n", ts->sram_size); +// fprintf(fp, "bootrom_base %x\n", ts->bootrom_base); +// fprintf(fp, "bootrom_size %x\n", ts->bootrom_size); +// fprintf(fp, "option_base %x\n", ts->option_base); +// fprintf(fp, "option_size %x\n", ts->option_size); +// fprintf(fp, "flags %x\n\n", ts->flags); +// fclose(fp); +// } +// } #if defined(STLINK_HAVE_DIRENT_H) #include @@ -248,7 +248,7 @@ void init_chipids(char *dir_to_scan) { closedir(d); } else { perror (dir_to_scan); - return; // XXX + return; } } #endif //STLINK_HAVE_DIRENT_H diff --git a/src/stlink-lib/chipid_db_old.h b/src/stlink-lib/chipid_db_old.h index 7acfef409..6578e35be 100644 --- a/src/stlink-lib/chipid_db_old.h +++ b/src/stlink-lib/chipid_db_old.h @@ -5,7 +5,7 @@ // change it both here and in the corresponding // config/chips/*.chip file. -static struct stlink_chipid_params devices[] = { +//static struct stlink_chipid_params devices[] = { { // STM32F03x // RM0091 @@ -874,4 +874,4 @@ static struct stlink_chipid_params devices[] = { .bootrom_base = 0x0, .bootrom_size = 0x0, }, -}; \ No newline at end of file +//}; \ No newline at end of file From 9b07c1dc191181b2d4311b2767a5731db1526f0c Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 9 Jan 2022 22:55:56 +0100 Subject: [PATCH 342/503] Transition to new enum stm32_flash_type --- config/chips/F03x.chip | 2 +- config/chips/F04x.chip | 2 +- config/chips/F05x.chip | 2 +- config/chips/F07x.chip | 2 +- config/chips/F09x.chip | 2 +- config/chips/F1xx_CL.chip | 2 +- config/chips/F1xx_HD.chip | 2 +- config/chips/F1xx_LD.chip | 2 +- config/chips/F1xx_MD.chip | 2 +- config/chips/F1xx_VL_HD.chip | 2 +- config/chips/F1xx_VL_MD_LD.chip | 2 +- config/chips/F1xx_XLD.chip | 2 +- config/chips/F2xx.chip | 2 +- config/chips/F301_F302_F318.chip | 2 +- config/chips/F302_F303_F358.chip | 2 +- config/chips/F302_F303_F398_HD.chip | 2 +- config/chips/F303_F328_F334.chip | 2 +- config/chips/F37x.chip | 2 +- config/chips/F401xB_xC.chip | 2 +- config/chips/F401xD_xE.chip | 2 +- config/chips/F410.chip | 2 +- config/chips/F411xC_xE.chip | 2 +- config/chips/F412.chip | 2 +- config/chips/F413_F423.chip | 2 +- config/chips/F42x_F43x.chip | 2 +- config/chips/F446.chip | 2 +- config/chips/F46x_F47x.chip | 2 +- config/chips/F4x5_F4x7.chip | 2 +- config/chips/F72x_F73x.chip | 2 +- config/chips/F74x_F75x.chip | 2 +- config/chips/F76x_F77x.chip | 2 +- config/chips/G03x_G04x.chip | 2 +- config/chips/G05x_G06x.chip | 2 +- config/chips/G07x_G08x.chip | 2 +- config/chips/G0Bx_G0Cx.chip | 2 +- config/chips/G43x_G44x.chip | 2 +- config/chips/G47x_G48x.chip | 2 +- config/chips/G49x_G4Ax.chip | 2 +- config/chips/H72x_H73x.chip | 2 +- config/chips/H74x_H75x.chip | 2 +- config/chips/H7Ax_H7Bx.chip | 2 +- config/chips/L0xxx_Cat_1.chip | 2 +- config/chips/L0xxx_Cat_2.chip | 2 +- config/chips/L0xxx_Cat_3.chip | 2 +- config/chips/L0xxx_Cat_5.chip | 2 +- config/chips/L1xx_Cat_1.chip | 2 +- config/chips/L1xx_Cat_2.chip | 2 +- config/chips/L1xx_Cat_3.chip | 2 +- config/chips/L1xx_Cat_4.chip | 2 +- config/chips/L1xx_Cat_5.chip | 2 +- config/chips/L41x_L42x.chip | 2 +- config/chips/L43x_L44x.chip | 2 +- config/chips/L45x_L46x.chip | 2 +- config/chips/L47x_L48x.chip | 2 +- config/chips/L496x_L4A6x.chip | 2 +- config/chips/L4Px.chip | 2 +- config/chips/L4Rx.chip | 2 +- config/chips/L5x5.chip | 2 +- config/chips/U5x5.chip | 2 +- config/chips/WBx0_WBx5.chip | 2 +- config/chips/WLx5.chip | 2 +- config/chips/unknown_device.chip | 2 +- inc/stlink.h | 5 +- inc/stm32.h | 18 + src/common.c | 505 ++++++++++++++-------------- src/st-flash/flash.c | 3 +- src/stlink-lib/chipid.c | 2 +- src/stlink-lib/chipid.h | 2 +- src/stlink-lib/flash_loader.c | 5 +- 69 files changed, 343 insertions(+), 321 deletions(-) diff --git a/config/chips/F03x.chip b/config/chips/F03x.chip index ea7fdb9e2..d19e6a657 100644 --- a/config/chips/F03x.chip +++ b/config/chips/F03x.chip @@ -3,7 +3,7 @@ dev_type STM32F03x ref_manual_id 0091 chip_id 0x444 // STLINK_CHIPID_STM32_F0xx_SMALL -flash_type 1 // STLINK_FLASH_TYPE_F0 +flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3 flash_size_reg 0x1ffff7cc flash_pagesize 0x400 // 1 KB sram_size 0x1000 // 4 KB diff --git a/config/chips/F04x.chip b/config/chips/F04x.chip index 3e702585b..7012d6d7e 100644 --- a/config/chips/F04x.chip +++ b/config/chips/F04x.chip @@ -3,7 +3,7 @@ dev_type STM32F04x ref_manual_id 0091 chip_id 0x445 // STLINK_CHIPID_STM32_F04 -flash_type 1 // STLINK_FLASH_TYPE_F0 +flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3 flash_size_reg 0x1ffff7cc flash_pagesize 0x400 // 1 KB sram_size 0x1800 // 6 KB diff --git a/config/chips/F05x.chip b/config/chips/F05x.chip index 1a4f61386..e987cf725 100644 --- a/config/chips/F05x.chip +++ b/config/chips/F05x.chip @@ -3,7 +3,7 @@ dev_type STM32F05x ref_manual_id 0091 chip_id 0x440 // STLINK_CHIPID_STM32_F0 -flash_type 1 // STLINK_FLASH_TYPE_F0 +flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3 flash_size_reg 0x1ffff7cc flash_pagesize 0x400 // 1 KB sram_size 0x2000 // 8 KB diff --git a/config/chips/F07x.chip b/config/chips/F07x.chip index 2a577b7b4..0f7513e1b 100644 --- a/config/chips/F07x.chip +++ b/config/chips/F07x.chip @@ -3,7 +3,7 @@ dev_type STM32F07x ref_manual_id 0091 chip_id 0x448 // STLINK_CHIPID_STM32_F0_CAN -flash_type 1 // STLINK_FLASH_TYPE_F0 +flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3 flash_size_reg 0x1ffff7cc flash_pagesize 0x800 // 2 KB sram_size 0x4000 // 16 KB diff --git a/config/chips/F09x.chip b/config/chips/F09x.chip index 9f419893e..3d3cc8c89 100644 --- a/config/chips/F09x.chip +++ b/config/chips/F09x.chip @@ -3,7 +3,7 @@ dev_type STM32F09x ref_manual_id 0091 chip_id 0x442 // STLINK_CHIPID_STM32_F09x -flash_type 1 // STLINK_FLASH_TYPE_F0 +flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3 flash_size_reg 0x1ffff7cc flash_pagesize 0x800 // 2 KB sram_size 0x8000 // 32 KB diff --git a/config/chips/F1xx_CL.chip b/config/chips/F1xx_CL.chip index 4c8bb0b8d..eb417132a 100644 --- a/config/chips/F1xx_CL.chip +++ b/config/chips/F1xx_CL.chip @@ -3,7 +3,7 @@ dev_type STM32F1xx_CL ref_manual_id 0008 chip_id 0x418 // STLINK_CHIPID_STM32_F1_CONN -flash_type 1 // STLINK_FLASH_TYPE_F0 +flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3 flash_size_reg 0x1ffff7e0 flash_pagesize 0x800 // 2 KB sram_size 0x10000 // 64 KB diff --git a/config/chips/F1xx_HD.chip b/config/chips/F1xx_HD.chip index 18757029a..5def8ebb9 100644 --- a/config/chips/F1xx_HD.chip +++ b/config/chips/F1xx_HD.chip @@ -3,7 +3,7 @@ dev_type F1xx_HD ref_manual_id 0008 chip_id 0x414 // STLINK_CHIPID_STM32_F1_HD -flash_type 1 // STLINK_FLASH_TYPE_F0 +flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3 flash_size_reg 0x1ffff7e0 flash_pagesize 0x800 // 2 KB sram_size 0x10000 // 64 KB diff --git a/config/chips/F1xx_LD.chip b/config/chips/F1xx_LD.chip index 8a8f5867d..33efe063a 100644 --- a/config/chips/F1xx_LD.chip +++ b/config/chips/F1xx_LD.chip @@ -3,7 +3,7 @@ dev_type STM32F1xx_LD ref_manual_id 0008 chip_id 0x412 // STLINK_CHIPID_STM32_F1_LD -flash_type 1 // STLINK_FLASH_TYPE_F0 +flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3 flash_size_reg 0x1ffff7e0 flash_pagesize 0x400 // 1 KB sram_size 0x2800 // 10 KB diff --git a/config/chips/F1xx_MD.chip b/config/chips/F1xx_MD.chip index be492f54a..5b250d9cd 100644 --- a/config/chips/F1xx_MD.chip +++ b/config/chips/F1xx_MD.chip @@ -3,7 +3,7 @@ dev_type STM32F1xx_MD ref_manual_id 0008 chip_id 0x410 // STLINK_CHIPID_STM32_F1_MD -flash_type 1 // STLINK_FLASH_TYPE_F0 +flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3 flash_size_reg 0x1ffff7e0 flash_pagesize 0x400 // 1 KB sram_size 0x5000 // 20 KB diff --git a/config/chips/F1xx_VL_HD.chip b/config/chips/F1xx_VL_HD.chip index f5ca6b023..1ceade91a 100644 --- a/config/chips/F1xx_VL_HD.chip +++ b/config/chips/F1xx_VL_HD.chip @@ -3,7 +3,7 @@ dev_type STM32F1xx_VL_HD ref_manual_id 0041 chip_id 0x428 // STLINK_CHIPID_STM32_F1_VL_HD -flash_type 1 // STLINK_FLASH_TYPE_F0 +flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3 flash_size_reg 0x1ffff7e0 flash_pagesize 0x800 // 2 KB sram_size 0x8000 // 32 KB diff --git a/config/chips/F1xx_VL_MD_LD.chip b/config/chips/F1xx_VL_MD_LD.chip index e79668c70..3f577f74e 100644 --- a/config/chips/F1xx_VL_MD_LD.chip +++ b/config/chips/F1xx_VL_MD_LD.chip @@ -3,7 +3,7 @@ dev_type STM32F1xx_VL_MD_LD ref_manual_id 0041 chip_id 0x420 // STLINK_CHIPID_STM32_F1_VL_MD_LD -flash_type 1 // STLINK_FLASH_TYPE_F0 +flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3 flash_size_reg 0x1ffff7e0 flash_pagesize 0x400 // 1 KB sram_size 0x2000 // 8 KB /* 0x1000 for low density devices */ diff --git a/config/chips/F1xx_XLD.chip b/config/chips/F1xx_XLD.chip index d7d8cf2b7..964105747 100644 --- a/config/chips/F1xx_XLD.chip +++ b/config/chips/F1xx_XLD.chip @@ -3,7 +3,7 @@ dev_type STM32F1xx_XLD ref_manual_id 0008 chip_id 0x430 // STLINK_CHIPID_STM32_F1_XLD -flash_type 2 // STLINK_FLASH_TYPE_F1_XL +flash_type 2 // STM32_FLASH_TYPE_F1_XL flash_size_reg 0x1ffff7e0 flash_pagesize 0x800 // 2 KB sram_size 0x18000 // 96 KB diff --git a/config/chips/F2xx.chip b/config/chips/F2xx.chip index 67c225af5..4cb99b2fc 100644 --- a/config/chips/F2xx.chip +++ b/config/chips/F2xx.chip @@ -3,7 +3,7 @@ dev_type STM32F2xx ref_manual_id 0033 chip_id 0x411 // STLINK_CHIPID_STM32_F2 -flash_type 3 // STLINK_FLASH_TYPE_F4 +flash_type 3 // STM32_FLASH_TYPE_F2_F4 flash_size_reg 0x1fff7a22 flash_pagesize 0x20000 // 128 KB sram_size 0x20000 // 128 KB diff --git a/config/chips/F301_F302_F318.chip b/config/chips/F301_F302_F318.chip index ee71dfe90..b35de12bf 100644 --- a/config/chips/F301_F302_F318.chip +++ b/config/chips/F301_F302_F318.chip @@ -3,7 +3,7 @@ dev_type STM32F301_F302_F318 ref_manual_id 0365 // also RM0366 chip_id 0x439 // STLINK_CHIPID_STM32_F3xx_SMALL -flash_type 1 // STLINK_FLASH_TYPE_F0 +flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3 flash_size_reg 0x1ffff7cc flash_pagesize 0x800 // 2 KB sram_size 0xa000 // 40 KB diff --git a/config/chips/F302_F303_F358.chip b/config/chips/F302_F303_F358.chip index 64d0651f2..6226ca8e8 100644 --- a/config/chips/F302_F303_F358.chip +++ b/config/chips/F302_F303_F358.chip @@ -3,7 +3,7 @@ dev_type STM32F302_F303_358 ref_manual_id 0365 // also RM0316 chip_id 0x422 // STLINK_CHIPID_STM32_F3 -flash_type 1 // STLINK_FLASH_TYPE_F0 +flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3 flash_size_reg 0x1ffff7cc flash_pagesize 0x800 // 2 KB sram_size 0xa000 // 40 KB diff --git a/config/chips/F302_F303_F398_HD.chip b/config/chips/F302_F303_F398_HD.chip index eaf36b74c..b4ad3aed8 100644 --- a/config/chips/F302_F303_F398_HD.chip +++ b/config/chips/F302_F303_F398_HD.chip @@ -3,7 +3,7 @@ dev_type STM32F302_F303_F398_HD ref_manual_id 0365 // also RM0316 (Rev 5) chip_id 0x446 // STLINK_CHIPID_STM32_F303_HD -flash_type 1 // STLINK_FLASH_TYPE_F0 +flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3 flash_size_reg 0x1ffff7cc flash_pagesize 0x800 // 2 KB sram_size 0x10000 // 64 KB diff --git a/config/chips/F303_F328_F334.chip b/config/chips/F303_F328_F334.chip index 2ecdbfb71..010c3b622 100644 --- a/config/chips/F303_F328_F334.chip +++ b/config/chips/F303_F328_F334.chip @@ -3,7 +3,7 @@ dev_type STM32F303_F328_F334 ref_manual_id 0364 // also RM0316 chip_id 0x438 // STLINK_CHIPID_STM32_F334 -flash_type 1 // STLINK_FLASH_TYPE_F0 +flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3 flash_size_reg 0x1ffff7cc flash_pagesize 0x800 // 2 KB sram_size 0x3000 // 12 KB diff --git a/config/chips/F37x.chip b/config/chips/F37x.chip index 1bd7ac421..9ca9d72f8 100644 --- a/config/chips/F37x.chip +++ b/config/chips/F37x.chip @@ -3,7 +3,7 @@ dev_type STM32F37x ref_manual_id 0313 chip_id 0x432 // STLINK_CHIPID_STM32_F37x -flash_type 1 // STLINK_FLASH_TYPE_F0 +flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3 flash_size_reg 0x1ffff7cc flash_pagesize 0x800 // 2 KB sram_size 0xa000 // 40 KB diff --git a/config/chips/F401xB_xC.chip b/config/chips/F401xB_xC.chip index fc93c2f1a..e1f37d94b 100644 --- a/config/chips/F401xB_xC.chip +++ b/config/chips/F401xB_xC.chip @@ -3,7 +3,7 @@ dev_type STM32F401xB_xC ref_manual_id 0368 chip_id 0x423 // STLINK_CHIPID_STM32_F4_LP -flash_type 3 // STLINK_FLASH_TYPE_F4 +flash_type 3 // STM32_FLASH_TYPE_F2_F4 flash_size_reg 0x1fff7a22 flash_pagesize 0x4000 // 16 KB sram_size 0x10000 // 64 KB diff --git a/config/chips/F401xD_xE.chip b/config/chips/F401xD_xE.chip index e31d5eace..f03661495 100644 --- a/config/chips/F401xD_xE.chip +++ b/config/chips/F401xD_xE.chip @@ -3,7 +3,7 @@ dev_type STM32F401xD_xE ref_manual_id 0368 chip_id 0x433 // STLINK_CHIPID_STM32_F4_DE -flash_type 3 // STLINK_FLASH_TYPE_F4 +flash_type 3 // STM32_FLASH_TYPE_F2_F4 flash_size_reg 0x1fff7a22 flash_pagesize 0x4000 // 16 KB sram_size 0x18000 // 96 KB diff --git a/config/chips/F410.chip b/config/chips/F410.chip index a8a7fbad0..6f7727921 100644 --- a/config/chips/F410.chip +++ b/config/chips/F410.chip @@ -3,7 +3,7 @@ dev_type STM32F410 ref_manual_id 0401 chip_id 0x458 // STLINK_CHIPID_STM32_F410 -flash_type 3 // STLINK_FLASH_TYPE_F4 +flash_type 3 // STM32_FLASH_TYPE_F2_F4 flash_size_reg 0x1fff7a22 flash_pagesize 0x4000 // 16 KB sram_size 0x8000 // 32 KB diff --git a/config/chips/F411xC_xE.chip b/config/chips/F411xC_xE.chip index cf2cbd2c1..5d624b7d9 100644 --- a/config/chips/F411xC_xE.chip +++ b/config/chips/F411xC_xE.chip @@ -3,7 +3,7 @@ dev_type STM32F411xC_xE ref_manual_id 0383 chip_id 0x431 // STLINK_CHIPID_STM32_F411xx -flash_type 3 // STLINK_FLASH_TYPE_F4 +flash_type 3 // STM32_FLASH_TYPE_F2_F4 flash_size_reg 0x1fff7a22 flash_pagesize 0x4000 // 16 KB sram_size 0x20000 // 128 KB diff --git a/config/chips/F412.chip b/config/chips/F412.chip index 4c866a3c5..bd18ec2ea 100644 --- a/config/chips/F412.chip +++ b/config/chips/F412.chip @@ -3,7 +3,7 @@ dev_type STM32F412 ref_manual_id 0402 chip_id 0x441 // STLINK_CHIPID_STM32_F412 -flash_type 3 // STLINK_FLASH_TYPE_F4 +flash_type 3 // STM32_FLASH_TYPE_F2_F4 flash_size_reg 0x1fff7a22 flash_pagesize 0x4000 // 16 KB sram_size 0x40000 // 256 KB diff --git a/config/chips/F413_F423.chip b/config/chips/F413_F423.chip index 81ca585f6..c7e036a2d 100644 --- a/config/chips/F413_F423.chip +++ b/config/chips/F413_F423.chip @@ -3,7 +3,7 @@ dev_type STM32F413_F423 ref_manual_id 0430 // RM0430 (Rev 2) chip_id 0x463 // STLINK_CHIPID_STM32_F413 -flash_type 3 // STLINK_FLASH_TYPE_F4 +flash_type 3 // STM32_FLASH_TYPE_F2_F4 flash_size_reg 0x1fff7a22 flash_pagesize 0x4000 // 16 KB sram_size 0x50000 // 320 KB diff --git a/config/chips/F42x_F43x.chip b/config/chips/F42x_F43x.chip index 2ec8fb8e8..cbb77e152 100644 --- a/config/chips/F42x_F43x.chip +++ b/config/chips/F42x_F43x.chip @@ -3,7 +3,7 @@ dev_type STM32F42x_F43x ref_manual_id 0090 // RM0090 (Rev. 2) chip_id 0x463 // STLINK_CHIPID_STM32_F4_HD -flash_type 3 // STLINK_FLASH_TYPE_F4 +flash_type 3 // STM32_FLASH_TYPE_F2_F4 flash_size_reg 0x1fff7a22 flash_pagesize 0x4000 // 16 KB sram_size 0x40000 // 256 KB diff --git a/config/chips/F446.chip b/config/chips/F446.chip index 8cebe358e..2ac868ddd 100644 --- a/config/chips/F446.chip +++ b/config/chips/F446.chip @@ -3,7 +3,7 @@ dev_type STM32F446 ref_manual_id 0390 chip_id 0x421 // STLINK_CHIPID_STM32_F446 -flash_type 3 // STLINK_FLASH_TYPE_F4 +flash_type 3 // STM32_FLASH_TYPE_F2_F4 flash_size_reg 0x1fff7a22 flash_pagesize 0x20000 // 128 KB sram_size 0x20000 // 128 KB diff --git a/config/chips/F46x_F47x.chip b/config/chips/F46x_F47x.chip index 2e4055f2c..e8d66cbd7 100644 --- a/config/chips/F46x_F47x.chip +++ b/config/chips/F46x_F47x.chip @@ -3,7 +3,7 @@ dev_type STM32F46x_F47x ref_manual_id 0090 // RM0090 (Rev. 2) chip_id 0x434 // STLINK_CHIPID_STM32_F4_DSI -flash_type 3 // STLINK_FLASH_TYPE_F4 +flash_type 3 // STM32_FLASH_TYPE_F2_F4 flash_size_reg 0x1fff7a22 flash_pagesize 0x4000 // 16 KB sram_size 0x40000 // 256 KB diff --git a/config/chips/F4x5_F4x7.chip b/config/chips/F4x5_F4x7.chip index 9313c8ae1..d75f74103 100644 --- a/config/chips/F4x5_F4x7.chip +++ b/config/chips/F4x5_F4x7.chip @@ -3,7 +3,7 @@ dev_type STM32F4x5_F4x7 ref_manual_id 0090 // RM0090 (Rev. 2) chip_id 0x413 // STLINK_CHIPID_STM32_F4 -flash_type 3 // STLINK_FLASH_TYPE_F4 +flash_type 3 // STM32_FLASH_TYPE_F2_F4 flash_size_reg 0x1fff7a22 flash_pagesize 0x4000 // 16 KB sram_size 0x30000 // 192 KB diff --git a/config/chips/F72x_F73x.chip b/config/chips/F72x_F73x.chip index 37dcd1234..c0f2df155 100644 --- a/config/chips/F72x_F73x.chip +++ b/config/chips/F72x_F73x.chip @@ -3,7 +3,7 @@ dev_type STM32F72x_F73x ref_manual_id 0431 chip_id 0x452 // STLINK_CHIPID_STM32_F72xxx -flash_type 3 // STLINK_FLASH_TYPE_F4 +flash_type 4 // STM32_FLASH_TYPE_F7 flash_size_reg 0x1ff07a22 flash_pagesize 0x800 // 2 KB sram_size 0x40000 // 256 KB diff --git a/config/chips/F74x_F75x.chip b/config/chips/F74x_F75x.chip index 96cc95217..fa0b6ddc2 100644 --- a/config/chips/F74x_F75x.chip +++ b/config/chips/F74x_F75x.chip @@ -3,7 +3,7 @@ dev_type STM32F74x_F75x ref_manual_id 0385 chip_id 0x449 // STLINK_CHIPID_STM32_F7 -flash_type 3 // STLINK_FLASH_TYPE_F4 +flash_type 4 // STM32_FLASH_TYPE_F7 flash_size_reg 0x1ff0f442 flash_pagesize 0x800 // 2 KB sram_size 0x50000 // 320 KB diff --git a/config/chips/F76x_F77x.chip b/config/chips/F76x_F77x.chip index a93aba2be..c1a5a9cf2 100644 --- a/config/chips/F76x_F77x.chip +++ b/config/chips/F76x_F77x.chip @@ -3,7 +3,7 @@ dev_type STM32F76x_F77x ref_manual_id 0410 chip_id 0x451 // STLINK_CHIPID_STM32_F76xxx -flash_type 4 // STLINK_FLASH_TYPE_F7 +flash_type 4 // STM32_FLASH_TYPE_F7 flash_size_reg 0x1ff0f442 flash_pagesize 0x800 // 2 KB sram_size 0x80000 // 512 KB diff --git a/config/chips/G03x_G04x.chip b/config/chips/G03x_G04x.chip index a21a9898f..aee016e0d 100644 --- a/config/chips/G03x_G04x.chip +++ b/config/chips/G03x_G04x.chip @@ -3,7 +3,7 @@ dev_type STM32G03x_G04x ref_manual_id 0444 // also RM454 chip_id 0x466 // STLINK_CHIPID_STM32_G0_CAT1 -flash_type 7 // STLINK_FLASH_TYPE_G0 +flash_type 5 // STM32_FLASH_TYPE_G0 flash_size_reg 0x1fff75e0 flash_pagesize 0x800 // 2 KB sram_size 0x2000 // 8 KB diff --git a/config/chips/G05x_G06x.chip b/config/chips/G05x_G06x.chip index 89af0825c..f92cad889 100644 --- a/config/chips/G05x_G06x.chip +++ b/config/chips/G05x_G06x.chip @@ -3,7 +3,7 @@ dev_type STM32G05x_G06x ref_manual_id 0444 chip_id 0x456 // STLINK_CHIPID_STM32_G0_CAT4 -flash_type 7 // STLINK_FLASH_TYPE_G0 +flash_type 5 // STM32_FLASH_TYPE_G0 flash_size_reg 0x1fff75e0 flash_pagesize 0x800 // 2 KB sram_size 0x9000 // 36 KB diff --git a/config/chips/G07x_G08x.chip b/config/chips/G07x_G08x.chip index c54de398f..29f527e73 100644 --- a/config/chips/G07x_G08x.chip +++ b/config/chips/G07x_G08x.chip @@ -3,7 +3,7 @@ dev_type STM32G07x_G08x ref_manual_id 0444 chip_id 0x460 // STLINK_CHIPID_STM32_G0_CAT2 -flash_type 7 // STLINK_FLASH_TYPE_G0 +flash_type 5 // STM32_FLASH_TYPE_G0 flash_size_reg 0x1fff75e0 flash_pagesize 0x800 // 2 KB sram_size 0x9000 // 36 KB diff --git a/config/chips/G0Bx_G0Cx.chip b/config/chips/G0Bx_G0Cx.chip index d8e0eb042..67254fbbd 100644 --- a/config/chips/G0Bx_G0Cx.chip +++ b/config/chips/G0Bx_G0Cx.chip @@ -3,7 +3,7 @@ dev_type STM32G0Bx_G0Cx ref_manual_id 0444 chip_id 0x467 // STLINK_CHIPID_STM32_G0_CAT3 -flash_type 7 // STLINK_FLASH_TYPE_G0 +flash_type 5 // STM32_FLASH_TYPE_G0 flash_size_reg 0x1fff75e0 flash_pagesize 0x800 // 2 KB sram_size 0x9000 // 36 KB diff --git a/config/chips/G43x_G44x.chip b/config/chips/G43x_G44x.chip index 455d65b8c..b33a1a0f8 100644 --- a/config/chips/G43x_G44x.chip +++ b/config/chips/G43x_G44x.chip @@ -3,7 +3,7 @@ dev_type STM32G43x_G44x ref_manual_id 0440 chip_id 0x468 // STLINK_CHIPID_STM32_G4_CAT2 -flash_type 8 // STLINK_FLASH_TYPE_G4 +flash_type 6 // STM32_FLASH_TYPE_G4 flash_size_reg 0x1fff75e0 flash_pagesize 0x800 // 2 KB sram_size 0x8000 // 32 KB diff --git a/config/chips/G47x_G48x.chip b/config/chips/G47x_G48x.chip index 250905c68..abf6a6f2d 100644 --- a/config/chips/G47x_G48x.chip +++ b/config/chips/G47x_G48x.chip @@ -3,7 +3,7 @@ dev_type STM32G47x_G48x ref_manual_id 0440 chip_id 0x469 // STLINK_CHIPID_STM32_G4_CAT3 -flash_type 8 // STLINK_FLASH_TYPE_G4 +flash_type 6 // STM32_FLASH_TYPE_G4 flash_size_reg 0x1fff75e0 flash_pagesize 0x800 // 2 KB sram_size 0x20000 // 128 KB diff --git a/config/chips/G49x_G4Ax.chip b/config/chips/G49x_G4Ax.chip index 9702541a8..3d8110f19 100644 --- a/config/chips/G49x_G4Ax.chip +++ b/config/chips/G49x_G4Ax.chip @@ -3,7 +3,7 @@ dev_type STM32G49x_G4Ax ref_manual_id 0440 chip_id 0x479 // STLINK_CHIPID_STM32_G4_CAT4 -flash_type 8 // STLINK_FLASH_TYPE_G4 +flash_type 6 // STM32_FLASH_TYPE_G4 flash_size_reg 0x1fff75e0 flash_pagesize 0x800 // 2 KB sram_size 0x1c000 // 112 KB diff --git a/config/chips/H72x_H73x.chip b/config/chips/H72x_H73x.chip index 183c7d197..1417cdb27 100644 --- a/config/chips/H72x_H73x.chip +++ b/config/chips/H72x_H73x.chip @@ -3,7 +3,7 @@ dev_type STM32H72x_H73x ref_manual_id 0468 chip_id 0x483 // STLINK_CHIPID_STM32_H72x -flash_type 10 // STLINK_FLASH_TYPE_H7 +flash_type 7 // STM32_FLASH_TYPE_H7 flash_size_reg 0x1ff1e880 flash_pagesize 0x20000 // 128 KB sram_size 0x20000 // 128 KB "DTCM" diff --git a/config/chips/H74x_H75x.chip b/config/chips/H74x_H75x.chip index 2e543b197..53a3e921a 100644 --- a/config/chips/H74x_H75x.chip +++ b/config/chips/H74x_H75x.chip @@ -3,7 +3,7 @@ dev_type STM32H74x_H75x ref_manual_id 0433 chip_id 0x450 // STLINK_CHIPID_STM32_H74xxx -flash_type 10 // STLINK_FLASH_TYPE_H7 +flash_type 7 // STM32_FLASH_TYPE_H7 flash_size_reg 0x1ff1e880 flash_pagesize 0x20000 // 128 KB sram_size 0x20000 // 128 KB "DTCM" diff --git a/config/chips/H7Ax_H7Bx.chip b/config/chips/H7Ax_H7Bx.chip index b5fe72119..516c4260e 100644 --- a/config/chips/H7Ax_H7Bx.chip +++ b/config/chips/H7Ax_H7Bx.chip @@ -3,7 +3,7 @@ dev_type STM32H7Ax_H7Bx ref_manual_id 0455 chip_id 0x480 // STLINK_CHIPID_STM32_H7Ax -flash_type 10 // STLINK_FLASH_TYPE_H7 +flash_type 7 // STM32_FLASH_TYPE_H7 flash_size_reg 0x08fff80c flash_pagesize 0x2000 // 8 KB sram_size 0x20000 // 128 KB "DTCM" diff --git a/config/chips/L0xxx_Cat_1.chip b/config/chips/L0xxx_Cat_1.chip index 1dd8a1acb..6dc227024 100644 --- a/config/chips/L0xxx_Cat_1.chip +++ b/config/chips/L0xxx_Cat_1.chip @@ -3,7 +3,7 @@ dev_type STM32L0xxx_Cat_1 ref_manual_id 0451 // also RM0377 chip_id 0x457 // STLINK_CHIPID_STM32_L011 -flash_type 5 // STLINK_FLASH_TYPE_L0 +flash_type 8 // STM32_FLASH_TYPE_L0_L1 flash_size_reg 0x1ff8007c flash_pagesize 0x80 // 128 B sram_size 0x2000 // 8 KB diff --git a/config/chips/L0xxx_Cat_2.chip b/config/chips/L0xxx_Cat_2.chip index 58d6439ba..74a3d6157 100644 --- a/config/chips/L0xxx_Cat_2.chip +++ b/config/chips/L0xxx_Cat_2.chip @@ -3,7 +3,7 @@ dev_type STM32L0xxx_Cat_2 ref_manual_id 0451 // also RM0377 chip_id 0x425 // STLINK_CHIPID_STM32_L0_CAT2 -flash_type 5 // STLINK_FLASH_TYPE_L0 +flash_type 8 // STM32_FLASH_TYPE_L0_L1 flash_size_reg 0x1ff8007c flash_pagesize 0x80 // 128 B sram_size 0x2000 // 8 KB diff --git a/config/chips/L0xxx_Cat_3.chip b/config/chips/L0xxx_Cat_3.chip index 406c1a037..0cfcc53bb 100644 --- a/config/chips/L0xxx_Cat_3.chip +++ b/config/chips/L0xxx_Cat_3.chip @@ -3,7 +3,7 @@ dev_type STM32L0xxx_Cat_3 ref_manual_id 0451 // also RM0367 & RM0377 chip_id 0x417 // STLINK_CHIPID_STM32_L0 -flash_type 5 // STLINK_FLASH_TYPE_L0 +flash_type 8 // STM32_FLASH_TYPE_L0_L1 flash_size_reg 0x1ff8007c flash_pagesize 0x80 // 128 B sram_size 0x2000 // 8 KB diff --git a/config/chips/L0xxx_Cat_5.chip b/config/chips/L0xxx_Cat_5.chip index 1a0c387a7..cbb1e6632 100644 --- a/config/chips/L0xxx_Cat_5.chip +++ b/config/chips/L0xxx_Cat_5.chip @@ -3,7 +3,7 @@ dev_type STM32L0xxx_Cat_5 ref_manual_id 0451 // also RM0367 & RM0377 chip_id 0x447 // STLINK_CHIPID_STM32_L0_CAT5 -flash_type 5 // STLINK_FLASH_TYPE_L0 +flash_type 8 // STM32_FLASH_TYPE_L0_L1 flash_size_reg 0x1ff8007c flash_pagesize 0x80 // 128 B sram_size 0x5000 // 20 KB diff --git a/config/chips/L1xx_Cat_1.chip b/config/chips/L1xx_Cat_1.chip index 1d0b9282f..cecc32996 100644 --- a/config/chips/L1xx_Cat_1.chip +++ b/config/chips/L1xx_Cat_1.chip @@ -3,7 +3,7 @@ dev_type STM32L1xx_Cat_1 ref_manual_id 0038 chip_id 0x416 // STLINK_CHIPID_STM32_L1_MD -flash_type 5 // STLINK_FLASH_TYPE_L0 +flash_type 8 // STM32_FLASH_TYPE_L0_L1 flash_size_reg 0x1ff8004c flash_pagesize 0x100 // 128 B sram_size 0x4000 // 16 KB diff --git a/config/chips/L1xx_Cat_2.chip b/config/chips/L1xx_Cat_2.chip index f311e702c..1981d58a5 100644 --- a/config/chips/L1xx_Cat_2.chip +++ b/config/chips/L1xx_Cat_2.chip @@ -3,7 +3,7 @@ dev_type STM32L1xx_Cat_2 ref_manual_id 0038 chip_id 0x429 // STLINK_CHIPID_STM32_L1_CAT2 -flash_type 5 // STLINK_FLASH_TYPE_L0 +flash_type 8 // STM32_FLASH_TYPE_L0_L1 flash_size_reg 0x1ff8004c flash_pagesize 0x100 // 128 B sram_size 0x8000 // 32 KB diff --git a/config/chips/L1xx_Cat_3.chip b/config/chips/L1xx_Cat_3.chip index e6ecaf49e..1d551c8a4 100644 --- a/config/chips/L1xx_Cat_3.chip +++ b/config/chips/L1xx_Cat_3.chip @@ -3,7 +3,7 @@ dev_type STM32L1xx_Cat_3 ref_manual_id 0038 chip_id 0x427 // STLINK_CHIPID_STM32_L1_MD_PLUS -flash_type 5 // STLINK_FLASH_TYPE_L0 +flash_type 8 // STM32_FLASH_TYPE_L0_L1 flash_size_reg 0x1ff800cc flash_pagesize 0x100 // 128 B sram_size 0x8000 // 32 KB diff --git a/config/chips/L1xx_Cat_4.chip b/config/chips/L1xx_Cat_4.chip index 8ed0e004a..1e9cfe91c 100644 --- a/config/chips/L1xx_Cat_4.chip +++ b/config/chips/L1xx_Cat_4.chip @@ -3,7 +3,7 @@ dev_type STM32L1xx_Cat_4 ref_manual_id 0038 chip_id 0x436 // STLINK_CHIPID_STM32_L1_MD_PLUS_HD -flash_type 5 // STLINK_FLASH_TYPE_L0 +flash_type 8 // STM32_FLASH_TYPE_L0_L1 flash_size_reg 0x1ff800cc flash_pagesize 0x100 // 128 B sram_size 0xc000 // 48 KB diff --git a/config/chips/L1xx_Cat_5.chip b/config/chips/L1xx_Cat_5.chip index 75cebd94c..a51356d7a 100644 --- a/config/chips/L1xx_Cat_5.chip +++ b/config/chips/L1xx_Cat_5.chip @@ -3,7 +3,7 @@ dev_type STM32L1xx_Cat_5 ref_manual_id 0038 chip_id 0x437 // STLINK_CHIPID_STM32_L152_RE -flash_type 5 // STLINK_FLASH_TYPE_L0 +flash_type 8 // STM32_FLASH_TYPE_L0_L1 flash_size_reg 0x1ff800cc flash_pagesize 0x100 // 128 B sram_size 0x14000 // 80 KB diff --git a/config/chips/L41x_L42x.chip b/config/chips/L41x_L42x.chip index 97d0939ab..2de859b0c 100644 --- a/config/chips/L41x_L42x.chip +++ b/config/chips/L41x_L42x.chip @@ -3,7 +3,7 @@ dev_type STM32L41x_L42x ref_manual_id 0394 chip_id 0x464 // STLINK_CHIPID_STM32_L41x_L42x -flash_type 6 // STLINK_FLASH_TYPE_L4 +flash_type 9 // STM32_FLASH_TYPE_L4_L4P flash_size_reg 0x1fff75e0 flash_pagesize 0x800 // 2 KB sram_size 0xa000 // 40 KB diff --git a/config/chips/L43x_L44x.chip b/config/chips/L43x_L44x.chip index 369fdfa1e..2dad90844 100644 --- a/config/chips/L43x_L44x.chip +++ b/config/chips/L43x_L44x.chip @@ -3,7 +3,7 @@ dev_type STM32L41x_L42x ref_manual_id 0392 chip_id 0x435 // STLINK_CHIPID_STM32_L43x_L44x -flash_type 6 // STLINK_FLASH_TYPE_L4 +flash_type 9 // STM32_FLASH_TYPE_L4_L4P flash_size_reg 0x1fff75e0 flash_pagesize 0x800 // 2 KB sram_size 0xc000 // 48 KB diff --git a/config/chips/L45x_L46x.chip b/config/chips/L45x_L46x.chip index 2d1cda441..f856e1315 100644 --- a/config/chips/L45x_L46x.chip +++ b/config/chips/L45x_L46x.chip @@ -3,7 +3,7 @@ dev_type STM32L45x_L46x ref_manual_id 0394 chip_id 0x462 // STLINK_CHIPID_STM32_L45x_L46x -flash_type 6 // STLINK_FLASH_TYPE_L4 +flash_type 9 // STM32_FLASH_TYPE_L4_L4P flash_size_reg 0x1fff75e0 flash_pagesize 0x800 // 2 KB sram_size 0x20000 // 128 KB diff --git a/config/chips/L47x_L48x.chip b/config/chips/L47x_L48x.chip index 4af25cf5c..51257a37c 100644 --- a/config/chips/L47x_L48x.chip +++ b/config/chips/L47x_L48x.chip @@ -3,7 +3,7 @@ dev_type STM32L47x_L48x ref_manual_id 0351 chip_id 0x415 // STLINK_CHIPID_STM32_L4 -flash_type 6 // STLINK_FLASH_TYPE_L4 +flash_type 9 // STM32_FLASH_TYPE_L4_L4P flash_size_reg 0x1fff75e0 flash_pagesize 0x800 // 2 KB sram_size 0x18000 // 96 KB diff --git a/config/chips/L496x_L4A6x.chip b/config/chips/L496x_L4A6x.chip index 822914c96..32d75b571 100644 --- a/config/chips/L496x_L4A6x.chip +++ b/config/chips/L496x_L4A6x.chip @@ -3,7 +3,7 @@ dev_type STM32L496x_L4A6x ref_manual_id 0351 chip_id 0x461 // STLINK_CHIPID_STM32_L496x_L4A6x -flash_type 6 // STLINK_FLASH_TYPE_L4 +flash_type 9 // STM32_FLASH_TYPE_L4_L4P flash_size_reg 0x1fff75e0 flash_pagesize 0x800 // 2 KB sram_size 0x40000 // 256 KB diff --git a/config/chips/L4Px.chip b/config/chips/L4Px.chip index 8366621e2..ff3f05b81 100644 --- a/config/chips/L4Px.chip +++ b/config/chips/L4Px.chip @@ -3,7 +3,7 @@ dev_type STM32L4Px ref_manual_id 0432 chip_id 0x471 // STLINK_CHIPID_STM32_L4PX -flash_type 6 // STLINK_FLASH_TYPE_L4 +flash_type 9 // STM32_FLASH_TYPE_L4_L4P flash_size_reg 0x1fff75e0 flash_pagesize 0x1000 // 4 KB sram_size 0xa0000 // 640 KB diff --git a/config/chips/L4Rx.chip b/config/chips/L4Rx.chip index 734f39199..535e282c9 100644 --- a/config/chips/L4Rx.chip +++ b/config/chips/L4Rx.chip @@ -3,7 +3,7 @@ dev_type STM32L4Rx ref_manual_id 0432 chip_id 0x470 // STLINK_CHIPID_STM32_L4RX -flash_type 6 // STLINK_FLASH_TYPE_L4 +flash_type 9 // STM32_FLASH_TYPE_L4_L4P flash_size_reg 0x1fff75e0 flash_pagesize 0x1000 // 4 KB sram_size 0xa0000 // 640 KB diff --git a/config/chips/L5x5.chip b/config/chips/L5x5.chip index ce268148b..9a5b2fdbf 100644 --- a/config/chips/L5x5.chip +++ b/config/chips/L5x5.chip @@ -3,7 +3,7 @@ dev_type STM32L5x2 ref_manual_id 0438 chip_id 0x0 // (temporary setting only!) -flash_type 0 // (temporary setting only!) +flash_type 10 // (temporary setting only!) flash_size_reg 0x0bfa07a0 flash_pagesize 0x2000 // 8 KB sram_size 0x40000 // 256 KB diff --git a/config/chips/U5x5.chip b/config/chips/U5x5.chip index 177359cc3..55dfdaf7d 100644 --- a/config/chips/U5x5.chip +++ b/config/chips/U5x5.chip @@ -3,7 +3,7 @@ dev_type STM32U5x5 ref_manual_id 0456 chip_id 0x0 // (temporary setting only!) -flash_type 0 // (temporary setting only!) +flash_type 10 // (temporary setting only!) flash_size_reg 0x0bfa07a0 flash_pagesize 0x2000 // 8 KB sram_size 0xc4800 // 786 KB diff --git a/config/chips/WBx0_WBx5.chip b/config/chips/WBx0_WBx5.chip index ba5fee778..5fa76ec75 100644 --- a/config/chips/WBx0_WBx5.chip +++ b/config/chips/WBx0_WBx5.chip @@ -3,7 +3,7 @@ dev_type STM32WBx0_WBx5 ref_manual_id 0434 // also RM0471 chip_id 0x495 // STLINK_CHIPID_STM32_WB55 -flash_type 9 // STLINK_FLASH_TYPE_WB +flash_type 11 // STM32_FLASH_TYPE_WB_WL flash_size_reg 0x1fff75e0 flash_pagesize 0x1000 // 4 KB sram_size 0x40000 // 256 KB diff --git a/config/chips/WLx5.chip b/config/chips/WLx5.chip index 2dc9ce648..62ff4f72f 100644 --- a/config/chips/WLx5.chip +++ b/config/chips/WLx5.chip @@ -3,7 +3,7 @@ dev_type STM32WLEx ref_manual_id 0033 chip_id 0x497 // STLINK_CHIPID_STM32_WLE -flash_type 9 // STLINK_FLASH_TYPE_WB +flash_type 11 // STM32_FLASH_TYPE_WB_WL flash_size_reg 0x1fff75e0 flash_pagesize 0x800 // 2 KB sram_size 0x10000 // 64 KB diff --git a/config/chips/unknown_device.chip b/config/chips/unknown_device.chip index 1b74f22fa..512211092 100644 --- a/config/chips/unknown_device.chip +++ b/config/chips/unknown_device.chip @@ -3,7 +3,7 @@ dev_type unknown ref_manual_id 0000 chip_id 0x0 // STLINK_CHIPID_UNKNOWN -flash_type 0 // STLINK_FLASH_TYPE_UNKNOWN +flash_type 0 // STM32_FLASH_TYPE_UNKNOWN flash_size_reg 0x0 flash_pagesize 0x0 sram_size 0x0 diff --git a/inc/stlink.h b/inc/stlink.h index 0c1ca73a4..b387881ae 100644 --- a/inc/stlink.h +++ b/inc/stlink.h @@ -200,6 +200,7 @@ enum run_type { typedef struct _stlink stlink_t; +#include #include struct _stlink { @@ -222,8 +223,8 @@ struct _stlink { char serial[STLINK_SERIAL_BUFFER_SIZE]; int freq; // set by stlink_open_usb(), values: STLINK_SWDCLK_xxx_DIVISOR - enum stlink_flash_type flash_type; - // stlink_chipid_params.flash_type, set by stlink_load_device_params(), values: STLINK_FLASH_TYPE_xxx + enum stm32_flash_type flash_type; + // stlink_chipid_params.flash_type, set by stlink_load_device_params(), values: STM32_FLASH_TYPE_xx stm32_addr_t flash_base; // STM32_FLASH_BASE, set by stlink_load_device_params() size_t flash_size; // calculated by stlink_load_device_params() diff --git a/inc/stm32.h b/inc/stm32.h index 7a5e983a4..280a61107 100644 --- a/inc/stm32.h +++ b/inc/stm32.h @@ -13,6 +13,24 @@ #define STM32H7_CORE_ID 0x6ba02477 // STM32H7 SWD ID Code #define STM32H7_CORE_ID_JTAG 0x6ba00477 // STM32H7 JTAG ID Code (RM0433 p.3065) +/* STM32 flash types */ +// New flash type definitions must go before STM32_FLASH_TYPE_UNDEFINED +// with the latter updated to the highest enum value. +enum stm32_flash_type { + STM32_FLASH_TYPE_UNKNOWN = 0, + STM32_FLASH_TYPE_F0_F1_F3 = 1, + STM32_FLASH_TYPE_F1_XL = 2, + STM32_FLASH_TYPE_F2_F4 = 3, + STM32_FLASH_TYPE_F7 = 4, + STM32_FLASH_TYPE_G0 = 5, // 7 + STM32_FLASH_TYPE_G4 = 6, // 8 + STM32_FLASH_TYPE_H7 = 7, // 10 + STM32_FLASH_TYPE_L0_L1 = 8, // 5 + STM32_FLASH_TYPE_L4_L4P = 9, // 6 + STM32_FLASH_TYPE_L5_U5 = 10, // new + STM32_FLASH_TYPE_WB_WL = 11, // 9 + STM32_FLASH_TYPE_UNDEFINED = 12, // max. value exceeded +}; /* Constant STM32 memory address */ #define STM32_SRAM_BASE ((uint32_t)0x20000000) diff --git a/src/common.c b/src/common.c index 48ff6120b..e73955f31 100644 --- a/src/common.c +++ b/src/common.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #ifdef STLINK_HAVE_SYS_MMAN_H @@ -467,18 +468,18 @@ static uint32_t __attribute__((unused)) read_flash_rdp(stlink_t *sl) { static inline uint32_t read_flash_cr(stlink_t *sl, unsigned bank) { uint32_t reg, res; - if (sl->flash_type == STLINK_FLASH_TYPE_F4) { + if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { reg = FLASH_F4_CR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { + } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { reg = FLASH_F7_CR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { reg = STM32L4_FLASH_CR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4) { reg = STM32Gx_FLASH_CR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { reg = STM32WB_FLASH_CR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; } else { reg = (bank == BANK_1) ? FLASH_CR : FLASH_CR2; @@ -498,30 +499,30 @@ static inline unsigned int is_flash_locked(stlink_t *sl) { uint32_t cr_reg; uint32_t n; - if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || - (sl->flash_type == STLINK_FLASH_TYPE_F1_XL)) { + if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || + (sl->flash_type == STM32_FLASH_TYPE_F1_XL)) { cr_reg = FLASH_CR; cr_lock_shift = FLASH_CR_LOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { cr_reg = FLASH_F4_CR; cr_lock_shift = FLASH_F4_CR_LOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { + } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { cr_reg = FLASH_F7_CR; cr_lock_shift = FLASH_F7_CR_LOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { cr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF; cr_lock_shift = STM32L0_FLASH_PELOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { cr_reg = STM32L4_FLASH_CR; cr_lock_shift = STM32L4_FLASH_CR_LOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4) { cr_reg = STM32Gx_FLASH_CR; cr_lock_shift = STM32Gx_FLASH_CR_LOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { cr_reg = STM32WB_FLASH_CR; cr_lock_shift = STM32WB_FLASH_CR_LOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { cr_reg = FLASH_H7_CR1; cr_lock_shift = FLASH_H7_CR_LOCK; } else { @@ -542,27 +543,27 @@ static void unlock_flash(stlink_t *sl) { * definitive lock of the FPEC block until next reset. */ - if (sl->flash_type == STLINK_FLASH_TYPE_F0) { + if (sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) { key_reg = FLASH_KEYR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL) { + } else if (sl->flash_type == STM32_FLASH_TYPE_F1_XL) { key_reg = FLASH_KEYR; key2_reg = FLASH_KEYR2; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { key_reg = FLASH_F4_KEYR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { + } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { key_reg = FLASH_F7_KEYR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { key_reg = get_stm32l0_flash_base(sl) + FLASH_PEKEYR_OFF; flash_key1 = FLASH_L0_PEKEY1; flash_key2 = FLASH_L0_PEKEY2; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { key_reg = STM32L4_FLASH_KEYR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4) { key_reg = STM32Gx_FLASH_KEYR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { key_reg = STM32WB_FLASH_KEYR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { key_reg = FLASH_H7_KEYR1; if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { key2_reg = FLASH_H7_KEYR2; @@ -600,33 +601,33 @@ static void lock_flash(stlink_t *sl) { uint32_t cr_lock_shift, cr_reg, n, cr2_reg = 0; uint32_t cr_mask = 0xffffffffu; - if (sl->flash_type == STLINK_FLASH_TYPE_F0) { + if (sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) { cr_reg = FLASH_CR; cr_lock_shift = FLASH_CR_LOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL) { + } else if (sl->flash_type == STM32_FLASH_TYPE_F1_XL) { cr_reg = FLASH_CR; cr2_reg = FLASH_CR2; cr_lock_shift = FLASH_CR_LOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { cr_reg = FLASH_F4_CR; cr_lock_shift = FLASH_F4_CR_LOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { + } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { cr_reg = FLASH_F7_CR; cr_lock_shift = FLASH_F7_CR_LOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { cr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF; cr_lock_shift = STM32L0_FLASH_PELOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { cr_reg = STM32L4_FLASH_CR; cr_lock_shift = STM32L4_FLASH_CR_LOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4) { cr_reg = STM32Gx_FLASH_CR; cr_lock_shift = STM32Gx_FLASH_CR_LOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { cr_reg = STM32WB_FLASH_CR; cr_lock_shift = STM32WB_FLASH_CR_LOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { cr_reg = FLASH_H7_CR1; if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { cr2_reg = FLASH_H7_CR2; @@ -655,38 +656,38 @@ static bool is_flash_option_locked(stlink_t *sl) { uint32_t n; switch (sl->flash_type) { - case STLINK_FLASH_TYPE_F0: - case STLINK_FLASH_TYPE_F1_XL: + case STM32_FLASH_TYPE_F0_F1_F3: + case STM32_FLASH_TYPE_F1_XL: optcr_reg = FLASH_CR; optlock_shift = FLASH_CR_OPTWRE; active_bit_level = 0; /* bit is "option write enable", not lock */ break; - case STLINK_FLASH_TYPE_F4: + case STM32_FLASH_TYPE_F2_F4: optcr_reg = FLASH_F4_OPTCR; optlock_shift = FLASH_F4_OPTCR_LOCK; break; - case STLINK_FLASH_TYPE_F7: + case STM32_FLASH_TYPE_F7: optcr_reg = FLASH_F7_OPTCR; optlock_shift = FLASH_F7_OPTCR_LOCK; break; - case STLINK_FLASH_TYPE_L0: + case STM32_FLASH_TYPE_L0_L1: optcr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF; optlock_shift = STM32L0_FLASH_OPTLOCK; break; - case STLINK_FLASH_TYPE_L4: + case STM32_FLASH_TYPE_L4_L4P: optcr_reg = STM32L4_FLASH_CR; optlock_shift = STM32L4_FLASH_CR_OPTLOCK; break; - case STLINK_FLASH_TYPE_G0: - case STLINK_FLASH_TYPE_G4: + case STM32_FLASH_TYPE_G0: + case STM32_FLASH_TYPE_G4: optcr_reg = STM32Gx_FLASH_CR; optlock_shift = STM32Gx_FLASH_CR_OPTLOCK; break; - case STLINK_FLASH_TYPE_WB: + case STM32_FLASH_TYPE_WB_WL: optcr_reg = STM32WB_FLASH_CR; optlock_shift = STM32WB_FLASH_CR_OPTLOCK; break; - case STLINK_FLASH_TYPE_H7: + case STM32_FLASH_TYPE_H7: optcr_reg = FLASH_H7_OPTCR; optlock_shift = FLASH_H7_OPTCR_OPTLOCK; break; @@ -709,38 +710,38 @@ static int lock_flash_option(stlink_t *sl) { int active_bit_level = 1; switch (sl->flash_type) { - case STLINK_FLASH_TYPE_F0: - case STLINK_FLASH_TYPE_F1_XL: + case STM32_FLASH_TYPE_F0_F1_F3: + case STM32_FLASH_TYPE_F1_XL: optcr_reg = FLASH_CR; optlock_shift = FLASH_CR_OPTWRE; active_bit_level = 0; break; - case STLINK_FLASH_TYPE_F4: + case STM32_FLASH_TYPE_F2_F4: optcr_reg = FLASH_F4_OPTCR; optlock_shift = FLASH_F4_OPTCR_LOCK; break; - case STLINK_FLASH_TYPE_F7: + case STM32_FLASH_TYPE_F7: optcr_reg = FLASH_F7_OPTCR; optlock_shift = FLASH_F7_OPTCR_LOCK; break; - case STLINK_FLASH_TYPE_L0: + case STM32_FLASH_TYPE_L0_L1: optcr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF; optlock_shift = STM32L0_FLASH_OPTLOCK; break; - case STLINK_FLASH_TYPE_L4: + case STM32_FLASH_TYPE_L4_L4P: optcr_reg = STM32L4_FLASH_CR; optlock_shift = STM32L4_FLASH_CR_OPTLOCK; break; - case STLINK_FLASH_TYPE_G0: - case STLINK_FLASH_TYPE_G4: + case STM32_FLASH_TYPE_G0: + case STM32_FLASH_TYPE_G4: optcr_reg = STM32Gx_FLASH_CR; optlock_shift = STM32Gx_FLASH_CR_OPTLOCK; break; - case STLINK_FLASH_TYPE_WB: + case STM32_FLASH_TYPE_WB_WL: optcr_reg = STM32WB_FLASH_CR; optlock_shift = STM32WB_FLASH_CR_OPTLOCK; break; - case STLINK_FLASH_TYPE_H7: + case STM32_FLASH_TYPE_H7: optcr_reg = FLASH_H7_OPTCR; optlock_shift = FLASH_H7_OPTCR_OPTLOCK; if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) @@ -782,34 +783,34 @@ static int unlock_flash_option(stlink_t *sl) { uint32_t optkey2 = FLASH_OPTKEY2; switch (sl->flash_type) { - case STLINK_FLASH_TYPE_F0: - case STLINK_FLASH_TYPE_F1_XL: + case STM32_FLASH_TYPE_F0_F1_F3: + case STM32_FLASH_TYPE_F1_XL: optkey_reg = FLASH_OPTKEYR; optkey1 = FLASH_F0_OPTKEY1; optkey2 = FLASH_F0_OPTKEY2; break; - case STLINK_FLASH_TYPE_F4: + case STM32_FLASH_TYPE_F2_F4: optkey_reg = FLASH_F4_OPT_KEYR; break; - case STLINK_FLASH_TYPE_F7: + case STM32_FLASH_TYPE_F7: optkey_reg = FLASH_F7_OPT_KEYR; break; - case STLINK_FLASH_TYPE_L0: + case STM32_FLASH_TYPE_L0_L1: optkey_reg = get_stm32l0_flash_base(sl) + FLASH_OPTKEYR_OFF; optkey1 = FLASH_L0_OPTKEY1; optkey2 = FLASH_L0_OPTKEY2; break; - case STLINK_FLASH_TYPE_L4: + case STM32_FLASH_TYPE_L4_L4P: optkey_reg = STM32L4_FLASH_OPTKEYR; break; - case STLINK_FLASH_TYPE_G0: - case STLINK_FLASH_TYPE_G4: + case STM32_FLASH_TYPE_G0: + case STM32_FLASH_TYPE_G4: optkey_reg = STM32Gx_FLASH_OPTKEYR; break; - case STLINK_FLASH_TYPE_WB: + case STM32_FLASH_TYPE_WB_WL: optkey_reg = STM32WB_FLASH_OPT_KEYR; break; - case STLINK_FLASH_TYPE_H7: + case STM32_FLASH_TYPE_H7: optkey_reg = FLASH_H7_OPT_KEYR; if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) optkey2_reg = FLASH_H7_OPT_KEYR2; @@ -852,24 +853,24 @@ static void set_flash_cr_pg(stlink_t *sl, unsigned bank) { x = read_flash_cr(sl, bank); - if (sl->flash_type == STLINK_FLASH_TYPE_F4) { + if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { cr_reg = FLASH_F4_CR; x |= 1 << FLASH_CR_PG; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { + } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { cr_reg = FLASH_F7_CR; x |= 1 << FLASH_CR_PG; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { cr_reg = STM32L4_FLASH_CR; x &= ~STM32L4_FLASH_CR_OPBITS; x |= (1 << STM32L4_FLASH_CR_PG); - } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4) { cr_reg = STM32Gx_FLASH_CR; x |= (1 << FLASH_CR_PG); - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { cr_reg = STM32WB_FLASH_CR; x |= (1 << FLASH_CR_PG); - } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { cr_reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; x |= (1 << FLASH_H7_CR_PG); } else { @@ -884,18 +885,18 @@ static void clear_flash_cr_pg(stlink_t *sl, unsigned bank) { uint32_t cr_reg, n; uint32_t bit = FLASH_CR_PG; - if (sl->flash_type == STLINK_FLASH_TYPE_F4) { + if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { cr_reg = FLASH_F4_CR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { + } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { cr_reg = FLASH_F7_CR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { cr_reg = STM32L4_FLASH_CR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4) { cr_reg = STM32Gx_FLASH_CR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { cr_reg = STM32WB_FLASH_CR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { cr_reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; bit = FLASH_H7_CR_PG; } else { @@ -909,10 +910,10 @@ static void clear_flash_cr_pg(stlink_t *sl, unsigned bank) { static void set_flash_cr_per(stlink_t *sl, unsigned bank) { uint32_t cr_reg, val; - if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { + if (sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4) { cr_reg = STM32Gx_FLASH_CR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { cr_reg = STM32WB_FLASH_CR; } else { cr_reg = (bank == BANK_1) ? FLASH_CR : FLASH_CR2; @@ -926,10 +927,10 @@ static void set_flash_cr_per(stlink_t *sl, unsigned bank) { static void clear_flash_cr_per(stlink_t *sl, unsigned bank) { uint32_t cr_reg; - if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { + if (sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4) { cr_reg = STM32Gx_FLASH_CR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { cr_reg = STM32WB_FLASH_CR; } else { cr_reg = (bank == BANK_1) ? FLASH_CR : FLASH_CR2; @@ -942,20 +943,20 @@ static void clear_flash_cr_per(stlink_t *sl, unsigned bank) { static void set_flash_cr_mer(stlink_t *sl, bool v, unsigned bank) { uint32_t val, cr_reg, cr_mer, cr_pg; - if (sl->flash_type == STLINK_FLASH_TYPE_F4) { + if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { cr_reg = FLASH_F4_CR; cr_mer = 1 << FLASH_CR_MER; cr_pg = 1 << FLASH_CR_PG; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { + } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { cr_reg = FLASH_F7_CR; cr_mer = 1 << FLASH_CR_MER; cr_pg = 1 << FLASH_CR_PG; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { cr_reg = STM32L4_FLASH_CR; cr_mer = (1 << STM32L4_FLASH_CR_MER1) | (1 << STM32L4_FLASH_CR_MER2); cr_pg = (1 << STM32L4_FLASH_CR_PG); - } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4) { cr_reg = STM32Gx_FLASH_CR; cr_mer = (1 << STM32Gx_FLASH_CR_MER1); @@ -964,11 +965,11 @@ static void set_flash_cr_mer(stlink_t *sl, bool v, unsigned bank) { } cr_pg = (1 << FLASH_CR_PG); - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { cr_reg = STM32WB_FLASH_CR; cr_mer = (1 << FLASH_CR_MER); cr_pg = (1 << FLASH_CR_PG); - } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { cr_reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; cr_mer = (1 << FLASH_H7_CR_BER); cr_pg = (1 << FLASH_H7_CR_PG); @@ -998,23 +999,23 @@ static void set_flash_cr_mer(stlink_t *sl, bool v, unsigned bank) { static void set_flash_cr_strt(stlink_t *sl, unsigned bank) { uint32_t val, cr_reg, cr_strt; - if (sl->flash_type == STLINK_FLASH_TYPE_F4) { + if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { cr_reg = FLASH_F4_CR; cr_strt = 1 << FLASH_F4_CR_STRT; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { + } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { cr_reg = FLASH_F7_CR; cr_strt = 1 << FLASH_F7_CR_STRT; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { cr_reg = STM32L4_FLASH_CR; cr_strt = (1 << STM32L4_FLASH_CR_STRT); - } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4) { cr_reg = STM32Gx_FLASH_CR; cr_strt = (1 << STM32Gx_FLASH_CR_STRT); - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { cr_reg = STM32WB_FLASH_CR; cr_strt = (1 << STM32WB_FLASH_CR_STRT); - } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { cr_reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; cr_strt = 1 << FLASH_H7_CR_START(sl->chip_id); } else { @@ -1030,23 +1031,23 @@ static void set_flash_cr_strt(stlink_t *sl, unsigned bank) { static inline uint32_t read_flash_sr(stlink_t *sl, unsigned bank) { uint32_t res, sr_reg; - if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || - (sl->flash_type == STLINK_FLASH_TYPE_F1_XL)) { + if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || + (sl->flash_type == STM32_FLASH_TYPE_F1_XL)) { sr_reg = (bank == BANK_1) ? FLASH_SR : FLASH_SR2; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { sr_reg = get_stm32l0_flash_base(sl) + FLASH_SR_OFF; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { sr_reg = FLASH_F4_SR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { + } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { sr_reg = FLASH_F7_SR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { sr_reg = STM32L4_FLASH_SR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4) { sr_reg = STM32Gx_FLASH_SR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { sr_reg = STM32WB_FLASH_SR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { sr_reg = (bank == BANK_1) ? FLASH_H7_SR1 : FLASH_H7_SR2; } else { ELOG("method 'read_flash_sr' is unsupported\n"); @@ -1060,23 +1061,23 @@ static inline uint32_t read_flash_sr(stlink_t *sl, unsigned bank) { static inline int write_flash_sr(stlink_t *sl, unsigned bank, uint32_t val) { uint32_t sr_reg; - if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || - (sl->flash_type == STLINK_FLASH_TYPE_F1_XL)) { + if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || + (sl->flash_type == STM32_FLASH_TYPE_F1_XL)) { sr_reg = (bank == BANK_1) ? FLASH_SR : FLASH_SR2; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { sr_reg = get_stm32l0_flash_base(sl) + FLASH_SR_OFF; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { sr_reg = FLASH_F4_SR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { + } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { sr_reg = FLASH_F7_SR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { sr_reg = STM32L4_FLASH_SR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4) { sr_reg = STM32Gx_FLASH_SR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { sr_reg = STM32WB_FLASH_SR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { sr_reg = (bank == BANK_1) ? FLASH_H7_SR1 : FLASH_H7_SR2; } else { ELOG("method 'write_flash_sr' is unsupported\n"); @@ -1090,22 +1091,22 @@ static inline unsigned int is_flash_busy(stlink_t *sl) { uint32_t sr_busy_shift; unsigned int res; - if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || - (sl->flash_type == STLINK_FLASH_TYPE_F1_XL) || - (sl->flash_type == STLINK_FLASH_TYPE_L0)) { + if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || + (sl->flash_type == STM32_FLASH_TYPE_F1_XL) || + (sl->flash_type == STM32_FLASH_TYPE_L0_L1)) { sr_busy_shift = FLASH_SR_BSY; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { sr_busy_shift = FLASH_F4_SR_BSY; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { + } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { sr_busy_shift = FLASH_F7_SR_BSY; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { sr_busy_shift = STM32L4_FLASH_SR_BSY; - } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4) { sr_busy_shift = STM32Gx_FLASH_SR_BSY; - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { sr_busy_shift = STM32WB_FLASH_SR_BSY; - } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { sr_busy_shift = FLASH_H7_SR_QW; } else { ELOG("method 'is_flash_busy' is unsupported\n"); @@ -1114,8 +1115,8 @@ static inline unsigned int is_flash_busy(stlink_t *sl) { res = read_flash_sr(sl, BANK_1) & (1 << sr_busy_shift); - if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL || - (sl->flash_type == STLINK_FLASH_TYPE_H7 && + if (sl->flash_type == STM32_FLASH_TYPE_F1_XL || + (sl->flash_type == STM32_FLASH_TYPE_H7 && sl->chip_flags & CHIP_F_HAS_DUAL_BANK)) { res |= read_flash_sr(sl, BANK_2) & (1 << sr_busy_shift); } @@ -1149,32 +1150,32 @@ static void wait_flash_busy_progress(stlink_t *sl) { static void clear_flash_error(stlink_t *sl) { switch (sl->flash_type) { - case STLINK_FLASH_TYPE_F0: + case STM32_FLASH_TYPE_F0_F1_F3: write_flash_sr(sl, BANK_1, FLASH_SR_ERROR_MASK); break; - case STLINK_FLASH_TYPE_F4: + case STM32_FLASH_TYPE_F2_F4: write_flash_sr(sl, BANK_1, FLASH_F4_SR_ERROR_MASK); break; - case STLINK_FLASH_TYPE_F7: + case STM32_FLASH_TYPE_F7: write_flash_sr(sl, BANK_1, FLASH_F7_SR_ERROR_MASK); break; - case STLINK_FLASH_TYPE_G0: - case STLINK_FLASH_TYPE_G4: + case STM32_FLASH_TYPE_G0: + case STM32_FLASH_TYPE_G4: write_flash_sr(sl, BANK_1, STM32Gx_FLASH_SR_ERROR_MASK); break; - case STLINK_FLASH_TYPE_L0: + case STM32_FLASH_TYPE_L0_L1: write_flash_sr(sl, BANK_1, STM32L0_FLASH_SR_ERROR_MASK); break; - case STLINK_FLASH_TYPE_L4: + case STM32_FLASH_TYPE_L4_L4P: write_flash_sr(sl, BANK_1, STM32L4_FLASH_SR_ERROR_MASK); break; - case STLINK_FLASH_TYPE_H7: + case STM32_FLASH_TYPE_H7: write_flash_sr(sl, BANK_1, FLASH_H7_SR_ERROR_MASK); if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { write_flash_sr(sl, BANK_2, FLASH_H7_SR_ERROR_MASK); } break; - case STLINK_FLASH_TYPE_WB: + case STM32_FLASH_TYPE_WB_WL: write_flash_sr(sl, BANK_1, STM32WB_FLASH_SR_ERROR_MASK); break; default: @@ -1189,52 +1190,52 @@ static int check_flash_error(stlink_t *sl) { WRPERR = PROGERR = PGAERR = 0; switch (sl->flash_type) { - case STLINK_FLASH_TYPE_F0: - case STLINK_FLASH_TYPE_F1_XL: + case STM32_FLASH_TYPE_F0_F1_F3: + case STM32_FLASH_TYPE_F1_XL: res = read_flash_sr(sl, BANK_1) & FLASH_SR_ERROR_MASK; - if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL) { + if (sl->flash_type == STM32_FLASH_TYPE_F1_XL) { res |= read_flash_sr(sl, BANK_2) & FLASH_SR_ERROR_MASK; } WRPERR = (1 << FLASH_SR_WRPRT_ERR); PROGERR = (1 << FLASH_SR_PG_ERR); break; - case STLINK_FLASH_TYPE_F4: + case STM32_FLASH_TYPE_F2_F4: res = read_flash_sr(sl, BANK_1) & FLASH_F4_SR_ERROR_MASK; WRPERR = (1 << FLASH_F4_SR_WRPERR); PGAERR = (1 << FLASH_F4_SR_PGAERR); break; - case STLINK_FLASH_TYPE_F7: + case STM32_FLASH_TYPE_F7: res = read_flash_sr(sl, BANK_1) & FLASH_F7_SR_ERROR_MASK; WRPERR = (1 << FLASH_F7_SR_WRP_ERR); PROGERR = (1 << FLASH_F7_SR_PGP_ERR); break; - case STLINK_FLASH_TYPE_G0: - case STLINK_FLASH_TYPE_G4: + case STM32_FLASH_TYPE_G0: + case STM32_FLASH_TYPE_G4: res = read_flash_sr(sl, BANK_1) & STM32Gx_FLASH_SR_ERROR_MASK; WRPERR = (1 << STM32Gx_FLASH_SR_WRPERR); PROGERR = (1 << STM32Gx_FLASH_SR_PROGERR); PGAERR = (1 << STM32Gx_FLASH_SR_PGAERR); break; - case STLINK_FLASH_TYPE_L0: + case STM32_FLASH_TYPE_L0_L1: res = read_flash_sr(sl, BANK_1) & STM32L0_FLASH_SR_ERROR_MASK; WRPERR = (1 << STM32L0_FLASH_SR_WRPERR); PROGERR = (1 << STM32L0_FLASH_SR_NOTZEROERR); PGAERR = (1 << STM32L0_FLASH_SR_PGAERR); break; - case STLINK_FLASH_TYPE_L4: + case STM32_FLASH_TYPE_L4_L4P: res = read_flash_sr(sl, BANK_1) & STM32L4_FLASH_SR_ERROR_MASK; WRPERR = (1 << STM32L4_FLASH_SR_WRPERR); PROGERR = (1 << STM32L4_FLASH_SR_PROGERR); PGAERR = (1 << STM32L4_FLASH_SR_PGAERR); break; - case STLINK_FLASH_TYPE_H7: + case STM32_FLASH_TYPE_H7: res = read_flash_sr(sl, BANK_1) & FLASH_H7_SR_ERROR_MASK; if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { res |= read_flash_sr(sl, BANK_2) & FLASH_H7_SR_ERROR_MASK; } WRPERR = (1 << FLASH_H7_SR_WRPERR); break; - case STLINK_FLASH_TYPE_WB: + case STM32_FLASH_TYPE_WB_WL: res = read_flash_sr(sl, BANK_1) & STM32WB_FLASH_SR_ERROR_MASK; WRPERR = (1 << STM32WB_FLASH_SR_WRPERR); PROGERR = (1 << STM32WB_FLASH_SR_PROGERR); @@ -1271,31 +1272,31 @@ static void stop_wdg_in_debug(stlink_t *sl) { uint32_t value; switch (sl->flash_type) { - case STLINK_FLASH_TYPE_F0: - case STLINK_FLASH_TYPE_F1_XL: - case STLINK_FLASH_TYPE_G4: + case STM32_FLASH_TYPE_F0_F1_F3: + case STM32_FLASH_TYPE_F1_XL: + case STM32_FLASH_TYPE_G4: dbgmcu_cr = STM32F0_DBGMCU_CR; set = (1 << STM32F0_DBGMCU_CR_IWDG_STOP) | (1 << STM32F0_DBGMCU_CR_WWDG_STOP); break; - case STLINK_FLASH_TYPE_F4: - case STLINK_FLASH_TYPE_F7: - case STLINK_FLASH_TYPE_L4: + case STM32_FLASH_TYPE_F2_F4: + case STM32_FLASH_TYPE_F7: + case STM32_FLASH_TYPE_L4_L4P: dbgmcu_cr = STM32F4_DBGMCU_APB1FZR1; set = (1 << STM32F4_DBGMCU_APB1FZR1_IWDG_STOP) | (1 << STM32F4_DBGMCU_APB1FZR1_WWDG_STOP); break; - case STLINK_FLASH_TYPE_L0: - case STLINK_FLASH_TYPE_G0: + case STM32_FLASH_TYPE_L0_L1: + case STM32_FLASH_TYPE_G0: dbgmcu_cr = STM32L0_DBGMCU_APB1_FZ; set = (1 << STM32L0_DBGMCU_APB1_FZ_IWDG_STOP) | (1 << STM32L0_DBGMCU_APB1_FZ_WWDG_STOP); break; - case STLINK_FLASH_TYPE_H7: + case STM32_FLASH_TYPE_H7: dbgmcu_cr = STM32H7_DBGMCU_APB1HFZ; set = (1 << STM32H7_DBGMCU_APB1HFZ_IWDG_STOP); break; - case STLINK_FLASH_TYPE_WB: + case STM32_FLASH_TYPE_WB_WL: dbgmcu_cr = STM32WB_DBGMCU_APB1FZR1; set = (1 << STM32WB_DBGMCU_APB1FZR1_IWDG_STOP) | (1 << STM32WB_DBGMCU_APB1FZR1_WWDG_STOP); @@ -1315,34 +1316,34 @@ static void set_dma_state(stlink_t *sl, flash_loader_t *fl, int bckpRstr) { rcc = rcc_dma_mask = value = 0; switch (sl->flash_type) { - case STLINK_FLASH_TYPE_F0: - case STLINK_FLASH_TYPE_F1_XL: + case STM32_FLASH_TYPE_F0_F1_F3: + case STM32_FLASH_TYPE_F1_XL: rcc = STM32F1_RCC_AHBENR; rcc_dma_mask = STM32F1_RCC_DMAEN; break; - case STLINK_FLASH_TYPE_F4: - case STLINK_FLASH_TYPE_F7: + case STM32_FLASH_TYPE_F2_F4: + case STM32_FLASH_TYPE_F7: rcc = STM32F4_RCC_AHB1ENR; rcc_dma_mask = STM32F4_RCC_DMAEN; break; - case STLINK_FLASH_TYPE_G0: + case STM32_FLASH_TYPE_G0: rcc = STM32G0_RCC_AHBENR; rcc_dma_mask = STM32G0_RCC_DMAEN; break; - case STLINK_FLASH_TYPE_G4: - case STLINK_FLASH_TYPE_L4: + case STM32_FLASH_TYPE_G4: + case STM32_FLASH_TYPE_L4_L4P: rcc = STM32G4_RCC_AHB1ENR; rcc_dma_mask = STM32G4_RCC_DMAEN; break; - case STLINK_FLASH_TYPE_L0: + case STM32_FLASH_TYPE_L0_L1: rcc = STM32L0_RCC_AHBENR; rcc_dma_mask = STM32L0_RCC_DMAEN; break; - case STLINK_FLASH_TYPE_H7: + case STM32_FLASH_TYPE_H7: rcc = STM32H7_RCC_AHB1ENR; rcc_dma_mask = STM32H7_RCC_DMAEN; break; - case STLINK_FLASH_TYPE_WB: + case STM32_FLASH_TYPE_WB_WL: rcc = STM32WB_RCC_AHB1ENR; rcc_dma_mask = STM32WB_RCC_DMAEN; break; @@ -1370,7 +1371,7 @@ static inline void write_flash_cr_psiz(stlink_t *sl, uint32_t n, uint32_t cr_reg, psize_shift; uint32_t x = read_flash_cr(sl, bank); - if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + if (sl->flash_type == STM32_FLASH_TYPE_H7) { cr_reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; psize_shift = FLASH_H7_CR_PSIZE; } else { @@ -1390,7 +1391,7 @@ static inline void write_flash_cr_snb(stlink_t *sl, uint32_t n, unsigned bank) { uint32_t cr_reg, snb_mask, snb_shift, ser_shift; uint32_t x = read_flash_cr(sl, bank); - if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + if (sl->flash_type == STM32_FLASH_TYPE_H7) { cr_reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; snb_mask = FLASH_H7_CR_SNB_MASK; snb_shift = FLASH_H7_CR_SNB; @@ -1443,7 +1444,7 @@ void stlink_close(stlink_t *sl) { int stlink_exit_debug_mode(stlink_t *sl) { DLOG("*** stlink_exit_debug_mode ***\n"); - if (sl->flash_type != STLINK_FLASH_TYPE_UNKNOWN && + if (sl->flash_type != STM32_FLASH_TYPE_UNKNOWN && sl->core_stat != TARGET_RESET) { // stop debugging if the target has been identified stlink_write_debug32(sl, STLINK_REG_DHCSR, STLINK_REG_DHCSR_DBGKEY); @@ -1604,7 +1605,7 @@ int stlink_load_device_params(stlink_t *sl) { return (-1); } - if (params->flash_type == STLINK_FLASH_TYPE_UNKNOWN) { + if (params->flash_type == STM32_FLASH_TYPE_UNKNOWN) { WLOG("Invalid flash type, please check device declaration\n"); sl->flash_size = 0; return (0); @@ -1666,7 +1667,7 @@ int stlink_load_device_params(stlink_t *sl) { // H7 devices with small flash has one bank if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK && - sl->flash_type == STLINK_FLASH_TYPE_H7) { + sl->flash_type == STM32_FLASH_TYPE_H7) { if ((sl->flash_size / sl->flash_pgsz) <= 1) sl->chip_flags &= ~CHIP_F_HAS_DUAL_BANK; } @@ -2777,9 +2778,9 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { // clear flash IO errors clear_flash_error(sl); - if (sl->flash_type == STLINK_FLASH_TYPE_F4 || - sl->flash_type == STLINK_FLASH_TYPE_F7 || - sl->flash_type == STLINK_FLASH_TYPE_L4) { + if (sl->flash_type == STM32_FLASH_TYPE_F2_F4 || + sl->flash_type == STM32_FLASH_TYPE_F7 || + sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { // unlock if locked unlock_flash_if(sl); @@ -2826,7 +2827,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { #if DEBUG_FLASH fprintf(stdout, "Erase Final CR:0x%x\n", read_flash_cr(sl, BANK_1)); #endif - } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { uint32_t val; uint32_t flash_regs_base = get_stm32l0_flash_base(sl); @@ -2882,15 +2883,15 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); val |= (1 << 0) | (1 << 1) | (1 << 2); stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB || - sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL || + sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4) { uint32_t val; unlock_flash_if(sl); set_flash_cr_per(sl, BANK_1); // set the 'enable Flash erase' bit // set the page to erase - if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { uint32_t flash_page = ((flashaddr - STM32_FLASH_BASE) / (uint32_t)(sl->flash_pgsz)); stlink_read_debug32(sl, STM32WB_FLASH_CR, &val); @@ -2900,7 +2901,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { val |= ((flash_page & 0xFF) << 3); stlink_write_debug32(sl, STM32WB_FLASH_CR, val); - } else if (sl->flash_type == STLINK_FLASH_TYPE_G0) { + } else if (sl->flash_type == STM32_FLASH_TYPE_G0) { uint32_t flash_page = ((flashaddr - STM32_FLASH_BASE) / (uint32_t)(sl->flash_pgsz)); stlink_read_debug32(sl, STM32Gx_FLASH_CR, &val); @@ -2908,7 +2909,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { val &= ~(0x3F << 3); val |= ((flash_page & 0x3F) << 3) | (1 << FLASH_CR_PER); stlink_write_debug32(sl, STM32Gx_FLASH_CR, val); - } else if (sl->flash_type == STLINK_FLASH_TYPE_G4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_G4) { uint32_t flash_page = ((flashaddr - STM32_FLASH_BASE) / (uint32_t)(sl->flash_pgsz)); stlink_read_debug32(sl, STM32Gx_FLASH_CR, &val); @@ -2922,8 +2923,8 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { wait_flash_busy(sl); // wait for the 'busy' bit to clear clear_flash_cr_per(sl, BANK_1); // clear the 'enable page erase' bit lock_flash(sl); - } else if (sl->flash_type == STLINK_FLASH_TYPE_F0 || - sl->flash_type == STLINK_FLASH_TYPE_F1_XL) { + } else if (sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3 || + sl->flash_type == STM32_FLASH_TYPE_F1_XL) { unsigned bank = (flashaddr < STM32_F1_FLASH_BANK2_BASE) ? BANK_1 : BANK_2; unlock_flash_if(sl); clear_flash_cr_pg(sl, bank); // clear the pg bit @@ -2934,7 +2935,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { wait_flash_busy(sl); clear_flash_cr_per(sl, bank); // clear the page erase bit lock_flash(sl); - } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { unsigned bank = (flashaddr < STM32_H7_FLASH_BANK2_BASE) ? BANK_1 : BANK_2; unlock_flash_if(sl); // unlock if locked uint32_t sector = calculate_H7_sectornum( @@ -2955,8 +2956,8 @@ int stlink_erase_flash_mass(stlink_t *sl) { int err = 0; // TODO: User MER bit to mass-erase WB series. - if (sl->flash_type == STLINK_FLASH_TYPE_L0 || - sl->flash_type == STLINK_FLASH_TYPE_WB) { + if (sl->flash_type == STM32_FLASH_TYPE_L0_L1 || + sl->flash_type == STM32_FLASH_TYPE_WB_WL) { // erase each page int i = 0, num_pages = (int)(sl->flash_size / sl->flash_pgsz); @@ -2980,7 +2981,7 @@ int stlink_erase_flash_mass(stlink_t *sl) { clear_flash_error(sl); unlock_flash_if(sl); - if (sl->flash_type == STLINK_FLASH_TYPE_H7 && + if (sl->flash_type == STM32_FLASH_TYPE_H7 && sl->chip_id != STLINK_CHIPID_STM32_H7Ax) { // set parallelism write_flash_cr_psiz(sl, 3 /*64it*/, BANK_1); @@ -2993,8 +2994,8 @@ int stlink_erase_flash_mass(stlink_t *sl) { set_flash_cr_strt( sl, BANK_1); // start erase operation, reset by hw with busy bit - if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL || - (sl->flash_type == STLINK_FLASH_TYPE_H7 && + if (sl->flash_type == STM32_FLASH_TYPE_F1_XL || + (sl->flash_type == STM32_FLASH_TYPE_H7 && sl->chip_flags & CHIP_F_HAS_DUAL_BANK)) { set_flash_cr_mer(sl, 1, BANK_2); // set the mass erase bit in bank 2 set_flash_cr_strt(sl, BANK_2); // start erase operation in bank 2 @@ -3005,8 +3006,8 @@ int stlink_erase_flash_mass(stlink_t *sl) { // reset the mass erase bit set_flash_cr_mer(sl, 0, BANK_1); - if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL || - (sl->flash_type == STLINK_FLASH_TYPE_H7 && + if (sl->flash_type == STM32_FLASH_TYPE_F1_XL || + (sl->flash_type == STM32_FLASH_TYPE_H7 && sl->chip_flags & CHIP_F_HAS_DUAL_BANK)) { set_flash_cr_mer(sl, 0, BANK_2); } @@ -3143,9 +3144,9 @@ int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { // Clear errors clear_flash_error(sl); - if ((sl->flash_type == STLINK_FLASH_TYPE_F4) || - (sl->flash_type == STLINK_FLASH_TYPE_F7) || - (sl->flash_type == STLINK_FLASH_TYPE_L4)) { + if ((sl->flash_type == STM32_FLASH_TYPE_F2_F4) || + (sl->flash_type == STM32_FLASH_TYPE_F7) || + (sl->flash_type == STM32_FLASH_TYPE_L4_L4P)) { ILOG("Starting Flash write for F2/F4/F7/L4\n"); // Flash loader initialisation @@ -3169,7 +3170,7 @@ int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { return (-1); } - if (sl->flash_type == STLINK_FLASH_TYPE_L4) { + if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { // L4 does not have a byte-write mode if (voltage < 1710) { ELOG("Target voltage (%d mV) too low for flash writes!\n", voltage); @@ -3189,14 +3190,14 @@ int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { // set programming mode set_flash_cr_pg(sl, BANK_1); - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB || - sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL || + sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4) { ILOG("Starting Flash write for WB/G0/G4\n"); unlock_flash_if(sl); // unlock flash if necessary set_flash_cr_pg(sl, BANK_1); // set PG 'allow programming' bit - } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { ILOG("Starting Flash write for L0\n"); uint32_t val; @@ -3233,8 +3234,8 @@ int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { // L0/L1 have fallback to soft write WLOG("stlink_flash_loader_init() == -1\n"); } - } else if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || - (sl->flash_type == STLINK_FLASH_TYPE_F1_XL)) { + } else if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || + (sl->flash_type == STM32_FLASH_TYPE_F1_XL)) { ILOG("Starting Flash write for VL/F0/F3/F1_XL\n"); // flash loader initialisation @@ -3248,10 +3249,10 @@ int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { // set programming mode set_flash_cr_pg(sl, BANK_1); - if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL) { + if (sl->flash_type == STM32_FLASH_TYPE_F1_XL) { set_flash_cr_pg(sl, BANK_2); } - } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { ILOG("Starting Flash write for H7\n"); unlock_flash_if(sl); // unlock the cr @@ -3277,9 +3278,9 @@ int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t addr, uint8_t *base, uint32_t len) { size_t off; - if ((sl->flash_type == STLINK_FLASH_TYPE_F4) || - (sl->flash_type == STLINK_FLASH_TYPE_F7) || - (sl->flash_type == STLINK_FLASH_TYPE_L4)) { + if ((sl->flash_type == STM32_FLASH_TYPE_F2_F4) || + (sl->flash_type == STM32_FLASH_TYPE_F7) || + (sl->flash_type == STM32_FLASH_TYPE_L4_L4P)) { size_t buf_size = (sl->sram_size > 0x8000) ? 0x8000 : 0x4000; for (off = 0; off < len;) { size_t size = len - off > buf_size ? buf_size : len - off; @@ -3293,9 +3294,9 @@ int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, off += size; } - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB || - sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL || + sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4) { DLOG("Starting %3u page write\r\n", (unsigned int)(len / sl->flash_pgsz)); for (off = 0; off < len; off += sizeof(uint32_t)) { uint32_t data; @@ -3319,7 +3320,7 @@ int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, 0); // write a single word of zeros wait_flash_busy(sl); // wait for 'busy' bit in FLASH_SR to clear } - } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { uint32_t val; uint32_t flash_regs_base = get_stm32l0_flash_base(sl); uint32_t pagesize = (flash_regs_base==STM32L0_FLASH_REGS_ADDR)? @@ -3359,8 +3360,8 @@ int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, // TODO: check redo write operation } fprintf(stdout, "\n"); - } else if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || - (sl->flash_type == STLINK_FLASH_TYPE_F1_XL)) { + } else if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || + (sl->flash_type == STM32_FLASH_TYPE_F1_XL)) { int write_block_count = 0; for (off = 0; off < len; off += sl->flash_pgsz) { // adjust last write size @@ -3392,7 +3393,7 @@ int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, if (sl->verbose >= 1) { fprintf(stdout, "\n"); } - } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { for (off = 0; off < len;) { // Program STM32H7x with 64-byte Flash words size_t chunk = (len - off > 64) ? 64 : len - off; @@ -3422,24 +3423,24 @@ int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, int stlink_flashloader_stop(stlink_t *sl, flash_loader_t *fl) { uint32_t dhcsr; - if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || - (sl->flash_type == STLINK_FLASH_TYPE_F1_XL) || - (sl->flash_type == STLINK_FLASH_TYPE_F4) || - (sl->flash_type == STLINK_FLASH_TYPE_F7) || - (sl->flash_type == STLINK_FLASH_TYPE_L4) || - (sl->flash_type == STLINK_FLASH_TYPE_WB) || - (sl->flash_type == STLINK_FLASH_TYPE_G0) || - (sl->flash_type == STLINK_FLASH_TYPE_G4) || - (sl->flash_type == STLINK_FLASH_TYPE_H7)) { + if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || + (sl->flash_type == STM32_FLASH_TYPE_F1_XL) || + (sl->flash_type == STM32_FLASH_TYPE_F2_F4) || + (sl->flash_type == STM32_FLASH_TYPE_F7) || + (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) || + (sl->flash_type == STM32_FLASH_TYPE_WB_WL) || + (sl->flash_type == STM32_FLASH_TYPE_G0) || + (sl->flash_type == STM32_FLASH_TYPE_G4) || + (sl->flash_type == STM32_FLASH_TYPE_H7)) { clear_flash_cr_pg(sl, BANK_1); - if ((sl->flash_type == STLINK_FLASH_TYPE_H7 && + if ((sl->flash_type == STM32_FLASH_TYPE_H7 && sl->chip_flags & CHIP_F_HAS_DUAL_BANK) || - sl->flash_type == STLINK_FLASH_TYPE_F1_XL) { + sl->flash_type == STM32_FLASH_TYPE_F1_XL) { clear_flash_cr_pg(sl, BANK_2); } lock_flash(sl); - } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { uint32_t val; uint32_t flash_regs_base = get_stm32l0_flash_base(sl); @@ -3716,7 +3717,7 @@ int stlink_parse_ihex(const char *path, uint8_t erased_pattern, uint8_t **mem, } uint8_t stlink_get_erased_pattern(stlink_t *sl) { - if (sl->flash_type == STLINK_FLASH_TYPE_L0) { + if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { return (0x00); } else { return (0xff); @@ -4387,7 +4388,7 @@ int stlink_read_option_bytes_boot_add32(stlink_t *sl, uint32_t *option_byte) { } switch (sl->flash_type) { - case STLINK_FLASH_TYPE_F7: + case STM32_FLASH_TYPE_F7: return stlink_read_option_bytes_boot_add_f7(sl, option_byte); default: return -1; @@ -4408,10 +4409,10 @@ int stlink_read_option_control_register32(stlink_t *sl, uint32_t *option_byte) { } switch (sl->flash_type) { - case STLINK_FLASH_TYPE_F0: - case STLINK_FLASH_TYPE_F1_XL: + case STM32_FLASH_TYPE_F0_F1_F3: + case STM32_FLASH_TYPE_F1_XL: return stlink_read_option_control_register_f0(sl, option_byte); - case STLINK_FLASH_TYPE_F7: + case STM32_FLASH_TYPE_F7: return stlink_read_option_control_register_f7(sl, option_byte); default: return -1; @@ -4432,7 +4433,7 @@ int stlink_read_option_control_register1_32(stlink_t *sl, } switch (sl->flash_type) { - case STLINK_FLASH_TYPE_F7: + case STM32_FLASH_TYPE_F7: return stlink_read_option_control_register1_f7(sl, option_byte); default: return -1; @@ -4494,27 +4495,27 @@ int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t *base, } switch (sl->flash_type) { - case STLINK_FLASH_TYPE_F0: - case STLINK_FLASH_TYPE_F1_XL: + case STM32_FLASH_TYPE_F0_F1_F3: + case STM32_FLASH_TYPE_F1_XL: ret = stlink_write_option_bytes_f0(sl, base, addr, len); break; - case STLINK_FLASH_TYPE_F4: + case STM32_FLASH_TYPE_F2_F4: ret = stlink_write_option_bytes_f4(sl, base, addr, len); break; - case STLINK_FLASH_TYPE_F7: + case STM32_FLASH_TYPE_F7: ret = stlink_write_option_bytes_f7(sl, base, addr, len); break; - case STLINK_FLASH_TYPE_L0: + case STM32_FLASH_TYPE_L0_L1: ret = stlink_write_option_bytes_l0(sl, base, addr, len); break; - case STLINK_FLASH_TYPE_L4: + case STM32_FLASH_TYPE_L4_L4P: ret = stlink_write_option_bytes_l4(sl, base, addr, len); break; - case STLINK_FLASH_TYPE_G0: - case STLINK_FLASH_TYPE_G4: + case STM32_FLASH_TYPE_G0: + case STM32_FLASH_TYPE_G4: ret = stlink_write_option_bytes_gx(sl, base, addr, len); break; - case STLINK_FLASH_TYPE_H7: + case STM32_FLASH_TYPE_H7: ret = stlink_write_option_bytes_h7(sl, base, addr, len); break; default: @@ -4732,7 +4733,7 @@ int stlink_write_option_bytes_boot_add32(stlink_t *sl, } switch (sl->flash_type) { - case STLINK_FLASH_TYPE_F7: + case STM32_FLASH_TYPE_F7: ret = stlink_write_option_bytes_boot_add_f7(sl, option_bytes_boot_add); break; default: @@ -4777,11 +4778,11 @@ int stlink_write_option_control_register32(stlink_t *sl, } switch (sl->flash_type) { - case STLINK_FLASH_TYPE_F0: - case STLINK_FLASH_TYPE_F1_XL: + case STM32_FLASH_TYPE_F0_F1_F3: + case STM32_FLASH_TYPE_F1_XL: ret = stlink_write_option_control_register_f0(sl, option_control_register); break; - case STLINK_FLASH_TYPE_F7: + case STM32_FLASH_TYPE_F7: ret = stlink_write_option_control_register_f7(sl, option_control_register); break; default: @@ -4826,7 +4827,7 @@ int stlink_write_option_control_register1_32( } switch (sl->flash_type) { - case STLINK_FLASH_TYPE_F7: + case STM32_FLASH_TYPE_F7: ret = stlink_write_option_control_register1_f7(sl, option_control_register1); break; diff --git a/src/st-flash/flash.c b/src/st-flash/flash.c index 51702b683..dfc972c4e 100644 --- a/src/st-flash/flash.c +++ b/src/st-flash/flash.c @@ -8,6 +8,7 @@ #include #include +#include #include #include "flash.h" @@ -67,7 +68,7 @@ int main(int ac, char** av) { if (sl == NULL) { return(-1); } - if (sl->flash_type == STLINK_FLASH_TYPE_UNKNOWN) { + if (sl->flash_type == STM32_FLASH_TYPE_UNKNOWN) { printf("Failed to connect to target\n"); goto on_error; } diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index 4ab83ba3d..78233ec1c 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -129,7 +129,7 @@ void process_chipfile(char *fname) { } else if (strcmp (word, "flash_type") == 0) { if (sscanf(value, "%i", (int *)&ts->flash_type) < 1) { fprintf(stderr, "Failed to parse flash type\n"); - } else if ((ts->flash_type < STLINK_FLASH_TYPE_UNKNOWN) || (ts->flash_type >= STLINK_FLASH_TYPE_MAX)) { + } else if ((ts->flash_type < STM32_FLASH_TYPE_UNKNOWN) || (ts->flash_type >= STM32_FLASH_TYPE_UNDEFINED)) { fprintf(stderr, "Unrecognized flash type\n"); } } else if (strcmp (word, "flash_size_reg") == 0) { diff --git a/src/stlink-lib/chipid.h b/src/stlink-lib/chipid.h index e821f0b57..86cd49ddb 100644 --- a/src/stlink-lib/chipid.h +++ b/src/stlink-lib/chipid.h @@ -13,7 +13,7 @@ struct stlink_chipid_params { char *dev_type; char *ref_manual_id; uint32_t chip_id; - enum stlink_flash_type flash_type; + enum stm32_flash_type flash_type; uint32_t flash_size_reg; uint32_t flash_pagesize; uint32_t sram_size; diff --git a/src/stlink-lib/flash_loader.c b/src/stlink-lib/flash_loader.c index 7076a2cfa..6b318dc46 100644 --- a/src/stlink-lib/flash_loader.c +++ b/src/stlink-lib/flash_loader.c @@ -2,6 +2,7 @@ #include #include +#include #include #include #include "flash_loader.h" @@ -176,7 +177,7 @@ int stlink_flash_loader_init(stlink_t *sl, flash_loader_t *fl) { ILOG("Successfully loaded flash loader in sram\n"); // set address of IWDG key register for reset it - if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + if (sl->flash_type == STM32_FLASH_TYPE_H7) { fl->iwdg_kr = STM32H7_WDG_KR; } else { fl->iwdg_kr = STM32F0_WDG_KR; @@ -333,7 +334,7 @@ int stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t targe return(-1); } - if ((sl->flash_type == STLINK_FLASH_TYPE_F1_XL) && (target >= FLASH_BANK2_START_ADDR)) { + if ((sl->flash_type == STM32_FLASH_TYPE_F1_XL) && (target >= FLASH_BANK2_START_ADDR)) { flash_base = FLASH_REGS_BANK2_OFS; } From 115f7c846adf612c1ee818713530dbf17287ed9b Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 9 Jan 2022 23:53:30 +0100 Subject: [PATCH 343/503] Transition to new enum stm32_chipids --- config/chips/F03x.chip | 2 +- config/chips/F04x.chip | 2 +- config/chips/F05x.chip | 2 +- config/chips/F07x.chip | 2 +- config/chips/F09x.chip | 2 +- config/chips/F1xx_CL.chip | 2 +- config/chips/F1xx_HD.chip | 2 +- config/chips/F1xx_LD.chip | 2 +- config/chips/F1xx_MD.chip | 2 +- config/chips/F1xx_VL_HD.chip | 2 +- config/chips/F1xx_VL_MD_LD.chip | 2 +- config/chips/F1xx_XLD.chip | 2 +- config/chips/F2xx.chip | 2 +- config/chips/F301_F302_F318.chip | 2 +- config/chips/F302_F303_F358.chip | 2 +- config/chips/F302_F303_F398_HD.chip | 2 +- config/chips/F303_F328_F334.chip | 2 +- config/chips/F37x.chip | 2 +- config/chips/F401xB_xC.chip | 2 +- config/chips/F401xD_xE.chip | 2 +- config/chips/F410.chip | 2 +- config/chips/F411xC_xE.chip | 2 +- config/chips/F412.chip | 2 +- config/chips/F413_F423.chip | 2 +- config/chips/F42x_F43x.chip | 2 +- config/chips/F446.chip | 2 +- config/chips/F46x_F47x.chip | 2 +- config/chips/F4x5_F4x7.chip | 2 +- config/chips/F72x_F73x.chip | 2 +- config/chips/F74x_F75x.chip | 2 +- config/chips/F76x_F77x.chip | 2 +- config/chips/G03x_G04x.chip | 2 +- config/chips/G05x_G06x.chip | 2 +- config/chips/G07x_G08x.chip | 2 +- config/chips/G0Bx_G0Cx.chip | 2 +- config/chips/G43x_G44x.chip | 2 +- config/chips/G47x_G48x.chip | 2 +- config/chips/G49x_G4Ax.chip | 2 +- config/chips/H72x_H73x.chip | 2 +- config/chips/H74x_H75x.chip | 2 +- config/chips/H7Ax_H7Bx.chip | 2 +- config/chips/L0xxx_Cat_1.chip | 2 +- config/chips/L0xxx_Cat_2.chip | 2 +- config/chips/L0xxx_Cat_3.chip | 2 +- config/chips/L0xxx_Cat_5.chip | 2 +- config/chips/L1xx_Cat_1.chip | 2 +- config/chips/L1xx_Cat_2.chip | 2 +- config/chips/L1xx_Cat_3.chip | 2 +- config/chips/L1xx_Cat_4.chip | 2 +- config/chips/L1xx_Cat_5.chip | 2 +- config/chips/L41x_L42x.chip | 2 +- config/chips/L43x_L44x.chip | 2 +- config/chips/L45x_L46x.chip | 2 +- config/chips/L47x_L48x.chip | 2 +- config/chips/L496x_L4A6x.chip | 2 +- config/chips/L4Px.chip | 2 +- config/chips/L4Rx.chip | 2 +- config/chips/WBx0_WBx5.chip | 2 +- config/chips/WLx5.chip | 2 +- config/chips/unknown_device.chip | 2 +- inc/stlink.h | 32 +- inc/stm32.h | 142 +++-- src/common.c | 96 +-- src/st-trace/trace.c | 2 +- src/st-util/gdb-server.c | 28 +- src/stlink-lib/chipid_db_old.h | 877 ---------------------------- src/stlink-lib/flash_loader.c | 92 +-- 67 files changed, 254 insertions(+), 1135 deletions(-) delete mode 100644 src/stlink-lib/chipid_db_old.h diff --git a/config/chips/F03x.chip b/config/chips/F03x.chip index d19e6a657..3b4ff2a74 100644 --- a/config/chips/F03x.chip +++ b/config/chips/F03x.chip @@ -2,7 +2,7 @@ # dev_type STM32F03x ref_manual_id 0091 -chip_id 0x444 // STLINK_CHIPID_STM32_F0xx_SMALL +chip_id 0x444 // STM32_CHIPID_STM32_F0xx_SMALL flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3 flash_size_reg 0x1ffff7cc flash_pagesize 0x400 // 1 KB diff --git a/config/chips/F04x.chip b/config/chips/F04x.chip index 7012d6d7e..267c93765 100644 --- a/config/chips/F04x.chip +++ b/config/chips/F04x.chip @@ -2,7 +2,7 @@ # dev_type STM32F04x ref_manual_id 0091 -chip_id 0x445 // STLINK_CHIPID_STM32_F04 +chip_id 0x445 // STM32_CHIPID_STM32_F04 flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3 flash_size_reg 0x1ffff7cc flash_pagesize 0x400 // 1 KB diff --git a/config/chips/F05x.chip b/config/chips/F05x.chip index e987cf725..dc511e1a2 100644 --- a/config/chips/F05x.chip +++ b/config/chips/F05x.chip @@ -2,7 +2,7 @@ # dev_type STM32F05x ref_manual_id 0091 -chip_id 0x440 // STLINK_CHIPID_STM32_F0 +chip_id 0x440 // STM32_CHIPID_STM32_F0 flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3 flash_size_reg 0x1ffff7cc flash_pagesize 0x400 // 1 KB diff --git a/config/chips/F07x.chip b/config/chips/F07x.chip index 0f7513e1b..b12ef1bab 100644 --- a/config/chips/F07x.chip +++ b/config/chips/F07x.chip @@ -2,7 +2,7 @@ # dev_type STM32F07x ref_manual_id 0091 -chip_id 0x448 // STLINK_CHIPID_STM32_F0_CAN +chip_id 0x448 // STM32_CHIPID_STM32_F0_CAN flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3 flash_size_reg 0x1ffff7cc flash_pagesize 0x800 // 2 KB diff --git a/config/chips/F09x.chip b/config/chips/F09x.chip index 3d3cc8c89..97f1a1a75 100644 --- a/config/chips/F09x.chip +++ b/config/chips/F09x.chip @@ -2,7 +2,7 @@ # dev_type STM32F09x ref_manual_id 0091 -chip_id 0x442 // STLINK_CHIPID_STM32_F09x +chip_id 0x442 // STM32_CHIPID_STM32_F09x flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3 flash_size_reg 0x1ffff7cc flash_pagesize 0x800 // 2 KB diff --git a/config/chips/F1xx_CL.chip b/config/chips/F1xx_CL.chip index eb417132a..dd316dca3 100644 --- a/config/chips/F1xx_CL.chip +++ b/config/chips/F1xx_CL.chip @@ -2,7 +2,7 @@ # dev_type STM32F1xx_CL ref_manual_id 0008 -chip_id 0x418 // STLINK_CHIPID_STM32_F1_CONN +chip_id 0x418 // STM32_CHIPID_STM32_F1_CONN flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3 flash_size_reg 0x1ffff7e0 flash_pagesize 0x800 // 2 KB diff --git a/config/chips/F1xx_HD.chip b/config/chips/F1xx_HD.chip index 5def8ebb9..696b284ba 100644 --- a/config/chips/F1xx_HD.chip +++ b/config/chips/F1xx_HD.chip @@ -2,7 +2,7 @@ # dev_type F1xx_HD ref_manual_id 0008 -chip_id 0x414 // STLINK_CHIPID_STM32_F1_HD +chip_id 0x414 // STM32_CHIPID_STM32_F1_HD flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3 flash_size_reg 0x1ffff7e0 flash_pagesize 0x800 // 2 KB diff --git a/config/chips/F1xx_LD.chip b/config/chips/F1xx_LD.chip index 33efe063a..898af4c8c 100644 --- a/config/chips/F1xx_LD.chip +++ b/config/chips/F1xx_LD.chip @@ -2,7 +2,7 @@ # dev_type STM32F1xx_LD ref_manual_id 0008 -chip_id 0x412 // STLINK_CHIPID_STM32_F1_LD +chip_id 0x412 // STM32_CHIPID_STM32_F1_LD flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3 flash_size_reg 0x1ffff7e0 flash_pagesize 0x400 // 1 KB diff --git a/config/chips/F1xx_MD.chip b/config/chips/F1xx_MD.chip index 5b250d9cd..a611f3f2d 100644 --- a/config/chips/F1xx_MD.chip +++ b/config/chips/F1xx_MD.chip @@ -2,7 +2,7 @@ # dev_type STM32F1xx_MD ref_manual_id 0008 -chip_id 0x410 // STLINK_CHIPID_STM32_F1_MD +chip_id 0x410 // STM32_CHIPID_STM32_F1_MD flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3 flash_size_reg 0x1ffff7e0 flash_pagesize 0x400 // 1 KB diff --git a/config/chips/F1xx_VL_HD.chip b/config/chips/F1xx_VL_HD.chip index 1ceade91a..d59fa4814 100644 --- a/config/chips/F1xx_VL_HD.chip +++ b/config/chips/F1xx_VL_HD.chip @@ -2,7 +2,7 @@ # dev_type STM32F1xx_VL_HD ref_manual_id 0041 -chip_id 0x428 // STLINK_CHIPID_STM32_F1_VL_HD +chip_id 0x428 // STM32_CHIPID_STM32_F1_VL_HD flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3 flash_size_reg 0x1ffff7e0 flash_pagesize 0x800 // 2 KB diff --git a/config/chips/F1xx_VL_MD_LD.chip b/config/chips/F1xx_VL_MD_LD.chip index 3f577f74e..aac2244fd 100644 --- a/config/chips/F1xx_VL_MD_LD.chip +++ b/config/chips/F1xx_VL_MD_LD.chip @@ -2,7 +2,7 @@ # dev_type STM32F1xx_VL_MD_LD ref_manual_id 0041 -chip_id 0x420 // STLINK_CHIPID_STM32_F1_VL_MD_LD +chip_id 0x420 // STM32_CHIPID_STM32_F1_VL_MD_LD flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3 flash_size_reg 0x1ffff7e0 flash_pagesize 0x400 // 1 KB diff --git a/config/chips/F1xx_XLD.chip b/config/chips/F1xx_XLD.chip index 964105747..7627dd883 100644 --- a/config/chips/F1xx_XLD.chip +++ b/config/chips/F1xx_XLD.chip @@ -2,7 +2,7 @@ # dev_type STM32F1xx_XLD ref_manual_id 0008 -chip_id 0x430 // STLINK_CHIPID_STM32_F1_XLD +chip_id 0x430 // STM32_CHIPID_STM32_F1_XLD flash_type 2 // STM32_FLASH_TYPE_F1_XL flash_size_reg 0x1ffff7e0 flash_pagesize 0x800 // 2 KB diff --git a/config/chips/F2xx.chip b/config/chips/F2xx.chip index 4cb99b2fc..5e6aac5a0 100644 --- a/config/chips/F2xx.chip +++ b/config/chips/F2xx.chip @@ -2,7 +2,7 @@ # dev_type STM32F2xx ref_manual_id 0033 -chip_id 0x411 // STLINK_CHIPID_STM32_F2 +chip_id 0x411 // STM32_CHIPID_STM32_F2 flash_type 3 // STM32_FLASH_TYPE_F2_F4 flash_size_reg 0x1fff7a22 flash_pagesize 0x20000 // 128 KB diff --git a/config/chips/F301_F302_F318.chip b/config/chips/F301_F302_F318.chip index b35de12bf..3a3d8bb45 100644 --- a/config/chips/F301_F302_F318.chip +++ b/config/chips/F301_F302_F318.chip @@ -2,7 +2,7 @@ # dev_type STM32F301_F302_F318 ref_manual_id 0365 // also RM0366 -chip_id 0x439 // STLINK_CHIPID_STM32_F3xx_SMALL +chip_id 0x439 // STM32_CHIPID_STM32_F3xx_SMALL flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3 flash_size_reg 0x1ffff7cc flash_pagesize 0x800 // 2 KB diff --git a/config/chips/F302_F303_F358.chip b/config/chips/F302_F303_F358.chip index 6226ca8e8..922387292 100644 --- a/config/chips/F302_F303_F358.chip +++ b/config/chips/F302_F303_F358.chip @@ -2,7 +2,7 @@ # dev_type STM32F302_F303_358 ref_manual_id 0365 // also RM0316 -chip_id 0x422 // STLINK_CHIPID_STM32_F3 +chip_id 0x422 // STM32_CHIPID_STM32_F3 flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3 flash_size_reg 0x1ffff7cc flash_pagesize 0x800 // 2 KB diff --git a/config/chips/F302_F303_F398_HD.chip b/config/chips/F302_F303_F398_HD.chip index b4ad3aed8..44cec8a6d 100644 --- a/config/chips/F302_F303_F398_HD.chip +++ b/config/chips/F302_F303_F398_HD.chip @@ -2,7 +2,7 @@ # dev_type STM32F302_F303_F398_HD ref_manual_id 0365 // also RM0316 (Rev 5) -chip_id 0x446 // STLINK_CHIPID_STM32_F303_HD +chip_id 0x446 // STM32_CHIPID_STM32_F303_HD flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3 flash_size_reg 0x1ffff7cc flash_pagesize 0x800 // 2 KB diff --git a/config/chips/F303_F328_F334.chip b/config/chips/F303_F328_F334.chip index 010c3b622..fb77e3117 100644 --- a/config/chips/F303_F328_F334.chip +++ b/config/chips/F303_F328_F334.chip @@ -2,7 +2,7 @@ # dev_type STM32F303_F328_F334 ref_manual_id 0364 // also RM0316 -chip_id 0x438 // STLINK_CHIPID_STM32_F334 +chip_id 0x438 // STM32_CHIPID_STM32_F334 flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3 flash_size_reg 0x1ffff7cc flash_pagesize 0x800 // 2 KB diff --git a/config/chips/F37x.chip b/config/chips/F37x.chip index 9ca9d72f8..5363da8fa 100644 --- a/config/chips/F37x.chip +++ b/config/chips/F37x.chip @@ -2,7 +2,7 @@ # dev_type STM32F37x ref_manual_id 0313 -chip_id 0x432 // STLINK_CHIPID_STM32_F37x +chip_id 0x432 // STM32_CHIPID_STM32_F37x flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3 flash_size_reg 0x1ffff7cc flash_pagesize 0x800 // 2 KB diff --git a/config/chips/F401xB_xC.chip b/config/chips/F401xB_xC.chip index e1f37d94b..e75b27d09 100644 --- a/config/chips/F401xB_xC.chip +++ b/config/chips/F401xB_xC.chip @@ -2,7 +2,7 @@ # dev_type STM32F401xB_xC ref_manual_id 0368 -chip_id 0x423 // STLINK_CHIPID_STM32_F4_LP +chip_id 0x423 // STM32_CHIPID_STM32_F4_LP flash_type 3 // STM32_FLASH_TYPE_F2_F4 flash_size_reg 0x1fff7a22 flash_pagesize 0x4000 // 16 KB diff --git a/config/chips/F401xD_xE.chip b/config/chips/F401xD_xE.chip index f03661495..022d5072a 100644 --- a/config/chips/F401xD_xE.chip +++ b/config/chips/F401xD_xE.chip @@ -2,7 +2,7 @@ # dev_type STM32F401xD_xE ref_manual_id 0368 -chip_id 0x433 // STLINK_CHIPID_STM32_F4_DE +chip_id 0x433 // STM32_CHIPID_STM32_F4_DE flash_type 3 // STM32_FLASH_TYPE_F2_F4 flash_size_reg 0x1fff7a22 flash_pagesize 0x4000 // 16 KB diff --git a/config/chips/F410.chip b/config/chips/F410.chip index 6f7727921..84c9c00bf 100644 --- a/config/chips/F410.chip +++ b/config/chips/F410.chip @@ -2,7 +2,7 @@ # dev_type STM32F410 ref_manual_id 0401 -chip_id 0x458 // STLINK_CHIPID_STM32_F410 +chip_id 0x458 // STM32_CHIPID_STM32_F410 flash_type 3 // STM32_FLASH_TYPE_F2_F4 flash_size_reg 0x1fff7a22 flash_pagesize 0x4000 // 16 KB diff --git a/config/chips/F411xC_xE.chip b/config/chips/F411xC_xE.chip index 5d624b7d9..d028a874c 100644 --- a/config/chips/F411xC_xE.chip +++ b/config/chips/F411xC_xE.chip @@ -2,7 +2,7 @@ # dev_type STM32F411xC_xE ref_manual_id 0383 -chip_id 0x431 // STLINK_CHIPID_STM32_F411xx +chip_id 0x431 // STM32_CHIPID_STM32_F411xx flash_type 3 // STM32_FLASH_TYPE_F2_F4 flash_size_reg 0x1fff7a22 flash_pagesize 0x4000 // 16 KB diff --git a/config/chips/F412.chip b/config/chips/F412.chip index bd18ec2ea..b4c1cb418 100644 --- a/config/chips/F412.chip +++ b/config/chips/F412.chip @@ -2,7 +2,7 @@ # dev_type STM32F412 ref_manual_id 0402 -chip_id 0x441 // STLINK_CHIPID_STM32_F412 +chip_id 0x441 // STM32_CHIPID_STM32_F412 flash_type 3 // STM32_FLASH_TYPE_F2_F4 flash_size_reg 0x1fff7a22 flash_pagesize 0x4000 // 16 KB diff --git a/config/chips/F413_F423.chip b/config/chips/F413_F423.chip index c7e036a2d..f042bce76 100644 --- a/config/chips/F413_F423.chip +++ b/config/chips/F413_F423.chip @@ -2,7 +2,7 @@ # dev_type STM32F413_F423 ref_manual_id 0430 // RM0430 (Rev 2) -chip_id 0x463 // STLINK_CHIPID_STM32_F413 +chip_id 0x463 // STM32_CHIPID_STM32_F413 flash_type 3 // STM32_FLASH_TYPE_F2_F4 flash_size_reg 0x1fff7a22 flash_pagesize 0x4000 // 16 KB diff --git a/config/chips/F42x_F43x.chip b/config/chips/F42x_F43x.chip index cbb77e152..69aff7c88 100644 --- a/config/chips/F42x_F43x.chip +++ b/config/chips/F42x_F43x.chip @@ -2,7 +2,7 @@ # dev_type STM32F42x_F43x ref_manual_id 0090 // RM0090 (Rev. 2) -chip_id 0x463 // STLINK_CHIPID_STM32_F4_HD +chip_id 0x463 // STM32_CHIPID_STM32_F4_HD flash_type 3 // STM32_FLASH_TYPE_F2_F4 flash_size_reg 0x1fff7a22 flash_pagesize 0x4000 // 16 KB diff --git a/config/chips/F446.chip b/config/chips/F446.chip index 2ac868ddd..5fa2edbcb 100644 --- a/config/chips/F446.chip +++ b/config/chips/F446.chip @@ -2,7 +2,7 @@ # dev_type STM32F446 ref_manual_id 0390 -chip_id 0x421 // STLINK_CHIPID_STM32_F446 +chip_id 0x421 // STM32_CHIPID_STM32_F446 flash_type 3 // STM32_FLASH_TYPE_F2_F4 flash_size_reg 0x1fff7a22 flash_pagesize 0x20000 // 128 KB diff --git a/config/chips/F46x_F47x.chip b/config/chips/F46x_F47x.chip index e8d66cbd7..e8364ead5 100644 --- a/config/chips/F46x_F47x.chip +++ b/config/chips/F46x_F47x.chip @@ -2,7 +2,7 @@ # dev_type STM32F46x_F47x ref_manual_id 0090 // RM0090 (Rev. 2) -chip_id 0x434 // STLINK_CHIPID_STM32_F4_DSI +chip_id 0x434 // STM32_CHIPID_STM32_F4_DSI flash_type 3 // STM32_FLASH_TYPE_F2_F4 flash_size_reg 0x1fff7a22 flash_pagesize 0x4000 // 16 KB diff --git a/config/chips/F4x5_F4x7.chip b/config/chips/F4x5_F4x7.chip index d75f74103..e78b552c4 100644 --- a/config/chips/F4x5_F4x7.chip +++ b/config/chips/F4x5_F4x7.chip @@ -2,7 +2,7 @@ # dev_type STM32F4x5_F4x7 ref_manual_id 0090 // RM0090 (Rev. 2) -chip_id 0x413 // STLINK_CHIPID_STM32_F4 +chip_id 0x413 // STM32_CHIPID_STM32_F4 flash_type 3 // STM32_FLASH_TYPE_F2_F4 flash_size_reg 0x1fff7a22 flash_pagesize 0x4000 // 16 KB diff --git a/config/chips/F72x_F73x.chip b/config/chips/F72x_F73x.chip index c0f2df155..5e1131d2e 100644 --- a/config/chips/F72x_F73x.chip +++ b/config/chips/F72x_F73x.chip @@ -2,7 +2,7 @@ # dev_type STM32F72x_F73x ref_manual_id 0431 -chip_id 0x452 // STLINK_CHIPID_STM32_F72xxx +chip_id 0x452 // STM32_CHIPID_STM32_F72xxx flash_type 4 // STM32_FLASH_TYPE_F7 flash_size_reg 0x1ff07a22 flash_pagesize 0x800 // 2 KB diff --git a/config/chips/F74x_F75x.chip b/config/chips/F74x_F75x.chip index fa0b6ddc2..391ae124d 100644 --- a/config/chips/F74x_F75x.chip +++ b/config/chips/F74x_F75x.chip @@ -2,7 +2,7 @@ # dev_type STM32F74x_F75x ref_manual_id 0385 -chip_id 0x449 // STLINK_CHIPID_STM32_F7 +chip_id 0x449 // STM32_CHIPID_STM32_F7 flash_type 4 // STM32_FLASH_TYPE_F7 flash_size_reg 0x1ff0f442 flash_pagesize 0x800 // 2 KB diff --git a/config/chips/F76x_F77x.chip b/config/chips/F76x_F77x.chip index c1a5a9cf2..bb87dce7a 100644 --- a/config/chips/F76x_F77x.chip +++ b/config/chips/F76x_F77x.chip @@ -2,7 +2,7 @@ # dev_type STM32F76x_F77x ref_manual_id 0410 -chip_id 0x451 // STLINK_CHIPID_STM32_F76xxx +chip_id 0x451 // STM32_CHIPID_STM32_F76xxx flash_type 4 // STM32_FLASH_TYPE_F7 flash_size_reg 0x1ff0f442 flash_pagesize 0x800 // 2 KB diff --git a/config/chips/G03x_G04x.chip b/config/chips/G03x_G04x.chip index aee016e0d..4a7e11fcd 100644 --- a/config/chips/G03x_G04x.chip +++ b/config/chips/G03x_G04x.chip @@ -2,7 +2,7 @@ # dev_type STM32G03x_G04x ref_manual_id 0444 // also RM454 -chip_id 0x466 // STLINK_CHIPID_STM32_G0_CAT1 +chip_id 0x466 // STM32_CHIPID_STM32_G0_CAT1 flash_type 5 // STM32_FLASH_TYPE_G0 flash_size_reg 0x1fff75e0 flash_pagesize 0x800 // 2 KB diff --git a/config/chips/G05x_G06x.chip b/config/chips/G05x_G06x.chip index f92cad889..81f97b58d 100644 --- a/config/chips/G05x_G06x.chip +++ b/config/chips/G05x_G06x.chip @@ -2,7 +2,7 @@ # dev_type STM32G05x_G06x ref_manual_id 0444 -chip_id 0x456 // STLINK_CHIPID_STM32_G0_CAT4 +chip_id 0x456 // STM32_CHIPID_STM32_G0_CAT4 flash_type 5 // STM32_FLASH_TYPE_G0 flash_size_reg 0x1fff75e0 flash_pagesize 0x800 // 2 KB diff --git a/config/chips/G07x_G08x.chip b/config/chips/G07x_G08x.chip index 29f527e73..cac804a78 100644 --- a/config/chips/G07x_G08x.chip +++ b/config/chips/G07x_G08x.chip @@ -2,7 +2,7 @@ # dev_type STM32G07x_G08x ref_manual_id 0444 -chip_id 0x460 // STLINK_CHIPID_STM32_G0_CAT2 +chip_id 0x460 // STM32_CHIPID_STM32_G0_CAT2 flash_type 5 // STM32_FLASH_TYPE_G0 flash_size_reg 0x1fff75e0 flash_pagesize 0x800 // 2 KB diff --git a/config/chips/G0Bx_G0Cx.chip b/config/chips/G0Bx_G0Cx.chip index 67254fbbd..845cf8280 100644 --- a/config/chips/G0Bx_G0Cx.chip +++ b/config/chips/G0Bx_G0Cx.chip @@ -2,7 +2,7 @@ # dev_type STM32G0Bx_G0Cx ref_manual_id 0444 -chip_id 0x467 // STLINK_CHIPID_STM32_G0_CAT3 +chip_id 0x467 // STM32_CHIPID_STM32_G0_CAT3 flash_type 5 // STM32_FLASH_TYPE_G0 flash_size_reg 0x1fff75e0 flash_pagesize 0x800 // 2 KB diff --git a/config/chips/G43x_G44x.chip b/config/chips/G43x_G44x.chip index b33a1a0f8..6b19d4fb4 100644 --- a/config/chips/G43x_G44x.chip +++ b/config/chips/G43x_G44x.chip @@ -2,7 +2,7 @@ # dev_type STM32G43x_G44x ref_manual_id 0440 -chip_id 0x468 // STLINK_CHIPID_STM32_G4_CAT2 +chip_id 0x468 // STM32_CHIPID_STM32_G4_CAT2 flash_type 6 // STM32_FLASH_TYPE_G4 flash_size_reg 0x1fff75e0 flash_pagesize 0x800 // 2 KB diff --git a/config/chips/G47x_G48x.chip b/config/chips/G47x_G48x.chip index abf6a6f2d..d3330da59 100644 --- a/config/chips/G47x_G48x.chip +++ b/config/chips/G47x_G48x.chip @@ -2,7 +2,7 @@ # dev_type STM32G47x_G48x ref_manual_id 0440 -chip_id 0x469 // STLINK_CHIPID_STM32_G4_CAT3 +chip_id 0x469 // STM32_CHIPID_STM32_G4_CAT3 flash_type 6 // STM32_FLASH_TYPE_G4 flash_size_reg 0x1fff75e0 flash_pagesize 0x800 // 2 KB diff --git a/config/chips/G49x_G4Ax.chip b/config/chips/G49x_G4Ax.chip index 3d8110f19..a39237142 100644 --- a/config/chips/G49x_G4Ax.chip +++ b/config/chips/G49x_G4Ax.chip @@ -2,7 +2,7 @@ # dev_type STM32G49x_G4Ax ref_manual_id 0440 -chip_id 0x479 // STLINK_CHIPID_STM32_G4_CAT4 +chip_id 0x479 // STM32_CHIPID_STM32_G4_CAT4 flash_type 6 // STM32_FLASH_TYPE_G4 flash_size_reg 0x1fff75e0 flash_pagesize 0x800 // 2 KB diff --git a/config/chips/H72x_H73x.chip b/config/chips/H72x_H73x.chip index 1417cdb27..998aa9812 100644 --- a/config/chips/H72x_H73x.chip +++ b/config/chips/H72x_H73x.chip @@ -2,7 +2,7 @@ # dev_type STM32H72x_H73x ref_manual_id 0468 -chip_id 0x483 // STLINK_CHIPID_STM32_H72x +chip_id 0x483 // STM32_CHIPID_STM32_H72x flash_type 7 // STM32_FLASH_TYPE_H7 flash_size_reg 0x1ff1e880 flash_pagesize 0x20000 // 128 KB diff --git a/config/chips/H74x_H75x.chip b/config/chips/H74x_H75x.chip index 53a3e921a..0bfea13a4 100644 --- a/config/chips/H74x_H75x.chip +++ b/config/chips/H74x_H75x.chip @@ -2,7 +2,7 @@ # dev_type STM32H74x_H75x ref_manual_id 0433 -chip_id 0x450 // STLINK_CHIPID_STM32_H74xxx +chip_id 0x450 // STM32_CHIPID_STM32_H74xxx flash_type 7 // STM32_FLASH_TYPE_H7 flash_size_reg 0x1ff1e880 flash_pagesize 0x20000 // 128 KB diff --git a/config/chips/H7Ax_H7Bx.chip b/config/chips/H7Ax_H7Bx.chip index 516c4260e..2e784193c 100644 --- a/config/chips/H7Ax_H7Bx.chip +++ b/config/chips/H7Ax_H7Bx.chip @@ -2,7 +2,7 @@ # dev_type STM32H7Ax_H7Bx ref_manual_id 0455 -chip_id 0x480 // STLINK_CHIPID_STM32_H7Ax +chip_id 0x480 // STM32_CHIPID_STM32_H7Ax flash_type 7 // STM32_FLASH_TYPE_H7 flash_size_reg 0x08fff80c flash_pagesize 0x2000 // 8 KB diff --git a/config/chips/L0xxx_Cat_1.chip b/config/chips/L0xxx_Cat_1.chip index 6dc227024..4b108b4f4 100644 --- a/config/chips/L0xxx_Cat_1.chip +++ b/config/chips/L0xxx_Cat_1.chip @@ -2,7 +2,7 @@ # dev_type STM32L0xxx_Cat_1 ref_manual_id 0451 // also RM0377 -chip_id 0x457 // STLINK_CHIPID_STM32_L011 +chip_id 0x457 // STM32_CHIPID_STM32_L011 flash_type 8 // STM32_FLASH_TYPE_L0_L1 flash_size_reg 0x1ff8007c flash_pagesize 0x80 // 128 B diff --git a/config/chips/L0xxx_Cat_2.chip b/config/chips/L0xxx_Cat_2.chip index 74a3d6157..5665e8df1 100644 --- a/config/chips/L0xxx_Cat_2.chip +++ b/config/chips/L0xxx_Cat_2.chip @@ -2,7 +2,7 @@ # dev_type STM32L0xxx_Cat_2 ref_manual_id 0451 // also RM0377 -chip_id 0x425 // STLINK_CHIPID_STM32_L0_CAT2 +chip_id 0x425 // STM32_CHIPID_STM32_L0_CAT2 flash_type 8 // STM32_FLASH_TYPE_L0_L1 flash_size_reg 0x1ff8007c flash_pagesize 0x80 // 128 B diff --git a/config/chips/L0xxx_Cat_3.chip b/config/chips/L0xxx_Cat_3.chip index 0cfcc53bb..e8cd7c685 100644 --- a/config/chips/L0xxx_Cat_3.chip +++ b/config/chips/L0xxx_Cat_3.chip @@ -2,7 +2,7 @@ # dev_type STM32L0xxx_Cat_3 ref_manual_id 0451 // also RM0367 & RM0377 -chip_id 0x417 // STLINK_CHIPID_STM32_L0 +chip_id 0x417 // STM32_CHIPID_STM32_L0 flash_type 8 // STM32_FLASH_TYPE_L0_L1 flash_size_reg 0x1ff8007c flash_pagesize 0x80 // 128 B diff --git a/config/chips/L0xxx_Cat_5.chip b/config/chips/L0xxx_Cat_5.chip index cbb1e6632..284057091 100644 --- a/config/chips/L0xxx_Cat_5.chip +++ b/config/chips/L0xxx_Cat_5.chip @@ -2,7 +2,7 @@ # dev_type STM32L0xxx_Cat_5 ref_manual_id 0451 // also RM0367 & RM0377 -chip_id 0x447 // STLINK_CHIPID_STM32_L0_CAT5 +chip_id 0x447 // STM32_CHIPID_STM32_L0_CAT5 flash_type 8 // STM32_FLASH_TYPE_L0_L1 flash_size_reg 0x1ff8007c flash_pagesize 0x80 // 128 B diff --git a/config/chips/L1xx_Cat_1.chip b/config/chips/L1xx_Cat_1.chip index cecc32996..f6a11288f 100644 --- a/config/chips/L1xx_Cat_1.chip +++ b/config/chips/L1xx_Cat_1.chip @@ -2,7 +2,7 @@ # dev_type STM32L1xx_Cat_1 ref_manual_id 0038 -chip_id 0x416 // STLINK_CHIPID_STM32_L1_MD +chip_id 0x416 // STM32_CHIPID_STM32_L1_MD flash_type 8 // STM32_FLASH_TYPE_L0_L1 flash_size_reg 0x1ff8004c flash_pagesize 0x100 // 128 B diff --git a/config/chips/L1xx_Cat_2.chip b/config/chips/L1xx_Cat_2.chip index 1981d58a5..c8c796111 100644 --- a/config/chips/L1xx_Cat_2.chip +++ b/config/chips/L1xx_Cat_2.chip @@ -2,7 +2,7 @@ # dev_type STM32L1xx_Cat_2 ref_manual_id 0038 -chip_id 0x429 // STLINK_CHIPID_STM32_L1_CAT2 +chip_id 0x429 // STM32_CHIPID_STM32_L1_CAT2 flash_type 8 // STM32_FLASH_TYPE_L0_L1 flash_size_reg 0x1ff8004c flash_pagesize 0x100 // 128 B diff --git a/config/chips/L1xx_Cat_3.chip b/config/chips/L1xx_Cat_3.chip index 1d551c8a4..f2615f952 100644 --- a/config/chips/L1xx_Cat_3.chip +++ b/config/chips/L1xx_Cat_3.chip @@ -2,7 +2,7 @@ # dev_type STM32L1xx_Cat_3 ref_manual_id 0038 -chip_id 0x427 // STLINK_CHIPID_STM32_L1_MD_PLUS +chip_id 0x427 // STM32_CHIPID_STM32_L1_MD_PLUS flash_type 8 // STM32_FLASH_TYPE_L0_L1 flash_size_reg 0x1ff800cc flash_pagesize 0x100 // 128 B diff --git a/config/chips/L1xx_Cat_4.chip b/config/chips/L1xx_Cat_4.chip index 1e9cfe91c..6a1df1267 100644 --- a/config/chips/L1xx_Cat_4.chip +++ b/config/chips/L1xx_Cat_4.chip @@ -2,7 +2,7 @@ # dev_type STM32L1xx_Cat_4 ref_manual_id 0038 -chip_id 0x436 // STLINK_CHIPID_STM32_L1_MD_PLUS_HD +chip_id 0x436 // STM32_CHIPID_STM32_L1_MD_PLUS_HD flash_type 8 // STM32_FLASH_TYPE_L0_L1 flash_size_reg 0x1ff800cc flash_pagesize 0x100 // 128 B diff --git a/config/chips/L1xx_Cat_5.chip b/config/chips/L1xx_Cat_5.chip index a51356d7a..4fccd99da 100644 --- a/config/chips/L1xx_Cat_5.chip +++ b/config/chips/L1xx_Cat_5.chip @@ -2,7 +2,7 @@ # dev_type STM32L1xx_Cat_5 ref_manual_id 0038 -chip_id 0x437 // STLINK_CHIPID_STM32_L152_RE +chip_id 0x437 // STM32_CHIPID_STM32_L152_RE flash_type 8 // STM32_FLASH_TYPE_L0_L1 flash_size_reg 0x1ff800cc flash_pagesize 0x100 // 128 B diff --git a/config/chips/L41x_L42x.chip b/config/chips/L41x_L42x.chip index 2de859b0c..40085d828 100644 --- a/config/chips/L41x_L42x.chip +++ b/config/chips/L41x_L42x.chip @@ -2,7 +2,7 @@ # dev_type STM32L41x_L42x ref_manual_id 0394 -chip_id 0x464 // STLINK_CHIPID_STM32_L41x_L42x +chip_id 0x464 // STM32_CHIPID_STM32_L41x_L42x flash_type 9 // STM32_FLASH_TYPE_L4_L4P flash_size_reg 0x1fff75e0 flash_pagesize 0x800 // 2 KB diff --git a/config/chips/L43x_L44x.chip b/config/chips/L43x_L44x.chip index 2dad90844..22045c372 100644 --- a/config/chips/L43x_L44x.chip +++ b/config/chips/L43x_L44x.chip @@ -2,7 +2,7 @@ # dev_type STM32L41x_L42x ref_manual_id 0392 -chip_id 0x435 // STLINK_CHIPID_STM32_L43x_L44x +chip_id 0x435 // STM32_CHIPID_STM32_L43x_L44x flash_type 9 // STM32_FLASH_TYPE_L4_L4P flash_size_reg 0x1fff75e0 flash_pagesize 0x800 // 2 KB diff --git a/config/chips/L45x_L46x.chip b/config/chips/L45x_L46x.chip index f856e1315..99e9beca1 100644 --- a/config/chips/L45x_L46x.chip +++ b/config/chips/L45x_L46x.chip @@ -2,7 +2,7 @@ # dev_type STM32L45x_L46x ref_manual_id 0394 -chip_id 0x462 // STLINK_CHIPID_STM32_L45x_L46x +chip_id 0x462 // STM32_CHIPID_STM32_L45x_L46x flash_type 9 // STM32_FLASH_TYPE_L4_L4P flash_size_reg 0x1fff75e0 flash_pagesize 0x800 // 2 KB diff --git a/config/chips/L47x_L48x.chip b/config/chips/L47x_L48x.chip index 51257a37c..44e5282ce 100644 --- a/config/chips/L47x_L48x.chip +++ b/config/chips/L47x_L48x.chip @@ -2,7 +2,7 @@ # dev_type STM32L47x_L48x ref_manual_id 0351 -chip_id 0x415 // STLINK_CHIPID_STM32_L4 +chip_id 0x415 // STM32_CHIPID_STM32_L4 flash_type 9 // STM32_FLASH_TYPE_L4_L4P flash_size_reg 0x1fff75e0 flash_pagesize 0x800 // 2 KB diff --git a/config/chips/L496x_L4A6x.chip b/config/chips/L496x_L4A6x.chip index 32d75b571..b983eb9eb 100644 --- a/config/chips/L496x_L4A6x.chip +++ b/config/chips/L496x_L4A6x.chip @@ -2,7 +2,7 @@ # dev_type STM32L496x_L4A6x ref_manual_id 0351 -chip_id 0x461 // STLINK_CHIPID_STM32_L496x_L4A6x +chip_id 0x461 // STM32_CHIPID_STM32_L496x_L4A6x flash_type 9 // STM32_FLASH_TYPE_L4_L4P flash_size_reg 0x1fff75e0 flash_pagesize 0x800 // 2 KB diff --git a/config/chips/L4Px.chip b/config/chips/L4Px.chip index ff3f05b81..41805c768 100644 --- a/config/chips/L4Px.chip +++ b/config/chips/L4Px.chip @@ -2,7 +2,7 @@ # dev_type STM32L4Px ref_manual_id 0432 -chip_id 0x471 // STLINK_CHIPID_STM32_L4PX +chip_id 0x471 // STM32_CHIPID_STM32_L4PX flash_type 9 // STM32_FLASH_TYPE_L4_L4P flash_size_reg 0x1fff75e0 flash_pagesize 0x1000 // 4 KB diff --git a/config/chips/L4Rx.chip b/config/chips/L4Rx.chip index 535e282c9..d0495f083 100644 --- a/config/chips/L4Rx.chip +++ b/config/chips/L4Rx.chip @@ -2,7 +2,7 @@ # dev_type STM32L4Rx ref_manual_id 0432 -chip_id 0x470 // STLINK_CHIPID_STM32_L4RX +chip_id 0x470 // STM32_CHIPID_STM32_L4RX flash_type 9 // STM32_FLASH_TYPE_L4_L4P flash_size_reg 0x1fff75e0 flash_pagesize 0x1000 // 4 KB diff --git a/config/chips/WBx0_WBx5.chip b/config/chips/WBx0_WBx5.chip index 5fa76ec75..e34c70815 100644 --- a/config/chips/WBx0_WBx5.chip +++ b/config/chips/WBx0_WBx5.chip @@ -2,7 +2,7 @@ # dev_type STM32WBx0_WBx5 ref_manual_id 0434 // also RM0471 -chip_id 0x495 // STLINK_CHIPID_STM32_WB55 +chip_id 0x495 // STM32_CHIPID_STM32_WB55 flash_type 11 // STM32_FLASH_TYPE_WB_WL flash_size_reg 0x1fff75e0 flash_pagesize 0x1000 // 4 KB diff --git a/config/chips/WLx5.chip b/config/chips/WLx5.chip index 62ff4f72f..b27e03dfe 100644 --- a/config/chips/WLx5.chip +++ b/config/chips/WLx5.chip @@ -2,7 +2,7 @@ # dev_type STM32WLEx ref_manual_id 0033 -chip_id 0x497 // STLINK_CHIPID_STM32_WLE +chip_id 0x497 // STM32_CHIPID_STM32_WLE flash_type 11 // STM32_FLASH_TYPE_WB_WL flash_size_reg 0x1fff75e0 flash_pagesize 0x800 // 2 KB diff --git a/config/chips/unknown_device.chip b/config/chips/unknown_device.chip index 512211092..bc50e7a00 100644 --- a/config/chips/unknown_device.chip +++ b/config/chips/unknown_device.chip @@ -2,7 +2,7 @@ # dev_type unknown ref_manual_id 0000 -chip_id 0x0 // STLINK_CHIPID_UNKNOWN +chip_id 0x0 // STM32_CHIPID_UNKNOWN flash_type 0 // STM32_FLASH_TYPE_UNKNOWN flash_size_reg 0x0 flash_pagesize 0x0 diff --git a/inc/stlink.h b/inc/stlink.h index b387881ae..f6bd5cb0d 100644 --- a/inc/stlink.h +++ b/inc/stlink.h @@ -106,22 +106,22 @@ enum target_state { #define C_BUF_LEN 32 -/* Old flash type definitions */ -// TODO: Transition to the new defines in stm32.h -enum stlink_flash_type { - /* 0 */ STLINK_FLASH_TYPE_UNKNOWN = 0, - /* 1 */ STLINK_FLASH_TYPE_F0, // used by f0, f1 (except f1xl),f3. */ - /* 2 */ STLINK_FLASH_TYPE_F1_XL, // f0 flash with dual bank */ - /* 3 */ STLINK_FLASH_TYPE_F4, // used by f2, f4 */ - /* 4 */ STLINK_FLASH_TYPE_F7, - /* 5 */ STLINK_FLASH_TYPE_L0, // l0, l1 */ - /* 6 */ STLINK_FLASH_TYPE_L4, // l4, l4+ */ - /* 7 */ STLINK_FLASH_TYPE_G0, - /* 8 */ STLINK_FLASH_TYPE_G4, - /* 9 */ STLINK_FLASH_TYPE_WB, - /* 10 */ STLINK_FLASH_TYPE_H7, - /* 11 */ STLINK_FLASH_TYPE_MAX, -}; +// /* Old flash type definitions */ +// // TODO: Transition to the new defines in stm32.h +// enum stlink_flash_type { +// /* 0 */ STLINK_FLASH_TYPE_UNKNOWN = 0, +// /* 1 */ STLINK_FLASH_TYPE_F0, // used by f0, f1 (except f1xl),f3. */ +// /* 2 */ STLINK_FLASH_TYPE_F1_XL, // f0 flash with dual bank */ +// /* 3 */ STLINK_FLASH_TYPE_F4, // used by f2, f4 */ +// /* 4 */ STLINK_FLASH_TYPE_F7, +// /* 5 */ STLINK_FLASH_TYPE_L0, // l0, l1 */ +// /* 6 */ STLINK_FLASH_TYPE_L4, // l4, l4+ */ +// /* 7 */ STLINK_FLASH_TYPE_G0, +// /* 8 */ STLINK_FLASH_TYPE_G4, +// /* 9 */ STLINK_FLASH_TYPE_WB, +// /* 10 */ STLINK_FLASH_TYPE_H7, +// /* 11 */ STLINK_FLASH_TYPE_MAX, +// }; struct stlink_reg { uint32_t r[16]; diff --git a/inc/stm32.h b/inc/stm32.h index 280a61107..8dff2a7d7 100644 --- a/inc/stm32.h +++ b/inc/stm32.h @@ -1,7 +1,7 @@ /* * File: stm32.h * - * STM32-specific defines + * STM32-specific defines & identification parametres */ #ifndef STM32_H @@ -32,6 +32,74 @@ enum stm32_flash_type { STM32_FLASH_TYPE_UNDEFINED = 12, // max. value exceeded }; +/* STM32 chip-ids */ +// See DBGMCU_IDCODE register (0xE0042000) in appropriate programming manual +// stm32 chipids, only lower 12 bits... + +enum stm32_chipids { + STM32_CHIPID_UNKNOWN = 0x000, + + STM32_CHIPID_STM32_F1_MD = 0x410, /* medium density */ + STM32_CHIPID_STM32_F2 = 0x411, + STM32_CHIPID_STM32_F1_LD = 0x412, /* low density */ + STM32_CHIPID_STM32_F4 = 0x413, + STM32_CHIPID_STM32_F1_HD = 0x414, /* high density */ + STM32_CHIPID_STM32_L4 = 0x415, + STM32_CHIPID_STM32_L1_MD = 0x416, /* medium density */ + STM32_CHIPID_STM32_L0 = 0x417, + STM32_CHIPID_STM32_F1_CONN = 0x418, /* connectivity line */ + STM32_CHIPID_STM32_F4_HD = 0x419, /* high density */ + STM32_CHIPID_STM32_F1_VL_MD_LD = 0x420, /* value line medium & low density */ + STM32_CHIPID_STM32_F446 = 0x421, + STM32_CHIPID_STM32_F3 = 0x422, + STM32_CHIPID_STM32_F4_LP = 0x423, + STM32_CHIPID_STM32_L0_CAT2 = 0x425, + STM32_CHIPID_STM32_L1_MD_PLUS = 0x427, /* medium density plus */ + STM32_CHIPID_STM32_F1_VL_HD = 0x428, /* value line high density */ + STM32_CHIPID_STM32_L1_CAT2 = 0x429, + STM32_CHIPID_STM32_F1_XLD = 0x430, /* extra low density plus */ + STM32_CHIPID_STM32_F411xx = 0x431, + STM32_CHIPID_STM32_F37x = 0x432, + STM32_CHIPID_STM32_F4_DE = 0x433, + STM32_CHIPID_STM32_F4_DSI = 0x434, + STM32_CHIPID_STM32_L43x_L44x = 0x435, + STM32_CHIPID_STM32_L1_MD_PLUS_HD = 0x436, /* medium density plus & high density */ + STM32_CHIPID_STM32_L152_RE = 0x437, + STM32_CHIPID_STM32_F334 = 0x438, + STM32_CHIPID_STM32_F3xx_SMALL = 0x439, + STM32_CHIPID_STM32_F0 = 0x440, + STM32_CHIPID_STM32_F412 = 0x441, + STM32_CHIPID_STM32_F09x = 0x442, + STM32_CHIPID_STM32_F0xx_SMALL = 0x444, + STM32_CHIPID_STM32_F04 = 0x445, + STM32_CHIPID_STM32_F303_HD = 0x446, /* high density */ + STM32_CHIPID_STM32_L0_CAT5 = 0x447, + STM32_CHIPID_STM32_F0_CAN = 0x448, + STM32_CHIPID_STM32_F7 = 0x449, /* Nucleo F746ZG board */ + STM32_CHIPID_STM32_H74xxx = 0x450, /* RM0433, p.3189 */ + STM32_CHIPID_STM32_F76xxx = 0x451, + STM32_CHIPID_STM32_F72xxx = 0x452, /* Nucleo F722ZE board */ + STM32_CHIPID_STM32_G0_CAT4 = 0x456, /* G051/G061 */ + STM32_CHIPID_STM32_L011 = 0x457, + STM32_CHIPID_STM32_F410 = 0x458, + STM32_CHIPID_STM32_G0_CAT2 = 0x460, /* G070/G071/G081 */ + STM32_CHIPID_STM32_L496x_L4A6x = 0x461, + STM32_CHIPID_STM32_L45x_L46x = 0x462, + STM32_CHIPID_STM32_F413 = 0x463, + STM32_CHIPID_STM32_L41x_L42x = 0x464, + STM32_CHIPID_STM32_G0_CAT1 = 0x466, /* G030/G031/G041 */ + STM32_CHIPID_STM32_G0_CAT3 = 0x467, /* G0B1/G0C1 */ + STM32_CHIPID_STM32_G4_CAT2 = 0x468, /* RM0440, section 46.6.1 "MCU device ID code" */ + STM32_CHIPID_STM32_G4_CAT3 = 0x469, + STM32_CHIPID_STM32_L4Rx = 0x470, /* RM0432, p.2247, found on the STM32L4R9I-DISCO board */ + STM32_CHIPID_STM32_L4PX = 0x471, /* RM0432, p.2247 */ + STM32_CHIPID_STM32_G4_CAT4 = 0x479, + STM32_CHIPID_STM32_H7Ax = 0x480, /* RM0455, p.2863 */ + STM32_CHIPID_STM32_H72x = 0x483, /* RM0468, p.3199 */ + STM32_CHIPID_STM32_WB55 = 0x495, + STM32_CHIPID_STM32_WLE = 0x497, +}; + /* Constant STM32 memory address */ #define STM32_SRAM_BASE ((uint32_t)0x20000000) #define STM32_FLASH_BASE ((uint32_t)0x08000000) @@ -60,76 +128,4 @@ enum stm32_flash_type { #define STM32_F3_OPTION_BYTES_BASE ((uint32_t)0x1ffff800) #define STM32_G4_OPTION_BYTES_BASE ((uint32_t)0x1ffff800) - -/* - * Chip IDs - * See DBGMCU_IDCODE register (0xE0042000) in appropriate programming manual - */ - -// stm32 chipids, only lower 12 bits... - -enum stlink_stm32_chipids { - STLINK_CHIPID_UNKNOWN = 0x000, - - STLINK_CHIPID_STM32_F1_MD = 0x410, /* medium density */ - STLINK_CHIPID_STM32_F2 = 0x411, - STLINK_CHIPID_STM32_F1_LD = 0x412, /* low density */ - STLINK_CHIPID_STM32_F4 = 0x413, - STLINK_CHIPID_STM32_F1_HD = 0x414, /* high density */ - STLINK_CHIPID_STM32_L4 = 0x415, - STLINK_CHIPID_STM32_L1_MD = 0x416, /* medium density */ - STLINK_CHIPID_STM32_L0 = 0x417, - STLINK_CHIPID_STM32_F1_CONN = 0x418, /* connectivity line */ - STLINK_CHIPID_STM32_F4_HD = 0x419, /* high density */ - STLINK_CHIPID_STM32_F1_VL_MD_LD = 0x420, /* value line medium & low density */ - STLINK_CHIPID_STM32_F446 = 0x421, - STLINK_CHIPID_STM32_F3 = 0x422, - STLINK_CHIPID_STM32_F4_LP = 0x423, - STLINK_CHIPID_STM32_L0_CAT2 = 0x425, - STLINK_CHIPID_STM32_L1_MD_PLUS = 0x427, /* medium density plus */ - STLINK_CHIPID_STM32_F1_VL_HD = 0x428, /* value line high density */ - STLINK_CHIPID_STM32_L1_CAT2 = 0x429, - STLINK_CHIPID_STM32_F1_XLD = 0x430, /* extra low density plus */ - STLINK_CHIPID_STM32_F411xx = 0x431, - STLINK_CHIPID_STM32_F37x = 0x432, - STLINK_CHIPID_STM32_F4_DE = 0x433, - STLINK_CHIPID_STM32_F4_DSI = 0x434, - STLINK_CHIPID_STM32_L43x_L44x = 0x435, - STLINK_CHIPID_STM32_L1_MD_PLUS_HD = 0x436, /* medium density plus & high density */ - STLINK_CHIPID_STM32_L152_RE = 0x437, - STLINK_CHIPID_STM32_F334 = 0x438, - STLINK_CHIPID_STM32_F3xx_SMALL = 0x439, - STLINK_CHIPID_STM32_F0 = 0x440, - STLINK_CHIPID_STM32_F412 = 0x441, - STLINK_CHIPID_STM32_F09x = 0x442, - STLINK_CHIPID_STM32_F0xx_SMALL = 0x444, - STLINK_CHIPID_STM32_F04 = 0x445, - STLINK_CHIPID_STM32_F303_HD = 0x446, /* high density */ - STLINK_CHIPID_STM32_L0_CAT5 = 0x447, - STLINK_CHIPID_STM32_F0_CAN = 0x448, - STLINK_CHIPID_STM32_F7 = 0x449, /* Nucleo F746ZG board */ - STLINK_CHIPID_STM32_H74xxx = 0x450, /* RM0433, p.3189 */ - STLINK_CHIPID_STM32_F76xxx = 0x451, - STLINK_CHIPID_STM32_F72xxx = 0x452, /* Nucleo F722ZE board */ - STLINK_CHIPID_STM32_G0_CAT4 = 0x456, /* G051/G061 */ - STLINK_CHIPID_STM32_L011 = 0x457, - STLINK_CHIPID_STM32_F410 = 0x458, - STLINK_CHIPID_STM32_G0_CAT2 = 0x460, /* G070/G071/G081 */ - STLINK_CHIPID_STM32_L496x_L4A6x = 0x461, - STLINK_CHIPID_STM32_L45x_L46x = 0x462, - STLINK_CHIPID_STM32_F413 = 0x463, - STLINK_CHIPID_STM32_L41x_L42x = 0x464, - STLINK_CHIPID_STM32_G0_CAT1 = 0x466, /* G030/G031/G041 */ - STLINK_CHIPID_STM32_G0_CAT3 = 0x467, /* G0B1/G0C1 */ - STLINK_CHIPID_STM32_G4_CAT2 = 0x468, /* RM0440, section 46.6.1 "MCU device ID code" */ - STLINK_CHIPID_STM32_G4_CAT3 = 0x469, - STLINK_CHIPID_STM32_L4Rx = 0x470, /* RM0432, p.2247, found on the STM32L4R9I-DISCO board */ - STLINK_CHIPID_STM32_L4PX = 0x471, /* RM0432, p.2247 */ - STLINK_CHIPID_STM32_G4_CAT4 = 0x479, - STLINK_CHIPID_STM32_H7Ax = 0x480, /* RM0455, p.2863 */ - STLINK_CHIPID_STM32_H72x = 0x483, /* RM0468, p.3199 */ - STLINK_CHIPID_STM32_WB55 = 0x495, - STLINK_CHIPID_STM32_WLE = 0x497, -}; - #endif // STM32_H diff --git a/src/common.c b/src/common.c index e73955f31..5a6d0d86b 100644 --- a/src/common.c +++ b/src/common.c @@ -334,7 +334,7 @@ #define FLASH_H7_CR_SER 2 #define FLASH_H7_CR_BER 3 #define FLASH_H7_CR_PSIZE 4 -#define FLASH_H7_CR_START(chipid) (chipid == STLINK_CHIPID_STM32_H7Ax ? 5 : 7) +#define FLASH_H7_CR_START(chipid) (chipid == STM32_CHIPID_STM32_H7Ax ? 5 : 7) #define FLASH_H7_CR_SNB 8 #define FLASH_H7_CR_SNB_MASK 0x700 @@ -441,16 +441,16 @@ uint16_t read_uint16(const unsigned char *c, const int pt) { static uint32_t get_stm32l0_flash_base(stlink_t *sl) { switch (sl->chip_id) { - case STLINK_CHIPID_STM32_L0: - case STLINK_CHIPID_STM32_L0_CAT5: - case STLINK_CHIPID_STM32_L0_CAT2: - case STLINK_CHIPID_STM32_L011: + case STM32_CHIPID_STM32_L0: + case STM32_CHIPID_STM32_L0_CAT5: + case STM32_CHIPID_STM32_L0_CAT2: + case STM32_CHIPID_STM32_L011: return (STM32L0_FLASH_REGS_ADDR); - case STLINK_CHIPID_STM32_L1_CAT2: - case STLINK_CHIPID_STM32_L1_MD: - case STLINK_CHIPID_STM32_L1_MD_PLUS: - case STLINK_CHIPID_STM32_L1_MD_PLUS_HD: + case STM32_CHIPID_STM32_L1_CAT2: + case STM32_CHIPID_STM32_L1_MD: + case STM32_CHIPID_STM32_L1_MD_PLUS: + case STM32_CHIPID_STM32_L1_MD_PLUS_HD: return (STM32L_FLASH_REGS_ADDR); default: @@ -1622,14 +1622,14 @@ int stlink_load_device_params(stlink_t *sl) { flash_size = flash_size & 0xffff; - if ((sl->chip_id == STLINK_CHIPID_STM32_L1_MD || - sl->chip_id == STLINK_CHIPID_STM32_F1_VL_MD_LD || - sl->chip_id == STLINK_CHIPID_STM32_L1_MD_PLUS) && + if ((sl->chip_id == STM32_CHIPID_STM32_L1_MD || + sl->chip_id == STM32_CHIPID_STM32_F1_VL_MD_LD || + sl->chip_id == STM32_CHIPID_STM32_L1_MD_PLUS) && (flash_size == 0)) { sl->flash_size = 128 * 1024; - } else if (sl->chip_id == STLINK_CHIPID_STM32_L1_CAT2) { + } else if (sl->chip_id == STM32_CHIPID_STM32_L1_CAT2) { sl->flash_size = (flash_size & 0xff) * 1024; - } else if ((sl->chip_id & 0xFFF) == STLINK_CHIPID_STM32_L1_MD_PLUS_HD) { + } else if ((sl->chip_id & 0xFFF) == STM32_CHIPID_STM32_L1_MD_PLUS_HD) { // 0 is 384k and 1 is 256k if (flash_size == 0) { sl->flash_size = 384 * 1024; @@ -1651,12 +1651,12 @@ int stlink_load_device_params(stlink_t *sl) { // medium and low devices have the same chipid. ram size depends on flash // size. STM32F100xx datasheet Doc ID 16455 Table 2 - if (sl->chip_id == STLINK_CHIPID_STM32_F1_VL_MD_LD && + if (sl->chip_id == STM32_CHIPID_STM32_F1_VL_MD_LD && sl->flash_size < 64 * 1024) { sl->sram_size = 0x1000; } - if (sl->chip_id == STLINK_CHIPID_STM32_G4_CAT3) { + if (sl->chip_id == STM32_CHIPID_STM32_G4_CAT3) { uint32_t flash_optr; stlink_read_debug32(sl, STM32Gx_FLASH_OPTR, &flash_optr); @@ -2706,9 +2706,9 @@ uint32_t calculate_L4_page(stlink_t *sl, uint32_t flashaddr) { stlink_read_debug32(sl, STM32L4_FLASH_OPTR, &flashopt); flashaddr -= STM32_FLASH_BASE; - if (sl->chip_id == STLINK_CHIPID_STM32_L4 || - sl->chip_id == STLINK_CHIPID_STM32_L496x_L4A6x || - sl->chip_id == STLINK_CHIPID_STM32_L4Rx) { + if (sl->chip_id == STM32_CHIPID_STM32_L4 || + sl->chip_id == STM32_CHIPID_STM32_L496x_L4A6x || + sl->chip_id == STM32_CHIPID_STM32_L4Rx) { // this chip use dual banked flash if (flashopt & (uint32_t)(1lu << STM32L4_FLASH_OPTR_DUALBANK)) { uint32_t banksize = (uint32_t)sl->flash_size / 2; @@ -2726,16 +2726,16 @@ uint32_t calculate_L4_page(stlink_t *sl, uint32_t flashaddr) { } uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr) { - if ((sl->chip_id == STLINK_CHIPID_STM32_F2) || - (sl->chip_id == STLINK_CHIPID_STM32_F4) || - (sl->chip_id == STLINK_CHIPID_STM32_F4_DE) || - (sl->chip_id == STLINK_CHIPID_STM32_F4_LP) || - (sl->chip_id == STLINK_CHIPID_STM32_F4_HD) || - (sl->chip_id == STLINK_CHIPID_STM32_F411xx) || - (sl->chip_id == STLINK_CHIPID_STM32_F446) || - (sl->chip_id == STLINK_CHIPID_STM32_F4_DSI) || - (sl->chip_id == STLINK_CHIPID_STM32_F72xxx) || - (sl->chip_id == STLINK_CHIPID_STM32_F412)) { + if ((sl->chip_id == STM32_CHIPID_STM32_F2) || + (sl->chip_id == STM32_CHIPID_STM32_F4) || + (sl->chip_id == STM32_CHIPID_STM32_F4_DE) || + (sl->chip_id == STM32_CHIPID_STM32_F4_LP) || + (sl->chip_id == STM32_CHIPID_STM32_F4_HD) || + (sl->chip_id == STM32_CHIPID_STM32_F411xx) || + (sl->chip_id == STM32_CHIPID_STM32_F446) || + (sl->chip_id == STM32_CHIPID_STM32_F4_DSI) || + (sl->chip_id == STM32_CHIPID_STM32_F72xxx) || + (sl->chip_id == STM32_CHIPID_STM32_F412)) { uint32_t sector = calculate_F4_sectornum(flashaddr); if (sector >= 12) { @@ -2749,8 +2749,8 @@ uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr) { } else { sl->flash_pgsz = 0x20000; } - } else if (sl->chip_id == STLINK_CHIPID_STM32_F7 || - sl->chip_id == STLINK_CHIPID_STM32_F76xxx) { + } else if (sl->chip_id == STM32_CHIPID_STM32_F7 || + sl->chip_id == STM32_CHIPID_STM32_F76xxx) { uint32_t sector = calculate_F7_sectornum(flashaddr); if (sector < 4) { @@ -2785,11 +2785,11 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { unlock_flash_if(sl); // select the page to erase - if ((sl->chip_id == STLINK_CHIPID_STM32_L4) || - (sl->chip_id == STLINK_CHIPID_STM32_L43x_L44x) || - (sl->chip_id == STLINK_CHIPID_STM32_L45x_L46x) || - (sl->chip_id == STLINK_CHIPID_STM32_L496x_L4A6x) || - (sl->chip_id == STLINK_CHIPID_STM32_L4Rx)) { + if ((sl->chip_id == STM32_CHIPID_STM32_L4) || + (sl->chip_id == STM32_CHIPID_STM32_L43x_L44x) || + (sl->chip_id == STM32_CHIPID_STM32_L45x_L46x) || + (sl->chip_id == STM32_CHIPID_STM32_L496x_L4A6x) || + (sl->chip_id == STM32_CHIPID_STM32_L4Rx)) { // calculate the actual bank+page from the address uint32_t page = calculate_L4_page(sl, flashaddr); @@ -2797,8 +2797,8 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { stlink_calculate_pagesize(sl, flashaddr)); write_flash_cr_bker_pnb(sl, page); - } else if (sl->chip_id == STLINK_CHIPID_STM32_F7 || - sl->chip_id == STLINK_CHIPID_STM32_F76xxx) { + } else if (sl->chip_id == STM32_CHIPID_STM32_F7 || + sl->chip_id == STM32_CHIPID_STM32_F76xxx) { // calculate the actual page from the address uint32_t sector = calculate_F7_sectornum(flashaddr); @@ -2982,7 +2982,7 @@ int stlink_erase_flash_mass(stlink_t *sl) { unlock_flash_if(sl); if (sl->flash_type == STM32_FLASH_TYPE_H7 && - sl->chip_id != STLINK_CHIPID_STM32_H7Ax) { + sl->chip_id != STM32_CHIPID_STM32_H7Ax) { // set parallelism write_flash_cr_psiz(sl, 3 /*64it*/, BANK_1); if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { @@ -3260,7 +3260,7 @@ int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { set_flash_cr_pg(sl, BANK_2); } - if (sl->chip_id != STLINK_CHIPID_STM32_H7Ax) { + if (sl->chip_id != STM32_CHIPID_STM32_H7Ax) { // set parallelism write_flash_cr_psiz(sl, 3 /*64it*/, BANK_1); if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { @@ -4357,17 +4357,17 @@ int stlink_read_option_bytes32(stlink_t *sl, uint32_t *option_byte) { } switch (sl->chip_id) { - case STLINK_CHIPID_STM32_F2: + case STM32_CHIPID_STM32_F2: return stlink_read_option_bytes_f2(sl, option_byte); - case STLINK_CHIPID_STM32_F4: - case STLINK_CHIPID_STM32_F446: + case STM32_CHIPID_STM32_F4: + case STM32_CHIPID_STM32_F446: return stlink_read_option_bytes_f4(sl, option_byte); - case STLINK_CHIPID_STM32_F76xxx: + case STM32_CHIPID_STM32_F76xxx: return stlink_read_option_bytes_f7(sl, option_byte); - case STLINK_CHIPID_STM32_G0_CAT1: - case STLINK_CHIPID_STM32_G0_CAT2: - case STLINK_CHIPID_STM32_G4_CAT2: - case STLINK_CHIPID_STM32_G4_CAT3: + case STM32_CHIPID_STM32_G0_CAT1: + case STM32_CHIPID_STM32_G0_CAT2: + case STM32_CHIPID_STM32_G4_CAT2: + case STM32_CHIPID_STM32_G4_CAT3: return stlink_read_option_bytes_Gx(sl, option_byte); default: return stlink_read_option_bytes_generic(sl, option_byte); diff --git a/src/st-trace/trace.c b/src/st-trace/trace.c index 46304d7d9..28a585071 100644 --- a/src/st-trace/trace.c +++ b/src/st-trace/trace.c @@ -540,7 +540,7 @@ int main(int argc, char **argv) { stlink->verbose = settings.logging_level; - if (stlink->chip_id == STLINK_CHIPID_UNKNOWN) { + if (stlink->chip_id == STM32_CHIPID_UNKNOWN) { ELOG("Your stlink is not connected to a device\n"); if (!settings.force) return APP_RESULT_STLINK_MISSING_DEVICE; diff --git a/src/st-util/gdb-server.c b/src/st-util/gdb-server.c index 81c0aa83a..4babef0cc 100644 --- a/src/st-util/gdb-server.c +++ b/src/st-util/gdb-server.c @@ -226,7 +226,7 @@ int main(int argc, char** argv) { sl = stlink_open_usb(state.logging_level, state.connect_mode, state.serialnumber, state.freq); if (sl == NULL) { return(1); } - if (sl->chip_id == STLINK_CHIPID_UNKNOWN) { + if (sl->chip_id == STM32_CHIPID_UNKNOWN) { ELOG("Unsupported Target (Chip ID is %#010x, Core ID is %#010x).\n", sl->chip_id, sl->core_id); return(1); } @@ -553,39 +553,39 @@ char* make_memory_map(stlink_t *sl) { char* map = malloc(sz); map[0] = '\0'; - if (sl->chip_id == STLINK_CHIPID_STM32_F4 || - sl->chip_id == STLINK_CHIPID_STM32_F446 || - sl->chip_id == STLINK_CHIPID_STM32_F411xx) { + if (sl->chip_id == STM32_CHIPID_STM32_F4 || + sl->chip_id == STM32_CHIPID_STM32_F446 || + sl->chip_id == STM32_CHIPID_STM32_F411xx) { strcpy(map, memory_map_template_F4); - } else if (sl->chip_id == STLINK_CHIPID_STM32_F4_DE) { + } else if (sl->chip_id == STM32_CHIPID_STM32_F4_DE) { strcpy(map, memory_map_template_F4_DE); } else if (sl->core_id == STM32F7_CORE_ID) { snprintf(map, sz, memory_map_template_F7, (unsigned int)sl->sram_size); - } else if (sl->chip_id == STLINK_CHIPID_STM32_H74xxx) { + } else if (sl->chip_id == STM32_CHIPID_STM32_H74xxx) { snprintf(map, sz, memory_map_template_H7, (unsigned int)sl->flash_size, (unsigned int)sl->flash_pgsz); - } else if (sl->chip_id == STLINK_CHIPID_STM32_F4_HD) { + } else if (sl->chip_id == STM32_CHIPID_STM32_F4_HD) { strcpy(map, memory_map_template_F4_HD); - } else if (sl->chip_id == STLINK_CHIPID_STM32_F2) { + } else if (sl->chip_id == STM32_CHIPID_STM32_F2) { snprintf(map, sz, memory_map_template_F2, (unsigned int)sl->flash_size, (unsigned int)sl->sram_size, (unsigned int)sl->flash_size - 0x20000, (unsigned int)sl->sys_base, (unsigned int)sl->sys_size); - } else if ((sl->chip_id == STLINK_CHIPID_STM32_L4) || - (sl->chip_id == STLINK_CHIPID_STM32_L43x_L44x) || - (sl->chip_id == STLINK_CHIPID_STM32_L45x_L46x)) { + } else if ((sl->chip_id == STM32_CHIPID_STM32_L4) || + (sl->chip_id == STM32_CHIPID_STM32_L43x_L44x) || + (sl->chip_id == STM32_CHIPID_STM32_L45x_L46x)) { snprintf(map, sz, memory_map_template_L4, (unsigned int)sl->flash_size, (unsigned int)sl->flash_size); - } else if (sl->chip_id == STLINK_CHIPID_STM32_L496x_L4A6x) { + } else if (sl->chip_id == STM32_CHIPID_STM32_L496x_L4A6x) { snprintf(map, sz, memory_map_template_L496, (unsigned int)sl->flash_size, (unsigned int)sl->flash_size); - } else if (sl->chip_id == STLINK_CHIPID_STM32_H72x) { + } else if (sl->chip_id == STM32_CHIPID_STM32_H72x) { snprintf(map, sz, memory_map_template_H72x3x, (unsigned int)sl->flash_size, (unsigned int)sl->flash_pgsz); @@ -1847,7 +1847,7 @@ int serve(stlink_t *sl, st_state_t *st) { stlink_close(sl); sl = stlink_open_usb(st->logging_level, st->connect_mode, st->serialnumber, st->freq); - if (sl == NULL || sl->chip_id == STLINK_CHIPID_UNKNOWN) { cleanup(0); } + if (sl == NULL || sl->chip_id == STM32_CHIPID_UNKNOWN) { cleanup(0); } connected_stlink = sl; diff --git a/src/stlink-lib/chipid_db_old.h b/src/stlink-lib/chipid_db_old.h deleted file mode 100644 index 6578e35be..000000000 --- a/src/stlink-lib/chipid_db_old.h +++ /dev/null @@ -1,877 +0,0 @@ -// This is the old chipid "database". -// It is kept here for now to be able to compare the -// result between the "old code" and the "new code". -// For now if you need to change something, please -// change it both here and in the corresponding -// config/chips/*.chip file. - -//static struct stlink_chipid_params devices[] = { - { - // STM32F03x - // RM0091 - .chip_id = STLINK_CHIPID_STM32_F0xx_SMALL, - .dev_type = "F03x", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) - .flash_pagesize = 0x400, // Page sizes listed in Table 4 - .sram_size = 0x1000, // "SRAM" byte size in hex from Table 2 - .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2 - .bootrom_size = 0xC00, // "System memory" byte size in hex from Table 2 - .option_base = STM32_F0_OPTION_BYTES_BASE, - .option_size = 16, - }, - { - // STM32F04x - // RM0091 - .chip_id = STLINK_CHIPID_STM32_F04, - .dev_type = "F04x", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) - .flash_pagesize = 0x400, // Page sizes listed in Table 4 - .sram_size = 0x1800, // "SRAM" byte size in hex from Table 2 - .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2 - .bootrom_size = 0xC00, // "System memory" byte size in hex from Table 2 - .option_base = STM32_F0_OPTION_BYTES_BASE, - .option_size = 16, - }, - { - // STM32F05x - // RM0091 - .chip_id = STLINK_CHIPID_STM32_F0, - .dev_type = "F05x", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) - .flash_pagesize = 0x400, // Page sizes listed in Table 4 - .sram_size = 0x2000, // "SRAM" byte size in hex from Table 2 - .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2 - .bootrom_size = 0xC00, // "System memory" byte size in hex from Table 2 - .option_base = STM32_F0_OPTION_BYTES_BASE, - .option_size = 16, - }, - { - // STM32F07x - // RM0091 - .chip_id = STLINK_CHIPID_STM32_F0_CAN, - .dev_type = "F07x", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) - .flash_pagesize = 0x800, // Page sizes listed in Table 4 - .sram_size = 0x4000, // "SRAM" byte size in hex from Table 2 - .bootrom_base = 0x1fffC800, // "System memory" starting address from Table 2 - .bootrom_size = 0x3000, // "System memory" byte size in hex from Table 2 - .option_base = STM32_F0_OPTION_BYTES_BASE, - .option_size = 16, - }, - { - // STM32F09x - // RM0091 - .chip_id = STLINK_CHIPID_STM32_F09x, - .dev_type = "F09x", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) - .flash_pagesize = 0x800, // Page sizes listed in Table 4 (pg 56) - .sram_size = 0x8000, // "SRAM" byte size in hex from Table 2 (pg 50) - .bootrom_base = 0x1fffd800, // "System memory" starting address from Table 2 - .bootrom_size = 0x2000, // "System memory" byte size in hex from Table 2 - .option_base = STM32_F0_OPTION_BYTES_BASE, - .option_size = 16, - }, - { - // STM32F1xx low- and medium-density value line devices - // RM0041 - .chip_id = STLINK_CHIPID_STM32_F1_VL_MD_LD, - .dev_type = "F1xx Value Line", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7e0, - .flash_pagesize = 0x400, - .sram_size = 0x2000, // 0x1000 for low density devices - .bootrom_base = 0x1ffff000, - .bootrom_size = 0x800, - .option_base = STM32_F0_OPTION_BYTES_BASE, - .option_size = 16, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32F1xx high-density value line devices - // RM0041 - .chip_id = STLINK_CHIPID_STM32_F1_VL_HD, - .dev_type = "F1xx High-density value line", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7e0, - .flash_pagesize = 0x800, - .sram_size = 0x8000, - .bootrom_base = 0x1ffff000, - .bootrom_size = 0x800, - .option_base = STM32_F0_OPTION_BYTES_BASE, - .option_size = 16, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32F1xx low-density devices - // RM0008 - .chip_id = STLINK_CHIPID_STM32_F1_LD, - .dev_type = "F1 Low-density device", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7e0, - .flash_pagesize = 0x400, - .sram_size = 0x2800, - .bootrom_base = 0x1ffff000, - .bootrom_size = 0x800, - .option_base = STM32_F0_OPTION_BYTES_BASE, - .option_size = 16, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32F1xx medium-density devices - // RM0008 - .chip_id = STLINK_CHIPID_STM32_F1_MD, - .dev_type = "F1xx Medium-density", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7e0, - .flash_pagesize = 0x400, - .sram_size = 0x5000, - .bootrom_base = 0x1ffff000, // 2.3.3 "Embedded Flash memory" - .bootrom_size = 0x800, - .option_base = STM32_F0_OPTION_BYTES_BASE, - .option_size = 16, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32F1xx high-density devices - // RM0008 - .chip_id = STLINK_CHIPID_STM32_F1_HD, - .dev_type = "F1xx High-density", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7e0, - .flash_pagesize = 0x800, - .sram_size = 0x10000, - .bootrom_base = 0x1ffff000, - .bootrom_size = 0x800, - .option_base = STM32_F0_OPTION_BYTES_BASE, - .option_size = 16, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32F1xx XL-density devices - // RM0008 - .chip_id = STLINK_CHIPID_STM32_F1_XLD, - .dev_type = "F1xx XL-density", - .flash_type = STLINK_FLASH_TYPE_F1_XL, - .flash_size_reg = 0x1ffff7e0, - .flash_pagesize = 0x800, - .sram_size = 0x18000, - .bootrom_base = 0x1fffe000, - .bootrom_size = 0x1800, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32F1xx connectivity devices - // RM0008 - .chip_id = STLINK_CHIPID_STM32_F1_CONN, - .dev_type = "F1xx CL", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7e0, - .flash_pagesize = 0x800, - .sram_size = 0x10000, - .bootrom_base = 0x1fffb000, - .bootrom_size = 0x4800, - .option_base = STM32_F0_OPTION_BYTES_BASE, - .option_size = 16, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32F205xx, STM32F207xx, STM32F215xx, STM32F217xx - // RM0033 (rev 5) - .chip_id = STLINK_CHIPID_STM32_F2, - .dev_type = "F2xx", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1fff7a22, - .flash_pagesize = 0x20000, - .sram_size = 0x20000, - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7800, - .option_base = 0x1FFFC000, - .option_size = 4, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32F301x6/8, STM32F302x6x8, STM32F318x8 - // RM0366, RM0365 - .chip_id = STLINK_CHIPID_STM32_F3xx_SMALL, - .dev_type = "F301/F302/F318", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7cc, - .flash_pagesize = 0x800, - .sram_size = 0xa000, - .bootrom_base = 0x1fffd800, - .bootrom_size = 0x2000, - .option_base = STM32_F0_OPTION_BYTES_BASE, - .option_size = 16, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32F302xBxC, STM32F303xB/C, STM32F358 - // RM0316, RM0365 - .chip_id = STLINK_CHIPID_STM32_F3, - .dev_type = "F302/F303/F358", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7cc, - .flash_pagesize = 0x800, - .sram_size = 0xa000, - .bootrom_base = 0x1ffff000, - .bootrom_size = 0x800, - .option_base = STM32_F0_OPTION_BYTES_BASE, - .option_size = 16, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32F302xD/E, STM32F303xD/E, STM32F398xE, - // RM0316 (rev 5), RM0365 - .chip_id = STLINK_CHIPID_STM32_F303_HD, - .dev_type = "F303 high density", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7cc, // 34.2.1 Flash size data register - .flash_pagesize = 0x800, // 4.2.1 Flash memory organization - .sram_size = 0x10000, // 3.3 Embedded SRAM - .bootrom_base = 0x1fffd800, // 3.3.2 / Table 4 System Memory - .bootrom_size = 0x2000, - .option_base = STM32_F0_OPTION_BYTES_BASE, - .option_size = 16, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32F303x6/8, STM32F328, STM32F334 - // RM0364, RM0316 - .chip_id = STLINK_CHIPID_STM32_F334, - .dev_type = "F303/F328/F334", // (RM0316 sec 33.6.1) - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7cc, - .flash_pagesize = 0x800, - .sram_size = 0x3000, - .bootrom_base = 0x1fffd800, - .bootrom_size = 0x2000, - .option_base = STM32_F0_OPTION_BYTES_BASE, - .option_size = 16, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32F373Cx/Rx/Vx, STM32F378Cx/Rx/Vx - // RM0313 - .chip_id = STLINK_CHIPID_STM32_F37x, - .dev_type = "F37x", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7cc, - .flash_pagesize = 0x800, - .sram_size = 0xa000, - .bootrom_base = 0x1ffff000, - .bootrom_size = 0x800, - .option_base = STM32_F0_OPTION_BYTES_BASE, - .option_size = 16, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - .chip_id = STLINK_CHIPID_STM32_F4_LP, - .dev_type = "F401xB/C", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1FFF7A22, - .flash_pagesize = 0x4000, - .sram_size = 0x10000, - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7800, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - .chip_id = STLINK_CHIPID_STM32_F4_DE, - .dev_type = "F401xD/E", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1FFF7A22, - .flash_pagesize = 0x4000, - .sram_size = 0x18000, - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7800, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32F410 - // RM0401 - .chip_id = STLINK_CHIPID_STM32_F410, - .dev_type = "F410", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1fff7a22, - .flash_pagesize = 0x4000, - .sram_size = 0x8000, - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7800, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - .chip_id = STLINK_CHIPID_STM32_F411xx, - .dev_type = "F411xC/E", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1FFF7A22, - .flash_pagesize = 0x4000, - .sram_size = 0x20000, - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7800, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32F412 - // RM0402 - .chip_id = STLINK_CHIPID_STM32_F412, - .dev_type = "F412", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1FFF7A22, // "Flash size data register" (pg1135) - .flash_pagesize = 0x4000, // Table 5. Flash module organization ? - .sram_size = 0x40000, // "SRAM" byte size in hex from Table 4 - .bootrom_base = 0x1FFF0000, // "System memory" starting address from Table 4 - .bootrom_size = 0x7800, // "System memory" byte size in hex from Table 4 - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32F413/F423 - // RM0430 (rev 2) - .chip_id = STLINK_CHIPID_STM32_F413, - .dev_type = "F413/F423", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1FFF7A22, // "Flash size data register" Section 35.2 - .flash_pagesize = 0x4000, // Table 5. Flash module organization (variable sector - // sizes, but 0x4000 is smallest) - .sram_size = 0x50000, // "SRAM" byte size in hex from Figure 2 (Table 4 - // only says 0x40000) - .bootrom_base = 0x1FFF0000, // "System memory" starting address from Table 4 - .bootrom_size = 0x7800, // "System memory" byte size in hex from Table 4 - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32F42x/F43x - // RM0090 (rev 2) - .chip_id = STLINK_CHIPID_STM32_F4_HD, - .dev_type = "F42x/F43x", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1FFF7A22, - .flash_pagesize = 0x4000, - .sram_size = 0x40000, - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7800, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32F446x family - // RM0390 - .chip_id = STLINK_CHIPID_STM32_F446, - .dev_type = "F446", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1fff7a22, - .flash_pagesize = 0x20000, - .sram_size = 0x20000, - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7800, - .option_base = 0x1FFFC000, - .option_size = 4, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32F46x/F47x - // RM0090 (rev 2) - .chip_id = STLINK_CHIPID_STM32_F4_DSI, - .dev_type = "F46x/F47x", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1FFF7A22, - .flash_pagesize = 0x4000, - .sram_size = 0x40000, - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7800, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32F4x5/F4x7 - // RM0090 (rev 2) - .chip_id = STLINK_CHIPID_STM32_F4, - .dev_type = "F4x5/F4x7", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1FFF7A22, - .flash_pagesize = 0x4000, - .sram_size = 0x30000, - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7800, - .option_base = STM32_F4_OPTION_BYTES_BASE, - .option_size = 4, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32F72x/F73x - // RM0431 - .chip_id = STLINK_CHIPID_STM32_F72xxx, - .dev_type = "F72x/F73x", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1ff07a22, // section 35.2 - .flash_pagesize = 0x800, // No flash pages - .sram_size = 0x40000, // "SRAM" byte size in hex from DS Fig 24 - .bootrom_base = 0x00100000, // "System memory" starting address from DS Fig 24 - .bootrom_size = 0xEDC0, // "System memory" byte size in hex from DS Fig 24 - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32F74x/F75x - // RM0385, DS10916 - .chip_id = STLINK_CHIPID_STM32_F7, - .dev_type = "F74x/F75x", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1ff0f442, // section 41.2 - .flash_pagesize = 0x800, // No flash pages - .sram_size = 0x50000, // "SRAM" byte size in hex from DS Fig 18 - .bootrom_base = 0x00100000, // "System memory" starting address from DS Fig 18 - .bootrom_size = 0xEDC0, // "System memory" byte size in hex from DS Fig 18 - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32F76x/F77x - // RM0410 - .chip_id = STLINK_CHIPID_STM32_F76xxx, - .dev_type = "F76x/F77x", - .flash_type = STLINK_FLASH_TYPE_F7, - .flash_size_reg = 0x1ff0f442, // section 45.2 - .flash_pagesize = 0x800, // No flash pages - .sram_size = 0x80000, // "SRAM" byte size in hex from - .bootrom_base = 0x00200000, // "System memory" starting address from - .bootrom_size = 0xEDC0, - .option_base = STM32_F7_OPTION_BYTES_BASE, /* Used for reading back the option - bytes, writing uses FLASH_F7_OPTCR - and FLASH_F7_OPTCR1 */ - .option_size = 0x20, - .flags = CHIP_F_HAS_DUAL_BANK | CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32G030/031/041 - // RM0454, RM0444 - .chip_id = STLINK_CHIPID_STM32_G0_CAT1, - .dev_type = "G03x/G04x", - .flash_type = STLINK_FLASH_TYPE_G0, - .flash_size_reg = 0x1FFF75E0, // Section 38.2 - .flash_pagesize = 0x800, // 2k (sec 3.2) - .sram_size = 0x2000, // 8k (sec 2.3) - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x2000, // 8k (sec 2.2.2 table 3) - .option_base = STM32_G0_OPTION_BYTES_BASE, - .option_size = 4, - }, - { - // STM32G051/G061 - // RM0444 - .chip_id = STLINK_CHIPID_STM32_G0_CAT4, - .dev_type = "G05x/G06x", - .flash_type = STLINK_FLASH_TYPE_G0, - .flash_size_reg = 0x1FFF75E0, // Section 38.2 - .flash_pagesize = 0x800, // 2k (sec 3.2) - .sram_size = 0x9000, // 36k (sec 2.3) - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7000, // 28k (sec 2.2.2 table 2) - .option_base = STM32_G0_OPTION_BYTES_BASE, - .option_size = 4, - }, - { - // STM32G071/081 - // RM0444 - .chip_id = STLINK_CHIPID_STM32_G0_CAT2, - .dev_type = "G07x/G08x", - .flash_type = STLINK_FLASH_TYPE_G0, - .flash_size_reg = 0x1FFF75E0, // Section 38.2 - .flash_pagesize = 0x800, // 2k (sec 3.2) - .sram_size = 0x9000, // 36k (sec 2.3) - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7000, // 28k (sec 2.2.2 table 2) - .option_base = STM32_G0_OPTION_BYTES_BASE, - .option_size = 4, - }, - { - // STM32G0B1/G0C1 - // RM0444 - .chip_id = STLINK_CHIPID_STM32_G0_CAT3, - .dev_type = "G0Bx/G0Cx", - .flash_type = STLINK_FLASH_TYPE_G0, - .flash_size_reg = 0x1FFF75E0, // Section 38.2 - .flash_pagesize = 0x800, // 2k (sec 3.2) - .sram_size = 0x9000, // 36k (sec 2.3) - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7000, // 28k (sec 2.2.2 table 2) - .option_base = STM32_G0_OPTION_BYTES_BASE, - .option_size = 4, - .flags = CHIP_F_HAS_DUAL_BANK, - }, - { - // STM32G431/441 - // RM0440 - .chip_id = STLINK_CHIPID_STM32_G4_CAT2, - .dev_type = "G43x/G44x", - .flash_type = STLINK_FLASH_TYPE_G4, - .flash_size_reg = 0x1FFF75E0, // Section 47.2 - .flash_pagesize = 0x800, // 2k (sec 3.3.1) - // SRAM1 is 16k at 0x20000000 - // SRAM2 is 6k at 0x20014000 - // SRAM3/CCM is 10k at 0x10000000, aliased at 0x20018000 - .sram_size = 0x8000, // 32k (sec 2.4) - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7000, // 28k (table 2) - .option_base = STM32_G4_OPTION_BYTES_BASE, - .option_size = 4, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32G471/473/474/483/484 - // RM0440 - .chip_id = STLINK_CHIPID_STM32_G4_CAT3, - .dev_type = "G47x/G48x", - .flash_type = STLINK_FLASH_TYPE_G4, - .flash_size_reg = 0x1FFF75E0, // Section 47.2 - .flash_pagesize = 0x800, // 2k (sec 3.3.1) - // SRAM1 is 80k at 0x20000000 - // SRAM2 is 16k at 0x20014000 - // SRAM3/CCM is 32k at 0x10000000, aliased at 0x20018000 - .sram_size = 0x20000, // 128k (sec 2.4) - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7000, // 28k (table 2) - .option_base = STM32_G4_OPTION_BYTES_BASE, - .option_size = 4, - .flags = CHIP_F_HAS_DUAL_BANK | CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32G491/G4A1 - // RM0440 - .chip_id = STLINK_CHIPID_STM32_G4_CAT4, - .dev_type = "G49x/G4Ax", - .flash_type = STLINK_FLASH_TYPE_G4, - .flash_size_reg = 0x1FFF75E0, // Section 47.2 - .flash_pagesize = 0x800, // 2k (sec 3.3.1) - // SRAM1 is 80k at 0x20000000 - // SRAM2 is 16k at 0x20014000 - // SRAM3/CCM is 32k at 0x10000000, aliased at 0x20018000 - .sram_size = 0x1C000, // 112k (sec 2.4) - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7000, // 28k (table 2) - .option_base = STM32_G4_OPTION_BYTES_BASE, - .option_size = 4, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32H7A3/7B3 - // RM0455 - .chip_id = STLINK_CHIPID_STM32_H7Ax, - .dev_type = "H7Ax/H7Bx", - .flash_type = STLINK_FLASH_TYPE_H7, - .flash_size_reg = 0x08FFF80C, // "Flash size register" (p.2949) - .flash_pagesize = 0x2000, // 8k sector (p.146) - .sram_size = 0x20000, // 128k "DTCM" (Figure 1) - .bootrom_base = 0x1FF00000, // "System memory" starting address (Table 12-14) - .bootrom_size = 0x20000, // "System memory" byte size in hex splitted to - // two banks (Table 12-14) - .option_base = STM32_H7_OPTION_BYTES_BASE, - .option_size = 44, - .flags = CHIP_F_HAS_DUAL_BANK | CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32H72x/H73x - // RM0468 - .chip_id = STLINK_CHIPID_STM32_H72x, - .dev_type = "H72x/H73x", - .flash_type = STLINK_FLASH_TYPE_H7, - .flash_size_reg = 0x1FF1E880, // "Flash size register" (p.3286) - .flash_pagesize = 0x20000, // 128k sector (p.152) - .sram_size = 0x20000, // 128k "DTCM" (Figure 1) - .bootrom_base = 0x1FF00000, // "System memory" starting address (Table 6) - .bootrom_size = 0x20000, // "System memory" byte size in hex (Table 6) - .option_base = STM32_H7_OPTION_BYTES_BASE, - .option_size = 44, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32H742/743/753 (from RM0433) - .chip_id = STLINK_CHIPID_STM32_H74xxx, - .dev_type = "H74x/H75x", - .flash_type = STLINK_FLASH_TYPE_H7, - .flash_size_reg = 0x1ff1e880, // "Flash size register" (pg3272) - .flash_pagesize = 0x20000, // 128k sector (pg147) - .sram_size = 0x20000, // 128k "DTCM" from Table 7 - .bootrom_base = 0x1ff00000, // "System memory" starting address from Table 7 - .bootrom_size = 0x20000, // "System memory" byte size in hex from Table 7 - .option_base = STM32_H7_OPTION_BYTES_BASE, - .option_size = 44, // FLASH_OPTSR_CUR to FLASH_BOOT_PRGR from Table 28 - .flags = CHIP_F_HAS_DUAL_BANK | CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32L0xx Category 1 - // RM0451, RM0377 - .chip_id = STLINK_CHIPID_STM32_L011, - .dev_type = "L01x/L02x", - .flash_type = STLINK_FLASH_TYPE_L0, - .flash_size_reg = 0x1ff8007c, - .flash_pagesize = 0x80, - .sram_size = 0x2000, - .bootrom_base = 0x1ff00000, - .bootrom_size = 0x2000, - }, - { - // STM32L0x Category 2 - // RM0367, RM0377 - .chip_id = STLINK_CHIPID_STM32_L0_CAT2, - .dev_type = "L0xx Cat.2", - .flash_type = STLINK_FLASH_TYPE_L0, - .flash_size_reg = 0x1ff8007c, - .flash_pagesize = 0x80, - .sram_size = 0x2000, - .bootrom_base = 0x1ff0000, - .bootrom_size = 0x1000, - .option_base = STM32_L0_OPTION_BYTES_BASE, - .option_size = 20, - }, - { - // STM32L0xx Category 3 - // RM0367, RM0377, RM0451 - .chip_id = STLINK_CHIPID_STM32_L0, - .dev_type = "L0xx Cat.3", - .flash_type = STLINK_FLASH_TYPE_L0, - .flash_size_reg = 0x1ff8007c, - .flash_pagesize = 0x80, - .sram_size = 0x2000, - .bootrom_base = 0x1ff0000, - .bootrom_size = 0x1000, - .option_base = STM32_L0_OPTION_BYTES_BASE, - .option_size = 20, - }, - { - // STM32L0x Category 5 - // RM0367, RM0377, RM0451 - .chip_id = STLINK_CHIPID_STM32_L0_CAT5, - .dev_type = "L0xx Cat.5", - .flash_type = STLINK_FLASH_TYPE_L0, - .flash_size_reg = 0x1ff8007c, - .flash_pagesize = 0x80, - .sram_size = 0x5000, - .bootrom_base = 0x1ff0000, - .bootrom_size = 0x2000, - .option_base = STM32_L0_OPTION_BYTES_BASE, - .option_size = 20, - .flags = CHIP_F_HAS_DUAL_BANK, - }, - { - // STM32L100/L15x/L16x Cat.1 - // RM0038 - .chip_id = STLINK_CHIPID_STM32_L1_MD, - .dev_type = "L1xx Cat.1", - .flash_type = STLINK_FLASH_TYPE_L0, - .flash_size_reg = 0x1ff8004c, - .flash_pagesize = 0x100, - .sram_size = 0x4000, // up to 16k - .bootrom_base = 0x1ff00000, - .bootrom_size = 0x1000, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32L100/L15x/L16x Cat.2 - // RM0038 - .chip_id = STLINK_CHIPID_STM32_L1_CAT2, - .dev_type = "L1xx Cat.2", - .flash_type = STLINK_FLASH_TYPE_L0, - .flash_size_reg = 0x1ff8004c, - .flash_pagesize = 0x100, - .sram_size = 0x8000, // up to 32k - .bootrom_base = 0x1ff00000, - .bootrom_size = 0x1000, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32L100/L15x/L16x Cat.3 - // RM0038 - .chip_id = STLINK_CHIPID_STM32_L1_MD_PLUS, - .dev_type = "L1xx Cat.3", - .flash_type = STLINK_FLASH_TYPE_L0, - .flash_size_reg = 0x1ff800cc, - .flash_pagesize = 0x100, - .sram_size = 0x8000, // up to 32k - .bootrom_base = 0x1ff00000, - .bootrom_size = 0x1000, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32L100/L15x/L16x Cat.4 - // RM0038 - .chip_id = STLINK_CHIPID_STM32_L1_MD_PLUS_HD, - .dev_type = "L1xx Cat.4", - .flash_type = STLINK_FLASH_TYPE_L0, - .flash_size_reg = 0x1ff800cc, - .flash_pagesize = 0x100, - .sram_size = 0xC000, // up to 48k - .bootrom_base = 0x1ff00000, - .bootrom_size = 0x1000, - .option_base = STM32_L1_OPTION_BYTES_BASE, - .option_size = 8, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32L100/L15x/L16x Cat.5 - // RM0038 - .chip_id = STLINK_CHIPID_STM32_L152_RE, - .dev_type = "L1xx Cat.5", - .flash_type = STLINK_FLASH_TYPE_L0, - .flash_size_reg = 0x1ff800cc, - .flash_pagesize = 0x100, - .sram_size = 0x14000, // up to 80k - .bootrom_base = 0x1ff00000, - .bootrom_size = 0x1000, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STLINK_CHIPID_STM32_L41x_L42x - // RM0394 (rev 4), DS12469 (rev 5) - .chip_id = STLINK_CHIPID_STM32_L41x_L42x, - .dev_type = "L41x/L42x", - .flash_type = STLINK_FLASH_TYPE_L4, - .flash_size_reg = 0x1fff75e0, // "Flash size data register" (RM0394, - // sec 47.2, page 1586) - .flash_pagesize = 0x800, // 2k (DS12469, sec 3.4, page 17) - // SRAM1 is 32k at 0x20000000 - // SRAM2 is 8k at 0x10000000 and 0x20008000 - // (DS12469, sec 3.5, page 18) - .sram_size = 0xa000, // 40k (DS12469, sec 3.5, page 18) - .bootrom_base = 0x1fff0000, // System Memory (RM0394, sec 3.3.1, table 8) - .bootrom_size = 0x7000, // 28k, same source as base - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STLINK_CHIPID_STM32_L43x_L44x - // RM0392 - .chip_id = STLINK_CHIPID_STM32_L43x_L44x, - .dev_type = "L43x/L44x", - .flash_type = STLINK_FLASH_TYPE_L4, - .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 43.2, page 1410) - .flash_pagesize = 0x800, // 2k (sec 3.2, page 74; also appears in sec 3.3.1 - // and tables 7-8 on pages 75-76) - // SRAM1 is "up to" 64k in the standard Cortex-M memory map; - // SRAM2 is 16k mapped at 0x10000000 (sec 2.3, page 73 for - // sizes; table 2, page 74 for SRAM2 location) - .sram_size = 0xc000, - .bootrom_base = 0x1fff0000, // Tables 4-6, pages 80-81 (Bank 1 system memory) - .bootrom_size = 0x7000, // 28k (per bank), same source as base - .option_base = STM32_L4_OPTION_BYTES_BASE, - .option_size = 4, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STLINK_CHIPID_STM32_L45x_L46x - // RM0394 (updated version of RM0392?) - .chip_id = STLINK_CHIPID_STM32_L45x_L46x, - .dev_type = "L45x/46x", - .flash_type = STLINK_FLASH_TYPE_L4, - .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 45.2, page 1463) - .flash_pagesize = 0x800, // 2k (sec 3.2, page 73; also appears in sec 3.3.1 - // and tables 7 on pages 73-74) - // SRAM1 is 128k at 0x20000000; - // SRAM2 is 32k mapped at 0x10000000 (sec 2.4.2, table 3-4, - // page 68, also fig 2 on page 63) - .sram_size = 0x20000, - .bootrom_base = 0x1fff0000, // Tables 6, pages 71-72 (Bank 1 system - // memory, also fig 2 on page 63) - .bootrom_size = 0x7000, // 28k (per bank), same source as base - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32L47x/L48x - // RM0351 - .chip_id = STLINK_CHIPID_STM32_L4, - .dev_type = "L47x/L48x", - .flash_type = STLINK_FLASH_TYPE_L4, - .flash_size_reg = 0x1FFF75e0, // "Flash size data register" (sec 45.2, page 1671) - .flash_pagesize = 0x800, // 2k (sec 3.2, page 78; also appears in sec 3.3.1 - // and tables 4-6 on pages 79-81) - // SRAM1 is "up to" 96k in the standard Cortex-M memory map; - // SRAM2 is 32k mapped at at 0x10000000 (sec 2.3, page 73 for - // sizes; table 2, page 74 for SRAM2 location) - .sram_size = 0x18000, - .bootrom_base = 0x1fff0000, // Tables 4-6, pages 80-81 (Bank 1 system memory) - .bootrom_size = 0x7000, // 28k (per bank), same source as base - .option_base = STM32_L4_OPTION_BYTES_BASE, - .option_size = 4, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STLINK_CHIPID_STM32_L496x_L4A6x - // RM0351 (rev 5) - .chip_id = STLINK_CHIPID_STM32_L496x_L4A6x, - .dev_type = "L496x/L4A6x", - .flash_type = STLINK_FLASH_TYPE_L4, - .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 49.2, page 1809) - .flash_pagesize = 0x800, // Page erase (2 Kbyte) (sec 3.2, page 93) - // SRAM1 is 256k at 0x20000000 - // SRAM2 is 64k at 0x20040000 (sec 2.2.1, fig 2, page 74) - .sram_size = 0x40000, // Embedded SRAM (sec 2.4, page 84) - .bootrom_base = 0x1fff0000, // System Memory (Bank 1) (sec 3.3.1) - .bootrom_size = 0x7000, // 28k (per bank), same source as base - .option_base = STM32_L4_OPTION_BYTES_BASE, - .option_size = 4, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32L4PX - // RM0432 - .chip_id = STLINK_CHIPID_STM32_L4PX, - .dev_type = "L4Px", - .flash_type = STLINK_FLASH_TYPE_L4, - .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 58.2, page 2274) - .flash_pagesize = 0x1000, // 4k, section 3.3, pg 117-120 - // TODO: flash_pagesize can be 8k depend on the dual-bank mode and flash size - .sram_size = 0xa0000, // 192k (SRAM1) + 64k SRAM2 + 384k SRAM3 = 640k, or 0xA0000 - .bootrom_base = 0x1fff0000, // 3.3.1, pg 117 - .bootrom_size = 0x7000, // 28k (per bank), same source as base (pg 117) - .flags = CHIP_F_HAS_DUAL_BANK | CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32L4RX - // RM0432 - .chip_id = STLINK_CHIPID_STM32_L4Rx, - .dev_type = "L4Rx", - .flash_type = STLINK_FLASH_TYPE_L4, - .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 58.2, page 2274) - .flash_pagesize = 0x1000, // 4k, section 3.3, pg 117-120 - // TODO: flash_pagesize can be 8k depend on the dual-bank mode and flash size - .sram_size = 0xa0000, // 192k (SRAM1) + 64k SRAM2 + 384k SRAM3 = 640k, or 0xA0000 - .bootrom_base = 0x1fff0000, // 3.3.1, pg 117 - .bootrom_size = 0x7000, // 28k (per bank), same source as base (pg 117) - .flags = CHIP_F_HAS_DUAL_BANK | CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32WB55xx, STM32WB35xx, STM32WB50CG/30CE - // RM0434, RM0471 - .chip_id = STLINK_CHIPID_STM32_WB55, - .dev_type = "WB5x/3x", - .flash_type = STLINK_FLASH_TYPE_WB, - .flash_size_reg = 0x1FFF75E0, - .flash_pagesize = 0x1000, // 4k - .sram_size = 0x40000, - .bootrom_base = 0x1fff0000, // see the memory map - .bootrom_size = 0x7000, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32WLEx - .chip_id = STLINK_CHIPID_STM32_WLE, - .dev_type = "WLEx", - .flash_type = STLINK_FLASH_TYPE_WB, - .flash_size_reg = 0x1FFF75E0, - .flash_pagesize = 0x800, // 2k - .sram_size = 0x10000, - .bootrom_base = 0x1fff0000, // see the memory map - .bootrom_size = 0x7000, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // unknown - .chip_id = STLINK_CHIPID_UNKNOWN, - .dev_type = "unknown device", - .flash_type = STLINK_FLASH_TYPE_UNKNOWN, - .flash_size_reg = 0x0, - .flash_pagesize = 0x0, - .sram_size = 0x0, - .bootrom_base = 0x0, - .bootrom_size = 0x0, - }, -//}; \ No newline at end of file diff --git a/src/stlink-lib/flash_loader.c b/src/stlink-lib/flash_loader.c index 6b318dc46..1796c388c 100644 --- a/src/stlink-lib/flash_loader.c +++ b/src/stlink-lib/flash_loader.c @@ -234,43 +234,43 @@ int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* const uint8_t* loader_code; size_t loader_size; - if (sl->chip_id == STLINK_CHIPID_STM32_L1_MD || - sl->chip_id == STLINK_CHIPID_STM32_L1_CAT2 || - sl->chip_id == STLINK_CHIPID_STM32_L1_MD_PLUS || - sl->chip_id == STLINK_CHIPID_STM32_L1_MD_PLUS_HD || - sl->chip_id == STLINK_CHIPID_STM32_L152_RE || - sl->chip_id == STLINK_CHIPID_STM32_L011 || - sl->chip_id == STLINK_CHIPID_STM32_L0 || - sl->chip_id == STLINK_CHIPID_STM32_L0_CAT5 || - sl->chip_id == STLINK_CHIPID_STM32_L0_CAT2) { + if (sl->chip_id == STM32_CHIPID_STM32_L1_MD || + sl->chip_id == STM32_CHIPID_STM32_L1_CAT2 || + sl->chip_id == STM32_CHIPID_STM32_L1_MD_PLUS || + sl->chip_id == STM32_CHIPID_STM32_L1_MD_PLUS_HD || + sl->chip_id == STM32_CHIPID_STM32_L152_RE || + sl->chip_id == STM32_CHIPID_STM32_L011 || + sl->chip_id == STM32_CHIPID_STM32_L0 || + sl->chip_id == STM32_CHIPID_STM32_L0_CAT5 || + sl->chip_id == STM32_CHIPID_STM32_L0_CAT2) { loader_code = loader_code_stm32lx; loader_size = sizeof(loader_code_stm32lx); } else if (sl->core_id == STM32VL_CORE_ID || - sl->chip_id == STLINK_CHIPID_STM32_F1_MD || - sl->chip_id == STLINK_CHIPID_STM32_F1_HD || - sl->chip_id == STLINK_CHIPID_STM32_F1_LD || - sl->chip_id == STLINK_CHIPID_STM32_F1_VL_MD_LD || - sl->chip_id == STLINK_CHIPID_STM32_F1_VL_HD || - sl->chip_id == STLINK_CHIPID_STM32_F1_XLD || - sl->chip_id == STLINK_CHIPID_STM32_F1_CONN || - sl->chip_id == STLINK_CHIPID_STM32_F3 || - sl->chip_id == STLINK_CHIPID_STM32_F3xx_SMALL || - sl->chip_id == STLINK_CHIPID_STM32_F303_HD || - sl->chip_id == STLINK_CHIPID_STM32_F37x || - sl->chip_id == STLINK_CHIPID_STM32_F334) { + sl->chip_id == STM32_CHIPID_STM32_F1_MD || + sl->chip_id == STM32_CHIPID_STM32_F1_HD || + sl->chip_id == STM32_CHIPID_STM32_F1_LD || + sl->chip_id == STM32_CHIPID_STM32_F1_VL_MD_LD || + sl->chip_id == STM32_CHIPID_STM32_F1_VL_HD || + sl->chip_id == STM32_CHIPID_STM32_F1_XLD || + sl->chip_id == STM32_CHIPID_STM32_F1_CONN || + sl->chip_id == STM32_CHIPID_STM32_F3 || + sl->chip_id == STM32_CHIPID_STM32_F3xx_SMALL || + sl->chip_id == STM32_CHIPID_STM32_F303_HD || + sl->chip_id == STM32_CHIPID_STM32_F37x || + sl->chip_id == STM32_CHIPID_STM32_F334) { loader_code = loader_code_stm32vl; loader_size = sizeof(loader_code_stm32vl); - } else if (sl->chip_id == STLINK_CHIPID_STM32_F2 || - sl->chip_id == STLINK_CHIPID_STM32_F4 || - sl->chip_id == STLINK_CHIPID_STM32_F4_DE || - sl->chip_id == STLINK_CHIPID_STM32_F4_LP || - sl->chip_id == STLINK_CHIPID_STM32_F4_HD || - sl->chip_id == STLINK_CHIPID_STM32_F4_DSI || - sl->chip_id == STLINK_CHIPID_STM32_F410 || - sl->chip_id == STLINK_CHIPID_STM32_F411xx || - sl->chip_id == STLINK_CHIPID_STM32_F412 || - sl->chip_id == STLINK_CHIPID_STM32_F413 || - sl->chip_id == STLINK_CHIPID_STM32_F446) { + } else if (sl->chip_id == STM32_CHIPID_STM32_F2 || + sl->chip_id == STM32_CHIPID_STM32_F4 || + sl->chip_id == STM32_CHIPID_STM32_F4_DE || + sl->chip_id == STM32_CHIPID_STM32_F4_LP || + sl->chip_id == STM32_CHIPID_STM32_F4_HD || + sl->chip_id == STM32_CHIPID_STM32_F4_DSI || + sl->chip_id == STM32_CHIPID_STM32_F410 || + sl->chip_id == STM32_CHIPID_STM32_F411xx || + sl->chip_id == STM32_CHIPID_STM32_F412 || + sl->chip_id == STM32_CHIPID_STM32_F413 || + sl->chip_id == STM32_CHIPID_STM32_F446) { int retval; retval = loader_v_dependent_assignment(sl, &loader_code, &loader_size, @@ -279,9 +279,9 @@ int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* if (retval == -1) { return(retval); } } else if (sl->core_id == STM32F7_CORE_ID || - sl->chip_id == STLINK_CHIPID_STM32_F7 || - sl->chip_id == STLINK_CHIPID_STM32_F76xxx || - sl->chip_id == STLINK_CHIPID_STM32_F72xxx) { + sl->chip_id == STM32_CHIPID_STM32_F7 || + sl->chip_id == STM32_CHIPID_STM32_F76xxx || + sl->chip_id == STM32_CHIPID_STM32_F72xxx) { int retval; retval = loader_v_dependent_assignment(sl, &loader_code, &loader_size, @@ -289,19 +289,19 @@ int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* loader_code_stm32f7_lv, sizeof(loader_code_stm32f7_lv)); if (retval == -1) { return(retval); } - } else if (sl->chip_id == STLINK_CHIPID_STM32_F0 || - sl->chip_id == STLINK_CHIPID_STM32_F04 || - sl->chip_id == STLINK_CHIPID_STM32_F0_CAN || - sl->chip_id == STLINK_CHIPID_STM32_F0xx_SMALL || - sl->chip_id == STLINK_CHIPID_STM32_F09x) { + } else if (sl->chip_id == STM32_CHIPID_STM32_F0 || + sl->chip_id == STM32_CHIPID_STM32_F04 || + sl->chip_id == STM32_CHIPID_STM32_F0_CAN || + sl->chip_id == STM32_CHIPID_STM32_F0xx_SMALL || + sl->chip_id == STM32_CHIPID_STM32_F09x) { loader_code = loader_code_stm32f0; loader_size = sizeof(loader_code_stm32f0); - } else if ((sl->chip_id == STLINK_CHIPID_STM32_L4) || - (sl->chip_id == STLINK_CHIPID_STM32_L41x_L42x) || - (sl->chip_id == STLINK_CHIPID_STM32_L43x_L44x) || - (sl->chip_id == STLINK_CHIPID_STM32_L45x_L46x) || - (sl->chip_id == STLINK_CHIPID_STM32_L4Rx) || - (sl->chip_id == STLINK_CHIPID_STM32_L496x_L4A6x)) { + } else if ((sl->chip_id == STM32_CHIPID_STM32_L4) || + (sl->chip_id == STM32_CHIPID_STM32_L41x_L42x) || + (sl->chip_id == STM32_CHIPID_STM32_L43x_L44x) || + (sl->chip_id == STM32_CHIPID_STM32_L45x_L46x) || + (sl->chip_id == STM32_CHIPID_STM32_L4Rx) || + (sl->chip_id == STM32_CHIPID_STM32_L496x_L4A6x)) { loader_code = loader_code_stm32l4; loader_size = sizeof(loader_code_stm32l4); } else { From d3bf1453fd8c2f57faaa91bec01f24f0b00af347 Mon Sep 17 00:00:00 2001 From: Antoine Faure Date: Mon, 10 Jan 2022 09:49:41 +1300 Subject: [PATCH 344/503] Get each page size before erasing --- src/common.c | 31 ++++++++++++++++--------------- 1 file changed, 16 insertions(+), 15 deletions(-) diff --git a/src/common.c b/src/common.c index fb5e431fa..de22ad851 100644 --- a/src/common.c +++ b/src/common.c @@ -2952,24 +2952,25 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { } int stlink_erase_flash_section(stlink_t *sl, stm32_addr_t base_addr, size_t size) { - // erase each page - int i = 0, num_pages = (int)(size / sl->flash_pgsz); - for (i = 0; i < num_pages; i++) { - // addr must be an addr inside the page - stm32_addr_t addr = - (stm32_addr_t)base_addr + i * (stm32_addr_t)sl->flash_pgsz; - - if (stlink_erase_flash_page(sl, addr)) { - WLOG("Failed to erase_flash_page(%#x) == -1\n", addr); - return (-1); - } + stm32_addr_t addr = (stm32_addr_t)base_addr; - fprintf(stdout, "-> Flash page at %5d/%5d erased\n", i, num_pages); - fflush(stdout); + do { + size_t page_size = stlink_calculate_pagesize(sl, addr); + + if (stlink_erase_flash_page(sl, addr)) { + WLOG("Failed to erase_flash_page(%#x) == -1\n", addr); + return (-1); } - fprintf(stdout, "\n"); - return 0; + fprintf(stdout, "-> Flash page at %#x erased (size: %#lx)\n", addr, page_size); + fflush(stdout); + + // check the next page is within the range to erase + addr += page_size; + } while (addr < (base_addr + size)); + + fprintf(stdout, "\n"); + return 0; } int stlink_erase_flash_mass(stlink_t *sl) { From 8a1535e2d2589a6594026b07ee3f4490533de692 Mon Sep 17 00:00:00 2001 From: Antoine Faure Date: Mon, 10 Jan 2022 10:26:14 +1300 Subject: [PATCH 345/503] Check parameters validity --- src/common.c | 5 +++++ src/st-flash/flash.c | 2 +- 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/src/common.c b/src/common.c index de22ad851..ec44f2f9c 100644 --- a/src/common.c +++ b/src/common.c @@ -2952,6 +2952,11 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { } int stlink_erase_flash_section(stlink_t *sl, stm32_addr_t base_addr, size_t size) { + if (base_addr < sl->flash_base || (base_addr + size) > (sl->flash_base + sl->flash_size)) { + ELOG("Invalid address or flash size\n"); + return (-1); + } + stm32_addr_t addr = (stm32_addr_t)base_addr; do { diff --git a/src/st-flash/flash.c b/src/st-flash/flash.c index b4b596cfc..b1cdd02b7 100644 --- a/src/st-flash/flash.c +++ b/src/st-flash/flash.c @@ -168,7 +168,7 @@ int main(int ac, char** av) { goto on_error; } } else if (o.cmd == FLASH_CMD_ERASE) { - if (o.size != 0 && o.addr >= sl->flash_base && (o.addr + o.size) <= (sl->flash_base + sl->flash_size)) + if (o.size > 0 && o.addr > 0) err = stlink_erase_flash_section(sl, o.addr, o.size); else err = stlink_erase_flash_mass(sl); From f277fdb67750033716101ec0d0c48add46c5e075 Mon Sep 17 00:00:00 2001 From: Antoine Faure Date: Mon, 10 Jan 2022 12:51:44 +1300 Subject: [PATCH 346/503] Make sure address and size are each aligned with a page --- src/common.c | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/src/common.c b/src/common.c index ec44f2f9c..a5d008abd 100644 --- a/src/common.c +++ b/src/common.c @@ -2957,11 +2957,26 @@ int stlink_erase_flash_section(stlink_t *sl, stm32_addr_t base_addr, size_t size return (-1); } - stm32_addr_t addr = (stm32_addr_t)base_addr; + stm32_addr_t addr = sl->flash_base; + + // Make sure the requested address is aligned with the beginning of a page + while (addr < base_addr) { + addr += stlink_calculate_pagesize(sl, addr); + } + if (addr != base_addr) { + ELOG("The address to erase is not aligned with the beginning of a page\n"); + return -1; + } do { size_t page_size = stlink_calculate_pagesize(sl, addr); + // Check if we are going further than the requested size + if ((addr + page_size) > (base_addr + size)) { + ELOG("Invalid size (not aligned with a page). Page size at address %#x is %#lx\n", addr, page_size); + return -1; + } + if (stlink_erase_flash_page(sl, addr)) { WLOG("Failed to erase_flash_page(%#x) == -1\n", addr); return (-1); From 1e7d89fc1323f26cd566e059639448e21d66e638 Mon Sep 17 00:00:00 2001 From: hydroconstructor Date: Mon, 10 Jan 2022 20:24:29 +0400 Subject: [PATCH 347/503] Removing env. var. STLINK_DEVICE from docs In #1210 from codebase was removed functionality to specify ST-LINK by environment variable. This still mentioned in documentation, so I updated it. --- doc/man/st-flash.md | 5 ++--- doc/man/st-info.md | 3 --- doc/man/st-util.1 | 2 -- doc/man/st-util.md | 3 +-- doc/tutorial.md | 3 +-- 5 files changed, 4 insertions(+), 12 deletions(-) diff --git a/doc/man/st-flash.md b/doc/man/st-flash.md index 80130c8f1..9b2cfcad5 100644 --- a/doc/man/st-flash.md +++ b/doc/man/st-flash.md @@ -20,8 +20,7 @@ You can use this instead of st-util(1) if you prefer, but remember to use the Use hexadecimal format for the *ADDR* and *SIZE*. -The STLink device to use can be specified using the --serial parameter, or via -the environment variable STLINK_DEVICE on the format :. +The STLink device to use can be specified using the --serial parameter. # COMMANDS @@ -52,7 +51,7 @@ reset : Enable ignore ending empty bytes optimization \--serial *iSerial* -: TODO +: Serial number of ST-LINK device to use \--flash=fsize : Where fsize is the size in decimal, octal, or hex followed by an optional multiplier diff --git a/doc/man/st-info.md b/doc/man/st-info.md index 91f9ea0b0..2cca61f83 100644 --- a/doc/man/st-info.md +++ b/doc/man/st-info.md @@ -15,9 +15,6 @@ st-info - Provides information about connected STLink and STM32 devices Provides information about connected STLink programmers and STM32 devices: Serial code, flash, page size, sram, chipid, description. -The STLink device to probe can be specified via the environment variable -STLINK_DEVICE on the format :. - # OPTIONS \--version diff --git a/doc/man/st-util.1 b/doc/man/st-util.1 index 9b46b4d65..2f718bb2b 100644 --- a/doc/man/st-util.1 +++ b/doc/man/st-util.1 @@ -19,8 +19,6 @@ option, the default \f[B]4242\f[R] port will be used. Stlink version 2 is used by default unless the option \f[B]\[en]stlinkv1\f[R] is given. .PP -The STLinkV2 device to use can be specified in the environment variable -STLINK_DEVICE on the format :. .SH OPTIONS .TP .B \-h, \-\-help diff --git a/doc/man/st-util.md b/doc/man/st-util.md index 9a54fb309..62f850203 100644 --- a/doc/man/st-util.md +++ b/doc/man/st-util.md @@ -17,8 +17,7 @@ Run the main binary of the local package (src/main.rs). If a port number is not specified using the **--listen_port** option, the default **4242** port will be used. -The STLink device to use can be specified using the --serial parameter, or via -the environment variable STLINK_DEVICE on the format :. +The STLink device to use can be specified using the --serial parameter. # OPTIONS diff --git a/doc/tutorial.md b/doc/tutorial.md index 955f85611..685325c37 100644 --- a/doc/tutorial.md +++ b/doc/tutorial.md @@ -244,8 +244,7 @@ There are a few options: Do not reset board on connection. ``` -The STLink device to use can be specified using the --serial parameter, or via -the environment variable STLINK_DEVICE on the format :. +The STLink device to use can be specified using the --serial parameter. Then, in your project directory, someting like this... (remember, you need to run an _ARM_ gdb, not an x86 gdb) From 77b3319fc91120cc7d053e14363c41eb123c8fa3 Mon Sep 17 00:00:00 2001 From: Antoine Faure Date: Thu, 13 Jan 2022 09:12:39 +1300 Subject: [PATCH 348/503] Use stlink_erase_flash_section in stlink_write_flash --- src/common.c | 20 ++------------------ 1 file changed, 2 insertions(+), 18 deletions(-) diff --git a/src/common.c b/src/common.c index a5d008abd..af2222c5b 100644 --- a/src/common.c +++ b/src/common.c @@ -3491,7 +3491,6 @@ int stlink_flashloader_stop(stlink_t *sl, flash_loader_t *fl) { int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint32_t len, uint8_t eraseonly) { - size_t off; int ret; flash_loader_t fl; ILOG("Attempting to write %d (%#x) bytes to stm32 address: %u (%#x)\n", len, @@ -3525,23 +3524,8 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t *base, // make sure we've loaded the context with the chip details stlink_core_id(sl); - // Erase each page - int page_count = 0; - - for (off = 0; off < len; - off += stlink_calculate_pagesize(sl, addr + (uint32_t)off)) { - // addr must be an addr inside the page - if (stlink_erase_flash_page(sl, addr + (uint32_t)off) == -1) { - ELOG("Failed to erase_flash_page(%#x) == -1\n", (unsigned)(addr + off)); - return (-1); - } - - ILOG("Flash page at addr: 0x%08lx erased\n", (unsigned long)(addr + off)); - page_count++; - } - - ILOG("Finished erasing %d pages of %u (%#x) bytes\n", page_count, - (unsigned)(sl->flash_pgsz), (unsigned)(sl->flash_pgsz)); + // Erase this section of the flash + stlink_erase_flash_section(sl, addr, len); if (eraseonly) { return (0); From a2a04dd1b79b5f8c00002d4a914dc3a82f04ea82 Mon Sep 17 00:00:00 2001 From: Antoine Faure Date: Thu, 13 Jan 2022 09:22:14 +1300 Subject: [PATCH 349/503] Update log --- src/common.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/common.c b/src/common.c index af2222c5b..4e276d23b 100644 --- a/src/common.c +++ b/src/common.c @@ -2953,7 +2953,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { int stlink_erase_flash_section(stlink_t *sl, stm32_addr_t base_addr, size_t size) { if (base_addr < sl->flash_base || (base_addr + size) > (sl->flash_base + sl->flash_size)) { - ELOG("Invalid address or flash size\n"); + ELOG("Invalid address or size\n"); return (-1); } From 8667990506da8642344adb5da7f1b76c9d6cbfec Mon Sep 17 00:00:00 2001 From: Antoine Faure Date: Thu, 13 Jan 2022 11:41:14 +1300 Subject: [PATCH 350/503] Allow to completely erase a page when size is not aligned --- inc/stlink.h | 2 +- src/common.c | 13 ++++++++----- src/st-flash/flash.c | 2 +- 3 files changed, 10 insertions(+), 7 deletions(-) diff --git a/inc/stlink.h b/inc/stlink.h index 852e95e42..083b3466c 100644 --- a/inc/stlink.h +++ b/inc/stlink.h @@ -274,7 +274,7 @@ int stlink_trace_enable(stlink_t* sl, uint32_t frequency); int stlink_trace_disable(stlink_t* sl); int stlink_trace_read(stlink_t* sl, uint8_t* buf, size_t size); int stlink_erase_flash_mass(stlink_t* sl); -int stlink_erase_flash_section(stlink_t *sl, stm32_addr_t base_addr, size_t size); +int stlink_erase_flash_section(stlink_t *sl, stm32_addr_t base_addr, size_t size, bool align_size); int stlink_write_flash(stlink_t* sl, stm32_addr_t address, uint8_t* data, uint32_t length, uint8_t eraseonly); int stlink_parse_ihex(const char* path, uint8_t erased_pattern, uint8_t * * mem, size_t * size, uint32_t * begin); uint8_t stlink_get_erased_pattern(stlink_t *sl); diff --git a/src/common.c b/src/common.c index 4e276d23b..f72cad582 100644 --- a/src/common.c +++ b/src/common.c @@ -2951,7 +2951,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { return check_flash_error(sl); } -int stlink_erase_flash_section(stlink_t *sl, stm32_addr_t base_addr, size_t size) { +int stlink_erase_flash_section(stlink_t *sl, stm32_addr_t base_addr, size_t size, bool align_size) { if (base_addr < sl->flash_base || (base_addr + size) > (sl->flash_base + sl->flash_size)) { ELOG("Invalid address or size\n"); return (-1); @@ -2971,8 +2971,8 @@ int stlink_erase_flash_section(stlink_t *sl, stm32_addr_t base_addr, size_t size do { size_t page_size = stlink_calculate_pagesize(sl, addr); - // Check if we are going further than the requested size - if ((addr + page_size) > (base_addr + size)) { + // Check if size is aligned with a page, unless we want to completely erase the last page + if ((addr + page_size) > (base_addr + size) && !align_size) { ELOG("Invalid size (not aligned with a page). Page size at address %#x is %#lx\n", addr, page_size); return -1; } @@ -3000,7 +3000,7 @@ int stlink_erase_flash_mass(stlink_t *sl) { if (sl->flash_type == STLINK_FLASH_TYPE_L0 || sl->flash_type == STLINK_FLASH_TYPE_WB) { - stlink_erase_flash_section(sl, sl->flash_base, sl->flash_size); + err = stlink_erase_flash_section(sl, sl->flash_base, sl->flash_size, false); } else { wait_flash_busy(sl); @@ -3525,7 +3525,10 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t *base, stlink_core_id(sl); // Erase this section of the flash - stlink_erase_flash_section(sl, addr, len); + if (stlink_erase_flash_section(sl, addr, len, true) < 0) { + ELOG("Failed to erase the flash prior to writing\n"); + return (-1); + } if (eraseonly) { return (0); diff --git a/src/st-flash/flash.c b/src/st-flash/flash.c index b1cdd02b7..6ac2ba48b 100644 --- a/src/st-flash/flash.c +++ b/src/st-flash/flash.c @@ -169,7 +169,7 @@ int main(int ac, char** av) { } } else if (o.cmd == FLASH_CMD_ERASE) { if (o.size > 0 && o.addr > 0) - err = stlink_erase_flash_section(sl, o.addr, o.size); + err = stlink_erase_flash_section(sl, o.addr, o.size, false); else err = stlink_erase_flash_mass(sl); From 2c62079ed1d07c9236c08cc1f0e6cf118dd4fb4a Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Fri, 14 Jan 2022 00:17:44 +0100 Subject: [PATCH 351/503] Removed stlink/v1 support for macOS 10.14 --- CHANGELOG.md | 2 +- README.md | 2 +- doc/version_support.md | 2 +- stlinkv1_macos_driver/install.sh | 3 - .../Contents/Info.plist | 82 ------------- .../Contents/MacOS/stlink_shield_10_14 | Bin 33840 -> 0 bytes .../stlink_shield_10_14.kext/Contents/PkgInfo | 1 - .../Contents/_CodeSignature/CodeResources | 115 ------------------ .../stlink_shield.xcodeproj/project.pbxproj | 50 -------- 9 files changed, 3 insertions(+), 254 deletions(-) delete mode 100644 stlinkv1_macos_driver/stlink_shield_10_14.kext/Contents/Info.plist delete mode 100644 stlinkv1_macos_driver/stlink_shield_10_14.kext/Contents/MacOS/stlink_shield_10_14 delete mode 100644 stlinkv1_macos_driver/stlink_shield_10_14.kext/Contents/PkgInfo delete mode 100644 stlinkv1_macos_driver/stlink_shield_10_14.kext/Contents/_CodeSignature/CodeResources diff --git a/CHANGELOG.md b/CHANGELOG.md index 06f995d21..039ca7848 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -2,7 +2,7 @@ # v1.7.1 -Release date: 2021-xx-xx +Release date: 2022-xx-xx This release drops support for some older operating systems. Check project README for details. Updated system requirements: Raised minimum version for `cmake` to 3.7.2. diff --git a/README.md b/README.md index 7f797a7d9..bc491189e 100644 --- a/README.md +++ b/README.md @@ -38,7 +38,7 @@ It supports several so called STLINK programmer boards (and clones thereof) whic - stand-alone programmer (STLINK-V3SET, STLINK-V3MINI, STLINK-V3MODS) - on-board on some STM32 Nucleo boards (STLINK-V3E) -_\*)_ **Note: Support for the STLINK/V1 on macOS is limited to 10.14 - 10.15. Due to the deprecation and removal of macOS Kernel Extensions (KEXT) there will be no support for this programmer on macOS 11 or any later version.** +_\*)_ *Note: Support for the STLINK/V1 on macOS is limited to 10.15. Due to the deprecation and removal of macOS Kernel Extensions (KEXT) there will be no support for this programmer on macOS 11 or any later version.* On the user level there is no difference in handling or operation between these different revisions. diff --git a/doc/version_support.md b/doc/version_support.md index 2c5df7461..4eeb5074a 100644 --- a/doc/version_support.md +++ b/doc/version_support.md @@ -17,7 +17,7 @@ Up on compiling c-make will **automatically** download and install the latest co | homebrew | 1.0.24 | 3.20.2 | 3.24.29
gtk+3 | 10.9 - 11.x | | MacPorts | 1.0.24 | 3.20.2 | 3.24.29
gtk3 | 10.4 - 11.x | -NOTE: In order to use a STLINK/V1 programmer on macOS, versions 10.14 or 10.15 are required. +NOTE: In order to use a STLINK/V1 programmer on macOS, version 10.15 is required. ### Linux-/Unix-based: diff --git a/stlinkv1_macos_driver/install.sh b/stlinkv1_macos_driver/install.sh index 5716281a1..f9878bd46 100644 --- a/stlinkv1_macos_driver/install.sh +++ b/stlinkv1_macos_driver/install.sh @@ -2,9 +2,6 @@ ISMACOS=$(sw_vers -productVersion) case $ISMACOS in -10.14*) - KEXT="stlink_shield_10_14.kext" - ;; 10.15*) KEXT="stlink_shield_10_15.kext" ;; diff --git a/stlinkv1_macos_driver/stlink_shield_10_14.kext/Contents/Info.plist b/stlinkv1_macos_driver/stlink_shield_10_14.kext/Contents/Info.plist deleted file mode 100644 index fd424ea93..000000000 --- a/stlinkv1_macos_driver/stlink_shield_10_14.kext/Contents/Info.plist +++ /dev/null @@ -1,82 +0,0 @@ - - - - - BuildMachineOSBuild - 18G7016 - CFBundleDevelopmentRegion - English - CFBundleIdentifier - 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10 - - ^embedded\.provisionprofile$ - - weight - 20 - - ^version\.plist$ - - weight - 20 - - - - diff --git a/stlinkv1_macos_driver/stlink_shield_xcode/stlink_shield.xcodeproj/project.pbxproj b/stlinkv1_macos_driver/stlink_shield_xcode/stlink_shield.xcodeproj/project.pbxproj index 4f2b80254..373600c64 100644 --- a/stlinkv1_macos_driver/stlink_shield_xcode/stlink_shield.xcodeproj/project.pbxproj +++ b/stlinkv1_macos_driver/stlink_shield_xcode/stlink_shield.xcodeproj/project.pbxproj @@ -8,7 +8,6 @@ /* Begin PBXFileReference section */ 8CD33C31149BB80D0033D618 /* Info.plist */ = {isa = PBXFileReference; lastKnownFileType = text.plist.xml; path = Info.plist; sourceTree = ""; }; - 8F9084FD24786F0F009109AD /* stlink_shield_10_14.kext */ = {isa = PBXFileReference; explicitFileType = wrapper.cfbundle; includeInIndex = 0; path = stlink_shield_10_14.kext; sourceTree = BUILT_PRODUCTS_DIR; }; 8F90850924786F39009109AD /* stlink_shield_10_15.kext */ = {isa = PBXFileReference; explicitFileType = wrapper.cfbundle; includeInIndex = 0; path = stlink_shield_10_15.kext; sourceTree = BUILT_PRODUCTS_DIR; }; /* End PBXFileReference section */ @@ -34,7 +33,6 @@ 19C28FB6FE9D52B211CA2CBB /* Products */ = { isa = PBXGroup; children = ( - 8F9084FD24786F0F009109AD /* stlink_shield_10_14.kext */, 8F90850924786F39009109AD /* stlink_shield_10_15.kext */, ); name = Products; @@ -60,26 +58,6 @@ /* End PBXHeadersBuildPhase section */ /* Begin PBXNativeTarget section */ - 8F9084F324786F0F009109AD /* stlink_shield_10_14 */ = { - isa = PBXNativeTarget; - buildConfigurationList = 8F9084FA24786F0F009109AD /* Build configuration list for PBXNativeTarget "stlink_shield_10_14" */; - buildPhases = ( - 8F9084F424786F0F009109AD /* ShellScript */, - 8F9084F524786F0F009109AD /* Headers */, - 8F9084F624786F0F009109AD /* Resources */, - 8F9084F824786F0F009109AD /* Sources */, - 8F9084F924786F0F009109AD /* ShellScript */, - ); - buildRules = ( - ); - dependencies = ( - ); - name = stlink_shield_10_14; - productInstallPath = "$(SYSTEM_LIBRARY_DIR)/Extensions"; - productName = NanosMouse; - productReference = 8F9084FD24786F0F009109AD /* stlink_shield_10_14.kext */; - productType = "com.apple.product-type.kernel-extension.iokit"; - }; 8F9084FF24786F39009109AD /* stlink_shield_10_15 */ = { isa = PBXNativeTarget; buildConfigurationList = 8F90850624786F39009109AD /* Build configuration list for PBXNativeTarget "stlink_shield_10_15" */; @@ -120,7 +98,6 @@ projectDirPath = ""; projectRoot = ""; targets = ( - 8F9084F324786F0F009109AD /* stlink_shield_10_14 */, 8F9084FF24786F39009109AD /* stlink_shield_10_15 */, ); }; @@ -458,24 +435,6 @@ }; name = Release; }; - 8F9084FB24786F0F009109AD /* Debug */ = { - isa = XCBuildConfiguration; - buildSettings = { - CODE_SIGN_IDENTITY = "-"; - MACOSX_DEPLOYMENT_TARGET = 10.14; - PRODUCT_NAME = "$(TARGET_NAME)"; - }; - name = Debug; - }; - 8F9084FC24786F0F009109AD /* Release */ = { - isa = XCBuildConfiguration; - buildSettings = { - CODE_SIGN_IDENTITY = "-"; - MACOSX_DEPLOYMENT_TARGET = 10.14; - PRODUCT_NAME = "$(TARGET_NAME)"; - }; - name = Release; - }; 8F90850724786F39009109AD /* Debug */ = { isa = XCBuildConfiguration; buildSettings = { @@ -506,15 +465,6 @@ defaultConfigurationIsVisible = 0; defaultConfigurationName = Release; }; - 8F9084FA24786F0F009109AD /* Build configuration list for PBXNativeTarget "stlink_shield_10_14" */ = { - isa = XCConfigurationList; - buildConfigurations = ( - 8F9084FB24786F0F009109AD /* Debug */, - 8F9084FC24786F0F009109AD /* Release */, - ); - defaultConfigurationIsVisible = 0; - defaultConfigurationName = Release; - }; 8F90850624786F39009109AD /* Build configuration list for PBXNativeTarget "stlink_shield_10_15" */ = { isa = XCConfigurationList; buildConfigurations = ( From 74957efc9dafb3569c4ef4d0ab9d9007d7989af4 Mon Sep 17 00:00:00 2001 From: Antoine Faure Date: Fri, 14 Jan 2022 14:50:35 +1300 Subject: [PATCH 352/503] Factorize address checks --- inc/stlink.h | 2 ++ src/common.c | 55 +++++++++++++++++++++++++++++++++------------------- 2 files changed, 37 insertions(+), 20 deletions(-) diff --git a/inc/stlink.h b/inc/stlink.h index 083b3466c..df13aa7c9 100644 --- a/inc/stlink.h +++ b/inc/stlink.h @@ -289,6 +289,8 @@ int stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid); int stlink_erase_flash_page(stlink_t* sl, stm32_addr_t flashaddr); uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr); +int stlink_check_address_range_validity(stlink_t *sl, stm32_addr_t addr, size_t size); +int stlink_check_address_alignment(stlink_t *sl, stm32_addr_t addr); uint16_t read_uint16(const unsigned char *c, const int pt); void stlink_core_stat(stlink_t *sl); void stlink_print_data(stlink_t *sl); diff --git a/src/common.c b/src/common.c index f72cad582..6cbd217ef 100644 --- a/src/common.c +++ b/src/common.c @@ -2951,23 +2951,47 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { return check_flash_error(sl); } -int stlink_erase_flash_section(stlink_t *sl, stm32_addr_t base_addr, size_t size, bool align_size) { - if (base_addr < sl->flash_base || (base_addr + size) > (sl->flash_base + sl->flash_size)) { - ELOG("Invalid address or size\n"); +// Check if an address and size are within the flash +int stlink_check_address_range_validity(stlink_t *sl, stm32_addr_t addr, size_t size) { + if (addr < sl->flash_base || addr >= (sl->flash_base + sl->flash_size)) { + ELOG("Invalid address, it should be within 0x%08x - 0x%08lx\n", sl->flash_base, (sl->flash_base + sl->flash_size -1)); + return (-1); + } + if ((addr + size) > (sl->flash_base + sl->flash_size)) { + ELOG("The size exceeds the size of the flash (0x%08lx bytes available)\n", (sl->flash_base + sl->flash_size - addr)); return (-1); } + return 0; +} - stm32_addr_t addr = sl->flash_base; +// Check if an address is aligned with the beginning of a page +int stlink_check_address_alignment(stlink_t *sl, stm32_addr_t addr) { + stm32_addr_t page = sl->flash_base; - // Make sure the requested address is aligned with the beginning of a page - while (addr < base_addr) { - addr += stlink_calculate_pagesize(sl, addr); + while (page < addr) { + page += stlink_calculate_pagesize(sl, page); } - if (addr != base_addr) { + + if (page != addr) { + return -1; + } + + return 0; +} + +int stlink_erase_flash_section(stlink_t *sl, stm32_addr_t base_addr, size_t size, bool align_size) { + // Check the address and size validity + if (stlink_check_address_range_validity(sl, base_addr, size) < 0) { + return -1; + } + + // Make sure the requested address is aligned with the beginning of a page + if (stlink_check_address_alignment(sl, base_addr) < 0) { ELOG("The address to erase is not aligned with the beginning of a page\n"); return -1; } + stm32_addr_t addr = base_addr; do { size_t page_size = stlink_calculate_pagesize(sl, addr); @@ -3498,22 +3522,13 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t *base, // check addr range is inside the flash stlink_calculate_pagesize(sl, addr); - if (addr < sl->flash_base) { - ELOG("addr too low %#x < %#x\n", addr, sl->flash_base); - return (-1); - } else if ((addr + len) < addr) { - ELOG("addr overruns\n"); - return (-1); - } else if ((addr + len) > (sl->flash_base + sl->flash_size)) { - ELOG("addr too high\n"); - return (-1); - } else if (addr & 1) { - ELOG("unaligned addr 0x%x\n", addr); + // Check the address and size validity + if (stlink_check_address_range_validity(sl, addr, len) < 0) { return (-1); } else if (len & 1) { WLOG("unaligned len 0x%x -- padding with zero\n", len); len += 1; - } else if (addr & (sl->flash_pgsz - 1)) { + } else if (stlink_check_address_alignment(sl, addr) < 0) { ELOG("addr not a multiple of current pagesize (%u bytes), not supported, " "check page start address and compare with flash module organisation " "in related ST reference manual of your device.\n", From c854df5edd1285c1016e6181bcd54acf6f2e0bcd Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sat, 15 Jan 2022 01:58:42 +0100 Subject: [PATCH 353/503] Updated MCU core-ids --- doc/devices_boards.md | 30 +++++++++++++++--------------- inc/stm32.h | 33 +++++++++++++++++++++------------ src/common.c | 2 +- src/st-util/gdb-server.c | 2 +- src/stlink-lib/flash_loader.c | 4 ++-- 5 files changed, 40 insertions(+), 31 deletions(-) diff --git a/doc/devices_boards.md b/doc/devices_boards.md index a8a366448..63569881a 100644 --- a/doc/devices_boards.md +++ b/doc/devices_boards.md @@ -2,7 +2,7 @@ The following devices are supported by the stlink toolset. -## STM32F0 / ARM Cortex M0 / Core-ID: 0x0bb11477 (STM32F0_CORE_ID) +## STM32F0 / ARM Cortex M0 | Chip-ID | Product-Code | | ------- | ------------------- | @@ -19,7 +19,7 @@ The following devices are supported by the stlink toolset. | 0x442 | STM32F0**9**xxx | -## STM32F1 / ARM Cortex M3 / Core-ID: 0x1ba01477 (STM32F1_CORE_ID) +## STM32F1 / ARM Cortex M3 | Product-Code | Product Line | | ----------------- | ----------------------- | @@ -45,20 +45,20 @@ Tested non-official ST boards [incl. STLINK programmers]: - HY-STM32 (STM32F103VETx) [v1, v2] - DecaWave EVB1000 (STM32F105RCTx) [v1, v2] -## STM32F2 / ARM Cortex M3 / Core-ID: 0x2ba01477 (STM32F2_CORE_ID) +## STM32F2 / ARM Cortex M3 | Chip-ID | Product-Code | Product Line | | ------- | ------------ | ------------- | | 0x411 | STM32F2yyxx | (all devices) | -## STM32F1 / ARM Cortex M3 / Core-ID: 0x2ba01477 (STM32F1c_CORE_ID) +## STM32F1 Clone / ARM Cortex M3 (Core-ID: 0x2ba01477) | Product-Code | Chip-ID | STLink
Programmer | Boards | | ------------- | ------- | ---------------------- | ----------------------------------------------------------------------------------------------- | | CKS32F103C8Tx | 0x410 | v2 | "STM32"-Bluepill ( _**Fake-Marking !**_ )
STM32F103C8T6 clone from China Key Systems (CKS) | | CKS32F103C8Tx | 0x410 | v2 | CKS32-Bluepill (Clone)
STM32F103C8T6 clone from China Key Systems (CKS) | -## STM32F3 / ARM Cortex M4F / Core-ID: 0x2ba01477 (STM32F3_CORE_ID) +## STM32F3 / ARM Cortex M4F | Product-Code | Product Line | | ----------------- | ------------------------------------------------------------- | @@ -85,13 +85,13 @@ Tested non-official ST boards [incl. STLINK programmers]: | 0x446 | _N/A_ | xD xE | | F302 | F303 | | | 0x446 | _N/A_ | - | | | | F398 | -## STM32F3 / ARM Cortex M4F / Core-ID: 0x2ba01477 (STM32F3c_CORE_ID) +## STM32F3 Clone / ARM Cortex M4F (Core-ID: 0x2ba01477) | Product-Code | Chip-ID | STLINK
Programmer | Boards | | ------------ | ------- | ---------------------- | ---------------------------------- | | GD32F303VGT6 | 0x430 | [v2] | STM32F303 clone from GigaDevice GD | -## STM32F4 / ARM Cortex M4F / Core-ID: 0x2ba01477 (STM32F4_CORE_ID) +## STM32F4 / ARM Cortex M4F | Chip-ID | Product-Code | | ------- | ------------------- | @@ -112,7 +112,7 @@ Tested non-official ST boards [incl. STLINK programmers]: | 0x463 | STM32F4**13**xx | | 0x463 | STM32F4**23**xx | -## STM32F7 / ARM Cortex M7F / Core-ID: 0x5ba02477 (STM32F7_CORE_ID) +## STM32F7 / ARM Cortex M7F | Chip-ID | Product-Code | | ------- | --------------- | @@ -123,7 +123,7 @@ Tested non-official ST boards [incl. STLINK programmers]: | 0x451 | STM32F7**6**xxx | | 0x451 | STM32F7**7**xxx | -## STM32H7 / ARM Cortex M7F / Core-ID: 0x6ba02477 (STM32H7_CORE_ID) +## STM32H7 / ARM Cortex M7F | Chip-ID | Product-Code | | ------- | ------------- | @@ -132,7 +132,7 @@ Tested non-official ST boards [incl. STLINK programmers]: | 0x480 | STM32H7**A**x | | 0x480 | STM32H7**B**x | -## STM32G0 / ARM Cortex M0+ / Core-ID: 0x0bc11477 (STM32G0_CORE_ID) +## STM32G0 / ARM Cortex M0+ | Chip-ID | Product-Code | | ------- | --------------- | @@ -141,7 +141,7 @@ Tested non-official ST boards [incl. STLINK programmers]: | 0x460 | STM32G0**7**xxx | | 0x460 | STM32G0**8**xxx | -## STM32G4 / ARM Cortex M4F / Core-ID: 0x2ba01477 (STM32G4_CORE_ID) +## STM32G4 / ARM Cortex M4F | Chip-ID | Product-Code | | ------- | --------------- | @@ -151,7 +151,7 @@ Tested non-official ST boards [incl. STLINK programmers]: | 0x469 | STM32G4**8**xxx | | 0x479 | STM32G4**91**xx | -## STM32L0 / ARM Cortex M0+ / Core-ID: 0x0bc11477 (STM32L0_CORE_ID) +## STM32L0 / ARM Cortex M0+ | Chip-ID | Product-Code | | ------- | --------------- | @@ -164,7 +164,7 @@ Tested non-official ST boards [incl. STLINK programmers]: | 0x447 | STM32L0**7**xxx | | 0x447 | STM32L0**8**xxx | -## STM32L1 / ARM Cortex M3 / Core-ID: 0x2ba01477 (STM32L1_CORE_ID) +## STM32L1 / ARM Cortex M3 | Chip-ID | Product-Code | | ------- | ---------------- | @@ -178,7 +178,7 @@ Tested non-official ST boards [incl. STLINK programmers]: | 0x436 | STM32L1xxx**D** | | 0x437 | STM32L1xxx**E** | -## STM32L4 / ARM Cortex M4F / Core-ID: 0x2ba01477 (STM32L4_CORE_ID) +## STM32L4 / ARM Cortex M4F | Chip-ID | Product-Code | | ------- | --------------- | @@ -197,7 +197,7 @@ Tested non-official ST boards [incl. STLINK programmers]: | 0x471 | STM32L4**P5**xx | | 0x471 | STM32L4**Q5**xx | -## STM32W / ARM Cortex M3 / Core-ID: 0x2ba01477 (STM32W_CORE_ID) +## STM32W / ARM Cortex M3 | Chip-ID | Product-Code | | ------- | --------------- | diff --git a/inc/stm32.h b/inc/stm32.h index 8dff2a7d7..d6faff12e 100644 --- a/inc/stm32.h +++ b/inc/stm32.h @@ -7,11 +7,20 @@ #ifndef STM32_H #define STM32_H -/* Cortex-M core ids */ -#define STM32VL_CORE_ID 0x1ba01477 -#define STM32F7_CORE_ID 0x5ba02477 -#define STM32H7_CORE_ID 0x6ba02477 // STM32H7 SWD ID Code -#define STM32H7_CORE_ID_JTAG 0x6ba00477 // STM32H7 JTAG ID Code (RM0433 p.3065) +/* Cortex-M core ids (CPUTAPID) */ +#define STM32_CORE_ID_M3_F2_JTAG 0x0ba00477 // unused // F2 JTAG (RM0033 p.1326) +//#define STM32_CORE_ID_M33_JTAG 0x0ba04477 // unused // L5 JTAG +#define STM32_CORE_ID_M0 0x0bb11477 // unused // F0 +#define STM32_CORE_ID_M0P 0x0bc11477 // unused // L0, G0 +#define STM32_CORE_ID_M33 0x0be01477 // unused // L5 SWD (RM0351 p.2029) +#define STM32_CORE_ID_M33_JTAG 0x0be02477 // unused // L5 JTAG (RM0438 p.2029) +#define STM32_CORE_ID_M3_F1 0x1ba01477 // F1 (RM0008 p.1092) +#define STM32_CORE_ID_M4F_L4 0x1ba01477 // unused // L4 (RM0351 p.1845) +#define STM32_CORE_ID_M4F_F4 0x2ba01477 // unused // F4 (RM0090 p.1695) +#define STM32_CORE_ID_M4F_F4_JTAG 0x4ba00477 // unused // F4 JTAG (RM090 p.1691) +#define STM32_CORE_ID_M7_F7 0x5ba02477 // F7 +#define STM32_CORE_ID_M7_H7 0x6ba02477 // H7 +#define STM32_CORE_ID_M7_H7_JTAG 0x6ba00477 // H7 JTAG (RM0433 p.3065) /* STM32 flash types */ // New flash type definitions must go before STM32_FLASH_TYPE_UNDEFINED @@ -22,13 +31,13 @@ enum stm32_flash_type { STM32_FLASH_TYPE_F1_XL = 2, STM32_FLASH_TYPE_F2_F4 = 3, STM32_FLASH_TYPE_F7 = 4, - STM32_FLASH_TYPE_G0 = 5, // 7 - STM32_FLASH_TYPE_G4 = 6, // 8 - STM32_FLASH_TYPE_H7 = 7, // 10 - STM32_FLASH_TYPE_L0_L1 = 8, // 5 - STM32_FLASH_TYPE_L4_L4P = 9, // 6 - STM32_FLASH_TYPE_L5_U5 = 10, // new - STM32_FLASH_TYPE_WB_WL = 11, // 9 + STM32_FLASH_TYPE_G0 = 5, + STM32_FLASH_TYPE_G4 = 6, + STM32_FLASH_TYPE_H7 = 7, + STM32_FLASH_TYPE_L0_L1 = 8, + STM32_FLASH_TYPE_L4_L4P = 9, + STM32_FLASH_TYPE_L5_U5 = 10, + STM32_FLASH_TYPE_WB_WL = 11, STM32_FLASH_TYPE_UNDEFINED = 12, // max. value exceeded }; diff --git a/src/common.c b/src/common.c index 5a6d0d86b..5a9c43c96 100644 --- a/src/common.c +++ b/src/common.c @@ -1514,7 +1514,7 @@ int stlink_chip_id(stlink_t *sl, uint32_t *chip_id) { * */ - if ((sl->core_id == STM32H7_CORE_ID || sl->core_id == STM32H7_CORE_ID_JTAG) && + if ((sl->core_id == STM32_CORE_ID_M7_H7 || sl->core_id == STM32_CORE_ID_M7_H7_JTAG) && cpu_id.part == STLINK_REG_CMx_CPUID_PARTNO_CM7) { // STM32H7 chipid in 0x5c001000 (RM0433 pg3189) ret = stlink_read_debug32(sl, 0x5c001000, chip_id); diff --git a/src/st-util/gdb-server.c b/src/st-util/gdb-server.c index 4babef0cc..19819a6cb 100644 --- a/src/st-util/gdb-server.c +++ b/src/st-util/gdb-server.c @@ -559,7 +559,7 @@ char* make_memory_map(stlink_t *sl) { strcpy(map, memory_map_template_F4); } else if (sl->chip_id == STM32_CHIPID_STM32_F4_DE) { strcpy(map, memory_map_template_F4_DE); - } else if (sl->core_id == STM32F7_CORE_ID) { + } else if (sl->core_id == STM32_CORE_ID_M7_F7) { snprintf(map, sz, memory_map_template_F7, (unsigned int)sl->sram_size); } else if (sl->chip_id == STM32_CHIPID_STM32_H74xxx) { diff --git a/src/stlink-lib/flash_loader.c b/src/stlink-lib/flash_loader.c index 1796c388c..ad52d6567 100644 --- a/src/stlink-lib/flash_loader.c +++ b/src/stlink-lib/flash_loader.c @@ -245,7 +245,7 @@ int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* sl->chip_id == STM32_CHIPID_STM32_L0_CAT2) { loader_code = loader_code_stm32lx; loader_size = sizeof(loader_code_stm32lx); - } else if (sl->core_id == STM32VL_CORE_ID || + } else if (sl->core_id == STM32_CORE_ID_M3_F1 || sl->chip_id == STM32_CHIPID_STM32_F1_MD || sl->chip_id == STM32_CHIPID_STM32_F1_HD || sl->chip_id == STM32_CHIPID_STM32_F1_LD || @@ -278,7 +278,7 @@ int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* loader_code_stm32f4_lv, sizeof(loader_code_stm32f4_lv)); if (retval == -1) { return(retval); } - } else if (sl->core_id == STM32F7_CORE_ID || + } else if (sl->core_id == STM32_CORE_ID_M7_F7 || sl->chip_id == STM32_CHIPID_STM32_F7 || sl->chip_id == STM32_CHIPID_STM32_F76xxx || sl->chip_id == STM32_CHIPID_STM32_F72xxx) { From 3be2c70a675e1cfec5d1a6c35621dcc1d1517566 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 16 Jan 2022 18:10:01 +0100 Subject: [PATCH 354/503] General Project Update - [doc] Updated system requirements -> cmake >= 3.10.2 -> libusb >= 1.0.21 (except for FreeBSD) -> gtk >= 3.22.30 - Updated CHANGELOG.md - Updated list of contributors --- CHANGELOG.md | 16 ++- CMakeLists.txt | 2 +- cmake/modules/Findlibusb.cmake | 2 +- cmake/packaging/cpack_config.cmake | 2 +- cmake/packaging/deb/control | 2 +- contributors.txt | 3 + doc/compiling.md | 4 +- doc/version_support.md | 153 +++++++++++++++-------------- 8 files changed, 103 insertions(+), 81 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index 039ca7848..d744ff564 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -5,7 +5,11 @@ Release date: 2022-xx-xx This release drops support for some older operating systems. Check project README for details. -Updated system requirements: Raised minimum version for `cmake` to 3.7.2. + +Updated system requirements: +- `cmake` >= 3.10.2 +- `libusb` >= 1.0.21 +- `libgtk-dev` >= 3.22.30 Features: @@ -15,6 +19,9 @@ Features: - Expanded and revised list of chips ([#1145](https://github.com/stlink-org/stlink/pull/1145), [#1164](https://github.com/stlink-org/stlink/pull/1164)) - [STM32H72X/3X]: Added full access to all device memory ([#1158](https://github.com/stlink-org/stlink/pull/1158), [#1159](https://github.com/stlink-org/stlink/pull/1159)) - Added support for STM32WLEx ([#1173](https://github.com/stlink-org/stlink/pull/1173)) +- Added support for STLINK-V3 devices with no MSD ([#1185](https://github.com/stlink-org/stlink/pull/1185)) +- Updated gdb-server.c to allow external memory access on STM32H73xx ([#1196](https://github.com/stlink-org/stlink/pull/1196), [#1197](https://github.com/stlink-org/stlink/pull/1197)) +- Erase addr size / section of the flash memory with st-flash ([#1213](https://github.com/stlink-org/stlink/pull/1213)) Updates & changes: @@ -22,10 +29,12 @@ Updates & changes: - Added instructions for bug-reports and feature-requests to contribution guidelines ([#906](https://github.com/stlink-org/stlink/pull/906)) - Added travis CI configuration for macOS 10.14 to maintain capability for 32-bit compilation ([#f5ada94](https://github.com/stlink-org/stlink/commit/f5ada9474cdb87ff37de0d4eb9e75622b5870646)) - Updated description of chip id 0x0457 to L01x/L02x ([#1143](https://github.com/stlink-org/stlink/pull/1143), [#1144](https://github.com/stlink-org/stlink/pull/1144)) -- Drop execute bits from source code files ([#1167](https://github.com/stlink-org/stlink/pull/1167)) +- Dropped execute bits from source code files ([#1167](https://github.com/stlink-org/stlink/pull/1167)) - Use proper Markdown headers for supported MCUs ([#1168](https://github.com/stlink-org/stlink/pull/1168)) - Removed redundant array ([#1178](https://github.com/stlink-org/stlink/pull/1178)) - Updated chip config files from the library structs ([#1181](https://github.com/stlink-org/stlink/pull/1181)) +- [doc] Corrected file path in tutorial ([#1186](https://github.com/stlink-org/stlink/pull/1186)) +- Improved chipid checks and printouts ([#1188](https://github.com/stlink-org/stlink/pull/1188)) Fixes: - cmake: Install shared libraries in proper directories ([#1142](https://github.com/stlink-org/stlink/pull/1142)) @@ -41,6 +50,9 @@ Fixes: - Fixed few warnings for msvc about type conversion with possible lost data ([#1179](https://github.com/stlink-org/stlink/pull/1179)) - st-flash and other utilities search for chip files in the wrong directory ([#1180](https://github.com/stlink-org/stlink/pull/1180), commit [#c8fc656](https://github.com/stlink-org/stlink/commit/c8fc6561fead79ad49c09d82bab864745086792c)) - Fixed broken build on 32 bit systems ([#985](https://github.com/stlink-org/stlink/pull/985), [#1175](https://github.com/stlink-org/stlink/pull/1175), commit [#c8fc656](https://github.com/stlink-org/stlink/commit/c8fc6561fead79ad49c09d82bab864745086792c)) +- Define 'SSIZE_MAX' if not defined ([#1183](https://github.com/stlink-org/stlink/pull/1183)) +- Fixed compliation for OpenBSD 7.0 ([#1202](https://github.com/stlink-org/stlink/pull/1202)) +- Included 'SSIZE_MAX' from 'limits.h' in 'src/common.c' ([#1207](https://github.com/stlink-org/stlink/pull/1207)) # v1.7.0 diff --git a/CMakeLists.txt b/CMakeLists.txt index fd17d47cc..66bf34e3e 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -2,7 +2,7 @@ # General cmake settings ### -cmake_minimum_required(VERSION 3.7.2) +cmake_minimum_required(VERSION 3.10.2) cmake_policy(SET CMP0042 NEW) set(CMAKE_MODULE_PATH ${CMAKE_SOURCE_DIR}/cmake/modules) set(CMAKE_ARCHIVE_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}/lib) diff --git a/cmake/modules/Findlibusb.cmake b/cmake/modules/Findlibusb.cmake index cd52026f5..bc04f848d 100644 --- a/cmake/modules/Findlibusb.cmake +++ b/cmake/modules/Findlibusb.cmake @@ -72,7 +72,7 @@ elseif (WIN32 OR (EXISTS "/etc/debian_version" AND MINGW)) # Windows or MinGW-to if (WIN32 AND NOT EXISTS "/etc/debian_version") # Skip this for Debian... # Preparations for installing libusb library - set(LIBUSB_WIN_VERSION 1.0.23) # set libusb version + set(LIBUSB_WIN_VERSION 1.0.24) # set libusb version set(LIBUSB_WIN_ARCHIVE libusb-${LIBUSB_WIN_VERSION}.7z) if (WIN32 AND NOT EXISTS "/etc/debian_version") # ... on native Windows systems set(LIBUSB_WIN_ARCHIVE_PATH ${CMAKE_BINARY_DIR}/${LIBUSB_WIN_ARCHIVE}) diff --git a/cmake/packaging/cpack_config.cmake b/cmake/packaging/cpack_config.cmake index acd5630fa..587ff5fb5 100644 --- a/cmake/packaging/cpack_config.cmake +++ b/cmake/packaging/cpack_config.cmake @@ -53,7 +53,7 @@ elseif (EXISTS "/etc/debian_version" AND NOT EXISTS WIN32) # Package-build is av set(CPACK_DEBIAN_PACKAGE_RELEASE "1") # CPACK_DEBIAN_PACKAGE_ARCHITECTURE --> Default: Output of dpkg --print-architecture - set(CPACK_DEBIAN_PACKAGE_DEPENDS "pkg-config, build-essential, debhelper (>=9), cmake (>= 3.4.2), libusb-1.0-0-dev (>= 1.0.20)") + set(CPACK_DEBIAN_PACKAGE_DEPENDS "pkg-config, build-essential, debhelper (>=9), cmake (>= 3.10.2), libusb-1.0-0-dev (>= 1.0.21)") set(CPACK_DEBIAN_PACKAGE_MAINTAINER "Nightwalker-87 ") # CPACK_DEBIAN_PACKAGE_DESCRIPTION --> Default: CPACK_DEBIAN_PACKAGE_DESCRIPTION (as it is set) # CPACK_DEBIAN_PACKAGE_SECTION --> Default: “devel” diff --git a/cmake/packaging/deb/control b/cmake/packaging/deb/control index ef51a6cea..7c8d13e47 100644 --- a/cmake/packaging/deb/control +++ b/cmake/packaging/deb/control @@ -1,7 +1,7 @@ Source: stlink Priority: optional Maintainer: Nightwalker-87 -Build-Depends: cmake, dh-cmake, debhelper (>= 9), libusb-1.0-0-dev, libgtk-3-dev +Build-Depends: cmake (>= 3.10.2), dh-cmake, debhelper (>= 9), libusb-1.0-0-dev (>= 1.0.21), libgtk-3-dev (>= 3.22.30) Standards-Version: 4.5.0 Rules-Requires-Root: no Section: electronics diff --git a/contributors.txt b/contributors.txt index bcaa0b538..cffef89f6 100644 --- a/contributors.txt +++ b/contributors.txt @@ -7,6 +7,8 @@ Andrea Mucignat Andrew Andrianov [necromant] Andrey Yurovsky Andy Isaacson +Andreas Sandberg [andysan] +Antoine Faure [antoinefaure] Anton [Ant-ON] Áron Radics A. Sheaff @@ -24,6 +26,7 @@ Chris Samuelson Christian Deussen [nullsub] Christophe Levantis Craig Lilley +Crest [Crest] Dan Dev Dan Hepler Daniel Campoverde [alx741] diff --git a/doc/compiling.md b/doc/compiling.md index eef207f95..0931c278a 100644 --- a/doc/compiling.md +++ b/doc/compiling.md @@ -7,7 +7,7 @@ On Windows users should ensure that the following software is installed: - `git` (_optional, but recommended_) -- `cmake` (3.17.0 or later) +- `cmake` - `MinGW-w64` (7.0.0 or later) with GCC toolchain 8.1.0 ### Installation @@ -95,7 +95,7 @@ Install the following packages from your package repository: - `git` - `gcc` or `clang` or `mingw32-gcc` or `mingw64-gcc` (C-compiler; very likely gcc is already present) - `build-essential` (on Debian based distros (Debian, Ubuntu)) -- `cmake` (3.4.2 or later, use the latest version available from the repository) +- `cmake` - `rpm` (on Debian based distros (Debian, Ubuntu), needed for package build with `make package`) - `libusb-1.0` - `libusb-1.0-0-dev` (development headers for building) diff --git a/doc/version_support.md b/doc/version_support.md index 4eeb5074a..d7ba5c102 100644 --- a/doc/version_support.md +++ b/doc/version_support.md @@ -1,97 +1,104 @@ -_Source:_ pkgs.org - [libusb](https://pkgs.org/search/?q=libusb); [cmake](https://pkgs.org/search/?q=cmake); [gtk](https://pkgs.org/search/?q=gtk) (as of May 2021) +_Source:_ [pkgs.org](https://pkgs.org/search) - libusb, cmake, gtk, libgtk) (as of Jan 2022) ## Supported Operating Systems ### Microsoft Windows -On Windows users should ensure that cmake 3.20.2 or any later version is installed.
-Up on compiling c-make will **automatically** download and install the latest compatible version of `libusb` (1.0.23 at the time of writing). +On Windows users should ensure that cmake **3.10.2** or any later version is installed.
+Up on compiling c-make will **automatically** download and install the latest compatible version of `libusb`. - Windows 10 - Windows 8.1 ### Apple macOS -| Package Repository | libusb
version | cmake
version | gtk-3
version | Supported macOS versions | -| ------------------ | ------------------- | ------------------ | ------------------ | ------------------------ | -| homebrew | 1.0.24 | 3.20.2 | 3.24.29
gtk+3 | 10.9 - 11.x | -| MacPorts | 1.0.24 | 3.20.2 | 3.24.29
gtk3 | 10.4 - 11.x | +| Package Repository | libusb | cmake | gtk-3-dev | Supported macOS versions | +| ------------------ | ------ | ------ | ------------------ | ------------------------ | +| homebrew | 1.0.24 | 3.22.1 | 3.24.30
gtk+3 | **10.10 - 12.x** | +| MacPorts | 1.0.24 | 3.22.1 | 3.24.31
gtk3 | **10.4 - 12.x** | NOTE: In order to use a STLINK/V1 programmer on macOS, version 10.15 is required. ### Linux-/Unix-based: -| Operating System | libusb | cmake | gtk-3 | Notes | -| ------------------------- | -------------------------------- | --------- | ----------- | ------------------------ | -| Debian Sid | 1.0.24 | 3.18.4 | 3.24.24 | | -| Debian 11 (Bullseye) | 1.0.24 | 3.18.4 | 3.24.24 | | -| Debian 10 (Buster) | 1.0.**22** | 3.13.4 | 3.24.**5** | | -| Debian 9 (Stretch) | 1.0.**21** | **3.7.2** | **3.22.11** | End of Support: Jun 2022 | -| | | | | | -| Ubuntu 21.04 (Hirsute) | 1.0.24 | 3.18.4 | 3.24.25 | End of Support: Jan 2022 | -| Ubuntu 20.04 LTS (Focal) | 1.0.23 | 3.16.3 | 3.24.**18** | | -| Ubuntu 18.04 LTS (Bionic) | 1.0.**21** | 3.10.2 | **3.22.30** | End of Support: Apr 2023 | -| | | | | | -| Fedora Rawhide [x64] | 1.0.24 (`libusbx`) | 3.20.2 | 3.24.29 | | -| Fedora 34 [x64] | 1.0.24 (`libusbx`) | 3.19.7 | 3.24.28 | | -| Fedora 33 [x64] | 1.0.23 (`libusbx`) | 3.18.3 | 3.24.23 | | -| | | | | | -| openSUSE Tumbleweed [x64] | 1.0.24 | 3.20.1 | 3.24.29 | | -| openSUSE Leap 15.3 [x64] | 1.0.**21** | 3.17.0 | 3.24.20 | | -| openSUSE Leap 15.2 [x64] | 1.0.**21** | 3.17.0 | 3.24.**14** | End of Support: Dec 2021 | -| | | | | | -| Alpine 3.14 | 1.0.24 | 3.20.3 | 4.2.1 | | -| Alpine 3.13 | 1.0.24 | 3.18.4 | 3.24.23 | End of Support: Nov 2022 | -| Alpine 3.12 | 1.0.23 | 3.17.2 | 3.24.22 | End of Support: May 2022 | -| Alpine 3.11 | 1.0.23 | 3.15.5 | 3.24.**13** | End of Support: Nov 2021 | -| | | | | | -| FreeBSD 13.x | 1.0.**16 - 18** (API 0x01000102) | 3.20.2 | 3.24.27 | | -| FreeBSD 12.x | 1.0.**16 - 18** (API 0x01000102) | 3.19.6 | 3.24.27 | | -| FreeBSD 11.x | 1.0.**16 - 18** (API 0x01000102) | 3.15.5 | 3.24.27 | End of Support: Sep 2021 | -| | | | | | -| Arch Linux | 1.0.24 | 3.20.2 | 3.24.29 | | -| KaOS [x64] | 1.0.24 | 3.20.2 | 3.24.29 | | -| Mageia Cauldron | 1.0.24 | 3.20.2 | 3.24.29 | | -| OpenMandriva Cooker | 1.0.24 | 3.20.2 | 3.24.29 | | -| PCLinuxOS [x64] | 1.0.24 | 3.20.2 | 3.24.29 | | -| Slackware Current | 1.0.24 | 3.20.2 | 3.24.28 | | -| Solus [x64] | 1.0.24 | 3.20.2 | 3.24.29 | | -| ALT Linux Sisyphus | 1.0.24 | 3.19.7 | 3.24.29 | | -| NetBSD 9.x | 1.0.24 | 3.19.7 | 3.24.27 | | -| NetBSD 8.x | 1.0.24 | 3.19.7 | 3.24.27 | | -| OpenMandriva Lx 4.2 | 1.0.24 | 3.19.3 | 3.24.24 | | -| Mageia 8 | 1.0.24 | 3.19.2 | 3.24.24 | End of Support: Aug 2022 | -| CentOS 8 Stream [x64] | 1.0.23 (`libusbx`) | 3.18.2 | **3.22.30** | | -| Adélie 1.0 | 1.0.23 | 3.16.4 | 3.24.23 | | -| ALT Linux P9 | 1.0.**22** | 3.16.3 | 3.24.**11** | | -| AlmaLinux 8 | 1.0.23 (`libusbx`) | 3.11.4 | 3.24.32 | | -| CentOS 8 [x64] | 1.0.23 (`libusbx`) | 3.11.4 | **3.22.30** | End of Support: Dec 2021 | +| Operating System | libusb | cmake | libgtk-dev | Notes | +| ------------------------- | ------------------------------ | ---------- | ----------- | ------------------------ | +| Debian Sid | 1.0.24 | 3.22.1 | 3.24.31 | | +| Debian 11 (Bullseye) | 1.0.24 | 3.18.4 | 3.24.24 | | +| Debian 10 (Buster) | 1.0.**22** | **3.13.4** | 3.24.**5** | | +| | | | | | +| Ubuntu 20.04 LTS (Focal) | 1.0.23 | 3.16.3 | 3.24.**18** | | +| Ubuntu 18.04 LTS (Bionic) | 1.0.**21** | **3.10.2** | 3.**22.30** | End of Support: Apr 2023 | +| | | | | | +| Fedora Rawhide [x64] | 1.0.24 | 3.22.3 | 3.24.31 | | +| Fedora 35 [x64] | 1.0.24 | 3.21.3 | 3.24.30 | | +| Fedora 34 [x64] | 1.0.24 (`libusbx`) | 3.19.7 | 3.24.28 | | +| | | | | | +| openSUSE Tumbleweed [x64] | 1.0.24 | 3.22.1 | 3.24.31 | | +| openSUSE Leap 15.3 [x64] | 1.0.**21** | 3.17.0 | 3.24.20 | End of Support: Dec 2022 | +| | | | | | +| Alpine 3.15 | 1.0.24 | 3.21.3 | 3.24.30 | | +| Alpine 3.14 | 1.0.24 | 3.20.3 | 3.24.28 | | +| Alpine 3.13 | 1.0.24 | 3.18.4 | 3.24.23 | End of Support: Nov 2022 | +| Alpine 3.12 | 1.0.23 | 3.17.2 | 3.24.22 | End of Support: May 2022 | +| | | | | | +| FreeBSD 13.x | 1.0.**16-18** (API 0x01000102) | 3.22.1 | 3.24.31 | | +| FreeBSD 12.x | 1.0.**16-18** (API 0x01000102) | 3.22.1 | 3.24.31 | | +| | | | | | +| NetBSD 9.x | 1.0.24 | 3.21.2 | 3.24.30 | | +| NetBSD 8.x | 1.0.24 | 3.19.7 | 3.24.27 | | +| | | | | | +| CentOS 9 Stream [x64] | 1.0.24 (`libusbx`) | 3.20.3 | 3.24.30 | | +| CentOS 8 Stream [x64] | 1.0.23 (`libusbx`) | 3.20.2 | 3.**22.30** | | +| | | | | | +| ALT Linux Sisyphus | 1.0.24 | 3.22.1 | 3.24.31 | | +| ALT Linux P10 | 1.0.24 | 3.20.5 | 3.24.31 | | +| ALT Linux P9 | 1.0.**22** | 3.16.3 | 3.24.29 | | +| | | | | | +| OpenMandriva Rolling | 1.0.24 | 3.22.1 | 3.24.31 | | +| OpenMandriva Cooker | 1.0.24 | 3.22.1 | 3.24.31 | | +| OpenMandriva Lx 4.2 | 1.0.24 | 3.19.3 | 3.24.24 | | +| | | | | | +| Arch Linux | 1.0.24 | 3.22.1 | - | | +| KaOS [x64] | 1.0.24 | 3.22.1 | 3.24.31 | | +| Mageia Cauldron | 1.0.24 | 3.22.1 | 3.24.31 | | +| PCLinuxOS [x64] | ? | 3.22.1 | 3.24.31 | | +| Solus [x64] | 1.0.24 | 3.22.1 | 3.24.30 | | +| Void Linux | 1.0.24 | 3.22.1 | 3.24.31 | | +| Slackware Current | 1.0.24 | 3.21.4 | 3.24.31 | | +| AlmaLinux 8 | 1.0.23 (`libusbx`) | 3.20.2 | 3.**22.30** | | +| Rocky Linux 8 [x64] | 1.0.23 | 3.20.2 | 3.**22.30** | | +| Mageia 8 | 1.0.24 | 3.19.2 | 3.24.24 | End of Support: Aug 2022 | +| Adélie 1.0 | 1.0.23 | 3.16.4 | 3.24.23 | | ## Unsupported Operating Systems (as of Release v1.7.1) Systems with highlighted versions remain compatible with this toolset. -| Operating System | libusb | cmake | End of
OS-Support | -| ------------------------- | ---------------------- | ---------- | ---------------------- | -| Fedora 32 [x64] | **1.0.23** (`libusbx`) | **3.17.0** | May 2021 | -| Ubuntu 20.10 (Groovy) | **1.0.23** | **3.16.3** | Jul 2021 | -| NetBSD 7.x | **1.0.22** | **3.16.1** | Jun 2020 | -| Alpine 3.10 | **1.0.22** | **3.14.5** | May 2021 | -| Fedora 31 [x64] | **1.0.22** (`libusbx`) | **3.14.5** | Nov 2020 | -| Mageia 7.1 | **1.0.22** | **3.14.3** | Jun 2021 | -| Fedora 30 | **1.0.22** (`libusbx`) | **3.14.2** | May 2020 | -| Ubuntu 19.10 (Eoan) | **1.0.23** | **3.13.4** | Jul 2020 | -| Alpine 3.9 | **1.0.22** | **3.13.0** | Jan 2021 | -| openSUSE Leap 15.1 [x64] | **1.0.21** | **3.10.2** | Jan 2021 | -| Slackware 14.2 | 1.0.20 | 3.5.2 | | -| Ubuntu 16.04 LTS (Xenial) | 1.0.20 | 3.5.1 | Apr 2021 | -| OpenMandriva Lx 3.0x | 1.0.20 | 3.4.2 | | -| Debian 8 (Jessie) | 1.0.19 | 3.0.2 | Jun 2020 | -| CentOS 7 [x64] | 1.0.21 (`libusbx`) | 2.8.12.2 | Jun 2024 | -| Ubuntu 14.04 LTS (Trusty) | 1.0.17 | 2.8.12.2 | Apr 2019 | -| CentOS 6 | 1.0.9 (`libusbx`) | 2.8.12.2 | Nov 2020 | -| Slackware 14.1 | 1.0.9 | 2.8.12 | | -| Slackware 14.0 | 1.0.9 | 2.8.8 | | +| Operating System | libusb | cmake | End of
OS-Support | +| ------------------------ | ------------------------------ | ---------- | ---------------------- | +| CentOS 8 [x64] | 1.0.**23** (`libusbx`) | 3.**20.3** | Dec 2021 | +| Ubuntu 21.04 (Hirsute) | 1.0.**24** | 3.**18.4** | Jan 2022 | +| Fedora 33 [x64] | 1.0.**23** (`libusbx`) | 3.**18.3** | Nov 2021 | +| Fedora 32 [x64] | 1.0.**23** (`libusbx`) | 3.**17.0** | May 2021 | +| openSUSE Leap 15.2 [x64] | 1.0.**21** | 3.**17.0** | Dec 2021 | +| Ubuntu 20.10 (Groovy) | 1.0.**23** | 3.**16.3** | Jul 2021 | +| NetBSD 7.x | 1.0.**22** | 3.**16.1** | Jun 2020 | +| Alpine 3.11 | 1.0.**23** | 3.**15.5** | Nov 2021 | +| FreeBSD 11.x | 1.0.**16-18** (API 0x01000102) | 3.**15.5** | Sep 2021 | +| Alpine 3.10 | 1.0.**22** | 3.**14.5** | May 2021 | +| Fedora 31 [x64] | 1.0.**22**(`libusbx`) | 3.**14.5** | Nov 2020 | +| Mageia 7.1 | 1.0.**22** | 3.**14.3** | Jun 2021 | +| Fedora 30 | 1.0.**22**(`libusbx`) | 3.**14.2** | May 2020 | +| Ubuntu 19.10 (Eoan) | 1.0.**23** | 3.**13.4** | Jul 2020 | +| Alpine 3.9 | 1.0.**22** | 3.**13.0** | Jan 2021 | +| openSUSE Leap 15.1 [x64] | 1.0.**21** | 3.**10.2** | Jan 2021 | +| Debian 9 (Stretch) | 1.0.**21** | 3.7.2 | Jun 2022 | +| Slackware 14.2 | 1.0.20 | 3.5.2 | | +| OpenMandriva Lx 3.0x | 1.0.20 | 3.4.2 | | +| CentOS 7 [x64] | 1.0.**21** (`libusbx`) | 2.8.12.2 | Jun 2024 | +| Slackware 14.1 | 1.0.9 | 2.8.12 | | +| Slackware 14.0 | 1.0.9 | 2.8.8 | | _All other operating systems which are not listed are unsupported._ From 75092952226682788c394e12c2b90ec121b2054a Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 16 Jan 2022 19:31:22 +0100 Subject: [PATCH 355/503] [refactoring] Clean-up for headers & defines - Removed additional extern "C" linkage specs - Removed commented sections - Moved out further device specific defines - Renamed defines STM32_CHIP_ID_* --- config/chips/F03x.chip | 2 +- config/chips/F04x.chip | 2 +- config/chips/F05x.chip | 2 +- config/chips/F07x.chip | 2 +- config/chips/F09x.chip | 2 +- config/chips/F1xx_CL.chip | 2 +- config/chips/F1xx_HD.chip | 2 +- config/chips/F1xx_LD.chip | 2 +- config/chips/F1xx_MD.chip | 2 +- config/chips/F1xx_VL_HD.chip | 2 +- config/chips/F1xx_VL_MD_LD.chip | 2 +- config/chips/F1xx_XLD.chip | 2 +- config/chips/F2xx.chip | 2 +- config/chips/F301_F302_F318.chip | 2 +- config/chips/F302_F303_F358.chip | 2 +- config/chips/F302_F303_F398_HD.chip | 2 +- config/chips/F303_F328_F334.chip | 2 +- config/chips/F37x.chip | 2 +- config/chips/F401xB_xC.chip | 2 +- config/chips/F401xD_xE.chip | 2 +- config/chips/F410.chip | 2 +- config/chips/F411xC_xE.chip | 2 +- config/chips/F412.chip | 2 +- config/chips/F413_F423.chip | 2 +- config/chips/F42x_F43x.chip | 2 +- config/chips/F446.chip | 2 +- config/chips/F46x_F47x.chip | 2 +- config/chips/F4x5_F4x7.chip | 2 +- config/chips/F72x_F73x.chip | 2 +- config/chips/F74x_F75x.chip | 2 +- config/chips/F76x_F77x.chip | 2 +- config/chips/G03x_G04x.chip | 2 +- config/chips/G05x_G06x.chip | 2 +- config/chips/G07x_G08x.chip | 2 +- config/chips/G0Bx_G0Cx.chip | 2 +- config/chips/G43x_G44x.chip | 2 +- config/chips/G47x_G48x.chip | 2 +- config/chips/G49x_G4Ax.chip | 2 +- config/chips/H72x_H73x.chip | 2 +- config/chips/H74x_H75x.chip | 2 +- config/chips/H7Ax_H7Bx.chip | 2 +- config/chips/L0xxx_Cat_1.chip | 2 +- config/chips/L0xxx_Cat_2.chip | 2 +- config/chips/L0xxx_Cat_3.chip | 2 +- config/chips/L0xxx_Cat_5.chip | 2 +- config/chips/L1xx_Cat_1.chip | 2 +- config/chips/L1xx_Cat_2.chip | 2 +- config/chips/L1xx_Cat_3.chip | 2 +- config/chips/L1xx_Cat_4.chip | 2 +- config/chips/L1xx_Cat_5.chip | 2 +- config/chips/L41x_L42x.chip | 2 +- config/chips/L43x_L44x.chip | 2 +- config/chips/L45x_L46x.chip | 2 +- config/chips/L47x_L48x.chip | 2 +- config/chips/L496x_L4A6x.chip | 2 +- config/chips/L4Px.chip | 2 +- config/chips/L4Rx.chip | 2 +- config/chips/WBx0_WBx5.chip | 2 +- config/chips/WLx5.chip | 2 +- inc/stlink.h | 17 - inc/stm32.h | 514 ++++++++++++++++++++++++---- src/common.c | 473 +++---------------------- src/st-util/gdb-server.c | 24 +- src/stlink-lib/chipid.c | 74 ---- src/stlink-lib/chipid.h | 6 - src/stlink-lib/flash_loader.c | 92 ++--- src/stlink-lib/flash_loader.h | 6 - src/stlink-lib/sg.h | 6 - src/stlink-lib/usb.h | 6 - src/win32/mmap.h | 6 - src/win32/sys_time.h | 7 - 71 files changed, 612 insertions(+), 737 deletions(-) diff --git a/config/chips/F03x.chip b/config/chips/F03x.chip index 3b4ff2a74..c0a6e5200 100644 --- a/config/chips/F03x.chip +++ b/config/chips/F03x.chip @@ -2,7 +2,7 @@ # dev_type STM32F03x ref_manual_id 0091 -chip_id 0x444 // STM32_CHIPID_STM32_F0xx_SMALL +chip_id 0x444 // STM32_CHIPID_F0xx_SMALL flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3 flash_size_reg 0x1ffff7cc flash_pagesize 0x400 // 1 KB diff --git a/config/chips/F04x.chip b/config/chips/F04x.chip index 267c93765..9b2ee5586 100644 --- a/config/chips/F04x.chip +++ b/config/chips/F04x.chip @@ -2,7 +2,7 @@ # dev_type STM32F04x ref_manual_id 0091 -chip_id 0x445 // STM32_CHIPID_STM32_F04 +chip_id 0x445 // STM32_CHIPID_F04 flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3 flash_size_reg 0x1ffff7cc flash_pagesize 0x400 // 1 KB diff --git a/config/chips/F05x.chip b/config/chips/F05x.chip index dc511e1a2..c32ba0b46 100644 --- a/config/chips/F05x.chip +++ b/config/chips/F05x.chip @@ -2,7 +2,7 @@ # dev_type STM32F05x ref_manual_id 0091 -chip_id 0x440 // STM32_CHIPID_STM32_F0 +chip_id 0x440 // STM32_CHIPID_F0 flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3 flash_size_reg 0x1ffff7cc flash_pagesize 0x400 // 1 KB diff --git a/config/chips/F07x.chip b/config/chips/F07x.chip index b12ef1bab..5ba832058 100644 --- a/config/chips/F07x.chip +++ b/config/chips/F07x.chip @@ -2,7 +2,7 @@ # dev_type STM32F07x ref_manual_id 0091 -chip_id 0x448 // STM32_CHIPID_STM32_F0_CAN +chip_id 0x448 // STM32_CHIPID_F0_CAN flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3 flash_size_reg 0x1ffff7cc flash_pagesize 0x800 // 2 KB diff --git a/config/chips/F09x.chip b/config/chips/F09x.chip index 97f1a1a75..ca987123d 100644 --- a/config/chips/F09x.chip +++ b/config/chips/F09x.chip @@ -2,7 +2,7 @@ # dev_type STM32F09x ref_manual_id 0091 -chip_id 0x442 // STM32_CHIPID_STM32_F09x +chip_id 0x442 // STM32_CHIPID_F09x flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3 flash_size_reg 0x1ffff7cc flash_pagesize 0x800 // 2 KB diff --git a/config/chips/F1xx_CL.chip b/config/chips/F1xx_CL.chip index dd316dca3..0f56362f0 100644 --- a/config/chips/F1xx_CL.chip +++ b/config/chips/F1xx_CL.chip @@ -2,7 +2,7 @@ # dev_type STM32F1xx_CL ref_manual_id 0008 -chip_id 0x418 // STM32_CHIPID_STM32_F1_CONN +chip_id 0x418 // STM32_CHIPID_F1_CONN flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3 flash_size_reg 0x1ffff7e0 flash_pagesize 0x800 // 2 KB diff --git a/config/chips/F1xx_HD.chip b/config/chips/F1xx_HD.chip index 696b284ba..2af8582e6 100644 --- a/config/chips/F1xx_HD.chip +++ b/config/chips/F1xx_HD.chip @@ -2,7 +2,7 @@ # dev_type F1xx_HD ref_manual_id 0008 -chip_id 0x414 // STM32_CHIPID_STM32_F1_HD +chip_id 0x414 // STM32_CHIPID_F1_HD flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3 flash_size_reg 0x1ffff7e0 flash_pagesize 0x800 // 2 KB diff --git a/config/chips/F1xx_LD.chip b/config/chips/F1xx_LD.chip index 898af4c8c..ffd34fd4a 100644 --- a/config/chips/F1xx_LD.chip +++ b/config/chips/F1xx_LD.chip @@ -2,7 +2,7 @@ # dev_type STM32F1xx_LD ref_manual_id 0008 -chip_id 0x412 // STM32_CHIPID_STM32_F1_LD +chip_id 0x412 // STM32_CHIPID_F1_LD flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3 flash_size_reg 0x1ffff7e0 flash_pagesize 0x400 // 1 KB diff --git a/config/chips/F1xx_MD.chip b/config/chips/F1xx_MD.chip index a611f3f2d..f27a7a062 100644 --- a/config/chips/F1xx_MD.chip +++ b/config/chips/F1xx_MD.chip @@ -2,7 +2,7 @@ # dev_type STM32F1xx_MD ref_manual_id 0008 -chip_id 0x410 // STM32_CHIPID_STM32_F1_MD +chip_id 0x410 // STM32_CHIPID_F1_MD flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3 flash_size_reg 0x1ffff7e0 flash_pagesize 0x400 // 1 KB diff --git a/config/chips/F1xx_VL_HD.chip b/config/chips/F1xx_VL_HD.chip index d59fa4814..4f2566949 100644 --- a/config/chips/F1xx_VL_HD.chip +++ b/config/chips/F1xx_VL_HD.chip @@ -2,7 +2,7 @@ # dev_type STM32F1xx_VL_HD ref_manual_id 0041 -chip_id 0x428 // STM32_CHIPID_STM32_F1_VL_HD +chip_id 0x428 // STM32_CHIPID_F1_VL_HD flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3 flash_size_reg 0x1ffff7e0 flash_pagesize 0x800 // 2 KB diff --git a/config/chips/F1xx_VL_MD_LD.chip b/config/chips/F1xx_VL_MD_LD.chip index aac2244fd..1705bc8e3 100644 --- a/config/chips/F1xx_VL_MD_LD.chip +++ b/config/chips/F1xx_VL_MD_LD.chip @@ -2,7 +2,7 @@ # dev_type STM32F1xx_VL_MD_LD ref_manual_id 0041 -chip_id 0x420 // STM32_CHIPID_STM32_F1_VL_MD_LD +chip_id 0x420 // STM32_CHIPID_F1_VL_MD_LD flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3 flash_size_reg 0x1ffff7e0 flash_pagesize 0x400 // 1 KB diff --git a/config/chips/F1xx_XLD.chip b/config/chips/F1xx_XLD.chip index 7627dd883..37c900f28 100644 --- a/config/chips/F1xx_XLD.chip +++ b/config/chips/F1xx_XLD.chip @@ -2,7 +2,7 @@ # dev_type STM32F1xx_XLD ref_manual_id 0008 -chip_id 0x430 // STM32_CHIPID_STM32_F1_XLD +chip_id 0x430 // STM32_CHIPID_F1_XLD flash_type 2 // STM32_FLASH_TYPE_F1_XL flash_size_reg 0x1ffff7e0 flash_pagesize 0x800 // 2 KB diff --git a/config/chips/F2xx.chip b/config/chips/F2xx.chip index 5e6aac5a0..314df7d6d 100644 --- a/config/chips/F2xx.chip +++ b/config/chips/F2xx.chip @@ -2,7 +2,7 @@ # dev_type STM32F2xx ref_manual_id 0033 -chip_id 0x411 // STM32_CHIPID_STM32_F2 +chip_id 0x411 // STM32_CHIPID_F2 flash_type 3 // STM32_FLASH_TYPE_F2_F4 flash_size_reg 0x1fff7a22 flash_pagesize 0x20000 // 128 KB diff --git a/config/chips/F301_F302_F318.chip b/config/chips/F301_F302_F318.chip index 3a3d8bb45..f620364b2 100644 --- a/config/chips/F301_F302_F318.chip +++ b/config/chips/F301_F302_F318.chip @@ -2,7 +2,7 @@ # dev_type STM32F301_F302_F318 ref_manual_id 0365 // also RM0366 -chip_id 0x439 // STM32_CHIPID_STM32_F3xx_SMALL +chip_id 0x439 // STM32_CHIPID_F3xx_SMALL flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3 flash_size_reg 0x1ffff7cc flash_pagesize 0x800 // 2 KB diff --git a/config/chips/F302_F303_F358.chip b/config/chips/F302_F303_F358.chip index 922387292..e48370159 100644 --- a/config/chips/F302_F303_F358.chip +++ b/config/chips/F302_F303_F358.chip @@ -2,7 +2,7 @@ # dev_type STM32F302_F303_358 ref_manual_id 0365 // also RM0316 -chip_id 0x422 // STM32_CHIPID_STM32_F3 +chip_id 0x422 // STM32_CHIPID_F3 flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3 flash_size_reg 0x1ffff7cc flash_pagesize 0x800 // 2 KB diff --git a/config/chips/F302_F303_F398_HD.chip b/config/chips/F302_F303_F398_HD.chip index 44cec8a6d..181fdfa72 100644 --- a/config/chips/F302_F303_F398_HD.chip +++ b/config/chips/F302_F303_F398_HD.chip @@ -2,7 +2,7 @@ # dev_type STM32F302_F303_F398_HD ref_manual_id 0365 // also RM0316 (Rev 5) -chip_id 0x446 // STM32_CHIPID_STM32_F303_HD +chip_id 0x446 // STM32_CHIPID_F303_HD flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3 flash_size_reg 0x1ffff7cc flash_pagesize 0x800 // 2 KB diff --git a/config/chips/F303_F328_F334.chip b/config/chips/F303_F328_F334.chip index fb77e3117..069de07fb 100644 --- a/config/chips/F303_F328_F334.chip +++ b/config/chips/F303_F328_F334.chip @@ -2,7 +2,7 @@ # dev_type STM32F303_F328_F334 ref_manual_id 0364 // also RM0316 -chip_id 0x438 // STM32_CHIPID_STM32_F334 +chip_id 0x438 // STM32_CHIPID_F334 flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3 flash_size_reg 0x1ffff7cc flash_pagesize 0x800 // 2 KB diff --git a/config/chips/F37x.chip b/config/chips/F37x.chip index 5363da8fa..dfe59af0f 100644 --- a/config/chips/F37x.chip +++ b/config/chips/F37x.chip @@ -2,7 +2,7 @@ # dev_type STM32F37x ref_manual_id 0313 -chip_id 0x432 // STM32_CHIPID_STM32_F37x +chip_id 0x432 // STM32_CHIPID_F37x flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3 flash_size_reg 0x1ffff7cc flash_pagesize 0x800 // 2 KB diff --git a/config/chips/F401xB_xC.chip b/config/chips/F401xB_xC.chip index e75b27d09..d961e82b0 100644 --- a/config/chips/F401xB_xC.chip +++ b/config/chips/F401xB_xC.chip @@ -2,7 +2,7 @@ # dev_type STM32F401xB_xC ref_manual_id 0368 -chip_id 0x423 // STM32_CHIPID_STM32_F4_LP +chip_id 0x423 // STM32_CHIPID_F4_LP flash_type 3 // STM32_FLASH_TYPE_F2_F4 flash_size_reg 0x1fff7a22 flash_pagesize 0x4000 // 16 KB diff --git a/config/chips/F401xD_xE.chip b/config/chips/F401xD_xE.chip index 022d5072a..1b58cb5ad 100644 --- a/config/chips/F401xD_xE.chip +++ b/config/chips/F401xD_xE.chip @@ -2,7 +2,7 @@ # dev_type STM32F401xD_xE ref_manual_id 0368 -chip_id 0x433 // STM32_CHIPID_STM32_F4_DE +chip_id 0x433 // STM32_CHIPID_F4_DE flash_type 3 // STM32_FLASH_TYPE_F2_F4 flash_size_reg 0x1fff7a22 flash_pagesize 0x4000 // 16 KB diff --git a/config/chips/F410.chip b/config/chips/F410.chip index 84c9c00bf..55dbb749d 100644 --- a/config/chips/F410.chip +++ b/config/chips/F410.chip @@ -2,7 +2,7 @@ # dev_type STM32F410 ref_manual_id 0401 -chip_id 0x458 // STM32_CHIPID_STM32_F410 +chip_id 0x458 // STM32_CHIPID_F410 flash_type 3 // STM32_FLASH_TYPE_F2_F4 flash_size_reg 0x1fff7a22 flash_pagesize 0x4000 // 16 KB diff --git a/config/chips/F411xC_xE.chip b/config/chips/F411xC_xE.chip index d028a874c..51081d338 100644 --- a/config/chips/F411xC_xE.chip +++ b/config/chips/F411xC_xE.chip @@ -2,7 +2,7 @@ # dev_type STM32F411xC_xE ref_manual_id 0383 -chip_id 0x431 // STM32_CHIPID_STM32_F411xx +chip_id 0x431 // STM32_CHIPID_F411xx flash_type 3 // STM32_FLASH_TYPE_F2_F4 flash_size_reg 0x1fff7a22 flash_pagesize 0x4000 // 16 KB diff --git a/config/chips/F412.chip b/config/chips/F412.chip index b4c1cb418..6e7aefd19 100644 --- a/config/chips/F412.chip +++ b/config/chips/F412.chip @@ -2,7 +2,7 @@ # dev_type STM32F412 ref_manual_id 0402 -chip_id 0x441 // STM32_CHIPID_STM32_F412 +chip_id 0x441 // STM32_CHIPID_F412 flash_type 3 // STM32_FLASH_TYPE_F2_F4 flash_size_reg 0x1fff7a22 flash_pagesize 0x4000 // 16 KB diff --git a/config/chips/F413_F423.chip b/config/chips/F413_F423.chip index f042bce76..3a865d304 100644 --- a/config/chips/F413_F423.chip +++ b/config/chips/F413_F423.chip @@ -2,7 +2,7 @@ # dev_type STM32F413_F423 ref_manual_id 0430 // RM0430 (Rev 2) -chip_id 0x463 // STM32_CHIPID_STM32_F413 +chip_id 0x463 // STM32_CHIPID_F413 flash_type 3 // STM32_FLASH_TYPE_F2_F4 flash_size_reg 0x1fff7a22 flash_pagesize 0x4000 // 16 KB diff --git a/config/chips/F42x_F43x.chip b/config/chips/F42x_F43x.chip index 69aff7c88..64f459064 100644 --- a/config/chips/F42x_F43x.chip +++ b/config/chips/F42x_F43x.chip @@ -2,7 +2,7 @@ # dev_type STM32F42x_F43x ref_manual_id 0090 // RM0090 (Rev. 2) -chip_id 0x463 // STM32_CHIPID_STM32_F4_HD +chip_id 0x463 // STM32_CHIPID_F4_HD flash_type 3 // STM32_FLASH_TYPE_F2_F4 flash_size_reg 0x1fff7a22 flash_pagesize 0x4000 // 16 KB diff --git a/config/chips/F446.chip b/config/chips/F446.chip index 5fa2edbcb..51ee52517 100644 --- a/config/chips/F446.chip +++ b/config/chips/F446.chip @@ -2,7 +2,7 @@ # dev_type STM32F446 ref_manual_id 0390 -chip_id 0x421 // STM32_CHIPID_STM32_F446 +chip_id 0x421 // STM32_CHIPID_F446 flash_type 3 // STM32_FLASH_TYPE_F2_F4 flash_size_reg 0x1fff7a22 flash_pagesize 0x20000 // 128 KB diff --git a/config/chips/F46x_F47x.chip b/config/chips/F46x_F47x.chip index e8364ead5..4d3931091 100644 --- a/config/chips/F46x_F47x.chip +++ b/config/chips/F46x_F47x.chip @@ -2,7 +2,7 @@ # dev_type STM32F46x_F47x ref_manual_id 0090 // RM0090 (Rev. 2) -chip_id 0x434 // STM32_CHIPID_STM32_F4_DSI +chip_id 0x434 // STM32_CHIPID_F4_DSI flash_type 3 // STM32_FLASH_TYPE_F2_F4 flash_size_reg 0x1fff7a22 flash_pagesize 0x4000 // 16 KB diff --git a/config/chips/F4x5_F4x7.chip b/config/chips/F4x5_F4x7.chip index e78b552c4..f65281272 100644 --- a/config/chips/F4x5_F4x7.chip +++ b/config/chips/F4x5_F4x7.chip @@ -2,7 +2,7 @@ # dev_type STM32F4x5_F4x7 ref_manual_id 0090 // RM0090 (Rev. 2) -chip_id 0x413 // STM32_CHIPID_STM32_F4 +chip_id 0x413 // STM32_CHIPID_F4 flash_type 3 // STM32_FLASH_TYPE_F2_F4 flash_size_reg 0x1fff7a22 flash_pagesize 0x4000 // 16 KB diff --git a/config/chips/F72x_F73x.chip b/config/chips/F72x_F73x.chip index 5e1131d2e..acd411bed 100644 --- a/config/chips/F72x_F73x.chip +++ b/config/chips/F72x_F73x.chip @@ -2,7 +2,7 @@ # dev_type STM32F72x_F73x ref_manual_id 0431 -chip_id 0x452 // STM32_CHIPID_STM32_F72xxx +chip_id 0x452 // STM32_CHIPID_F72xxx flash_type 4 // STM32_FLASH_TYPE_F7 flash_size_reg 0x1ff07a22 flash_pagesize 0x800 // 2 KB diff --git a/config/chips/F74x_F75x.chip b/config/chips/F74x_F75x.chip index 391ae124d..e081da39d 100644 --- a/config/chips/F74x_F75x.chip +++ b/config/chips/F74x_F75x.chip @@ -2,7 +2,7 @@ # dev_type STM32F74x_F75x ref_manual_id 0385 -chip_id 0x449 // STM32_CHIPID_STM32_F7 +chip_id 0x449 // STM32_CHIPID_F7 flash_type 4 // STM32_FLASH_TYPE_F7 flash_size_reg 0x1ff0f442 flash_pagesize 0x800 // 2 KB diff --git a/config/chips/F76x_F77x.chip b/config/chips/F76x_F77x.chip index bb87dce7a..c6d04ff78 100644 --- a/config/chips/F76x_F77x.chip +++ b/config/chips/F76x_F77x.chip @@ -2,7 +2,7 @@ # dev_type STM32F76x_F77x ref_manual_id 0410 -chip_id 0x451 // STM32_CHIPID_STM32_F76xxx +chip_id 0x451 // STM32_CHIPID_F76xxx flash_type 4 // STM32_FLASH_TYPE_F7 flash_size_reg 0x1ff0f442 flash_pagesize 0x800 // 2 KB diff --git a/config/chips/G03x_G04x.chip b/config/chips/G03x_G04x.chip index 4a7e11fcd..fd6dc3bcf 100644 --- a/config/chips/G03x_G04x.chip +++ b/config/chips/G03x_G04x.chip @@ -2,7 +2,7 @@ # dev_type STM32G03x_G04x ref_manual_id 0444 // also RM454 -chip_id 0x466 // STM32_CHIPID_STM32_G0_CAT1 +chip_id 0x466 // STM32_CHIPID_G0_CAT1 flash_type 5 // STM32_FLASH_TYPE_G0 flash_size_reg 0x1fff75e0 flash_pagesize 0x800 // 2 KB diff --git a/config/chips/G05x_G06x.chip b/config/chips/G05x_G06x.chip index 81f97b58d..ce5e52de4 100644 --- a/config/chips/G05x_G06x.chip +++ b/config/chips/G05x_G06x.chip @@ -2,7 +2,7 @@ # dev_type STM32G05x_G06x ref_manual_id 0444 -chip_id 0x456 // STM32_CHIPID_STM32_G0_CAT4 +chip_id 0x456 // STM32_CHIPID_G0_CAT4 flash_type 5 // STM32_FLASH_TYPE_G0 flash_size_reg 0x1fff75e0 flash_pagesize 0x800 // 2 KB diff --git a/config/chips/G07x_G08x.chip b/config/chips/G07x_G08x.chip index cac804a78..7a10fc052 100644 --- a/config/chips/G07x_G08x.chip +++ b/config/chips/G07x_G08x.chip @@ -2,7 +2,7 @@ # dev_type STM32G07x_G08x ref_manual_id 0444 -chip_id 0x460 // STM32_CHIPID_STM32_G0_CAT2 +chip_id 0x460 // STM32_CHIPID_G0_CAT2 flash_type 5 // STM32_FLASH_TYPE_G0 flash_size_reg 0x1fff75e0 flash_pagesize 0x800 // 2 KB diff --git a/config/chips/G0Bx_G0Cx.chip b/config/chips/G0Bx_G0Cx.chip index 845cf8280..6ab8ca55a 100644 --- a/config/chips/G0Bx_G0Cx.chip +++ b/config/chips/G0Bx_G0Cx.chip @@ -2,7 +2,7 @@ # dev_type STM32G0Bx_G0Cx ref_manual_id 0444 -chip_id 0x467 // STM32_CHIPID_STM32_G0_CAT3 +chip_id 0x467 // STM32_CHIPID_G0_CAT3 flash_type 5 // STM32_FLASH_TYPE_G0 flash_size_reg 0x1fff75e0 flash_pagesize 0x800 // 2 KB diff --git a/config/chips/G43x_G44x.chip b/config/chips/G43x_G44x.chip index 6b19d4fb4..a7eb86d34 100644 --- a/config/chips/G43x_G44x.chip +++ b/config/chips/G43x_G44x.chip @@ -2,7 +2,7 @@ # dev_type STM32G43x_G44x ref_manual_id 0440 -chip_id 0x468 // STM32_CHIPID_STM32_G4_CAT2 +chip_id 0x468 // STM32_CHIPID_G4_CAT2 flash_type 6 // STM32_FLASH_TYPE_G4 flash_size_reg 0x1fff75e0 flash_pagesize 0x800 // 2 KB diff --git a/config/chips/G47x_G48x.chip b/config/chips/G47x_G48x.chip index d3330da59..1b2b386fd 100644 --- a/config/chips/G47x_G48x.chip +++ b/config/chips/G47x_G48x.chip @@ -2,7 +2,7 @@ # dev_type STM32G47x_G48x ref_manual_id 0440 -chip_id 0x469 // STM32_CHIPID_STM32_G4_CAT3 +chip_id 0x469 // STM32_CHIPID_G4_CAT3 flash_type 6 // STM32_FLASH_TYPE_G4 flash_size_reg 0x1fff75e0 flash_pagesize 0x800 // 2 KB diff --git a/config/chips/G49x_G4Ax.chip b/config/chips/G49x_G4Ax.chip index a39237142..1defbfff8 100644 --- a/config/chips/G49x_G4Ax.chip +++ b/config/chips/G49x_G4Ax.chip @@ -2,7 +2,7 @@ # dev_type STM32G49x_G4Ax ref_manual_id 0440 -chip_id 0x479 // STM32_CHIPID_STM32_G4_CAT4 +chip_id 0x479 // STM32_CHIPID_G4_CAT4 flash_type 6 // STM32_FLASH_TYPE_G4 flash_size_reg 0x1fff75e0 flash_pagesize 0x800 // 2 KB diff --git a/config/chips/H72x_H73x.chip b/config/chips/H72x_H73x.chip index 998aa9812..50925fdcd 100644 --- a/config/chips/H72x_H73x.chip +++ b/config/chips/H72x_H73x.chip @@ -2,7 +2,7 @@ # dev_type STM32H72x_H73x ref_manual_id 0468 -chip_id 0x483 // STM32_CHIPID_STM32_H72x +chip_id 0x483 // STM32_CHIPID_H72x flash_type 7 // STM32_FLASH_TYPE_H7 flash_size_reg 0x1ff1e880 flash_pagesize 0x20000 // 128 KB diff --git a/config/chips/H74x_H75x.chip b/config/chips/H74x_H75x.chip index 0bfea13a4..20bfcd2cb 100644 --- a/config/chips/H74x_H75x.chip +++ b/config/chips/H74x_H75x.chip @@ -2,7 +2,7 @@ # dev_type STM32H74x_H75x ref_manual_id 0433 -chip_id 0x450 // STM32_CHIPID_STM32_H74xxx +chip_id 0x450 // STM32_CHIPID_H74xxx flash_type 7 // STM32_FLASH_TYPE_H7 flash_size_reg 0x1ff1e880 flash_pagesize 0x20000 // 128 KB diff --git a/config/chips/H7Ax_H7Bx.chip b/config/chips/H7Ax_H7Bx.chip index 2e784193c..b31e4fb88 100644 --- a/config/chips/H7Ax_H7Bx.chip +++ b/config/chips/H7Ax_H7Bx.chip @@ -2,7 +2,7 @@ # dev_type STM32H7Ax_H7Bx ref_manual_id 0455 -chip_id 0x480 // STM32_CHIPID_STM32_H7Ax +chip_id 0x480 // STM32_CHIPID_H7Ax flash_type 7 // STM32_FLASH_TYPE_H7 flash_size_reg 0x08fff80c flash_pagesize 0x2000 // 8 KB diff --git a/config/chips/L0xxx_Cat_1.chip b/config/chips/L0xxx_Cat_1.chip index 4b108b4f4..d612143d5 100644 --- a/config/chips/L0xxx_Cat_1.chip +++ b/config/chips/L0xxx_Cat_1.chip @@ -2,7 +2,7 @@ # dev_type STM32L0xxx_Cat_1 ref_manual_id 0451 // also RM0377 -chip_id 0x457 // STM32_CHIPID_STM32_L011 +chip_id 0x457 // STM32_CHIPID_L011 flash_type 8 // STM32_FLASH_TYPE_L0_L1 flash_size_reg 0x1ff8007c flash_pagesize 0x80 // 128 B diff --git a/config/chips/L0xxx_Cat_2.chip b/config/chips/L0xxx_Cat_2.chip index 5665e8df1..49d3e8b07 100644 --- a/config/chips/L0xxx_Cat_2.chip +++ b/config/chips/L0xxx_Cat_2.chip @@ -2,7 +2,7 @@ # dev_type STM32L0xxx_Cat_2 ref_manual_id 0451 // also RM0377 -chip_id 0x425 // STM32_CHIPID_STM32_L0_CAT2 +chip_id 0x425 // STM32_CHIPID_L0_CAT2 flash_type 8 // STM32_FLASH_TYPE_L0_L1 flash_size_reg 0x1ff8007c flash_pagesize 0x80 // 128 B diff --git a/config/chips/L0xxx_Cat_3.chip b/config/chips/L0xxx_Cat_3.chip index e8cd7c685..c1b6c3bf4 100644 --- a/config/chips/L0xxx_Cat_3.chip +++ b/config/chips/L0xxx_Cat_3.chip @@ -2,7 +2,7 @@ # dev_type STM32L0xxx_Cat_3 ref_manual_id 0451 // also RM0367 & RM0377 -chip_id 0x417 // STM32_CHIPID_STM32_L0 +chip_id 0x417 // STM32_CHIPID_L0 flash_type 8 // STM32_FLASH_TYPE_L0_L1 flash_size_reg 0x1ff8007c flash_pagesize 0x80 // 128 B diff --git a/config/chips/L0xxx_Cat_5.chip b/config/chips/L0xxx_Cat_5.chip index 284057091..94e14dfe0 100644 --- a/config/chips/L0xxx_Cat_5.chip +++ b/config/chips/L0xxx_Cat_5.chip @@ -2,7 +2,7 @@ # dev_type STM32L0xxx_Cat_5 ref_manual_id 0451 // also RM0367 & RM0377 -chip_id 0x447 // STM32_CHIPID_STM32_L0_CAT5 +chip_id 0x447 // STM32_CHIPID_L0_CAT5 flash_type 8 // STM32_FLASH_TYPE_L0_L1 flash_size_reg 0x1ff8007c flash_pagesize 0x80 // 128 B diff --git a/config/chips/L1xx_Cat_1.chip b/config/chips/L1xx_Cat_1.chip index f6a11288f..16f2ff8c9 100644 --- a/config/chips/L1xx_Cat_1.chip +++ b/config/chips/L1xx_Cat_1.chip @@ -2,7 +2,7 @@ # dev_type STM32L1xx_Cat_1 ref_manual_id 0038 -chip_id 0x416 // STM32_CHIPID_STM32_L1_MD +chip_id 0x416 // STM32_CHIPID_L1_MD flash_type 8 // STM32_FLASH_TYPE_L0_L1 flash_size_reg 0x1ff8004c flash_pagesize 0x100 // 128 B diff --git a/config/chips/L1xx_Cat_2.chip b/config/chips/L1xx_Cat_2.chip index c8c796111..82d7dfe44 100644 --- a/config/chips/L1xx_Cat_2.chip +++ b/config/chips/L1xx_Cat_2.chip @@ -2,7 +2,7 @@ # dev_type STM32L1xx_Cat_2 ref_manual_id 0038 -chip_id 0x429 // STM32_CHIPID_STM32_L1_CAT2 +chip_id 0x429 // STM32_CHIPID_L1_CAT2 flash_type 8 // STM32_FLASH_TYPE_L0_L1 flash_size_reg 0x1ff8004c flash_pagesize 0x100 // 128 B diff --git a/config/chips/L1xx_Cat_3.chip b/config/chips/L1xx_Cat_3.chip index f2615f952..2241e5bde 100644 --- a/config/chips/L1xx_Cat_3.chip +++ b/config/chips/L1xx_Cat_3.chip @@ -2,7 +2,7 @@ # dev_type STM32L1xx_Cat_3 ref_manual_id 0038 -chip_id 0x427 // STM32_CHIPID_STM32_L1_MD_PLUS +chip_id 0x427 // STM32_CHIPID_L1_MD_PLUS flash_type 8 // STM32_FLASH_TYPE_L0_L1 flash_size_reg 0x1ff800cc flash_pagesize 0x100 // 128 B diff --git a/config/chips/L1xx_Cat_4.chip b/config/chips/L1xx_Cat_4.chip index 6a1df1267..7933d7121 100644 --- a/config/chips/L1xx_Cat_4.chip +++ b/config/chips/L1xx_Cat_4.chip @@ -2,7 +2,7 @@ # dev_type STM32L1xx_Cat_4 ref_manual_id 0038 -chip_id 0x436 // STM32_CHIPID_STM32_L1_MD_PLUS_HD +chip_id 0x436 // STM32_CHIPID_L1_MD_PLUS_HD flash_type 8 // STM32_FLASH_TYPE_L0_L1 flash_size_reg 0x1ff800cc flash_pagesize 0x100 // 128 B diff --git a/config/chips/L1xx_Cat_5.chip b/config/chips/L1xx_Cat_5.chip index 4fccd99da..0e95e54e8 100644 --- a/config/chips/L1xx_Cat_5.chip +++ b/config/chips/L1xx_Cat_5.chip @@ -2,7 +2,7 @@ # dev_type STM32L1xx_Cat_5 ref_manual_id 0038 -chip_id 0x437 // STM32_CHIPID_STM32_L152_RE +chip_id 0x437 // STM32_CHIPID_L152_RE flash_type 8 // STM32_FLASH_TYPE_L0_L1 flash_size_reg 0x1ff800cc flash_pagesize 0x100 // 128 B diff --git a/config/chips/L41x_L42x.chip b/config/chips/L41x_L42x.chip index 40085d828..726645552 100644 --- a/config/chips/L41x_L42x.chip +++ b/config/chips/L41x_L42x.chip @@ -2,7 +2,7 @@ # dev_type STM32L41x_L42x ref_manual_id 0394 -chip_id 0x464 // STM32_CHIPID_STM32_L41x_L42x +chip_id 0x464 // STM32_CHIPID_L41x_L42x flash_type 9 // STM32_FLASH_TYPE_L4_L4P flash_size_reg 0x1fff75e0 flash_pagesize 0x800 // 2 KB diff --git a/config/chips/L43x_L44x.chip b/config/chips/L43x_L44x.chip index 22045c372..baba13e55 100644 --- a/config/chips/L43x_L44x.chip +++ b/config/chips/L43x_L44x.chip @@ -2,7 +2,7 @@ # dev_type STM32L41x_L42x ref_manual_id 0392 -chip_id 0x435 // STM32_CHIPID_STM32_L43x_L44x +chip_id 0x435 // STM32_CHIPID_L43x_L44x flash_type 9 // STM32_FLASH_TYPE_L4_L4P flash_size_reg 0x1fff75e0 flash_pagesize 0x800 // 2 KB diff --git a/config/chips/L45x_L46x.chip b/config/chips/L45x_L46x.chip index 99e9beca1..8886633e2 100644 --- a/config/chips/L45x_L46x.chip +++ b/config/chips/L45x_L46x.chip @@ -2,7 +2,7 @@ # dev_type STM32L45x_L46x ref_manual_id 0394 -chip_id 0x462 // STM32_CHIPID_STM32_L45x_L46x +chip_id 0x462 // STM32_CHIPID_L45x_L46x flash_type 9 // STM32_FLASH_TYPE_L4_L4P flash_size_reg 0x1fff75e0 flash_pagesize 0x800 // 2 KB diff --git a/config/chips/L47x_L48x.chip b/config/chips/L47x_L48x.chip index 44e5282ce..df96ee2fb 100644 --- a/config/chips/L47x_L48x.chip +++ b/config/chips/L47x_L48x.chip @@ -2,7 +2,7 @@ # dev_type STM32L47x_L48x ref_manual_id 0351 -chip_id 0x415 // STM32_CHIPID_STM32_L4 +chip_id 0x415 // STM32_CHIPID_L4 flash_type 9 // STM32_FLASH_TYPE_L4_L4P flash_size_reg 0x1fff75e0 flash_pagesize 0x800 // 2 KB diff --git a/config/chips/L496x_L4A6x.chip b/config/chips/L496x_L4A6x.chip index b983eb9eb..0f4bd285d 100644 --- a/config/chips/L496x_L4A6x.chip +++ b/config/chips/L496x_L4A6x.chip @@ -2,7 +2,7 @@ # dev_type STM32L496x_L4A6x ref_manual_id 0351 -chip_id 0x461 // STM32_CHIPID_STM32_L496x_L4A6x +chip_id 0x461 // STM32_CHIPID_L496x_L4A6x flash_type 9 // STM32_FLASH_TYPE_L4_L4P flash_size_reg 0x1fff75e0 flash_pagesize 0x800 // 2 KB diff --git a/config/chips/L4Px.chip b/config/chips/L4Px.chip index 41805c768..2d1a59806 100644 --- a/config/chips/L4Px.chip +++ b/config/chips/L4Px.chip @@ -2,7 +2,7 @@ # dev_type STM32L4Px ref_manual_id 0432 -chip_id 0x471 // STM32_CHIPID_STM32_L4PX +chip_id 0x471 // STM32_CHIPID_L4PX flash_type 9 // STM32_FLASH_TYPE_L4_L4P flash_size_reg 0x1fff75e0 flash_pagesize 0x1000 // 4 KB diff --git a/config/chips/L4Rx.chip b/config/chips/L4Rx.chip index d0495f083..f0593a97e 100644 --- a/config/chips/L4Rx.chip +++ b/config/chips/L4Rx.chip @@ -2,7 +2,7 @@ # dev_type STM32L4Rx ref_manual_id 0432 -chip_id 0x470 // STM32_CHIPID_STM32_L4RX +chip_id 0x470 // STM32_CHIPID_L4RX flash_type 9 // STM32_FLASH_TYPE_L4_L4P flash_size_reg 0x1fff75e0 flash_pagesize 0x1000 // 4 KB diff --git a/config/chips/WBx0_WBx5.chip b/config/chips/WBx0_WBx5.chip index e34c70815..3d27edd6d 100644 --- a/config/chips/WBx0_WBx5.chip +++ b/config/chips/WBx0_WBx5.chip @@ -2,7 +2,7 @@ # dev_type STM32WBx0_WBx5 ref_manual_id 0434 // also RM0471 -chip_id 0x495 // STM32_CHIPID_STM32_WB55 +chip_id 0x495 // STM32_CHIPID_WB55 flash_type 11 // STM32_FLASH_TYPE_WB_WL flash_size_reg 0x1fff75e0 flash_pagesize 0x1000 // 4 KB diff --git a/config/chips/WLx5.chip b/config/chips/WLx5.chip index b27e03dfe..9669fe27f 100644 --- a/config/chips/WLx5.chip +++ b/config/chips/WLx5.chip @@ -2,7 +2,7 @@ # dev_type STM32WLEx ref_manual_id 0033 -chip_id 0x497 // STM32_CHIPID_STM32_WLE +chip_id 0x497 // STM32_CHIPID_WLE flash_type 11 // STM32_FLASH_TYPE_WB_WL flash_size_reg 0x1fff75e0 flash_pagesize 0x800 // 2 KB diff --git a/inc/stlink.h b/inc/stlink.h index f6bd5cb0d..4899533ec 100644 --- a/inc/stlink.h +++ b/inc/stlink.h @@ -106,23 +106,6 @@ enum target_state { #define C_BUF_LEN 32 -// /* Old flash type definitions */ -// // TODO: Transition to the new defines in stm32.h -// enum stlink_flash_type { -// /* 0 */ STLINK_FLASH_TYPE_UNKNOWN = 0, -// /* 1 */ STLINK_FLASH_TYPE_F0, // used by f0, f1 (except f1xl),f3. */ -// /* 2 */ STLINK_FLASH_TYPE_F1_XL, // f0 flash with dual bank */ -// /* 3 */ STLINK_FLASH_TYPE_F4, // used by f2, f4 */ -// /* 4 */ STLINK_FLASH_TYPE_F7, -// /* 5 */ STLINK_FLASH_TYPE_L0, // l0, l1 */ -// /* 6 */ STLINK_FLASH_TYPE_L4, // l4, l4+ */ -// /* 7 */ STLINK_FLASH_TYPE_G0, -// /* 8 */ STLINK_FLASH_TYPE_G4, -// /* 9 */ STLINK_FLASH_TYPE_WB, -// /* 10 */ STLINK_FLASH_TYPE_H7, -// /* 11 */ STLINK_FLASH_TYPE_MAX, -// }; - struct stlink_reg { uint32_t r[16]; uint32_t s[32]; diff --git a/inc/stm32.h b/inc/stm32.h index d6faff12e..2e8ed6889 100644 --- a/inc/stm32.h +++ b/inc/stm32.h @@ -48,75 +48,67 @@ enum stm32_flash_type { enum stm32_chipids { STM32_CHIPID_UNKNOWN = 0x000, - STM32_CHIPID_STM32_F1_MD = 0x410, /* medium density */ - STM32_CHIPID_STM32_F2 = 0x411, - STM32_CHIPID_STM32_F1_LD = 0x412, /* low density */ - STM32_CHIPID_STM32_F4 = 0x413, - STM32_CHIPID_STM32_F1_HD = 0x414, /* high density */ - STM32_CHIPID_STM32_L4 = 0x415, - STM32_CHIPID_STM32_L1_MD = 0x416, /* medium density */ - STM32_CHIPID_STM32_L0 = 0x417, - STM32_CHIPID_STM32_F1_CONN = 0x418, /* connectivity line */ - STM32_CHIPID_STM32_F4_HD = 0x419, /* high density */ - STM32_CHIPID_STM32_F1_VL_MD_LD = 0x420, /* value line medium & low density */ - STM32_CHIPID_STM32_F446 = 0x421, - STM32_CHIPID_STM32_F3 = 0x422, - STM32_CHIPID_STM32_F4_LP = 0x423, - STM32_CHIPID_STM32_L0_CAT2 = 0x425, - STM32_CHIPID_STM32_L1_MD_PLUS = 0x427, /* medium density plus */ - STM32_CHIPID_STM32_F1_VL_HD = 0x428, /* value line high density */ - STM32_CHIPID_STM32_L1_CAT2 = 0x429, - STM32_CHIPID_STM32_F1_XLD = 0x430, /* extra low density plus */ - STM32_CHIPID_STM32_F411xx = 0x431, - STM32_CHIPID_STM32_F37x = 0x432, - STM32_CHIPID_STM32_F4_DE = 0x433, - STM32_CHIPID_STM32_F4_DSI = 0x434, - STM32_CHIPID_STM32_L43x_L44x = 0x435, - STM32_CHIPID_STM32_L1_MD_PLUS_HD = 0x436, /* medium density plus & high density */ - STM32_CHIPID_STM32_L152_RE = 0x437, - STM32_CHIPID_STM32_F334 = 0x438, - STM32_CHIPID_STM32_F3xx_SMALL = 0x439, - STM32_CHIPID_STM32_F0 = 0x440, - STM32_CHIPID_STM32_F412 = 0x441, - STM32_CHIPID_STM32_F09x = 0x442, - STM32_CHIPID_STM32_F0xx_SMALL = 0x444, - STM32_CHIPID_STM32_F04 = 0x445, - STM32_CHIPID_STM32_F303_HD = 0x446, /* high density */ - STM32_CHIPID_STM32_L0_CAT5 = 0x447, - STM32_CHIPID_STM32_F0_CAN = 0x448, - STM32_CHIPID_STM32_F7 = 0x449, /* Nucleo F746ZG board */ - STM32_CHIPID_STM32_H74xxx = 0x450, /* RM0433, p.3189 */ - STM32_CHIPID_STM32_F76xxx = 0x451, - STM32_CHIPID_STM32_F72xxx = 0x452, /* Nucleo F722ZE board */ - STM32_CHIPID_STM32_G0_CAT4 = 0x456, /* G051/G061 */ - STM32_CHIPID_STM32_L011 = 0x457, - STM32_CHIPID_STM32_F410 = 0x458, - STM32_CHIPID_STM32_G0_CAT2 = 0x460, /* G070/G071/G081 */ - STM32_CHIPID_STM32_L496x_L4A6x = 0x461, - STM32_CHIPID_STM32_L45x_L46x = 0x462, - STM32_CHIPID_STM32_F413 = 0x463, - STM32_CHIPID_STM32_L41x_L42x = 0x464, - STM32_CHIPID_STM32_G0_CAT1 = 0x466, /* G030/G031/G041 */ - STM32_CHIPID_STM32_G0_CAT3 = 0x467, /* G0B1/G0C1 */ - STM32_CHIPID_STM32_G4_CAT2 = 0x468, /* RM0440, section 46.6.1 "MCU device ID code" */ - STM32_CHIPID_STM32_G4_CAT3 = 0x469, - STM32_CHIPID_STM32_L4Rx = 0x470, /* RM0432, p.2247, found on the STM32L4R9I-DISCO board */ - STM32_CHIPID_STM32_L4PX = 0x471, /* RM0432, p.2247 */ - STM32_CHIPID_STM32_G4_CAT4 = 0x479, - STM32_CHIPID_STM32_H7Ax = 0x480, /* RM0455, p.2863 */ - STM32_CHIPID_STM32_H72x = 0x483, /* RM0468, p.3199 */ - STM32_CHIPID_STM32_WB55 = 0x495, - STM32_CHIPID_STM32_WLE = 0x497, + STM32_CHIPID_F1_MD = 0x410, /* medium density */ + STM32_CHIPID_F2 = 0x411, + STM32_CHIPID_F1_LD = 0x412, /* low density */ + STM32_CHIPID_F4 = 0x413, + STM32_CHIPID_F1_HD = 0x414, /* high density */ + STM32_CHIPID_L4 = 0x415, + STM32_CHIPID_L1_MD = 0x416, /* medium density */ + STM32_CHIPID_L0 = 0x417, + STM32_CHIPID_F1_CONN = 0x418, /* connectivity line */ + STM32_CHIPID_F4_HD = 0x419, /* high density */ + STM32_CHIPID_F1_VL_MD_LD = 0x420, /* value line medium & low density */ + STM32_CHIPID_F446 = 0x421, + STM32_CHIPID_F3 = 0x422, + STM32_CHIPID_F4_LP = 0x423, + STM32_CHIPID_L0_CAT2 = 0x425, + STM32_CHIPID_L1_MD_PLUS = 0x427, /* medium density plus */ + STM32_CHIPID_F1_VL_HD = 0x428, /* value line high density */ + STM32_CHIPID_L1_CAT2 = 0x429, + STM32_CHIPID_F1_XLD = 0x430, /* extra low density plus */ + STM32_CHIPID_F411xx = 0x431, + STM32_CHIPID_F37x = 0x432, + STM32_CHIPID_F4_DE = 0x433, + STM32_CHIPID_F4_DSI = 0x434, + STM32_CHIPID_L43x_L44x = 0x435, + STM32_CHIPID_L1_MD_PLUS_HD = 0x436, /* medium density plus & high density */ + STM32_CHIPID_L152_RE = 0x437, + STM32_CHIPID_F334 = 0x438, + STM32_CHIPID_F3xx_SMALL = 0x439, + STM32_CHIPID_F0 = 0x440, + STM32_CHIPID_F412 = 0x441, + STM32_CHIPID_F09x = 0x442, + STM32_CHIPID_F0xx_SMALL = 0x444, + STM32_CHIPID_F04 = 0x445, + STM32_CHIPID_F303_HD = 0x446, /* high density */ + STM32_CHIPID_L0_CAT5 = 0x447, + STM32_CHIPID_F0_CAN = 0x448, + STM32_CHIPID_F7 = 0x449, /* Nucleo F746ZG board */ + STM32_CHIPID_H74xxx = 0x450, /* RM0433, p.3189 */ + STM32_CHIPID_F76xxx = 0x451, + STM32_CHIPID_F72xxx = 0x452, /* Nucleo F722ZE board */ + STM32_CHIPID_G0_CAT4 = 0x456, /* G051/G061 */ + STM32_CHIPID_L011 = 0x457, + STM32_CHIPID_F410 = 0x458, + STM32_CHIPID_G0_CAT2 = 0x460, /* G070/G071/G081 */ + STM32_CHIPID_L496x_L4A6x = 0x461, + STM32_CHIPID_L45x_L46x = 0x462, + STM32_CHIPID_F413 = 0x463, + STM32_CHIPID_L41x_L42x = 0x464, + STM32_CHIPID_G0_CAT1 = 0x466, /* G030/G031/G041 */ + STM32_CHIPID_G0_CAT3 = 0x467, /* G0B1/G0C1 */ + STM32_CHIPID_G4_CAT2 = 0x468, /* RM0440, section 46.6.1 "MCU device ID code" */ + STM32_CHIPID_G4_CAT3 = 0x469, + STM32_CHIPID_L4Rx = 0x470, /* RM0432, p.2247, found on the STM32L4R9I-DISCO board */ + STM32_CHIPID_L4PX = 0x471, /* RM0432, p.2247 */ + STM32_CHIPID_G4_CAT4 = 0x479, + STM32_CHIPID_H7Ax = 0x480, /* RM0455, p.2863 */ + STM32_CHIPID_H72x = 0x483, /* RM0468, p.3199 */ + STM32_CHIPID_WB55 = 0x495, + STM32_CHIPID_WLE = 0x497, }; -/* Constant STM32 memory address */ -#define STM32_SRAM_BASE ((uint32_t)0x20000000) -#define STM32_FLASH_BASE ((uint32_t)0x08000000) - -#define STM32_F1_FLASH_BANK2_BASE ((uint32_t)0x08080000) -#define STM32_H7_FLASH_BANK2_BASE ((uint32_t)0x08100000) - - /* Constant STM32 option bytes base memory address */ #define STM32_F4_OPTION_BYTES_BASE ((uint32_t)0x40023c14) @@ -137,4 +129,392 @@ enum stm32_chipids { #define STM32_F3_OPTION_BYTES_BASE ((uint32_t)0x1ffff800) #define STM32_G4_OPTION_BYTES_BASE ((uint32_t)0x1ffff800) +/* ============ */ +/* Old defines from common.c are below */ +/* ============ */ + +/* Constant STM32 memory address */ +#define STM32_SRAM_BASE ((uint32_t)0x20000000) +#define STM32_FLASH_BASE ((uint32_t)0x08000000) + +#define STM32_F1_FLASH_BANK2_BASE ((uint32_t)0x08080000) +#define STM32_H7_FLASH_BANK2_BASE ((uint32_t)0x08100000) + +/* stm32f FPEC flash controller interface, pm0063 manual */ +// STM32F05x is identical, based on RM0091 (DM00031936, Doc ID 018940 Rev 2, August 2012) +#define FLASH_REGS_ADDR 0x40022000 +#define FLASH_REGS_SIZE 0x28 + +#define FLASH_ACR (FLASH_REGS_ADDR + 0x00) +#define FLASH_KEYR (FLASH_REGS_ADDR + 0x04) +#define FLASH_OPTKEYR (FLASH_REGS_ADDR + 0x08) +#define FLASH_SR (FLASH_REGS_ADDR + 0x0c) +#define FLASH_CR (FLASH_REGS_ADDR + 0x10) +#define FLASH_AR (FLASH_REGS_ADDR + 0x14) +#define FLASH_OBR (FLASH_REGS_ADDR + 0x1c) +#define FLASH_WRPR (FLASH_REGS_ADDR + 0x20) + +// STM32F10x_XL has two flash memory banks with separate registers to control +// the second bank. +#define FLASH_KEYR2 (FLASH_REGS_ADDR + 0x44) +#define FLASH_SR2 (FLASH_REGS_ADDR + 0x4c) +#define FLASH_CR2 (FLASH_REGS_ADDR + 0x50) +#define FLASH_AR2 (FLASH_REGS_ADDR + 0x54) + +// For STM32F05x, the RDPTR_KEY may be wrong, but as it is not used anywhere... +#define FLASH_RDPTR_KEY 0x00a5 +#define FLASH_KEY1 0x45670123 +#define FLASH_KEY2 0xcdef89ab + +#define FLASH_L0_PRGKEY1 0x8c9daebf +#define FLASH_L0_PRGKEY2 0x13141516 + +#define FLASH_L0_PEKEY1 0x89abcdef +#define FLASH_L0_PEKEY2 0x02030405 + +#define FLASH_OPTKEY1 0x08192A3B +#define FLASH_OPTKEY2 0x4C5D6E7F + +#define FLASH_F0_OPTKEY1 0x45670123 +#define FLASH_F0_OPTKEY2 0xCDEF89AB + +#define FLASH_L0_OPTKEY1 0xFBEAD9C8 +#define FLASH_L0_OPTKEY2 0x24252627 + +#define FLASH_SR_BSY 0 +#define FLASH_SR_PG_ERR 2 +#define FLASH_SR_WRPRT_ERR 4 +#define FLASH_SR_EOP 5 + +#define FLASH_SR_ERROR_MASK ((1 << FLASH_SR_PG_ERR) | (1 << FLASH_SR_WRPRT_ERR)) + +#define FLASH_CR_PG 0 +#define FLASH_CR_PER 1 +#define FLASH_CR_MER 2 +#define FLASH_CR_OPTPG 4 +#define FLASH_CR_OPTER 5 +#define FLASH_CR_STRT 6 +#define FLASH_CR_LOCK 7 +#define FLASH_CR_OPTWRE 9 +#define FLASH_CR_OBL_LAUNCH 13 + +#define STM32L_FLASH_REGS_ADDR ((uint32_t)0x40023c00) +#define STM32L_FLASH_ACR (STM32L_FLASH_REGS_ADDR + 0x00) +#define STM32L_FLASH_PECR (STM32L_FLASH_REGS_ADDR + 0x04) +#define STM32L_FLASH_PDKEYR (STM32L_FLASH_REGS_ADDR + 0x08) +#define STM32L_FLASH_PEKEYR (STM32L_FLASH_REGS_ADDR + 0x0c) +#define STM32L_FLASH_PRGKEYR (STM32L_FLASH_REGS_ADDR + 0x10) +#define STM32L_FLASH_OPTKEYR (STM32L_FLASH_REGS_ADDR + 0x14) +#define STM32L_FLASH_SR (STM32L_FLASH_REGS_ADDR + 0x18) +#define STM32L_FLASH_OBR (STM32L_FLASH_REGS_ADDR + 0x1c) +#define STM32L_FLASH_WRPR (STM32L_FLASH_REGS_ADDR + 0x20) +#define FLASH_L1_FPRG 10 +#define FLASH_L1_PROG 3 + +// Flash registers common to STM32G0 and STM32G4 series. +#define STM32Gx_FLASH_REGS_ADDR ((uint32_t)0x40022000) +#define STM32Gx_FLASH_ACR (STM32Gx_FLASH_REGS_ADDR + 0x00) +#define STM32Gx_FLASH_KEYR (STM32Gx_FLASH_REGS_ADDR + 0x08) +#define STM32Gx_FLASH_OPTKEYR (STM32Gx_FLASH_REGS_ADDR + 0x0c) +#define STM32Gx_FLASH_SR (STM32Gx_FLASH_REGS_ADDR + 0x10) +#define STM32Gx_FLASH_CR (STM32Gx_FLASH_REGS_ADDR + 0x14) +#define STM32Gx_FLASH_ECCR (STM32Gx_FLASH_REGS_ADDR + 0x18) +#define STM32Gx_FLASH_OPTR (STM32Gx_FLASH_REGS_ADDR + 0x20) + +// G0 (RM0444 Table 1, sec 3.7) +// Mostly the same as G4 chips, but the notation +// varies a bit after the 'OPTR' register. +#define STM32G0_FLASH_REGS_ADDR (STM32Gx_FLASH_REGS_ADDR) +#define STM32G0_FLASH_PCROP1ASR (STM32G0_FLASH_REGS_ADDR + 0x24) +#define STM32G0_FLASH_PCROP1AER (STM32G0_FLASH_REGS_ADDR + 0x28) +#define STM32G0_FLASH_WRP1AR (STM32G0_FLASH_REGS_ADDR + 0x2C) +#define STM32G0_FLASH_WRP1BR (STM32G0_FLASH_REGS_ADDR + 0x30) +#define STM32G0_FLASH_PCROP1BSR (STM32G0_FLASH_REGS_ADDR + 0x34) +#define STM32G0_FLASH_PCROP1BER (STM32G0_FLASH_REGS_ADDR + 0x38) +#define STM32G0_FLASH_SECR (STM32G0_FLASH_REGS_ADDR + 0x80) + +// G4 (RM0440 Table 17, sec 3.7.19) +// Mostly the same as STM32G0 chips, but there are a few extra +// registers because 'cat 3' devices can have two Flash banks. +#define STM32G4_FLASH_REGS_ADDR (STM32Gx_FLASH_REGS_ADDR) +#define STM32G4_FLASH_PDKEYR (STM32G4_FLASH_REGS_ADDR + 0x04) +#define STM32G4_FLASH_PCROP1SR (STM32G4_FLASH_REGS_ADDR + 0x24) +#define STM32G4_FLASH_PCROP1ER (STM32G4_FLASH_REGS_ADDR + 0x28) +#define STM32G4_FLASH_WRP1AR (STM32G4_FLASH_REGS_ADDR + 0x2C) +#define STM32G4_FLASH_WRP1BR (STM32G4_FLASH_REGS_ADDR + 0x30) +#define STM32G4_FLASH_PCROP2SR (STM32G4_FLASH_REGS_ADDR + 0x44) +#define STM32G4_FLASH_PCROP2ER (STM32G4_FLASH_REGS_ADDR + 0x48) +#define STM32G4_FLASH_WRP2AR (STM32G4_FLASH_REGS_ADDR + 0x4C) +#define STM32G4_FLASH_WRP2BR (STM32G4_FLASH_REGS_ADDR + 0x50) +#define STM32G4_FLASH_SEC1R (STM32G4_FLASH_REGS_ADDR + 0x70) +#define STM32G4_FLASH_SEC2R (STM32G4_FLASH_REGS_ADDR + 0x74) + +// G0/G4 FLASH control register +#define STM32Gx_FLASH_CR_PG (0) /* Program */ +#define STM32Gx_FLASH_CR_PER (1) /* Page erase */ +#define STM32Gx_FLASH_CR_MER1 (2) /* Mass erase */ +#define STM32Gx_FLASH_CR_PNB (3) /* Page number */ +#define STM32G0_FLASH_CR_PNG_LEN (5) /* STM32G0: 5 page number bits */ +#define STM32G4_FLASH_CR_PNG_LEN (7) /* STM32G4: 7 page number bits */ +#define STM32Gx_FLASH_CR_MER2 (15) /* Mass erase (2nd bank)*/ +#define STM32Gx_FLASH_CR_STRT (16) /* Start */ +#define STM32Gx_FLASH_CR_OPTSTRT \ + (17) /* Start of modification of option bytes */ +#define STM32Gx_FLASH_CR_FSTPG (18) /* Fast programming */ +#define STM32Gx_FLASH_CR_EOPIE (24) /* End of operation interrupt enable */ +#define STM32Gx_FLASH_CR_ERRIE (25) /* Error interrupt enable */ +#define STM32Gx_FLASH_CR_OBL_LAUNCH (27) /* Forces the option byte loading */ +#define STM32Gx_FLASH_CR_OPTLOCK (30) /* Options Lock */ +#define STM32Gx_FLASH_CR_LOCK (31) /* FLASH_CR Lock */ + +// G0/G4 FLASH status register +#define STM32Gx_FLASH_SR_ERROR_MASK (0x3fa) +#define STM32Gx_FLASH_SR_PROGERR (3) +#define STM32Gx_FLASH_SR_WRPERR (4) +#define STM32Gx_FLASH_SR_PGAERR (5) +#define STM32Gx_FLASH_SR_BSY (16) /* FLASH_SR Busy */ +#define STM32Gx_FLASH_SR_EOP (0) /* FLASH_EOP End of Operation */ + +// G4 FLASH option register +#define STM32G4_FLASH_OPTR_DBANK (22) /* FLASH_OPTR Dual Bank Mode */ + +// WB (RM0434) +#define STM32WB_FLASH_REGS_ADDR ((uint32_t)0x58004000) +#define STM32WB_FLASH_ACR (STM32WB_FLASH_REGS_ADDR + 0x00) +#define STM32WB_FLASH_KEYR (STM32WB_FLASH_REGS_ADDR + 0x08) +#define STM32WB_FLASH_OPT_KEYR (STM32WB_FLASH_REGS_ADDR + 0x0C) +#define STM32WB_FLASH_SR (STM32WB_FLASH_REGS_ADDR + 0x10) +#define STM32WB_FLASH_CR (STM32WB_FLASH_REGS_ADDR + 0x14) +#define STM32WB_FLASH_ECCR (STM32WB_FLASH_REGS_ADDR + 0x18) +#define STM32WB_FLASH_OPTR (STM32WB_FLASH_REGS_ADDR + 0x20) +#define STM32WB_FLASH_PCROP1ASR (STM32WB_FLASH_REGS_ADDR + 0x24) +#define STM32WB_FLASH_PCROP1AER (STM32WB_FLASH_REGS_ADDR + 0x28) +#define STM32WB_FLASH_WRP1AR (STM32WB_FLASH_REGS_ADDR + 0x2C) +#define STM32WB_FLASH_WRP1BR (STM32WB_FLASH_REGS_ADDR + 0x30) +#define STM32WB_FLASH_PCROP1BSR (STM32WB_FLASH_REGS_ADDR + 0x34) +#define STM32WB_FLASH_PCROP1BER (STM32WB_FLASH_REGS_ADDR + 0x38) +#define STM32WB_FLASH_IPCCBR (STM32WB_FLASH_REGS_ADDR + 0x3C) +#define STM32WB_FLASH_C2ACR (STM32WB_FLASH_REGS_ADDR + 0x5C) +#define STM32WB_FLASH_C2SR (STM32WB_FLASH_REGS_ADDR + 0x60) +#define STM32WB_FLASH_C2CR (STM32WB_FLASH_REGS_ADDR + 0x64) +#define STM32WB_FLASH_SFR (STM32WB_FLASH_REGS_ADDR + 0x80) +#define STM32WB_FLASH_SRRVR (STM32WB_FLASH_REGS_ADDR + 0x84) + +// WB Flash control register. +#define STM32WB_FLASH_CR_STRT (16) /* Start */ +#define STM32WB_FLASH_CR_OPTLOCK (30) /* Option Lock */ +#define STM32WB_FLASH_CR_LOCK (31) /* Lock */ +// WB Flash status register. +#define STM32WB_FLASH_SR_ERROR_MASK (0x3f8) /* SR [9:3] */ +#define STM32WB_FLASH_SR_PROGERR (3) /* Programming alignment error */ +#define STM32WB_FLASH_SR_WRPERR (4) /* Write protection error */ +#define STM32WB_FLASH_SR_PGAERR (5) /* Programming error */ +#define STM32WB_FLASH_SR_BSY (16) /* Busy */ + +// 32L4 register base is at FLASH_REGS_ADDR (0x40022000) +#define STM32L4_FLASH_KEYR (FLASH_REGS_ADDR + 0x08) +#define STM32L4_FLASH_OPTKEYR (FLASH_REGS_ADDR + 0x0C) +#define STM32L4_FLASH_SR (FLASH_REGS_ADDR + 0x10) +#define STM32L4_FLASH_CR (FLASH_REGS_ADDR + 0x14) +#define STM32L4_FLASH_OPTR (FLASH_REGS_ADDR + 0x20) + +#define STM32L4_FLASH_SR_ERROR_MASK 0x3f8 /* SR [9:3] */ +#define STM32L4_FLASH_SR_PROGERR 3 +#define STM32L4_FLASH_SR_WRPERR 4 +#define STM32L4_FLASH_SR_PGAERR 5 +#define STM32L4_FLASH_SR_BSY 16 + +#define STM32L4_FLASH_CR_LOCK 31 /* Lock control register */ +#define STM32L4_FLASH_CR_OPTLOCK 30 /* Lock option bytes */ +#define STM32L4_FLASH_CR_PG 0 /* Program */ +#define STM32L4_FLASH_CR_PER 1 /* Page erase */ +#define STM32L4_FLASH_CR_MER1 2 /* Bank 1 erase */ +#define STM32L4_FLASH_CR_MER2 15 /* Bank 2 erase */ +#define STM32L4_FLASH_CR_STRT 16 /* Start command */ +#define STM32L4_FLASH_CR_OPTSTRT 17 /* Start writing option bytes */ +#define STM32L4_FLASH_CR_BKER 11 /* Bank select for page erase */ +#define STM32L4_FLASH_CR_PNB 3 /* Page number (8 bits) */ +#define STM32L4_FLASH_CR_OBL_LAUNCH 27 /* Option bytes reload */ +// Bits requesting flash operations (useful when we want to clear them) +#define STM32L4_FLASH_CR_OPBITS \ + (uint32_t)((1lu << STM32L4_FLASH_CR_PG) | (1lu << STM32L4_FLASH_CR_PER) | \ + (1lu << STM32L4_FLASH_CR_MER1) | (1lu << STM32L4_FLASH_CR_MER1)) +// Page is fully specified by BKER and PNB +#define STM32L4_FLASH_CR_PAGEMASK (uint32_t)(0x1fflu << STM32L4_FLASH_CR_PNB) + +#define STM32L4_FLASH_OPTR_DUALBANK 21 + +// STM32L0x flash register base and offsets RM0090 - DM00031020.pdf +#define STM32L0_FLASH_REGS_ADDR ((uint32_t)0x40022000) + +#define STM32L0_FLASH_PELOCK (0) +#define STM32L0_FLASH_OPTLOCK (2) +#define STM32L0_FLASH_OBL_LAUNCH (18) + +#define STM32L0_FLASH_SR_ERROR_MASK 0x00013F00 +#define STM32L0_FLASH_SR_WRPERR 8 +#define STM32L0_FLASH_SR_PGAERR 9 +#define STM32L0_FLASH_SR_NOTZEROERR 16 + +#define FLASH_ACR_OFF ((uint32_t)0x00) +#define FLASH_PECR_OFF ((uint32_t)0x04) +#define FLASH_PDKEYR_OFF ((uint32_t)0x08) +#define FLASH_PEKEYR_OFF ((uint32_t)0x0c) +#define FLASH_PRGKEYR_OFF ((uint32_t)0x10) +#define FLASH_OPTKEYR_OFF ((uint32_t)0x14) +#define FLASH_SR_OFF ((uint32_t)0x18) +#define FLASH_OBR_OFF ((uint32_t)0x1c) +#define FLASH_WRPR_OFF ((uint32_t)0x20) + +// STM32F7 +#define FLASH_F7_REGS_ADDR ((uint32_t)0x40023c00) +#define FLASH_F7_KEYR (FLASH_F7_REGS_ADDR + 0x04) +#define FLASH_F7_OPT_KEYR (FLASH_F7_REGS_ADDR + 0x08) +#define FLASH_F7_SR (FLASH_F7_REGS_ADDR + 0x0c) +#define FLASH_F7_CR (FLASH_F7_REGS_ADDR + 0x10) +#define FLASH_F7_OPTCR (FLASH_F7_REGS_ADDR + 0x14) +#define FLASH_F7_OPTCR1 (FLASH_F7_REGS_ADDR + 0x18) +#define FLASH_F7_OPTCR_LOCK 0 +#define FLASH_F7_OPTCR_START 1 +#define FLASH_F7_CR_STRT 16 +#define FLASH_F7_CR_LOCK 31 +#define FLASH_F7_CR_SER 1 +#define FLASH_F7_CR_SNB 3 +#define FLASH_F7_CR_SNB_MASK 0xf8 +#define FLASH_F7_SR_BSY 16 +#define FLASH_F7_SR_ERS_ERR 7 /* Erase Sequence Error */ +#define FLASH_F7_SR_PGP_ERR 6 /* Programming parallelism error */ +#define FLASH_F7_SR_PGA_ERR 5 /* Programming alignment error */ +#define FLASH_F7_SR_WRP_ERR 4 /* Write protection error */ +#define FLASH_F7_SR_OP_ERR 1 /* Operation error */ +#define FLASH_F7_SR_EOP 0 /* End of operation */ +#define FLASH_F7_OPTCR1_BOOT_ADD0 0 +#define FLASH_F7_OPTCR1_BOOT_ADD1 16 + +#define FLASH_F7_SR_ERROR_MASK \ + ((1 << FLASH_F7_SR_ERS_ERR) | (1 << FLASH_F7_SR_PGP_ERR) | \ + (1 << FLASH_F7_SR_PGA_ERR) | (1 << FLASH_F7_SR_WRP_ERR) | \ + (1 << FLASH_F7_SR_OP_ERR)) + +// STM32F4 +#define FLASH_F4_REGS_ADDR ((uint32_t)0x40023c00) +#define FLASH_F4_KEYR (FLASH_F4_REGS_ADDR + 0x04) +#define FLASH_F4_OPT_KEYR (FLASH_F4_REGS_ADDR + 0x08) +#define FLASH_F4_SR (FLASH_F4_REGS_ADDR + 0x0c) +#define FLASH_F4_CR (FLASH_F4_REGS_ADDR + 0x10) +#define FLASH_F4_OPTCR (FLASH_F4_REGS_ADDR + 0x14) +#define FLASH_F4_OPTCR_LOCK 0 +#define FLASH_F4_OPTCR_START 1 +#define FLASH_F4_CR_STRT 16 +#define FLASH_F4_CR_LOCK 31 +#define FLASH_F4_CR_SER 1 +#define FLASH_F4_CR_SNB 3 +#define FLASH_F4_CR_SNB_MASK 0xf8 +#define FLASH_F4_SR_ERROR_MASK 0x000000F0 +#define FLASH_F4_SR_PGAERR 5 +#define FLASH_F4_SR_WRPERR 4 +#define FLASH_F4_SR_BSY 16 + +// STM32F2 +#define FLASH_F2_REGS_ADDR ((uint32_t)0x40023c00) +#define FLASH_F2_KEYR (FLASH_F2_REGS_ADDR + 0x04) +#define FLASH_F2_OPT_KEYR (FLASH_F2_REGS_ADDR + 0x08) +#define FLASH_F2_SR (FLASH_F2_REGS_ADDR + 0x0c) +#define FLASH_F2_CR (FLASH_F2_REGS_ADDR + 0x10) +#define FLASH_F2_OPT_CR (FLASH_F2_REGS_ADDR + 0x14) +#define FLASH_F2_OPT_LOCK_BIT (1u << 0) +#define FLASH_F2_CR_STRT 16 +#define FLASH_F2_CR_LOCK 31 + +#define FLASH_F2_CR_SER 1 +#define FLASH_F2_CR_SNB 3 +#define FLASH_F2_CR_SNB_MASK 0x78 +#define FLASH_F2_SR_BSY 16 + +// STM32H7xx +#define FLASH_H7_CR_LOCK 0 +#define FLASH_H7_CR_PG 1 +#define FLASH_H7_CR_SER 2 +#define FLASH_H7_CR_BER 3 +#define FLASH_H7_CR_PSIZE 4 +#define FLASH_H7_CR_START(chipid) (chipid == STM32_CHIPID_H7Ax ? 5 : 7) +#define FLASH_H7_CR_SNB 8 +#define FLASH_H7_CR_SNB_MASK 0x700 + +#define FLASH_H7_SR_QW 2 +#define FLASH_H7_SR_WRPERR 17 +#define FLASH_H7_SR_PGSERR 18 +#define FLASH_H7_SR_STRBERR 19 +#define FLASH_H7_SR_ERROR_MASK \ + ((1 << FLASH_H7_SR_PGSERR) | (1 << FLASH_H7_SR_STRBERR) | \ + (1 << FLASH_H7_SR_WRPERR)) + +#define FLASH_H7_OPTCR_OPTLOCK 0 +#define FLASH_H7_OPTCR_OPTSTART 1 +#define FLASH_H7_OPTCR_MER 4 + +#define FLASH_H7_OPTSR_OPT_BUSY 0 +#define FLASH_H7_OPTSR_OPTCHANGEERR 30 + +#define FLASH_H7_OPTCCR_CLR_OPTCHANGEERR 30 + +#define FLASH_H7_REGS_ADDR ((uint32_t)0x52002000) +#define FLASH_H7_KEYR1 (FLASH_H7_REGS_ADDR + 0x04) +#define FLASH_H7_KEYR2 (FLASH_H7_REGS_ADDR + 0x104) +#define FLASH_H7_OPT_KEYR (FLASH_H7_REGS_ADDR + 0x08) +#define FLASH_H7_OPT_KEYR2 (FLASH_H7_REGS_ADDR + 0x108) +#define FLASH_H7_CR1 (FLASH_H7_REGS_ADDR + 0x0c) +#define FLASH_H7_CR2 (FLASH_H7_REGS_ADDR + 0x10c) +#define FLASH_H7_SR1 (FLASH_H7_REGS_ADDR + 0x10) +#define FLASH_H7_SR2 (FLASH_H7_REGS_ADDR + 0x110) +#define FLASH_H7_CCR1 (FLASH_H7_REGS_ADDR + 0x14) +#define FLASH_H7_CCR2 (FLASH_H7_REGS_ADDR + 0x114) +#define FLASH_H7_OPTCR (FLASH_H7_REGS_ADDR + 0x18) +#define FLASH_H7_OPTCR2 (FLASH_H7_REGS_ADDR + 0x118) +#define FLASH_H7_OPTSR_CUR (FLASH_H7_REGS_ADDR + 0x1c) +#define FLASH_H7_OPTCCR (FLASH_H7_REGS_ADDR + 0x24) + +#define STM32F0_DBGMCU_CR 0xE0042004 +#define STM32F0_DBGMCU_CR_IWDG_STOP 8 +#define STM32F0_DBGMCU_CR_WWDG_STOP 9 + +#define STM32F4_DBGMCU_APB1FZR1 0xE0042008 +#define STM32F4_DBGMCU_APB1FZR1_WWDG_STOP 11 +#define STM32F4_DBGMCU_APB1FZR1_IWDG_STOP 12 + +#define STM32L0_DBGMCU_APB1_FZ 0x40015808 +#define STM32L0_DBGMCU_APB1_FZ_WWDG_STOP 11 +#define STM32L0_DBGMCU_APB1_FZ_IWDG_STOP 12 + +#define STM32H7_DBGMCU_APB1HFZ 0x5C001054 +#define STM32H7_DBGMCU_APB1HFZ_IWDG_STOP 18 + +#define STM32WB_DBGMCU_APB1FZR1 0xE004203C +#define STM32WB_DBGMCU_APB1FZR1_WWDG_STOP 11 +#define STM32WB_DBGMCU_APB1FZR1_IWDG_STOP 12 + +#define STM32F1_RCC_AHBENR 0x40021014 +#define STM32F1_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN + +#define STM32F4_RCC_AHB1ENR 0x40023830 +#define STM32F4_RCC_DMAEN 0x00600000 // DMA2EN | DMA1EN + +#define STM32G0_RCC_AHBENR 0x40021038 +#define STM32G0_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN + +#define STM32G4_RCC_AHB1ENR 0x40021048 +#define STM32G4_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN + +#define STM32L0_RCC_AHBENR 0x40021030 +#define STM32L0_RCC_DMAEN 0x00000001 // DMAEN + +#define STM32H7_RCC_AHB1ENR 0x58024538 +#define STM32H7_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN + +#define STM32WB_RCC_AHB1ENR 0x58000048 +#define STM32WB_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN + +#define L1_WRITE_BLOCK_SIZE 0x80 +#define L0_WRITE_BLOCK_SIZE 0x40 + #endif // STM32_H diff --git a/src/common.c b/src/common.c index 5a9c43c96..bdd38b21a 100644 --- a/src/common.c +++ b/src/common.c @@ -35,384 +35,7 @@ #define BANK_1 0 #define BANK_2 1 -/* stm32f FPEC flash controller interface, pm0063 manual */ -// TODO - all of this needs to be abstracted out.... -// STM32F05x is identical, based on RM0091 (DM00031936, Doc ID 018940 Rev 2, -// August 2012) -#define FLASH_REGS_ADDR 0x40022000 -#define FLASH_REGS_SIZE 0x28 - -#define FLASH_ACR (FLASH_REGS_ADDR + 0x00) -#define FLASH_KEYR (FLASH_REGS_ADDR + 0x04) -#define FLASH_OPTKEYR (FLASH_REGS_ADDR + 0x08) -#define FLASH_SR (FLASH_REGS_ADDR + 0x0c) -#define FLASH_CR (FLASH_REGS_ADDR + 0x10) -#define FLASH_AR (FLASH_REGS_ADDR + 0x14) -#define FLASH_OBR (FLASH_REGS_ADDR + 0x1c) -#define FLASH_WRPR (FLASH_REGS_ADDR + 0x20) - -// STM32F10x_XL has two flash memory banks with separate registers to control -// the second bank. -#define FLASH_KEYR2 (FLASH_REGS_ADDR + 0x44) -#define FLASH_SR2 (FLASH_REGS_ADDR + 0x4c) -#define FLASH_CR2 (FLASH_REGS_ADDR + 0x50) -#define FLASH_AR2 (FLASH_REGS_ADDR + 0x54) - -// For STM32F05x, the RDPTR_KEY may be wrong, but as it is not used anywhere... -#define FLASH_RDPTR_KEY 0x00a5 -#define FLASH_KEY1 0x45670123 -#define FLASH_KEY2 0xcdef89ab - -#define FLASH_L0_PRGKEY1 0x8c9daebf -#define FLASH_L0_PRGKEY2 0x13141516 - -#define FLASH_L0_PEKEY1 0x89abcdef -#define FLASH_L0_PEKEY2 0x02030405 - -#define FLASH_OPTKEY1 0x08192A3B -#define FLASH_OPTKEY2 0x4C5D6E7F - -#define FLASH_F0_OPTKEY1 0x45670123 -#define FLASH_F0_OPTKEY2 0xCDEF89AB - -#define FLASH_L0_OPTKEY1 0xFBEAD9C8 -#define FLASH_L0_OPTKEY2 0x24252627 - -#define FLASH_SR_BSY 0 -#define FLASH_SR_PG_ERR 2 -#define FLASH_SR_WRPRT_ERR 4 -#define FLASH_SR_EOP 5 - -#define FLASH_SR_ERROR_MASK ((1 << FLASH_SR_PG_ERR) | (1 << FLASH_SR_WRPRT_ERR)) - -#define FLASH_CR_PG 0 -#define FLASH_CR_PER 1 -#define FLASH_CR_MER 2 -#define FLASH_CR_OPTPG 4 -#define FLASH_CR_OPTER 5 -#define FLASH_CR_STRT 6 -#define FLASH_CR_LOCK 7 -#define FLASH_CR_OPTWRE 9 -#define FLASH_CR_OBL_LAUNCH 13 - -#define STM32L_FLASH_REGS_ADDR ((uint32_t)0x40023c00) -#define STM32L_FLASH_ACR (STM32L_FLASH_REGS_ADDR + 0x00) -#define STM32L_FLASH_PECR (STM32L_FLASH_REGS_ADDR + 0x04) -#define STM32L_FLASH_PDKEYR (STM32L_FLASH_REGS_ADDR + 0x08) -#define STM32L_FLASH_PEKEYR (STM32L_FLASH_REGS_ADDR + 0x0c) -#define STM32L_FLASH_PRGKEYR (STM32L_FLASH_REGS_ADDR + 0x10) -#define STM32L_FLASH_OPTKEYR (STM32L_FLASH_REGS_ADDR + 0x14) -#define STM32L_FLASH_SR (STM32L_FLASH_REGS_ADDR + 0x18) -#define STM32L_FLASH_OBR (STM32L_FLASH_REGS_ADDR + 0x1c) -#define STM32L_FLASH_WRPR (STM32L_FLASH_REGS_ADDR + 0x20) -#define FLASH_L1_FPRG 10 -#define FLASH_L1_PROG 3 - -// Flash registers common to STM32G0 and STM32G4 series. -#define STM32Gx_FLASH_REGS_ADDR ((uint32_t)0x40022000) -#define STM32Gx_FLASH_ACR (STM32Gx_FLASH_REGS_ADDR + 0x00) -#define STM32Gx_FLASH_KEYR (STM32Gx_FLASH_REGS_ADDR + 0x08) -#define STM32Gx_FLASH_OPTKEYR (STM32Gx_FLASH_REGS_ADDR + 0x0c) -#define STM32Gx_FLASH_SR (STM32Gx_FLASH_REGS_ADDR + 0x10) -#define STM32Gx_FLASH_CR (STM32Gx_FLASH_REGS_ADDR + 0x14) -#define STM32Gx_FLASH_ECCR (STM32Gx_FLASH_REGS_ADDR + 0x18) -#define STM32Gx_FLASH_OPTR (STM32Gx_FLASH_REGS_ADDR + 0x20) - -// G0 (RM0444 Table 1, sec 3.7) -// Mostly the same as G4 chips, but the notation -// varies a bit after the 'OPTR' register. -#define STM32G0_FLASH_REGS_ADDR (STM32Gx_FLASH_REGS_ADDR) -#define STM32G0_FLASH_PCROP1ASR (STM32G0_FLASH_REGS_ADDR + 0x24) -#define STM32G0_FLASH_PCROP1AER (STM32G0_FLASH_REGS_ADDR + 0x28) -#define STM32G0_FLASH_WRP1AR (STM32G0_FLASH_REGS_ADDR + 0x2C) -#define STM32G0_FLASH_WRP1BR (STM32G0_FLASH_REGS_ADDR + 0x30) -#define STM32G0_FLASH_PCROP1BSR (STM32G0_FLASH_REGS_ADDR + 0x34) -#define STM32G0_FLASH_PCROP1BER (STM32G0_FLASH_REGS_ADDR + 0x38) -#define STM32G0_FLASH_SECR (STM32G0_FLASH_REGS_ADDR + 0x80) - -// G4 (RM0440 Table 17, sec 3.7.19) -// Mostly the same as STM32G0 chips, but there are a few extra -// registers because 'cat 3' devices can have two Flash banks. -#define STM32G4_FLASH_REGS_ADDR (STM32Gx_FLASH_REGS_ADDR) -#define STM32G4_FLASH_PDKEYR (STM32G4_FLASH_REGS_ADDR + 0x04) -#define STM32G4_FLASH_PCROP1SR (STM32G4_FLASH_REGS_ADDR + 0x24) -#define STM32G4_FLASH_PCROP1ER (STM32G4_FLASH_REGS_ADDR + 0x28) -#define STM32G4_FLASH_WRP1AR (STM32G4_FLASH_REGS_ADDR + 0x2C) -#define STM32G4_FLASH_WRP1BR (STM32G4_FLASH_REGS_ADDR + 0x30) -#define STM32G4_FLASH_PCROP2SR (STM32G4_FLASH_REGS_ADDR + 0x44) -#define STM32G4_FLASH_PCROP2ER (STM32G4_FLASH_REGS_ADDR + 0x48) -#define STM32G4_FLASH_WRP2AR (STM32G4_FLASH_REGS_ADDR + 0x4C) -#define STM32G4_FLASH_WRP2BR (STM32G4_FLASH_REGS_ADDR + 0x50) -#define STM32G4_FLASH_SEC1R (STM32G4_FLASH_REGS_ADDR + 0x70) -#define STM32G4_FLASH_SEC2R (STM32G4_FLASH_REGS_ADDR + 0x74) - -// G0/G4 FLASH control register -#define STM32Gx_FLASH_CR_PG (0) /* Program */ -#define STM32Gx_FLASH_CR_PER (1) /* Page erase */ -#define STM32Gx_FLASH_CR_MER1 (2) /* Mass erase */ -#define STM32Gx_FLASH_CR_PNB (3) /* Page number */ -#define STM32G0_FLASH_CR_PNG_LEN (5) /* STM32G0: 5 page number bits */ -#define STM32G4_FLASH_CR_PNG_LEN (7) /* STM32G4: 7 page number bits */ -#define STM32Gx_FLASH_CR_MER2 (15) /* Mass erase (2nd bank)*/ -#define STM32Gx_FLASH_CR_STRT (16) /* Start */ -#define STM32Gx_FLASH_CR_OPTSTRT \ - (17) /* Start of modification of option bytes */ -#define STM32Gx_FLASH_CR_FSTPG (18) /* Fast programming */ -#define STM32Gx_FLASH_CR_EOPIE (24) /* End of operation interrupt enable */ -#define STM32Gx_FLASH_CR_ERRIE (25) /* Error interrupt enable */ -#define STM32Gx_FLASH_CR_OBL_LAUNCH (27) /* Forces the option byte loading */ -#define STM32Gx_FLASH_CR_OPTLOCK (30) /* Options Lock */ -#define STM32Gx_FLASH_CR_LOCK (31) /* FLASH_CR Lock */ - -// G0/G4 FLASH status register -#define STM32Gx_FLASH_SR_ERROR_MASK (0x3fa) -#define STM32Gx_FLASH_SR_PROGERR (3) -#define STM32Gx_FLASH_SR_WRPERR (4) -#define STM32Gx_FLASH_SR_PGAERR (5) -#define STM32Gx_FLASH_SR_BSY (16) /* FLASH_SR Busy */ -#define STM32Gx_FLASH_SR_EOP (0) /* FLASH_EOP End of Operation */ - -// G4 FLASH option register -#define STM32G4_FLASH_OPTR_DBANK (22) /* FLASH_OPTR Dual Bank Mode */ - -// WB (RM0434) -#define STM32WB_FLASH_REGS_ADDR ((uint32_t)0x58004000) -#define STM32WB_FLASH_ACR (STM32WB_FLASH_REGS_ADDR + 0x00) -#define STM32WB_FLASH_KEYR (STM32WB_FLASH_REGS_ADDR + 0x08) -#define STM32WB_FLASH_OPT_KEYR (STM32WB_FLASH_REGS_ADDR + 0x0C) -#define STM32WB_FLASH_SR (STM32WB_FLASH_REGS_ADDR + 0x10) -#define STM32WB_FLASH_CR (STM32WB_FLASH_REGS_ADDR + 0x14) -#define STM32WB_FLASH_ECCR (STM32WB_FLASH_REGS_ADDR + 0x18) -#define STM32WB_FLASH_OPTR (STM32WB_FLASH_REGS_ADDR + 0x20) -#define STM32WB_FLASH_PCROP1ASR (STM32WB_FLASH_REGS_ADDR + 0x24) -#define STM32WB_FLASH_PCROP1AER (STM32WB_FLASH_REGS_ADDR + 0x28) -#define STM32WB_FLASH_WRP1AR (STM32WB_FLASH_REGS_ADDR + 0x2C) -#define STM32WB_FLASH_WRP1BR (STM32WB_FLASH_REGS_ADDR + 0x30) -#define STM32WB_FLASH_PCROP1BSR (STM32WB_FLASH_REGS_ADDR + 0x34) -#define STM32WB_FLASH_PCROP1BER (STM32WB_FLASH_REGS_ADDR + 0x38) -#define STM32WB_FLASH_IPCCBR (STM32WB_FLASH_REGS_ADDR + 0x3C) -#define STM32WB_FLASH_C2ACR (STM32WB_FLASH_REGS_ADDR + 0x5C) -#define STM32WB_FLASH_C2SR (STM32WB_FLASH_REGS_ADDR + 0x60) -#define STM32WB_FLASH_C2CR (STM32WB_FLASH_REGS_ADDR + 0x64) -#define STM32WB_FLASH_SFR (STM32WB_FLASH_REGS_ADDR + 0x80) -#define STM32WB_FLASH_SRRVR (STM32WB_FLASH_REGS_ADDR + 0x84) - -// WB Flash control register. -#define STM32WB_FLASH_CR_STRT (16) /* Start */ -#define STM32WB_FLASH_CR_OPTLOCK (30) /* Option Lock */ -#define STM32WB_FLASH_CR_LOCK (31) /* Lock */ -// WB Flash status register. -#define STM32WB_FLASH_SR_ERROR_MASK (0x3f8) /* SR [9:3] */ -#define STM32WB_FLASH_SR_PROGERR (3) /* Programming alignment error */ -#define STM32WB_FLASH_SR_WRPERR (4) /* Write protection error */ -#define STM32WB_FLASH_SR_PGAERR (5) /* Programming error */ -#define STM32WB_FLASH_SR_BSY (16) /* Busy */ - -// 32L4 register base is at FLASH_REGS_ADDR (0x40022000) -#define STM32L4_FLASH_KEYR (FLASH_REGS_ADDR + 0x08) -#define STM32L4_FLASH_OPTKEYR (FLASH_REGS_ADDR + 0x0C) -#define STM32L4_FLASH_SR (FLASH_REGS_ADDR + 0x10) -#define STM32L4_FLASH_CR (FLASH_REGS_ADDR + 0x14) -#define STM32L4_FLASH_OPTR (FLASH_REGS_ADDR + 0x20) - -#define STM32L4_FLASH_SR_ERROR_MASK 0x3f8 /* SR [9:3] */ -#define STM32L4_FLASH_SR_PROGERR 3 -#define STM32L4_FLASH_SR_WRPERR 4 -#define STM32L4_FLASH_SR_PGAERR 5 -#define STM32L4_FLASH_SR_BSY 16 - -#define STM32L4_FLASH_CR_LOCK 31 /* Lock control register */ -#define STM32L4_FLASH_CR_OPTLOCK 30 /* Lock option bytes */ -#define STM32L4_FLASH_CR_PG 0 /* Program */ -#define STM32L4_FLASH_CR_PER 1 /* Page erase */ -#define STM32L4_FLASH_CR_MER1 2 /* Bank 1 erase */ -#define STM32L4_FLASH_CR_MER2 15 /* Bank 2 erase */ -#define STM32L4_FLASH_CR_STRT 16 /* Start command */ -#define STM32L4_FLASH_CR_OPTSTRT 17 /* Start writing option bytes */ -#define STM32L4_FLASH_CR_BKER 11 /* Bank select for page erase */ -#define STM32L4_FLASH_CR_PNB 3 /* Page number (8 bits) */ -#define STM32L4_FLASH_CR_OBL_LAUNCH 27 /* Option bytes reload */ -// Bits requesting flash operations (useful when we want to clear them) -#define STM32L4_FLASH_CR_OPBITS \ - (uint32_t)((1lu << STM32L4_FLASH_CR_PG) | (1lu << STM32L4_FLASH_CR_PER) | \ - (1lu << STM32L4_FLASH_CR_MER1) | (1lu << STM32L4_FLASH_CR_MER1)) -// Page is fully specified by BKER and PNB -#define STM32L4_FLASH_CR_PAGEMASK (uint32_t)(0x1fflu << STM32L4_FLASH_CR_PNB) - -#define STM32L4_FLASH_OPTR_DUALBANK 21 - -// STM32L0x flash register base and offsets RM0090 - DM00031020.pdf -#define STM32L0_FLASH_REGS_ADDR ((uint32_t)0x40022000) - -#define STM32L0_FLASH_PELOCK (0) -#define STM32L0_FLASH_OPTLOCK (2) -#define STM32L0_FLASH_OBL_LAUNCH (18) - -#define STM32L0_FLASH_SR_ERROR_MASK 0x00013F00 -#define STM32L0_FLASH_SR_WRPERR 8 -#define STM32L0_FLASH_SR_PGAERR 9 -#define STM32L0_FLASH_SR_NOTZEROERR 16 - -#define FLASH_ACR_OFF ((uint32_t)0x00) -#define FLASH_PECR_OFF ((uint32_t)0x04) -#define FLASH_PDKEYR_OFF ((uint32_t)0x08) -#define FLASH_PEKEYR_OFF ((uint32_t)0x0c) -#define FLASH_PRGKEYR_OFF ((uint32_t)0x10) -#define FLASH_OPTKEYR_OFF ((uint32_t)0x14) -#define FLASH_SR_OFF ((uint32_t)0x18) -#define FLASH_OBR_OFF ((uint32_t)0x1c) -#define FLASH_WRPR_OFF ((uint32_t)0x20) - -// STM32F7 -#define FLASH_F7_REGS_ADDR ((uint32_t)0x40023c00) -#define FLASH_F7_KEYR (FLASH_F7_REGS_ADDR + 0x04) -#define FLASH_F7_OPT_KEYR (FLASH_F7_REGS_ADDR + 0x08) -#define FLASH_F7_SR (FLASH_F7_REGS_ADDR + 0x0c) -#define FLASH_F7_CR (FLASH_F7_REGS_ADDR + 0x10) -#define FLASH_F7_OPTCR (FLASH_F7_REGS_ADDR + 0x14) -#define FLASH_F7_OPTCR1 (FLASH_F7_REGS_ADDR + 0x18) -#define FLASH_F7_OPTCR_LOCK 0 -#define FLASH_F7_OPTCR_START 1 -#define FLASH_F7_CR_STRT 16 -#define FLASH_F7_CR_LOCK 31 -#define FLASH_F7_CR_SER 1 -#define FLASH_F7_CR_SNB 3 -#define FLASH_F7_CR_SNB_MASK 0xf8 -#define FLASH_F7_SR_BSY 16 -#define FLASH_F7_SR_ERS_ERR 7 /* Erase Sequence Error */ -#define FLASH_F7_SR_PGP_ERR 6 /* Programming parallelism error */ -#define FLASH_F7_SR_PGA_ERR 5 /* Programming alignment error */ -#define FLASH_F7_SR_WRP_ERR 4 /* Write protection error */ -#define FLASH_F7_SR_OP_ERR 1 /* Operation error */ -#define FLASH_F7_SR_EOP 0 /* End of operation */ -#define FLASH_F7_OPTCR1_BOOT_ADD0 0 -#define FLASH_F7_OPTCR1_BOOT_ADD1 16 - -#define FLASH_F7_SR_ERROR_MASK \ - ((1 << FLASH_F7_SR_ERS_ERR) | (1 << FLASH_F7_SR_PGP_ERR) | \ - (1 << FLASH_F7_SR_PGA_ERR) | (1 << FLASH_F7_SR_WRP_ERR) | \ - (1 << FLASH_F7_SR_OP_ERR)) - -// STM32F4 -#define FLASH_F4_REGS_ADDR ((uint32_t)0x40023c00) -#define FLASH_F4_KEYR (FLASH_F4_REGS_ADDR + 0x04) -#define FLASH_F4_OPT_KEYR (FLASH_F4_REGS_ADDR + 0x08) -#define FLASH_F4_SR (FLASH_F4_REGS_ADDR + 0x0c) -#define FLASH_F4_CR (FLASH_F4_REGS_ADDR + 0x10) -#define FLASH_F4_OPTCR (FLASH_F4_REGS_ADDR + 0x14) -#define FLASH_F4_OPTCR_LOCK 0 -#define FLASH_F4_OPTCR_START 1 -#define FLASH_F4_CR_STRT 16 -#define FLASH_F4_CR_LOCK 31 -#define FLASH_F4_CR_SER 1 -#define FLASH_F4_CR_SNB 3 -#define FLASH_F4_CR_SNB_MASK 0xf8 -#define FLASH_F4_SR_ERROR_MASK 0x000000F0 -#define FLASH_F4_SR_PGAERR 5 -#define FLASH_F4_SR_WRPERR 4 -#define FLASH_F4_SR_BSY 16 - -// STM32F2 -#define FLASH_F2_REGS_ADDR ((uint32_t)0x40023c00) -#define FLASH_F2_KEYR (FLASH_F2_REGS_ADDR + 0x04) -#define FLASH_F2_OPT_KEYR (FLASH_F2_REGS_ADDR + 0x08) -#define FLASH_F2_SR (FLASH_F2_REGS_ADDR + 0x0c) -#define FLASH_F2_CR (FLASH_F2_REGS_ADDR + 0x10) -#define FLASH_F2_OPT_CR (FLASH_F2_REGS_ADDR + 0x14) -#define FLASH_F2_OPT_LOCK_BIT (1u << 0) -#define FLASH_F2_CR_STRT 16 -#define FLASH_F2_CR_LOCK 31 - -#define FLASH_F2_CR_SER 1 -#define FLASH_F2_CR_SNB 3 -#define FLASH_F2_CR_SNB_MASK 0x78 -#define FLASH_F2_SR_BSY 16 - -// STM32H7xx -#define FLASH_H7_CR_LOCK 0 -#define FLASH_H7_CR_PG 1 -#define FLASH_H7_CR_SER 2 -#define FLASH_H7_CR_BER 3 -#define FLASH_H7_CR_PSIZE 4 -#define FLASH_H7_CR_START(chipid) (chipid == STM32_CHIPID_STM32_H7Ax ? 5 : 7) -#define FLASH_H7_CR_SNB 8 -#define FLASH_H7_CR_SNB_MASK 0x700 - -#define FLASH_H7_SR_QW 2 -#define FLASH_H7_SR_WRPERR 17 -#define FLASH_H7_SR_PGSERR 18 -#define FLASH_H7_SR_STRBERR 19 -#define FLASH_H7_SR_ERROR_MASK \ - ((1 << FLASH_H7_SR_PGSERR) | (1 << FLASH_H7_SR_STRBERR) | \ - (1 << FLASH_H7_SR_WRPERR)) - -#define FLASH_H7_OPTCR_OPTLOCK 0 -#define FLASH_H7_OPTCR_OPTSTART 1 -#define FLASH_H7_OPTCR_MER 4 - -#define FLASH_H7_OPTSR_OPT_BUSY 0 -#define FLASH_H7_OPTSR_OPTCHANGEERR 30 - -#define FLASH_H7_OPTCCR_CLR_OPTCHANGEERR 30 - -#define FLASH_H7_REGS_ADDR ((uint32_t)0x52002000) -#define FLASH_H7_KEYR1 (FLASH_H7_REGS_ADDR + 0x04) -#define FLASH_H7_KEYR2 (FLASH_H7_REGS_ADDR + 0x104) -#define FLASH_H7_OPT_KEYR (FLASH_H7_REGS_ADDR + 0x08) -#define FLASH_H7_OPT_KEYR2 (FLASH_H7_REGS_ADDR + 0x108) -#define FLASH_H7_CR1 (FLASH_H7_REGS_ADDR + 0x0c) -#define FLASH_H7_CR2 (FLASH_H7_REGS_ADDR + 0x10c) -#define FLASH_H7_SR1 (FLASH_H7_REGS_ADDR + 0x10) -#define FLASH_H7_SR2 (FLASH_H7_REGS_ADDR + 0x110) -#define FLASH_H7_CCR1 (FLASH_H7_REGS_ADDR + 0x14) -#define FLASH_H7_CCR2 (FLASH_H7_REGS_ADDR + 0x114) -#define FLASH_H7_OPTCR (FLASH_H7_REGS_ADDR + 0x18) -#define FLASH_H7_OPTCR2 (FLASH_H7_REGS_ADDR + 0x118) -#define FLASH_H7_OPTSR_CUR (FLASH_H7_REGS_ADDR + 0x1c) -#define FLASH_H7_OPTCCR (FLASH_H7_REGS_ADDR + 0x24) - -#define STM32F0_DBGMCU_CR 0xE0042004 -#define STM32F0_DBGMCU_CR_IWDG_STOP 8 -#define STM32F0_DBGMCU_CR_WWDG_STOP 9 - -#define STM32F4_DBGMCU_APB1FZR1 0xE0042008 -#define STM32F4_DBGMCU_APB1FZR1_WWDG_STOP 11 -#define STM32F4_DBGMCU_APB1FZR1_IWDG_STOP 12 - -#define STM32L0_DBGMCU_APB1_FZ 0x40015808 -#define STM32L0_DBGMCU_APB1_FZ_WWDG_STOP 11 -#define STM32L0_DBGMCU_APB1_FZ_IWDG_STOP 12 - -#define STM32H7_DBGMCU_APB1HFZ 0x5C001054 -#define STM32H7_DBGMCU_APB1HFZ_IWDG_STOP 18 - -#define STM32WB_DBGMCU_APB1FZR1 0xE004203C -#define STM32WB_DBGMCU_APB1FZR1_WWDG_STOP 11 -#define STM32WB_DBGMCU_APB1FZR1_IWDG_STOP 12 - -#define STM32F1_RCC_AHBENR 0x40021014 -#define STM32F1_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN - -#define STM32F4_RCC_AHB1ENR 0x40023830 -#define STM32F4_RCC_DMAEN 0x00600000 // DMA2EN | DMA1EN - -#define STM32G0_RCC_AHBENR 0x40021038 -#define STM32G0_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN - -#define STM32G4_RCC_AHB1ENR 0x40021048 -#define STM32G4_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN - -#define STM32L0_RCC_AHBENR 0x40021030 -#define STM32L0_RCC_DMAEN 0x00000001 // DMAEN - -#define STM32H7_RCC_AHB1ENR 0x58024538 -#define STM32H7_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN - -#define STM32WB_RCC_AHB1ENR 0x58000048 -#define STM32WB_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN - -#define L1_WRITE_BLOCK_SIZE 0x80 -#define L0_WRITE_BLOCK_SIZE 0x40 + // Endianness // https://commandcenter.blogspot.com/2012/04/byte-order-fallacy.html @@ -441,16 +64,16 @@ uint16_t read_uint16(const unsigned char *c, const int pt) { static uint32_t get_stm32l0_flash_base(stlink_t *sl) { switch (sl->chip_id) { - case STM32_CHIPID_STM32_L0: - case STM32_CHIPID_STM32_L0_CAT5: - case STM32_CHIPID_STM32_L0_CAT2: - case STM32_CHIPID_STM32_L011: + case STM32_CHIPID_L0: + case STM32_CHIPID_L0_CAT5: + case STM32_CHIPID_L0_CAT2: + case STM32_CHIPID_L011: return (STM32L0_FLASH_REGS_ADDR); - case STM32_CHIPID_STM32_L1_CAT2: - case STM32_CHIPID_STM32_L1_MD: - case STM32_CHIPID_STM32_L1_MD_PLUS: - case STM32_CHIPID_STM32_L1_MD_PLUS_HD: + case STM32_CHIPID_L1_CAT2: + case STM32_CHIPID_L1_MD: + case STM32_CHIPID_L1_MD_PLUS: + case STM32_CHIPID_L1_MD_PLUS_HD: return (STM32L_FLASH_REGS_ADDR); default: @@ -1622,14 +1245,14 @@ int stlink_load_device_params(stlink_t *sl) { flash_size = flash_size & 0xffff; - if ((sl->chip_id == STM32_CHIPID_STM32_L1_MD || - sl->chip_id == STM32_CHIPID_STM32_F1_VL_MD_LD || - sl->chip_id == STM32_CHIPID_STM32_L1_MD_PLUS) && + if ((sl->chip_id == STM32_CHIPID_L1_MD || + sl->chip_id == STM32_CHIPID_F1_VL_MD_LD || + sl->chip_id == STM32_CHIPID_L1_MD_PLUS) && (flash_size == 0)) { sl->flash_size = 128 * 1024; - } else if (sl->chip_id == STM32_CHIPID_STM32_L1_CAT2) { + } else if (sl->chip_id == STM32_CHIPID_L1_CAT2) { sl->flash_size = (flash_size & 0xff) * 1024; - } else if ((sl->chip_id & 0xFFF) == STM32_CHIPID_STM32_L1_MD_PLUS_HD) { + } else if ((sl->chip_id & 0xFFF) == STM32_CHIPID_L1_MD_PLUS_HD) { // 0 is 384k and 1 is 256k if (flash_size == 0) { sl->flash_size = 384 * 1024; @@ -1651,12 +1274,12 @@ int stlink_load_device_params(stlink_t *sl) { // medium and low devices have the same chipid. ram size depends on flash // size. STM32F100xx datasheet Doc ID 16455 Table 2 - if (sl->chip_id == STM32_CHIPID_STM32_F1_VL_MD_LD && + if (sl->chip_id == STM32_CHIPID_F1_VL_MD_LD && sl->flash_size < 64 * 1024) { sl->sram_size = 0x1000; } - if (sl->chip_id == STM32_CHIPID_STM32_G4_CAT3) { + if (sl->chip_id == STM32_CHIPID_G4_CAT3) { uint32_t flash_optr; stlink_read_debug32(sl, STM32Gx_FLASH_OPTR, &flash_optr); @@ -2706,9 +2329,9 @@ uint32_t calculate_L4_page(stlink_t *sl, uint32_t flashaddr) { stlink_read_debug32(sl, STM32L4_FLASH_OPTR, &flashopt); flashaddr -= STM32_FLASH_BASE; - if (sl->chip_id == STM32_CHIPID_STM32_L4 || - sl->chip_id == STM32_CHIPID_STM32_L496x_L4A6x || - sl->chip_id == STM32_CHIPID_STM32_L4Rx) { + if (sl->chip_id == STM32_CHIPID_L4 || + sl->chip_id == STM32_CHIPID_L496x_L4A6x || + sl->chip_id == STM32_CHIPID_L4Rx) { // this chip use dual banked flash if (flashopt & (uint32_t)(1lu << STM32L4_FLASH_OPTR_DUALBANK)) { uint32_t banksize = (uint32_t)sl->flash_size / 2; @@ -2726,16 +2349,16 @@ uint32_t calculate_L4_page(stlink_t *sl, uint32_t flashaddr) { } uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr) { - if ((sl->chip_id == STM32_CHIPID_STM32_F2) || - (sl->chip_id == STM32_CHIPID_STM32_F4) || - (sl->chip_id == STM32_CHIPID_STM32_F4_DE) || - (sl->chip_id == STM32_CHIPID_STM32_F4_LP) || - (sl->chip_id == STM32_CHIPID_STM32_F4_HD) || - (sl->chip_id == STM32_CHIPID_STM32_F411xx) || - (sl->chip_id == STM32_CHIPID_STM32_F446) || - (sl->chip_id == STM32_CHIPID_STM32_F4_DSI) || - (sl->chip_id == STM32_CHIPID_STM32_F72xxx) || - (sl->chip_id == STM32_CHIPID_STM32_F412)) { + if ((sl->chip_id == STM32_CHIPID_F2) || + (sl->chip_id == STM32_CHIPID_F4) || + (sl->chip_id == STM32_CHIPID_F4_DE) || + (sl->chip_id == STM32_CHIPID_F4_LP) || + (sl->chip_id == STM32_CHIPID_F4_HD) || + (sl->chip_id == STM32_CHIPID_F411xx) || + (sl->chip_id == STM32_CHIPID_F446) || + (sl->chip_id == STM32_CHIPID_F4_DSI) || + (sl->chip_id == STM32_CHIPID_F72xxx) || + (sl->chip_id == STM32_CHIPID_F412)) { uint32_t sector = calculate_F4_sectornum(flashaddr); if (sector >= 12) { @@ -2749,8 +2372,8 @@ uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr) { } else { sl->flash_pgsz = 0x20000; } - } else if (sl->chip_id == STM32_CHIPID_STM32_F7 || - sl->chip_id == STM32_CHIPID_STM32_F76xxx) { + } else if (sl->chip_id == STM32_CHIPID_F7 || + sl->chip_id == STM32_CHIPID_F76xxx) { uint32_t sector = calculate_F7_sectornum(flashaddr); if (sector < 4) { @@ -2785,11 +2408,11 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { unlock_flash_if(sl); // select the page to erase - if ((sl->chip_id == STM32_CHIPID_STM32_L4) || - (sl->chip_id == STM32_CHIPID_STM32_L43x_L44x) || - (sl->chip_id == STM32_CHIPID_STM32_L45x_L46x) || - (sl->chip_id == STM32_CHIPID_STM32_L496x_L4A6x) || - (sl->chip_id == STM32_CHIPID_STM32_L4Rx)) { + if ((sl->chip_id == STM32_CHIPID_L4) || + (sl->chip_id == STM32_CHIPID_L43x_L44x) || + (sl->chip_id == STM32_CHIPID_L45x_L46x) || + (sl->chip_id == STM32_CHIPID_L496x_L4A6x) || + (sl->chip_id == STM32_CHIPID_L4Rx)) { // calculate the actual bank+page from the address uint32_t page = calculate_L4_page(sl, flashaddr); @@ -2797,8 +2420,8 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { stlink_calculate_pagesize(sl, flashaddr)); write_flash_cr_bker_pnb(sl, page); - } else if (sl->chip_id == STM32_CHIPID_STM32_F7 || - sl->chip_id == STM32_CHIPID_STM32_F76xxx) { + } else if (sl->chip_id == STM32_CHIPID_F7 || + sl->chip_id == STM32_CHIPID_F76xxx) { // calculate the actual page from the address uint32_t sector = calculate_F7_sectornum(flashaddr); @@ -2982,7 +2605,7 @@ int stlink_erase_flash_mass(stlink_t *sl) { unlock_flash_if(sl); if (sl->flash_type == STM32_FLASH_TYPE_H7 && - sl->chip_id != STM32_CHIPID_STM32_H7Ax) { + sl->chip_id != STM32_CHIPID_H7Ax) { // set parallelism write_flash_cr_psiz(sl, 3 /*64it*/, BANK_1); if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { @@ -3260,7 +2883,7 @@ int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { set_flash_cr_pg(sl, BANK_2); } - if (sl->chip_id != STM32_CHIPID_STM32_H7Ax) { + if (sl->chip_id != STM32_CHIPID_H7Ax) { // set parallelism write_flash_cr_psiz(sl, 3 /*64it*/, BANK_1); if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { @@ -4357,17 +3980,17 @@ int stlink_read_option_bytes32(stlink_t *sl, uint32_t *option_byte) { } switch (sl->chip_id) { - case STM32_CHIPID_STM32_F2: + case STM32_CHIPID_F2: return stlink_read_option_bytes_f2(sl, option_byte); - case STM32_CHIPID_STM32_F4: - case STM32_CHIPID_STM32_F446: + case STM32_CHIPID_F4: + case STM32_CHIPID_F446: return stlink_read_option_bytes_f4(sl, option_byte); - case STM32_CHIPID_STM32_F76xxx: + case STM32_CHIPID_F76xxx: return stlink_read_option_bytes_f7(sl, option_byte); - case STM32_CHIPID_STM32_G0_CAT1: - case STM32_CHIPID_STM32_G0_CAT2: - case STM32_CHIPID_STM32_G4_CAT2: - case STM32_CHIPID_STM32_G4_CAT3: + case STM32_CHIPID_G0_CAT1: + case STM32_CHIPID_G0_CAT2: + case STM32_CHIPID_G4_CAT2: + case STM32_CHIPID_G4_CAT3: return stlink_read_option_bytes_Gx(sl, option_byte); default: return stlink_read_option_bytes_generic(sl, option_byte); diff --git a/src/st-util/gdb-server.c b/src/st-util/gdb-server.c index 19819a6cb..2b6875d9f 100644 --- a/src/st-util/gdb-server.c +++ b/src/st-util/gdb-server.c @@ -553,39 +553,39 @@ char* make_memory_map(stlink_t *sl) { char* map = malloc(sz); map[0] = '\0'; - if (sl->chip_id == STM32_CHIPID_STM32_F4 || - sl->chip_id == STM32_CHIPID_STM32_F446 || - sl->chip_id == STM32_CHIPID_STM32_F411xx) { + if (sl->chip_id == STM32_CHIPID_F4 || + sl->chip_id == STM32_CHIPID_F446 || + sl->chip_id == STM32_CHIPID_F411xx) { strcpy(map, memory_map_template_F4); - } else if (sl->chip_id == STM32_CHIPID_STM32_F4_DE) { + } else if (sl->chip_id == STM32_CHIPID_F4_DE) { strcpy(map, memory_map_template_F4_DE); } else if (sl->core_id == STM32_CORE_ID_M7_F7) { snprintf(map, sz, memory_map_template_F7, (unsigned int)sl->sram_size); - } else if (sl->chip_id == STM32_CHIPID_STM32_H74xxx) { + } else if (sl->chip_id == STM32_CHIPID_H74xxx) { snprintf(map, sz, memory_map_template_H7, (unsigned int)sl->flash_size, (unsigned int)sl->flash_pgsz); - } else if (sl->chip_id == STM32_CHIPID_STM32_F4_HD) { + } else if (sl->chip_id == STM32_CHIPID_F4_HD) { strcpy(map, memory_map_template_F4_HD); - } else if (sl->chip_id == STM32_CHIPID_STM32_F2) { + } else if (sl->chip_id == STM32_CHIPID_F2) { snprintf(map, sz, memory_map_template_F2, (unsigned int)sl->flash_size, (unsigned int)sl->sram_size, (unsigned int)sl->flash_size - 0x20000, (unsigned int)sl->sys_base, (unsigned int)sl->sys_size); - } else if ((sl->chip_id == STM32_CHIPID_STM32_L4) || - (sl->chip_id == STM32_CHIPID_STM32_L43x_L44x) || - (sl->chip_id == STM32_CHIPID_STM32_L45x_L46x)) { + } else if ((sl->chip_id == STM32_CHIPID_L4) || + (sl->chip_id == STM32_CHIPID_L43x_L44x) || + (sl->chip_id == STM32_CHIPID_L45x_L46x)) { snprintf(map, sz, memory_map_template_L4, (unsigned int)sl->flash_size, (unsigned int)sl->flash_size); - } else if (sl->chip_id == STM32_CHIPID_STM32_L496x_L4A6x) { + } else if (sl->chip_id == STM32_CHIPID_L496x_L4A6x) { snprintf(map, sz, memory_map_template_L496, (unsigned int)sl->flash_size, (unsigned int)sl->flash_size); - } else if (sl->chip_id == STM32_CHIPID_STM32_H72x) { + } else if (sl->chip_id == STM32_CHIPID_H72x) { snprintf(map, sz, memory_map_template_H72x3x, (unsigned int)sl->flash_size, (unsigned int)sl->flash_pgsz); diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index 78233ec1c..c8147229b 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -9,18 +9,6 @@ #include -// struct stlink_chipid_params *stlink_chipid_get_params_old(uint32_t chipid) { -// struct stlink_chipid_params *params = NULL; - -// for (size_t n = 0; n < STLINK_ARRAY_SIZE(devices); n++) -// if (devices[n].chip_id == chipid) { -// params = &devices[n]; -// break; -// } - -// return (params); -// } - static struct stlink_chipid_params *devicelist; void dump_a_chip (FILE *fp, struct stlink_chipid_params *dev) { @@ -39,22 +27,6 @@ void dump_a_chip (FILE *fp, struct stlink_chipid_params *dev) { fprintf(fp, "flags %d\n\n", dev->flags); } -// static int chipid_params_eq(const struct stlink_chipid_params *p1, const struct stlink_chipid_params *p2) -// { -// return p1->chip_id == p2->chip_id && -// p1->dev_type && p2->dev_type && -// strcmp(p1->dev_type, p2->dev_type) == 0 && -// p1->flash_type == p2->flash_type && -// p1->flash_size_reg == p2->flash_size_reg && -// p1->flash_pagesize == p2->flash_pagesize && -// p1->sram_size == p2->sram_size && -// p1->bootrom_base == p2->bootrom_base && -// p1->bootrom_size == p2->bootrom_size && -// p1->option_base == p2->option_base && -// p1->option_size == p2->option_size && -// p1->flags == p2->flags; -// } - struct stlink_chipid_params *stlink_chipid_get_params(uint32_t chip_id) { struct stlink_chipid_params *params = NULL; // struct stlink_chipid_params *p2; @@ -65,20 +37,6 @@ struct stlink_chipid_params *stlink_chipid_get_params(uint32_t chip_id) { break; } -// p2 = stlink_chipid_get_params_old(chipid); - -// #if 1 -// if (params == NULL) { -// params = p2; -// } else if (!chipid_params_eq(params, p2)) { -// // fprintf (stderr, "Error, chipid params not identical\n"); -// // return NULL; -// fprintf(stderr, "---------- old ------------\n"); -// dump_a_chip(stderr, p2); -// fprintf(stderr, "---------- new ------------\n"); -// dump_a_chip(stderr, params); -// } -// #endif return(params); } @@ -187,38 +145,6 @@ void process_chipfile(char *fname) { devicelist = ts; } -// void dump_chips (void) { -// struct stlink_chipid_params *ts; -// char *p, buf[100]; -// FILE *fp; - -// for (size_t n = 0; n < STLINK_ARRAY_SIZE(devices); n++) { -// ts = &devices[n]; - -// strcpy(buf, ts->dev_type); - -// while ((p = strchr(buf, '/'))) // change slashes to underscore. -// *p = '_'; - -// strcat(buf, ".chip"); -// fp = fopen(buf, "w"); -// fprintf(fp, "# Device Type: %s\n", ts->dev_type); -// fprintf(fp, "# Reference Manual: RM%s\n", ts->ref_manual_id); -// fprintf(fp, "#\n"); -// fprintf(fp, "chip_id %x\n", ts->chip_id); -// fprintf(fp, "flash_type %x\n", ts->flash_type); -// fprintf(fp, "flash_size_reg %x\n", ts->flash_size_reg); -// fprintf(fp, "flash_pagesize %x\n", ts->flash_pagesize); -// fprintf(fp, "sram_size %x\n", ts->sram_size); -// fprintf(fp, "bootrom_base %x\n", ts->bootrom_base); -// fprintf(fp, "bootrom_size %x\n", ts->bootrom_size); -// fprintf(fp, "option_base %x\n", ts->option_base); -// fprintf(fp, "option_size %x\n", ts->option_size); -// fprintf(fp, "flags %x\n\n", ts->flags); -// fclose(fp); -// } -// } - #if defined(STLINK_HAVE_DIRENT_H) #include void init_chipids(char *dir_to_scan) { diff --git a/src/stlink-lib/chipid.h b/src/stlink-lib/chipid.h index 86cd49ddb..8efcd653e 100644 --- a/src/stlink-lib/chipid.h +++ b/src/stlink-lib/chipid.h @@ -4,9 +4,6 @@ #include #include -#ifdef __cplusplus -extern "C" { -#endif /** Chipid parametres */ struct stlink_chipid_params { @@ -28,8 +25,5 @@ struct stlink_chipid_params { struct stlink_chipid_params *stlink_chipid_get_params(uint32_t chipid); void init_chipids(char *dir_to_scan); -#ifdef __cplusplus -} -#endif #endif // STLINK_CHIPID_H_ diff --git a/src/stlink-lib/flash_loader.c b/src/stlink-lib/flash_loader.c index ad52d6567..92b6f0f4b 100644 --- a/src/stlink-lib/flash_loader.c +++ b/src/stlink-lib/flash_loader.c @@ -234,43 +234,43 @@ int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* const uint8_t* loader_code; size_t loader_size; - if (sl->chip_id == STM32_CHIPID_STM32_L1_MD || - sl->chip_id == STM32_CHIPID_STM32_L1_CAT2 || - sl->chip_id == STM32_CHIPID_STM32_L1_MD_PLUS || - sl->chip_id == STM32_CHIPID_STM32_L1_MD_PLUS_HD || - sl->chip_id == STM32_CHIPID_STM32_L152_RE || - sl->chip_id == STM32_CHIPID_STM32_L011 || - sl->chip_id == STM32_CHIPID_STM32_L0 || - sl->chip_id == STM32_CHIPID_STM32_L0_CAT5 || - sl->chip_id == STM32_CHIPID_STM32_L0_CAT2) { + if (sl->chip_id == STM32_CHIPID_L1_MD || + sl->chip_id == STM32_CHIPID_L1_CAT2 || + sl->chip_id == STM32_CHIPID_L1_MD_PLUS || + sl->chip_id == STM32_CHIPID_L1_MD_PLUS_HD || + sl->chip_id == STM32_CHIPID_L152_RE || + sl->chip_id == STM32_CHIPID_L011 || + sl->chip_id == STM32_CHIPID_L0 || + sl->chip_id == STM32_CHIPID_L0_CAT5 || + sl->chip_id == STM32_CHIPID_L0_CAT2) { loader_code = loader_code_stm32lx; loader_size = sizeof(loader_code_stm32lx); } else if (sl->core_id == STM32_CORE_ID_M3_F1 || - sl->chip_id == STM32_CHIPID_STM32_F1_MD || - sl->chip_id == STM32_CHIPID_STM32_F1_HD || - sl->chip_id == STM32_CHIPID_STM32_F1_LD || - sl->chip_id == STM32_CHIPID_STM32_F1_VL_MD_LD || - sl->chip_id == STM32_CHIPID_STM32_F1_VL_HD || - sl->chip_id == STM32_CHIPID_STM32_F1_XLD || - sl->chip_id == STM32_CHIPID_STM32_F1_CONN || - sl->chip_id == STM32_CHIPID_STM32_F3 || - sl->chip_id == STM32_CHIPID_STM32_F3xx_SMALL || - sl->chip_id == STM32_CHIPID_STM32_F303_HD || - sl->chip_id == STM32_CHIPID_STM32_F37x || - sl->chip_id == STM32_CHIPID_STM32_F334) { + sl->chip_id == STM32_CHIPID_F1_MD || + sl->chip_id == STM32_CHIPID_F1_HD || + sl->chip_id == STM32_CHIPID_F1_LD || + sl->chip_id == STM32_CHIPID_F1_VL_MD_LD || + sl->chip_id == STM32_CHIPID_F1_VL_HD || + sl->chip_id == STM32_CHIPID_F1_XLD || + sl->chip_id == STM32_CHIPID_F1_CONN || + sl->chip_id == STM32_CHIPID_F3 || + sl->chip_id == STM32_CHIPID_F3xx_SMALL || + sl->chip_id == STM32_CHIPID_F303_HD || + sl->chip_id == STM32_CHIPID_F37x || + sl->chip_id == STM32_CHIPID_F334) { loader_code = loader_code_stm32vl; loader_size = sizeof(loader_code_stm32vl); - } else if (sl->chip_id == STM32_CHIPID_STM32_F2 || - sl->chip_id == STM32_CHIPID_STM32_F4 || - sl->chip_id == STM32_CHIPID_STM32_F4_DE || - sl->chip_id == STM32_CHIPID_STM32_F4_LP || - sl->chip_id == STM32_CHIPID_STM32_F4_HD || - sl->chip_id == STM32_CHIPID_STM32_F4_DSI || - sl->chip_id == STM32_CHIPID_STM32_F410 || - sl->chip_id == STM32_CHIPID_STM32_F411xx || - sl->chip_id == STM32_CHIPID_STM32_F412 || - sl->chip_id == STM32_CHIPID_STM32_F413 || - sl->chip_id == STM32_CHIPID_STM32_F446) { + } else if (sl->chip_id == STM32_CHIPID_F2 || + sl->chip_id == STM32_CHIPID_F4 || + sl->chip_id == STM32_CHIPID_F4_DE || + sl->chip_id == STM32_CHIPID_F4_LP || + sl->chip_id == STM32_CHIPID_F4_HD || + sl->chip_id == STM32_CHIPID_F4_DSI || + sl->chip_id == STM32_CHIPID_F410 || + sl->chip_id == STM32_CHIPID_F411xx || + sl->chip_id == STM32_CHIPID_F412 || + sl->chip_id == STM32_CHIPID_F413 || + sl->chip_id == STM32_CHIPID_F446) { int retval; retval = loader_v_dependent_assignment(sl, &loader_code, &loader_size, @@ -279,9 +279,9 @@ int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* if (retval == -1) { return(retval); } } else if (sl->core_id == STM32_CORE_ID_M7_F7 || - sl->chip_id == STM32_CHIPID_STM32_F7 || - sl->chip_id == STM32_CHIPID_STM32_F76xxx || - sl->chip_id == STM32_CHIPID_STM32_F72xxx) { + sl->chip_id == STM32_CHIPID_F7 || + sl->chip_id == STM32_CHIPID_F76xxx || + sl->chip_id == STM32_CHIPID_F72xxx) { int retval; retval = loader_v_dependent_assignment(sl, &loader_code, &loader_size, @@ -289,19 +289,19 @@ int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* loader_code_stm32f7_lv, sizeof(loader_code_stm32f7_lv)); if (retval == -1) { return(retval); } - } else if (sl->chip_id == STM32_CHIPID_STM32_F0 || - sl->chip_id == STM32_CHIPID_STM32_F04 || - sl->chip_id == STM32_CHIPID_STM32_F0_CAN || - sl->chip_id == STM32_CHIPID_STM32_F0xx_SMALL || - sl->chip_id == STM32_CHIPID_STM32_F09x) { + } else if (sl->chip_id == STM32_CHIPID_F0 || + sl->chip_id == STM32_CHIPID_F04 || + sl->chip_id == STM32_CHIPID_F0_CAN || + sl->chip_id == STM32_CHIPID_F0xx_SMALL || + sl->chip_id == STM32_CHIPID_F09x) { loader_code = loader_code_stm32f0; loader_size = sizeof(loader_code_stm32f0); - } else if ((sl->chip_id == STM32_CHIPID_STM32_L4) || - (sl->chip_id == STM32_CHIPID_STM32_L41x_L42x) || - (sl->chip_id == STM32_CHIPID_STM32_L43x_L44x) || - (sl->chip_id == STM32_CHIPID_STM32_L45x_L46x) || - (sl->chip_id == STM32_CHIPID_STM32_L4Rx) || - (sl->chip_id == STM32_CHIPID_STM32_L496x_L4A6x)) { + } else if ((sl->chip_id == STM32_CHIPID_L4) || + (sl->chip_id == STM32_CHIPID_L41x_L42x) || + (sl->chip_id == STM32_CHIPID_L43x_L44x) || + (sl->chip_id == STM32_CHIPID_L45x_L46x) || + (sl->chip_id == STM32_CHIPID_L4Rx) || + (sl->chip_id == STM32_CHIPID_L496x_L4A6x)) { loader_code = loader_code_stm32l4; loader_size = sizeof(loader_code_stm32l4); } else { diff --git a/src/stlink-lib/flash_loader.h b/src/stlink-lib/flash_loader.h index 29fd5b068..bac99bdb4 100644 --- a/src/stlink-lib/flash_loader.h +++ b/src/stlink-lib/flash_loader.h @@ -12,16 +12,10 @@ #include -#ifdef __cplusplus -extern "C" { -#endif int stlink_flash_loader_init(stlink_t *sl, flash_loader_t* fl); int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size); int stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, const uint8_t* buf, size_t size); -#ifdef __cplusplus -} -#endif #endif // STLINK_FLASH_LOADER_H_ diff --git a/src/stlink-lib/sg.h b/src/stlink-lib/sg.h index f34b2e122..4161d3967 100644 --- a/src/stlink-lib/sg.h +++ b/src/stlink-lib/sg.h @@ -9,9 +9,6 @@ #include #include -#ifdef __cplusplus -extern "C" { -#endif /* Device access */ #define RDWR 0 @@ -60,8 +57,5 @@ struct stlink_libsg { stlink_t* stlink_v1_open(const int verbose, int reset); -#ifdef __cplusplus -} -#endif #endif // STLINK_SG_H diff --git a/src/stlink-lib/usb.h b/src/stlink-lib/usb.h index c6b71ba4e..d04ef2dca 100644 --- a/src/stlink-lib/usb.h +++ b/src/stlink-lib/usb.h @@ -12,9 +12,6 @@ #include #include "logging.h" -#ifdef __cplusplus -extern "C" { -#endif #define STLINK_USB_VID_ST 0x0483 #define STLINK_USB_PID_STLINK 0x3744 @@ -73,8 +70,5 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, enum connect_type connect, size_t stlink_probe_usb(stlink_t **stdevs[], enum connect_type connect, int freq); void stlink_probe_usb_free(stlink_t **stdevs[], size_t size); -#ifdef __cplusplus -} -#endif #endif // STLINK_USB_H diff --git a/src/win32/mmap.h b/src/win32/mmap.h index 1f2e756cb..67558b0cc 100644 --- a/src/win32/mmap.h +++ b/src/win32/mmap.h @@ -13,16 +13,10 @@ #define MAP_ANONYMOUS (1 << 5) #define MAP_FAILED ((void *)-1) -#ifdef __cplusplus -extern "C" { -#endif void *mmap(void *addr, size_t len, int prot, int flags, int fd, long long offset); int munmap(void *addr, size_t len); -#ifdef __cplusplus -} -#endif #endif /* HAVE_SYS_MMAN_H */ diff --git a/src/win32/sys_time.h b/src/win32/sys_time.h index 39f97f739..3f35390c3 100644 --- a/src/win32/sys_time.h +++ b/src/win32/sys_time.h @@ -12,15 +12,8 @@ struct timezone { int tz_dsttime; }; -#ifdef __cplusplus -extern "C" { -#endif - int gettimeofday(struct timeval *tv, struct timezone *tz); -#ifdef __cplusplus -} -#endif #endif /* STLINK_HAVE_SYS_TIME_H */ From a5d644160b071fb0ef8f79d38043a3c1299ee750 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 16 Jan 2022 20:28:53 +0100 Subject: [PATCH 356/503] Fixed define names and removed old include. --- src/common.c | 4 ++-- src/stlink-lib/chipid.c | 1 - 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/src/common.c b/src/common.c index 1a6c89c63..08f2c5dc1 100644 --- a/src/common.c +++ b/src/common.c @@ -2645,8 +2645,8 @@ int stlink_erase_flash_mass(stlink_t *sl) { int err = 0; // TODO: User MER bit to mass-erase WB series. - if (sl->flash_type == STLINK_FLASH_TYPE_L0_L1 || - sl->flash_type == STLINK_FLASH_TYPE_WB_WL) { + if (sl->flash_type == STM32_FLASH_TYPE_L0_L1 || + sl->flash_type == STM32_FLASH_TYPE_WB_WL) { err = stlink_erase_flash_section(sl, sl->flash_base, sl->flash_size, false); diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index c8147229b..dbfd2882d 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -1,6 +1,5 @@ #include #include "chipid.h" -//#include "chipid_db_old.h" #include #include From 80b05c547e34a214ffd9171e600051e8474a9f0a Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Mon, 17 Jan 2022 00:39:57 +0100 Subject: [PATCH 357/503] Updated MCU core-ids --- inc/stm32.h | 52 +++++++++++++++++++++++++---------- src/common.c | 2 +- src/st-util/gdb-server.c | 2 +- src/stlink-lib/flash_loader.c | 4 +-- 4 files changed, 42 insertions(+), 18 deletions(-) diff --git a/inc/stm32.h b/inc/stm32.h index 2e8ed6889..56176bd6f 100644 --- a/inc/stm32.h +++ b/inc/stm32.h @@ -7,20 +7,44 @@ #ifndef STM32_H #define STM32_H -/* Cortex-M core ids (CPUTAPID) */ -#define STM32_CORE_ID_M3_F2_JTAG 0x0ba00477 // unused // F2 JTAG (RM0033 p.1326) -//#define STM32_CORE_ID_M33_JTAG 0x0ba04477 // unused // L5 JTAG -#define STM32_CORE_ID_M0 0x0bb11477 // unused // F0 -#define STM32_CORE_ID_M0P 0x0bc11477 // unused // L0, G0 -#define STM32_CORE_ID_M33 0x0be01477 // unused // L5 SWD (RM0351 p.2029) -#define STM32_CORE_ID_M33_JTAG 0x0be02477 // unused // L5 JTAG (RM0438 p.2029) -#define STM32_CORE_ID_M3_F1 0x1ba01477 // F1 (RM0008 p.1092) -#define STM32_CORE_ID_M4F_L4 0x1ba01477 // unused // L4 (RM0351 p.1845) -#define STM32_CORE_ID_M4F_F4 0x2ba01477 // unused // F4 (RM0090 p.1695) -#define STM32_CORE_ID_M4F_F4_JTAG 0x4ba00477 // unused // F4 JTAG (RM090 p.1691) -#define STM32_CORE_ID_M7_F7 0x5ba02477 // F7 -#define STM32_CORE_ID_M7_H7 0x6ba02477 // H7 -#define STM32_CORE_ID_M7_H7_JTAG 0x6ba00477 // H7 JTAG (RM0433 p.3065) +/* STM32 Cortex-M core ids (CPUTAPID) */ +#define STM32_CORE_ID_M0_SWD 0x0bb11477 // (RM0091 Section 32.5.3) F0 SW-DP + // (RM0444 Section 40.5.3) G0 SW-DP + +#define STM32_CORE_ID_M0P_SWD 0x0bc11477 // (RM0385 Section 27.5.3) L0 SW-DP + +#define STM32_CORE_ID_M3_r1p1_SWD 0x1ba01477 // (RM0008 Section 31.8.3) F1 SW-DP +#define STM32_CORE_ID_M3_r1p1_JTAG 0x3ba00477 // (RM0008 Section 31.6.3) F1 JTAG + +#define STM32_CORE_ID_M3_r2p0_SWD 0x2ba01477 // (RM0033 Section 32.8.3) F2 SW-DP + // (RM0038 Section 30.8.3) L1 SW-DP +#define STM32_CORE_ID_M3_r2p0_JTAG 0x0ba00477 // (RM0033 Section 32.6.3) F2 JTAG + // (RM0038 Section 30.6.2) L1 JTAG + +#define STM32_CORE_ID_M4_r0p1_SWD 0x1ba01477 // (RM0316 Section 33.8.3) F3 SW-DP + // (RM0351 Section 48.8.3) L4 SW-DP + // (RM0432 Section 57.8.3) L4+ SW-DP +#define STM32_CORE_ID_M4_r0p1_JTAG 0x4ba00477 // (RM0316 Section 33.6.3) F3 JTAG + // (RM0351 Section 48.6.3) L4 JTAG + // (RM0432 Section 57.6.3) L4+ JTAG + +#define STM32_CORE_ID_M4F_r0p1_SWD 0x2ba01477 // (RM0090 Section 38.8.3) F4 SW-DP + // (RM0090 Section 47.8.3) G4 SW-DP +#define STM32_CORE_ID_M4F_r0p1_JTAG 0x4ba00477 // (RM0090 Section 38.6.3) F4 JTAG + // (RM0090 Section 47.6.3) G4 JTAG + +#define STM32_CORE_ID_M7F_SWD 0x5ba02477 // (RM0385 Section 40.8.3) F7 SW-DP +#define STM32_CORE_ID_M7F_JTAG 0x5ba00477 // (RM0385 Section 40.6.3) F7 JTAG + +#define STM32_CORE_ID_M7F_H7_SWD 0x6ba02477 // (RM0433 Section 60.4.1) H7 SW-DP +#define STM32_CORE_ID_M7F_H7_JTAG 0x6ba00477 // (RM0433 Section 60.4.1) H7 JTAG + +#define STM32_CORE_ID_M33_SWD 0x0be02477 // (RM0438 Section 52.2.10) L5 SW-DP + // (RM0456 Section 65.3.3) U5 SW-DP +#define STM32_CORE_ID_M33_JTAGD 0x0be01477 // (RM0438 Section 52.2.10) L5 JTAG-DP + // (RM0456 Section 65.3.3) U5 JTAG-DP +#define STM32_CORE_ID_M33_JTAG 0x0ba04477 // (RM0438 Section 52.2.8) L5 JTAG + // (RM0456 Section 56.3.1) U5 JTAG /* STM32 flash types */ // New flash type definitions must go before STM32_FLASH_TYPE_UNDEFINED diff --git a/src/common.c b/src/common.c index 08f2c5dc1..266722b91 100644 --- a/src/common.c +++ b/src/common.c @@ -1137,7 +1137,7 @@ int stlink_chip_id(stlink_t *sl, uint32_t *chip_id) { * */ - if ((sl->core_id == STM32_CORE_ID_M7_H7 || sl->core_id == STM32_CORE_ID_M7_H7_JTAG) && + if ((sl->core_id == STM32_CORE_ID_M7F_H7_SWD || sl->core_id == STM32_CORE_ID_M7F_H7_JTAG) && cpu_id.part == STLINK_REG_CMx_CPUID_PARTNO_CM7) { // STM32H7 chipid in 0x5c001000 (RM0433 pg3189) ret = stlink_read_debug32(sl, 0x5c001000, chip_id); diff --git a/src/st-util/gdb-server.c b/src/st-util/gdb-server.c index 2b6875d9f..4f7a1fe2e 100644 --- a/src/st-util/gdb-server.c +++ b/src/st-util/gdb-server.c @@ -559,7 +559,7 @@ char* make_memory_map(stlink_t *sl) { strcpy(map, memory_map_template_F4); } else if (sl->chip_id == STM32_CHIPID_F4_DE) { strcpy(map, memory_map_template_F4_DE); - } else if (sl->core_id == STM32_CORE_ID_M7_F7) { + } else if (sl->core_id == STM32_CORE_ID_M7F_SWD) { snprintf(map, sz, memory_map_template_F7, (unsigned int)sl->sram_size); } else if (sl->chip_id == STM32_CHIPID_H74xxx) { diff --git a/src/stlink-lib/flash_loader.c b/src/stlink-lib/flash_loader.c index 92b6f0f4b..2b47c1114 100644 --- a/src/stlink-lib/flash_loader.c +++ b/src/stlink-lib/flash_loader.c @@ -245,7 +245,7 @@ int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* sl->chip_id == STM32_CHIPID_L0_CAT2) { loader_code = loader_code_stm32lx; loader_size = sizeof(loader_code_stm32lx); - } else if (sl->core_id == STM32_CORE_ID_M3_F1 || + } else if (sl->core_id == STM32_CORE_ID_M3_r1p1_SWD || sl->chip_id == STM32_CHIPID_F1_MD || sl->chip_id == STM32_CHIPID_F1_HD || sl->chip_id == STM32_CHIPID_F1_LD || @@ -278,7 +278,7 @@ int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* loader_code_stm32f4_lv, sizeof(loader_code_stm32f4_lv)); if (retval == -1) { return(retval); } - } else if (sl->core_id == STM32_CORE_ID_M7_F7 || + } else if (sl->core_id == STM32_CORE_ID_M7F_SWD || sl->chip_id == STM32_CHIPID_F7 || sl->chip_id == STM32_CHIPID_F76xxx || sl->chip_id == STM32_CHIPID_F72xxx) { From e5ff479d4829843d04fe51931256ac095ad4c0b8 Mon Sep 17 00:00:00 2001 From: hydroconstructor Date: Thu, 20 Jan 2022 12:54:14 +0400 Subject: [PATCH 358/503] #1216 refactoring of common.c File divided to some parts. Functions with "flash" in names extracted to common_flash.c, with "option" extracted to option.c etc. Removed unnecessary headers. Removed one single function which was used nowhere. And so on. Project built under Windows and seems to be working. --- CMakeLists.txt | 10 +- inc/stlink.h | 6 +- inc/stm32flash.h | 340 +++++++++++ src/calculate.c | 74 +++ src/calculate.h | 15 + src/common.h | 15 + src/common_flash.c | 1374 ++++++++++++++++++++++++++++++++++++++++++++ src/common_flash.h | 27 + src/flashloader.c | 481 ++++++++++++++++ src/map_file.c | 57 ++ src/map_file.h | 28 + src/option.c | 1026 +++++++++++++++++++++++++++++++++ src/read_write.c | 142 +++++ 13 files changed, 3592 insertions(+), 3 deletions(-) create mode 100644 inc/stm32flash.h create mode 100644 src/calculate.c create mode 100644 src/calculate.h create mode 100644 src/common.h create mode 100644 src/common_flash.c create mode 100644 src/common_flash.h create mode 100644 src/flashloader.c create mode 100644 src/map_file.c create mode 100644 src/map_file.h create mode 100644 src/option.c create mode 100644 src/read_write.c diff --git a/CMakeLists.txt b/CMakeLists.txt index 66bf34e3e..a3338df71 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -2,7 +2,7 @@ # General cmake settings ### -cmake_minimum_required(VERSION 3.10.2) +cmake_minimum_required(VERSION 3.7.2) cmake_policy(SET CMP0042 NEW) set(CMAKE_MODULE_PATH ${CMAKE_SOURCE_DIR}/cmake/modules) set(CMAKE_ARCHIVE_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}/lib) @@ -110,6 +110,8 @@ add_subdirectory(inc) set(STLINK_HEADERS inc/backend.h inc/stlink.h + src/common_flash.h + src/calculate.h src/stlink-lib/commands.h src/stlink-lib/libusb_settings.h src/stlink-lib/reg.h @@ -123,7 +125,13 @@ set(STLINK_HEADERS ) set(STLINK_SOURCE + src/read_write.c src/common.c + src/option.c + src/common_flash.c + src/map_file.c + src/flashloader.c + src/calculate.c src/stlink-lib/chipid.c src/stlink-lib/flash_loader.c src/stlink-lib/logging.c diff --git a/inc/stlink.h b/inc/stlink.h index df13aa7c9..a8a52458d 100644 --- a/inc/stlink.h +++ b/inc/stlink.h @@ -1,3 +1,4 @@ + /* * File: stlink.h * @@ -13,6 +14,7 @@ #include #include "stm32.h" +#include "stm32flash.h" #ifdef __cplusplus extern "C" { @@ -284,7 +286,7 @@ int stlink_mwrite_sram(stlink_t *sl, uint8_t* data, uint32_t length, stm32_addr_ int stlink_fwrite_sram(stlink_t *sl, const char* path, stm32_addr_t addr); int stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, uint32_t length); -int stlink_chip_id(stlink_t *sl, uint32_t *chip_id); +//int stlink_chip_id(stlink_t *sl, uint32_t *chip_id); int stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid); int stlink_erase_flash_page(stlink_t* sl, stm32_addr_t flashaddr); @@ -292,7 +294,7 @@ uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr); int stlink_check_address_range_validity(stlink_t *sl, stm32_addr_t addr, size_t size); int stlink_check_address_alignment(stlink_t *sl, stm32_addr_t addr); uint16_t read_uint16(const unsigned char *c, const int pt); -void stlink_core_stat(stlink_t *sl); +//void stlink_core_stat(stlink_t *sl); void stlink_print_data(stlink_t *sl); unsigned int is_bigendian(void); uint32_t read_uint32(const unsigned char *c, const int pt); diff --git a/inc/stm32flash.h b/inc/stm32flash.h new file mode 100644 index 000000000..01c76946c --- /dev/null +++ b/inc/stm32flash.h @@ -0,0 +1,340 @@ +#ifndef STM32FLASH_H +#define STM32FLASH_H + +/* stm32f FPEC flash controller interface, pm0063 manual */ +// TODO - all of this needs to be abstracted out.... +// STM32F05x is identical, based on RM0091 (DM00031936, Doc ID 018940 Rev 2, +// August 2012) +#define FLASH_REGS_ADDR 0x40022000 +#define FLASH_REGS_SIZE 0x28 + +#define FLASH_ACR (FLASH_REGS_ADDR + 0x00) +#define FLASH_KEYR (FLASH_REGS_ADDR + 0x04) +#define FLASH_OPTKEYR (FLASH_REGS_ADDR + 0x08) +#define FLASH_SR (FLASH_REGS_ADDR + 0x0c) +#define FLASH_CR (FLASH_REGS_ADDR + 0x10) +#define FLASH_AR (FLASH_REGS_ADDR + 0x14) +#define FLASH_OBR (FLASH_REGS_ADDR + 0x1c) +#define FLASH_WRPR (FLASH_REGS_ADDR + 0x20) + +// STM32F10x_XL has two flash memory banks with separate registers to control +// the second bank. +#define FLASH_KEYR2 (FLASH_REGS_ADDR + 0x44) +#define FLASH_SR2 (FLASH_REGS_ADDR + 0x4c) +#define FLASH_CR2 (FLASH_REGS_ADDR + 0x50) +#define FLASH_AR2 (FLASH_REGS_ADDR + 0x54) + +// For STM32F05x, the RDPTR_KEY may be wrong, but as it is not used anywhere... +#define FLASH_RDPTR_KEY 0x00a5 +#define FLASH_KEY1 0x45670123 +#define FLASH_KEY2 0xcdef89ab + +#define FLASH_L0_PRGKEY1 0x8c9daebf +#define FLASH_L0_PRGKEY2 0x13141516 + +#define FLASH_L0_PEKEY1 0x89abcdef +#define FLASH_L0_PEKEY2 0x02030405 + +#define FLASH_OPTKEY1 0x08192A3B +#define FLASH_OPTKEY2 0x4C5D6E7F + +#define FLASH_F0_OPTKEY1 0x45670123 +#define FLASH_F0_OPTKEY2 0xCDEF89AB + +#define FLASH_L0_OPTKEY1 0xFBEAD9C8 +#define FLASH_L0_OPTKEY2 0x24252627 + +#define FLASH_SR_BSY 0 +#define FLASH_SR_PG_ERR 2 +#define FLASH_SR_WRPRT_ERR 4 +#define FLASH_SR_EOP 5 + +#define FLASH_SR_ERROR_MASK ((1 << FLASH_SR_PG_ERR) | (1 << FLASH_SR_WRPRT_ERR)) + +#define FLASH_CR_PG 0 +#define FLASH_CR_PER 1 +#define FLASH_CR_MER 2 +#define FLASH_CR_OPTPG 4 +#define FLASH_CR_OPTER 5 +#define FLASH_CR_STRT 6 +#define FLASH_CR_LOCK 7 +#define FLASH_CR_OPTWRE 9 +#define FLASH_CR_OBL_LAUNCH 13 + +#define STM32L_FLASH_REGS_ADDR ((uint32_t)0x40023c00) +#define STM32L_FLASH_ACR (STM32L_FLASH_REGS_ADDR + 0x00) +#define STM32L_FLASH_PECR (STM32L_FLASH_REGS_ADDR + 0x04) +#define STM32L_FLASH_PDKEYR (STM32L_FLASH_REGS_ADDR + 0x08) +#define STM32L_FLASH_PEKEYR (STM32L_FLASH_REGS_ADDR + 0x0c) +#define STM32L_FLASH_PRGKEYR (STM32L_FLASH_REGS_ADDR + 0x10) +#define STM32L_FLASH_OPTKEYR (STM32L_FLASH_REGS_ADDR + 0x14) +#define STM32L_FLASH_SR (STM32L_FLASH_REGS_ADDR + 0x18) +#define STM32L_FLASH_OBR (STM32L_FLASH_REGS_ADDR + 0x1c) +#define STM32L_FLASH_WRPR (STM32L_FLASH_REGS_ADDR + 0x20) +#define FLASH_L1_FPRG 10 +#define FLASH_L1_PROG 3 + +// Flash registers common to STM32G0 and STM32G4 series. +#define STM32Gx_FLASH_REGS_ADDR ((uint32_t)0x40022000) +#define STM32Gx_FLASH_ACR (STM32Gx_FLASH_REGS_ADDR + 0x00) +#define STM32Gx_FLASH_KEYR (STM32Gx_FLASH_REGS_ADDR + 0x08) +#define STM32Gx_FLASH_OPTKEYR (STM32Gx_FLASH_REGS_ADDR + 0x0c) +#define STM32Gx_FLASH_SR (STM32Gx_FLASH_REGS_ADDR + 0x10) +#define STM32Gx_FLASH_CR (STM32Gx_FLASH_REGS_ADDR + 0x14) +#define STM32Gx_FLASH_ECCR (STM32Gx_FLASH_REGS_ADDR + 0x18) +#define STM32Gx_FLASH_OPTR (STM32Gx_FLASH_REGS_ADDR + 0x20) + +// G0 (RM0444 Table 1, sec 3.7) +// Mostly the same as G4 chips, but the notation +// varies a bit after the 'OPTR' register. +#define STM32G0_FLASH_REGS_ADDR (STM32Gx_FLASH_REGS_ADDR) +#define STM32G0_FLASH_PCROP1ASR (STM32G0_FLASH_REGS_ADDR + 0x24) +#define STM32G0_FLASH_PCROP1AER (STM32G0_FLASH_REGS_ADDR + 0x28) +#define STM32G0_FLASH_WRP1AR (STM32G0_FLASH_REGS_ADDR + 0x2C) +#define STM32G0_FLASH_WRP1BR (STM32G0_FLASH_REGS_ADDR + 0x30) +#define STM32G0_FLASH_PCROP1BSR (STM32G0_FLASH_REGS_ADDR + 0x34) +#define STM32G0_FLASH_PCROP1BER (STM32G0_FLASH_REGS_ADDR + 0x38) +#define STM32G0_FLASH_SECR (STM32G0_FLASH_REGS_ADDR + 0x80) + +// G4 (RM0440 Table 17, sec 3.7.19) +// Mostly the same as STM32G0 chips, but there are a few extra +// registers because 'cat 3' devices can have two Flash banks. +#define STM32G4_FLASH_REGS_ADDR (STM32Gx_FLASH_REGS_ADDR) +#define STM32G4_FLASH_PDKEYR (STM32G4_FLASH_REGS_ADDR + 0x04) +#define STM32G4_FLASH_PCROP1SR (STM32G4_FLASH_REGS_ADDR + 0x24) +#define STM32G4_FLASH_PCROP1ER (STM32G4_FLASH_REGS_ADDR + 0x28) +#define STM32G4_FLASH_WRP1AR (STM32G4_FLASH_REGS_ADDR + 0x2C) +#define STM32G4_FLASH_WRP1BR (STM32G4_FLASH_REGS_ADDR + 0x30) +#define STM32G4_FLASH_PCROP2SR (STM32G4_FLASH_REGS_ADDR + 0x44) +#define STM32G4_FLASH_PCROP2ER (STM32G4_FLASH_REGS_ADDR + 0x48) +#define STM32G4_FLASH_WRP2AR (STM32G4_FLASH_REGS_ADDR + 0x4C) +#define STM32G4_FLASH_WRP2BR (STM32G4_FLASH_REGS_ADDR + 0x50) +#define STM32G4_FLASH_SEC1R (STM32G4_FLASH_REGS_ADDR + 0x70) +#define STM32G4_FLASH_SEC2R (STM32G4_FLASH_REGS_ADDR + 0x74) + +// G0/G4 FLASH control register +#define STM32Gx_FLASH_CR_PG (0) /* Program */ +#define STM32Gx_FLASH_CR_PER (1) /* Page erase */ +#define STM32Gx_FLASH_CR_MER1 (2) /* Mass erase */ +#define STM32Gx_FLASH_CR_PNB (3) /* Page number */ +#define STM32G0_FLASH_CR_PNG_LEN (5) /* STM32G0: 5 page number bits */ +#define STM32G4_FLASH_CR_PNG_LEN (7) /* STM32G4: 7 page number bits */ +#define STM32Gx_FLASH_CR_MER2 (15) /* Mass erase (2nd bank)*/ +#define STM32Gx_FLASH_CR_STRT (16) /* Start */ +#define STM32Gx_FLASH_CR_OPTSTRT \ + (17) /* Start of modification of option bytes */ +#define STM32Gx_FLASH_CR_FSTPG (18) /* Fast programming */ +#define STM32Gx_FLASH_CR_EOPIE (24) /* End of operation interrupt enable */ +#define STM32Gx_FLASH_CR_ERRIE (25) /* Error interrupt enable */ +#define STM32Gx_FLASH_CR_OBL_LAUNCH (27) /* Forces the option byte loading */ +#define STM32Gx_FLASH_CR_OPTLOCK (30) /* Options Lock */ +#define STM32Gx_FLASH_CR_LOCK (31) /* FLASH_CR Lock */ + +// G0/G4 FLASH status register +#define STM32Gx_FLASH_SR_ERROR_MASK (0x3fa) +#define STM32Gx_FLASH_SR_PROGERR (3) +#define STM32Gx_FLASH_SR_WRPERR (4) +#define STM32Gx_FLASH_SR_PGAERR (5) +#define STM32Gx_FLASH_SR_BSY (16) /* FLASH_SR Busy */ +#define STM32Gx_FLASH_SR_EOP (0) /* FLASH_EOP End of Operation */ + +// G4 FLASH option register +#define STM32G4_FLASH_OPTR_DBANK (22) /* FLASH_OPTR Dual Bank Mode */ + +// WB (RM0434) +#define STM32WB_FLASH_REGS_ADDR ((uint32_t)0x58004000) +#define STM32WB_FLASH_ACR (STM32WB_FLASH_REGS_ADDR + 0x00) +#define STM32WB_FLASH_KEYR (STM32WB_FLASH_REGS_ADDR + 0x08) +#define STM32WB_FLASH_OPT_KEYR (STM32WB_FLASH_REGS_ADDR + 0x0C) +#define STM32WB_FLASH_SR (STM32WB_FLASH_REGS_ADDR + 0x10) +#define STM32WB_FLASH_CR (STM32WB_FLASH_REGS_ADDR + 0x14) +#define STM32WB_FLASH_ECCR (STM32WB_FLASH_REGS_ADDR + 0x18) +#define STM32WB_FLASH_OPTR (STM32WB_FLASH_REGS_ADDR + 0x20) +#define STM32WB_FLASH_PCROP1ASR (STM32WB_FLASH_REGS_ADDR + 0x24) +#define STM32WB_FLASH_PCROP1AER (STM32WB_FLASH_REGS_ADDR + 0x28) +#define STM32WB_FLASH_WRP1AR (STM32WB_FLASH_REGS_ADDR + 0x2C) +#define STM32WB_FLASH_WRP1BR (STM32WB_FLASH_REGS_ADDR + 0x30) +#define STM32WB_FLASH_PCROP1BSR (STM32WB_FLASH_REGS_ADDR + 0x34) +#define STM32WB_FLASH_PCROP1BER (STM32WB_FLASH_REGS_ADDR + 0x38) +#define STM32WB_FLASH_IPCCBR (STM32WB_FLASH_REGS_ADDR + 0x3C) +#define STM32WB_FLASH_C2ACR (STM32WB_FLASH_REGS_ADDR + 0x5C) +#define STM32WB_FLASH_C2SR (STM32WB_FLASH_REGS_ADDR + 0x60) +#define STM32WB_FLASH_C2CR (STM32WB_FLASH_REGS_ADDR + 0x64) +#define STM32WB_FLASH_SFR (STM32WB_FLASH_REGS_ADDR + 0x80) +#define STM32WB_FLASH_SRRVR (STM32WB_FLASH_REGS_ADDR + 0x84) + +// WB Flash control register. +#define STM32WB_FLASH_CR_STRT (16) /* Start */ +#define STM32WB_FLASH_CR_OPTLOCK (30) /* Option Lock */ +#define STM32WB_FLASH_CR_LOCK (31) /* Lock */ +// WB Flash status register. +#define STM32WB_FLASH_SR_ERROR_MASK (0x3f8) /* SR [9:3] */ +#define STM32WB_FLASH_SR_PROGERR (3) /* Programming alignment error */ +#define STM32WB_FLASH_SR_WRPERR (4) /* Write protection error */ +#define STM32WB_FLASH_SR_PGAERR (5) /* Programming error */ +#define STM32WB_FLASH_SR_BSY (16) /* Busy */ + +// 32L4 register base is at FLASH_REGS_ADDR (0x40022000) +#define STM32L4_FLASH_KEYR (FLASH_REGS_ADDR + 0x08) +#define STM32L4_FLASH_OPTKEYR (FLASH_REGS_ADDR + 0x0C) +#define STM32L4_FLASH_SR (FLASH_REGS_ADDR + 0x10) +#define STM32L4_FLASH_CR (FLASH_REGS_ADDR + 0x14) +#define STM32L4_FLASH_OPTR (FLASH_REGS_ADDR + 0x20) + +#define STM32L4_FLASH_SR_ERROR_MASK 0x3f8 /* SR [9:3] */ +#define STM32L4_FLASH_SR_PROGERR 3 +#define STM32L4_FLASH_SR_WRPERR 4 +#define STM32L4_FLASH_SR_PGAERR 5 +#define STM32L4_FLASH_SR_BSY 16 + +#define STM32L4_FLASH_CR_LOCK 31 /* Lock control register */ +#define STM32L4_FLASH_CR_OPTLOCK 30 /* Lock option bytes */ +#define STM32L4_FLASH_CR_PG 0 /* Program */ +#define STM32L4_FLASH_CR_PER 1 /* Page erase */ +#define STM32L4_FLASH_CR_MER1 2 /* Bank 1 erase */ +#define STM32L4_FLASH_CR_MER2 15 /* Bank 2 erase */ +#define STM32L4_FLASH_CR_STRT 16 /* Start command */ +#define STM32L4_FLASH_CR_OPTSTRT 17 /* Start writing option bytes */ +#define STM32L4_FLASH_CR_BKER 11 /* Bank select for page erase */ +#define STM32L4_FLASH_CR_PNB 3 /* Page number (8 bits) */ +#define STM32L4_FLASH_CR_OBL_LAUNCH 27 /* Option bytes reload */ +// Bits requesting flash operations (useful when we want to clear them) +#define STM32L4_FLASH_CR_OPBITS \ + (uint32_t)((1lu << STM32L4_FLASH_CR_PG) | (1lu << STM32L4_FLASH_CR_PER) | \ + (1lu << STM32L4_FLASH_CR_MER1) | (1lu << STM32L4_FLASH_CR_MER1)) +// Page is fully specified by BKER and PNB +#define STM32L4_FLASH_CR_PAGEMASK (uint32_t)(0x1fflu << STM32L4_FLASH_CR_PNB) + +#define STM32L4_FLASH_OPTR_DUALBANK 21 + +// STM32L0x flash register base and offsets RM0090 - DM00031020.pdf +#define STM32L0_FLASH_REGS_ADDR ((uint32_t)0x40022000) + +#define STM32L0_FLASH_PELOCK (0) +#define STM32L0_FLASH_OPTLOCK (2) +#define STM32L0_FLASH_OBL_LAUNCH (18) + +#define STM32L0_FLASH_SR_ERROR_MASK 0x00013F00 +#define STM32L0_FLASH_SR_WRPERR 8 +#define STM32L0_FLASH_SR_PGAERR 9 +#define STM32L0_FLASH_SR_NOTZEROERR 16 + +#define FLASH_ACR_OFF ((uint32_t)0x00) +#define FLASH_PECR_OFF ((uint32_t)0x04) +#define FLASH_PDKEYR_OFF ((uint32_t)0x08) +#define FLASH_PEKEYR_OFF ((uint32_t)0x0c) +#define FLASH_PRGKEYR_OFF ((uint32_t)0x10) +#define FLASH_OPTKEYR_OFF ((uint32_t)0x14) +#define FLASH_SR_OFF ((uint32_t)0x18) +#define FLASH_OBR_OFF ((uint32_t)0x1c) +#define FLASH_WRPR_OFF ((uint32_t)0x20) + +// STM32F7 +#define FLASH_F7_REGS_ADDR ((uint32_t)0x40023c00) +#define FLASH_F7_KEYR (FLASH_F7_REGS_ADDR + 0x04) +#define FLASH_F7_OPT_KEYR (FLASH_F7_REGS_ADDR + 0x08) +#define FLASH_F7_SR (FLASH_F7_REGS_ADDR + 0x0c) +#define FLASH_F7_CR (FLASH_F7_REGS_ADDR + 0x10) +#define FLASH_F7_OPTCR (FLASH_F7_REGS_ADDR + 0x14) +#define FLASH_F7_OPTCR1 (FLASH_F7_REGS_ADDR + 0x18) +#define FLASH_F7_OPTCR_LOCK 0 +#define FLASH_F7_OPTCR_START 1 +#define FLASH_F7_CR_STRT 16 +#define FLASH_F7_CR_LOCK 31 +#define FLASH_F7_CR_SER 1 +#define FLASH_F7_CR_SNB 3 +#define FLASH_F7_CR_SNB_MASK 0xf8 +#define FLASH_F7_SR_BSY 16 +#define FLASH_F7_SR_ERS_ERR 7 /* Erase Sequence Error */ +#define FLASH_F7_SR_PGP_ERR 6 /* Programming parallelism error */ +#define FLASH_F7_SR_PGA_ERR 5 /* Programming alignment error */ +#define FLASH_F7_SR_WRP_ERR 4 /* Write protection error */ +#define FLASH_F7_SR_OP_ERR 1 /* Operation error */ +#define FLASH_F7_SR_EOP 0 /* End of operation */ +#define FLASH_F7_OPTCR1_BOOT_ADD0 0 +#define FLASH_F7_OPTCR1_BOOT_ADD1 16 + +#define FLASH_F7_SR_ERROR_MASK \ + ((1 << FLASH_F7_SR_ERS_ERR) | (1 << FLASH_F7_SR_PGP_ERR) | \ + (1 << FLASH_F7_SR_PGA_ERR) | (1 << FLASH_F7_SR_WRP_ERR) | \ + (1 << FLASH_F7_SR_OP_ERR)) + +// STM32F4 +#define FLASH_F4_REGS_ADDR ((uint32_t)0x40023c00) +#define FLASH_F4_KEYR (FLASH_F4_REGS_ADDR + 0x04) +#define FLASH_F4_OPT_KEYR (FLASH_F4_REGS_ADDR + 0x08) +#define FLASH_F4_SR (FLASH_F4_REGS_ADDR + 0x0c) +#define FLASH_F4_CR (FLASH_F4_REGS_ADDR + 0x10) +#define FLASH_F4_OPTCR (FLASH_F4_REGS_ADDR + 0x14) +#define FLASH_F4_OPTCR_LOCK 0 +#define FLASH_F4_OPTCR_START 1 +#define FLASH_F4_CR_STRT 16 +#define FLASH_F4_CR_LOCK 31 +#define FLASH_F4_CR_SER 1 +#define FLASH_F4_CR_SNB 3 +#define FLASH_F4_CR_SNB_MASK 0xf8 +#define FLASH_F4_SR_ERROR_MASK 0x000000F0 +#define FLASH_F4_SR_PGAERR 5 +#define FLASH_F4_SR_WRPERR 4 +#define FLASH_F4_SR_BSY 16 + +// STM32F2 +#define FLASH_F2_REGS_ADDR ((uint32_t)0x40023c00) +#define FLASH_F2_KEYR (FLASH_F2_REGS_ADDR + 0x04) +#define FLASH_F2_OPT_KEYR (FLASH_F2_REGS_ADDR + 0x08) +#define FLASH_F2_SR (FLASH_F2_REGS_ADDR + 0x0c) +#define FLASH_F2_CR (FLASH_F2_REGS_ADDR + 0x10) +#define FLASH_F2_OPT_CR (FLASH_F2_REGS_ADDR + 0x14) +#define FLASH_F2_OPT_LOCK_BIT (1u << 0) +#define FLASH_F2_CR_STRT 16 +#define FLASH_F2_CR_LOCK 31 + +#define FLASH_F2_CR_SER 1 +#define FLASH_F2_CR_SNB 3 +#define FLASH_F2_CR_SNB_MASK 0x78 +#define FLASH_F2_SR_BSY 16 + +// STM32H7xx +#define FLASH_H7_CR_LOCK 0 +#define FLASH_H7_CR_PG 1 +#define FLASH_H7_CR_SER 2 +#define FLASH_H7_CR_BER 3 +#define FLASH_H7_CR_PSIZE 4 +#define FLASH_H7_CR_START(chipid) (chipid == STLINK_CHIPID_STM32_H7Ax ? 5 : 7) +#define FLASH_H7_CR_SNB 8 +#define FLASH_H7_CR_SNB_MASK 0x700 + +#define FLASH_H7_SR_QW 2 +#define FLASH_H7_SR_WRPERR 17 +#define FLASH_H7_SR_PGSERR 18 +#define FLASH_H7_SR_STRBERR 19 +#define FLASH_H7_SR_ERROR_MASK \ + ((1 << FLASH_H7_SR_PGSERR) | (1 << FLASH_H7_SR_STRBERR) | \ + (1 << FLASH_H7_SR_WRPERR)) + +#define FLASH_H7_OPTCR_OPTLOCK 0 +#define FLASH_H7_OPTCR_OPTSTART 1 +#define FLASH_H7_OPTCR_MER 4 + +#define FLASH_H7_OPTSR_OPT_BUSY 0 +#define FLASH_H7_OPTSR_OPTCHANGEERR 30 + +#define FLASH_H7_OPTCCR_CLR_OPTCHANGEERR 30 + +#define FLASH_H7_REGS_ADDR ((uint32_t)0x52002000) +#define FLASH_H7_KEYR1 (FLASH_H7_REGS_ADDR + 0x04) +#define FLASH_H7_KEYR2 (FLASH_H7_REGS_ADDR + 0x104) +#define FLASH_H7_OPT_KEYR (FLASH_H7_REGS_ADDR + 0x08) +#define FLASH_H7_OPT_KEYR2 (FLASH_H7_REGS_ADDR + 0x108) +#define FLASH_H7_CR1 (FLASH_H7_REGS_ADDR + 0x0c) +#define FLASH_H7_CR2 (FLASH_H7_REGS_ADDR + 0x10c) +#define FLASH_H7_SR1 (FLASH_H7_REGS_ADDR + 0x10) +#define FLASH_H7_SR2 (FLASH_H7_REGS_ADDR + 0x110) +#define FLASH_H7_CCR1 (FLASH_H7_REGS_ADDR + 0x14) +#define FLASH_H7_CCR2 (FLASH_H7_REGS_ADDR + 0x114) +#define FLASH_H7_OPTCR (FLASH_H7_REGS_ADDR + 0x18) +#define FLASH_H7_OPTCR2 (FLASH_H7_REGS_ADDR + 0x118) +#define FLASH_H7_OPTSR_CUR (FLASH_H7_REGS_ADDR + 0x1c) +#define FLASH_H7_OPTCCR (FLASH_H7_REGS_ADDR + 0x24) + +#endif // STM32FLASH_H \ No newline at end of file diff --git a/src/calculate.c b/src/calculate.c new file mode 100644 index 000000000..22f6e3a5b --- /dev/null +++ b/src/calculate.c @@ -0,0 +1,74 @@ +#include +#include "calculate.h" +#include "common_flash.h" + +uint32_t calculate_F4_sectornum(uint32_t flashaddr) { + uint32_t offset = 0; + flashaddr &= ~STM32_FLASH_BASE; // page now holding the actual flash address + + if (flashaddr >= 0x100000) { + offset = 12; + flashaddr -= 0x100000; + } + + if (flashaddr < 0x4000) { + return (offset + 0); + } else if (flashaddr < 0x8000) { + return (offset + 1); + } else if (flashaddr < 0xc000) { + return (offset + 2); + } else if (flashaddr < 0x10000) { + return (offset + 3); + } else if (flashaddr < 0x20000) { + return (offset + 4); + } else { + return (offset + (flashaddr / 0x20000) + 4); + } +} + +uint32_t calculate_F7_sectornum(uint32_t flashaddr) { + flashaddr &= ~STM32_FLASH_BASE; // Page now holding the actual flash address + + if (flashaddr < 0x20000) { + return (flashaddr / 0x8000); + } else if (flashaddr < 0x40000) { + return (4); + } else { + return ((flashaddr / 0x40000) + 4); + } +} + +uint32_t calculate_H7_sectornum(stlink_t *sl, uint32_t flashaddr, + unsigned bank) { + flashaddr &= + ~((bank == BANK_1) + ? STM32_FLASH_BASE + : STM32_H7_FLASH_BANK2_BASE); // sector holding the flash address + return (flashaddr / sl->flash_pgsz); +} + +// returns BKER:PNB for the given page address +uint32_t calculate_L4_page(stlink_t *sl, uint32_t flashaddr) { + uint32_t bker = 0; + uint32_t flashopt; + stlink_read_debug32(sl, STM32L4_FLASH_OPTR, &flashopt); + flashaddr -= STM32_FLASH_BASE; + + if (sl->chip_id == STLINK_CHIPID_STM32_L4 || + sl->chip_id == STLINK_CHIPID_STM32_L496x_L4A6x || + sl->chip_id == STLINK_CHIPID_STM32_L4Rx) { + // this chip use dual banked flash + if (flashopt & (uint32_t)(1lu << STM32L4_FLASH_OPTR_DUALBANK)) { + uint32_t banksize = (uint32_t)sl->flash_size / 2; + + if (flashaddr >= banksize) { + flashaddr -= banksize; + bker = 0x100; + } + } + } + + // For 1MB chips without the dual-bank option set, the page address will + // overflow into the BKER bit, which gives us the correct bank:page value. + return (bker | flashaddr / (uint32_t)sl->flash_pgsz); +} diff --git a/src/calculate.h b/src/calculate.h new file mode 100644 index 000000000..68c1fb988 --- /dev/null +++ b/src/calculate.h @@ -0,0 +1,15 @@ +/* + * File: calculate.h + * + * TODO: add a description + */ + +#ifndef CALCULATE_H +#define CALCULATE_H + +uint32_t calculate_F4_sectornum(uint32_t); +uint32_t calculate_F7_sectornum(uint32_t); +uint32_t calculate_H7_sectornum(stlink_t *, uint32_t, unsigned); +uint32_t calculate_L4_page(stlink_t *, uint32_t); + +#endif // CALCULATE_H diff --git a/src/common.h b/src/common.h new file mode 100644 index 000000000..6c22d58c0 --- /dev/null +++ b/src/common.h @@ -0,0 +1,15 @@ +/* + * File: common.h + * + * TODO: add a description + */ + +#ifndef COMMON_H +#define COMMON_H + +int check_file(stlink_t *, mapped_file_t *, stm32_addr_t); +void md5_calculate(mapped_file_t *); +void stlink_checksum(mapped_file_t *); +void stlink_fwrite_finalize(stlink_t *, stm32_addr_t); + +#endif // COMMON_H diff --git a/src/common_flash.c b/src/common_flash.c new file mode 100644 index 000000000..4f7f46257 --- /dev/null +++ b/src/common_flash.c @@ -0,0 +1,1374 @@ +#include +#include +#include +#include "calculate.h" +#include "common_flash.h" +#include "map_file.h" +#include "common.h" + +#define DEBUG_FLASH 0 + +uint32_t get_stm32l0_flash_base(stlink_t *sl) { + switch (sl->chip_id) { + case STLINK_CHIPID_STM32_L0: + case STLINK_CHIPID_STM32_L0_CAT5: + case STLINK_CHIPID_STM32_L0_CAT2: + case STLINK_CHIPID_STM32_L011: + return (STM32L0_FLASH_REGS_ADDR); + + case STLINK_CHIPID_STM32_L1_CAT2: + case STLINK_CHIPID_STM32_L1_MD: + case STLINK_CHIPID_STM32_L1_MD_PLUS: + case STLINK_CHIPID_STM32_L1_MD_PLUS_HD: + return (STM32L_FLASH_REGS_ADDR); + + default: + WLOG("Flash base use default L0 address\n"); + return (STM32L0_FLASH_REGS_ADDR); + } +} + +uint32_t read_flash_cr(stlink_t *sl, unsigned bank) { + uint32_t reg, res; + + if (sl->flash_type == STLINK_FLASH_TYPE_F4) { + reg = FLASH_F4_CR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { + reg = FLASH_F7_CR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { + reg = STM32L4_FLASH_CR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || + sl->flash_type == STLINK_FLASH_TYPE_G4) { + reg = STM32Gx_FLASH_CR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + reg = STM32WB_FLASH_CR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; + } else { + reg = (bank == BANK_1) ? FLASH_CR : FLASH_CR2; + } + + stlink_read_debug32(sl, reg, &res); + +#if DEBUG_FLASH + fprintf(stdout, "CR:0x%x\n", res); +#endif + return (res); +} + +void lock_flash(stlink_t *sl) { + uint32_t cr_lock_shift, cr_reg, n, cr2_reg = 0; + uint32_t cr_mask = 0xffffffffu; + + if (sl->flash_type == STLINK_FLASH_TYPE_F0) { + cr_reg = FLASH_CR; + cr_lock_shift = FLASH_CR_LOCK; + } else if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL) { + cr_reg = FLASH_CR; + cr2_reg = FLASH_CR2; + cr_lock_shift = FLASH_CR_LOCK; + } else if (sl->flash_type == STLINK_FLASH_TYPE_F4) { + cr_reg = FLASH_F4_CR; + cr_lock_shift = FLASH_F4_CR_LOCK; + } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { + cr_reg = FLASH_F7_CR; + cr_lock_shift = FLASH_F7_CR_LOCK; + } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { + cr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF; + cr_lock_shift = STM32L0_FLASH_PELOCK; + } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { + cr_reg = STM32L4_FLASH_CR; + cr_lock_shift = STM32L4_FLASH_CR_LOCK; + } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || + sl->flash_type == STLINK_FLASH_TYPE_G4) { + cr_reg = STM32Gx_FLASH_CR; + cr_lock_shift = STM32Gx_FLASH_CR_LOCK; + } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + cr_reg = STM32WB_FLASH_CR; + cr_lock_shift = STM32WB_FLASH_CR_LOCK; + } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + cr_reg = FLASH_H7_CR1; + if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { + cr2_reg = FLASH_H7_CR2; + } + cr_lock_shift = FLASH_H7_CR_LOCK; + cr_mask = ~(1u << FLASH_H7_CR_SER); + } else { + ELOG("unsupported flash method, abort\n"); + return; + } + + stlink_read_debug32(sl, cr_reg, &n); + n &= cr_mask; + n |= (1u << cr_lock_shift); + stlink_write_debug32(sl, cr_reg, n); + + if (cr2_reg) { + n = read_flash_cr(sl, BANK_2) | (1u << cr_lock_shift); + stlink_write_debug32(sl, cr2_reg, n); + } +} + +static inline int write_flash_sr(stlink_t *sl, unsigned bank, uint32_t val) { + uint32_t sr_reg; + + if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || + (sl->flash_type == STLINK_FLASH_TYPE_F1_XL)) { + sr_reg = (bank == BANK_1) ? FLASH_SR : FLASH_SR2; + } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { + sr_reg = get_stm32l0_flash_base(sl) + FLASH_SR_OFF; + } else if (sl->flash_type == STLINK_FLASH_TYPE_F4) { + sr_reg = FLASH_F4_SR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { + sr_reg = FLASH_F7_SR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { + sr_reg = STM32L4_FLASH_SR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || + sl->flash_type == STLINK_FLASH_TYPE_G4) { + sr_reg = STM32Gx_FLASH_SR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + sr_reg = STM32WB_FLASH_SR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + sr_reg = (bank == BANK_1) ? FLASH_H7_SR1 : FLASH_H7_SR2; + } else { + ELOG("method 'write_flash_sr' is unsupported\n"); + return (-1); + } + + return stlink_write_debug32(sl, sr_reg, val); +} + +void clear_flash_error(stlink_t *sl) { + switch (sl->flash_type) { + case STLINK_FLASH_TYPE_F0: + write_flash_sr(sl, BANK_1, FLASH_SR_ERROR_MASK); + break; + case STLINK_FLASH_TYPE_F4: + write_flash_sr(sl, BANK_1, FLASH_F4_SR_ERROR_MASK); + break; + case STLINK_FLASH_TYPE_F7: + write_flash_sr(sl, BANK_1, FLASH_F7_SR_ERROR_MASK); + break; + case STLINK_FLASH_TYPE_G0: + case STLINK_FLASH_TYPE_G4: + write_flash_sr(sl, BANK_1, STM32Gx_FLASH_SR_ERROR_MASK); + break; + case STLINK_FLASH_TYPE_L0: + write_flash_sr(sl, BANK_1, STM32L0_FLASH_SR_ERROR_MASK); + break; + case STLINK_FLASH_TYPE_L4: + write_flash_sr(sl, BANK_1, STM32L4_FLASH_SR_ERROR_MASK); + break; + case STLINK_FLASH_TYPE_H7: + write_flash_sr(sl, BANK_1, FLASH_H7_SR_ERROR_MASK); + if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { + write_flash_sr(sl, BANK_2, FLASH_H7_SR_ERROR_MASK); + } + break; + case STLINK_FLASH_TYPE_WB: + write_flash_sr(sl, BANK_1, STM32WB_FLASH_SR_ERROR_MASK); + break; + default: + break; + } +} + +uint32_t read_flash_sr(stlink_t *sl, unsigned bank) { + uint32_t res, sr_reg; + + if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || + (sl->flash_type == STLINK_FLASH_TYPE_F1_XL)) { + sr_reg = (bank == BANK_1) ? FLASH_SR : FLASH_SR2; + } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { + sr_reg = get_stm32l0_flash_base(sl) + FLASH_SR_OFF; + } else if (sl->flash_type == STLINK_FLASH_TYPE_F4) { + sr_reg = FLASH_F4_SR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { + sr_reg = FLASH_F7_SR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { + sr_reg = STM32L4_FLASH_SR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || + sl->flash_type == STLINK_FLASH_TYPE_G4) { + sr_reg = STM32Gx_FLASH_SR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + sr_reg = STM32WB_FLASH_SR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + sr_reg = (bank == BANK_1) ? FLASH_H7_SR1 : FLASH_H7_SR2; + } else { + ELOG("method 'read_flash_sr' is unsupported\n"); + return (-1); + } + + stlink_read_debug32(sl, sr_reg, &res); + return (res); +} + +unsigned int is_flash_busy(stlink_t *sl) { + uint32_t sr_busy_shift; + unsigned int res; + + if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || + (sl->flash_type == STLINK_FLASH_TYPE_F1_XL) || + (sl->flash_type == STLINK_FLASH_TYPE_L0)) { + sr_busy_shift = FLASH_SR_BSY; + } else if (sl->flash_type == STLINK_FLASH_TYPE_F4) { + sr_busy_shift = FLASH_F4_SR_BSY; + } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { + sr_busy_shift = FLASH_F7_SR_BSY; + } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { + sr_busy_shift = STM32L4_FLASH_SR_BSY; + } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || + sl->flash_type == STLINK_FLASH_TYPE_G4) { + sr_busy_shift = STM32Gx_FLASH_SR_BSY; + } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + sr_busy_shift = STM32WB_FLASH_SR_BSY; + } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + sr_busy_shift = FLASH_H7_SR_QW; + } else { + ELOG("method 'is_flash_busy' is unsupported\n"); + return (-1); + } + + res = read_flash_sr(sl, BANK_1) & (1 << sr_busy_shift); + + if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL || + (sl->flash_type == STLINK_FLASH_TYPE_H7 && + sl->chip_flags & CHIP_F_HAS_DUAL_BANK)) { + res |= read_flash_sr(sl, BANK_2) & (1 << sr_busy_shift); + } + + return (res); +} + +void wait_flash_busy(stlink_t *sl) { + // TODO: add some delays here + while (is_flash_busy(sl)) + ; +} + +int check_flash_error(stlink_t *sl) { + uint32_t res = 0; + uint32_t WRPERR, PROGERR, PGAERR; + + WRPERR = PROGERR = PGAERR = 0; + + switch (sl->flash_type) { + case STLINK_FLASH_TYPE_F0: + case STLINK_FLASH_TYPE_F1_XL: + res = read_flash_sr(sl, BANK_1) & FLASH_SR_ERROR_MASK; + if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL) { + res |= read_flash_sr(sl, BANK_2) & FLASH_SR_ERROR_MASK; + } + WRPERR = (1 << FLASH_SR_WRPRT_ERR); + PROGERR = (1 << FLASH_SR_PG_ERR); + break; + case STLINK_FLASH_TYPE_F4: + res = read_flash_sr(sl, BANK_1) & FLASH_F4_SR_ERROR_MASK; + WRPERR = (1 << FLASH_F4_SR_WRPERR); + PGAERR = (1 << FLASH_F4_SR_PGAERR); + break; + case STLINK_FLASH_TYPE_F7: + res = read_flash_sr(sl, BANK_1) & FLASH_F7_SR_ERROR_MASK; + WRPERR = (1 << FLASH_F7_SR_WRP_ERR); + PROGERR = (1 << FLASH_F7_SR_PGP_ERR); + break; + case STLINK_FLASH_TYPE_G0: + case STLINK_FLASH_TYPE_G4: + res = read_flash_sr(sl, BANK_1) & STM32Gx_FLASH_SR_ERROR_MASK; + WRPERR = (1 << STM32Gx_FLASH_SR_WRPERR); + PROGERR = (1 << STM32Gx_FLASH_SR_PROGERR); + PGAERR = (1 << STM32Gx_FLASH_SR_PGAERR); + break; + case STLINK_FLASH_TYPE_L0: + res = read_flash_sr(sl, BANK_1) & STM32L0_FLASH_SR_ERROR_MASK; + WRPERR = (1 << STM32L0_FLASH_SR_WRPERR); + PROGERR = (1 << STM32L0_FLASH_SR_NOTZEROERR); + PGAERR = (1 << STM32L0_FLASH_SR_PGAERR); + break; + case STLINK_FLASH_TYPE_L4: + res = read_flash_sr(sl, BANK_1) & STM32L4_FLASH_SR_ERROR_MASK; + WRPERR = (1 << STM32L4_FLASH_SR_WRPERR); + PROGERR = (1 << STM32L4_FLASH_SR_PROGERR); + PGAERR = (1 << STM32L4_FLASH_SR_PGAERR); + break; + case STLINK_FLASH_TYPE_H7: + res = read_flash_sr(sl, BANK_1) & FLASH_H7_SR_ERROR_MASK; + if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { + res |= read_flash_sr(sl, BANK_2) & FLASH_H7_SR_ERROR_MASK; + } + WRPERR = (1 << FLASH_H7_SR_WRPERR); + break; + case STLINK_FLASH_TYPE_WB: + res = read_flash_sr(sl, BANK_1) & STM32WB_FLASH_SR_ERROR_MASK; + WRPERR = (1 << STM32WB_FLASH_SR_WRPERR); + PROGERR = (1 << STM32WB_FLASH_SR_PROGERR); + PGAERR = (1 << STM32WB_FLASH_SR_PGAERR); + break; + default: + break; + } + + if (res) { + if (WRPERR && (WRPERR & res) == WRPERR) { + ELOG("Flash memory is write protected\n"); + res &= ~WRPERR; + } else if (PROGERR && (PROGERR & res) == PROGERR) { + ELOG("Flash memory contains a non-erased value\n"); + res &= ~PROGERR; + } else if (PGAERR && (PGAERR & res) == PGAERR) { + ELOG("Invalid flash address\n"); + res &= ~PGAERR; + } + + if (res) { + ELOG("Flash programming error: %#010x\n", res); + } + return (-1); + } + + return (0); +} + +static inline unsigned int is_flash_locked(stlink_t *sl) { + /* return non zero for true */ + uint32_t cr_lock_shift; + uint32_t cr_reg; + uint32_t n; + + if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || + (sl->flash_type == STLINK_FLASH_TYPE_F1_XL)) { + cr_reg = FLASH_CR; + cr_lock_shift = FLASH_CR_LOCK; + } else if (sl->flash_type == STLINK_FLASH_TYPE_F4) { + cr_reg = FLASH_F4_CR; + cr_lock_shift = FLASH_F4_CR_LOCK; + } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { + cr_reg = FLASH_F7_CR; + cr_lock_shift = FLASH_F7_CR_LOCK; + } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { + cr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF; + cr_lock_shift = STM32L0_FLASH_PELOCK; + } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { + cr_reg = STM32L4_FLASH_CR; + cr_lock_shift = STM32L4_FLASH_CR_LOCK; + } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || + sl->flash_type == STLINK_FLASH_TYPE_G4) { + cr_reg = STM32Gx_FLASH_CR; + cr_lock_shift = STM32Gx_FLASH_CR_LOCK; + } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + cr_reg = STM32WB_FLASH_CR; + cr_lock_shift = STM32WB_FLASH_CR_LOCK; + } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + cr_reg = FLASH_H7_CR1; + cr_lock_shift = FLASH_H7_CR_LOCK; + } else { + ELOG("unsupported flash method, abort\n"); + return (-1); + } + + stlink_read_debug32(sl, cr_reg, &n); + return (n & (1u << cr_lock_shift)); +} + +static void unlock_flash(stlink_t *sl) { + uint32_t key_reg, key2_reg = 0; + uint32_t flash_key1 = FLASH_KEY1; + uint32_t flash_key2 = FLASH_KEY2; + /* The unlock sequence consists of 2 write cycles where 2 key values are + * written to the FLASH_KEYR register. An invalid sequence results in a + * definitive lock of the FPEC block until next reset. + */ + + if (sl->flash_type == STLINK_FLASH_TYPE_F0) { + key_reg = FLASH_KEYR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL) { + key_reg = FLASH_KEYR; + key2_reg = FLASH_KEYR2; + } else if (sl->flash_type == STLINK_FLASH_TYPE_F4) { + key_reg = FLASH_F4_KEYR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { + key_reg = FLASH_F7_KEYR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { + key_reg = get_stm32l0_flash_base(sl) + FLASH_PEKEYR_OFF; + flash_key1 = FLASH_L0_PEKEY1; + flash_key2 = FLASH_L0_PEKEY2; + } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { + key_reg = STM32L4_FLASH_KEYR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || + sl->flash_type == STLINK_FLASH_TYPE_G4) { + key_reg = STM32Gx_FLASH_KEYR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + key_reg = STM32WB_FLASH_KEYR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + key_reg = FLASH_H7_KEYR1; + if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { + key2_reg = FLASH_H7_KEYR2; + } + } else { + ELOG("unsupported flash method, abort\n"); + return; + } + + stlink_write_debug32(sl, key_reg, flash_key1); + stlink_write_debug32(sl, key_reg, flash_key2); + + if (key2_reg) { + stlink_write_debug32(sl, key2_reg, flash_key1); + stlink_write_debug32(sl, key2_reg, flash_key2); + } +} + +/* unlock flash if already locked */ +int unlock_flash_if(stlink_t *sl) { + if (is_flash_locked(sl)) { + unlock_flash(sl); + + if (is_flash_locked(sl)) { + WLOG("Failed to unlock flash!\n"); + return (-1); + } + } + + DLOG("Successfully unlocked flash\n"); + return (0); +} + +int lock_flash_option(stlink_t *sl) { + uint32_t optlock_shift, optcr_reg, n, optcr2_reg = 0; + int active_bit_level = 1; + + switch (sl->flash_type) { + case STLINK_FLASH_TYPE_F0: + case STLINK_FLASH_TYPE_F1_XL: + optcr_reg = FLASH_CR; + optlock_shift = FLASH_CR_OPTWRE; + active_bit_level = 0; + break; + case STLINK_FLASH_TYPE_F4: + optcr_reg = FLASH_F4_OPTCR; + optlock_shift = FLASH_F4_OPTCR_LOCK; + break; + case STLINK_FLASH_TYPE_F7: + optcr_reg = FLASH_F7_OPTCR; + optlock_shift = FLASH_F7_OPTCR_LOCK; + break; + case STLINK_FLASH_TYPE_L0: + optcr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF; + optlock_shift = STM32L0_FLASH_OPTLOCK; + break; + case STLINK_FLASH_TYPE_L4: + optcr_reg = STM32L4_FLASH_CR; + optlock_shift = STM32L4_FLASH_CR_OPTLOCK; + break; + case STLINK_FLASH_TYPE_G0: + case STLINK_FLASH_TYPE_G4: + optcr_reg = STM32Gx_FLASH_CR; + optlock_shift = STM32Gx_FLASH_CR_OPTLOCK; + break; + case STLINK_FLASH_TYPE_WB: + optcr_reg = STM32WB_FLASH_CR; + optlock_shift = STM32WB_FLASH_CR_OPTLOCK; + break; + case STLINK_FLASH_TYPE_H7: + optcr_reg = FLASH_H7_OPTCR; + optlock_shift = FLASH_H7_OPTCR_OPTLOCK; + if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) + optcr2_reg = FLASH_H7_OPTCR2; + break; + default: + ELOG("unsupported flash method, abort\n"); + return -1; + } + + stlink_read_debug32(sl, optcr_reg, &n); + + if (active_bit_level == 0) { + n &= ~(1u << optlock_shift); + } else { + n |= (1u << optlock_shift); + } + + stlink_write_debug32(sl, optcr_reg, n); + + if (optcr2_reg) { + stlink_read_debug32(sl, optcr2_reg, &n); + + if (active_bit_level == 0) { + n &= ~(1u << optlock_shift); + } else { + n |= (1u << optlock_shift); + } + + stlink_write_debug32(sl, optcr2_reg, n); + } + + return (0); +} + +static bool is_flash_option_locked(stlink_t *sl) { + uint32_t optlock_shift, optcr_reg; + int active_bit_level = 1; + uint32_t n; + + switch (sl->flash_type) { + case STLINK_FLASH_TYPE_F0: + case STLINK_FLASH_TYPE_F1_XL: + optcr_reg = FLASH_CR; + optlock_shift = FLASH_CR_OPTWRE; + active_bit_level = 0; /* bit is "option write enable", not lock */ + break; + case STLINK_FLASH_TYPE_F4: + optcr_reg = FLASH_F4_OPTCR; + optlock_shift = FLASH_F4_OPTCR_LOCK; + break; + case STLINK_FLASH_TYPE_F7: + optcr_reg = FLASH_F7_OPTCR; + optlock_shift = FLASH_F7_OPTCR_LOCK; + break; + case STLINK_FLASH_TYPE_L0: + optcr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF; + optlock_shift = STM32L0_FLASH_OPTLOCK; + break; + case STLINK_FLASH_TYPE_L4: + optcr_reg = STM32L4_FLASH_CR; + optlock_shift = STM32L4_FLASH_CR_OPTLOCK; + break; + case STLINK_FLASH_TYPE_G0: + case STLINK_FLASH_TYPE_G4: + optcr_reg = STM32Gx_FLASH_CR; + optlock_shift = STM32Gx_FLASH_CR_OPTLOCK; + break; + case STLINK_FLASH_TYPE_WB: + optcr_reg = STM32WB_FLASH_CR; + optlock_shift = STM32WB_FLASH_CR_OPTLOCK; + break; + case STLINK_FLASH_TYPE_H7: + optcr_reg = FLASH_H7_OPTCR; + optlock_shift = FLASH_H7_OPTCR_OPTLOCK; + break; + default: + ELOG("unsupported flash method, abort\n"); + return -1; + } + + stlink_read_debug32(sl, optcr_reg, &n); + + if (active_bit_level == 0) { + return (!(n & (1u << optlock_shift))); + } + + return (n & (1u << optlock_shift)); +} + +static int unlock_flash_option(stlink_t *sl) { + uint32_t optkey_reg, optkey2_reg = 0; + uint32_t optkey1 = FLASH_OPTKEY1; + uint32_t optkey2 = FLASH_OPTKEY2; + + switch (sl->flash_type) { + case STLINK_FLASH_TYPE_F0: + case STLINK_FLASH_TYPE_F1_XL: + optkey_reg = FLASH_OPTKEYR; + optkey1 = FLASH_F0_OPTKEY1; + optkey2 = FLASH_F0_OPTKEY2; + break; + case STLINK_FLASH_TYPE_F4: + optkey_reg = FLASH_F4_OPT_KEYR; + break; + case STLINK_FLASH_TYPE_F7: + optkey_reg = FLASH_F7_OPT_KEYR; + break; + case STLINK_FLASH_TYPE_L0: + optkey_reg = get_stm32l0_flash_base(sl) + FLASH_OPTKEYR_OFF; + optkey1 = FLASH_L0_OPTKEY1; + optkey2 = FLASH_L0_OPTKEY2; + break; + case STLINK_FLASH_TYPE_L4: + optkey_reg = STM32L4_FLASH_OPTKEYR; + break; + case STLINK_FLASH_TYPE_G0: + case STLINK_FLASH_TYPE_G4: + optkey_reg = STM32Gx_FLASH_OPTKEYR; + break; + case STLINK_FLASH_TYPE_WB: + optkey_reg = STM32WB_FLASH_OPT_KEYR; + break; + case STLINK_FLASH_TYPE_H7: + optkey_reg = FLASH_H7_OPT_KEYR; + if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) + optkey2_reg = FLASH_H7_OPT_KEYR2; + break; + default: + ELOG("unsupported flash method, abort\n"); + return (-1); + } + + stlink_write_debug32(sl, optkey_reg, optkey1); + stlink_write_debug32(sl, optkey_reg, optkey2); + + if (optkey2_reg) { + stlink_write_debug32(sl, optkey2_reg, optkey1); + stlink_write_debug32(sl, optkey2_reg, optkey2); + } + + return (0); +} + +int unlock_flash_option_if(stlink_t *sl) { + if (is_flash_option_locked(sl)) { + if (unlock_flash_option(sl)) { + ELOG("Could not unlock flash option!\n"); + return (-1); + } + + if (is_flash_option_locked(sl)) { + ELOG("Failed to unlock flash option!\n"); + return (-1); + } + } + + DLOG("Successfully unlocked flash option\n"); + return (0); +} + +void write_flash_cr_psiz(stlink_t *sl, uint32_t n, + unsigned bank) { + uint32_t cr_reg, psize_shift; + uint32_t x = read_flash_cr(sl, bank); + + if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + cr_reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; + psize_shift = FLASH_H7_CR_PSIZE; + } else { + cr_reg = FLASH_F4_CR; + psize_shift = 8; + } + + x &= ~(0x03 << psize_shift); + x |= (n << psize_shift); +#if DEBUG_FLASH + fprintf(stdout, "PSIZ:0x%x 0x%x\n", x, n); +#endif + stlink_write_debug32(sl, cr_reg, x); +} + +void clear_flash_cr_pg(stlink_t *sl, unsigned bank) { + uint32_t cr_reg, n; + uint32_t bit = FLASH_CR_PG; + + if (sl->flash_type == STLINK_FLASH_TYPE_F4) { + cr_reg = FLASH_F4_CR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { + cr_reg = FLASH_F7_CR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { + cr_reg = STM32L4_FLASH_CR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || + sl->flash_type == STLINK_FLASH_TYPE_G4) { + cr_reg = STM32Gx_FLASH_CR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + cr_reg = STM32WB_FLASH_CR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + cr_reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; + bit = FLASH_H7_CR_PG; + } else { + cr_reg = FLASH_CR; + } + + n = read_flash_cr(sl, bank) & ~(1 << bit); + stlink_write_debug32(sl, cr_reg, n); +} +/* ------------------------------------------------------------------------ */ + +static void wait_flash_busy_progress(stlink_t *sl) { + int i = 0; + fprintf(stdout, "Mass erasing"); + fflush(stdout); + + while (is_flash_busy(sl)) { + usleep(10000); + i++; + + if (i % 100 == 0) { + fprintf(stdout, "."); + fflush(stdout); + } + } + + fprintf(stdout, "\n"); +} + +static inline void write_flash_ar(stlink_t *sl, uint32_t n, unsigned bank) { + stlink_write_debug32(sl, (bank == BANK_1) ? FLASH_AR : FLASH_AR2, n); +} + +static inline void write_flash_cr_snb(stlink_t *sl, uint32_t n, unsigned bank) { + uint32_t cr_reg, snb_mask, snb_shift, ser_shift; + uint32_t x = read_flash_cr(sl, bank); + + if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + cr_reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; + snb_mask = FLASH_H7_CR_SNB_MASK; + snb_shift = FLASH_H7_CR_SNB; + ser_shift = FLASH_H7_CR_SER; + } else { + cr_reg = FLASH_F4_CR; + snb_mask = FLASH_F4_CR_SNB_MASK; + snb_shift = FLASH_F4_CR_SNB; + ser_shift = FLASH_F4_CR_SER; + } + + x &= ~snb_mask; + x |= (n << snb_shift); + x |= (1 << ser_shift); +#if DEBUG_FLASH + fprintf(stdout, "SNB:0x%x 0x%x\n", x, n); +#endif + stlink_write_debug32(sl, cr_reg, x); +} + +static void set_flash_cr_per(stlink_t *sl, unsigned bank) { + uint32_t cr_reg, val; + + if (sl->flash_type == STLINK_FLASH_TYPE_G0 || + sl->flash_type == STLINK_FLASH_TYPE_G4) { + cr_reg = STM32Gx_FLASH_CR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + cr_reg = STM32WB_FLASH_CR; + } else { + cr_reg = (bank == BANK_1) ? FLASH_CR : FLASH_CR2; + } + + stlink_read_debug32(sl, cr_reg, &val); + val |= (1 << FLASH_CR_PER); + stlink_write_debug32(sl, cr_reg, val); +} + +static void clear_flash_cr_per(stlink_t *sl, unsigned bank) { + uint32_t cr_reg; + + if (sl->flash_type == STLINK_FLASH_TYPE_G0 || + sl->flash_type == STLINK_FLASH_TYPE_G4) { + cr_reg = STM32Gx_FLASH_CR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + cr_reg = STM32WB_FLASH_CR; + } else { + cr_reg = (bank == BANK_1) ? FLASH_CR : FLASH_CR2; + } + + const uint32_t n = read_flash_cr(sl, bank) & ~(1 << FLASH_CR_PER); + stlink_write_debug32(sl, cr_reg, n); +} + +static inline void write_flash_cr_bker_pnb(stlink_t *sl, uint32_t n) { + stlink_write_debug32(sl, STM32L4_FLASH_SR, + 0xFFFFFFFF & ~(1 << STM32L4_FLASH_SR_BSY)); + uint32_t x = read_flash_cr(sl, BANK_1); + x &= ~STM32L4_FLASH_CR_OPBITS; + x &= ~STM32L4_FLASH_CR_PAGEMASK; + x &= ~(1 << STM32L4_FLASH_CR_MER1); + x &= ~(1 << STM32L4_FLASH_CR_MER2); + x |= (n << STM32L4_FLASH_CR_PNB); + x |= (uint32_t)(1lu << STM32L4_FLASH_CR_PER); +#if DEBUG_FLASH + fprintf(stdout, "BKER:PNB:0x%x 0x%x\n", x, n); +#endif + stlink_write_debug32(sl, STM32L4_FLASH_CR, x); +} + +static void set_flash_cr_strt(stlink_t *sl, unsigned bank) { + uint32_t val, cr_reg, cr_strt; + + if (sl->flash_type == STLINK_FLASH_TYPE_F4) { + cr_reg = FLASH_F4_CR; + cr_strt = 1 << FLASH_F4_CR_STRT; + } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { + cr_reg = FLASH_F7_CR; + cr_strt = 1 << FLASH_F7_CR_STRT; + } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { + cr_reg = STM32L4_FLASH_CR; + cr_strt = (1 << STM32L4_FLASH_CR_STRT); + } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || + sl->flash_type == STLINK_FLASH_TYPE_G4) { + cr_reg = STM32Gx_FLASH_CR; + cr_strt = (1 << STM32Gx_FLASH_CR_STRT); + } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + cr_reg = STM32WB_FLASH_CR; + cr_strt = (1 << STM32WB_FLASH_CR_STRT); + } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + cr_reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; + cr_strt = 1 << FLASH_H7_CR_START(sl->chip_id); + } else { + cr_reg = (bank == BANK_1) ? FLASH_CR : FLASH_CR2; + cr_strt = (1 << FLASH_CR_STRT); + } + + stlink_read_debug32(sl, cr_reg, &val); + val |= cr_strt; + stlink_write_debug32(sl, cr_reg, val); +} + +static void set_flash_cr_mer(stlink_t *sl, bool v, unsigned bank) { + uint32_t val, cr_reg, cr_mer, cr_pg; + + if (sl->flash_type == STLINK_FLASH_TYPE_F4) { + cr_reg = FLASH_F4_CR; + cr_mer = 1 << FLASH_CR_MER; + cr_pg = 1 << FLASH_CR_PG; + } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { + cr_reg = FLASH_F7_CR; + cr_mer = 1 << FLASH_CR_MER; + cr_pg = 1 << FLASH_CR_PG; + } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { + cr_reg = STM32L4_FLASH_CR; + cr_mer = (1 << STM32L4_FLASH_CR_MER1) | (1 << STM32L4_FLASH_CR_MER2); + cr_pg = (1 << STM32L4_FLASH_CR_PG); + } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || + sl->flash_type == STLINK_FLASH_TYPE_G4) { + cr_reg = STM32Gx_FLASH_CR; + cr_mer = (1 << STM32Gx_FLASH_CR_MER1); + + if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { + cr_mer |= (1 << STM32Gx_FLASH_CR_MER2); + } + + cr_pg = (1 << FLASH_CR_PG); + } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + cr_reg = STM32WB_FLASH_CR; + cr_mer = (1 << FLASH_CR_MER); + cr_pg = (1 << FLASH_CR_PG); + } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + cr_reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; + cr_mer = (1 << FLASH_H7_CR_BER); + cr_pg = (1 << FLASH_H7_CR_PG); + } else { + cr_reg = (bank == BANK_1) ? FLASH_CR : FLASH_CR2; + cr_mer = (1 << FLASH_CR_MER); + cr_pg = (1 << FLASH_CR_PG); + } + + stlink_read_debug32(sl, cr_reg, &val); + + if (val & cr_pg) { + // STM32F030 will drop MER bit if PG was set + val &= ~cr_pg; + stlink_write_debug32(sl, cr_reg, val); + } + + if (v) { + val |= cr_mer; + } else { + val &= ~cr_mer; + } + + stlink_write_debug32(sl, cr_reg, val); +} + +/** + * Erase a page of flash, assumes sl is fully populated with things like + * chip/core ids + * @param sl stlink context + * @param flashaddr an address in the flash page to erase + * @return 0 on success -ve on failure + */ +int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { + // wait for ongoing op to finish + wait_flash_busy(sl); + // clear flash IO errors + clear_flash_error(sl); + + if (sl->flash_type == STLINK_FLASH_TYPE_F4 || + sl->flash_type == STLINK_FLASH_TYPE_F7 || + sl->flash_type == STLINK_FLASH_TYPE_L4) { + // unlock if locked + unlock_flash_if(sl); + + // select the page to erase + if ((sl->chip_id == STLINK_CHIPID_STM32_L4) || + (sl->chip_id == STLINK_CHIPID_STM32_L43x_L44x) || + (sl->chip_id == STLINK_CHIPID_STM32_L45x_L46x) || + (sl->chip_id == STLINK_CHIPID_STM32_L496x_L4A6x) || + (sl->chip_id == STLINK_CHIPID_STM32_L4Rx)) { + // calculate the actual bank+page from the address + uint32_t page = calculate_L4_page(sl, flashaddr); + + fprintf(stderr, "EraseFlash - Page:0x%x Size:0x%x ", page, + stlink_calculate_pagesize(sl, flashaddr)); + + write_flash_cr_bker_pnb(sl, page); + } else if (sl->chip_id == STLINK_CHIPID_STM32_F7 || + sl->chip_id == STLINK_CHIPID_STM32_F76xxx) { + // calculate the actual page from the address + uint32_t sector = calculate_F7_sectornum(flashaddr); + + fprintf(stderr, "EraseFlash - Sector:0x%x Size:0x%x ", sector, + stlink_calculate_pagesize(sl, flashaddr)); + write_flash_cr_snb(sl, sector, BANK_1); + } else { + // calculate the actual page from the address + uint32_t sector = calculate_F4_sectornum(flashaddr); + + fprintf(stderr, "EraseFlash - Sector:0x%x Size:0x%x ", sector, + stlink_calculate_pagesize(sl, flashaddr)); + + // the SNB values for flash sectors in the second bank do not directly + // follow the values for the first bank on 2mb devices... + if (sector >= 12) { + sector += 4; + } + + write_flash_cr_snb(sl, sector, BANK_1); + } + + set_flash_cr_strt(sl, BANK_1); // start erase operation + wait_flash_busy(sl); // wait for completion + lock_flash(sl); // TODO: fails to program if this is in +#if DEBUG_FLASH + fprintf(stdout, "Erase Final CR:0x%x\n", read_flash_cr(sl, BANK_1)); +#endif + } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { + + uint32_t val; + uint32_t flash_regs_base = get_stm32l0_flash_base(sl); + + // check if the locks are set + stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); + + if ((val & (1 << 0)) || (val & (1 << 1))) { + // disable pecr protection + stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, + FLASH_L0_PEKEY1); + stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, + FLASH_L0_PEKEY2); + + // check pecr.pelock is cleared + stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); + + if (val & (1 << 0)) { + WLOG("pecr.pelock not clear (%#x)\n", val); + return (-1); + } + + // unlock program memory + stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, + FLASH_L0_PRGKEY1); + stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, + FLASH_L0_PRGKEY2); + + // check pecr.prglock is cleared + stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); + + if (val & (1 << 1)) { + WLOG("pecr.prglock not clear (%#x)\n", val); + return (-1); + } + } + + // set pecr.{erase,prog} + val |= (1 << 9) | (1 << 3); + stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); + + // write 0 to the first word of the page to be erased + stlink_write_debug32(sl, flashaddr, 0); + + /* MP: It is better to wait for clearing the busy bit after issuing page + * erase command, even though PM0062 recommends to wait before it. + * Test shows that a few iterations is performed in the following loop + * before busy bit is cleared. + */ + wait_flash_busy(sl); + + // reset lock bits + stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); + val |= (1 << 0) | (1 << 1) | (1 << 2); + stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); + } else if (sl->flash_type == STLINK_FLASH_TYPE_WB || + sl->flash_type == STLINK_FLASH_TYPE_G0 || + sl->flash_type == STLINK_FLASH_TYPE_G4) { + uint32_t val; + unlock_flash_if(sl); + set_flash_cr_per(sl, BANK_1); // set the 'enable Flash erase' bit + + // set the page to erase + if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + uint32_t flash_page = + ((flashaddr - STM32_FLASH_BASE) / (uint32_t)(sl->flash_pgsz)); + stlink_read_debug32(sl, STM32WB_FLASH_CR, &val); + + // sec 3.10.5 - PNB[7:0] is offset by 3. + val &= ~(0xFF << 3); // Clear previously set page number (if any) + val |= ((flash_page & 0xFF) << 3); + + stlink_write_debug32(sl, STM32WB_FLASH_CR, val); + } else if (sl->flash_type == STLINK_FLASH_TYPE_G0) { + uint32_t flash_page = + ((flashaddr - STM32_FLASH_BASE) / (uint32_t)(sl->flash_pgsz)); + stlink_read_debug32(sl, STM32Gx_FLASH_CR, &val); + // sec 3.7.5 - PNB[5:0] is offset by 3. PER is 0x2. + val &= ~(0x3F << 3); + val |= ((flash_page & 0x3F) << 3) | (1 << FLASH_CR_PER); + stlink_write_debug32(sl, STM32Gx_FLASH_CR, val); + } else if (sl->flash_type == STLINK_FLASH_TYPE_G4) { + uint32_t flash_page = + ((flashaddr - STM32_FLASH_BASE) / (uint32_t)(sl->flash_pgsz)); + stlink_read_debug32(sl, STM32Gx_FLASH_CR, &val); + // sec 3.7.5 - PNB[6:0] is offset by 3. PER is 0x2. + val &= ~(0x7F << 3); + val |= ((flash_page & 0x7F) << 3) | (1 << FLASH_CR_PER); + stlink_write_debug32(sl, STM32Gx_FLASH_CR, val); + } + + set_flash_cr_strt(sl, BANK_1); // set the 'start operation' bit + wait_flash_busy(sl); // wait for the 'busy' bit to clear + clear_flash_cr_per(sl, BANK_1); // clear the 'enable page erase' bit + lock_flash(sl); + } else if (sl->flash_type == STLINK_FLASH_TYPE_F0 || + sl->flash_type == STLINK_FLASH_TYPE_F1_XL) { + unsigned bank = (flashaddr < STM32_F1_FLASH_BANK2_BASE) ? BANK_1 : BANK_2; + unlock_flash_if(sl); + clear_flash_cr_pg(sl, bank); // clear the pg bit + set_flash_cr_per(sl, bank); // set the page erase bit + write_flash_ar(sl, flashaddr, bank); // select the page to erase + set_flash_cr_strt(sl, + bank); // start erase operation, reset by hw with busy bit + wait_flash_busy(sl); + clear_flash_cr_per(sl, bank); // clear the page erase bit + lock_flash(sl); + } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + unsigned bank = (flashaddr < STM32_H7_FLASH_BANK2_BASE) ? BANK_1 : BANK_2; + unlock_flash_if(sl); // unlock if locked + uint32_t sector = calculate_H7_sectornum( + sl, flashaddr, bank); // calculate the actual page from the address + write_flash_cr_snb(sl, sector, bank); // select the page to erase + set_flash_cr_strt(sl, bank); // start erase operation + wait_flash_busy(sl); // wait for completion + lock_flash(sl); + } else { + WLOG("unknown coreid %x, page erase failed\n", sl->core_id); + return (-1); + } + + return check_flash_error(sl); +} + +int stlink_erase_flash_section(stlink_t *sl, stm32_addr_t base_addr, size_t size, bool align_size) { + // Check the address and size validity + if (stlink_check_address_range_validity(sl, base_addr, size) < 0) { + return -1; + } + + // Make sure the requested address is aligned with the beginning of a page + if (stlink_check_address_alignment(sl, base_addr) < 0) { + ELOG("The address to erase is not aligned with the beginning of a page\n"); + return -1; + } + + stm32_addr_t addr = base_addr; + do { + long unsigned int page_size = stlink_calculate_pagesize(sl, addr); + + // Check if size is aligned with a page, unless we want to completely erase the last page + if ((addr + page_size) > (base_addr + size) && !align_size) { + ELOG("Invalid size (not aligned with a page). Page size at address %#x is %#lx\n", addr, page_size); + return -1; + } + + if (stlink_erase_flash_page(sl, addr)) { + WLOG("Failed to erase_flash_page(%#x) == -1\n", addr); + return (-1); + } + + fprintf(stdout, "-> Flash page at %#x erased (size: %#lx)\n", addr, page_size); + fflush(stdout); + + // check the next page is within the range to erase + addr += page_size; + } while (addr < (base_addr + size)); + + fprintf(stdout, "\n"); + return 0; +} + +int stlink_erase_flash_mass(stlink_t *sl) { + int err = 0; + + // TODO: User MER bit to mass-erase WB series. + if (sl->flash_type == STLINK_FLASH_TYPE_L0 || + sl->flash_type == STLINK_FLASH_TYPE_WB) { + + err = stlink_erase_flash_section(sl, sl->flash_base, sl->flash_size, false); + + } else { + wait_flash_busy(sl); + clear_flash_error(sl); + unlock_flash_if(sl); + + if (sl->flash_type == STLINK_FLASH_TYPE_H7 && + sl->chip_id != STLINK_CHIPID_STM32_H7Ax) { + // set parallelism + write_flash_cr_psiz(sl, 3 /*64it*/, BANK_1); + if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { + write_flash_cr_psiz(sl, 3 /*64bit*/, BANK_2); + } + } + + set_flash_cr_mer(sl, 1, BANK_1); // set the mass erase bit + set_flash_cr_strt( + sl, BANK_1); // start erase operation, reset by hw with busy bit + + if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL || + (sl->flash_type == STLINK_FLASH_TYPE_H7 && + sl->chip_flags & CHIP_F_HAS_DUAL_BANK)) { + set_flash_cr_mer(sl, 1, BANK_2); // set the mass erase bit in bank 2 + set_flash_cr_strt(sl, BANK_2); // start erase operation in bank 2 + } + + wait_flash_busy_progress(sl); + lock_flash(sl); + + // reset the mass erase bit + set_flash_cr_mer(sl, 0, BANK_1); + if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL || + (sl->flash_type == STLINK_FLASH_TYPE_H7 && + sl->chip_flags & CHIP_F_HAS_DUAL_BANK)) { + set_flash_cr_mer(sl, 0, BANK_2); + } + + err = check_flash_error(sl); + } + + return (err); +} + +int stlink_mwrite_flash(stlink_t *sl, uint8_t *data, uint32_t length, + stm32_addr_t addr) { + /* Write the block in flash at addr */ + int err; + unsigned int num_empty, idx; + uint8_t erased_pattern = stlink_get_erased_pattern(sl); + + /* + * This optimisation may cause unexpected garbage data remaining. + * Therfore it is turned off by default. + */ + if (sl->opt) { + idx = (unsigned int)length; + + for (num_empty = 0; num_empty != length; ++num_empty) + if (data[--idx] != erased_pattern) { + break; + } + + num_empty -= (num_empty & 3); // Round down to words + + if (num_empty != 0) { + ILOG("Ignoring %d bytes of 0x%02x at end of file\n", num_empty, + erased_pattern); + } + } else { + num_empty = 0; + } + + /* + * TODO: investigate a kind of weird behaviour here: + * If the file is identified to be all-empty and four-bytes aligned, + * still flash the whole file even if ignoring message is printed. + */ + err = stlink_write_flash(sl, addr, data, + (num_empty == length) ? (uint32_t)length + : (uint32_t)length - num_empty, + num_empty == length); + stlink_fwrite_finalize(sl, addr); + return (err); +} + +/** + * Write the given binary file into flash at address "addr" + * @param sl + * @param path readable file path, should be binary image + * @param addr where to start writing + * @return 0 on success, -ve on failure. + */ +int stlink_fwrite_flash(stlink_t *sl, const char *path, stm32_addr_t addr) { + /* Write the file in flash at addr */ + int err; + unsigned int num_empty, idx; + uint8_t erased_pattern = stlink_get_erased_pattern(sl); + mapped_file_t mf = MAPPED_FILE_INITIALIZER; + + if (map_file(&mf, path) == -1) { + ELOG("map_file() == -1\n"); + return (-1); + } + + printf("file %s ", path); + md5_calculate(&mf); + stlink_checksum(&mf); + + if (sl->opt) { + idx = (unsigned int)mf.len; + + for (num_empty = 0; num_empty != mf.len; ++num_empty) { + if (mf.base[--idx] != erased_pattern) { + break; + } + } + + num_empty -= (num_empty & 3); // round down to words + + if (num_empty != 0) { + ILOG("Ignoring %d bytes of 0x%02x at end of file\n", num_empty, + erased_pattern); + } + } else { + num_empty = 0; + } + + /* + * TODO: investigate a kind of weird behaviour here: + * If the file is identified to be all-empty and four-bytes aligned, + * still flash the whole file even if ignoring message is printed. + */ + err = stlink_write_flash(sl, addr, mf.base, + (num_empty == mf.len) ? (uint32_t)mf.len + : (uint32_t)mf.len - num_empty, + num_empty == mf.len); + stlink_fwrite_finalize(sl, addr); + unmap_file(&mf); + return (err); +} + + +int stlink_fcheck_flash(stlink_t *sl, const char *path, stm32_addr_t addr) { + // check the contents of path are at addr + + int res; + mapped_file_t mf = MAPPED_FILE_INITIALIZER; + + if (map_file(&mf, path) == -1) { + return (-1); + } + + res = check_file(sl, &mf, addr); + unmap_file(&mf); + return (res); +} + +/** + * Verify addr..addr+len is binary identical to base...base+len + * @param sl stlink context + * @param address stm device address + * @param data host side buffer to check against + * @param length how much + * @return 0 for success, -ve for failure + */ +int stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, + unsigned length) { + size_t off; + size_t cmp_size = (sl->flash_pgsz > 0x1800) ? 0x1800 : sl->flash_pgsz; + ILOG("Starting verification of write complete\n"); + + for (off = 0; off < length; off += cmp_size) { + size_t aligned_size; + + // adjust last page size + if ((off + cmp_size) > length) { + cmp_size = length - off; + } + + aligned_size = cmp_size; + + if (aligned_size & (4 - 1)) { + aligned_size = (cmp_size + 4) & ~(4 - 1); + } + + stlink_read_mem32(sl, address + (uint32_t)off, (uint16_t)aligned_size); + + if (memcmp(sl->q_buf, data + off, cmp_size)) { + ELOG("Verification of flash failed at offset: %u\n", (unsigned int)off); + return (-1); + } + } + + ILOG("Flash written and verified! jolly good!\n"); + return (0); +} + +// Check if an address and size are within the flash +int stlink_check_address_range_validity(stlink_t *sl, stm32_addr_t addr, size_t size) { + long unsigned int logvar; + if (addr < sl->flash_base || addr >= (sl->flash_base + sl->flash_size)) { + logvar = sl->flash_base + sl->flash_size - 1; + ELOG("Invalid address, it should be within 0x%08x - 0x%08lx\n", sl->flash_base, logvar); + return (-1); + } + if ((addr + size) > (sl->flash_base + sl->flash_size)) { + logvar = sl->flash_base + sl->flash_size - addr; + ELOG("The size exceeds the size of the flash (0x%08lx bytes available)\n", logvar); + return (-1); + } + return 0; +} + +// Check if an address is aligned with the beginning of a page +int stlink_check_address_alignment(stlink_t *sl, stm32_addr_t addr) { + stm32_addr_t page = sl->flash_base; + + while (page < addr) { + page += stlink_calculate_pagesize(sl, page); + } + + if (page != addr) { + return -1; + } + + return 0; +} + +int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t *base, + uint32_t len, uint8_t eraseonly) { + int ret; + flash_loader_t fl; + ILOG("Attempting to write %d (%#x) bytes to stm32 address: %u (%#x)\n", len, + len, addr, addr); + // check addr range is inside the flash + stlink_calculate_pagesize(sl, addr); + + // Check the address and size validity + if (stlink_check_address_range_validity(sl, addr, len) < 0) { + return (-1); + } else if (len & 1) { + WLOG("unaligned len 0x%x -- padding with zero\n", len); + len += 1; + } else if (stlink_check_address_alignment(sl, addr) < 0) { + ELOG("addr not a multiple of current pagesize (%u bytes), not supported, " + "check page start address and compare with flash module organisation " + "in related ST reference manual of your device.\n", + (unsigned)(sl->flash_pgsz)); + return (-1); + } + + // make sure we've loaded the context with the chip details + stlink_core_id(sl); + + // Erase this section of the flash + if (stlink_erase_flash_section(sl, addr, len, true) < 0) { + ELOG("Failed to erase the flash prior to writing\n"); + return (-1); + } + + if (eraseonly) { + return (0); + } + + ret = stlink_flashloader_start(sl, &fl); + if (ret) + return ret; + ret = stlink_flashloader_write(sl, &fl, addr, base, len); + if (ret) + return ret; + ret = stlink_flashloader_stop(sl, &fl); + if (ret) + return ret; + + return (stlink_verify_write_flash(sl, addr, base, len)); +} diff --git a/src/common_flash.h b/src/common_flash.h new file mode 100644 index 000000000..70a6f0e04 --- /dev/null +++ b/src/common_flash.h @@ -0,0 +1,27 @@ +/* + * File: common_flash.h + * + * TODO: add a description + */ + +#ifndef COMMON_FLASH_H +#define COMMON_FLASH_H + +void lock_flash(stlink_t *); +void clear_flash_error(stlink_t *); +void wait_flash_busy(stlink_t *); +int check_flash_error(stlink_t *); +int unlock_flash_if(stlink_t *); +int lock_flash_option(stlink_t *); +int unlock_flash_option_if(stlink_t *); +void write_flash_cr_psiz(stlink_t *, uint32_t, unsigned); +void clear_flash_cr_pg(stlink_t *, unsigned); + +// TODO: move to private defines if possible + +#define BANK_1 0 +#define BANK_2 1 + +uint32_t read_flash_cr(stlink_t *, unsigned); +uint32_t get_stm32l0_flash_base(stlink_t *); +#endif // STLINK_H diff --git a/src/flashloader.c b/src/flashloader.c new file mode 100644 index 000000000..df14e506c --- /dev/null +++ b/src/flashloader.c @@ -0,0 +1,481 @@ +#include +#include +#include "common_flash.h" + +#define L1_WRITE_BLOCK_SIZE 0x80 +#define L0_WRITE_BLOCK_SIZE 0x40 + +int stm32l1_write_half_pages(stlink_t *sl, stm32_addr_t addr, uint8_t *base, + uint32_t len, uint32_t pagesize) { + unsigned int count, off; + unsigned int num_half_pages = len / pagesize; + uint32_t val; + uint32_t flash_regs_base = get_stm32l0_flash_base(sl); + flash_loader_t fl; + bool use_loader = true; + int ret = 0; + + // enable half page write + stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); + val |= (1 << FLASH_L1_FPRG); + stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); + val |= (1 << FLASH_L1_PROG); + stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); + + wait_flash_busy(sl); + + for (count = 0; count < num_half_pages; count++) { + if (use_loader) { + ret = stlink_flash_loader_run(sl, &fl, addr + count * pagesize, + base + count * pagesize, pagesize); + if (ret && count == 0) { + /* It seems that stm32lx devices have a problem when it is blank */ + WLOG("Failed to use flash loader, fallback to soft write\n"); + use_loader = false; + } + } + if (!use_loader) { + ret = 0; + for (off = 0; off < pagesize && !ret; off += 64) { + size_t chunk = (pagesize - off > 64) ? 64 : pagesize - off; + memcpy(sl->q_buf, base + count * pagesize + off, chunk); + ret = stlink_write_mem32(sl, addr + count * pagesize + off, (uint16_t)chunk); + } + } + + if (ret) { + WLOG("l1_stlink_flash_loader_run(%#x) failed! == -1\n", + addr + count * pagesize); + break; + } + + if (sl->verbose >= 1) { + // show progress; writing procedure is slow and previous errors are + // misleading + fprintf(stdout, "\r%3u/%u halfpages written", count + 1, num_half_pages); + fflush(stdout); + } + + // wait for sr.busy to be cleared + wait_flash_busy(sl); + } + + // disable half page write + stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); + val &= ~((1 << FLASH_L1_FPRG) | (1 << FLASH_L1_PROG)); + stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); + return (ret); +} + +static void set_flash_cr_pg(stlink_t *sl, unsigned bank) { + uint32_t cr_reg, x; + + x = read_flash_cr(sl, bank); + + if (sl->flash_type == STLINK_FLASH_TYPE_F4) { + cr_reg = FLASH_F4_CR; + x |= 1 << FLASH_CR_PG; + } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { + cr_reg = FLASH_F7_CR; + x |= 1 << FLASH_CR_PG; + } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { + cr_reg = STM32L4_FLASH_CR; + x &= ~STM32L4_FLASH_CR_OPBITS; + x |= (1 << STM32L4_FLASH_CR_PG); + } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || + sl->flash_type == STLINK_FLASH_TYPE_G4) { + cr_reg = STM32Gx_FLASH_CR; + x |= (1 << FLASH_CR_PG); + } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + cr_reg = STM32WB_FLASH_CR; + x |= (1 << FLASH_CR_PG); + } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + cr_reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; + x |= (1 << FLASH_H7_CR_PG); + } else { + cr_reg = FLASH_CR; + x = (1 << FLASH_CR_PG); + } + + stlink_write_debug32(sl, cr_reg, x); +} + +static void set_dma_state(stlink_t *sl, flash_loader_t *fl, int bckpRstr) { + uint32_t rcc, rcc_dma_mask, value; + + rcc = rcc_dma_mask = value = 0; + + switch (sl->flash_type) { + case STLINK_FLASH_TYPE_F0: + case STLINK_FLASH_TYPE_F1_XL: + rcc = STM32F1_RCC_AHBENR; + rcc_dma_mask = STM32F1_RCC_DMAEN; + break; + case STLINK_FLASH_TYPE_F4: + case STLINK_FLASH_TYPE_F7: + rcc = STM32F4_RCC_AHB1ENR; + rcc_dma_mask = STM32F4_RCC_DMAEN; + break; + case STLINK_FLASH_TYPE_G0: + rcc = STM32G0_RCC_AHBENR; + rcc_dma_mask = STM32G0_RCC_DMAEN; + break; + case STLINK_FLASH_TYPE_G4: + case STLINK_FLASH_TYPE_L4: + rcc = STM32G4_RCC_AHB1ENR; + rcc_dma_mask = STM32G4_RCC_DMAEN; + break; + case STLINK_FLASH_TYPE_L0: + rcc = STM32L0_RCC_AHBENR; + rcc_dma_mask = STM32L0_RCC_DMAEN; + break; + case STLINK_FLASH_TYPE_H7: + rcc = STM32H7_RCC_AHB1ENR; + rcc_dma_mask = STM32H7_RCC_DMAEN; + break; + case STLINK_FLASH_TYPE_WB: + rcc = STM32WB_RCC_AHB1ENR; + rcc_dma_mask = STM32WB_RCC_DMAEN; + break; + default: + return; + } + + if (!stlink_read_debug32(sl, rcc, &value)) { + if (bckpRstr) { + value = (value & (~rcc_dma_mask)) | fl->rcc_dma_bkp; + } else { + fl->rcc_dma_bkp = value & rcc_dma_mask; + value &= ~rcc_dma_mask; + } + stlink_write_debug32(sl, rcc, value); + } +} + +int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { + // disable DMA + set_dma_state(sl, fl, 0); + + // wait for ongoing op to finish + wait_flash_busy(sl); + // Clear errors + clear_flash_error(sl); + + if ((sl->flash_type == STLINK_FLASH_TYPE_F4) || + (sl->flash_type == STLINK_FLASH_TYPE_F7) || + (sl->flash_type == STLINK_FLASH_TYPE_L4)) { + ILOG("Starting Flash write for F2/F4/F7/L4\n"); + + // Flash loader initialisation + if (stlink_flash_loader_init(sl, fl) == -1) { + ELOG("stlink_flash_loader_init() == -1\n"); + return (-1); + } + + unlock_flash_if(sl); // first unlock the cr + + int voltage; + if (sl->version.stlink_v == 1) { + WLOG("STLINK V1 cannot read voltage, use default voltage 3.2V\n"); + voltage = 3200; + } else { + voltage = stlink_target_voltage(sl); + } + + if (voltage == -1) { + ELOG("Failed to read Target voltage\n"); + return (-1); + } + + if (sl->flash_type == STLINK_FLASH_TYPE_L4) { + // L4 does not have a byte-write mode + if (voltage < 1710) { + ELOG("Target voltage (%d mV) too low for flash writes!\n", voltage); + return (-1); + } + } else { + if (voltage > 2700) { + ILOG("enabling 32-bit flash writes\n"); + write_flash_cr_psiz(sl, 2, BANK_1); + } else { + ILOG("Target voltage (%d mV) too low for 32-bit flash, " + "using 8-bit flash writes\n", + voltage); + write_flash_cr_psiz(sl, 0, BANK_1); + } + } + + // set programming mode + set_flash_cr_pg(sl, BANK_1); + } else if (sl->flash_type == STLINK_FLASH_TYPE_WB || + sl->flash_type == STLINK_FLASH_TYPE_G0 || + sl->flash_type == STLINK_FLASH_TYPE_G4) { + ILOG("Starting Flash write for WB/G0/G4\n"); + + unlock_flash_if(sl); // unlock flash if necessary + set_flash_cr_pg(sl, BANK_1); // set PG 'allow programming' bit + } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { + ILOG("Starting Flash write for L0\n"); + + uint32_t val; + uint32_t flash_regs_base = get_stm32l0_flash_base(sl); + + // disable pecr protection + stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, + FLASH_L0_PEKEY1); + stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, + FLASH_L0_PEKEY2); + + // check pecr.pelock is cleared + stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); + if (val & (1 << 0)) { + ELOG("pecr.pelock not clear\n"); + return (-1); + } + + // unlock program memory + stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, + FLASH_L0_PRGKEY1); + stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, + FLASH_L0_PRGKEY2); + + // check pecr.prglock is cleared + stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); + if (val & (1 << 1)) { + ELOG("pecr.prglock not clear\n"); + return (-1); + } + + /* Flash loader initialisation */ + if (stlink_flash_loader_init(sl, fl) == -1) { + // L0/L1 have fallback to soft write + WLOG("stlink_flash_loader_init() == -1\n"); + } + } else if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || + (sl->flash_type == STLINK_FLASH_TYPE_F1_XL)) { + ILOG("Starting Flash write for VL/F0/F3/F1_XL\n"); + + // flash loader initialisation + if (stlink_flash_loader_init(sl, fl) == -1) { + ELOG("stlink_flash_loader_init() == -1\n"); + return (-1); + } + + // unlock flash + unlock_flash_if(sl); + + // set programming mode + set_flash_cr_pg(sl, BANK_1); + if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL) { + set_flash_cr_pg(sl, BANK_2); + } + } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + ILOG("Starting Flash write for H7\n"); + + unlock_flash_if(sl); // unlock the cr + set_flash_cr_pg(sl, BANK_1); // set programming mode + if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { + set_flash_cr_pg(sl, BANK_2); + } + if (sl->chip_id != STLINK_CHIPID_STM32_H7Ax) { + // set parallelism + write_flash_cr_psiz(sl, 3 /*64it*/, BANK_1); + if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { + write_flash_cr_psiz(sl, 3 /*64bit*/, BANK_2); + } + } + } else { + ELOG("unknown coreid, not sure how to write: %x\n", sl->core_id); + return (-1); + } + + return (0); +} + +int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, + stm32_addr_t addr, uint8_t *base, uint32_t len) { + size_t off; + if ((sl->flash_type == STLINK_FLASH_TYPE_F4) || + (sl->flash_type == STLINK_FLASH_TYPE_F7) || + (sl->flash_type == STLINK_FLASH_TYPE_L4)) { + size_t buf_size = (sl->sram_size > 0x8000) ? 0x8000 : 0x4000; + for (off = 0; off < len;) { + size_t size = len - off > buf_size ? buf_size : len - off; + if (stlink_flash_loader_run(sl, fl, addr + (uint32_t)off, base + off, + size) == -1) { + ELOG("stlink_flash_loader_run(%#x) failed! == -1\n", + (unsigned)(addr + off)); + check_flash_error(sl); + return (-1); + } + + off += size; + } + } else if (sl->flash_type == STLINK_FLASH_TYPE_WB || + sl->flash_type == STLINK_FLASH_TYPE_G0 || + sl->flash_type == STLINK_FLASH_TYPE_G4) { + DLOG("Starting %3u page write\r\n", (unsigned int)(len / sl->flash_pgsz)); + for (off = 0; off < len; off += sizeof(uint32_t)) { + uint32_t data; + + if ((off % sl->flash_pgsz) > (sl->flash_pgsz - 5)) { + fprintf(stdout, "\r%3u/%3u pages written", + (unsigned int)(off / sl->flash_pgsz), + (unsigned int)(len / sl->flash_pgsz)); + fflush(stdout); + } + + write_uint32((unsigned char *)&data, *(uint32_t *)(base + off)); + stlink_write_debug32(sl, addr + (uint32_t)off, data); + wait_flash_busy(sl); // wait for 'busy' bit in FLASH_SR to clear + } + fprintf(stdout, "\n"); + + // flash writes happen as 2 words at a time + if ((off / sizeof(uint32_t)) % 2 != 0) { + stlink_write_debug32(sl, addr + (uint32_t)off, + 0); // write a single word of zeros + wait_flash_busy(sl); // wait for 'busy' bit in FLASH_SR to clear + } + } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { + uint32_t val; + uint32_t flash_regs_base = get_stm32l0_flash_base(sl); + uint32_t pagesize = (flash_regs_base==STM32L0_FLASH_REGS_ADDR)? + L0_WRITE_BLOCK_SIZE:L1_WRITE_BLOCK_SIZE; + + DLOG("Starting %3u page write\r\n", (unsigned int)(len / sl->flash_pgsz)); + + off = 0; + + if (len > pagesize) { + if (stm32l1_write_half_pages(sl, addr, base, len, pagesize)) { + return (-1); + } else { + off = (size_t)(len / pagesize) * pagesize; + } + } + + // write remaining word in program memory + for (; off < len; off += sizeof(uint32_t)) { + uint32_t data; + + if ((off % sl->flash_pgsz) > (sl->flash_pgsz - 5)) { + fprintf(stdout, "\r%3u/%3u pages written", + (unsigned int)(off / sl->flash_pgsz), + (unsigned int)(len / sl->flash_pgsz)); + fflush(stdout); + } + + write_uint32((unsigned char *)&data, *(uint32_t *)(base + off)); + stlink_write_debug32(sl, addr + (uint32_t)off, data); + + // wait for sr.busy to be cleared + do { + stlink_read_debug32(sl, flash_regs_base + FLASH_SR_OFF, &val); + } while ((val & (1 << 0)) != 0); + + // TODO: check redo write operation + } + fprintf(stdout, "\n"); + } else if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || + (sl->flash_type == STLINK_FLASH_TYPE_F1_XL)) { + int write_block_count = 0; + for (off = 0; off < len; off += sl->flash_pgsz) { + // adjust last write size + size_t size = len - off > sl->flash_pgsz ? sl->flash_pgsz : len - off; + + // unlock and set programming mode + unlock_flash_if(sl); + + DLOG("Finished unlocking flash, running loader!\n"); + + if (stlink_flash_loader_run(sl, fl, addr + (uint32_t)off, base + off, + size) == -1) { + ELOG("stlink_flash_loader_run(%#x) failed! == -1\n", + (unsigned)(addr + off)); + check_flash_error(sl); + return (-1); + } + + lock_flash(sl); + + if (sl->verbose >= 1) { + // show progress; writing procedure is slow and previous errors are + // misleading + fprintf(stdout, "\r%3u/%3u pages written", ++write_block_count, + (unsigned int)((len + sl->flash_pgsz - 1) / sl->flash_pgsz)); + fflush(stdout); + } + } + if (sl->verbose >= 1) { + fprintf(stdout, "\n"); + } + } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + for (off = 0; off < len;) { + // Program STM32H7x with 64-byte Flash words + size_t chunk = (len - off > 64) ? 64 : len - off; + memcpy(sl->q_buf, base + off, chunk); + stlink_write_mem32(sl, addr + (uint32_t)off, 64); + wait_flash_busy(sl); + + off += chunk; + + if (sl->verbose >= 1) { + // show progress + fprintf(stdout, "\r%u/%u bytes written", (unsigned int)off, + (unsigned int)len); + fflush(stdout); + } + } + if (sl->verbose >= 1) { + fprintf(stdout, "\n"); + } + } else { + return (-1); + } + + return check_flash_error(sl); +} + +int stlink_flashloader_stop(stlink_t *sl, flash_loader_t *fl) { + uint32_t dhcsr; + + if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || + (sl->flash_type == STLINK_FLASH_TYPE_F1_XL) || + (sl->flash_type == STLINK_FLASH_TYPE_F4) || + (sl->flash_type == STLINK_FLASH_TYPE_F7) || + (sl->flash_type == STLINK_FLASH_TYPE_L4) || + (sl->flash_type == STLINK_FLASH_TYPE_WB) || + (sl->flash_type == STLINK_FLASH_TYPE_G0) || + (sl->flash_type == STLINK_FLASH_TYPE_G4) || + (sl->flash_type == STLINK_FLASH_TYPE_H7)) { + + clear_flash_cr_pg(sl, BANK_1); + if ((sl->flash_type == STLINK_FLASH_TYPE_H7 && + sl->chip_flags & CHIP_F_HAS_DUAL_BANK) || + sl->flash_type == STLINK_FLASH_TYPE_F1_XL) { + clear_flash_cr_pg(sl, BANK_2); + } + lock_flash(sl); + } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { + uint32_t val; + uint32_t flash_regs_base = get_stm32l0_flash_base(sl); + + // reset lock bits + stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); + val |= (1 << 0) | (1 << 1) | (1 << 2); + stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); + } + + // enable interrupt + if (!stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr)) { + stlink_write_debug32(sl, STLINK_REG_DHCSR, + STLINK_REG_DHCSR_DBGKEY | STLINK_REG_DHCSR_C_DEBUGEN | + (dhcsr & (~STLINK_REG_DHCSR_C_MASKINTS))); + } + + // restore DMA state + set_dma_state(sl, fl, 1); + + return (0); +} diff --git a/src/map_file.c b/src/map_file.c new file mode 100644 index 000000000..5282fae27 --- /dev/null +++ b/src/map_file.c @@ -0,0 +1,57 @@ +#include +#include +#include +#include + +#include "map_file.h" + +#ifndef MAX_FILE_SIZE +#define MAX_FILE_SIZE (1<<20) // 1 GB max file size +#endif + +int map_file(mapped_file_t *mf, const char *path) { + int error = -1; + struct stat st; + + const int fd = open(path, O_RDONLY | O_BINARY); + + if (fd == -1) { + fprintf(stderr, "open(%s) == -1\n", path); + return (-1); + } + + if (fstat(fd, &st) == -1) { + fprintf(stderr, "fstat(%s) == -1\n", path); + goto on_error; + } + + if (sizeof(st.st_size) != sizeof(size_t)) { + // on 32 bit systems, check if there is an overflow + if (st.st_size > (off_t)MAX_FILE_SIZE /*1 GB*/ ) { + // limit file size to 1 GB + fprintf(stderr, "mmap() size_t overflow for file %s\n", path); + goto on_error; + } + } + + mf->base = + (uint8_t *)mmap(NULL, (size_t)(st.st_size), PROT_READ, MAP_SHARED, fd, 0); + + if (mf->base == MAP_FAILED) { + fprintf(stderr, "mmap() == MAP_FAILED for file %s\n", path); + goto on_error; + } + + mf->len = (size_t)st.st_size; + error = 0; // success + +on_error: + close(fd); + return (error); +} + +void unmap_file(mapped_file_t *mf) { + munmap((void *)mf->base, mf->len); + mf->base = (unsigned char *)MAP_FAILED; + mf->len = 0; +} diff --git a/src/map_file.h b/src/map_file.h new file mode 100644 index 000000000..b35f24ad0 --- /dev/null +++ b/src/map_file.h @@ -0,0 +1,28 @@ +/* + * File: map_file.h + * + * TODO: add a description + */ + +#ifndef MAP_FILE_H +#define MAP_FILE_H + +#ifdef STLINK_HAVE_SYS_MMAN_H +#include +#else +#include +#endif + +/* Memory mapped file */ +typedef struct mapped_file { + uint8_t *base; + size_t len; +} mapped_file_t; + +#define MAPPED_FILE_INITIALIZER \ + { NULL, 0 } + +int map_file(mapped_file_t *, const char *); +void unmap_file(mapped_file_t *); + +#endif // MAP_FILE_H diff --git a/src/option.c b/src/option.c new file mode 100644 index 000000000..b70f7a533 --- /dev/null +++ b/src/option.c @@ -0,0 +1,1026 @@ +#include +#include +#include "common_flash.h" +#include "map_file.h" +#include "common.h" + +/** + * Read option bytes + * @param sl + * @param option_byte value to write + * @return 0 on success, -ve on failure. + */ +int stlink_read_option_control_register_Gx(stlink_t *sl, + uint32_t *option_byte) { + return stlink_read_debug32(sl, STM32Gx_FLASH_OPTR, option_byte); +} + +/** + * Read option bytes + * @param sl + * @param option_byte value to write + * @return 0 on success, -ve on failure. + */ +int stlink_read_option_bytes_Gx(stlink_t *sl, uint32_t *option_byte) { + return stlink_read_option_control_register_Gx(sl, option_byte); +} + +/** + * Read first option bytes + * @param sl + * @param option_byte option value + * @return 0 on success, -ve on failure. + */ +int stlink_read_option_bytes_generic(stlink_t *sl, uint32_t *option_byte) { + DLOG("@@@@ Read option bytes boot address from %#10x\n", sl->option_base); + return stlink_read_debug32(sl, sl->option_base, option_byte); +} + +/** + * Read option bytes + * @param sl + * @param option_byte value to write + * @return 0 on success, -ve on failure. + */ +int stlink_read_option_control_register_f2(stlink_t *sl, + uint32_t *option_byte) { + return stlink_read_debug32(sl, FLASH_F2_OPT_CR, option_byte); +} + +/** + * Read option bytes + * @param sl + * @param option_byte value to write + * @return 0 on success, -ve on failure. + */ +int stlink_read_option_bytes_f2(stlink_t *sl, uint32_t *option_byte) { + return stlink_read_option_control_register_f2(sl, option_byte); +} + +/** + * Read option bytes + * @param sl + * @param option_byte value to read + * @return 0 on success, -ve on failure. + */ +int stlink_read_option_control_register_f4(stlink_t *sl, + uint32_t *option_byte) { + return stlink_read_debug32(sl, FLASH_F4_OPTCR, option_byte); +} + +/** + * Read option bytes + * @param sl + * @param option_byte value to read + * @return 0 on success, -ve on failure. + */ +int stlink_read_option_bytes_f4(stlink_t *sl, uint32_t *option_byte) { + return stlink_read_option_control_register_f4(sl, option_byte); +} + +/** + * Read option bytes + * @param sl + * @param option_byte value to read + * @return 0 on success, -ve on failure. + * + * Since multiple bytes can be read, we read and print all but one here + * and then return the last one just like other devices + */ +int stlink_read_option_bytes_f7(stlink_t *sl, uint32_t *option_byte) { + int err = -1; + for (uint32_t counter = 0; counter < (sl->option_size / 4 - 1); counter++) { + err = stlink_read_debug32(sl, sl->option_base + counter * sizeof(uint32_t), + option_byte); + if (err == -1) { + return err; + } else { + printf("%08x\n", *option_byte); + } + } + + return stlink_read_debug32( + sl, + sl->option_base + (uint32_t)(sl->option_size / 4 - 1) * sizeof(uint32_t), + option_byte); +} + +/** + * Read option bytes + * @param sl + * @param option_byte option value + * @return 0 on success, -ve on failure. + */ +int stlink_read_option_bytes32(stlink_t *sl, uint32_t *option_byte) { + if (sl->option_base == 0) { + ELOG("Option bytes read is currently not supported for connected chip\n"); + return (-1); + } + + switch (sl->chip_id) { + case STLINK_CHIPID_STM32_F2: + return stlink_read_option_bytes_f2(sl, option_byte); + case STLINK_CHIPID_STM32_F4: + case STLINK_CHIPID_STM32_F446: + return stlink_read_option_bytes_f4(sl, option_byte); + case STLINK_CHIPID_STM32_F76xxx: + return stlink_read_option_bytes_f7(sl, option_byte); + case STLINK_CHIPID_STM32_G0_CAT1: + case STLINK_CHIPID_STM32_G0_CAT2: + case STLINK_CHIPID_STM32_G4_CAT2: + case STLINK_CHIPID_STM32_G4_CAT3: + return stlink_read_option_bytes_Gx(sl, option_byte); + default: + return stlink_read_option_bytes_generic(sl, option_byte); + } +} + + +/** + * Write option bytes + * @param sl + * @param base option bytes to write + * @param addr of the memory mapped option bytes + * @param len of options bytes to write + * @return 0 on success, -ve on failure. + */ +static int stlink_write_option_bytes_f0( + stlink_t *sl, uint8_t* base, stm32_addr_t addr, uint32_t len) { + int ret = 0; + + if (len < 12 || addr != STM32_F0_OPTION_BYTES_BASE) { + WLOG("Only full write of option bytes area is supported\n"); + return -1; + } + + clear_flash_error(sl); + + WLOG("Erasing option bytes\n"); + + /* erase option bytes */ + stlink_write_debug32(sl, FLASH_CR, (1 << FLASH_CR_OPTER) | (1 << FLASH_CR_OPTWRE)); + ret = stlink_write_debug32(sl, FLASH_CR, (1 << FLASH_CR_OPTER) | (1 << FLASH_CR_STRT) | (1 << FLASH_CR_OPTWRE)); + if (ret) { + return ret; + } + + wait_flash_busy(sl); + + ret = check_flash_error(sl); + if (ret) { + return ret; + } + + WLOG("Writing option bytes to %#10x\n", addr); + + /* Set the Option PG bit to enable programming */ + stlink_write_debug32(sl, FLASH_CR, (1 << FLASH_CR_OPTPG) | (1 << FLASH_CR_OPTWRE)); + + /* Use flash loader for write OP + * because flash memory writable by half word */ + flash_loader_t fl; + ret = stlink_flash_loader_init(sl, &fl); + if (ret) { + return ret; + } + ret = stlink_flash_loader_run(sl, &fl, addr, base, len); + if (ret) { + return ret; + } + + /* Reload option bytes */ + stlink_write_debug32(sl, FLASH_CR, (1 << FLASH_CR_OBL_LAUNCH)); + + return check_flash_error(sl); +} + +/** + * Write option bytes + * @param sl + * @param addr of the memory mapped option bytes + * @param base option bytes to write + * @return 0 on success, -ve on failure. + */ +static int stlink_write_option_bytes_gx(stlink_t *sl, uint8_t *base, + stm32_addr_t addr, uint32_t len) { + /* Write options bytes */ + uint32_t val; + int ret = 0; + (void)len; + uint32_t data; + + clear_flash_error(sl); + + write_uint32((unsigned char *)&data, *(uint32_t *)(base)); + WLOG("Writing option bytes %#10x to %#10x\n", data, addr); + stlink_write_debug32(sl, STM32Gx_FLASH_OPTR, data); + + // Set Options Start bit + stlink_read_debug32(sl, STM32Gx_FLASH_CR, &val); + val |= (1 << STM32Gx_FLASH_CR_OPTSTRT); + stlink_write_debug32(sl, STM32Gx_FLASH_CR, val); + + wait_flash_busy(sl); + + ret = check_flash_error(sl); + + // Reload options + stlink_read_debug32(sl, STM32Gx_FLASH_CR, &val); + val |= (1 << STM32Gx_FLASH_CR_OBL_LAUNCH); + stlink_write_debug32(sl, STM32Gx_FLASH_CR, val); + + return (ret); +} + +/** + * Write option bytes + * @param sl + * @param addr of the memory mapped option bytes + * @param base option bytes to write + * @return 0 on success, -ve on failure. + */ +static int stlink_write_option_bytes_l0(stlink_t *sl, uint8_t *base, + stm32_addr_t addr, uint32_t len) { + uint32_t flash_base = get_stm32l0_flash_base(sl); + uint32_t val; + uint32_t data; + int ret = 0; + + // Clear errors + clear_flash_error(sl); + + while (len != 0) { + write_uint32((unsigned char *)&data, + *(uint32_t *)(base)); // write options bytes + + WLOG("Writing option bytes %#10x to %#10x\n", data, addr); + stlink_write_debug32(sl, addr, data); + wait_flash_busy(sl); + + if ((ret = check_flash_error(sl))) { + break; + } + + len -= 4; + addr += 4; + base += 4; + } + + // Reload options + stlink_read_debug32(sl, flash_base + FLASH_PECR_OFF, &val); + val |= (1 << STM32L0_FLASH_OBL_LAUNCH); + stlink_write_debug32(sl, flash_base + FLASH_PECR_OFF, val); + + return (ret); +} + +/** + * Write option bytes + * @param sl + * @param addr of the memory mapped option bytes + * @param base option bytes to write + * @return 0 on success, -ve on failure. + */ +static int stlink_write_option_bytes_l4(stlink_t *sl, uint8_t *base, + stm32_addr_t addr, uint32_t len) { + + uint32_t val; + int ret = 0; + (void)addr; + (void)len; + + // Clear errors + clear_flash_error(sl); + + // write options bytes + uint32_t data; + write_uint32((unsigned char *)&data, *(uint32_t *)(base)); + WLOG("Writing option bytes 0x%04x\n", data); + stlink_write_debug32(sl, STM32L4_FLASH_OPTR, data); + + // set options start bit + stlink_read_debug32(sl, STM32L4_FLASH_CR, &val); + val |= (1 << STM32L4_FLASH_CR_OPTSTRT); + stlink_write_debug32(sl, STM32L4_FLASH_CR, val); + + wait_flash_busy(sl); + ret = check_flash_error(sl); + + // apply options bytes immediate + stlink_read_debug32(sl, STM32L4_FLASH_CR, &val); + val |= (1 << STM32L4_FLASH_CR_OBL_LAUNCH); + stlink_write_debug32(sl, STM32L4_FLASH_CR, val); + + return (ret); +} + +/** + * Write option bytes + * @param sl + * @param option_byte value to write + * @return 0 on success, -ve on failure. + */ +static int stlink_write_option_bytes_f4(stlink_t *sl, uint8_t *base, + stm32_addr_t addr, uint32_t len) { + uint32_t option_byte; + int ret = 0; + (void)addr; + (void)len; + + // Clear errors + clear_flash_error(sl); + + write_uint32((unsigned char *)&option_byte, *(uint32_t *)(base)); + + // write option byte, ensuring we dont lock opt, and set strt bit + stlink_write_debug32(sl, FLASH_F4_OPTCR, + (option_byte & ~(1 << FLASH_F4_OPTCR_LOCK)) | + (1 << FLASH_F4_OPTCR_START)); + + wait_flash_busy(sl); + ret = check_flash_error(sl); + + // option bytes are reloaded at reset only, no obl. */ + return (ret); +} + +/** + * Write option bytes + * @param sl + * @param option_byte value to write + * @return 0 on success, -ve on failure. + */ +static int stlink_write_option_bytes_f7(stlink_t *sl, uint8_t *base, + stm32_addr_t addr, uint32_t len) { + uint32_t option_byte; + int ret = 0; + + // Clear errors + clear_flash_error(sl); + + ILOG("Asked to write option byte %#10x to %#010x.\n", *(uint32_t *)(base), + addr); + write_uint32((unsigned char *)&option_byte, *(uint32_t *)(base)); + ILOG("Write %d option bytes %#010x to %#010x!\n", len, option_byte, addr); + + if (addr == 0) { + addr = FLASH_F7_OPTCR; + ILOG("No address provided, using %#10x\n", addr); + } + + if (addr == FLASH_F7_OPTCR) { + /* write option byte, ensuring we dont lock opt, and set strt bit */ + stlink_write_debug32(sl, FLASH_F7_OPTCR, + (option_byte & ~(1 << FLASH_F7_OPTCR_LOCK)) | + (1 << FLASH_F7_OPTCR_START)); + } else if (addr == FLASH_F7_OPTCR1) { + // Read FLASH_F7_OPTCR + uint32_t oldvalue; + stlink_read_debug32(sl, FLASH_F7_OPTCR, &oldvalue); + /* write option byte */ + stlink_write_debug32(sl, FLASH_F7_OPTCR1, option_byte); + // Write FLASH_F7_OPTCR lock and start address + stlink_write_debug32(sl, FLASH_F7_OPTCR, + (oldvalue & ~(1 << FLASH_F7_OPTCR_LOCK)) | + (1 << FLASH_F7_OPTCR_START)); + } else { + WLOG("WIP: write %#010x to address %#010x\n", option_byte, addr); + stlink_write_debug32(sl, addr, option_byte); + } + + wait_flash_busy(sl); + + ret = check_flash_error(sl); + if (!ret) + ILOG("Wrote %d option bytes %#010x to %#010x!\n", len, *(uint32_t *)base, + addr); + + /* option bytes are reloaded at reset only, no obl. */ + + return ret; +} + +/** + * Write STM32H7xx option bytes + * @param sl + * @param base option bytes to write + * @param addr of the memory mapped option bytes + * @param len number of bytes to write (must be multiple of 4) + * @return 0 on success, -ve on failure. + */ +static int stlink_write_option_bytes_h7(stlink_t *sl, uint8_t *base, + stm32_addr_t addr, uint32_t len) { + uint32_t val; + uint32_t data; + + // Wait until previous flash option has completed + wait_flash_busy(sl); + + // Clear previous error + stlink_write_debug32(sl, FLASH_H7_OPTCCR, + 1 << FLASH_H7_OPTCCR_CLR_OPTCHANGEERR); + + while (len != 0) { + switch (addr) { + case FLASH_H7_REGS_ADDR + 0x20: // FLASH_OPTSR_PRG + case FLASH_H7_REGS_ADDR + 0x2c: // FLASH_PRAR_PRG1 + case FLASH_H7_REGS_ADDR + 0x34: // FLASH_SCAR_PRG1 + case FLASH_H7_REGS_ADDR + 0x3c: // FLASH_WPSN_PRG1 + case FLASH_H7_REGS_ADDR + 0x44: // FLASH_BOOT_PRG + /* Write to FLASH_xxx_PRG registers */ + write_uint32((unsigned char *)&data, + *(uint32_t *)(base)); // write options bytes + + WLOG("Writing option bytes %#10x to %#10x\n", data, addr); + + /* Skip if the value in the CUR register is identical */ + stlink_read_debug32(sl, addr - 4, &val); + if (val == data) { + break; + } + + /* Write new option byte values and start modification */ + stlink_write_debug32(sl, addr, data); + stlink_read_debug32(sl, FLASH_H7_OPTCR, &val); + val |= (1 << FLASH_H7_OPTCR_OPTSTART); + stlink_write_debug32(sl, FLASH_H7_OPTCR, val); + + /* Wait for the option bytes modification to complete */ + do { + stlink_read_debug32(sl, FLASH_H7_OPTSR_CUR, &val); + } while ((val & (1 << FLASH_H7_OPTSR_OPT_BUSY)) != 0); + + /* Check for errors */ + if ((val & (1 << FLASH_H7_OPTSR_OPTCHANGEERR)) != 0) { + stlink_write_debug32(sl, FLASH_H7_OPTCCR, + 1 << FLASH_H7_OPTCCR_CLR_OPTCHANGEERR); + return -1; + } + break; + + default: + /* Skip non-programmable registers */ + break; + } + + len -= 4; + addr += 4; + base += 4; + } + + return 0; +} + +/** + * Write option bytes + * @param sl + * @param addr of the memory mapped option bytes + * @param base option bytes to write + * @return 0 on success, -ve on failure. + */ +int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t *base, + uint32_t len) { + int ret = -1; + + if (sl->option_base == 0) { + ELOG( + "Option bytes writing is currently not supported for connected chip\n"); + return (-1); + } + + if ((addr < sl->option_base) || addr > sl->option_base + sl->option_size) { + ELOG("Option bytes start address out of Option bytes range\n"); + return (-1); + } + + if (addr + len > sl->option_base + sl->option_size) { + ELOG("Option bytes data too long\n"); + return (-1); + } + + wait_flash_busy(sl); + + if (unlock_flash_if(sl)) { + ELOG("Flash unlock failed! System reset required to be able to unlock it " + "again!\n"); + return (-1); + } + + if (unlock_flash_option_if(sl)) { + ELOG("Flash option unlock failed!\n"); + return (-1); + } + + switch (sl->flash_type) { + case STLINK_FLASH_TYPE_F0: + case STLINK_FLASH_TYPE_F1_XL: + ret = stlink_write_option_bytes_f0(sl, base, addr, len); + break; + case STLINK_FLASH_TYPE_F4: + ret = stlink_write_option_bytes_f4(sl, base, addr, len); + break; + case STLINK_FLASH_TYPE_F7: + ret = stlink_write_option_bytes_f7(sl, base, addr, len); + break; + case STLINK_FLASH_TYPE_L0: + ret = stlink_write_option_bytes_l0(sl, base, addr, len); + break; + case STLINK_FLASH_TYPE_L4: + ret = stlink_write_option_bytes_l4(sl, base, addr, len); + break; + case STLINK_FLASH_TYPE_G0: + case STLINK_FLASH_TYPE_G4: + ret = stlink_write_option_bytes_gx(sl, base, addr, len); + break; + case STLINK_FLASH_TYPE_H7: + ret = stlink_write_option_bytes_h7(sl, base, addr, len); + break; + default: + ELOG("Option bytes writing is currently not implemented for connected " + "chip\n"); + break; + } + + if (ret) { + ELOG("Flash option write failed!\n"); + } else { + ILOG("Wrote %d option bytes to %#010x!\n", len, addr); + } + + /* Re-lock flash. */ + lock_flash_option(sl); + lock_flash(sl); + + return ret; +} + + +/** + * Write option bytes + * @param sl + * @param option_byte value to write + * @return 0 on success, -ve on failure. + */ +static int +stlink_write_option_control_register_f0(stlink_t *sl, + uint32_t option_control_register) { + int ret = 0; + uint16_t opt_val[8]; + unsigned protection, optiondata; + uint16_t user_options, user_data, rdp; + unsigned option_offset, user_data_offset; + + ILOG("Asked to write option control register %#10x to %#010x.\n", + option_control_register, FLASH_OBR); + + /* Clear errors */ + clear_flash_error(sl); + + /* Retrieve current values */ + ret = stlink_read_debug32(sl, FLASH_OBR, &optiondata); + if (ret) { + return ret; + } + ret = stlink_read_debug32(sl, FLASH_WRPR, &protection); + if (ret) { + return ret; + } + + /* Translate OBR value to flash store structure + * F0: RM0091, Option byte description, pp. 75-78 + * F1: PM0075, Option byte description, pp. 19-22 + * F3: RM0316, Option byte description, pp. 85-87 */ + switch(sl->chip_id) + { + case 0x422: /* STM32F30x */ + case 0x432: /* STM32F37x */ + case 0x438: /* STM32F303x6/8 and STM32F328 */ + case 0x446: /* STM32F303xD/E and STM32F398xE */ + case 0x439: /* STM32F302x6/8 */ + case 0x440: /* STM32F05x */ + case 0x444: /* STM32F03x */ + case 0x445: /* STM32F04x */ + case 0x448: /* STM32F07x */ + case 0x442: /* STM32F09x */ + option_offset = 6; + user_data_offset = 16; + rdp = 0x55AA; + break; + default: + option_offset = 0; + user_data_offset = 10; + rdp = 0x5AA5; + break; + } + + user_options = (option_control_register >> option_offset >> 2) & 0xFFFF; + user_data = (option_control_register >> user_data_offset) & 0xFFFF; + +#define VAL_WITH_COMPLEMENT(v) (uint16_t)(((v)&0xFF) | (((~(v))<<8)&0xFF00)) + + opt_val[0] = (option_control_register & (1 << 1/*OPT_READOUT*/)) ? 0xFFFF : rdp; + opt_val[1] = VAL_WITH_COMPLEMENT(user_options); + opt_val[2] = VAL_WITH_COMPLEMENT(user_data); + opt_val[3] = VAL_WITH_COMPLEMENT(user_data >> 8); + opt_val[4] = VAL_WITH_COMPLEMENT(protection); + opt_val[5] = VAL_WITH_COMPLEMENT(protection >> 8); + opt_val[6] = VAL_WITH_COMPLEMENT(protection >> 16); + opt_val[7] = VAL_WITH_COMPLEMENT(protection >> 24); + +#undef VAL_WITH_COMPLEMENT + + /* Write bytes and check errors */ + ret = stlink_write_option_bytes_f0(sl, (uint8_t*)opt_val, STM32_F0_OPTION_BYTES_BASE, sizeof(opt_val)); + if (ret) + return ret; + + ret = check_flash_error(sl); + if (!ret) { + ILOG("Wrote option bytes %#010x to %#010x!\n", option_control_register, + FLASH_OBR); + } + + return ret; +} + + +/** + * Write option bytes + * @param sl + * @param option_byte value to write + * @return 0 on success, -ve on failure. + */ +static int +stlink_write_option_control_register1_f7(stlink_t *sl, + uint32_t option_control_register1) { + int ret = 0; + + // Clear errors + clear_flash_error(sl); + + ILOG("Asked to write option control register 1 %#010x to %#010x.\n", + option_control_register1, FLASH_F7_OPTCR1); + + /* write option byte, ensuring we dont lock opt, and set strt bit */ + uint32_t current_control_register_value; + stlink_read_debug32(sl, FLASH_F7_OPTCR, ¤t_control_register_value); + + /* write option byte */ + stlink_write_debug32(sl, FLASH_F7_OPTCR1, option_control_register1); + stlink_write_debug32( + sl, FLASH_F7_OPTCR, + (current_control_register_value & ~(1 << FLASH_F7_OPTCR_LOCK)) | + (1 << FLASH_F7_OPTCR_START)); + + wait_flash_busy(sl); + + ret = check_flash_error(sl); + if (!ret) + ILOG("Wrote option bytes %#010x to %#010x!\n", option_control_register1, + FLASH_F7_OPTCR1); + + return ret; +} + +/** + * Write option bytes + * @param sl + * @param option_byte value to write + * @return 0 on success, -ve on failure. + */ +static int +stlink_write_option_control_register_f7(stlink_t *sl, + uint32_t option_control_register) { + int ret = 0; + + // Clear errors + clear_flash_error(sl); + + ILOG("Asked to write option control register 1 %#10x to %#010x.\n", + option_control_register, FLASH_F7_OPTCR); + + /* write option byte, ensuring we dont lock opt, and set strt bit */ + stlink_write_debug32(sl, FLASH_F7_OPTCR, + (option_control_register & ~(1 << FLASH_F7_OPTCR_LOCK)) | + (1 << FLASH_F7_OPTCR_START)); + + wait_flash_busy(sl); + + ret = check_flash_error(sl); + if (!ret) + ILOG("Wrote option bytes %#010x to %#010x!\n", option_control_register, + FLASH_F7_OPTCR); + + return ret; +} + +/** + * Write option bytes + * @param sl + * @param option bytes boot address to write + * @return 0 on success, -ve on failure. + */ +int stlink_write_option_control_register32(stlink_t *sl, + uint32_t option_control_register) { + int ret = -1; + + wait_flash_busy(sl); + + if (unlock_flash_if(sl)) { + ELOG("Flash unlock failed! System reset required to be able to unlock it " + "again!\n"); + return -1; + } + + if (unlock_flash_option_if(sl)) { + ELOG("Flash option unlock failed!\n"); + return -1; + } + + switch (sl->flash_type) { + case STLINK_FLASH_TYPE_F0: + case STLINK_FLASH_TYPE_F1_XL: + ret = stlink_write_option_control_register_f0(sl, option_control_register); + break; + case STLINK_FLASH_TYPE_F7: + ret = stlink_write_option_control_register_f7(sl, option_control_register); + break; + default: + ELOG("Option control register writing is currently not implemented for " + "connected chip\n"); + break; + } + + if (ret) + ELOG("Flash option write failed!\n"); + else + ILOG("Wrote option control register %#010x!\n", option_control_register); + + /* Re-lock flash. */ + lock_flash_option(sl); + lock_flash(sl); + + return ret; +} + +/** + * Write option bytes + * @param sl + * @param option bytes boot address to write + * @return 0 on success, -ve on failure. + */ +int stlink_write_option_control_register1_32( + stlink_t *sl, uint32_t option_control_register1) { + int ret = -1; + + wait_flash_busy(sl); + + if (unlock_flash_if(sl)) { + ELOG("Flash unlock failed! System reset required to be able to unlock it " + "again!\n"); + return -1; + } + + if (unlock_flash_option_if(sl)) { + ELOG("Flash option unlock failed!\n"); + return -1; + } + + switch (sl->flash_type) { + case STLINK_FLASH_TYPE_F7: + ret = + stlink_write_option_control_register1_f7(sl, option_control_register1); + break; + default: + ELOG("Option control register 1 writing is currently not implemented for " + "connected chip\n"); + break; + } + + if (ret) + ELOG("Flash option write failed!\n"); + else + ILOG("Wrote option control register 1 %#010x!\n", option_control_register1); + + lock_flash_option(sl); + lock_flash(sl); + + return (ret); +} + + +/** + * Write option bytes + * @param sl + * @param option_byte value to write + * @return 0 on success, -ve on failure. + */ +static int +stlink_write_option_bytes_boot_add_f7(stlink_t *sl, + uint32_t option_byte_boot_add) { + ILOG("Asked to write option byte boot add %#010x.\n", option_byte_boot_add); + return stlink_write_option_control_register1_f7(sl, option_byte_boot_add); +} + +/** + * Write option bytes + * @param sl + * @param option bytes boot address to write + * @return 0 on success, -ve on failure. + */ +int stlink_write_option_bytes_boot_add32(stlink_t *sl, + uint32_t option_bytes_boot_add) { + int ret = -1; + + wait_flash_busy(sl); + + if (unlock_flash_if(sl)) { + ELOG("Flash unlock failed! System reset required to be able to unlock it " + "again!\n"); + return -1; + } + + if (unlock_flash_option_if(sl)) { + ELOG("Flash option unlock failed!\n"); + return -1; + } + + switch (sl->flash_type) { + case STLINK_FLASH_TYPE_F7: + ret = stlink_write_option_bytes_boot_add_f7(sl, option_bytes_boot_add); + break; + default: + ELOG("Option bytes boot address writing is currently not implemented for " + "connected chip\n"); + break; + } + + if (ret) + ELOG("Flash option write failed!\n"); + else + ILOG("Wrote option bytes boot address %#010x!\n", option_bytes_boot_add); + + /* Re-lock flash. */ + lock_flash_option(sl); + lock_flash(sl); + + return ret; +} + +/** + * Write option bytes + * @param sl + * @param option_byte value to write + * @return 0 on success, -ve on failure. + */ +int stlink_write_option_bytes32(stlink_t *sl, uint32_t option_byte) { + WLOG("About to write option byte %#10x to %#10x.\n", option_byte, + sl->option_base); + return stlink_write_option_bytes(sl, sl->option_base, (uint8_t *)&option_byte, + 4); +} + +/** + * Write the given binary file with option bytes + * @param sl + * @param path readable file path, should be binary image + * @param addr of the memory mapped option bytes + * @return 0 on success, -ve on failure. + */ +int stlink_fwrite_option_bytes(stlink_t *sl, const char *path, + stm32_addr_t addr) { + /* Write the file in flash at addr */ + int err; + mapped_file_t mf = MAPPED_FILE_INITIALIZER; + + if (map_file(&mf, path) == -1) { + ELOG("map_file() == -1\n"); + return (-1); + } + + printf("file %s ", path); + md5_calculate(&mf); + stlink_checksum(&mf); + + err = stlink_write_option_bytes(sl, addr, mf.base, (uint32_t)mf.len); + stlink_fwrite_finalize(sl, addr); + unmap_file(&mf); + + return (err); +} + +/** + * Read option bytes + * @param sl + * @param option_byte value to read + * @return 0 on success, -ve on failure. + */ +int stlink_read_option_control_register1_f7(stlink_t *sl, + uint32_t *option_byte) { + DLOG("@@@@ Read option control register 1 byte from %#10x\n", + FLASH_F7_OPTCR1); + return stlink_read_debug32(sl, FLASH_F7_OPTCR1, option_byte); +} + +/** + * Read option bytes + * @param sl + * @param option_byte option value + * @return 0 on success, -ve on failure. + */ +int stlink_read_option_control_register1_32(stlink_t *sl, + uint32_t *option_byte) { + if (sl->option_base == 0) { + ELOG("Option bytes read is currently not supported for connected chip\n"); + return -1; + } + + switch (sl->flash_type) { + case STLINK_FLASH_TYPE_F7: + return stlink_read_option_control_register1_f7(sl, option_byte); + default: + return -1; + // return stlink_read_option_control_register1_generic(sl, option_byte); + } +} + + +/** + * Read option bytes + * @param sl + * @param option_byte value to read + * @return 0 on success, -ve on failure. + */ +int stlink_read_option_bytes_boot_add_f7(stlink_t *sl, uint32_t *option_byte) { + DLOG("@@@@ Read option byte boot address\n"); + return stlink_read_option_control_register1_f7(sl, option_byte); +} + +/** + * Read option bytes + * @param sl + * @param option_byte option value + * @return 0 on success, -ve on failure. + */ +int stlink_read_option_bytes_boot_add32(stlink_t *sl, uint32_t *option_byte) { + if (sl->option_base == 0) { + ELOG("Option bytes boot address read is currently not supported for " + "connected chip\n"); + return -1; + } + + switch (sl->flash_type) { + case STLINK_FLASH_TYPE_F7: + return stlink_read_option_bytes_boot_add_f7(sl, option_byte); + default: + return -1; + // return stlink_read_option_bytes_boot_add_generic(sl, option_byte); + } +} + +/** + * Read option bytes + * @param sl + * @param option_byte value to read + * @return 0 on success, -ve on failure. + */ +int stlink_read_option_control_register_f7(stlink_t *sl, + uint32_t *option_byte) { + DLOG("@@@@ Read option control register byte from %#10x\n", FLASH_F7_OPTCR); + return stlink_read_debug32(sl, FLASH_F7_OPTCR, option_byte); +} + +/** + * Read option bytes + * @param sl + * @param option_byte value to read + * @return 0 on success, -ve on failure. + */ +int stlink_read_option_control_register_f0(stlink_t *sl, + uint32_t *option_byte) { + DLOG("@@@@ Read option control register byte from %#10x\n", FLASH_OBR); + return stlink_read_debug32(sl, FLASH_OBR, option_byte); +} + +/** + * Read option bytes + * @param sl + * @param option_byte option value + * @return 0 on success, -ve on failure. + */ +int stlink_read_option_control_register32(stlink_t *sl, uint32_t *option_byte) { + if (sl->option_base == 0) { + ELOG("Option bytes read is currently not supported for connected chip\n"); + return -1; + } + + switch (sl->flash_type) { + case STLINK_FLASH_TYPE_F0: + case STLINK_FLASH_TYPE_F1_XL: + return stlink_read_option_control_register_f0(sl, option_byte); + case STLINK_FLASH_TYPE_F7: + return stlink_read_option_control_register_f7(sl, option_byte); + default: + return -1; + } +} diff --git a/src/read_write.c b/src/read_write.c new file mode 100644 index 000000000..adcda6f3b --- /dev/null +++ b/src/read_write.c @@ -0,0 +1,142 @@ +#include +#include + +// Endianness +// https://commandcenter.blogspot.com/2012/04/byte-order-fallacy.html +// These functions encode and decode little endian uint16 and uint32 values. + +void write_uint32(unsigned char *buf, uint32_t ui) { + buf[0] = ui; + buf[1] = ui >> 8; + buf[2] = ui >> 16; + buf[3] = ui >> 24; +} + +void write_uint16(unsigned char *buf, uint16_t ui) { + buf[0] = (uint8_t)ui; + buf[1] = (uint8_t)(ui >> 8); +} + +uint32_t read_uint32(const unsigned char *c, const int pt) { + return ((uint32_t)c[pt]) | ((uint32_t)c[pt + 1] << 8) | + ((uint32_t)c[pt + 2] << 16) | ((uint32_t)c[pt + 3] << 24); +} + +uint16_t read_uint16(const unsigned char *c, const int pt) { + return ((uint16_t)c[pt]) | ((uint16_t)c[pt + 1] << 8); +} + +int stlink_read_debug32(stlink_t *sl, uint32_t addr, uint32_t *data) { + int ret; + + ret = sl->backend->read_debug32(sl, addr, data); + if (!ret) + DLOG("*** stlink_read_debug32 %#010x at %#010x\n", *data, addr); + + return (ret); +} + +int stlink_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data) { + DLOG("*** stlink_write_debug32 %#010x to %#010x\n", data, addr); + return sl->backend->write_debug32(sl, addr, data); +} + +int stlink_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { + DLOG("*** stlink_write_mem32 %u bytes to %#x\n", len, addr); + + if (len % 4 != 0) { + ELOG("Data length doesn't have a 32 bit alignment: +%d byte.\n", len % 4); + return (-1); + } + + return (sl->backend->write_mem32(sl, addr, len)); +} + +int stlink_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { + DLOG("*** stlink_read_mem32 ***\n"); + + if (len % 4 != 0) { // !!! never ever: fw gives just wrong values + ELOG("Data length doesn't have a 32 bit alignment: +%d byte.\n", len % 4); + return (-1); + } + + return (sl->backend->read_mem32(sl, addr, len)); +} + +int stlink_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len) { + DLOG("*** stlink_write_mem8 ***\n"); + return (sl->backend->write_mem8(sl, addr, len)); +} + +int stlink_read_all_regs(stlink_t *sl, struct stlink_reg *regp) { + DLOG("*** stlink_read_all_regs ***\n"); + return (sl->backend->read_all_regs(sl, regp)); +} + +int stlink_read_all_unsupported_regs(stlink_t *sl, struct stlink_reg *regp) { + DLOG("*** stlink_read_all_unsupported_regs ***\n"); + return (sl->backend->read_all_unsupported_regs(sl, regp)); +} + +int stlink_write_reg(stlink_t *sl, uint32_t reg, int idx) { + DLOG("*** stlink_write_reg\n"); + return (sl->backend->write_reg(sl, reg, idx)); +} + +int stlink_read_reg(stlink_t *sl, int r_idx, struct stlink_reg *regp) { + DLOG("*** stlink_read_reg\n"); + DLOG(" (%d) ***\n", r_idx); + + if (r_idx > 20 || r_idx < 0) { + fprintf(stderr, "Error: register index must be in [0..20]\n"); + return (-1); + } + + return (sl->backend->read_reg(sl, r_idx, regp)); +} + +int stlink_read_unsupported_reg(stlink_t *sl, int r_idx, + struct stlink_reg *regp) { + int r_convert; + + DLOG("*** stlink_read_unsupported_reg\n"); + DLOG(" (%d) ***\n", r_idx); + + /* Convert to values used by STLINK_REG_DCRSR */ + if (r_idx >= 0x1C && + r_idx <= 0x1F) { // primask, basepri, faultmask, or control + r_convert = 0x14; + } else if (r_idx == 0x40) { // FPSCR + r_convert = 0x21; + } else if (r_idx >= 0x20 && r_idx < 0x40) { + r_convert = 0x40 + (r_idx - 0x20); + } else { + fprintf(stderr, "Error: register address must be in [0x1C..0x40]\n"); + return (-1); + } + + return (sl->backend->read_unsupported_reg(sl, r_convert, regp)); +} + +int stlink_write_unsupported_reg(stlink_t *sl, uint32_t val, int r_idx, + struct stlink_reg *regp) { + int r_convert; + + DLOG("*** stlink_write_unsupported_reg\n"); + DLOG(" (%d) ***\n", r_idx); + + /* Convert to values used by STLINK_REG_DCRSR */ + if (r_idx >= 0x1C && + r_idx <= 0x1F) { /* primask, basepri, faultmask, or control */ + r_convert = r_idx; // the backend function handles this + } else if (r_idx == 0x40) { // FPSCR + r_convert = 0x21; + } else if (r_idx >= 0x20 && r_idx < 0x40) { + r_convert = 0x40 + (r_idx - 0x20); + } else { + fprintf(stderr, "Error: register address must be in [0x1C..0x40]\n"); + return (-1); + } + + return (sl->backend->write_unsupported_reg(sl, val, r_convert, regp)); +} From 4ce20d07e0fedd103a0f24f583ea591f8eb12694 Mon Sep 17 00:00:00 2001 From: hydroconstructor Date: Thu, 20 Jan 2022 13:46:42 +0400 Subject: [PATCH 359/503] stlink-org#1216 refactoring of common.c File divided to some parts. Functions with "flash" in names extracted to common_flash.c, with "option" extracted to option.c etc. Removed unnecessary headers. Removed one single function which was used nowhere. And so on. Project built under Windows and seems to be working. --- src/common.c | 5701 +++++++++----------------------------------- src/common_flash.c | 1 + src/flashloader.c | 1 + src/map_file.c | 7 + src/option.c | 1 + src/read_write.c | 1 + 6 files changed, 1090 insertions(+), 4622 deletions(-) diff --git a/src/common.c b/src/common.c index 6cbd217ef..0f8117fea 100644 --- a/src/common.c +++ b/src/common.c @@ -1,27 +1,17 @@ -#define DEBUG_FLASH 0 -#include -#include -#include -#include -#include - -#include +#include #include -#include #include #include #include - -#include -#include +#include +#include #include +#include #include - -#ifdef STLINK_HAVE_SYS_MMAN_H -#include -#else -#include -#endif +#include "common_flash.h" +#include "calculate.h" +#include "map_file.h" +#include "common.h" #ifndef O_BINARY #define O_BINARY 0 @@ -31,4922 +21,1389 @@ #define __attribute__(x) #endif -#define BANK_1 0 -#define BANK_2 1 - -/* stm32f FPEC flash controller interface, pm0063 manual */ -// TODO - all of this needs to be abstracted out.... -// STM32F05x is identical, based on RM0091 (DM00031936, Doc ID 018940 Rev 2, -// August 2012) -#define FLASH_REGS_ADDR 0x40022000 -#define FLASH_REGS_SIZE 0x28 - -#define FLASH_ACR (FLASH_REGS_ADDR + 0x00) -#define FLASH_KEYR (FLASH_REGS_ADDR + 0x04) -#define FLASH_OPTKEYR (FLASH_REGS_ADDR + 0x08) -#define FLASH_SR (FLASH_REGS_ADDR + 0x0c) -#define FLASH_CR (FLASH_REGS_ADDR + 0x10) -#define FLASH_AR (FLASH_REGS_ADDR + 0x14) -#define FLASH_OBR (FLASH_REGS_ADDR + 0x1c) -#define FLASH_WRPR (FLASH_REGS_ADDR + 0x20) - -// STM32F10x_XL has two flash memory banks with separate registers to control -// the second bank. -#define FLASH_KEYR2 (FLASH_REGS_ADDR + 0x44) -#define FLASH_SR2 (FLASH_REGS_ADDR + 0x4c) -#define FLASH_CR2 (FLASH_REGS_ADDR + 0x50) -#define FLASH_AR2 (FLASH_REGS_ADDR + 0x54) - -// For STM32F05x, the RDPTR_KEY may be wrong, but as it is not used anywhere... -#define FLASH_RDPTR_KEY 0x00a5 -#define FLASH_KEY1 0x45670123 -#define FLASH_KEY2 0xcdef89ab - -#define FLASH_L0_PRGKEY1 0x8c9daebf -#define FLASH_L0_PRGKEY2 0x13141516 - -#define FLASH_L0_PEKEY1 0x89abcdef -#define FLASH_L0_PEKEY2 0x02030405 - -#define FLASH_OPTKEY1 0x08192A3B -#define FLASH_OPTKEY2 0x4C5D6E7F - -#define FLASH_F0_OPTKEY1 0x45670123 -#define FLASH_F0_OPTKEY2 0xCDEF89AB - -#define FLASH_L0_OPTKEY1 0xFBEAD9C8 -#define FLASH_L0_OPTKEY2 0x24252627 - -#define FLASH_SR_BSY 0 -#define FLASH_SR_PG_ERR 2 -#define FLASH_SR_WRPRT_ERR 4 -#define FLASH_SR_EOP 5 - -#define FLASH_SR_ERROR_MASK ((1 << FLASH_SR_PG_ERR) | (1 << FLASH_SR_WRPRT_ERR)) - -#define FLASH_CR_PG 0 -#define FLASH_CR_PER 1 -#define FLASH_CR_MER 2 -#define FLASH_CR_OPTPG 4 -#define FLASH_CR_OPTER 5 -#define FLASH_CR_STRT 6 -#define FLASH_CR_LOCK 7 -#define FLASH_CR_OPTWRE 9 -#define FLASH_CR_OBL_LAUNCH 13 - -#define STM32L_FLASH_REGS_ADDR ((uint32_t)0x40023c00) -#define STM32L_FLASH_ACR (STM32L_FLASH_REGS_ADDR + 0x00) -#define STM32L_FLASH_PECR (STM32L_FLASH_REGS_ADDR + 0x04) -#define STM32L_FLASH_PDKEYR (STM32L_FLASH_REGS_ADDR + 0x08) -#define STM32L_FLASH_PEKEYR (STM32L_FLASH_REGS_ADDR + 0x0c) -#define STM32L_FLASH_PRGKEYR (STM32L_FLASH_REGS_ADDR + 0x10) -#define STM32L_FLASH_OPTKEYR (STM32L_FLASH_REGS_ADDR + 0x14) -#define STM32L_FLASH_SR (STM32L_FLASH_REGS_ADDR + 0x18) -#define STM32L_FLASH_OBR (STM32L_FLASH_REGS_ADDR + 0x1c) -#define STM32L_FLASH_WRPR (STM32L_FLASH_REGS_ADDR + 0x20) -#define FLASH_L1_FPRG 10 -#define FLASH_L1_PROG 3 - -// Flash registers common to STM32G0 and STM32G4 series. -#define STM32Gx_FLASH_REGS_ADDR ((uint32_t)0x40022000) -#define STM32Gx_FLASH_ACR (STM32Gx_FLASH_REGS_ADDR + 0x00) -#define STM32Gx_FLASH_KEYR (STM32Gx_FLASH_REGS_ADDR + 0x08) -#define STM32Gx_FLASH_OPTKEYR (STM32Gx_FLASH_REGS_ADDR + 0x0c) -#define STM32Gx_FLASH_SR (STM32Gx_FLASH_REGS_ADDR + 0x10) -#define STM32Gx_FLASH_CR (STM32Gx_FLASH_REGS_ADDR + 0x14) -#define STM32Gx_FLASH_ECCR (STM32Gx_FLASH_REGS_ADDR + 0x18) -#define STM32Gx_FLASH_OPTR (STM32Gx_FLASH_REGS_ADDR + 0x20) - -// G0 (RM0444 Table 1, sec 3.7) -// Mostly the same as G4 chips, but the notation -// varies a bit after the 'OPTR' register. -#define STM32G0_FLASH_REGS_ADDR (STM32Gx_FLASH_REGS_ADDR) -#define STM32G0_FLASH_PCROP1ASR (STM32G0_FLASH_REGS_ADDR + 0x24) -#define STM32G0_FLASH_PCROP1AER (STM32G0_FLASH_REGS_ADDR + 0x28) -#define STM32G0_FLASH_WRP1AR (STM32G0_FLASH_REGS_ADDR + 0x2C) -#define STM32G0_FLASH_WRP1BR (STM32G0_FLASH_REGS_ADDR + 0x30) -#define STM32G0_FLASH_PCROP1BSR (STM32G0_FLASH_REGS_ADDR + 0x34) -#define STM32G0_FLASH_PCROP1BER (STM32G0_FLASH_REGS_ADDR + 0x38) -#define STM32G0_FLASH_SECR (STM32G0_FLASH_REGS_ADDR + 0x80) - -// G4 (RM0440 Table 17, sec 3.7.19) -// Mostly the same as STM32G0 chips, but there are a few extra -// registers because 'cat 3' devices can have two Flash banks. -#define STM32G4_FLASH_REGS_ADDR (STM32Gx_FLASH_REGS_ADDR) -#define STM32G4_FLASH_PDKEYR (STM32G4_FLASH_REGS_ADDR + 0x04) -#define STM32G4_FLASH_PCROP1SR (STM32G4_FLASH_REGS_ADDR + 0x24) -#define STM32G4_FLASH_PCROP1ER (STM32G4_FLASH_REGS_ADDR + 0x28) -#define STM32G4_FLASH_WRP1AR (STM32G4_FLASH_REGS_ADDR + 0x2C) -#define STM32G4_FLASH_WRP1BR (STM32G4_FLASH_REGS_ADDR + 0x30) -#define STM32G4_FLASH_PCROP2SR (STM32G4_FLASH_REGS_ADDR + 0x44) -#define STM32G4_FLASH_PCROP2ER (STM32G4_FLASH_REGS_ADDR + 0x48) -#define STM32G4_FLASH_WRP2AR (STM32G4_FLASH_REGS_ADDR + 0x4C) -#define STM32G4_FLASH_WRP2BR (STM32G4_FLASH_REGS_ADDR + 0x50) -#define STM32G4_FLASH_SEC1R (STM32G4_FLASH_REGS_ADDR + 0x70) -#define STM32G4_FLASH_SEC2R (STM32G4_FLASH_REGS_ADDR + 0x74) - -// G0/G4 FLASH control register -#define STM32Gx_FLASH_CR_PG (0) /* Program */ -#define STM32Gx_FLASH_CR_PER (1) /* Page erase */ -#define STM32Gx_FLASH_CR_MER1 (2) /* Mass erase */ -#define STM32Gx_FLASH_CR_PNB (3) /* Page number */ -#define STM32G0_FLASH_CR_PNG_LEN (5) /* STM32G0: 5 page number bits */ -#define STM32G4_FLASH_CR_PNG_LEN (7) /* STM32G4: 7 page number bits */ -#define STM32Gx_FLASH_CR_MER2 (15) /* Mass erase (2nd bank)*/ -#define STM32Gx_FLASH_CR_STRT (16) /* Start */ -#define STM32Gx_FLASH_CR_OPTSTRT \ - (17) /* Start of modification of option bytes */ -#define STM32Gx_FLASH_CR_FSTPG (18) /* Fast programming */ -#define STM32Gx_FLASH_CR_EOPIE (24) /* End of operation interrupt enable */ -#define STM32Gx_FLASH_CR_ERRIE (25) /* Error interrupt enable */ -#define STM32Gx_FLASH_CR_OBL_LAUNCH (27) /* Forces the option byte loading */ -#define STM32Gx_FLASH_CR_OPTLOCK (30) /* Options Lock */ -#define STM32Gx_FLASH_CR_LOCK (31) /* FLASH_CR Lock */ - -// G0/G4 FLASH status register -#define STM32Gx_FLASH_SR_ERROR_MASK (0x3fa) -#define STM32Gx_FLASH_SR_PROGERR (3) -#define STM32Gx_FLASH_SR_WRPERR (4) -#define STM32Gx_FLASH_SR_PGAERR (5) -#define STM32Gx_FLASH_SR_BSY (16) /* FLASH_SR Busy */ -#define STM32Gx_FLASH_SR_EOP (0) /* FLASH_EOP End of Operation */ - -// G4 FLASH option register -#define STM32G4_FLASH_OPTR_DBANK (22) /* FLASH_OPTR Dual Bank Mode */ - -// WB (RM0434) -#define STM32WB_FLASH_REGS_ADDR ((uint32_t)0x58004000) -#define STM32WB_FLASH_ACR (STM32WB_FLASH_REGS_ADDR + 0x00) -#define STM32WB_FLASH_KEYR (STM32WB_FLASH_REGS_ADDR + 0x08) -#define STM32WB_FLASH_OPT_KEYR (STM32WB_FLASH_REGS_ADDR + 0x0C) -#define STM32WB_FLASH_SR (STM32WB_FLASH_REGS_ADDR + 0x10) -#define STM32WB_FLASH_CR (STM32WB_FLASH_REGS_ADDR + 0x14) -#define STM32WB_FLASH_ECCR (STM32WB_FLASH_REGS_ADDR + 0x18) -#define STM32WB_FLASH_OPTR (STM32WB_FLASH_REGS_ADDR + 0x20) -#define STM32WB_FLASH_PCROP1ASR (STM32WB_FLASH_REGS_ADDR + 0x24) -#define STM32WB_FLASH_PCROP1AER (STM32WB_FLASH_REGS_ADDR + 0x28) -#define STM32WB_FLASH_WRP1AR (STM32WB_FLASH_REGS_ADDR + 0x2C) -#define STM32WB_FLASH_WRP1BR (STM32WB_FLASH_REGS_ADDR + 0x30) -#define STM32WB_FLASH_PCROP1BSR (STM32WB_FLASH_REGS_ADDR + 0x34) -#define STM32WB_FLASH_PCROP1BER (STM32WB_FLASH_REGS_ADDR + 0x38) -#define STM32WB_FLASH_IPCCBR (STM32WB_FLASH_REGS_ADDR + 0x3C) -#define STM32WB_FLASH_C2ACR (STM32WB_FLASH_REGS_ADDR + 0x5C) -#define STM32WB_FLASH_C2SR (STM32WB_FLASH_REGS_ADDR + 0x60) -#define STM32WB_FLASH_C2CR (STM32WB_FLASH_REGS_ADDR + 0x64) -#define STM32WB_FLASH_SFR (STM32WB_FLASH_REGS_ADDR + 0x80) -#define STM32WB_FLASH_SRRVR (STM32WB_FLASH_REGS_ADDR + 0x84) - -// WB Flash control register. -#define STM32WB_FLASH_CR_STRT (16) /* Start */ -#define STM32WB_FLASH_CR_OPTLOCK (30) /* Option Lock */ -#define STM32WB_FLASH_CR_LOCK (31) /* Lock */ -// WB Flash status register. -#define STM32WB_FLASH_SR_ERROR_MASK (0x3f8) /* SR [9:3] */ -#define STM32WB_FLASH_SR_PROGERR (3) /* Programming alignment error */ -#define STM32WB_FLASH_SR_WRPERR (4) /* Write protection error */ -#define STM32WB_FLASH_SR_PGAERR (5) /* Programming error */ -#define STM32WB_FLASH_SR_BSY (16) /* Busy */ - -// 32L4 register base is at FLASH_REGS_ADDR (0x40022000) -#define STM32L4_FLASH_KEYR (FLASH_REGS_ADDR + 0x08) -#define STM32L4_FLASH_OPTKEYR (FLASH_REGS_ADDR + 0x0C) -#define STM32L4_FLASH_SR (FLASH_REGS_ADDR + 0x10) -#define STM32L4_FLASH_CR (FLASH_REGS_ADDR + 0x14) -#define STM32L4_FLASH_OPTR (FLASH_REGS_ADDR + 0x20) - -#define STM32L4_FLASH_SR_ERROR_MASK 0x3f8 /* SR [9:3] */ -#define STM32L4_FLASH_SR_PROGERR 3 -#define STM32L4_FLASH_SR_WRPERR 4 -#define STM32L4_FLASH_SR_PGAERR 5 -#define STM32L4_FLASH_SR_BSY 16 - -#define STM32L4_FLASH_CR_LOCK 31 /* Lock control register */ -#define STM32L4_FLASH_CR_OPTLOCK 30 /* Lock option bytes */ -#define STM32L4_FLASH_CR_PG 0 /* Program */ -#define STM32L4_FLASH_CR_PER 1 /* Page erase */ -#define STM32L4_FLASH_CR_MER1 2 /* Bank 1 erase */ -#define STM32L4_FLASH_CR_MER2 15 /* Bank 2 erase */ -#define STM32L4_FLASH_CR_STRT 16 /* Start command */ -#define STM32L4_FLASH_CR_OPTSTRT 17 /* Start writing option bytes */ -#define STM32L4_FLASH_CR_BKER 11 /* Bank select for page erase */ -#define STM32L4_FLASH_CR_PNB 3 /* Page number (8 bits) */ -#define STM32L4_FLASH_CR_OBL_LAUNCH 27 /* Option bytes reload */ -// Bits requesting flash operations (useful when we want to clear them) -#define STM32L4_FLASH_CR_OPBITS \ - (uint32_t)((1lu << STM32L4_FLASH_CR_PG) | (1lu << STM32L4_FLASH_CR_PER) | \ - (1lu << STM32L4_FLASH_CR_MER1) | (1lu << STM32L4_FLASH_CR_MER1)) -// Page is fully specified by BKER and PNB -#define STM32L4_FLASH_CR_PAGEMASK (uint32_t)(0x1fflu << STM32L4_FLASH_CR_PNB) - -#define STM32L4_FLASH_OPTR_DUALBANK 21 - -// STM32L0x flash register base and offsets RM0090 - DM00031020.pdf -#define STM32L0_FLASH_REGS_ADDR ((uint32_t)0x40022000) - -#define STM32L0_FLASH_PELOCK (0) -#define STM32L0_FLASH_OPTLOCK (2) -#define STM32L0_FLASH_OBL_LAUNCH (18) - -#define STM32L0_FLASH_SR_ERROR_MASK 0x00013F00 -#define STM32L0_FLASH_SR_WRPERR 8 -#define STM32L0_FLASH_SR_PGAERR 9 -#define STM32L0_FLASH_SR_NOTZEROERR 16 - -#define FLASH_ACR_OFF ((uint32_t)0x00) -#define FLASH_PECR_OFF ((uint32_t)0x04) -#define FLASH_PDKEYR_OFF ((uint32_t)0x08) -#define FLASH_PEKEYR_OFF ((uint32_t)0x0c) -#define FLASH_PRGKEYR_OFF ((uint32_t)0x10) -#define FLASH_OPTKEYR_OFF ((uint32_t)0x14) -#define FLASH_SR_OFF ((uint32_t)0x18) -#define FLASH_OBR_OFF ((uint32_t)0x1c) -#define FLASH_WRPR_OFF ((uint32_t)0x20) - -// STM32F7 -#define FLASH_F7_REGS_ADDR ((uint32_t)0x40023c00) -#define FLASH_F7_KEYR (FLASH_F7_REGS_ADDR + 0x04) -#define FLASH_F7_OPT_KEYR (FLASH_F7_REGS_ADDR + 0x08) -#define FLASH_F7_SR (FLASH_F7_REGS_ADDR + 0x0c) -#define FLASH_F7_CR (FLASH_F7_REGS_ADDR + 0x10) -#define FLASH_F7_OPTCR (FLASH_F7_REGS_ADDR + 0x14) -#define FLASH_F7_OPTCR1 (FLASH_F7_REGS_ADDR + 0x18) -#define FLASH_F7_OPTCR_LOCK 0 -#define FLASH_F7_OPTCR_START 1 -#define FLASH_F7_CR_STRT 16 -#define FLASH_F7_CR_LOCK 31 -#define FLASH_F7_CR_SER 1 -#define FLASH_F7_CR_SNB 3 -#define FLASH_F7_CR_SNB_MASK 0xf8 -#define FLASH_F7_SR_BSY 16 -#define FLASH_F7_SR_ERS_ERR 7 /* Erase Sequence Error */ -#define FLASH_F7_SR_PGP_ERR 6 /* Programming parallelism error */ -#define FLASH_F7_SR_PGA_ERR 5 /* Programming alignment error */ -#define FLASH_F7_SR_WRP_ERR 4 /* Write protection error */ -#define FLASH_F7_SR_OP_ERR 1 /* Operation error */ -#define FLASH_F7_SR_EOP 0 /* End of operation */ -#define FLASH_F7_OPTCR1_BOOT_ADD0 0 -#define FLASH_F7_OPTCR1_BOOT_ADD1 16 - -#define FLASH_F7_SR_ERROR_MASK \ - ((1 << FLASH_F7_SR_ERS_ERR) | (1 << FLASH_F7_SR_PGP_ERR) | \ - (1 << FLASH_F7_SR_PGA_ERR) | (1 << FLASH_F7_SR_WRP_ERR) | \ - (1 << FLASH_F7_SR_OP_ERR)) - -// STM32F4 -#define FLASH_F4_REGS_ADDR ((uint32_t)0x40023c00) -#define FLASH_F4_KEYR (FLASH_F4_REGS_ADDR + 0x04) -#define FLASH_F4_OPT_KEYR (FLASH_F4_REGS_ADDR + 0x08) -#define FLASH_F4_SR (FLASH_F4_REGS_ADDR + 0x0c) -#define FLASH_F4_CR (FLASH_F4_REGS_ADDR + 0x10) -#define FLASH_F4_OPTCR (FLASH_F4_REGS_ADDR + 0x14) -#define FLASH_F4_OPTCR_LOCK 0 -#define FLASH_F4_OPTCR_START 1 -#define FLASH_F4_CR_STRT 16 -#define FLASH_F4_CR_LOCK 31 -#define FLASH_F4_CR_SER 1 -#define FLASH_F4_CR_SNB 3 -#define FLASH_F4_CR_SNB_MASK 0xf8 -#define FLASH_F4_SR_ERROR_MASK 0x000000F0 -#define FLASH_F4_SR_PGAERR 5 -#define FLASH_F4_SR_WRPERR 4 -#define FLASH_F4_SR_BSY 16 - -// STM32F2 -#define FLASH_F2_REGS_ADDR ((uint32_t)0x40023c00) -#define FLASH_F2_KEYR (FLASH_F2_REGS_ADDR + 0x04) -#define FLASH_F2_OPT_KEYR (FLASH_F2_REGS_ADDR + 0x08) -#define FLASH_F2_SR (FLASH_F2_REGS_ADDR + 0x0c) -#define FLASH_F2_CR (FLASH_F2_REGS_ADDR + 0x10) -#define FLASH_F2_OPT_CR (FLASH_F2_REGS_ADDR + 0x14) -#define FLASH_F2_OPT_LOCK_BIT (1u << 0) -#define FLASH_F2_CR_STRT 16 -#define FLASH_F2_CR_LOCK 31 - -#define FLASH_F2_CR_SER 1 -#define FLASH_F2_CR_SNB 3 -#define FLASH_F2_CR_SNB_MASK 0x78 -#define FLASH_F2_SR_BSY 16 - -// STM32H7xx -#define FLASH_H7_CR_LOCK 0 -#define FLASH_H7_CR_PG 1 -#define FLASH_H7_CR_SER 2 -#define FLASH_H7_CR_BER 3 -#define FLASH_H7_CR_PSIZE 4 -#define FLASH_H7_CR_START(chipid) (chipid == STLINK_CHIPID_STM32_H7Ax ? 5 : 7) -#define FLASH_H7_CR_SNB 8 -#define FLASH_H7_CR_SNB_MASK 0x700 - -#define FLASH_H7_SR_QW 2 -#define FLASH_H7_SR_WRPERR 17 -#define FLASH_H7_SR_PGSERR 18 -#define FLASH_H7_SR_STRBERR 19 -#define FLASH_H7_SR_ERROR_MASK \ - ((1 << FLASH_H7_SR_PGSERR) | (1 << FLASH_H7_SR_STRBERR) | \ - (1 << FLASH_H7_SR_WRPERR)) - -#define FLASH_H7_OPTCR_OPTLOCK 0 -#define FLASH_H7_OPTCR_OPTSTART 1 -#define FLASH_H7_OPTCR_MER 4 - -#define FLASH_H7_OPTSR_OPT_BUSY 0 -#define FLASH_H7_OPTSR_OPTCHANGEERR 30 - -#define FLASH_H7_OPTCCR_CLR_OPTCHANGEERR 30 - -#define FLASH_H7_REGS_ADDR ((uint32_t)0x52002000) -#define FLASH_H7_KEYR1 (FLASH_H7_REGS_ADDR + 0x04) -#define FLASH_H7_KEYR2 (FLASH_H7_REGS_ADDR + 0x104) -#define FLASH_H7_OPT_KEYR (FLASH_H7_REGS_ADDR + 0x08) -#define FLASH_H7_OPT_KEYR2 (FLASH_H7_REGS_ADDR + 0x108) -#define FLASH_H7_CR1 (FLASH_H7_REGS_ADDR + 0x0c) -#define FLASH_H7_CR2 (FLASH_H7_REGS_ADDR + 0x10c) -#define FLASH_H7_SR1 (FLASH_H7_REGS_ADDR + 0x10) -#define FLASH_H7_SR2 (FLASH_H7_REGS_ADDR + 0x110) -#define FLASH_H7_CCR1 (FLASH_H7_REGS_ADDR + 0x14) -#define FLASH_H7_CCR2 (FLASH_H7_REGS_ADDR + 0x114) -#define FLASH_H7_OPTCR (FLASH_H7_REGS_ADDR + 0x18) -#define FLASH_H7_OPTCR2 (FLASH_H7_REGS_ADDR + 0x118) -#define FLASH_H7_OPTSR_CUR (FLASH_H7_REGS_ADDR + 0x1c) -#define FLASH_H7_OPTCCR (FLASH_H7_REGS_ADDR + 0x24) - -#define STM32F0_DBGMCU_CR 0xE0042004 -#define STM32F0_DBGMCU_CR_IWDG_STOP 8 -#define STM32F0_DBGMCU_CR_WWDG_STOP 9 - -#define STM32F4_DBGMCU_APB1FZR1 0xE0042008 -#define STM32F4_DBGMCU_APB1FZR1_WWDG_STOP 11 -#define STM32F4_DBGMCU_APB1FZR1_IWDG_STOP 12 - -#define STM32L0_DBGMCU_APB1_FZ 0x40015808 -#define STM32L0_DBGMCU_APB1_FZ_WWDG_STOP 11 -#define STM32L0_DBGMCU_APB1_FZ_IWDG_STOP 12 - -#define STM32H7_DBGMCU_APB1HFZ 0x5C001054 -#define STM32H7_DBGMCU_APB1HFZ_IWDG_STOP 18 - -#define STM32WB_DBGMCU_APB1FZR1 0xE004203C -#define STM32WB_DBGMCU_APB1FZR1_WWDG_STOP 11 -#define STM32WB_DBGMCU_APB1FZR1_IWDG_STOP 12 - -#define STM32F1_RCC_AHBENR 0x40021014 -#define STM32F1_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN - -#define STM32F4_RCC_AHB1ENR 0x40023830 -#define STM32F4_RCC_DMAEN 0x00600000 // DMA2EN | DMA1EN - -#define STM32G0_RCC_AHBENR 0x40021038 -#define STM32G0_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN - -#define STM32G4_RCC_AHB1ENR 0x40021048 -#define STM32G4_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN - -#define STM32L0_RCC_AHBENR 0x40021030 -#define STM32L0_RCC_DMAEN 0x00000001 // DMAEN - -#define STM32H7_RCC_AHB1ENR 0x58024538 -#define STM32H7_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN - -#define STM32WB_RCC_AHB1ENR 0x58000048 -#define STM32WB_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN - -#define L1_WRITE_BLOCK_SIZE 0x80 -#define L0_WRITE_BLOCK_SIZE 0x40 - -// Endianness -// https://commandcenter.blogspot.com/2012/04/byte-order-fallacy.html -// These functions encode and decode little endian uint16 and uint32 values. - -void write_uint32(unsigned char *buf, uint32_t ui) { - buf[0] = ui; - buf[1] = ui >> 8; - buf[2] = ui >> 16; - buf[3] = ui >> 24; -} +// Private structs and functions defines +struct stlink_fread_worker_arg { + int fd; +}; -void write_uint16(unsigned char *buf, uint16_t ui) { - buf[0] = (uint8_t)ui; - buf[1] = (uint8_t)(ui >> 8); -} +struct stlink_fread_ihex_worker_arg { + FILE *file; + uint32_t addr; + uint32_t lba; + uint8_t buf[16]; + uint8_t buf_pos; +}; -uint32_t read_uint32(const unsigned char *c, const int pt) { - return ((uint32_t)c[pt]) | ((uint32_t)c[pt + 1] << 8) | - ((uint32_t)c[pt + 2] << 16) | ((uint32_t)c[pt + 3] << 24); -} +typedef bool (*save_block_fn)(void *arg, uint8_t *block, ssize_t len); -uint16_t read_uint16(const unsigned char *c, const int pt) { - return ((uint16_t)c[pt]) | ((uint16_t)c[pt + 1] << 8); -} +static void stop_wdg_in_debug(stlink_t *); +int stlink_jtag_reset(stlink_t *, int); +int stlink_soft_reset(stlink_t *, int); +void _parse_version(stlink_t *, stlink_version_t *); +static uint8_t stlink_parse_hex(const char *); +static int stlink_read(stlink_t *, stm32_addr_t, size_t, save_block_fn, void *); +static bool stlink_fread_ihex_init(struct stlink_fread_ihex_worker_arg *, int, stm32_addr_t); +static bool stlink_fread_ihex_worker(void *, uint8_t *, ssize_t); +static bool stlink_fread_ihex_finalize(struct stlink_fread_ihex_worker_arg *); +static bool stlink_fread_worker(void *, uint8_t *, ssize_t); +// End of private structs and functions defines + +// Functions below are defined in stlink.h (see line num before function) +// 252 +void stlink_close(stlink_t *sl) { + DLOG("*** stlink_close ***\n"); -static uint32_t get_stm32l0_flash_base(stlink_t *sl) { - switch (sl->chip_id) { - case STLINK_CHIPID_STM32_L0: - case STLINK_CHIPID_STM32_L0_CAT5: - case STLINK_CHIPID_STM32_L0_CAT2: - case STLINK_CHIPID_STM32_L011: - return (STM32L0_FLASH_REGS_ADDR); + if (!sl) { + return; + } - case STLINK_CHIPID_STM32_L1_CAT2: - case STLINK_CHIPID_STM32_L1_MD: - case STLINK_CHIPID_STM32_L1_MD_PLUS: - case STLINK_CHIPID_STM32_L1_MD_PLUS_HD: - return (STM32L_FLASH_REGS_ADDR); + sl->backend->close(sl); + free(sl); +} +// 250 +int stlink_exit_debug_mode(stlink_t *sl) { + DLOG("*** stlink_exit_debug_mode ***\n"); - default: - WLOG("Flash base use default L0 address\n"); - return (STM32L0_FLASH_REGS_ADDR); + if (sl->flash_type != STLINK_FLASH_TYPE_UNKNOWN && + sl->core_stat != TARGET_RESET) { + // stop debugging if the target has been identified + stlink_write_debug32(sl, STLINK_REG_DHCSR, STLINK_REG_DHCSR_DBGKEY); } -} -static uint32_t __attribute__((unused)) read_flash_rdp(stlink_t *sl) { - uint32_t rdp; - stlink_read_debug32(sl, FLASH_WRPR, &rdp); - return (rdp & 0xff); + return (sl->backend->exit_debug_mode(sl)); } - -static inline uint32_t read_flash_cr(stlink_t *sl, unsigned bank) { - uint32_t reg, res; - - if (sl->flash_type == STLINK_FLASH_TYPE_F4) { - reg = FLASH_F4_CR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { - reg = FLASH_F7_CR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { - reg = STM32L4_FLASH_CR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { - reg = STM32Gx_FLASH_CR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { - reg = STM32WB_FLASH_CR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { - reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; - } else { - reg = (bank == BANK_1) ? FLASH_CR : FLASH_CR2; +//248 +int stlink_enter_swd_mode(stlink_t *sl) { + DLOG("*** stlink_enter_swd_mode ***\n"); + return (sl->backend->enter_swd_mode(sl)); +} +// 271 +// Force the core into the debug mode -> halted state. +int stlink_force_debug(stlink_t *sl) { + DLOG("*** stlink_force_debug_mode ***\n"); + int res = sl->backend->force_debug(sl); + if (res) { + return (res); } + // Stop the watchdogs in the halted state for suppress target reboot + stop_wdg_in_debug(sl); + return (0); +} +// 251 +int stlink_exit_dfu_mode(stlink_t *sl) { + DLOG("*** stlink_exit_dfu_mode ***\n"); + return (sl->backend->exit_dfu_mode(sl)); +} +// 253 +int stlink_core_id(stlink_t *sl) { + int ret; - stlink_read_debug32(sl, reg, &res); + DLOG("*** stlink_core_id ***\n"); + ret = sl->backend->core_id(sl); -#if DEBUG_FLASH - fprintf(stdout, "CR:0x%x\n", res); -#endif - return (res); -} + if (ret == -1) { + ELOG("Failed to read core_id\n"); + return (ret); + } -static inline unsigned int is_flash_locked(stlink_t *sl) { - /* return non zero for true */ - uint32_t cr_lock_shift; - uint32_t cr_reg; - uint32_t n; - - if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || - (sl->flash_type == STLINK_FLASH_TYPE_F1_XL)) { - cr_reg = FLASH_CR; - cr_lock_shift = FLASH_CR_LOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F4) { - cr_reg = FLASH_F4_CR; - cr_lock_shift = FLASH_F4_CR_LOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { - cr_reg = FLASH_F7_CR; - cr_lock_shift = FLASH_F7_CR_LOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { - cr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF; - cr_lock_shift = STM32L0_FLASH_PELOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { - cr_reg = STM32L4_FLASH_CR; - cr_lock_shift = STM32L4_FLASH_CR_LOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { - cr_reg = STM32Gx_FLASH_CR; - cr_lock_shift = STM32Gx_FLASH_CR_LOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { - cr_reg = STM32WB_FLASH_CR; - cr_lock_shift = STM32WB_FLASH_CR_LOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { - cr_reg = FLASH_H7_CR1; - cr_lock_shift = FLASH_H7_CR_LOCK; - } else { - ELOG("unsupported flash method, abort\n"); - return (-1); + if (sl->verbose > 2) { + stlink_print_data(sl); } - stlink_read_debug32(sl, cr_reg, &n); - return (n & (1u << cr_lock_shift)); + DLOG("core_id = 0x%08x\n", sl->core_id); + return (ret); } +// 287 +// stlink_chip_id() is called by stlink_load_device_params() +// do not call this procedure directly. +int stlink_chip_id(stlink_t *sl, uint32_t *chip_id) { + int ret; + cortex_m3_cpuid_t cpu_id; -static void unlock_flash(stlink_t *sl) { - uint32_t key_reg, key2_reg = 0; - uint32_t flash_key1 = FLASH_KEY1; - uint32_t flash_key2 = FLASH_KEY2; - /* The unlock sequence consists of 2 write cycles where 2 key values are - * written to the FLASH_KEYR register. An invalid sequence results in a - * definitive lock of the FPEC block until next reset. - */ - - if (sl->flash_type == STLINK_FLASH_TYPE_F0) { - key_reg = FLASH_KEYR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL) { - key_reg = FLASH_KEYR; - key2_reg = FLASH_KEYR2; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F4) { - key_reg = FLASH_F4_KEYR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { - key_reg = FLASH_F7_KEYR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { - key_reg = get_stm32l0_flash_base(sl) + FLASH_PEKEYR_OFF; - flash_key1 = FLASH_L0_PEKEY1; - flash_key2 = FLASH_L0_PEKEY2; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { - key_reg = STM32L4_FLASH_KEYR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { - key_reg = STM32Gx_FLASH_KEYR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { - key_reg = STM32WB_FLASH_KEYR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { - key_reg = FLASH_H7_KEYR1; - if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { - key2_reg = FLASH_H7_KEYR2; - } - } else { - ELOG("unsupported flash method, abort\n"); - return; + // Read the CPU ID to determine where to read the core id + if (stlink_cpu_id(sl, &cpu_id) || + cpu_id.implementer_id != STLINK_REG_CMx_CPUID_IMPL_ARM) { + ELOG("Can not connect to target. Please use \'connect under reset\' and " + "try again\n"); + return -1; } - stlink_write_debug32(sl, key_reg, flash_key1); - stlink_write_debug32(sl, key_reg, flash_key2); + /* + * the chip_id register in the reference manual have + * DBGMCU_IDCODE / DBG_IDCODE name + * + */ + + if ((sl->core_id == STM32H7_CORE_ID || sl->core_id == STM32H7_CORE_ID_JTAG) && + cpu_id.part == STLINK_REG_CMx_CPUID_PARTNO_CM7) { + // STM32H7 chipid in 0x5c001000 (RM0433 pg3189) + ret = stlink_read_debug32(sl, 0x5c001000, chip_id); + } else if (cpu_id.part == STLINK_REG_CMx_CPUID_PARTNO_CM0 || + cpu_id.part == STLINK_REG_CMx_CPUID_PARTNO_CM0P) { + // STM32F0 (RM0091, pg914; RM0360, pg713) + // STM32L0 (RM0377, pg813; RM0367, pg915; RM0376, pg917) + // STM32G0 (RM0444, pg1367) + ret = stlink_read_debug32(sl, 0x40015800, chip_id); + } else if (cpu_id.part == STLINK_REG_CMx_CPUID_PARTNO_CM33) { + // STM32L5 (RM0438, pg2157) + ret = stlink_read_debug32(sl, 0xE0044000, chip_id); + } else /* СM3, СM4, CM7 */ { + // default chipid address - if (key2_reg) { - stlink_write_debug32(sl, key2_reg, flash_key1); - stlink_write_debug32(sl, key2_reg, flash_key2); + // STM32F1 (RM0008, pg1087; RM0041, pg681) + // STM32F2 (RM0033, pg1326) + // STM32F3 (RM0316, pg1095; RM0313, pg874) + // STM32F7 (RM0385, pg1676; RM0410, pg1912) + // STM32L1 (RM0038, pg861) + // STM32L4 (RM0351, pg1840; RM0394, pg1560) + // STM32G4 (RM0440, pg2086) + // STM32WB (RM0434, pg1406) + ret = stlink_read_debug32(sl, 0xE0042000, chip_id); } -} -/* unlock flash if already locked */ -static int unlock_flash_if(stlink_t *sl) { - if (is_flash_locked(sl)) { - unlock_flash(sl); + if (ret || !(*chip_id)) { + *chip_id = 0; + ret = ret?ret:-1; + ELOG("Could not find chip id!\n"); + } else { + *chip_id = (*chip_id) & 0xfff; - if (is_flash_locked(sl)) { - WLOG("Failed to unlock flash!\n"); - return (-1); + // Fix chip_id for F4 rev A errata, read CPU ID, as CoreID is the same for + // F2/F4 + if (*chip_id == 0x411 && cpu_id.part == STLINK_REG_CMx_CPUID_PARTNO_CM4) { + *chip_id = 0x413; } } - DLOG("Successfully unlocked flash\n"); - return (0); + return (ret); } +// 288 +/** + * Cortex M tech ref manual, CPUID register description + * @param sl stlink context + * @param cpuid pointer to the result object + */ +int stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid) { + uint32_t raw; -static void lock_flash(stlink_t *sl) { - uint32_t cr_lock_shift, cr_reg, n, cr2_reg = 0; - uint32_t cr_mask = 0xffffffffu; - - if (sl->flash_type == STLINK_FLASH_TYPE_F0) { - cr_reg = FLASH_CR; - cr_lock_shift = FLASH_CR_LOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL) { - cr_reg = FLASH_CR; - cr2_reg = FLASH_CR2; - cr_lock_shift = FLASH_CR_LOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F4) { - cr_reg = FLASH_F4_CR; - cr_lock_shift = FLASH_F4_CR_LOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { - cr_reg = FLASH_F7_CR; - cr_lock_shift = FLASH_F7_CR_LOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { - cr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF; - cr_lock_shift = STM32L0_FLASH_PELOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { - cr_reg = STM32L4_FLASH_CR; - cr_lock_shift = STM32L4_FLASH_CR_LOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { - cr_reg = STM32Gx_FLASH_CR; - cr_lock_shift = STM32Gx_FLASH_CR_LOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { - cr_reg = STM32WB_FLASH_CR; - cr_lock_shift = STM32WB_FLASH_CR_LOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { - cr_reg = FLASH_H7_CR1; - if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { - cr2_reg = FLASH_H7_CR2; - } - cr_lock_shift = FLASH_H7_CR_LOCK; - cr_mask = ~(1u << FLASH_H7_CR_SER); - } else { - ELOG("unsupported flash method, abort\n"); - return; + if (stlink_read_debug32(sl, STLINK_REG_CM3_CPUID, &raw)) { + cpuid->implementer_id = 0; + cpuid->variant = 0; + cpuid->part = 0; + cpuid->revision = 0; + return (-1); } - stlink_read_debug32(sl, cr_reg, &n); - n &= cr_mask; - n |= (1u << cr_lock_shift); - stlink_write_debug32(sl, cr_reg, n); - - if (cr2_reg) { - n = read_flash_cr(sl, BANK_2) | (1u << cr_lock_shift); - stlink_write_debug32(sl, cr2_reg, n); - } + cpuid->implementer_id = (raw >> 24) & 0x7f; + cpuid->variant = (raw >> 20) & 0xf; + cpuid->part = (raw >> 4) & 0xfff; + cpuid->revision = raw & 0xf; + return (0); } +// 303 +/** + * Reads and decodes the flash parameters, as dynamically as possible + * @param sl + * @return 0 for success, or -1 for unsupported core type. + */ +int stlink_load_device_params(stlink_t *sl) { + // This seems to normally work so is unnecessary info for a normal user. + // Demoted to debug. -- REW + DLOG("Loading device parameters....\n"); + const struct stlink_chipid_params *params = NULL; + stlink_core_id(sl); + uint32_t flash_size; -static bool is_flash_option_locked(stlink_t *sl) { - uint32_t optlock_shift, optcr_reg; - int active_bit_level = 1; - uint32_t n; - - switch (sl->flash_type) { - case STLINK_FLASH_TYPE_F0: - case STLINK_FLASH_TYPE_F1_XL: - optcr_reg = FLASH_CR; - optlock_shift = FLASH_CR_OPTWRE; - active_bit_level = 0; /* bit is "option write enable", not lock */ - break; - case STLINK_FLASH_TYPE_F4: - optcr_reg = FLASH_F4_OPTCR; - optlock_shift = FLASH_F4_OPTCR_LOCK; - break; - case STLINK_FLASH_TYPE_F7: - optcr_reg = FLASH_F7_OPTCR; - optlock_shift = FLASH_F7_OPTCR_LOCK; - break; - case STLINK_FLASH_TYPE_L0: - optcr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF; - optlock_shift = STM32L0_FLASH_OPTLOCK; - break; - case STLINK_FLASH_TYPE_L4: - optcr_reg = STM32L4_FLASH_CR; - optlock_shift = STM32L4_FLASH_CR_OPTLOCK; - break; - case STLINK_FLASH_TYPE_G0: - case STLINK_FLASH_TYPE_G4: - optcr_reg = STM32Gx_FLASH_CR; - optlock_shift = STM32Gx_FLASH_CR_OPTLOCK; - break; - case STLINK_FLASH_TYPE_WB: - optcr_reg = STM32WB_FLASH_CR; - optlock_shift = STM32WB_FLASH_CR_OPTLOCK; - break; - case STLINK_FLASH_TYPE_H7: - optcr_reg = FLASH_H7_OPTCR; - optlock_shift = FLASH_H7_OPTCR_OPTLOCK; - break; - default: - ELOG("unsupported flash method, abort\n"); - return -1; + if (stlink_chip_id(sl, &sl->chip_id)) { + return (-1); } - stlink_read_debug32(sl, optcr_reg, &n); + params = stlink_chipid_get_params(sl->chip_id); - if (active_bit_level == 0) { - return (!(n & (1u << optlock_shift))); + if (params == NULL) { + WLOG("unknown chip id! %#x\n", sl->chip_id); + return (-1); } - return (n & (1u << optlock_shift)); -} - -static int lock_flash_option(stlink_t *sl) { - uint32_t optlock_shift, optcr_reg, n, optcr2_reg = 0; - int active_bit_level = 1; - - switch (sl->flash_type) { - case STLINK_FLASH_TYPE_F0: - case STLINK_FLASH_TYPE_F1_XL: - optcr_reg = FLASH_CR; - optlock_shift = FLASH_CR_OPTWRE; - active_bit_level = 0; - break; - case STLINK_FLASH_TYPE_F4: - optcr_reg = FLASH_F4_OPTCR; - optlock_shift = FLASH_F4_OPTCR_LOCK; - break; - case STLINK_FLASH_TYPE_F7: - optcr_reg = FLASH_F7_OPTCR; - optlock_shift = FLASH_F7_OPTCR_LOCK; - break; - case STLINK_FLASH_TYPE_L0: - optcr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF; - optlock_shift = STM32L0_FLASH_OPTLOCK; - break; - case STLINK_FLASH_TYPE_L4: - optcr_reg = STM32L4_FLASH_CR; - optlock_shift = STM32L4_FLASH_CR_OPTLOCK; - break; - case STLINK_FLASH_TYPE_G0: - case STLINK_FLASH_TYPE_G4: - optcr_reg = STM32Gx_FLASH_CR; - optlock_shift = STM32Gx_FLASH_CR_OPTLOCK; - break; - case STLINK_FLASH_TYPE_WB: - optcr_reg = STM32WB_FLASH_CR; - optlock_shift = STM32WB_FLASH_CR_OPTLOCK; - break; - case STLINK_FLASH_TYPE_H7: - optcr_reg = FLASH_H7_OPTCR; - optlock_shift = FLASH_H7_OPTCR_OPTLOCK; - if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) - optcr2_reg = FLASH_H7_OPTCR2; - break; - default: - ELOG("unsupported flash method, abort\n"); - return -1; + if (params->flash_type == STLINK_FLASH_TYPE_UNKNOWN) { + WLOG("Invalid flash type, please check device declaration\n"); + sl->flash_size = 0; + return (0); } - stlink_read_debug32(sl, optcr_reg, &n); + // These are fixed... + sl->flash_base = STM32_FLASH_BASE; + sl->sram_base = STM32_SRAM_BASE; + stlink_read_debug32(sl, (params->flash_size_reg) & ~3, &flash_size); - if (active_bit_level == 0) { - n &= ~(1u << optlock_shift); - } else { - n |= (1u << optlock_shift); + if (params->flash_size_reg & 2) { + flash_size = flash_size >> 16; } - stlink_write_debug32(sl, optcr_reg, n); - - if (optcr2_reg) { - stlink_read_debug32(sl, optcr2_reg, &n); + flash_size = flash_size & 0xffff; - if (active_bit_level == 0) { - n &= ~(1u << optlock_shift); + if ((sl->chip_id == STLINK_CHIPID_STM32_L1_MD || + sl->chip_id == STLINK_CHIPID_STM32_F1_VL_MD_LD || + sl->chip_id == STLINK_CHIPID_STM32_L1_MD_PLUS) && + (flash_size == 0)) { + sl->flash_size = 128 * 1024; + } else if (sl->chip_id == STLINK_CHIPID_STM32_L1_CAT2) { + sl->flash_size = (flash_size & 0xff) * 1024; + } else if ((sl->chip_id & 0xFFF) == STLINK_CHIPID_STM32_L1_MD_PLUS_HD) { + // 0 is 384k and 1 is 256k + if (flash_size == 0) { + sl->flash_size = 384 * 1024; } else { - n |= (1u << optlock_shift); + sl->flash_size = 256 * 1024; } - - stlink_write_debug32(sl, optcr2_reg, n); + } else { + sl->flash_size = flash_size * 1024; } - return (0); -} - -static int unlock_flash_option(stlink_t *sl) { - uint32_t optkey_reg, optkey2_reg = 0; - uint32_t optkey1 = FLASH_OPTKEY1; - uint32_t optkey2 = FLASH_OPTKEY2; - - switch (sl->flash_type) { - case STLINK_FLASH_TYPE_F0: - case STLINK_FLASH_TYPE_F1_XL: - optkey_reg = FLASH_OPTKEYR; - optkey1 = FLASH_F0_OPTKEY1; - optkey2 = FLASH_F0_OPTKEY2; - break; - case STLINK_FLASH_TYPE_F4: - optkey_reg = FLASH_F4_OPT_KEYR; - break; - case STLINK_FLASH_TYPE_F7: - optkey_reg = FLASH_F7_OPT_KEYR; - break; - case STLINK_FLASH_TYPE_L0: - optkey_reg = get_stm32l0_flash_base(sl) + FLASH_OPTKEYR_OFF; - optkey1 = FLASH_L0_OPTKEY1; - optkey2 = FLASH_L0_OPTKEY2; - break; - case STLINK_FLASH_TYPE_L4: - optkey_reg = STM32L4_FLASH_OPTKEYR; - break; - case STLINK_FLASH_TYPE_G0: - case STLINK_FLASH_TYPE_G4: - optkey_reg = STM32Gx_FLASH_OPTKEYR; - break; - case STLINK_FLASH_TYPE_WB: - optkey_reg = STM32WB_FLASH_OPT_KEYR; - break; - case STLINK_FLASH_TYPE_H7: - optkey_reg = FLASH_H7_OPT_KEYR; - if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) - optkey2_reg = FLASH_H7_OPT_KEYR2; - break; - default: - ELOG("unsupported flash method, abort\n"); - return (-1); - } - - stlink_write_debug32(sl, optkey_reg, optkey1); - stlink_write_debug32(sl, optkey_reg, optkey2); + sl->flash_type = params->flash_type; + sl->flash_pgsz = params->flash_pagesize; + sl->sram_size = params->sram_size; + sl->sys_base = params->bootrom_base; + sl->sys_size = params->bootrom_size; + sl->option_base = params->option_base; + sl->option_size = params->option_size; + sl->chip_flags = params->flags; - if (optkey2_reg) { - stlink_write_debug32(sl, optkey2_reg, optkey1); - stlink_write_debug32(sl, optkey2_reg, optkey2); + // medium and low devices have the same chipid. ram size depends on flash + // size. STM32F100xx datasheet Doc ID 16455 Table 2 + if (sl->chip_id == STLINK_CHIPID_STM32_F1_VL_MD_LD && + sl->flash_size < 64 * 1024) { + sl->sram_size = 0x1000; } - return (0); -} + if (sl->chip_id == STLINK_CHIPID_STM32_G4_CAT3) { + uint32_t flash_optr; + stlink_read_debug32(sl, STM32Gx_FLASH_OPTR, &flash_optr); -static int unlock_flash_option_if(stlink_t *sl) { - if (is_flash_option_locked(sl)) { - if (unlock_flash_option(sl)) { - ELOG("Could not unlock flash option!\n"); - return (-1); + if (!(flash_optr & (1 << STM32G4_FLASH_OPTR_DBANK))) { + sl->flash_pgsz <<= 1; } + } - if (is_flash_option_locked(sl)) { - ELOG("Failed to unlock flash option!\n"); - return (-1); - } + // H7 devices with small flash has one bank + if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK && + sl->flash_type == STLINK_FLASH_TYPE_H7) { + if ((sl->flash_size / sl->flash_pgsz) <= 1) + sl->chip_flags &= ~CHIP_F_HAS_DUAL_BANK; } - DLOG("Successfully unlocked flash option\n"); + ILOG("%s: %u KiB SRAM, %u KiB flash in at least %u %s pages.\n", + params->description, (unsigned)(sl->sram_size / 1024), + (unsigned)(sl->flash_size / 1024), + (sl->flash_pgsz < 1024) ? (unsigned)(sl->flash_pgsz) + : (unsigned)(sl->flash_pgsz / 1024), + (sl->flash_pgsz < 1024) ? "byte" : "KiB"); + return (0); } +// 254 +int stlink_reset(stlink_t *sl, enum reset_type type) { + uint32_t dhcsr; + unsigned timeout; -static void set_flash_cr_pg(stlink_t *sl, unsigned bank) { - uint32_t cr_reg, x; - - x = read_flash_cr(sl, bank); - - if (sl->flash_type == STLINK_FLASH_TYPE_F4) { - cr_reg = FLASH_F4_CR; - x |= 1 << FLASH_CR_PG; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { - cr_reg = FLASH_F7_CR; - x |= 1 << FLASH_CR_PG; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { - cr_reg = STM32L4_FLASH_CR; - x &= ~STM32L4_FLASH_CR_OPBITS; - x |= (1 << STM32L4_FLASH_CR_PG); - } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { - cr_reg = STM32Gx_FLASH_CR; - x |= (1 << FLASH_CR_PG); - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { - cr_reg = STM32WB_FLASH_CR; - x |= (1 << FLASH_CR_PG); - } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { - cr_reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; - x |= (1 << FLASH_H7_CR_PG); - } else { - cr_reg = FLASH_CR; - x = (1 << FLASH_CR_PG); - } + DLOG("*** stlink_reset ***\n"); - stlink_write_debug32(sl, cr_reg, x); -} + sl->core_stat = TARGET_RESET; -static void clear_flash_cr_pg(stlink_t *sl, unsigned bank) { - uint32_t cr_reg, n; - uint32_t bit = FLASH_CR_PG; - - if (sl->flash_type == STLINK_FLASH_TYPE_F4) { - cr_reg = FLASH_F4_CR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { - cr_reg = FLASH_F7_CR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { - cr_reg = STM32L4_FLASH_CR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { - cr_reg = STM32Gx_FLASH_CR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { - cr_reg = STM32WB_FLASH_CR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { - cr_reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; - bit = FLASH_H7_CR_PG; - } else { - cr_reg = FLASH_CR; + if (type == RESET_AUTO) { + // clear S_RESET_ST in DHCSR register for reset state detection + stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); } - n = read_flash_cr(sl, bank) & ~(1 << bit); - stlink_write_debug32(sl, cr_reg, n); -} - -static void set_flash_cr_per(stlink_t *sl, unsigned bank) { - uint32_t cr_reg, val; - - if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { - cr_reg = STM32Gx_FLASH_CR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { - cr_reg = STM32WB_FLASH_CR; - } else { - cr_reg = (bank == BANK_1) ? FLASH_CR : FLASH_CR2; + if (type == RESET_HARD || type == RESET_AUTO) { + // hardware target reset + if (sl->version.stlink_v > 1) { + stlink_jtag_reset(sl, STLINK_DEBUG_APIV2_DRIVE_NRST_LOW); + // minimum reset pulse duration of 20 us (RM0008, 8.1.2 Power reset) + usleep(100); + stlink_jtag_reset(sl, STLINK_DEBUG_APIV2_DRIVE_NRST_HIGH); + } + sl->backend->reset(sl); + usleep(10000); } - stlink_read_debug32(sl, cr_reg, &val); - val |= (1 << FLASH_CR_PER); - stlink_write_debug32(sl, cr_reg, val); -} - -static void clear_flash_cr_per(stlink_t *sl, unsigned bank) { - uint32_t cr_reg; + if (type == RESET_AUTO) { + /* Check if the S_RESET_ST bit is set in DHCSR + * This means that a reset has occurred + * DDI0337E, p. 10-4, Debug Halting Control and Status Register */ - if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { - cr_reg = STM32Gx_FLASH_CR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { - cr_reg = STM32WB_FLASH_CR; - } else { - cr_reg = (bank == BANK_1) ? FLASH_CR : FLASH_CR2; - } + dhcsr = 0; + int res = stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); + if ((dhcsr & STLINK_REG_DHCSR_S_RESET_ST) == 0 && !res) { + // reset not done yet + // try reset through AIRCR so that NRST does not need to be connected - const uint32_t n = read_flash_cr(sl, bank) & ~(1 << FLASH_CR_PER); - stlink_write_debug32(sl, cr_reg, n); -} + WLOG("NRST is not connected\n"); + DLOG("Using reset through SYSRESETREQ\n"); + return stlink_soft_reset(sl, 0); + } -static void set_flash_cr_mer(stlink_t *sl, bool v, unsigned bank) { - uint32_t val, cr_reg, cr_mer, cr_pg; - - if (sl->flash_type == STLINK_FLASH_TYPE_F4) { - cr_reg = FLASH_F4_CR; - cr_mer = 1 << FLASH_CR_MER; - cr_pg = 1 << FLASH_CR_PG; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { - cr_reg = FLASH_F7_CR; - cr_mer = 1 << FLASH_CR_MER; - cr_pg = 1 << FLASH_CR_PG; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { - cr_reg = STM32L4_FLASH_CR; - cr_mer = (1 << STM32L4_FLASH_CR_MER1) | (1 << STM32L4_FLASH_CR_MER2); - cr_pg = (1 << STM32L4_FLASH_CR_PG); - } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { - cr_reg = STM32Gx_FLASH_CR; - cr_mer = (1 << STM32Gx_FLASH_CR_MER1); - - if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { - cr_mer |= (1 << STM32Gx_FLASH_CR_MER2); + // waiting for reset the S_RESET_ST bit within 500ms + timeout = time_ms() + 500; + while (time_ms() < timeout) { + dhcsr = STLINK_REG_DHCSR_S_RESET_ST; + stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); + if ((dhcsr & STLINK_REG_DHCSR_S_RESET_ST) == 0) { + return (0); + } } - cr_pg = (1 << FLASH_CR_PG); - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { - cr_reg = STM32WB_FLASH_CR; - cr_mer = (1 << FLASH_CR_MER); - cr_pg = (1 << FLASH_CR_PG); - } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { - cr_reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; - cr_mer = (1 << FLASH_H7_CR_BER); - cr_pg = (1 << FLASH_H7_CR_PG); - } else { - cr_reg = (bank == BANK_1) ? FLASH_CR : FLASH_CR2; - cr_mer = (1 << FLASH_CR_MER); - cr_pg = (1 << FLASH_CR_PG); + return (-1); } - stlink_read_debug32(sl, cr_reg, &val); - - if (val & cr_pg) { - // STM32F030 will drop MER bit if PG was set - val &= ~cr_pg; - stlink_write_debug32(sl, cr_reg, val); + if (type == RESET_SOFT || type == RESET_SOFT_AND_HALT) { + return stlink_soft_reset(sl, (type == RESET_SOFT_AND_HALT)); } - if (v) { - val |= cr_mer; - } else { - val &= ~cr_mer; + return (0); +} +// 255 +int stlink_run(stlink_t *sl, enum run_type type) { + struct stlink_reg rr; + DLOG("*** stlink_run ***\n"); + + /* Make sure we are in Thumb mode + * Cortex-M chips don't support ARM mode instructions + * xPSR may be incorrect if the vector table has invalid data */ + stlink_read_reg(sl, 16, &rr); + if ((rr.xpsr & (1 << 24)) == 0) { + ILOG("Go to Thumb mode\n"); + stlink_write_reg(sl, rr.xpsr | (1 << 24), 16); } - stlink_write_debug32(sl, cr_reg, val); + return (sl->backend->run(sl, type)); } - -static void set_flash_cr_strt(stlink_t *sl, unsigned bank) { - uint32_t val, cr_reg, cr_strt; - - if (sl->flash_type == STLINK_FLASH_TYPE_F4) { - cr_reg = FLASH_F4_CR; - cr_strt = 1 << FLASH_F4_CR_STRT; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { - cr_reg = FLASH_F7_CR; - cr_strt = 1 << FLASH_F7_CR_STRT; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { - cr_reg = STM32L4_FLASH_CR; - cr_strt = (1 << STM32L4_FLASH_CR_STRT); - } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { - cr_reg = STM32Gx_FLASH_CR; - cr_strt = (1 << STM32Gx_FLASH_CR_STRT); - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { - cr_reg = STM32WB_FLASH_CR; - cr_strt = (1 << STM32WB_FLASH_CR_STRT); - } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { - cr_reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; - cr_strt = 1 << FLASH_H7_CR_START(sl->chip_id); - } else { - cr_reg = (bank == BANK_1) ? FLASH_CR : FLASH_CR2; - cr_strt = (1 << FLASH_CR_STRT); +// 273 +int stlink_set_swdclk(stlink_t *sl, int freq_khz) { + DLOG("*** set_swdclk ***\n"); + return (sl->backend->set_swdclk(sl, freq_khz)); +} +// 293 +// this function is called by stlink_status() +// do not call stlink_core_stat() directly, always use stlink_status() +void stlink_core_stat(stlink_t *sl) { + switch (sl->core_stat) { + case TARGET_RUNNING: + DLOG(" core status: running\n"); + return; + case TARGET_HALTED: + DLOG(" core status: halted\n"); + return; + case TARGET_RESET: + DLOG(" core status: reset\n"); + return; + case TARGET_DEBUG_RUNNING: + DLOG(" core status: debug running\n"); + return; + default: + DLOG(" core status: unknown\n"); } +} +// 256 +int stlink_status(stlink_t *sl) { + int ret; - stlink_read_debug32(sl, cr_reg, &val); - val |= cr_strt; - stlink_write_debug32(sl, cr_reg, val); + DLOG("*** stlink_status ***\n"); + ret = sl->backend->status(sl); + stlink_core_stat(sl); + return (ret); } +// 257 +int stlink_version(stlink_t *sl) { + DLOG("*** looking up stlink version\n"); -static inline uint32_t read_flash_sr(stlink_t *sl, unsigned bank) { - uint32_t res, sr_reg; - - if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || - (sl->flash_type == STLINK_FLASH_TYPE_F1_XL)) { - sr_reg = (bank == BANK_1) ? FLASH_SR : FLASH_SR2; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { - sr_reg = get_stm32l0_flash_base(sl) + FLASH_SR_OFF; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F4) { - sr_reg = FLASH_F4_SR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { - sr_reg = FLASH_F7_SR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { - sr_reg = STM32L4_FLASH_SR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { - sr_reg = STM32Gx_FLASH_SR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { - sr_reg = STM32WB_FLASH_SR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { - sr_reg = (bank == BANK_1) ? FLASH_H7_SR1 : FLASH_H7_SR2; - } else { - ELOG("method 'read_flash_sr' is unsupported\n"); + if (sl->backend->version(sl)) { return (-1); } - stlink_read_debug32(sl, sr_reg, &res); - return (res); -} + _parse_version(sl, &sl->version); -static inline int write_flash_sr(stlink_t *sl, unsigned bank, uint32_t val) { - uint32_t sr_reg; - - if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || - (sl->flash_type == STLINK_FLASH_TYPE_F1_XL)) { - sr_reg = (bank == BANK_1) ? FLASH_SR : FLASH_SR2; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { - sr_reg = get_stm32l0_flash_base(sl) + FLASH_SR_OFF; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F4) { - sr_reg = FLASH_F4_SR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { - sr_reg = FLASH_F7_SR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { - sr_reg = STM32L4_FLASH_SR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { - sr_reg = STM32Gx_FLASH_SR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { - sr_reg = STM32WB_FLASH_SR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { - sr_reg = (bank == BANK_1) ? FLASH_H7_SR1 : FLASH_H7_SR2; - } else { - ELOG("method 'write_flash_sr' is unsupported\n"); - return (-1); + DLOG("st vid = 0x%04x (expect 0x%04x)\n", sl->version.st_vid, + STLINK_USB_VID_ST); + DLOG("stlink pid = 0x%04x\n", sl->version.stlink_pid); + DLOG("stlink version = 0x%x\n", sl->version.stlink_v); + DLOG("jtag version = 0x%x\n", sl->version.jtag_v); + DLOG("swim version = 0x%x\n", sl->version.swim_v); + + if (sl->version.jtag_v == 0) { + WLOG(" warning: stlink doesn't support JTAG/SWD interface\n"); } - return stlink_write_debug32(sl, sr_reg, val); + return (0); } +// 272 +int stlink_target_voltage(stlink_t *sl) { + int voltage = -1; + DLOG("*** reading target voltage\n"); -static inline unsigned int is_flash_busy(stlink_t *sl) { - uint32_t sr_busy_shift; - unsigned int res; - - if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || - (sl->flash_type == STLINK_FLASH_TYPE_F1_XL) || - (sl->flash_type == STLINK_FLASH_TYPE_L0)) { - sr_busy_shift = FLASH_SR_BSY; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F4) { - sr_busy_shift = FLASH_F4_SR_BSY; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { - sr_busy_shift = FLASH_F7_SR_BSY; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { - sr_busy_shift = STM32L4_FLASH_SR_BSY; - } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { - sr_busy_shift = STM32Gx_FLASH_SR_BSY; - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { - sr_busy_shift = STM32WB_FLASH_SR_BSY; - } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { - sr_busy_shift = FLASH_H7_SR_QW; + if (sl->backend->target_voltage != NULL) { + voltage = sl->backend->target_voltage(sl); + + if (voltage != -1) { + DLOG("target voltage = %imV\n", voltage); + } else { + DLOG("error reading target voltage\n"); + } } else { - ELOG("method 'is_flash_busy' is unsupported\n"); - return (-1); + DLOG("reading voltage not supported by backend\n"); } - res = read_flash_sr(sl, BANK_1) & (1 << sr_busy_shift); + return (voltage); +} +// 299 +bool stlink_is_core_halted(stlink_t *sl) { + stlink_status(sl); + return (sl->core_stat == TARGET_HALTED); +} +// 269 +int stlink_step(stlink_t *sl) { + DLOG("*** stlink_step ***\n"); + return (sl->backend->step(sl)); +} +// 270 +int stlink_current_mode(stlink_t *sl) { + int mode = sl->backend->current_mode(sl); - if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL || - (sl->flash_type == STLINK_FLASH_TYPE_H7 && - sl->chip_flags & CHIP_F_HAS_DUAL_BANK)) { - res |= read_flash_sr(sl, BANK_2) & (1 << sr_busy_shift); + switch (mode) { + case STLINK_DEV_DFU_MODE: + DLOG("stlink current mode: dfu\n"); + return (mode); + case STLINK_DEV_DEBUG_MODE: + DLOG("stlink current mode: debug (jtag or swd)\n"); + return (mode); + case STLINK_DEV_MASS_MODE: + DLOG("stlink current mode: mass\n"); + return (mode); } - return (res); + DLOG("stlink mode: unknown!\n"); + return (STLINK_DEV_UNKNOWN_MODE); } - -static void wait_flash_busy(stlink_t *sl) { - // TODO: add some delays here - while (is_flash_busy(sl)) - ; +// 274 +int stlink_trace_enable(stlink_t *sl, uint32_t frequency) { + DLOG("*** stlink_trace_enable ***\n"); + return (sl->backend->trace_enable(sl, frequency)); } +// 275 +int stlink_trace_disable(stlink_t *sl) { + DLOG("*** stlink_trace_disable ***\n"); + return (sl->backend->trace_disable(sl)); +} +// 276 +int stlink_trace_read(stlink_t *sl, uint8_t *buf, size_t size) { + return (sl->backend->trace_read(sl, buf, size)); +} +// 294 +void stlink_print_data(stlink_t *sl) { + if (sl->q_len <= 0 || sl->verbose < UDEBUG) { + return; + } -static void wait_flash_busy_progress(stlink_t *sl) { - int i = 0; - fprintf(stdout, "Mass erasing"); - fflush(stdout); - - while (is_flash_busy(sl)) { - usleep(10000); - i++; + if (sl->verbose > 2) { + DLOG("data_len = %d 0x%x\n", sl->q_len, sl->q_len); + } - if (i % 100 == 0) { - fprintf(stdout, "."); - fflush(stdout); + for (int i = 0; i < sl->q_len; i++) { + if (i % 16 == 0) { + /* + if (sl->q_data_dir == Q_DATA_OUT) { + fprintf(stdout, "\n<- 0x%08x ", sl->q_addr + i); + } else { + fprintf(stdout, "\n-> 0x%08x ", sl->q_addr + i); + } + */ } + // DLOG(" %02x", (unsigned int) sl->q_buf[i]); + fprintf(stderr, " %02x", (unsigned int)sl->q_buf[i]); } - - fprintf(stdout, "\n"); -} - -static void clear_flash_error(stlink_t *sl) { - switch (sl->flash_type) { - case STLINK_FLASH_TYPE_F0: - write_flash_sr(sl, BANK_1, FLASH_SR_ERROR_MASK); - break; - case STLINK_FLASH_TYPE_F4: - write_flash_sr(sl, BANK_1, FLASH_F4_SR_ERROR_MASK); - break; - case STLINK_FLASH_TYPE_F7: - write_flash_sr(sl, BANK_1, FLASH_F7_SR_ERROR_MASK); - break; - case STLINK_FLASH_TYPE_G0: - case STLINK_FLASH_TYPE_G4: - write_flash_sr(sl, BANK_1, STM32Gx_FLASH_SR_ERROR_MASK); - break; - case STLINK_FLASH_TYPE_L0: - write_flash_sr(sl, BANK_1, STM32L0_FLASH_SR_ERROR_MASK); - break; - case STLINK_FLASH_TYPE_L4: - write_flash_sr(sl, BANK_1, STM32L4_FLASH_SR_ERROR_MASK); - break; - case STLINK_FLASH_TYPE_H7: - write_flash_sr(sl, BANK_1, FLASH_H7_SR_ERROR_MASK); - if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { - write_flash_sr(sl, BANK_2, FLASH_H7_SR_ERROR_MASK); - } - break; - case STLINK_FLASH_TYPE_WB: - write_flash_sr(sl, BANK_1, STM32WB_FLASH_SR_ERROR_MASK); - break; - default: - break; - } + // DLOG("\n\n"); + fprintf(stderr, "\n"); } +// 283 +int stlink_mwrite_sram(stlink_t *sl, uint8_t *data, uint32_t length, + stm32_addr_t addr) { + // write the file in sram at addr -static int check_flash_error(stlink_t *sl) { - uint32_t res = 0; - uint32_t WRPERR, PROGERR, PGAERR; + int error = -1; + size_t off; + size_t len; - WRPERR = PROGERR = PGAERR = 0; + // check addr range is inside the sram + if (addr < sl->sram_base) { + fprintf(stderr, "addr too low\n"); + goto on_error; + } else if ((addr + length) < addr) { + fprintf(stderr, "addr overruns\n"); + goto on_error; + } else if ((addr + length) > (sl->sram_base + sl->sram_size)) { + fprintf(stderr, "addr too high\n"); + goto on_error; + } else if (addr & 3) { + fprintf(stderr, "unaligned addr\n"); + goto on_error; + } - switch (sl->flash_type) { - case STLINK_FLASH_TYPE_F0: - case STLINK_FLASH_TYPE_F1_XL: - res = read_flash_sr(sl, BANK_1) & FLASH_SR_ERROR_MASK; - if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL) { - res |= read_flash_sr(sl, BANK_2) & FLASH_SR_ERROR_MASK; - } - WRPERR = (1 << FLASH_SR_WRPRT_ERR); - PROGERR = (1 << FLASH_SR_PG_ERR); - break; - case STLINK_FLASH_TYPE_F4: - res = read_flash_sr(sl, BANK_1) & FLASH_F4_SR_ERROR_MASK; - WRPERR = (1 << FLASH_F4_SR_WRPERR); - PGAERR = (1 << FLASH_F4_SR_PGAERR); - break; - case STLINK_FLASH_TYPE_F7: - res = read_flash_sr(sl, BANK_1) & FLASH_F7_SR_ERROR_MASK; - WRPERR = (1 << FLASH_F7_SR_WRP_ERR); - PROGERR = (1 << FLASH_F7_SR_PGP_ERR); - break; - case STLINK_FLASH_TYPE_G0: - case STLINK_FLASH_TYPE_G4: - res = read_flash_sr(sl, BANK_1) & STM32Gx_FLASH_SR_ERROR_MASK; - WRPERR = (1 << STM32Gx_FLASH_SR_WRPERR); - PROGERR = (1 << STM32Gx_FLASH_SR_PROGERR); - PGAERR = (1 << STM32Gx_FLASH_SR_PGAERR); - break; - case STLINK_FLASH_TYPE_L0: - res = read_flash_sr(sl, BANK_1) & STM32L0_FLASH_SR_ERROR_MASK; - WRPERR = (1 << STM32L0_FLASH_SR_WRPERR); - PROGERR = (1 << STM32L0_FLASH_SR_NOTZEROERR); - PGAERR = (1 << STM32L0_FLASH_SR_PGAERR); - break; - case STLINK_FLASH_TYPE_L4: - res = read_flash_sr(sl, BANK_1) & STM32L4_FLASH_SR_ERROR_MASK; - WRPERR = (1 << STM32L4_FLASH_SR_WRPERR); - PROGERR = (1 << STM32L4_FLASH_SR_PROGERR); - PGAERR = (1 << STM32L4_FLASH_SR_PGAERR); - break; - case STLINK_FLASH_TYPE_H7: - res = read_flash_sr(sl, BANK_1) & FLASH_H7_SR_ERROR_MASK; - if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { - res |= read_flash_sr(sl, BANK_2) & FLASH_H7_SR_ERROR_MASK; - } - WRPERR = (1 << FLASH_H7_SR_WRPERR); - break; - case STLINK_FLASH_TYPE_WB: - res = read_flash_sr(sl, BANK_1) & STM32WB_FLASH_SR_ERROR_MASK; - WRPERR = (1 << STM32WB_FLASH_SR_WRPERR); - PROGERR = (1 << STM32WB_FLASH_SR_PROGERR); - PGAERR = (1 << STM32WB_FLASH_SR_PGAERR); - break; - default: - break; + len = length; + + if (len & 3) { + len -= len & 3; } - if (res) { - if (WRPERR && (WRPERR & res) == WRPERR) { - ELOG("Flash memory is write protected\n"); - res &= ~WRPERR; - } else if (PROGERR && (PROGERR & res) == PROGERR) { - ELOG("Flash memory contains a non-erased value\n"); - res &= ~PROGERR; - } else if (PGAERR && (PGAERR & res) == PGAERR) { - ELOG("Invalid flash address\n"); - res &= ~PGAERR; - } + // do the copy by 1kB blocks + for (off = 0; off < len; off += 1024) { + size_t size = 1024; - if (res) { - ELOG("Flash programming error: %#010x\n", res); + if ((off + size) > len) { + size = len - off; } - return (-1); - } - return (0); -} + memcpy(sl->q_buf, data + off, size); -static void stop_wdg_in_debug(stlink_t *sl) { - uint32_t dbgmcu_cr; - uint32_t set; - uint32_t value; + if (size & 3) { + size += 2; + } // round size if needed - switch (sl->flash_type) { - case STLINK_FLASH_TYPE_F0: - case STLINK_FLASH_TYPE_F1_XL: - case STLINK_FLASH_TYPE_G4: - dbgmcu_cr = STM32F0_DBGMCU_CR; - set = (1 << STM32F0_DBGMCU_CR_IWDG_STOP) | - (1 << STM32F0_DBGMCU_CR_WWDG_STOP); - break; - case STLINK_FLASH_TYPE_F4: - case STLINK_FLASH_TYPE_F7: - case STLINK_FLASH_TYPE_L4: - dbgmcu_cr = STM32F4_DBGMCU_APB1FZR1; - set = (1 << STM32F4_DBGMCU_APB1FZR1_IWDG_STOP) | - (1 << STM32F4_DBGMCU_APB1FZR1_WWDG_STOP); - break; - case STLINK_FLASH_TYPE_L0: - case STLINK_FLASH_TYPE_G0: - dbgmcu_cr = STM32L0_DBGMCU_APB1_FZ; - set = (1 << STM32L0_DBGMCU_APB1_FZ_IWDG_STOP) | - (1 << STM32L0_DBGMCU_APB1_FZ_WWDG_STOP); - break; - case STLINK_FLASH_TYPE_H7: - dbgmcu_cr = STM32H7_DBGMCU_APB1HFZ; - set = (1 << STM32H7_DBGMCU_APB1HFZ_IWDG_STOP); - break; - case STLINK_FLASH_TYPE_WB: - dbgmcu_cr = STM32WB_DBGMCU_APB1FZR1; - set = (1 << STM32WB_DBGMCU_APB1FZR1_IWDG_STOP) | - (1 << STM32WB_DBGMCU_APB1FZR1_WWDG_STOP); - break; - default: - return; + stlink_write_mem32(sl, addr + (uint32_t)off, (uint16_t)size); } - if (!stlink_read_debug32(sl, dbgmcu_cr, &value)) { - stlink_write_debug32(sl, dbgmcu_cr, value | set); + if (length > len) { + memcpy(sl->q_buf, data + len, length - len); + stlink_write_mem8(sl, addr + (uint32_t)len, (uint16_t)(length - len)); } -} -static void set_dma_state(stlink_t *sl, flash_loader_t *fl, int bckpRstr) { - uint32_t rcc, rcc_dma_mask, value; + error = 0; // success + stlink_fwrite_finalize(sl, addr); - rcc = rcc_dma_mask = value = 0; +on_error: + return (error); +} +//284 +int stlink_fwrite_sram(stlink_t *sl, const char *path, stm32_addr_t addr) { + // write the file in sram at addr - switch (sl->flash_type) { - case STLINK_FLASH_TYPE_F0: - case STLINK_FLASH_TYPE_F1_XL: - rcc = STM32F1_RCC_AHBENR; - rcc_dma_mask = STM32F1_RCC_DMAEN; - break; - case STLINK_FLASH_TYPE_F4: - case STLINK_FLASH_TYPE_F7: - rcc = STM32F4_RCC_AHB1ENR; - rcc_dma_mask = STM32F4_RCC_DMAEN; - break; - case STLINK_FLASH_TYPE_G0: - rcc = STM32G0_RCC_AHBENR; - rcc_dma_mask = STM32G0_RCC_DMAEN; - break; - case STLINK_FLASH_TYPE_G4: - case STLINK_FLASH_TYPE_L4: - rcc = STM32G4_RCC_AHB1ENR; - rcc_dma_mask = STM32G4_RCC_DMAEN; - break; - case STLINK_FLASH_TYPE_L0: - rcc = STM32L0_RCC_AHBENR; - rcc_dma_mask = STM32L0_RCC_DMAEN; - break; - case STLINK_FLASH_TYPE_H7: - rcc = STM32H7_RCC_AHB1ENR; - rcc_dma_mask = STM32H7_RCC_DMAEN; - break; - case STLINK_FLASH_TYPE_WB: - rcc = STM32WB_RCC_AHB1ENR; - rcc_dma_mask = STM32WB_RCC_DMAEN; - break; - default: - return; - } + int error = -1; + size_t off; + size_t len; + mapped_file_t mf = MAPPED_FILE_INITIALIZER; - if (!stlink_read_debug32(sl, rcc, &value)) { - if (bckpRstr) { - value = (value & (~rcc_dma_mask)) | fl->rcc_dma_bkp; - } else { - fl->rcc_dma_bkp = value & rcc_dma_mask; - value &= ~rcc_dma_mask; - } - stlink_write_debug32(sl, rcc, value); + if (map_file(&mf, path) == -1) { + fprintf(stderr, "map_file() == -1\n"); + return (-1); } -} -static inline void write_flash_ar(stlink_t *sl, uint32_t n, unsigned bank) { - stlink_write_debug32(sl, (bank == BANK_1) ? FLASH_AR : FLASH_AR2, n); -} - -static inline void write_flash_cr_psiz(stlink_t *sl, uint32_t n, - unsigned bank) { - uint32_t cr_reg, psize_shift; - uint32_t x = read_flash_cr(sl, bank); + printf("file %s ", path); + md5_calculate(&mf); + stlink_checksum(&mf); - if (sl->flash_type == STLINK_FLASH_TYPE_H7) { - cr_reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; - psize_shift = FLASH_H7_CR_PSIZE; - } else { - cr_reg = FLASH_F4_CR; - psize_shift = 8; + // check if addr range is inside the SRAM + if (addr < sl->sram_base) { + fprintf(stderr, "addr too low\n"); + goto on_error; + } else if ((addr + mf.len) < addr) { + fprintf(stderr, "addr overruns\n"); + goto on_error; + } else if ((addr + mf.len) > (sl->sram_base + sl->sram_size)) { + fprintf(stderr, "addr too high\n"); + goto on_error; + } else if (addr & 3) { + fprintf(stderr, "unaligned addr\n"); + goto on_error; } - x &= ~(0x03 << psize_shift); - x |= (n << psize_shift); -#if DEBUG_FLASH - fprintf(stdout, "PSIZ:0x%x 0x%x\n", x, n); -#endif - stlink_write_debug32(sl, cr_reg, x); -} - -static inline void write_flash_cr_snb(stlink_t *sl, uint32_t n, unsigned bank) { - uint32_t cr_reg, snb_mask, snb_shift, ser_shift; - uint32_t x = read_flash_cr(sl, bank); + len = mf.len; - if (sl->flash_type == STLINK_FLASH_TYPE_H7) { - cr_reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; - snb_mask = FLASH_H7_CR_SNB_MASK; - snb_shift = FLASH_H7_CR_SNB; - ser_shift = FLASH_H7_CR_SER; - } else { - cr_reg = FLASH_F4_CR; - snb_mask = FLASH_F4_CR_SNB_MASK; - snb_shift = FLASH_F4_CR_SNB; - ser_shift = FLASH_F4_CR_SER; + if (len & 3) { + len -= len & 3; } - x &= ~snb_mask; - x |= (n << snb_shift); - x |= (1 << ser_shift); -#if DEBUG_FLASH - fprintf(stdout, "SNB:0x%x 0x%x\n", x, n); -#endif - stlink_write_debug32(sl, cr_reg, x); -} + // do the copy by 1kB blocks + for (off = 0; off < len; off += 1024) { + size_t size = 1024; -static inline void write_flash_cr_bker_pnb(stlink_t *sl, uint32_t n) { - stlink_write_debug32(sl, STM32L4_FLASH_SR, - 0xFFFFFFFF & ~(1 << STM32L4_FLASH_SR_BSY)); - uint32_t x = read_flash_cr(sl, BANK_1); - x &= ~STM32L4_FLASH_CR_OPBITS; - x &= ~STM32L4_FLASH_CR_PAGEMASK; - x &= ~(1 << STM32L4_FLASH_CR_MER1); - x &= ~(1 << STM32L4_FLASH_CR_MER2); - x |= (n << STM32L4_FLASH_CR_PNB); - x |= (uint32_t)(1lu << STM32L4_FLASH_CR_PER); -#if DEBUG_FLASH - fprintf(stdout, "BKER:PNB:0x%x 0x%x\n", x, n); -#endif - stlink_write_debug32(sl, STM32L4_FLASH_CR, x); -} + if ((off + size) > len) { + size = len - off; + } -// Delegates to the backends... + memcpy(sl->q_buf, mf.base + off, size); -void stlink_close(stlink_t *sl) { - DLOG("*** stlink_close ***\n"); + if (size & 3) { + size += 2; + } // round size if needed - if (!sl) { - return; + stlink_write_mem32(sl, addr + (uint32_t)off, (uint16_t)size); } - sl->backend->close(sl); - free(sl); -} - -int stlink_exit_debug_mode(stlink_t *sl) { - DLOG("*** stlink_exit_debug_mode ***\n"); + if (mf.len > len) { + memcpy(sl->q_buf, mf.base + len, mf.len - len); + stlink_write_mem8(sl, addr + (uint32_t)len, (uint16_t)(mf.len - len)); + } - if (sl->flash_type != STLINK_FLASH_TYPE_UNKNOWN && - sl->core_stat != TARGET_RESET) { - // stop debugging if the target has been identified - stlink_write_debug32(sl, STLINK_REG_DHCSR, STLINK_REG_DHCSR_DBGKEY); + // check the file has been written + if (check_file(sl, &mf, addr) == -1) { + fprintf(stderr, "check_file() == -1\n"); + goto on_error; } - return (sl->backend->exit_debug_mode(sl)); -} + error = 0; // success + stlink_fwrite_finalize(sl, addr); -int stlink_enter_swd_mode(stlink_t *sl) { - DLOG("*** stlink_enter_swd_mode ***\n"); - return (sl->backend->enter_swd_mode(sl)); +on_error: + unmap_file(&mf); + return (error); } +// 302 +int stlink_fread(stlink_t *sl, const char *path, bool is_ihex, + stm32_addr_t addr, size_t size) { + // read size bytes from addr to file + ILOG("read from address %#010x size %u\n", addr, (unsigned)size); -// Force the core into the debug mode -> halted state. -int stlink_force_debug(stlink_t *sl) { - DLOG("*** stlink_force_debug_mode ***\n"); - int res = sl->backend->force_debug(sl); - if (res) { - return (res); - } - // Stop the watchdogs in the halted state for suppress target reboot - stop_wdg_in_debug(sl); - return (0); -} - -int stlink_exit_dfu_mode(stlink_t *sl) { - DLOG("*** stlink_exit_dfu_mode ***\n"); - return (sl->backend->exit_dfu_mode(sl)); -} - -int stlink_core_id(stlink_t *sl) { - int ret; - - DLOG("*** stlink_core_id ***\n"); - ret = sl->backend->core_id(sl); - - if (ret == -1) { - ELOG("Failed to read core_id\n"); - return (ret); - } - - if (sl->verbose > 2) { - stlink_print_data(sl); - } - - DLOG("core_id = 0x%08x\n", sl->core_id); - return (ret); -} - -// stlink_chip_id() is called by stlink_load_device_params() -// do not call this procedure directly. -int stlink_chip_id(stlink_t *sl, uint32_t *chip_id) { - int ret; - cortex_m3_cpuid_t cpu_id; - - // Read the CPU ID to determine where to read the core id - if (stlink_cpu_id(sl, &cpu_id) || - cpu_id.implementer_id != STLINK_REG_CMx_CPUID_IMPL_ARM) { - ELOG("Can not connect to target. Please use \'connect under reset\' and " - "try again\n"); - return -1; - } - - /* - * the chip_id register in the reference manual have - * DBGMCU_IDCODE / DBG_IDCODE name - * - */ - - if ((sl->core_id == STM32H7_CORE_ID || sl->core_id == STM32H7_CORE_ID_JTAG) && - cpu_id.part == STLINK_REG_CMx_CPUID_PARTNO_CM7) { - // STM32H7 chipid in 0x5c001000 (RM0433 pg3189) - ret = stlink_read_debug32(sl, 0x5c001000, chip_id); - } else if (cpu_id.part == STLINK_REG_CMx_CPUID_PARTNO_CM0 || - cpu_id.part == STLINK_REG_CMx_CPUID_PARTNO_CM0P) { - // STM32F0 (RM0091, pg914; RM0360, pg713) - // STM32L0 (RM0377, pg813; RM0367, pg915; RM0376, pg917) - // STM32G0 (RM0444, pg1367) - ret = stlink_read_debug32(sl, 0x40015800, chip_id); - } else if (cpu_id.part == STLINK_REG_CMx_CPUID_PARTNO_CM33) { - // STM32L5 (RM0438, pg2157) - ret = stlink_read_debug32(sl, 0xE0044000, chip_id); - } else /* СM3, СM4, CM7 */ { - // default chipid address - - // STM32F1 (RM0008, pg1087; RM0041, pg681) - // STM32F2 (RM0033, pg1326) - // STM32F3 (RM0316, pg1095; RM0313, pg874) - // STM32F7 (RM0385, pg1676; RM0410, pg1912) - // STM32L1 (RM0038, pg861) - // STM32L4 (RM0351, pg1840; RM0394, pg1560) - // STM32G4 (RM0440, pg2086) - // STM32WB (RM0434, pg1406) - ret = stlink_read_debug32(sl, 0xE0042000, chip_id); - } - - if (ret || !(*chip_id)) { - *chip_id = 0; - ret = ret?ret:-1; - ELOG("Could not find chip id!\n"); - } else { - *chip_id = (*chip_id) & 0xfff; - - // Fix chip_id for F4 rev A errata, read CPU ID, as CoreID is the same for - // F2/F4 - if (*chip_id == 0x411 && cpu_id.part == STLINK_REG_CMx_CPUID_PARTNO_CM4) { - *chip_id = 0x413; - } - } - - return (ret); -} - -/** - * Cortex M tech ref manual, CPUID register description - * @param sl stlink context - * @param cpuid pointer to the result object - */ -int stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid) { - uint32_t raw; - - if (stlink_read_debug32(sl, STLINK_REG_CM3_CPUID, &raw)) { - cpuid->implementer_id = 0; - cpuid->variant = 0; - cpuid->part = 0; - cpuid->revision = 0; - return (-1); - } - - cpuid->implementer_id = (raw >> 24) & 0x7f; - cpuid->variant = (raw >> 20) & 0xf; - cpuid->part = (raw >> 4) & 0xfff; - cpuid->revision = raw & 0xf; - return (0); -} - -/** - * Reads and decodes the flash parameters, as dynamically as possible - * @param sl - * @return 0 for success, or -1 for unsupported core type. - */ -int stlink_load_device_params(stlink_t *sl) { - // This seems to normally work so is unnecessary info for a normal user. - // Demoted to debug. -- REW - DLOG("Loading device parameters....\n"); - const struct stlink_chipid_params *params = NULL; - stlink_core_id(sl); - uint32_t flash_size; - - if (stlink_chip_id(sl, &sl->chip_id)) { - return (-1); - } - - params = stlink_chipid_get_params(sl->chip_id); - - if (params == NULL) { - WLOG("unknown chip id! %#x\n", sl->chip_id); - return (-1); - } - - if (params->flash_type == STLINK_FLASH_TYPE_UNKNOWN) { - WLOG("Invalid flash type, please check device declaration\n"); - sl->flash_size = 0; - return (0); - } - - // These are fixed... - sl->flash_base = STM32_FLASH_BASE; - sl->sram_base = STM32_SRAM_BASE; - stlink_read_debug32(sl, (params->flash_size_reg) & ~3, &flash_size); - - if (params->flash_size_reg & 2) { - flash_size = flash_size >> 16; - } - - flash_size = flash_size & 0xffff; - - if ((sl->chip_id == STLINK_CHIPID_STM32_L1_MD || - sl->chip_id == STLINK_CHIPID_STM32_F1_VL_MD_LD || - sl->chip_id == STLINK_CHIPID_STM32_L1_MD_PLUS) && - (flash_size == 0)) { - sl->flash_size = 128 * 1024; - } else if (sl->chip_id == STLINK_CHIPID_STM32_L1_CAT2) { - sl->flash_size = (flash_size & 0xff) * 1024; - } else if ((sl->chip_id & 0xFFF) == STLINK_CHIPID_STM32_L1_MD_PLUS_HD) { - // 0 is 384k and 1 is 256k - if (flash_size == 0) { - sl->flash_size = 384 * 1024; - } else { - sl->flash_size = 256 * 1024; - } - } else { - sl->flash_size = flash_size * 1024; - } - - sl->flash_type = params->flash_type; - sl->flash_pgsz = params->flash_pagesize; - sl->sram_size = params->sram_size; - sl->sys_base = params->bootrom_base; - sl->sys_size = params->bootrom_size; - sl->option_base = params->option_base; - sl->option_size = params->option_size; - sl->chip_flags = params->flags; - - // medium and low devices have the same chipid. ram size depends on flash - // size. STM32F100xx datasheet Doc ID 16455 Table 2 - if (sl->chip_id == STLINK_CHIPID_STM32_F1_VL_MD_LD && - sl->flash_size < 64 * 1024) { - sl->sram_size = 0x1000; - } - - if (sl->chip_id == STLINK_CHIPID_STM32_G4_CAT3) { - uint32_t flash_optr; - stlink_read_debug32(sl, STM32Gx_FLASH_OPTR, &flash_optr); - - if (!(flash_optr & (1 << STM32G4_FLASH_OPTR_DBANK))) { - sl->flash_pgsz <<= 1; - } - } - - // H7 devices with small flash has one bank - if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK && - sl->flash_type == STLINK_FLASH_TYPE_H7) { - if ((sl->flash_size / sl->flash_pgsz) <= 1) - sl->chip_flags &= ~CHIP_F_HAS_DUAL_BANK; - } - - ILOG("%s: %u KiB SRAM, %u KiB flash in at least %u %s pages.\n", - params->description, (unsigned)(sl->sram_size / 1024), - (unsigned)(sl->flash_size / 1024), - (sl->flash_pgsz < 1024) ? (unsigned)(sl->flash_pgsz) - : (unsigned)(sl->flash_pgsz / 1024), - (sl->flash_pgsz < 1024) ? "byte" : "KiB"); - - return (0); -} - -int stlink_jtag_reset(stlink_t *sl, int value) { - DLOG("*** stlink_jtag_reset %d ***\n", value); - return (sl->backend->jtag_reset(sl, value)); -} - -int stlink_soft_reset(stlink_t *sl, int halt_on_reset) { - int ret; - unsigned timeout; - uint32_t dhcsr, dfsr; - - DLOG("*** stlink_soft_reset %s***\n", halt_on_reset ? "(halt) " : ""); - - // halt core and enable debugging (if not already done) - // C_DEBUGEN is required to Halt on reset (DDI0337E, p. 10-6) - stlink_write_debug32(sl, STLINK_REG_DHCSR, - STLINK_REG_DHCSR_DBGKEY | STLINK_REG_DHCSR_C_HALT | - STLINK_REG_DHCSR_C_DEBUGEN); - - // enable Halt on reset by set VC_CORERESET and TRCENA (DDI0337E, p. 10-10) - if (halt_on_reset) { - stlink_write_debug32( - sl, STLINK_REG_CM3_DEMCR, - STLINK_REG_CM3_DEMCR_TRCENA | STLINK_REG_CM3_DEMCR_VC_HARDERR | - STLINK_REG_CM3_DEMCR_VC_BUSERR | STLINK_REG_CM3_DEMCR_VC_CORERESET); - - // clear VCATCH in the DFSR register - stlink_write_debug32(sl, STLINK_REG_DFSR, STLINK_REG_DFSR_VCATCH); - } else { - stlink_write_debug32(sl, STLINK_REG_CM3_DEMCR, - STLINK_REG_CM3_DEMCR_TRCENA | - STLINK_REG_CM3_DEMCR_VC_HARDERR | - STLINK_REG_CM3_DEMCR_VC_BUSERR); - } - - // clear S_RESET_ST in the DHCSR register - stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); - - // soft reset (core reset) by SYSRESETREQ (DDI0337E, p. 8-23) - ret = stlink_write_debug32(sl, STLINK_REG_AIRCR, - STLINK_REG_AIRCR_VECTKEY | - STLINK_REG_AIRCR_SYSRESETREQ); - if (ret) { - ELOG("Soft reset failed: error write to AIRCR\n"); - return (ret); - } - - // waiting for a reset within 500ms - // DDI0337E, p. 10-4, Debug Halting Control and Status Register - timeout = time_ms() + 500; - while (time_ms() < timeout) { - // DDI0337E, p. 10-4, Debug Halting Control and Status Register - dhcsr = STLINK_REG_DHCSR_S_RESET_ST; - stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); - if ((dhcsr & STLINK_REG_DHCSR_S_RESET_ST) == 0) { - if (halt_on_reset) { - // waiting halt by the SYSRESETREQ exception - // DDI0403E, p. C1-699, Debug Fault Status Register - dfsr = 0; - stlink_read_debug32(sl, STLINK_REG_DFSR, &dfsr); - if ((dfsr & STLINK_REG_DFSR_VCATCH) == 0) { - continue; - } - } - timeout = 0; - break; - } - } - - // reset DFSR register. DFSR is power-on reset only (DDI0337H, p. 7-5) - stlink_write_debug32(sl, STLINK_REG_DFSR, STLINK_REG_DFSR_CLEAR); - - if (timeout) { - ELOG("Soft reset failed: timeout\n"); - return (-1); - } - - return (0); -} - -int stlink_reset(stlink_t *sl, enum reset_type type) { - uint32_t dhcsr; - unsigned timeout; - - DLOG("*** stlink_reset ***\n"); - - sl->core_stat = TARGET_RESET; - - if (type == RESET_AUTO) { - // clear S_RESET_ST in DHCSR register for reset state detection - stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); - } - - if (type == RESET_HARD || type == RESET_AUTO) { - // hardware target reset - if (sl->version.stlink_v > 1) { - stlink_jtag_reset(sl, STLINK_DEBUG_APIV2_DRIVE_NRST_LOW); - // minimum reset pulse duration of 20 us (RM0008, 8.1.2 Power reset) - usleep(100); - stlink_jtag_reset(sl, STLINK_DEBUG_APIV2_DRIVE_NRST_HIGH); - } - sl->backend->reset(sl); - usleep(10000); - } - - if (type == RESET_AUTO) { - /* Check if the S_RESET_ST bit is set in DHCSR - * This means that a reset has occurred - * DDI0337E, p. 10-4, Debug Halting Control and Status Register */ - - dhcsr = 0; - int res = stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); - if ((dhcsr & STLINK_REG_DHCSR_S_RESET_ST) == 0 && !res) { - // reset not done yet - // try reset through AIRCR so that NRST does not need to be connected - - WLOG("NRST is not connected\n"); - DLOG("Using reset through SYSRESETREQ\n"); - return stlink_soft_reset(sl, 0); - } - - // waiting for reset the S_RESET_ST bit within 500ms - timeout = time_ms() + 500; - while (time_ms() < timeout) { - dhcsr = STLINK_REG_DHCSR_S_RESET_ST; - stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); - if ((dhcsr & STLINK_REG_DHCSR_S_RESET_ST) == 0) { - return (0); - } - } - - return (-1); - } - - if (type == RESET_SOFT || type == RESET_SOFT_AND_HALT) { - return stlink_soft_reset(sl, (type == RESET_SOFT_AND_HALT)); - } - - return (0); -} - -int stlink_run(stlink_t *sl, enum run_type type) { - struct stlink_reg rr; - DLOG("*** stlink_run ***\n"); - - /* Make sure we are in Thumb mode - * Cortex-M chips don't support ARM mode instructions - * xPSR may be incorrect if the vector table has invalid data */ - stlink_read_reg(sl, 16, &rr); - if ((rr.xpsr & (1 << 24)) == 0) { - ILOG("Go to Thumb mode\n"); - stlink_write_reg(sl, rr.xpsr | (1 << 24), 16); - } - - return (sl->backend->run(sl, type)); -} - -int stlink_set_swdclk(stlink_t *sl, int freq_khz) { - DLOG("*** set_swdclk ***\n"); - return (sl->backend->set_swdclk(sl, freq_khz)); -} - -int stlink_status(stlink_t *sl) { - int ret; - - DLOG("*** stlink_status ***\n"); - ret = sl->backend->status(sl); - stlink_core_stat(sl); - return (ret); -} - -/** - * Decode the version bits, originally from -sg, verified with usb - * @param sl stlink context, assumed to contain valid data in the buffer - * @param slv output parsed version object - */ -void _parse_version(stlink_t *sl, stlink_version_t *slv) { - sl->version.flags = 0; - - if (sl->version.stlink_v < 3) { - uint32_t b0 = sl->q_buf[0]; // lsb - uint32_t b1 = sl->q_buf[1]; - uint32_t b2 = sl->q_buf[2]; - uint32_t b3 = sl->q_buf[3]; - uint32_t b4 = sl->q_buf[4]; - uint32_t b5 = sl->q_buf[5]; // msb - - // b0 b1 || b2 b3 | b4 b5 - // 4b | 6b | 6b || 2B | 2B - // stlink_v | jtag_v | swim_v || st_vid | stlink_pid - - slv->stlink_v = (b0 & 0xf0) >> 4; - slv->jtag_v = ((b0 & 0x0f) << 2) | ((b1 & 0xc0) >> 6); - slv->swim_v = b1 & 0x3f; - slv->st_vid = (b3 << 8) | b2; - slv->stlink_pid = (b5 << 8) | b4; - - // ST-LINK/V1 from J11 switch to api-v2 (and support SWD) - if (slv->stlink_v == 1) { - slv->jtag_api = - slv->jtag_v > 11 ? STLINK_JTAG_API_V2 : STLINK_JTAG_API_V1; - } else { - slv->jtag_api = STLINK_JTAG_API_V2; - - // preferred API to get last R/W status from J15 - if (sl->version.jtag_v >= 15) { - sl->version.flags |= STLINK_F_HAS_GETLASTRWSTATUS2; - } - - if (sl->version.jtag_v >= 13) { - sl->version.flags |= STLINK_F_HAS_TRACE; - sl->max_trace_freq = STLINK_V2_MAX_TRACE_FREQUENCY; - } - } - } else { - // V3 uses different version format, for reference see OpenOCD source - // (that was written from docs available from ST under NDA): - // https://github.com/ntfreak/openocd/blob/a6dacdff58ef36fcdac00c53ec27f19de1fbce0d/src/jtag/drivers/stlink_usb.c#L965 - slv->stlink_v = sl->q_buf[0]; - slv->swim_v = sl->q_buf[1]; - slv->jtag_v = sl->q_buf[2]; - slv->st_vid = (uint32_t)((sl->q_buf[9] << 8) | sl->q_buf[8]); - slv->stlink_pid = (uint32_t)((sl->q_buf[11] << 8) | sl->q_buf[10]); - slv->jtag_api = STLINK_JTAG_API_V3; - /* preferred API to get last R/W status */ - sl->version.flags |= STLINK_F_HAS_GETLASTRWSTATUS2; - sl->version.flags |= STLINK_F_HAS_TRACE; - sl->max_trace_freq = STLINK_V3_MAX_TRACE_FREQUENCY; - } - - return; -} - -int stlink_version(stlink_t *sl) { - DLOG("*** looking up stlink version\n"); - - if (sl->backend->version(sl)) { - return (-1); - } - - _parse_version(sl, &sl->version); - - DLOG("st vid = 0x%04x (expect 0x%04x)\n", sl->version.st_vid, - STLINK_USB_VID_ST); - DLOG("stlink pid = 0x%04x\n", sl->version.stlink_pid); - DLOG("stlink version = 0x%x\n", sl->version.stlink_v); - DLOG("jtag version = 0x%x\n", sl->version.jtag_v); - DLOG("swim version = 0x%x\n", sl->version.swim_v); - - if (sl->version.jtag_v == 0) { - WLOG(" warning: stlink doesn't support JTAG/SWD interface\n"); - } - - return (0); -} - -int stlink_target_voltage(stlink_t *sl) { - int voltage = -1; - DLOG("*** reading target voltage\n"); - - if (sl->backend->target_voltage != NULL) { - voltage = sl->backend->target_voltage(sl); - - if (voltage != -1) { - DLOG("target voltage = %imV\n", voltage); - } else { - DLOG("error reading target voltage\n"); - } - } else { - DLOG("reading voltage not supported by backend\n"); - } - - return (voltage); -} - -int stlink_read_debug32(stlink_t *sl, uint32_t addr, uint32_t *data) { - int ret; - - ret = sl->backend->read_debug32(sl, addr, data); - if (!ret) - DLOG("*** stlink_read_debug32 %#010x at %#010x\n", *data, addr); - - return (ret); -} - -int stlink_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data) { - DLOG("*** stlink_write_debug32 %#010x to %#010x\n", data, addr); - return sl->backend->write_debug32(sl, addr, data); -} - -int stlink_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { - DLOG("*** stlink_write_mem32 %u bytes to %#x\n", len, addr); - - if (len % 4 != 0) { - ELOG("Data length doesn't have a 32 bit alignment: +%d byte.\n", len % 4); - return (-1); - } - - return (sl->backend->write_mem32(sl, addr, len)); -} - -int stlink_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { - DLOG("*** stlink_read_mem32 ***\n"); - - if (len % 4 != 0) { // !!! never ever: fw gives just wrong values - ELOG("Data length doesn't have a 32 bit alignment: +%d byte.\n", len % 4); - return (-1); - } - - return (sl->backend->read_mem32(sl, addr, len)); -} - -int stlink_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len) { - DLOG("*** stlink_write_mem8 ***\n"); - return (sl->backend->write_mem8(sl, addr, len)); -} - -int stlink_read_all_regs(stlink_t *sl, struct stlink_reg *regp) { - DLOG("*** stlink_read_all_regs ***\n"); - return (sl->backend->read_all_regs(sl, regp)); -} - -int stlink_read_all_unsupported_regs(stlink_t *sl, struct stlink_reg *regp) { - DLOG("*** stlink_read_all_unsupported_regs ***\n"); - return (sl->backend->read_all_unsupported_regs(sl, regp)); -} - -int stlink_write_reg(stlink_t *sl, uint32_t reg, int idx) { - DLOG("*** stlink_write_reg\n"); - return (sl->backend->write_reg(sl, reg, idx)); -} - -int stlink_read_reg(stlink_t *sl, int r_idx, struct stlink_reg *regp) { - DLOG("*** stlink_read_reg\n"); - DLOG(" (%d) ***\n", r_idx); - - if (r_idx > 20 || r_idx < 0) { - fprintf(stderr, "Error: register index must be in [0..20]\n"); - return (-1); - } - - return (sl->backend->read_reg(sl, r_idx, regp)); -} - -int stlink_read_unsupported_reg(stlink_t *sl, int r_idx, - struct stlink_reg *regp) { - int r_convert; - - DLOG("*** stlink_read_unsupported_reg\n"); - DLOG(" (%d) ***\n", r_idx); - - /* Convert to values used by STLINK_REG_DCRSR */ - if (r_idx >= 0x1C && - r_idx <= 0x1F) { // primask, basepri, faultmask, or control - r_convert = 0x14; - } else if (r_idx == 0x40) { // FPSCR - r_convert = 0x21; - } else if (r_idx >= 0x20 && r_idx < 0x40) { - r_convert = 0x40 + (r_idx - 0x20); - } else { - fprintf(stderr, "Error: register address must be in [0x1C..0x40]\n"); - return (-1); - } - - return (sl->backend->read_unsupported_reg(sl, r_convert, regp)); -} - -int stlink_write_unsupported_reg(stlink_t *sl, uint32_t val, int r_idx, - struct stlink_reg *regp) { - int r_convert; - - DLOG("*** stlink_write_unsupported_reg\n"); - DLOG(" (%d) ***\n", r_idx); - - /* Convert to values used by STLINK_REG_DCRSR */ - if (r_idx >= 0x1C && - r_idx <= 0x1F) { /* primask, basepri, faultmask, or control */ - r_convert = r_idx; // the backend function handles this - } else if (r_idx == 0x40) { // FPSCR - r_convert = 0x21; - } else if (r_idx >= 0x20 && r_idx < 0x40) { - r_convert = 0x40 + (r_idx - 0x20); - } else { - fprintf(stderr, "Error: register address must be in [0x1C..0x40]\n"); - return (-1); - } - - return (sl->backend->write_unsupported_reg(sl, val, r_convert, regp)); -} - -bool stlink_is_core_halted(stlink_t *sl) { - stlink_status(sl); - return (sl->core_stat == TARGET_HALTED); -} - -int stlink_step(stlink_t *sl) { - DLOG("*** stlink_step ***\n"); - return (sl->backend->step(sl)); -} - -int stlink_current_mode(stlink_t *sl) { - int mode = sl->backend->current_mode(sl); - - switch (mode) { - case STLINK_DEV_DFU_MODE: - DLOG("stlink current mode: dfu\n"); - return (mode); - case STLINK_DEV_DEBUG_MODE: - DLOG("stlink current mode: debug (jtag or swd)\n"); - return (mode); - case STLINK_DEV_MASS_MODE: - DLOG("stlink current mode: mass\n"); - return (mode); - } - - DLOG("stlink mode: unknown!\n"); - return (STLINK_DEV_UNKNOWN_MODE); -} - -int stlink_trace_enable(stlink_t *sl, uint32_t frequency) { - DLOG("*** stlink_trace_enable ***\n"); - return (sl->backend->trace_enable(sl, frequency)); -} - -int stlink_trace_disable(stlink_t *sl) { - DLOG("*** stlink_trace_disable ***\n"); - return (sl->backend->trace_disable(sl)); -} - -int stlink_trace_read(stlink_t *sl, uint8_t *buf, size_t size) { - return (sl->backend->trace_read(sl, buf, size)); -} - -// End of delegates.... Common code below here... - -// same as above with entrypoint. - -void stlink_run_at(stlink_t *sl, stm32_addr_t addr) { - stlink_write_reg(sl, addr, 15); /* pc register */ - stlink_run(sl, RUN_NORMAL); - - while (stlink_is_core_halted(sl)) { - usleep(3000000); - } -} - -// this function is called by stlink_status() -// do not call stlink_core_stat() directly, always use stlink_status() -void stlink_core_stat(stlink_t *sl) { - switch (sl->core_stat) { - case TARGET_RUNNING: - DLOG(" core status: running\n"); - return; - case TARGET_HALTED: - DLOG(" core status: halted\n"); - return; - case TARGET_RESET: - DLOG(" core status: reset\n"); - return; - case TARGET_DEBUG_RUNNING: - DLOG(" core status: debug running\n"); - return; - default: - DLOG(" core status: unknown\n"); - } -} - -void stlink_print_data(stlink_t *sl) { - if (sl->q_len <= 0 || sl->verbose < UDEBUG) { - return; - } - - if (sl->verbose > 2) { - DLOG("data_len = %d 0x%x\n", sl->q_len, sl->q_len); - } - - for (int i = 0; i < sl->q_len; i++) { - if (i % 16 == 0) { - /* - if (sl->q_data_dir == Q_DATA_OUT) { - fprintf(stdout, "\n<- 0x%08x ", sl->q_addr + i); - } else { - fprintf(stdout, "\n-> 0x%08x ", sl->q_addr + i); - } - */ - } - // DLOG(" %02x", (unsigned int) sl->q_buf[i]); - fprintf(stderr, " %02x", (unsigned int)sl->q_buf[i]); - } - // DLOG("\n\n"); - fprintf(stderr, "\n"); -} - -/* Memory mapped file */ -typedef struct mapped_file { - uint8_t *base; - size_t len; -} mapped_file_t; - -#define MAPPED_FILE_INITIALIZER \ - { NULL, 0 } - -static int map_file(mapped_file_t *mf, const char *path) { - int error = -1; - struct stat st; - - const int fd = open(path, O_RDONLY | O_BINARY); - - if (fd == -1) { - fprintf(stderr, "open(%s) == -1\n", path); - return (-1); - } - - if (fstat(fd, &st) == -1) { - fprintf(stderr, "fstat(%s) == -1\n", path); - goto on_error; - } - - if (sizeof(st.st_size) != sizeof(size_t)) { - // on 32 bit systems, check if there is an overflow - if (st.st_size > (off_t)SSIZE_MAX) { - fprintf(stderr, "mmap() size_t overflow for file %s\n", path); - goto on_error; - } - } - - mf->base = - (uint8_t *)mmap(NULL, (size_t)(st.st_size), PROT_READ, MAP_SHARED, fd, 0); - - if (mf->base == MAP_FAILED) { - fprintf(stderr, "mmap() == MAP_FAILED for file %s\n", path); - goto on_error; - } - - mf->len = (size_t)st.st_size; - error = 0; // success - -on_error: - close(fd); - return (error); -} - -static void unmap_file(mapped_file_t *mf) { - munmap((void *)mf->base, mf->len); - mf->base = (unsigned char *)MAP_FAILED; - mf->len = 0; -} - -/* Limit the block size to compare to 0x1800 as anything larger will stall the - * STLINK2 Maybe STLINK V1 needs smaller value! - */ -static int check_file(stlink_t *sl, mapped_file_t *mf, stm32_addr_t addr) { - size_t off; - size_t n_cmp = sl->flash_pgsz; - - if (n_cmp > 0x1800) { - n_cmp = 0x1800; - } - - for (off = 0; off < mf->len; off += n_cmp) { - size_t aligned_size; - - size_t cmp_size = n_cmp; // adjust last page size - - if ((off + n_cmp) > mf->len) { - cmp_size = mf->len - off; - } - - aligned_size = cmp_size; - - if (aligned_size & (4 - 1)) { - aligned_size = (cmp_size + 4) & ~(4 - 1); - } - - stlink_read_mem32(sl, addr + (uint32_t)off, (uint16_t)aligned_size); - - if (memcmp(sl->q_buf, mf->base + off, cmp_size)) { - return (-1); - } - } - - return (0); -} - -static void md5_calculate(mapped_file_t *mf) { - // calculate md5 checksum of given binary file - Md5Context md5Context; - MD5_HASH md5Hash; - Md5Initialise(&md5Context); - Md5Update(&md5Context, mf->base, (uint32_t)mf->len); - Md5Finalise(&md5Context, &md5Hash); - printf("md5 checksum: "); - - for (int i = 0; i < (int)sizeof(md5Hash); i++) { - printf("%x", md5Hash.bytes[i]); - } - - printf(", "); -} - -static void stlink_checksum(mapped_file_t *mp) { - /* checksum that backward compatible with official ST tools */ - uint32_t sum = 0; - uint8_t *mp_byte = (uint8_t *)mp->base; - - for (size_t i = 0; i < mp->len; ++i) { - sum += mp_byte[i]; - } - - printf("stlink checksum: 0x%08x\n", sum); -} - -static void stlink_fwrite_finalize(stlink_t *sl, stm32_addr_t addr) { - unsigned int val; - // set PC to the reset routine - stlink_read_debug32(sl, addr + 4, &val); - stlink_write_reg(sl, val, 15); - stlink_run(sl, RUN_NORMAL); -} - -int stlink_mwrite_sram(stlink_t *sl, uint8_t *data, uint32_t length, - stm32_addr_t addr) { - // write the file in sram at addr - - int error = -1; - size_t off; - size_t len; - - // check addr range is inside the sram - if (addr < sl->sram_base) { - fprintf(stderr, "addr too low\n"); - goto on_error; - } else if ((addr + length) < addr) { - fprintf(stderr, "addr overruns\n"); - goto on_error; - } else if ((addr + length) > (sl->sram_base + sl->sram_size)) { - fprintf(stderr, "addr too high\n"); - goto on_error; - } else if (addr & 3) { - fprintf(stderr, "unaligned addr\n"); - goto on_error; - } - - len = length; - - if (len & 3) { - len -= len & 3; - } - - // do the copy by 1kB blocks - for (off = 0; off < len; off += 1024) { - size_t size = 1024; - - if ((off + size) > len) { - size = len - off; - } - - memcpy(sl->q_buf, data + off, size); - - if (size & 3) { - size += 2; - } // round size if needed - - stlink_write_mem32(sl, addr + (uint32_t)off, (uint16_t)size); - } - - if (length > len) { - memcpy(sl->q_buf, data + len, length - len); - stlink_write_mem8(sl, addr + (uint32_t)len, (uint16_t)(length - len)); - } - - error = 0; // success - stlink_fwrite_finalize(sl, addr); - -on_error: - return (error); -} - -int stlink_fwrite_sram(stlink_t *sl, const char *path, stm32_addr_t addr) { - // write the file in sram at addr - - int error = -1; - size_t off; - size_t len; - mapped_file_t mf = MAPPED_FILE_INITIALIZER; - - if (map_file(&mf, path) == -1) { - fprintf(stderr, "map_file() == -1\n"); - return (-1); - } - - printf("file %s ", path); - md5_calculate(&mf); - stlink_checksum(&mf); - - // check if addr range is inside the SRAM - if (addr < sl->sram_base) { - fprintf(stderr, "addr too low\n"); - goto on_error; - } else if ((addr + mf.len) < addr) { - fprintf(stderr, "addr overruns\n"); - goto on_error; - } else if ((addr + mf.len) > (sl->sram_base + sl->sram_size)) { - fprintf(stderr, "addr too high\n"); - goto on_error; - } else if (addr & 3) { - fprintf(stderr, "unaligned addr\n"); - goto on_error; - } - - len = mf.len; - - if (len & 3) { - len -= len & 3; - } - - // do the copy by 1kB blocks - for (off = 0; off < len; off += 1024) { - size_t size = 1024; - - if ((off + size) > len) { - size = len - off; - } - - memcpy(sl->q_buf, mf.base + off, size); - - if (size & 3) { - size += 2; - } // round size if needed - - stlink_write_mem32(sl, addr + (uint32_t)off, (uint16_t)size); - } - - if (mf.len > len) { - memcpy(sl->q_buf, mf.base + len, mf.len - len); - stlink_write_mem8(sl, addr + (uint32_t)len, (uint16_t)(mf.len - len)); - } - - // check the file has been written - if (check_file(sl, &mf, addr) == -1) { - fprintf(stderr, "check_file() == -1\n"); - goto on_error; - } - - error = 0; // success - stlink_fwrite_finalize(sl, addr); - -on_error: - unmap_file(&mf); - return (error); -} - -typedef bool (*save_block_fn)(void *arg, uint8_t *block, ssize_t len); - -static int stlink_read(stlink_t *sl, stm32_addr_t addr, size_t size, - save_block_fn fn, void *fn_arg) { - - int error = -1; - - if (size < 1) { - size = sl->flash_size; - } - - if (size > sl->flash_size) { - size = sl->flash_size; - } - - size_t cmp_size = (sl->flash_pgsz > 0x1800) ? 0x1800 : sl->flash_pgsz; - - for (size_t off = 0; off < size; off += cmp_size) { - size_t aligned_size; - - // adjust last page size - if ((off + cmp_size) > size) { - cmp_size = size - off; - } - - aligned_size = cmp_size; - - if (aligned_size & (4 - 1)) { - aligned_size = (cmp_size + 4) & ~(4 - 1); - } - - stlink_read_mem32(sl, addr + (uint32_t)off, (uint16_t)aligned_size); - - if (!fn(fn_arg, sl->q_buf, aligned_size)) { - goto on_error; - } - } - - error = 0; // success - -on_error: - return (error); -} - -struct stlink_fread_worker_arg { - int fd; -}; - -static bool stlink_fread_worker(void *arg, uint8_t *block, ssize_t len) { - struct stlink_fread_worker_arg *the_arg = - (struct stlink_fread_worker_arg *)arg; - - if (write(the_arg->fd, block, len) != len) { - fprintf(stderr, "write() != aligned_size\n"); - return (false); - } else { - return (true); - } -} - -struct stlink_fread_ihex_worker_arg { - FILE *file; - uint32_t addr; - uint32_t lba; - uint8_t buf[16]; - uint8_t buf_pos; -}; - -static bool -stlink_fread_ihex_newsegment(struct stlink_fread_ihex_worker_arg *the_arg) { - uint32_t addr = the_arg->addr; - uint8_t sum = 2 + 4 + (uint8_t)((addr & 0xFF000000) >> 24) + - (uint8_t)((addr & 0x00FF0000) >> 16); - - if (17 != fprintf(the_arg->file, ":02000004%04X%02X\r\n", - (addr & 0xFFFF0000) >> 16, (uint8_t)(0x100 - sum))) { - return (false); - } - - the_arg->lba = (addr & 0xFFFF0000); - return (true); -} - -static bool -stlink_fread_ihex_writeline(struct stlink_fread_ihex_worker_arg *the_arg) { - uint8_t count = the_arg->buf_pos; - - if (count == 0) { - return (true); - } - - uint32_t addr = the_arg->addr; - - if (the_arg->lba != (addr & 0xFFFF0000)) { // segment changed - if (!stlink_fread_ihex_newsegment(the_arg)) { - return (false); - } - } - - uint8_t sum = count + (uint8_t)((addr & 0x0000FF00) >> 8) + - (uint8_t)(addr & 0x000000FF); - - if (9 != fprintf(the_arg->file, ":%02X%04X00", count, (addr & 0x0000FFFF))) { - return (false); - } - - for (uint8_t i = 0; i < count; ++i) { - uint8_t b = the_arg->buf[i]; - sum += b; - - if (2 != fprintf(the_arg->file, "%02X", b)) { - return (false); - } - } - - if (4 != fprintf(the_arg->file, "%02X\r\n", (uint8_t)(0x100 - sum))) { - return (false); - } - - the_arg->addr += count; - the_arg->buf_pos = 0; - - return (true); -} - -static bool stlink_fread_ihex_init(struct stlink_fread_ihex_worker_arg *the_arg, - int fd, stm32_addr_t addr) { - the_arg->file = fdopen(fd, "w"); - the_arg->addr = addr; - the_arg->lba = 0; - the_arg->buf_pos = 0; - - return (the_arg->file != NULL); -} - -static bool stlink_fread_ihex_worker(void *arg, uint8_t *block, ssize_t len) { - struct stlink_fread_ihex_worker_arg *the_arg = - (struct stlink_fread_ihex_worker_arg *)arg; - - for (ssize_t i = 0; i < len; ++i) { - if (the_arg->buf_pos == sizeof(the_arg->buf)) { // line is full - if (!stlink_fread_ihex_writeline(the_arg)) { - return (false); - } - } - - the_arg->buf[the_arg->buf_pos++] = block[i]; - } - - return (true); -} - -static bool -stlink_fread_ihex_finalize(struct stlink_fread_ihex_worker_arg *the_arg) { - if (!stlink_fread_ihex_writeline(the_arg)) { - return (false); - } - - // FIXME: do we need the Start Linear Address? - - if (13 != fprintf(the_arg->file, ":00000001FF\r\n")) { // EoF - return (false); - } - - return (0 == fclose(the_arg->file)); -} - -int stlink_fread(stlink_t *sl, const char *path, bool is_ihex, - stm32_addr_t addr, size_t size) { - // read size bytes from addr to file - ILOG("read from address %#010x size %u\n", addr, (unsigned)size); - - int error; - int fd = open(path, O_RDWR | O_TRUNC | O_CREAT | O_BINARY, 00700); - - if (fd == -1) { - fprintf(stderr, "open(%s) == -1\n", path); - return (-1); - } - - if (is_ihex) { - struct stlink_fread_ihex_worker_arg arg; - - if (stlink_fread_ihex_init(&arg, fd, addr)) { - error = stlink_read(sl, addr, size, &stlink_fread_ihex_worker, &arg); - - if (!stlink_fread_ihex_finalize(&arg)) { - error = -1; - } - } else { - error = -1; - } - } else { - struct stlink_fread_worker_arg arg = {fd}; - error = stlink_read(sl, addr, size, &stlink_fread_worker, &arg); - } - - close(fd); - return (error); -} - -int write_buffer_to_sram(stlink_t *sl, flash_loader_t *fl, const uint8_t *buf, - size_t size) { - // write the buffer right after the loader - int ret = 0; - size_t chunk = size & ~0x3; - size_t rem = size & 0x3; - - if (chunk) { - memcpy(sl->q_buf, buf, chunk); - ret = stlink_write_mem32(sl, fl->buf_addr, (uint16_t)chunk); - } - - if (rem && !ret) { - memcpy(sl->q_buf, buf + chunk, rem); - ret = stlink_write_mem8(sl, (fl->buf_addr) + (uint32_t)chunk, (uint16_t)rem); - } - - return (ret); -} - -uint32_t calculate_F4_sectornum(uint32_t flashaddr) { - uint32_t offset = 0; - flashaddr &= ~STM32_FLASH_BASE; // page now holding the actual flash address - - if (flashaddr >= 0x100000) { - offset = 12; - flashaddr -= 0x100000; - } - - if (flashaddr < 0x4000) { - return (offset + 0); - } else if (flashaddr < 0x8000) { - return (offset + 1); - } else if (flashaddr < 0xc000) { - return (offset + 2); - } else if (flashaddr < 0x10000) { - return (offset + 3); - } else if (flashaddr < 0x20000) { - return (offset + 4); - } else { - return (offset + (flashaddr / 0x20000) + 4); - } -} - -uint32_t calculate_F7_sectornum(uint32_t flashaddr) { - flashaddr &= ~STM32_FLASH_BASE; // Page now holding the actual flash address - - if (flashaddr < 0x20000) { - return (flashaddr / 0x8000); - } else if (flashaddr < 0x40000) { - return (4); - } else { - return ((flashaddr / 0x40000) + 4); - } -} - -uint32_t calculate_H7_sectornum(stlink_t *sl, uint32_t flashaddr, - unsigned bank) { - flashaddr &= - ~((bank == BANK_1) - ? STM32_FLASH_BASE - : STM32_H7_FLASH_BANK2_BASE); // sector holding the flash address - return (flashaddr / sl->flash_pgsz); -} - -// returns BKER:PNB for the given page address -uint32_t calculate_L4_page(stlink_t *sl, uint32_t flashaddr) { - uint32_t bker = 0; - uint32_t flashopt; - stlink_read_debug32(sl, STM32L4_FLASH_OPTR, &flashopt); - flashaddr -= STM32_FLASH_BASE; - - if (sl->chip_id == STLINK_CHIPID_STM32_L4 || - sl->chip_id == STLINK_CHIPID_STM32_L496x_L4A6x || - sl->chip_id == STLINK_CHIPID_STM32_L4Rx) { - // this chip use dual banked flash - if (flashopt & (uint32_t)(1lu << STM32L4_FLASH_OPTR_DUALBANK)) { - uint32_t banksize = (uint32_t)sl->flash_size / 2; - - if (flashaddr >= banksize) { - flashaddr -= banksize; - bker = 0x100; - } - } - } - - // For 1MB chips without the dual-bank option set, the page address will - // overflow into the BKER bit, which gives us the correct bank:page value. - return (bker | flashaddr / (uint32_t)sl->flash_pgsz); -} - -uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr) { - if ((sl->chip_id == STLINK_CHIPID_STM32_F2) || - (sl->chip_id == STLINK_CHIPID_STM32_F4) || - (sl->chip_id == STLINK_CHIPID_STM32_F4_DE) || - (sl->chip_id == STLINK_CHIPID_STM32_F4_LP) || - (sl->chip_id == STLINK_CHIPID_STM32_F4_HD) || - (sl->chip_id == STLINK_CHIPID_STM32_F411xx) || - (sl->chip_id == STLINK_CHIPID_STM32_F446) || - (sl->chip_id == STLINK_CHIPID_STM32_F4_DSI) || - (sl->chip_id == STLINK_CHIPID_STM32_F72xxx) || - (sl->chip_id == STLINK_CHIPID_STM32_F412)) { - uint32_t sector = calculate_F4_sectornum(flashaddr); - - if (sector >= 12) { - sector -= 12; - } - - if (sector < 4) { - sl->flash_pgsz = 0x4000; - } else if (sector < 5) { - sl->flash_pgsz = 0x10000; - } else { - sl->flash_pgsz = 0x20000; - } - } else if (sl->chip_id == STLINK_CHIPID_STM32_F7 || - sl->chip_id == STLINK_CHIPID_STM32_F76xxx) { - uint32_t sector = calculate_F7_sectornum(flashaddr); - - if (sector < 4) { - sl->flash_pgsz = 0x8000; - } else if (sector < 5) { - sl->flash_pgsz = 0x20000; - } else { - sl->flash_pgsz = 0x40000; - } - } - - return ((uint32_t)sl->flash_pgsz); -} - -/** - * Erase a page of flash, assumes sl is fully populated with things like - * chip/core ids - * @param sl stlink context - * @param flashaddr an address in the flash page to erase - * @return 0 on success -ve on failure - */ -int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { - // wait for ongoing op to finish - wait_flash_busy(sl); - // clear flash IO errors - clear_flash_error(sl); - - if (sl->flash_type == STLINK_FLASH_TYPE_F4 || - sl->flash_type == STLINK_FLASH_TYPE_F7 || - sl->flash_type == STLINK_FLASH_TYPE_L4) { - // unlock if locked - unlock_flash_if(sl); - - // select the page to erase - if ((sl->chip_id == STLINK_CHIPID_STM32_L4) || - (sl->chip_id == STLINK_CHIPID_STM32_L43x_L44x) || - (sl->chip_id == STLINK_CHIPID_STM32_L45x_L46x) || - (sl->chip_id == STLINK_CHIPID_STM32_L496x_L4A6x) || - (sl->chip_id == STLINK_CHIPID_STM32_L4Rx)) { - // calculate the actual bank+page from the address - uint32_t page = calculate_L4_page(sl, flashaddr); - - fprintf(stderr, "EraseFlash - Page:0x%x Size:0x%x ", page, - stlink_calculate_pagesize(sl, flashaddr)); - - write_flash_cr_bker_pnb(sl, page); - } else if (sl->chip_id == STLINK_CHIPID_STM32_F7 || - sl->chip_id == STLINK_CHIPID_STM32_F76xxx) { - // calculate the actual page from the address - uint32_t sector = calculate_F7_sectornum(flashaddr); - - fprintf(stderr, "EraseFlash - Sector:0x%x Size:0x%x ", sector, - stlink_calculate_pagesize(sl, flashaddr)); - write_flash_cr_snb(sl, sector, BANK_1); - } else { - // calculate the actual page from the address - uint32_t sector = calculate_F4_sectornum(flashaddr); - - fprintf(stderr, "EraseFlash - Sector:0x%x Size:0x%x ", sector, - stlink_calculate_pagesize(sl, flashaddr)); - - // the SNB values for flash sectors in the second bank do not directly - // follow the values for the first bank on 2mb devices... - if (sector >= 12) { - sector += 4; - } - - write_flash_cr_snb(sl, sector, BANK_1); - } - - set_flash_cr_strt(sl, BANK_1); // start erase operation - wait_flash_busy(sl); // wait for completion - lock_flash(sl); // TODO: fails to program if this is in -#if DEBUG_FLASH - fprintf(stdout, "Erase Final CR:0x%x\n", read_flash_cr(sl, BANK_1)); -#endif - } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { - - uint32_t val; - uint32_t flash_regs_base = get_stm32l0_flash_base(sl); - - // check if the locks are set - stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); - - if ((val & (1 << 0)) || (val & (1 << 1))) { - // disable pecr protection - stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, - FLASH_L0_PEKEY1); - stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, - FLASH_L0_PEKEY2); - - // check pecr.pelock is cleared - stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); - - if (val & (1 << 0)) { - WLOG("pecr.pelock not clear (%#x)\n", val); - return (-1); - } - - // unlock program memory - stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, - FLASH_L0_PRGKEY1); - stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, - FLASH_L0_PRGKEY2); - - // check pecr.prglock is cleared - stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); - - if (val & (1 << 1)) { - WLOG("pecr.prglock not clear (%#x)\n", val); - return (-1); - } - } - - // set pecr.{erase,prog} - val |= (1 << 9) | (1 << 3); - stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); - - // write 0 to the first word of the page to be erased - stlink_write_debug32(sl, flashaddr, 0); - - /* MP: It is better to wait for clearing the busy bit after issuing page - * erase command, even though PM0062 recommends to wait before it. - * Test shows that a few iterations is performed in the following loop - * before busy bit is cleared. - */ - wait_flash_busy(sl); - - // reset lock bits - stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); - val |= (1 << 0) | (1 << 1) | (1 << 2); - stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB || - sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { - uint32_t val; - unlock_flash_if(sl); - set_flash_cr_per(sl, BANK_1); // set the 'enable Flash erase' bit - - // set the page to erase - if (sl->flash_type == STLINK_FLASH_TYPE_WB) { - uint32_t flash_page = - ((flashaddr - STM32_FLASH_BASE) / (uint32_t)(sl->flash_pgsz)); - stlink_read_debug32(sl, STM32WB_FLASH_CR, &val); - - // sec 3.10.5 - PNB[7:0] is offset by 3. - val &= ~(0xFF << 3); // Clear previously set page number (if any) - val |= ((flash_page & 0xFF) << 3); - - stlink_write_debug32(sl, STM32WB_FLASH_CR, val); - } else if (sl->flash_type == STLINK_FLASH_TYPE_G0) { - uint32_t flash_page = - ((flashaddr - STM32_FLASH_BASE) / (uint32_t)(sl->flash_pgsz)); - stlink_read_debug32(sl, STM32Gx_FLASH_CR, &val); - // sec 3.7.5 - PNB[5:0] is offset by 3. PER is 0x2. - val &= ~(0x3F << 3); - val |= ((flash_page & 0x3F) << 3) | (1 << FLASH_CR_PER); - stlink_write_debug32(sl, STM32Gx_FLASH_CR, val); - } else if (sl->flash_type == STLINK_FLASH_TYPE_G4) { - uint32_t flash_page = - ((flashaddr - STM32_FLASH_BASE) / (uint32_t)(sl->flash_pgsz)); - stlink_read_debug32(sl, STM32Gx_FLASH_CR, &val); - // sec 3.7.5 - PNB[6:0] is offset by 3. PER is 0x2. - val &= ~(0x7F << 3); - val |= ((flash_page & 0x7F) << 3) | (1 << FLASH_CR_PER); - stlink_write_debug32(sl, STM32Gx_FLASH_CR, val); - } - - set_flash_cr_strt(sl, BANK_1); // set the 'start operation' bit - wait_flash_busy(sl); // wait for the 'busy' bit to clear - clear_flash_cr_per(sl, BANK_1); // clear the 'enable page erase' bit - lock_flash(sl); - } else if (sl->flash_type == STLINK_FLASH_TYPE_F0 || - sl->flash_type == STLINK_FLASH_TYPE_F1_XL) { - unsigned bank = (flashaddr < STM32_F1_FLASH_BANK2_BASE) ? BANK_1 : BANK_2; - unlock_flash_if(sl); - clear_flash_cr_pg(sl, bank); // clear the pg bit - set_flash_cr_per(sl, bank); // set the page erase bit - write_flash_ar(sl, flashaddr, bank); // select the page to erase - set_flash_cr_strt(sl, - bank); // start erase operation, reset by hw with busy bit - wait_flash_busy(sl); - clear_flash_cr_per(sl, bank); // clear the page erase bit - lock_flash(sl); - } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { - unsigned bank = (flashaddr < STM32_H7_FLASH_BANK2_BASE) ? BANK_1 : BANK_2; - unlock_flash_if(sl); // unlock if locked - uint32_t sector = calculate_H7_sectornum( - sl, flashaddr, bank); // calculate the actual page from the address - write_flash_cr_snb(sl, sector, bank); // select the page to erase - set_flash_cr_strt(sl, bank); // start erase operation - wait_flash_busy(sl); // wait for completion - lock_flash(sl); - } else { - WLOG("unknown coreid %x, page erase failed\n", sl->core_id); - return (-1); - } - - return check_flash_error(sl); -} - -// Check if an address and size are within the flash -int stlink_check_address_range_validity(stlink_t *sl, stm32_addr_t addr, size_t size) { - if (addr < sl->flash_base || addr >= (sl->flash_base + sl->flash_size)) { - ELOG("Invalid address, it should be within 0x%08x - 0x%08lx\n", sl->flash_base, (sl->flash_base + sl->flash_size -1)); - return (-1); - } - if ((addr + size) > (sl->flash_base + sl->flash_size)) { - ELOG("The size exceeds the size of the flash (0x%08lx bytes available)\n", (sl->flash_base + sl->flash_size - addr)); - return (-1); - } - return 0; -} - -// Check if an address is aligned with the beginning of a page -int stlink_check_address_alignment(stlink_t *sl, stm32_addr_t addr) { - stm32_addr_t page = sl->flash_base; - - while (page < addr) { - page += stlink_calculate_pagesize(sl, page); - } - - if (page != addr) { - return -1; - } - - return 0; -} - -int stlink_erase_flash_section(stlink_t *sl, stm32_addr_t base_addr, size_t size, bool align_size) { - // Check the address and size validity - if (stlink_check_address_range_validity(sl, base_addr, size) < 0) { - return -1; - } - - // Make sure the requested address is aligned with the beginning of a page - if (stlink_check_address_alignment(sl, base_addr) < 0) { - ELOG("The address to erase is not aligned with the beginning of a page\n"); - return -1; - } - - stm32_addr_t addr = base_addr; - do { - size_t page_size = stlink_calculate_pagesize(sl, addr); - - // Check if size is aligned with a page, unless we want to completely erase the last page - if ((addr + page_size) > (base_addr + size) && !align_size) { - ELOG("Invalid size (not aligned with a page). Page size at address %#x is %#lx\n", addr, page_size); - return -1; - } - - if (stlink_erase_flash_page(sl, addr)) { - WLOG("Failed to erase_flash_page(%#x) == -1\n", addr); - return (-1); - } - - fprintf(stdout, "-> Flash page at %#x erased (size: %#lx)\n", addr, page_size); - fflush(stdout); - - // check the next page is within the range to erase - addr += page_size; - } while (addr < (base_addr + size)); - - fprintf(stdout, "\n"); - return 0; -} - -int stlink_erase_flash_mass(stlink_t *sl) { - int err = 0; - - // TODO: User MER bit to mass-erase WB series. - if (sl->flash_type == STLINK_FLASH_TYPE_L0 || - sl->flash_type == STLINK_FLASH_TYPE_WB) { - - err = stlink_erase_flash_section(sl, sl->flash_base, sl->flash_size, false); - - } else { - wait_flash_busy(sl); - clear_flash_error(sl); - unlock_flash_if(sl); - - if (sl->flash_type == STLINK_FLASH_TYPE_H7 && - sl->chip_id != STLINK_CHIPID_STM32_H7Ax) { - // set parallelism - write_flash_cr_psiz(sl, 3 /*64it*/, BANK_1); - if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { - write_flash_cr_psiz(sl, 3 /*64bit*/, BANK_2); - } - } - - set_flash_cr_mer(sl, 1, BANK_1); // set the mass erase bit - set_flash_cr_strt( - sl, BANK_1); // start erase operation, reset by hw with busy bit - - if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL || - (sl->flash_type == STLINK_FLASH_TYPE_H7 && - sl->chip_flags & CHIP_F_HAS_DUAL_BANK)) { - set_flash_cr_mer(sl, 1, BANK_2); // set the mass erase bit in bank 2 - set_flash_cr_strt(sl, BANK_2); // start erase operation in bank 2 - } - - wait_flash_busy_progress(sl); - lock_flash(sl); - - // reset the mass erase bit - set_flash_cr_mer(sl, 0, BANK_1); - if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL || - (sl->flash_type == STLINK_FLASH_TYPE_H7 && - sl->chip_flags & CHIP_F_HAS_DUAL_BANK)) { - set_flash_cr_mer(sl, 0, BANK_2); - } - - err = check_flash_error(sl); - } - - return (err); -} - -int stlink_fcheck_flash(stlink_t *sl, const char *path, stm32_addr_t addr) { - // check the contents of path are at addr - - int res; - mapped_file_t mf = MAPPED_FILE_INITIALIZER; - - if (map_file(&mf, path) == -1) { - return (-1); - } - - res = check_file(sl, &mf, addr); - unmap_file(&mf); - return (res); -} - -/** - * Verify addr..addr+len is binary identical to base...base+len - * @param sl stlink context - * @param address stm device address - * @param data host side buffer to check against - * @param length how much - * @return 0 for success, -ve for failure - */ -int stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, - unsigned length) { - size_t off; - size_t cmp_size = (sl->flash_pgsz > 0x1800) ? 0x1800 : sl->flash_pgsz; - ILOG("Starting verification of write complete\n"); - - for (off = 0; off < length; off += cmp_size) { - size_t aligned_size; - - // adjust last page size - if ((off + cmp_size) > length) { - cmp_size = length - off; - } - - aligned_size = cmp_size; - - if (aligned_size & (4 - 1)) { - aligned_size = (cmp_size + 4) & ~(4 - 1); - } - - stlink_read_mem32(sl, address + (uint32_t)off, (uint16_t)aligned_size); - - if (memcmp(sl->q_buf, data + off, cmp_size)) { - ELOG("Verification of flash failed at offset: %u\n", (unsigned int)off); - return (-1); - } - } - - ILOG("Flash written and verified! jolly good!\n"); - return (0); -} - -int stm32l1_write_half_pages(stlink_t *sl, stm32_addr_t addr, uint8_t *base, - uint32_t len, uint32_t pagesize) { - unsigned int count, off; - unsigned int num_half_pages = len / pagesize; - uint32_t val; - uint32_t flash_regs_base = get_stm32l0_flash_base(sl); - flash_loader_t fl; - bool use_loader = true; - int ret = 0; - - // enable half page write - stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); - val |= (1 << FLASH_L1_FPRG); - stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); - val |= (1 << FLASH_L1_PROG); - stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); - - wait_flash_busy(sl); - - for (count = 0; count < num_half_pages; count++) { - if (use_loader) { - ret = stlink_flash_loader_run(sl, &fl, addr + count * pagesize, - base + count * pagesize, pagesize); - if (ret && count == 0) { - /* It seems that stm32lx devices have a problem when it is blank */ - WLOG("Failed to use flash loader, fallback to soft write\n"); - use_loader = false; - } - } - if (!use_loader) { - ret = 0; - for (off = 0; off < pagesize && !ret; off += 64) { - size_t chunk = (pagesize - off > 64) ? 64 : pagesize - off; - memcpy(sl->q_buf, base + count * pagesize + off, chunk); - ret = stlink_write_mem32(sl, addr + count * pagesize + off, (uint16_t)chunk); - } - } - - if (ret) { - WLOG("l1_stlink_flash_loader_run(%#x) failed! == -1\n", - addr + count * pagesize); - break; - } - - if (sl->verbose >= 1) { - // show progress; writing procedure is slow and previous errors are - // misleading - fprintf(stdout, "\r%3u/%u halfpages written", count + 1, num_half_pages); - fflush(stdout); - } - - // wait for sr.busy to be cleared - wait_flash_busy(sl); - } - - // disable half page write - stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); - val &= ~((1 << FLASH_L1_FPRG) | (1 << FLASH_L1_PROG)); - stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); - return (ret); -} - -int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { - // disable DMA - set_dma_state(sl, fl, 0); - - // wait for ongoing op to finish - wait_flash_busy(sl); - // Clear errors - clear_flash_error(sl); - - if ((sl->flash_type == STLINK_FLASH_TYPE_F4) || - (sl->flash_type == STLINK_FLASH_TYPE_F7) || - (sl->flash_type == STLINK_FLASH_TYPE_L4)) { - ILOG("Starting Flash write for F2/F4/F7/L4\n"); - - // Flash loader initialisation - if (stlink_flash_loader_init(sl, fl) == -1) { - ELOG("stlink_flash_loader_init() == -1\n"); - return (-1); - } - - unlock_flash_if(sl); // first unlock the cr - - int voltage; - if (sl->version.stlink_v == 1) { - WLOG("STLINK V1 cannot read voltage, use default voltage 3.2V\n"); - voltage = 3200; - } else { - voltage = stlink_target_voltage(sl); - } - - if (voltage == -1) { - ELOG("Failed to read Target voltage\n"); - return (-1); - } - - if (sl->flash_type == STLINK_FLASH_TYPE_L4) { - // L4 does not have a byte-write mode - if (voltage < 1710) { - ELOG("Target voltage (%d mV) too low for flash writes!\n", voltage); - return (-1); - } - } else { - if (voltage > 2700) { - ILOG("enabling 32-bit flash writes\n"); - write_flash_cr_psiz(sl, 2, BANK_1); - } else { - ILOG("Target voltage (%d mV) too low for 32-bit flash, " - "using 8-bit flash writes\n", - voltage); - write_flash_cr_psiz(sl, 0, BANK_1); - } - } - - // set programming mode - set_flash_cr_pg(sl, BANK_1); - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB || - sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { - ILOG("Starting Flash write for WB/G0/G4\n"); - - unlock_flash_if(sl); // unlock flash if necessary - set_flash_cr_pg(sl, BANK_1); // set PG 'allow programming' bit - } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { - ILOG("Starting Flash write for L0\n"); - - uint32_t val; - uint32_t flash_regs_base = get_stm32l0_flash_base(sl); - - // disable pecr protection - stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, - FLASH_L0_PEKEY1); - stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, - FLASH_L0_PEKEY2); - - // check pecr.pelock is cleared - stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); - if (val & (1 << 0)) { - ELOG("pecr.pelock not clear\n"); - return (-1); - } - - // unlock program memory - stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, - FLASH_L0_PRGKEY1); - stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, - FLASH_L0_PRGKEY2); - - // check pecr.prglock is cleared - stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); - if (val & (1 << 1)) { - ELOG("pecr.prglock not clear\n"); - return (-1); - } - - /* Flash loader initialisation */ - if (stlink_flash_loader_init(sl, fl) == -1) { - // L0/L1 have fallback to soft write - WLOG("stlink_flash_loader_init() == -1\n"); - } - } else if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || - (sl->flash_type == STLINK_FLASH_TYPE_F1_XL)) { - ILOG("Starting Flash write for VL/F0/F3/F1_XL\n"); - - // flash loader initialisation - if (stlink_flash_loader_init(sl, fl) == -1) { - ELOG("stlink_flash_loader_init() == -1\n"); - return (-1); - } - - // unlock flash - unlock_flash_if(sl); - - // set programming mode - set_flash_cr_pg(sl, BANK_1); - if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL) { - set_flash_cr_pg(sl, BANK_2); - } - } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { - ILOG("Starting Flash write for H7\n"); - - unlock_flash_if(sl); // unlock the cr - set_flash_cr_pg(sl, BANK_1); // set programming mode - if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { - set_flash_cr_pg(sl, BANK_2); - } - if (sl->chip_id != STLINK_CHIPID_STM32_H7Ax) { - // set parallelism - write_flash_cr_psiz(sl, 3 /*64it*/, BANK_1); - if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { - write_flash_cr_psiz(sl, 3 /*64bit*/, BANK_2); - } - } - } else { - ELOG("unknown coreid, not sure how to write: %x\n", sl->core_id); - return (-1); - } - - return (0); -} - -int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, - stm32_addr_t addr, uint8_t *base, uint32_t len) { - size_t off; - if ((sl->flash_type == STLINK_FLASH_TYPE_F4) || - (sl->flash_type == STLINK_FLASH_TYPE_F7) || - (sl->flash_type == STLINK_FLASH_TYPE_L4)) { - size_t buf_size = (sl->sram_size > 0x8000) ? 0x8000 : 0x4000; - for (off = 0; off < len;) { - size_t size = len - off > buf_size ? buf_size : len - off; - if (stlink_flash_loader_run(sl, fl, addr + (uint32_t)off, base + off, - size) == -1) { - ELOG("stlink_flash_loader_run(%#x) failed! == -1\n", - (unsigned)(addr + off)); - check_flash_error(sl); - return (-1); - } - - off += size; - } - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB || - sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { - DLOG("Starting %3u page write\r\n", (unsigned int)(len / sl->flash_pgsz)); - for (off = 0; off < len; off += sizeof(uint32_t)) { - uint32_t data; - - if ((off % sl->flash_pgsz) > (sl->flash_pgsz - 5)) { - fprintf(stdout, "\r%3u/%3u pages written", - (unsigned int)(off / sl->flash_pgsz), - (unsigned int)(len / sl->flash_pgsz)); - fflush(stdout); - } - - write_uint32((unsigned char *)&data, *(uint32_t *)(base + off)); - stlink_write_debug32(sl, addr + (uint32_t)off, data); - wait_flash_busy(sl); // wait for 'busy' bit in FLASH_SR to clear - } - fprintf(stdout, "\n"); - - // flash writes happen as 2 words at a time - if ((off / sizeof(uint32_t)) % 2 != 0) { - stlink_write_debug32(sl, addr + (uint32_t)off, - 0); // write a single word of zeros - wait_flash_busy(sl); // wait for 'busy' bit in FLASH_SR to clear - } - } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { - uint32_t val; - uint32_t flash_regs_base = get_stm32l0_flash_base(sl); - uint32_t pagesize = (flash_regs_base==STM32L0_FLASH_REGS_ADDR)? - L0_WRITE_BLOCK_SIZE:L1_WRITE_BLOCK_SIZE; - - DLOG("Starting %3u page write\r\n", (unsigned int)(len / sl->flash_pgsz)); - - off = 0; - - if (len > pagesize) { - if (stm32l1_write_half_pages(sl, addr, base, len, pagesize)) { - return (-1); - } else { - off = (size_t)(len / pagesize) * pagesize; - } - } - - // write remaining word in program memory - for (; off < len; off += sizeof(uint32_t)) { - uint32_t data; - - if ((off % sl->flash_pgsz) > (sl->flash_pgsz - 5)) { - fprintf(stdout, "\r%3u/%3u pages written", - (unsigned int)(off / sl->flash_pgsz), - (unsigned int)(len / sl->flash_pgsz)); - fflush(stdout); - } - - write_uint32((unsigned char *)&data, *(uint32_t *)(base + off)); - stlink_write_debug32(sl, addr + (uint32_t)off, data); - - // wait for sr.busy to be cleared - do { - stlink_read_debug32(sl, flash_regs_base + FLASH_SR_OFF, &val); - } while ((val & (1 << 0)) != 0); - - // TODO: check redo write operation - } - fprintf(stdout, "\n"); - } else if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || - (sl->flash_type == STLINK_FLASH_TYPE_F1_XL)) { - int write_block_count = 0; - for (off = 0; off < len; off += sl->flash_pgsz) { - // adjust last write size - size_t size = len - off > sl->flash_pgsz ? sl->flash_pgsz : len - off; - - // unlock and set programming mode - unlock_flash_if(sl); - - DLOG("Finished unlocking flash, running loader!\n"); - - if (stlink_flash_loader_run(sl, fl, addr + (uint32_t)off, base + off, - size) == -1) { - ELOG("stlink_flash_loader_run(%#x) failed! == -1\n", - (unsigned)(addr + off)); - check_flash_error(sl); - return (-1); - } - - lock_flash(sl); - - if (sl->verbose >= 1) { - // show progress; writing procedure is slow and previous errors are - // misleading - fprintf(stdout, "\r%3u/%3u pages written", ++write_block_count, - (unsigned int)((len + sl->flash_pgsz - 1) / sl->flash_pgsz)); - fflush(stdout); - } - } - if (sl->verbose >= 1) { - fprintf(stdout, "\n"); - } - } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { - for (off = 0; off < len;) { - // Program STM32H7x with 64-byte Flash words - size_t chunk = (len - off > 64) ? 64 : len - off; - memcpy(sl->q_buf, base + off, chunk); - stlink_write_mem32(sl, addr + (uint32_t)off, 64); - wait_flash_busy(sl); - - off += chunk; - - if (sl->verbose >= 1) { - // show progress - fprintf(stdout, "\r%u/%u bytes written", (unsigned int)off, - (unsigned int)len); - fflush(stdout); - } - } - if (sl->verbose >= 1) { - fprintf(stdout, "\n"); - } - } else { - return (-1); - } - - return check_flash_error(sl); -} - -int stlink_flashloader_stop(stlink_t *sl, flash_loader_t *fl) { - uint32_t dhcsr; - - if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || - (sl->flash_type == STLINK_FLASH_TYPE_F1_XL) || - (sl->flash_type == STLINK_FLASH_TYPE_F4) || - (sl->flash_type == STLINK_FLASH_TYPE_F7) || - (sl->flash_type == STLINK_FLASH_TYPE_L4) || - (sl->flash_type == STLINK_FLASH_TYPE_WB) || - (sl->flash_type == STLINK_FLASH_TYPE_G0) || - (sl->flash_type == STLINK_FLASH_TYPE_G4) || - (sl->flash_type == STLINK_FLASH_TYPE_H7)) { - - clear_flash_cr_pg(sl, BANK_1); - if ((sl->flash_type == STLINK_FLASH_TYPE_H7 && - sl->chip_flags & CHIP_F_HAS_DUAL_BANK) || - sl->flash_type == STLINK_FLASH_TYPE_F1_XL) { - clear_flash_cr_pg(sl, BANK_2); - } - lock_flash(sl); - } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { - uint32_t val; - uint32_t flash_regs_base = get_stm32l0_flash_base(sl); - - // reset lock bits - stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); - val |= (1 << 0) | (1 << 1) | (1 << 2); - stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); - } - - // enable interrupt - if (!stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr)) { - stlink_write_debug32(sl, STLINK_REG_DHCSR, - STLINK_REG_DHCSR_DBGKEY | STLINK_REG_DHCSR_C_DEBUGEN | - (dhcsr & (~STLINK_REG_DHCSR_C_MASKINTS))); - } - - // restore DMA state - set_dma_state(sl, fl, 1); - - return (0); -} - -int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t *base, - uint32_t len, uint8_t eraseonly) { - int ret; - flash_loader_t fl; - ILOG("Attempting to write %d (%#x) bytes to stm32 address: %u (%#x)\n", len, - len, addr, addr); - // check addr range is inside the flash - stlink_calculate_pagesize(sl, addr); - - // Check the address and size validity - if (stlink_check_address_range_validity(sl, addr, len) < 0) { - return (-1); - } else if (len & 1) { - WLOG("unaligned len 0x%x -- padding with zero\n", len); - len += 1; - } else if (stlink_check_address_alignment(sl, addr) < 0) { - ELOG("addr not a multiple of current pagesize (%u bytes), not supported, " - "check page start address and compare with flash module organisation " - "in related ST reference manual of your device.\n", - (unsigned)(sl->flash_pgsz)); - return (-1); - } - - // make sure we've loaded the context with the chip details - stlink_core_id(sl); - - // Erase this section of the flash - if (stlink_erase_flash_section(sl, addr, len, true) < 0) { - ELOG("Failed to erase the flash prior to writing\n"); - return (-1); - } - - if (eraseonly) { - return (0); - } - - ret = stlink_flashloader_start(sl, &fl); - if (ret) - return ret; - ret = stlink_flashloader_write(sl, &fl, addr, base, len); - if (ret) - return ret; - ret = stlink_flashloader_stop(sl, &fl); - if (ret) - return ret; - - return (stlink_verify_write_flash(sl, addr, base, len)); -} - -// TODO: length not checked -static uint8_t stlink_parse_hex(const char *hex) { - uint8_t d[2]; - - for (int i = 0; i < 2; ++i) { - char c = *(hex + i); - - if (c >= '0' && c <= '9') { - d[i] = c - '0'; - } else if (c >= 'A' && c <= 'F') { - d[i] = c - 'A' + 10; - } else if (c >= 'a' && c <= 'f') { - d[i] = c - 'a' + 10; - } else { - return (0); // error - } - } - - return ((d[0] << 4) | (d[1])); -} - -int stlink_parse_ihex(const char *path, uint8_t erased_pattern, uint8_t **mem, - size_t *size, uint32_t *begin) { - int res = 0; - *begin = UINT32_MAX; - uint8_t *data = NULL; - uint32_t end = 0; - bool eof_found = false; - - for (int scan = 0; (res == 0) && (scan < 2); ++scan) { - // parse file two times - first to find memory range, second - to fill it - if (scan == 1) { - if (!eof_found) { - ELOG("No EoF recond\n"); - res = -1; - break; - } - - if (*begin >= end) { - ELOG("No data found in file\n"); - res = -1; - break; - } - - *size = (end - *begin) + 1; - data = calloc(*size, 1); // use calloc to get NULL if out of memory - - if (!data) { - ELOG("Cannot allocate %u bytes\n", (unsigned)(*size)); - res = -1; - break; - } - - memset(data, erased_pattern, *size); - } - - FILE *file = fopen(path, "r"); - - if (!file) { - ELOG("Cannot open file\n"); - res = -1; - break; - } - - uint32_t lba = 0; - char line[1 + 5 * 2 + 255 * 2 + 2]; - - while (fgets(line, sizeof(line), file)) { - if (line[0] == '\n' || line[0] == '\r') { - continue; - } // skip empty lines - - if (line[0] != ':') { // no marker - wrong file format - ELOG("Wrong file format - no marker\n"); - res = -1; - break; - } - - size_t l = strlen(line); - - while (l > 0 && (line[l - 1] == '\n' || line[l - 1] == '\r')) { - --l; - } // trim EoL - - if ((l < 11) || - (l == - (sizeof(line) - 1))) { // line too short or long - wrong file format - ELOG("Wrong file format - wrong line length\n"); - res = -1; - break; - } - - uint8_t chksum = 0; // check sum - - for (size_t i = 1; i < l; i += 2) { - chksum += stlink_parse_hex(line + i); - } - - if (chksum != 0) { - ELOG("Wrong file format - checksum mismatch\n"); - res = -1; - break; - } - - uint8_t reclen = stlink_parse_hex(line + 1); - - if (((uint32_t)reclen + 5) * 2 + 1 != l) { - ELOG("Wrong file format - record length mismatch\n"); - res = -1; - break; - } - - uint16_t offset = ((uint16_t)stlink_parse_hex(line + 3) << 8) | - ((uint16_t)stlink_parse_hex(line + 5)); - uint8_t rectype = stlink_parse_hex(line + 7); - - switch (rectype) { - case 0: /* Data */ - if (scan == 0) { - uint32_t b = lba + offset; - uint32_t e = b + reclen - 1; - - if (b < *begin) { - *begin = b; - } - - if (e > end) { - end = e; - } - } else { - for (uint8_t i = 0; i < reclen; ++i) { - uint8_t b = stlink_parse_hex(line + 9 + i * 2); - uint32_t addr = lba + offset + i; - - if (addr >= *begin && addr <= end) { - data[addr - *begin] = b; - } - } - } - break; - case 1: /* EoF */ - eof_found = true; - break; - case 2: /* Extended Segment Address, unexpected */ - res = -1; - break; - case 3: /* Start Segment Address, unexpected */ - res = -1; - break; - case 4: /* Extended Linear Address */ - if (reclen == 2) { - lba = ((uint32_t)stlink_parse_hex(line + 9) << 24) | - ((uint32_t)stlink_parse_hex(line + 11) << 16); - } else { - ELOG("Wrong file format - wrong LBA length\n"); - res = -1; - } - break; - case 5: /* Start Linear Address - expected, but ignore */ - break; - default: - ELOG("Wrong file format - unexpected record type %d\n", rectype); - res = -1; - } - - if (res != 0) { - break; - } - } - - fclose(file); - } - - if (res == 0) { - *mem = data; - } else { - free(data); - } - - return (res); -} - -uint8_t stlink_get_erased_pattern(stlink_t *sl) { - if (sl->flash_type == STLINK_FLASH_TYPE_L0) { - return (0x00); - } else { - return (0xff); - } -} - -int stlink_mwrite_flash(stlink_t *sl, uint8_t *data, uint32_t length, - stm32_addr_t addr) { - /* Write the block in flash at addr */ - int err; - unsigned int num_empty, idx; - uint8_t erased_pattern = stlink_get_erased_pattern(sl); - - /* - * This optimisation may cause unexpected garbage data remaining. - * Therfore it is turned off by default. - */ - if (sl->opt) { - idx = (unsigned int)length; - - for (num_empty = 0; num_empty != length; ++num_empty) - if (data[--idx] != erased_pattern) { - break; - } - - num_empty -= (num_empty & 3); // Round down to words - - if (num_empty != 0) { - ILOG("Ignoring %d bytes of 0x%02x at end of file\n", num_empty, - erased_pattern); - } - } else { - num_empty = 0; - } - - /* - * TODO: investigate a kind of weird behaviour here: - * If the file is identified to be all-empty and four-bytes aligned, - * still flash the whole file even if ignoring message is printed. - */ - err = stlink_write_flash(sl, addr, data, - (num_empty == length) ? (uint32_t)length - : (uint32_t)length - num_empty, - num_empty == length); - stlink_fwrite_finalize(sl, addr); - return (err); -} - -/** - * Write the given binary file into flash at address "addr" - * @param sl - * @param path readable file path, should be binary image - * @param addr where to start writing - * @return 0 on success, -ve on failure. - */ -int stlink_fwrite_flash(stlink_t *sl, const char *path, stm32_addr_t addr) { - /* Write the file in flash at addr */ - int err; - unsigned int num_empty, idx; - uint8_t erased_pattern = stlink_get_erased_pattern(sl); - mapped_file_t mf = MAPPED_FILE_INITIALIZER; + int error; + int fd = open(path, O_RDWR | O_TRUNC | O_CREAT | O_BINARY, 00700); - if (map_file(&mf, path) == -1) { - ELOG("map_file() == -1\n"); + if (fd == -1) { + fprintf(stderr, "open(%s) == -1\n", path); return (-1); } - printf("file %s ", path); - md5_calculate(&mf); - stlink_checksum(&mf); + if (is_ihex) { + struct stlink_fread_ihex_worker_arg arg; - if (sl->opt) { - idx = (unsigned int)mf.len; + if (stlink_fread_ihex_init(&arg, fd, addr)) { + error = stlink_read(sl, addr, size, &stlink_fread_ihex_worker, &arg); - for (num_empty = 0; num_empty != mf.len; ++num_empty) { - if (mf.base[--idx] != erased_pattern) { - break; + if (!stlink_fread_ihex_finalize(&arg)) { + error = -1; } - } - - num_empty -= (num_empty & 3); // round down to words - - if (num_empty != 0) { - ILOG("Ignoring %d bytes of 0x%02x at end of file\n", num_empty, - erased_pattern); + } else { + error = -1; } } else { - num_empty = 0; + struct stlink_fread_worker_arg arg = {fd}; + error = stlink_read(sl, addr, size, &stlink_fread_worker, &arg); } - /* - * TODO: investigate a kind of weird behaviour here: - * If the file is identified to be all-empty and four-bytes aligned, - * still flash the whole file even if ignoring message is printed. - */ - err = stlink_write_flash(sl, addr, mf.base, - (num_empty == mf.len) ? (uint32_t)mf.len - : (uint32_t)mf.len - num_empty, - num_empty == mf.len); - stlink_fwrite_finalize(sl, addr); - unmap_file(&mf); - return (err); + close(fd); + return (error); } - -/** - * Write option bytes - * @param sl - * @param base option bytes to write - * @param addr of the memory mapped option bytes - * @param len of options bytes to write - * @return 0 on success, -ve on failure. - */ -static int stlink_write_option_bytes_f0( - stlink_t *sl, uint8_t* base, stm32_addr_t addr, uint32_t len) { +// 300 +int write_buffer_to_sram(stlink_t *sl, flash_loader_t *fl, const uint8_t *buf, + size_t size) { + // write the buffer right after the loader int ret = 0; + size_t chunk = size & ~0x3; + size_t rem = size & 0x3; - if (len < 12 || addr != STM32_F0_OPTION_BYTES_BASE) { - WLOG("Only full write of option bytes area is supported\n"); - return -1; - } - - clear_flash_error(sl); - - WLOG("Erasing option bytes\n"); - - /* erase option bytes */ - stlink_write_debug32(sl, FLASH_CR, (1 << FLASH_CR_OPTER) | (1 << FLASH_CR_OPTWRE)); - ret = stlink_write_debug32(sl, FLASH_CR, (1 << FLASH_CR_OPTER) | (1 << FLASH_CR_STRT) | (1 << FLASH_CR_OPTWRE)); - if (ret) { - return ret; - } - - wait_flash_busy(sl); - - ret = check_flash_error(sl); - if (ret) { - return ret; - } - - WLOG("Writing option bytes to %#10x\n", addr); - - /* Set the Option PG bit to enable programming */ - stlink_write_debug32(sl, FLASH_CR, (1 << FLASH_CR_OPTPG) | (1 << FLASH_CR_OPTWRE)); - - /* Use flash loader for write OP - * because flash memory writable by half word */ - flash_loader_t fl; - ret = stlink_flash_loader_init(sl, &fl); - if (ret) { - return ret; - } - ret = stlink_flash_loader_run(sl, &fl, addr, base, len); - if (ret) { - return ret; + if (chunk) { + memcpy(sl->q_buf, buf, chunk); + ret = stlink_write_mem32(sl, fl->buf_addr, (uint16_t)chunk); } - /* Reload option bytes */ - stlink_write_debug32(sl, FLASH_CR, (1 << FLASH_CR_OBL_LAUNCH)); - - return check_flash_error(sl); -} - -/** - * Write option bytes - * @param sl - * @param addr of the memory mapped option bytes - * @param base option bytes to write - * @return 0 on success, -ve on failure. - */ -static int stlink_write_option_bytes_gx(stlink_t *sl, uint8_t *base, - stm32_addr_t addr, uint32_t len) { - /* Write options bytes */ - uint32_t val; - int ret = 0; - (void)len; - uint32_t data; - - clear_flash_error(sl); - - write_uint32((unsigned char *)&data, *(uint32_t *)(base)); - WLOG("Writing option bytes %#10x to %#10x\n", data, addr); - stlink_write_debug32(sl, STM32Gx_FLASH_OPTR, data); - - // Set Options Start bit - stlink_read_debug32(sl, STM32Gx_FLASH_CR, &val); - val |= (1 << STM32Gx_FLASH_CR_OPTSTRT); - stlink_write_debug32(sl, STM32Gx_FLASH_CR, val); - - wait_flash_busy(sl); - - ret = check_flash_error(sl); - - // Reload options - stlink_read_debug32(sl, STM32Gx_FLASH_CR, &val); - val |= (1 << STM32Gx_FLASH_CR_OBL_LAUNCH); - stlink_write_debug32(sl, STM32Gx_FLASH_CR, val); - - return (ret); -} - -/** - * Write option bytes - * @param sl - * @param addr of the memory mapped option bytes - * @param base option bytes to write - * @return 0 on success, -ve on failure. - */ -static int stlink_write_option_bytes_l0(stlink_t *sl, uint8_t *base, - stm32_addr_t addr, uint32_t len) { - uint32_t flash_base = get_stm32l0_flash_base(sl); - uint32_t val; - uint32_t data; - int ret = 0; - - // Clear errors - clear_flash_error(sl); - - while (len != 0) { - write_uint32((unsigned char *)&data, - *(uint32_t *)(base)); // write options bytes - - WLOG("Writing option bytes %#10x to %#10x\n", data, addr); - stlink_write_debug32(sl, addr, data); - wait_flash_busy(sl); - - if ((ret = check_flash_error(sl))) { - break; - } - - len -= 4; - addr += 4; - base += 4; + if (rem && !ret) { + memcpy(sl->q_buf, buf + chunk, rem); + ret = stlink_write_mem8(sl, (fl->buf_addr) + (uint32_t)chunk, (uint16_t)rem); } - // Reload options - stlink_read_debug32(sl, flash_base + FLASH_PECR_OFF, &val); - val |= (1 << STM32L0_FLASH_OBL_LAUNCH); - stlink_write_debug32(sl, flash_base + FLASH_PECR_OFF, val); - - return (ret); -} - -/** - * Write option bytes - * @param sl - * @param addr of the memory mapped option bytes - * @param base option bytes to write - * @return 0 on success, -ve on failure. - */ -static int stlink_write_option_bytes_l4(stlink_t *sl, uint8_t *base, - stm32_addr_t addr, uint32_t len) { - - uint32_t val; - int ret = 0; - (void)addr; - (void)len; - - // Clear errors - clear_flash_error(sl); - - // write options bytes - uint32_t data; - write_uint32((unsigned char *)&data, *(uint32_t *)(base)); - WLOG("Writing option bytes 0x%04x\n", data); - stlink_write_debug32(sl, STM32L4_FLASH_OPTR, data); - - // set options start bit - stlink_read_debug32(sl, STM32L4_FLASH_CR, &val); - val |= (1 << STM32L4_FLASH_CR_OPTSTRT); - stlink_write_debug32(sl, STM32L4_FLASH_CR, val); - - wait_flash_busy(sl); - ret = check_flash_error(sl); - - // apply options bytes immediate - stlink_read_debug32(sl, STM32L4_FLASH_CR, &val); - val |= (1 << STM32L4_FLASH_CR_OBL_LAUNCH); - stlink_write_debug32(sl, STM32L4_FLASH_CR, val); - - return (ret); -} - -/** - * Write option bytes - * @param sl - * @param option_byte value to write - * @return 0 on success, -ve on failure. - */ -static int stlink_write_option_bytes_f4(stlink_t *sl, uint8_t *base, - stm32_addr_t addr, uint32_t len) { - uint32_t option_byte; - int ret = 0; - (void)addr; - (void)len; - - // Clear errors - clear_flash_error(sl); - - write_uint32((unsigned char *)&option_byte, *(uint32_t *)(base)); - - // write option byte, ensuring we dont lock opt, and set strt bit - stlink_write_debug32(sl, FLASH_F4_OPTCR, - (option_byte & ~(1 << FLASH_F4_OPTCR_LOCK)) | - (1 << FLASH_F4_OPTCR_START)); - - wait_flash_busy(sl); - ret = check_flash_error(sl); - - // option bytes are reloaded at reset only, no obl. */ return (ret); } +// 291 +uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr) { + if ((sl->chip_id == STLINK_CHIPID_STM32_F2) || + (sl->chip_id == STLINK_CHIPID_STM32_F4) || + (sl->chip_id == STLINK_CHIPID_STM32_F4_DE) || + (sl->chip_id == STLINK_CHIPID_STM32_F4_LP) || + (sl->chip_id == STLINK_CHIPID_STM32_F4_HD) || + (sl->chip_id == STLINK_CHIPID_STM32_F411xx) || + (sl->chip_id == STLINK_CHIPID_STM32_F446) || + (sl->chip_id == STLINK_CHIPID_STM32_F4_DSI) || + (sl->chip_id == STLINK_CHIPID_STM32_F72xxx) || + (sl->chip_id == STLINK_CHIPID_STM32_F412)) { + uint32_t sector = calculate_F4_sectornum(flashaddr); -/** - * Write option bytes - * @param sl - * @param option_byte value to write - * @return 0 on success, -ve on failure. - */ -static int stlink_write_option_bytes_f7(stlink_t *sl, uint8_t *base, - stm32_addr_t addr, uint32_t len) { - uint32_t option_byte; - int ret = 0; - - // Clear errors - clear_flash_error(sl); - - ILOG("Asked to write option byte %#10x to %#010x.\n", *(uint32_t *)(base), - addr); - write_uint32((unsigned char *)&option_byte, *(uint32_t *)(base)); - ILOG("Write %d option bytes %#010x to %#010x!\n", len, option_byte, addr); + if (sector >= 12) { + sector -= 12; + } - if (addr == 0) { - addr = FLASH_F7_OPTCR; - ILOG("No address provided, using %#10x\n", addr); - } + if (sector < 4) { + sl->flash_pgsz = 0x4000; + } else if (sector < 5) { + sl->flash_pgsz = 0x10000; + } else { + sl->flash_pgsz = 0x20000; + } + } else if (sl->chip_id == STLINK_CHIPID_STM32_F7 || + sl->chip_id == STLINK_CHIPID_STM32_F76xxx) { + uint32_t sector = calculate_F7_sectornum(flashaddr); - if (addr == FLASH_F7_OPTCR) { - /* write option byte, ensuring we dont lock opt, and set strt bit */ - stlink_write_debug32(sl, FLASH_F7_OPTCR, - (option_byte & ~(1 << FLASH_F7_OPTCR_LOCK)) | - (1 << FLASH_F7_OPTCR_START)); - } else if (addr == FLASH_F7_OPTCR1) { - // Read FLASH_F7_OPTCR - uint32_t oldvalue; - stlink_read_debug32(sl, FLASH_F7_OPTCR, &oldvalue); - /* write option byte */ - stlink_write_debug32(sl, FLASH_F7_OPTCR1, option_byte); - // Write FLASH_F7_OPTCR lock and start address - stlink_write_debug32(sl, FLASH_F7_OPTCR, - (oldvalue & ~(1 << FLASH_F7_OPTCR_LOCK)) | - (1 << FLASH_F7_OPTCR_START)); - } else { - WLOG("WIP: write %#010x to address %#010x\n", option_byte, addr); - stlink_write_debug32(sl, addr, option_byte); + if (sector < 4) { + sl->flash_pgsz = 0x8000; + } else if (sector < 5) { + sl->flash_pgsz = 0x20000; + } else { + sl->flash_pgsz = 0x40000; + } } - wait_flash_busy(sl); - - ret = check_flash_error(sl); - if (!ret) - ILOG("Wrote %d option bytes %#010x to %#010x!\n", len, *(uint32_t *)base, - addr); - - /* option bytes are reloaded at reset only, no obl. */ - - return ret; + return ((uint32_t)sl->flash_pgsz); } +// 279 +int stlink_parse_ihex(const char *path, uint8_t erased_pattern, uint8_t **mem, + size_t *size, uint32_t *begin) { + int res = 0; + *begin = UINT32_MAX; + uint8_t *data = NULL; + uint32_t end = 0; + bool eof_found = false; -/** - * Write STM32H7xx option bytes - * @param sl - * @param base option bytes to write - * @param addr of the memory mapped option bytes - * @param len number of bytes to write (must be multiple of 4) - * @return 0 on success, -ve on failure. - */ -static int stlink_write_option_bytes_h7(stlink_t *sl, uint8_t *base, - stm32_addr_t addr, uint32_t len) { - uint32_t val; - uint32_t data; - - // Wait until previous flash option has completed - wait_flash_busy(sl); - - // Clear previous error - stlink_write_debug32(sl, FLASH_H7_OPTCCR, - 1 << FLASH_H7_OPTCCR_CLR_OPTCHANGEERR); - - while (len != 0) { - switch (addr) { - case FLASH_H7_REGS_ADDR + 0x20: // FLASH_OPTSR_PRG - case FLASH_H7_REGS_ADDR + 0x2c: // FLASH_PRAR_PRG1 - case FLASH_H7_REGS_ADDR + 0x34: // FLASH_SCAR_PRG1 - case FLASH_H7_REGS_ADDR + 0x3c: // FLASH_WPSN_PRG1 - case FLASH_H7_REGS_ADDR + 0x44: // FLASH_BOOT_PRG - /* Write to FLASH_xxx_PRG registers */ - write_uint32((unsigned char *)&data, - *(uint32_t *)(base)); // write options bytes - - WLOG("Writing option bytes %#10x to %#10x\n", data, addr); - - /* Skip if the value in the CUR register is identical */ - stlink_read_debug32(sl, addr - 4, &val); - if (val == data) { + for (int scan = 0; (res == 0) && (scan < 2); ++scan) { + // parse file two times - first to find memory range, second - to fill it + if (scan == 1) { + if (!eof_found) { + ELOG("No EoF recond\n"); + res = -1; break; } - /* Write new option byte values and start modification */ - stlink_write_debug32(sl, addr, data); - stlink_read_debug32(sl, FLASH_H7_OPTCR, &val); - val |= (1 << FLASH_H7_OPTCR_OPTSTART); - stlink_write_debug32(sl, FLASH_H7_OPTCR, val); - - /* Wait for the option bytes modification to complete */ - do { - stlink_read_debug32(sl, FLASH_H7_OPTSR_CUR, &val); - } while ((val & (1 << FLASH_H7_OPTSR_OPT_BUSY)) != 0); - - /* Check for errors */ - if ((val & (1 << FLASH_H7_OPTSR_OPTCHANGEERR)) != 0) { - stlink_write_debug32(sl, FLASH_H7_OPTCCR, - 1 << FLASH_H7_OPTCCR_CLR_OPTCHANGEERR); - return -1; + if (*begin >= end) { + ELOG("No data found in file\n"); + res = -1; + break; } - break; - - default: - /* Skip non-programmable registers */ - break; - } - - len -= 4; - addr += 4; - base += 4; - } - return 0; -} + *size = (end - *begin) + 1; + data = calloc(*size, 1); // use calloc to get NULL if out of memory -/** - * Read option bytes - * @param sl - * @param option_byte value to write - * @return 0 on success, -ve on failure. - */ -int stlink_read_option_control_register_Gx(stlink_t *sl, - uint32_t *option_byte) { - return stlink_read_debug32(sl, STM32Gx_FLASH_OPTR, option_byte); -} + if (!data) { + ELOG("Cannot allocate %u bytes\n", (unsigned)(*size)); + res = -1; + break; + } -/** - * Read option bytes - * @param sl - * @param option_byte value to write - * @return 0 on success, -ve on failure. - */ -int stlink_read_option_bytes_Gx(stlink_t *sl, uint32_t *option_byte) { - return stlink_read_option_control_register_Gx(sl, option_byte); -} + memset(data, erased_pattern, *size); + } -/** - * Read option bytes - * @param sl - * @param option_byte value to write - * @return 0 on success, -ve on failure. - */ -int stlink_read_option_control_register_f2(stlink_t *sl, - uint32_t *option_byte) { - return stlink_read_debug32(sl, FLASH_F2_OPT_CR, option_byte); -} + FILE *file = fopen(path, "r"); -/** - * Read option bytes - * @param sl - * @param option_byte value to write - * @return 0 on success, -ve on failure. - */ -int stlink_read_option_bytes_f2(stlink_t *sl, uint32_t *option_byte) { - return stlink_read_option_control_register_f2(sl, option_byte); -} + if (!file) { + ELOG("Cannot open file\n"); + res = -1; + break; + } -/** - * Read option bytes - * @param sl - * @param option_byte value to read - * @return 0 on success, -ve on failure. - */ -int stlink_read_option_control_register_f4(stlink_t *sl, - uint32_t *option_byte) { - return stlink_read_debug32(sl, FLASH_F4_OPTCR, option_byte); -} + uint32_t lba = 0; + char line[1 + 5 * 2 + 255 * 2 + 2]; -/** - * Read option bytes - * @param sl - * @param option_byte value to read - * @return 0 on success, -ve on failure. - */ -int stlink_read_option_bytes_f4(stlink_t *sl, uint32_t *option_byte) { - return stlink_read_option_control_register_f4(sl, option_byte); -} + while (fgets(line, sizeof(line), file)) { + if (line[0] == '\n' || line[0] == '\r') { + continue; + } // skip empty lines -/** - * Read option bytes - * @param sl - * @param option_byte value to read - * @return 0 on success, -ve on failure. - */ -int stlink_read_option_control_register_f7(stlink_t *sl, - uint32_t *option_byte) { - DLOG("@@@@ Read option control register byte from %#10x\n", FLASH_F7_OPTCR); - return stlink_read_debug32(sl, FLASH_F7_OPTCR, option_byte); -} + if (line[0] != ':') { // no marker - wrong file format + ELOG("Wrong file format - no marker\n"); + res = -1; + break; + } -/** - * Read option bytes - * @param sl - * @param option_byte value to read - * @return 0 on success, -ve on failure. - */ -int stlink_read_option_control_register_f0(stlink_t *sl, - uint32_t *option_byte) { - DLOG("@@@@ Read option control register byte from %#10x\n", FLASH_OBR); - return stlink_read_debug32(sl, FLASH_OBR, option_byte); -} + size_t l = strlen(line); -/** - * Read option bytes - * @param sl - * @param option_byte value to read - * @return 0 on success, -ve on failure. - */ -int stlink_read_option_control_register1_f7(stlink_t *sl, - uint32_t *option_byte) { - DLOG("@@@@ Read option control register 1 byte from %#10x\n", - FLASH_F7_OPTCR1); - return stlink_read_debug32(sl, FLASH_F7_OPTCR1, option_byte); -} + while (l > 0 && (line[l - 1] == '\n' || line[l - 1] == '\r')) { + --l; + } // trim EoL -/** - * Read option bytes - * @param sl - * @param option_byte value to read - * @return 0 on success, -ve on failure. - */ -int stlink_read_option_bytes_boot_add_f7(stlink_t *sl, uint32_t *option_byte) { - DLOG("@@@@ Read option byte boot address\n"); - return stlink_read_option_control_register1_f7(sl, option_byte); -} + if ((l < 11) || + (l == + (sizeof(line) - 1))) { // line too short or long - wrong file format + ELOG("Wrong file format - wrong line length\n"); + res = -1; + break; + } -/** - * Read option bytes - * @param sl - * @param option_byte value to read - * @return 0 on success, -ve on failure. - * - * Since multiple bytes can be read, we read and print all but one here - * and then return the last one just like other devices - */ -int stlink_read_option_bytes_f7(stlink_t *sl, uint32_t *option_byte) { - int err = -1; - for (uint32_t counter = 0; counter < (sl->option_size / 4 - 1); counter++) { - err = stlink_read_debug32(sl, sl->option_base + counter * sizeof(uint32_t), - option_byte); - if (err == -1) { - return err; - } else { - printf("%08x\n", *option_byte); - } - } + uint8_t chksum = 0; // check sum - return stlink_read_debug32( - sl, - sl->option_base + (uint32_t)(sl->option_size / 4 - 1) * sizeof(uint32_t), - option_byte); -} + for (size_t i = 1; i < l; i += 2) { + chksum += stlink_parse_hex(line + i); + } -/** - * Read first option bytes - * @param sl - * @param option_byte option value - * @return 0 on success, -ve on failure. - */ -int stlink_read_option_bytes_generic(stlink_t *sl, uint32_t *option_byte) { - DLOG("@@@@ Read option bytes boot address from %#10x\n", sl->option_base); - return stlink_read_debug32(sl, sl->option_base, option_byte); -} + if (chksum != 0) { + ELOG("Wrong file format - checksum mismatch\n"); + res = -1; + break; + } -/** - * Read option bytes - * @param sl - * @param option_byte value to read - * @return 0 on success, -ve on failure. - */ -// int stlink_read_option_bytes_boot_add_generic(stlink_t *sl, uint32_t* -// option_byte) { -// DLOG("@@@@ Read option bytes boot address from %#10x\n", sl->option_base); -// return stlink_read_debug32(sl, sl->option_base, option_byte); -//} + uint8_t reclen = stlink_parse_hex(line + 1); -/** - * Read option bytes - * @param sl - * @param option_byte value to read - * @return 0 on success, -ve on failure. - */ -// int stlink_read_option_control_register_generic(stlink_t *sl, uint32_t* -// option_byte) { -// DLOG("@@@@ Read option control register byte from %#10x\n", -// sl->option_base); return stlink_read_debug32(sl, sl->option_base, -// option_byte); -//} + if (((uint32_t)reclen + 5) * 2 + 1 != l) { + ELOG("Wrong file format - record length mismatch\n"); + res = -1; + break; + } -/** - * Read option bytes - * @param sl - * @param option_byte value to read - * @return 0 on success, -ve on failure. - */ -// int stlink_read_option_control_register1_generic(stlink_t *sl, uint32_t* -// option_byte) { -// DLOG("@@@@ Read option control register 1 byte from %#10x\n", -// sl->option_base); return stlink_read_debug32(sl, sl->option_base, -// option_byte); -//} + uint16_t offset = ((uint16_t)stlink_parse_hex(line + 3) << 8) | + ((uint16_t)stlink_parse_hex(line + 5)); + uint8_t rectype = stlink_parse_hex(line + 7); -/** - * Read option bytes - * @param sl - * @param option_byte option value - * @return 0 on success, -ve on failure. - */ -int stlink_read_option_bytes32(stlink_t *sl, uint32_t *option_byte) { - if (sl->option_base == 0) { - ELOG("Option bytes read is currently not supported for connected chip\n"); - return (-1); - } + switch (rectype) { + case 0: /* Data */ + if (scan == 0) { + uint32_t b = lba + offset; + uint32_t e = b + reclen - 1; - switch (sl->chip_id) { - case STLINK_CHIPID_STM32_F2: - return stlink_read_option_bytes_f2(sl, option_byte); - case STLINK_CHIPID_STM32_F4: - case STLINK_CHIPID_STM32_F446: - return stlink_read_option_bytes_f4(sl, option_byte); - case STLINK_CHIPID_STM32_F76xxx: - return stlink_read_option_bytes_f7(sl, option_byte); - case STLINK_CHIPID_STM32_G0_CAT1: - case STLINK_CHIPID_STM32_G0_CAT2: - case STLINK_CHIPID_STM32_G4_CAT2: - case STLINK_CHIPID_STM32_G4_CAT3: - return stlink_read_option_bytes_Gx(sl, option_byte); - default: - return stlink_read_option_bytes_generic(sl, option_byte); - } -} + if (b < *begin) { + *begin = b; + } -/** - * Read option bytes - * @param sl - * @param option_byte option value - * @return 0 on success, -ve on failure. - */ -int stlink_read_option_bytes_boot_add32(stlink_t *sl, uint32_t *option_byte) { - if (sl->option_base == 0) { - ELOG("Option bytes boot address read is currently not supported for " - "connected chip\n"); - return -1; - } + if (e > end) { + end = e; + } + } else { + for (uint8_t i = 0; i < reclen; ++i) { + uint8_t b = stlink_parse_hex(line + 9 + i * 2); + uint32_t addr = lba + offset + i; - switch (sl->flash_type) { - case STLINK_FLASH_TYPE_F7: - return stlink_read_option_bytes_boot_add_f7(sl, option_byte); - default: - return -1; - // return stlink_read_option_bytes_boot_add_generic(sl, option_byte); - } -} + if (addr >= *begin && addr <= end) { + data[addr - *begin] = b; + } + } + } + break; + case 1: /* EoF */ + eof_found = true; + break; + case 2: /* Extended Segment Address, unexpected */ + res = -1; + break; + case 3: /* Start Segment Address, unexpected */ + res = -1; + break; + case 4: /* Extended Linear Address */ + if (reclen == 2) { + lba = ((uint32_t)stlink_parse_hex(line + 9) << 24) | + ((uint32_t)stlink_parse_hex(line + 11) << 16); + } else { + ELOG("Wrong file format - wrong LBA length\n"); + res = -1; + } + break; + case 5: /* Start Linear Address - expected, but ignore */ + break; + default: + ELOG("Wrong file format - unexpected record type %d\n", rectype); + res = -1; + } -/** - * Read option bytes - * @param sl - * @param option_byte option value - * @return 0 on success, -ve on failure. - */ -int stlink_read_option_control_register32(stlink_t *sl, uint32_t *option_byte) { - if (sl->option_base == 0) { - ELOG("Option bytes read is currently not supported for connected chip\n"); - return -1; - } + if (res != 0) { + break; + } + } - switch (sl->flash_type) { - case STLINK_FLASH_TYPE_F0: - case STLINK_FLASH_TYPE_F1_XL: - return stlink_read_option_control_register_f0(sl, option_byte); - case STLINK_FLASH_TYPE_F7: - return stlink_read_option_control_register_f7(sl, option_byte); - default: - return -1; + fclose(file); } -} -/** - * Read option bytes - * @param sl - * @param option_byte option value - * @return 0 on success, -ve on failure. - */ -int stlink_read_option_control_register1_32(stlink_t *sl, - uint32_t *option_byte) { - if (sl->option_base == 0) { - ELOG("Option bytes read is currently not supported for connected chip\n"); - return -1; + if (res == 0) { + *mem = data; + } else { + free(data); } - switch (sl->flash_type) { - case STLINK_FLASH_TYPE_F7: - return stlink_read_option_control_register1_f7(sl, option_byte); - default: - return -1; - // return stlink_read_option_control_register1_generic(sl, option_byte); + return (res); +} +// 280 +uint8_t stlink_get_erased_pattern(stlink_t *sl) { + if (sl->flash_type == STLINK_FLASH_TYPE_L0) { + return (0x00); + } else { + return (0xff); } } +// 322 +int stlink_target_connect(stlink_t *sl, enum connect_type connect) { + if (connect == CONNECT_UNDER_RESET) { + stlink_enter_swd_mode(sl); -/** - * Write option bytes - * @param sl - * @param option_byte value to write - * @return 0 on success, -ve on failure. - */ -int stlink_write_option_bytes32(stlink_t *sl, uint32_t option_byte) { - WLOG("About to write option byte %#10x to %#10x.\n", option_byte, - sl->option_base); - return stlink_write_option_bytes(sl, sl->option_base, (uint8_t *)&option_byte, - 4); -} + stlink_jtag_reset(sl, STLINK_DEBUG_APIV2_DRIVE_NRST_LOW); -/** - * Write option bytes - * @param sl - * @param addr of the memory mapped option bytes - * @param base option bytes to write - * @return 0 on success, -ve on failure. - */ -int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t *base, - uint32_t len) { - int ret = -1; + // try to halt the core before reset + // this is useful if the NRST pin is not connected + sl->backend->force_debug(sl); - if (sl->option_base == 0) { - ELOG( - "Option bytes writing is currently not supported for connected chip\n"); - return (-1); + // minimum reset pulse duration of 20 us (RM0008, 8.1.2 Power reset) + usleep(20); + + stlink_jtag_reset(sl, STLINK_DEBUG_APIV2_DRIVE_NRST_HIGH); + + // try to halt the core after reset + unsigned timeout = time_ms() + 10; + while (time_ms() < timeout) { + sl->backend->force_debug(sl); + usleep(100); + } + + // check NRST connection + uint32_t dhcsr = 0; + stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); + if ((dhcsr & STLINK_REG_DHCSR_S_RESET_ST) == 0) { + WLOG("NRST is not connected\n"); + } + + // addition soft reset for halt before the first instruction + stlink_soft_reset(sl, 1 /* halt on reset */); } - if ((addr < sl->option_base) || addr > sl->option_base + sl->option_size) { - ELOG("Option bytes start address out of Option bytes range\n"); - return (-1); + if (stlink_current_mode(sl) != STLINK_DEV_DEBUG_MODE && + stlink_enter_swd_mode(sl)) { + printf("Failed to enter SWD mode\n"); + return -1; } - if (addr + len > sl->option_base + sl->option_size) { - ELOG("Option bytes data too long\n"); - return (-1); + if (connect == CONNECT_NORMAL) { + stlink_reset(sl, RESET_AUTO); } - wait_flash_busy(sl); + return stlink_load_device_params(sl); +} - if (unlock_flash_if(sl)) { - ELOG("Flash unlock failed! System reset required to be able to unlock it " - "again!\n"); - return (-1); - } +// End of delegates.... functions below are private to this module +// same as above with entrypoint. - if (unlock_flash_option_if(sl)) { - ELOG("Flash option unlock failed!\n"); - return (-1); - } +static void stop_wdg_in_debug(stlink_t *sl) { + uint32_t dbgmcu_cr; + uint32_t set; + uint32_t value; switch (sl->flash_type) { case STLINK_FLASH_TYPE_F0: case STLINK_FLASH_TYPE_F1_XL: - ret = stlink_write_option_bytes_f0(sl, base, addr, len); + case STLINK_FLASH_TYPE_G4: + dbgmcu_cr = STM32F0_DBGMCU_CR; + set = (1 << STM32F0_DBGMCU_CR_IWDG_STOP) | + (1 << STM32F0_DBGMCU_CR_WWDG_STOP); break; case STLINK_FLASH_TYPE_F4: - ret = stlink_write_option_bytes_f4(sl, base, addr, len); - break; case STLINK_FLASH_TYPE_F7: - ret = stlink_write_option_bytes_f7(sl, base, addr, len); - break; - case STLINK_FLASH_TYPE_L0: - ret = stlink_write_option_bytes_l0(sl, base, addr, len); - break; case STLINK_FLASH_TYPE_L4: - ret = stlink_write_option_bytes_l4(sl, base, addr, len); + dbgmcu_cr = STM32F4_DBGMCU_APB1FZR1; + set = (1 << STM32F4_DBGMCU_APB1FZR1_IWDG_STOP) | + (1 << STM32F4_DBGMCU_APB1FZR1_WWDG_STOP); break; + case STLINK_FLASH_TYPE_L0: case STLINK_FLASH_TYPE_G0: - case STLINK_FLASH_TYPE_G4: - ret = stlink_write_option_bytes_gx(sl, base, addr, len); + dbgmcu_cr = STM32L0_DBGMCU_APB1_FZ; + set = (1 << STM32L0_DBGMCU_APB1_FZ_IWDG_STOP) | + (1 << STM32L0_DBGMCU_APB1_FZ_WWDG_STOP); break; case STLINK_FLASH_TYPE_H7: - ret = stlink_write_option_bytes_h7(sl, base, addr, len); + dbgmcu_cr = STM32H7_DBGMCU_APB1HFZ; + set = (1 << STM32H7_DBGMCU_APB1HFZ_IWDG_STOP); break; - default: - ELOG("Option bytes writing is currently not implemented for connected " - "chip\n"); + case STLINK_FLASH_TYPE_WB: + dbgmcu_cr = STM32WB_DBGMCU_APB1FZR1; + set = (1 << STM32WB_DBGMCU_APB1FZR1_IWDG_STOP) | + (1 << STM32WB_DBGMCU_APB1FZR1_WWDG_STOP); break; + default: + return; } - if (ret) { - ELOG("Flash option write failed!\n"); - } else { - ILOG("Wrote %d option bytes to %#010x!\n", len, addr); + if (!stlink_read_debug32(sl, dbgmcu_cr, &value)) { + stlink_write_debug32(sl, dbgmcu_cr, value | set); } +} - /* Re-lock flash. */ - lock_flash_option(sl); - lock_flash(sl); - - return ret; +int stlink_jtag_reset(stlink_t *sl, int value) { + DLOG("*** stlink_jtag_reset %d ***\n", value); + return (sl->backend->jtag_reset(sl, value)); } -/** - * Write option bytes - * @param sl - * @param option_byte value to write - * @return 0 on success, -ve on failure. - */ -static int -stlink_write_option_control_register_f7(stlink_t *sl, - uint32_t option_control_register) { - int ret = 0; +int stlink_soft_reset(stlink_t *sl, int halt_on_reset) { + int ret; + unsigned timeout; + uint32_t dhcsr, dfsr; + + DLOG("*** stlink_soft_reset %s***\n", halt_on_reset ? "(halt) " : ""); + + // halt core and enable debugging (if not already done) + // C_DEBUGEN is required to Halt on reset (DDI0337E, p. 10-6) + stlink_write_debug32(sl, STLINK_REG_DHCSR, + STLINK_REG_DHCSR_DBGKEY | STLINK_REG_DHCSR_C_HALT | + STLINK_REG_DHCSR_C_DEBUGEN); - // Clear errors - clear_flash_error(sl); + // enable Halt on reset by set VC_CORERESET and TRCENA (DDI0337E, p. 10-10) + if (halt_on_reset) { + stlink_write_debug32( + sl, STLINK_REG_CM3_DEMCR, + STLINK_REG_CM3_DEMCR_TRCENA | STLINK_REG_CM3_DEMCR_VC_HARDERR | + STLINK_REG_CM3_DEMCR_VC_BUSERR | STLINK_REG_CM3_DEMCR_VC_CORERESET); - ILOG("Asked to write option control register 1 %#10x to %#010x.\n", - option_control_register, FLASH_F7_OPTCR); + // clear VCATCH in the DFSR register + stlink_write_debug32(sl, STLINK_REG_DFSR, STLINK_REG_DFSR_VCATCH); + } else { + stlink_write_debug32(sl, STLINK_REG_CM3_DEMCR, + STLINK_REG_CM3_DEMCR_TRCENA | + STLINK_REG_CM3_DEMCR_VC_HARDERR | + STLINK_REG_CM3_DEMCR_VC_BUSERR); + } - /* write option byte, ensuring we dont lock opt, and set strt bit */ - stlink_write_debug32(sl, FLASH_F7_OPTCR, - (option_control_register & ~(1 << FLASH_F7_OPTCR_LOCK)) | - (1 << FLASH_F7_OPTCR_START)); + // clear S_RESET_ST in the DHCSR register + stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); - wait_flash_busy(sl); + // soft reset (core reset) by SYSRESETREQ (DDI0337E, p. 8-23) + ret = stlink_write_debug32(sl, STLINK_REG_AIRCR, + STLINK_REG_AIRCR_VECTKEY | + STLINK_REG_AIRCR_SYSRESETREQ); + if (ret) { + ELOG("Soft reset failed: error write to AIRCR\n"); + return (ret); + } - ret = check_flash_error(sl); - if (!ret) - ILOG("Wrote option bytes %#010x to %#010x!\n", option_control_register, - FLASH_F7_OPTCR); + // waiting for a reset within 500ms + // DDI0337E, p. 10-4, Debug Halting Control and Status Register + timeout = time_ms() + 500; + while (time_ms() < timeout) { + // DDI0337E, p. 10-4, Debug Halting Control and Status Register + dhcsr = STLINK_REG_DHCSR_S_RESET_ST; + stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); + if ((dhcsr & STLINK_REG_DHCSR_S_RESET_ST) == 0) { + if (halt_on_reset) { + // waiting halt by the SYSRESETREQ exception + // DDI0403E, p. C1-699, Debug Fault Status Register + dfsr = 0; + stlink_read_debug32(sl, STLINK_REG_DFSR, &dfsr); + if ((dfsr & STLINK_REG_DFSR_VCATCH) == 0) { + continue; + } + } + timeout = 0; + break; + } + } - return ret; -} + // reset DFSR register. DFSR is power-on reset only (DDI0337H, p. 7-5) + stlink_write_debug32(sl, STLINK_REG_DFSR, STLINK_REG_DFSR_CLEAR); + if (timeout) { + ELOG("Soft reset failed: timeout\n"); + return (-1); + } + return (0); +} /** - * Write option bytes - * @param sl - * @param option_byte value to write - * @return 0 on success, -ve on failure. + * Decode the version bits, originally from -sg, verified with usb + * @param sl stlink context, assumed to contain valid data in the buffer + * @param slv output parsed version object */ -static int -stlink_write_option_control_register_f0(stlink_t *sl, - uint32_t option_control_register) { - int ret = 0; - uint16_t opt_val[8]; - unsigned protection, optiondata; - uint16_t user_options, user_data, rdp; - unsigned option_offset, user_data_offset; +void _parse_version(stlink_t *sl, stlink_version_t *slv) { + sl->version.flags = 0; + + if (sl->version.stlink_v < 3) { + uint32_t b0 = sl->q_buf[0]; // lsb + uint32_t b1 = sl->q_buf[1]; + uint32_t b2 = sl->q_buf[2]; + uint32_t b3 = sl->q_buf[3]; + uint32_t b4 = sl->q_buf[4]; + uint32_t b5 = sl->q_buf[5]; // msb - ILOG("Asked to write option control register %#10x to %#010x.\n", - option_control_register, FLASH_OBR); + // b0 b1 || b2 b3 | b4 b5 + // 4b | 6b | 6b || 2B | 2B + // stlink_v | jtag_v | swim_v || st_vid | stlink_pid - /* Clear errors */ - clear_flash_error(sl); + slv->stlink_v = (b0 & 0xf0) >> 4; + slv->jtag_v = ((b0 & 0x0f) << 2) | ((b1 & 0xc0) >> 6); + slv->swim_v = b1 & 0x3f; + slv->st_vid = (b3 << 8) | b2; + slv->stlink_pid = (b5 << 8) | b4; - /* Retrieve current values */ - ret = stlink_read_debug32(sl, FLASH_OBR, &optiondata); - if (ret) { - return ret; + // ST-LINK/V1 from J11 switch to api-v2 (and support SWD) + if (slv->stlink_v == 1) { + slv->jtag_api = + slv->jtag_v > 11 ? STLINK_JTAG_API_V2 : STLINK_JTAG_API_V1; + } else { + slv->jtag_api = STLINK_JTAG_API_V2; + + // preferred API to get last R/W status from J15 + if (sl->version.jtag_v >= 15) { + sl->version.flags |= STLINK_F_HAS_GETLASTRWSTATUS2; + } + + if (sl->version.jtag_v >= 13) { + sl->version.flags |= STLINK_F_HAS_TRACE; + sl->max_trace_freq = STLINK_V2_MAX_TRACE_FREQUENCY; + } + } + } else { + // V3 uses different version format, for reference see OpenOCD source + // (that was written from docs available from ST under NDA): + // https://github.com/ntfreak/openocd/blob/a6dacdff58ef36fcdac00c53ec27f19de1fbce0d/src/jtag/drivers/stlink_usb.c#L965 + slv->stlink_v = sl->q_buf[0]; + slv->swim_v = sl->q_buf[1]; + slv->jtag_v = sl->q_buf[2]; + slv->st_vid = (uint32_t)((sl->q_buf[9] << 8) | sl->q_buf[8]); + slv->stlink_pid = (uint32_t)((sl->q_buf[11] << 8) | sl->q_buf[10]); + slv->jtag_api = STLINK_JTAG_API_V3; + /* preferred API to get last R/W status */ + sl->version.flags |= STLINK_F_HAS_GETLASTRWSTATUS2; + sl->version.flags |= STLINK_F_HAS_TRACE; + sl->max_trace_freq = STLINK_V3_MAX_TRACE_FREQUENCY; } - ret = stlink_read_debug32(sl, FLASH_WRPR, &protection); - if (ret) { - return ret; + + return; +} + +void stlink_run_at(stlink_t *sl, stm32_addr_t addr) { + stlink_write_reg(sl, addr, 15); /* pc register */ + stlink_run(sl, RUN_NORMAL); + + while (stlink_is_core_halted(sl)) { + usleep(3000000); } +} - /* Translate OBR value to flash store structure - * F0: RM0091, Option byte description, pp. 75-78 - * F1: PM0075, Option byte description, pp. 19-22 - * F3: RM0316, Option byte description, pp. 85-87 */ - switch(sl->chip_id) - { - case 0x422: /* STM32F30x */ - case 0x432: /* STM32F37x */ - case 0x438: /* STM32F303x6/8 and STM32F328 */ - case 0x446: /* STM32F303xD/E and STM32F398xE */ - case 0x439: /* STM32F302x6/8 */ - case 0x440: /* STM32F05x */ - case 0x444: /* STM32F03x */ - case 0x445: /* STM32F04x */ - case 0x448: /* STM32F07x */ - case 0x442: /* STM32F09x */ - option_offset = 6; - user_data_offset = 16; - rdp = 0x55AA; - break; - default: - option_offset = 0; - user_data_offset = 10; - rdp = 0x5AA5; - break; +/* Limit the block size to compare to 0x1800 as anything larger will stall the + * STLINK2 Maybe STLINK V1 needs smaller value! + */ +int check_file(stlink_t *sl, mapped_file_t *mf, stm32_addr_t addr) { + size_t off; + size_t n_cmp = sl->flash_pgsz; + + if (n_cmp > 0x1800) { + n_cmp = 0x1800; } - user_options = (option_control_register >> option_offset >> 2) & 0xFFFF; - user_data = (option_control_register >> user_data_offset) & 0xFFFF; + for (off = 0; off < mf->len; off += n_cmp) { + size_t aligned_size; + + size_t cmp_size = n_cmp; // adjust last page size -#define VAL_WITH_COMPLEMENT(v) (uint16_t)(((v)&0xFF) | (((~(v))<<8)&0xFF00)) + if ((off + n_cmp) > mf->len) { + cmp_size = mf->len - off; + } - opt_val[0] = (option_control_register & (1 << 1/*OPT_READOUT*/)) ? 0xFFFF : rdp; - opt_val[1] = VAL_WITH_COMPLEMENT(user_options); - opt_val[2] = VAL_WITH_COMPLEMENT(user_data); - opt_val[3] = VAL_WITH_COMPLEMENT(user_data >> 8); - opt_val[4] = VAL_WITH_COMPLEMENT(protection); - opt_val[5] = VAL_WITH_COMPLEMENT(protection >> 8); - opt_val[6] = VAL_WITH_COMPLEMENT(protection >> 16); - opt_val[7] = VAL_WITH_COMPLEMENT(protection >> 24); + aligned_size = cmp_size; -#undef VAL_WITH_COMPLEMENT + if (aligned_size & (4 - 1)) { + aligned_size = (cmp_size + 4) & ~(4 - 1); + } - /* Write bytes and check errors */ - ret = stlink_write_option_bytes_f0(sl, (uint8_t*)opt_val, STM32_F0_OPTION_BYTES_BASE, sizeof(opt_val)); - if (ret) - return ret; + stlink_read_mem32(sl, addr + (uint32_t)off, (uint16_t)aligned_size); - ret = check_flash_error(sl); - if (!ret) { - ILOG("Wrote option bytes %#010x to %#010x!\n", option_control_register, - FLASH_OBR); + if (memcmp(sl->q_buf, mf->base + off, cmp_size)) { + return (-1); + } } - return ret; + return (0); } -/** - * Write option bytes - * @param sl - * @param option_byte value to write - * @return 0 on success, -ve on failure. - */ -static int -stlink_write_option_control_register1_f7(stlink_t *sl, - uint32_t option_control_register1) { - int ret = 0; - - // Clear errors - clear_flash_error(sl); - - ILOG("Asked to write option control register 1 %#010x to %#010x.\n", - option_control_register1, FLASH_F7_OPTCR1); +void md5_calculate(mapped_file_t *mf) { + // calculate md5 checksum of given binary file + Md5Context md5Context; + MD5_HASH md5Hash; + Md5Initialise(&md5Context); + Md5Update(&md5Context, mf->base, (uint32_t)mf->len); + Md5Finalise(&md5Context, &md5Hash); + printf("md5 checksum: "); - /* write option byte, ensuring we dont lock opt, and set strt bit */ - uint32_t current_control_register_value; - stlink_read_debug32(sl, FLASH_F7_OPTCR, ¤t_control_register_value); + for (int i = 0; i < (int)sizeof(md5Hash); i++) { + printf("%x", md5Hash.bytes[i]); + } - /* write option byte */ - stlink_write_debug32(sl, FLASH_F7_OPTCR1, option_control_register1); - stlink_write_debug32( - sl, FLASH_F7_OPTCR, - (current_control_register_value & ~(1 << FLASH_F7_OPTCR_LOCK)) | - (1 << FLASH_F7_OPTCR_START)); + printf(", "); +} - wait_flash_busy(sl); +void stlink_checksum(mapped_file_t *mp) { + /* checksum that backward compatible with official ST tools */ + uint32_t sum = 0; + uint8_t *mp_byte = (uint8_t *)mp->base; - ret = check_flash_error(sl); - if (!ret) - ILOG("Wrote option bytes %#010x to %#010x!\n", option_control_register1, - FLASH_F7_OPTCR1); + for (size_t i = 0; i < mp->len; ++i) { + sum += mp_byte[i]; + } - return ret; + printf("stlink checksum: 0x%08x\n", sum); } -/** - * Write option bytes - * @param sl - * @param option_byte value to write - * @return 0 on success, -ve on failure. - */ -static int -stlink_write_option_bytes_boot_add_f7(stlink_t *sl, - uint32_t option_byte_boot_add) { - ILOG("Asked to write option byte boot add %#010x.\n", option_byte_boot_add); - return stlink_write_option_control_register1_f7(sl, option_byte_boot_add); +void stlink_fwrite_finalize(stlink_t *sl, stm32_addr_t addr) { + unsigned int val; + // set PC to the reset routine + stlink_read_debug32(sl, addr + 4, &val); + stlink_write_reg(sl, val, 15); + stlink_run(sl, RUN_NORMAL); } -/** - * Write option bytes - * @param sl - * @param option bytes boot address to write - * @return 0 on success, -ve on failure. - */ -int stlink_write_option_bytes_boot_add32(stlink_t *sl, - uint32_t option_bytes_boot_add) { - int ret = -1; - - wait_flash_busy(sl); +static int stlink_read(stlink_t *sl, stm32_addr_t addr, size_t size, + save_block_fn fn, void *fn_arg) { - if (unlock_flash_if(sl)) { - ELOG("Flash unlock failed! System reset required to be able to unlock it " - "again!\n"); - return -1; - } + int error = -1; - if (unlock_flash_option_if(sl)) { - ELOG("Flash option unlock failed!\n"); - return -1; + if (size < 1) { + size = sl->flash_size; } - switch (sl->flash_type) { - case STLINK_FLASH_TYPE_F7: - ret = stlink_write_option_bytes_boot_add_f7(sl, option_bytes_boot_add); - break; - default: - ELOG("Option bytes boot address writing is currently not implemented for " - "connected chip\n"); - break; + if (size > sl->flash_size) { + size = sl->flash_size; } - if (ret) - ELOG("Flash option write failed!\n"); - else - ILOG("Wrote option bytes boot address %#010x!\n", option_bytes_boot_add); + size_t cmp_size = (sl->flash_pgsz > 0x1800) ? 0x1800 : sl->flash_pgsz; - /* Re-lock flash. */ - lock_flash_option(sl); - lock_flash(sl); + for (size_t off = 0; off < size; off += cmp_size) { + size_t aligned_size; - return ret; -} + // adjust last page size + if ((off + cmp_size) > size) { + cmp_size = size - off; + } -/** - * Write option bytes - * @param sl - * @param option bytes boot address to write - * @return 0 on success, -ve on failure. - */ -int stlink_write_option_control_register32(stlink_t *sl, - uint32_t option_control_register) { - int ret = -1; + aligned_size = cmp_size; - wait_flash_busy(sl); + if (aligned_size & (4 - 1)) { + aligned_size = (cmp_size + 4) & ~(4 - 1); + } - if (unlock_flash_if(sl)) { - ELOG("Flash unlock failed! System reset required to be able to unlock it " - "again!\n"); - return -1; - } + stlink_read_mem32(sl, addr + (uint32_t)off, (uint16_t)aligned_size); - if (unlock_flash_option_if(sl)) { - ELOG("Flash option unlock failed!\n"); - return -1; + if (!fn(fn_arg, sl->q_buf, aligned_size)) { + goto on_error; + } } - switch (sl->flash_type) { - case STLINK_FLASH_TYPE_F0: - case STLINK_FLASH_TYPE_F1_XL: - ret = stlink_write_option_control_register_f0(sl, option_control_register); - break; - case STLINK_FLASH_TYPE_F7: - ret = stlink_write_option_control_register_f7(sl, option_control_register); - break; - default: - ELOG("Option control register writing is currently not implemented for " - "connected chip\n"); - break; - } + error = 0; // success - if (ret) - ELOG("Flash option write failed!\n"); - else - ILOG("Wrote option control register %#010x!\n", option_control_register); +on_error: + return (error); +} - /* Re-lock flash. */ - lock_flash_option(sl); - lock_flash(sl); +static bool stlink_fread_worker(void *arg, uint8_t *block, ssize_t len) { + struct stlink_fread_worker_arg *the_arg = + (struct stlink_fread_worker_arg *)arg; - return ret; + if (write(the_arg->fd, block, len) != len) { + fprintf(stderr, "write() != aligned_size\n"); + return (false); + } else { + return (true); + } } -/** - * Write option bytes - * @param sl - * @param option bytes boot address to write - * @return 0 on success, -ve on failure. - */ -int stlink_write_option_control_register1_32( - stlink_t *sl, uint32_t option_control_register1) { - int ret = -1; +// TODO: length not checked +static uint8_t stlink_parse_hex(const char *hex) { + uint8_t d[2]; - wait_flash_busy(sl); + for (int i = 0; i < 2; ++i) { + char c = *(hex + i); - if (unlock_flash_if(sl)) { - ELOG("Flash unlock failed! System reset required to be able to unlock it " - "again!\n"); - return -1; + if (c >= '0' && c <= '9') { + d[i] = c - '0'; + } else if (c >= 'A' && c <= 'F') { + d[i] = c - 'A' + 10; + } else if (c >= 'a' && c <= 'f') { + d[i] = c - 'a' + 10; + } else { + return (0); // error + } } - if (unlock_flash_option_if(sl)) { - ELOG("Flash option unlock failed!\n"); - return -1; - } + return ((d[0] << 4) | (d[1])); +} - switch (sl->flash_type) { - case STLINK_FLASH_TYPE_F7: - ret = - stlink_write_option_control_register1_f7(sl, option_control_register1); - break; - default: - ELOG("Option control register 1 writing is currently not implemented for " - "connected chip\n"); - break; +static bool +stlink_fread_ihex_newsegment(struct stlink_fread_ihex_worker_arg *the_arg) { + uint32_t addr = the_arg->addr; + uint8_t sum = 2 + 4 + (uint8_t)((addr & 0xFF000000) >> 24) + + (uint8_t)((addr & 0x00FF0000) >> 16); + + if (17 != fprintf(the_arg->file, ":02000004%04X%02X\r\n", + (addr & 0xFFFF0000) >> 16, (uint8_t)(0x100 - sum))) { + return (false); } - if (ret) - ELOG("Flash option write failed!\n"); - else - ILOG("Wrote option control register 1 %#010x!\n", option_control_register1); + the_arg->lba = (addr & 0xFFFF0000); + return (true); +} - lock_flash_option(sl); - lock_flash(sl); +static bool +stlink_fread_ihex_writeline(struct stlink_fread_ihex_worker_arg *the_arg) { + uint8_t count = the_arg->buf_pos; - return (ret); -} + if (count == 0) { + return (true); + } -/** - * Write the given binary file with option bytes - * @param sl - * @param path readable file path, should be binary image - * @param addr of the memory mapped option bytes - * @return 0 on success, -ve on failure. - */ -int stlink_fwrite_option_bytes(stlink_t *sl, const char *path, - stm32_addr_t addr) { - /* Write the file in flash at addr */ - int err; - mapped_file_t mf = MAPPED_FILE_INITIALIZER; + uint32_t addr = the_arg->addr; - if (map_file(&mf, path) == -1) { - ELOG("map_file() == -1\n"); - return (-1); + if (the_arg->lba != (addr & 0xFFFF0000)) { // segment changed + if (!stlink_fread_ihex_newsegment(the_arg)) { + return (false); + } } - printf("file %s ", path); - md5_calculate(&mf); - stlink_checksum(&mf); + uint8_t sum = count + (uint8_t)((addr & 0x0000FF00) >> 8) + + (uint8_t)(addr & 0x000000FF); - err = stlink_write_option_bytes(sl, addr, mf.base, (uint32_t)mf.len); - stlink_fwrite_finalize(sl, addr); - unmap_file(&mf); + if (9 != fprintf(the_arg->file, ":%02X%04X00", count, (addr & 0x0000FFFF))) { + return (false); + } - return (err); -} + for (uint8_t i = 0; i < count; ++i) { + uint8_t b = the_arg->buf[i]; + sum += b; -int stlink_target_connect(stlink_t *sl, enum connect_type connect) { - if (connect == CONNECT_UNDER_RESET) { - stlink_enter_swd_mode(sl); + if (2 != fprintf(the_arg->file, "%02X", b)) { + return (false); + } + } - stlink_jtag_reset(sl, STLINK_DEBUG_APIV2_DRIVE_NRST_LOW); + if (4 != fprintf(the_arg->file, "%02X\r\n", (uint8_t)(0x100 - sum))) { + return (false); + } - // try to halt the core before reset - // this is useful if the NRST pin is not connected - sl->backend->force_debug(sl); + the_arg->addr += count; + the_arg->buf_pos = 0; - // minimum reset pulse duration of 20 us (RM0008, 8.1.2 Power reset) - usleep(20); + return (true); +} - stlink_jtag_reset(sl, STLINK_DEBUG_APIV2_DRIVE_NRST_HIGH); +static bool stlink_fread_ihex_init(struct stlink_fread_ihex_worker_arg *the_arg, + int fd, stm32_addr_t addr) { + the_arg->file = fdopen(fd, "w"); + the_arg->addr = addr; + the_arg->lba = 0; + the_arg->buf_pos = 0; - // try to halt the core after reset - unsigned timeout = time_ms() + 10; - while (time_ms() < timeout) { - sl->backend->force_debug(sl); - usleep(100); - } + return (the_arg->file != NULL); +} - // check NRST connection - uint32_t dhcsr = 0; - stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); - if ((dhcsr & STLINK_REG_DHCSR_S_RESET_ST) == 0) { - WLOG("NRST is not connected\n"); +static bool stlink_fread_ihex_worker(void *arg, uint8_t *block, ssize_t len) { + struct stlink_fread_ihex_worker_arg *the_arg = + (struct stlink_fread_ihex_worker_arg *)arg; + + for (ssize_t i = 0; i < len; ++i) { + if (the_arg->buf_pos == sizeof(the_arg->buf)) { // line is full + if (!stlink_fread_ihex_writeline(the_arg)) { + return (false); + } } - // addition soft reset for halt before the first instruction - stlink_soft_reset(sl, 1 /* halt on reset */); + the_arg->buf[the_arg->buf_pos++] = block[i]; } - if (stlink_current_mode(sl) != STLINK_DEV_DEBUG_MODE && - stlink_enter_swd_mode(sl)) { - printf("Failed to enter SWD mode\n"); - return -1; + return (true); +} + +static bool +stlink_fread_ihex_finalize(struct stlink_fread_ihex_worker_arg *the_arg) { + if (!stlink_fread_ihex_writeline(the_arg)) { + return (false); } - if (connect == CONNECT_NORMAL) { - stlink_reset(sl, RESET_AUTO); + // FIXME: do we need the Start Linear Address? + + if (13 != fprintf(the_arg->file, ":00000001FF\r\n")) { // EoF + return (false); } - return stlink_load_device_params(sl); + return (0 == fclose(the_arg->file)); } diff --git a/src/common_flash.c b/src/common_flash.c index 4f7f46257..1f438c74f 100644 --- a/src/common_flash.c +++ b/src/common_flash.c @@ -1,6 +1,7 @@ #include #include #include +#include #include "calculate.h" #include "common_flash.h" #include "map_file.h" diff --git a/src/flashloader.c b/src/flashloader.c index df14e506c..f84e16ef0 100644 --- a/src/flashloader.c +++ b/src/flashloader.c @@ -1,4 +1,5 @@ #include +#include #include #include "common_flash.h" diff --git a/src/map_file.c b/src/map_file.c index 5282fae27..cb7d4f525 100644 --- a/src/map_file.c +++ b/src/map_file.c @@ -1,10 +1,17 @@ #include #include #include +#include // for close #include +#include + #include "map_file.h" +#ifndef O_BINARY +#define O_BINARY 0 +#endif + #ifndef MAX_FILE_SIZE #define MAX_FILE_SIZE (1<<20) // 1 GB max file size #endif diff --git a/src/option.c b/src/option.c index b70f7a533..ed9ee4f39 100644 --- a/src/option.c +++ b/src/option.c @@ -1,4 +1,5 @@ #include +#include #include #include "common_flash.h" #include "map_file.h" diff --git a/src/read_write.c b/src/read_write.c index adcda6f3b..efaa5a25f 100644 --- a/src/read_write.c +++ b/src/read_write.c @@ -1,4 +1,5 @@ #include +#include #include // Endianness From 8d96e769f32d1c85be913f77e6aab4b1d84b80b1 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Thu, 20 Jan 2022 23:19:10 +0100 Subject: [PATCH 360/503] Updated device parametres - Human-readable FLASH_TYPE in .chip files - Added enum for STM32_CORE_IDs --- config/chips/F03x.chip | 2 +- config/chips/F04x.chip | 2 +- config/chips/F05x.chip | 2 +- config/chips/F07x.chip | 2 +- config/chips/F09x.chip | 2 +- config/chips/F1xx_CL.chip | 2 +- config/chips/F1xx_HD.chip | 2 +- config/chips/F1xx_LD.chip | 2 +- config/chips/F1xx_MD.chip | 2 +- config/chips/F1xx_VL_HD.chip | 2 +- config/chips/F1xx_VL_MD_LD.chip | 2 +- config/chips/F1xx_XLD.chip | 2 +- config/chips/F2xx.chip | 2 +- config/chips/F301_F302_F318.chip | 2 +- config/chips/F302_F303_F358.chip | 2 +- config/chips/F302_F303_F398_HD.chip | 2 +- config/chips/F303_F328_F334.chip | 2 +- config/chips/F37x.chip | 2 +- config/chips/F401xB_xC.chip | 2 +- config/chips/F401xD_xE.chip | 2 +- config/chips/F410.chip | 2 +- config/chips/F411xC_xE.chip | 2 +- config/chips/F412.chip | 2 +- config/chips/F413_F423.chip | 2 +- config/chips/F42x_F43x.chip | 2 +- config/chips/F446.chip | 2 +- config/chips/F46x_F47x.chip | 2 +- config/chips/F4x5_F4x7.chip | 2 +- config/chips/F72x_F73x.chip | 2 +- config/chips/F74x_F75x.chip | 2 +- config/chips/F76x_F77x.chip | 2 +- config/chips/G03x_G04x.chip | 2 +- config/chips/G05x_G06x.chip | 2 +- config/chips/G07x_G08x.chip | 2 +- config/chips/G0Bx_G0Cx.chip | 2 +- config/chips/G43x_G44x.chip | 2 +- config/chips/G47x_G48x.chip | 2 +- config/chips/G49x_G4Ax.chip | 2 +- config/chips/H72x_H73x.chip | 2 +- config/chips/H74x_H75x.chip | 2 +- config/chips/H7Ax_H7Bx.chip | 2 +- config/chips/L0xxx_Cat_1.chip | 2 +- config/chips/L0xxx_Cat_2.chip | 2 +- config/chips/L0xxx_Cat_3.chip | 2 +- config/chips/L0xxx_Cat_5.chip | 2 +- config/chips/L1xx_Cat_1.chip | 2 +- config/chips/L1xx_Cat_2.chip | 2 +- config/chips/L1xx_Cat_3.chip | 2 +- config/chips/L1xx_Cat_4.chip | 2 +- config/chips/L1xx_Cat_5.chip | 2 +- config/chips/L41x_L42x.chip | 2 +- config/chips/L43x_L44x.chip | 2 +- config/chips/L45x_L46x.chip | 2 +- config/chips/L47x_L48x.chip | 2 +- config/chips/L496x_L4A6x.chip | 2 +- config/chips/L4Px.chip | 2 +- config/chips/L4Rx.chip | 2 +- config/chips/{L5x5.chip => L5x5.chip.txt} | 2 +- config/chips/{U5x5.chip => U5x5.chip.txt} | 2 +- config/chips/WBx0_WBx5.chip | 2 +- config/chips/WLx5.chip | 2 +- config/chips/unknown_device.chip | 2 +- inc/stm32.h | 49 +++++++----------- src/stlink-lib/chipid.c | 63 +++++++++++++++-------- 64 files changed, 123 insertions(+), 113 deletions(-) rename config/chips/{L5x5.chip => L5x5.chip.txt} (85%) rename config/chips/{U5x5.chip => U5x5.chip.txt} (85%) diff --git a/config/chips/F03x.chip b/config/chips/F03x.chip index c0a6e5200..84543dc23 100644 --- a/config/chips/F03x.chip +++ b/config/chips/F03x.chip @@ -3,7 +3,7 @@ dev_type STM32F03x ref_manual_id 0091 chip_id 0x444 // STM32_CHIPID_F0xx_SMALL -flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3 +flash_type F0_F1_F3 flash_size_reg 0x1ffff7cc flash_pagesize 0x400 // 1 KB sram_size 0x1000 // 4 KB diff --git a/config/chips/F04x.chip b/config/chips/F04x.chip index 9b2ee5586..322e61e51 100644 --- a/config/chips/F04x.chip +++ b/config/chips/F04x.chip @@ -3,7 +3,7 @@ dev_type STM32F04x ref_manual_id 0091 chip_id 0x445 // STM32_CHIPID_F04 -flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3 +flash_type F0_F1_F3 flash_size_reg 0x1ffff7cc flash_pagesize 0x400 // 1 KB sram_size 0x1800 // 6 KB diff --git a/config/chips/F05x.chip b/config/chips/F05x.chip index c32ba0b46..3ba9566eb 100644 --- a/config/chips/F05x.chip +++ b/config/chips/F05x.chip @@ -3,7 +3,7 @@ dev_type STM32F05x ref_manual_id 0091 chip_id 0x440 // STM32_CHIPID_F0 -flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3 +flash_type F0_F1_F3 flash_size_reg 0x1ffff7cc flash_pagesize 0x400 // 1 KB sram_size 0x2000 // 8 KB diff --git a/config/chips/F07x.chip b/config/chips/F07x.chip index 5ba832058..4b1465ca6 100644 --- a/config/chips/F07x.chip +++ b/config/chips/F07x.chip @@ -3,7 +3,7 @@ dev_type STM32F07x ref_manual_id 0091 chip_id 0x448 // STM32_CHIPID_F0_CAN -flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3 +flash_type F0_F1_F3 flash_size_reg 0x1ffff7cc flash_pagesize 0x800 // 2 KB sram_size 0x4000 // 16 KB diff --git a/config/chips/F09x.chip b/config/chips/F09x.chip index ca987123d..eb6dec428 100644 --- a/config/chips/F09x.chip +++ b/config/chips/F09x.chip @@ -3,7 +3,7 @@ dev_type STM32F09x ref_manual_id 0091 chip_id 0x442 // STM32_CHIPID_F09x -flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3 +flash_type F0_F1_F3 flash_size_reg 0x1ffff7cc flash_pagesize 0x800 // 2 KB sram_size 0x8000 // 32 KB diff --git a/config/chips/F1xx_CL.chip b/config/chips/F1xx_CL.chip index 0f56362f0..d774412e1 100644 --- a/config/chips/F1xx_CL.chip +++ b/config/chips/F1xx_CL.chip @@ -3,7 +3,7 @@ dev_type STM32F1xx_CL ref_manual_id 0008 chip_id 0x418 // STM32_CHIPID_F1_CONN -flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3 +flash_type F0_F1_F3 flash_size_reg 0x1ffff7e0 flash_pagesize 0x800 // 2 KB sram_size 0x10000 // 64 KB diff --git a/config/chips/F1xx_HD.chip b/config/chips/F1xx_HD.chip index 2af8582e6..f454e2a1c 100644 --- a/config/chips/F1xx_HD.chip +++ b/config/chips/F1xx_HD.chip @@ -3,7 +3,7 @@ dev_type F1xx_HD ref_manual_id 0008 chip_id 0x414 // STM32_CHIPID_F1_HD -flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3 +flash_type F0_F1_F3 flash_size_reg 0x1ffff7e0 flash_pagesize 0x800 // 2 KB sram_size 0x10000 // 64 KB diff --git a/config/chips/F1xx_LD.chip b/config/chips/F1xx_LD.chip index ffd34fd4a..50f115148 100644 --- a/config/chips/F1xx_LD.chip +++ b/config/chips/F1xx_LD.chip @@ -3,7 +3,7 @@ dev_type STM32F1xx_LD ref_manual_id 0008 chip_id 0x412 // STM32_CHIPID_F1_LD -flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3 +flash_type F0_F1_F3 flash_size_reg 0x1ffff7e0 flash_pagesize 0x400 // 1 KB sram_size 0x2800 // 10 KB diff --git a/config/chips/F1xx_MD.chip b/config/chips/F1xx_MD.chip index f27a7a062..17af311c1 100644 --- a/config/chips/F1xx_MD.chip +++ b/config/chips/F1xx_MD.chip @@ -3,7 +3,7 @@ dev_type STM32F1xx_MD ref_manual_id 0008 chip_id 0x410 // STM32_CHIPID_F1_MD -flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3 +flash_type F0_F1_F3 flash_size_reg 0x1ffff7e0 flash_pagesize 0x400 // 1 KB sram_size 0x5000 // 20 KB diff --git a/config/chips/F1xx_VL_HD.chip b/config/chips/F1xx_VL_HD.chip index 4f2566949..c77e013ce 100644 --- a/config/chips/F1xx_VL_HD.chip +++ b/config/chips/F1xx_VL_HD.chip @@ -3,7 +3,7 @@ dev_type STM32F1xx_VL_HD ref_manual_id 0041 chip_id 0x428 // STM32_CHIPID_F1_VL_HD -flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3 +flash_type F0_F1_F3 flash_size_reg 0x1ffff7e0 flash_pagesize 0x800 // 2 KB sram_size 0x8000 // 32 KB diff --git a/config/chips/F1xx_VL_MD_LD.chip b/config/chips/F1xx_VL_MD_LD.chip index 1705bc8e3..467fb786f 100644 --- a/config/chips/F1xx_VL_MD_LD.chip +++ b/config/chips/F1xx_VL_MD_LD.chip @@ -3,7 +3,7 @@ dev_type STM32F1xx_VL_MD_LD ref_manual_id 0041 chip_id 0x420 // STM32_CHIPID_F1_VL_MD_LD -flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3 +flash_type F0_F1_F3 flash_size_reg 0x1ffff7e0 flash_pagesize 0x400 // 1 KB sram_size 0x2000 // 8 KB /* 0x1000 for low density devices */ diff --git a/config/chips/F1xx_XLD.chip b/config/chips/F1xx_XLD.chip index 37c900f28..622bd9d02 100644 --- a/config/chips/F1xx_XLD.chip +++ b/config/chips/F1xx_XLD.chip @@ -3,7 +3,7 @@ dev_type STM32F1xx_XLD ref_manual_id 0008 chip_id 0x430 // STM32_CHIPID_F1_XLD -flash_type 2 // STM32_FLASH_TYPE_F1_XL +flash_type F1_XL flash_size_reg 0x1ffff7e0 flash_pagesize 0x800 // 2 KB sram_size 0x18000 // 96 KB diff --git a/config/chips/F2xx.chip b/config/chips/F2xx.chip index 314df7d6d..30ea174ee 100644 --- a/config/chips/F2xx.chip +++ b/config/chips/F2xx.chip @@ -3,7 +3,7 @@ dev_type STM32F2xx ref_manual_id 0033 chip_id 0x411 // STM32_CHIPID_F2 -flash_type 3 // STM32_FLASH_TYPE_F2_F4 +flash_type F2_F4 flash_size_reg 0x1fff7a22 flash_pagesize 0x20000 // 128 KB sram_size 0x20000 // 128 KB diff --git a/config/chips/F301_F302_F318.chip b/config/chips/F301_F302_F318.chip index f620364b2..408f1435e 100644 --- a/config/chips/F301_F302_F318.chip +++ b/config/chips/F301_F302_F318.chip @@ -3,7 +3,7 @@ dev_type STM32F301_F302_F318 ref_manual_id 0365 // also RM0366 chip_id 0x439 // STM32_CHIPID_F3xx_SMALL -flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3 +flash_type F0_F1_F3 flash_size_reg 0x1ffff7cc flash_pagesize 0x800 // 2 KB sram_size 0xa000 // 40 KB diff --git a/config/chips/F302_F303_F358.chip b/config/chips/F302_F303_F358.chip index e48370159..08c6dc371 100644 --- a/config/chips/F302_F303_F358.chip +++ b/config/chips/F302_F303_F358.chip @@ -3,7 +3,7 @@ dev_type STM32F302_F303_358 ref_manual_id 0365 // also RM0316 chip_id 0x422 // STM32_CHIPID_F3 -flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3 +flash_type F0_F1_F3 flash_size_reg 0x1ffff7cc flash_pagesize 0x800 // 2 KB sram_size 0xa000 // 40 KB diff --git a/config/chips/F302_F303_F398_HD.chip b/config/chips/F302_F303_F398_HD.chip index 181fdfa72..7b254c486 100644 --- a/config/chips/F302_F303_F398_HD.chip +++ b/config/chips/F302_F303_F398_HD.chip @@ -3,7 +3,7 @@ dev_type STM32F302_F303_F398_HD ref_manual_id 0365 // also RM0316 (Rev 5) chip_id 0x446 // STM32_CHIPID_F303_HD -flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3 +flash_type F0_F1_F3 flash_size_reg 0x1ffff7cc flash_pagesize 0x800 // 2 KB sram_size 0x10000 // 64 KB diff --git a/config/chips/F303_F328_F334.chip b/config/chips/F303_F328_F334.chip index 069de07fb..daf299cea 100644 --- a/config/chips/F303_F328_F334.chip +++ b/config/chips/F303_F328_F334.chip @@ -3,7 +3,7 @@ dev_type STM32F303_F328_F334 ref_manual_id 0364 // also RM0316 chip_id 0x438 // STM32_CHIPID_F334 -flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3 +flash_type F0_F1_F3 flash_size_reg 0x1ffff7cc flash_pagesize 0x800 // 2 KB sram_size 0x3000 // 12 KB diff --git a/config/chips/F37x.chip b/config/chips/F37x.chip index dfe59af0f..ac249f24f 100644 --- a/config/chips/F37x.chip +++ b/config/chips/F37x.chip @@ -3,7 +3,7 @@ dev_type STM32F37x ref_manual_id 0313 chip_id 0x432 // STM32_CHIPID_F37x -flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3 +flash_type F0_F1_F3 flash_size_reg 0x1ffff7cc flash_pagesize 0x800 // 2 KB sram_size 0xa000 // 40 KB diff --git a/config/chips/F401xB_xC.chip b/config/chips/F401xB_xC.chip index d961e82b0..1022f0fe9 100644 --- a/config/chips/F401xB_xC.chip +++ b/config/chips/F401xB_xC.chip @@ -3,7 +3,7 @@ dev_type STM32F401xB_xC ref_manual_id 0368 chip_id 0x423 // STM32_CHIPID_F4_LP -flash_type 3 // STM32_FLASH_TYPE_F2_F4 +flash_type F2_F4 flash_size_reg 0x1fff7a22 flash_pagesize 0x4000 // 16 KB sram_size 0x10000 // 64 KB diff --git a/config/chips/F401xD_xE.chip b/config/chips/F401xD_xE.chip index 1b58cb5ad..39748a604 100644 --- a/config/chips/F401xD_xE.chip +++ b/config/chips/F401xD_xE.chip @@ -3,7 +3,7 @@ dev_type STM32F401xD_xE ref_manual_id 0368 chip_id 0x433 // STM32_CHIPID_F4_DE -flash_type 3 // STM32_FLASH_TYPE_F2_F4 +flash_type F2_F4 flash_size_reg 0x1fff7a22 flash_pagesize 0x4000 // 16 KB sram_size 0x18000 // 96 KB diff --git a/config/chips/F410.chip b/config/chips/F410.chip index 55dbb749d..5c19450f6 100644 --- a/config/chips/F410.chip +++ b/config/chips/F410.chip @@ -3,7 +3,7 @@ dev_type STM32F410 ref_manual_id 0401 chip_id 0x458 // STM32_CHIPID_F410 -flash_type 3 // STM32_FLASH_TYPE_F2_F4 +flash_type F2_F4 flash_size_reg 0x1fff7a22 flash_pagesize 0x4000 // 16 KB sram_size 0x8000 // 32 KB diff --git a/config/chips/F411xC_xE.chip b/config/chips/F411xC_xE.chip index 51081d338..ce93aea26 100644 --- a/config/chips/F411xC_xE.chip +++ b/config/chips/F411xC_xE.chip @@ -3,7 +3,7 @@ dev_type STM32F411xC_xE ref_manual_id 0383 chip_id 0x431 // STM32_CHIPID_F411xx -flash_type 3 // STM32_FLASH_TYPE_F2_F4 +flash_type F2_F4 flash_size_reg 0x1fff7a22 flash_pagesize 0x4000 // 16 KB sram_size 0x20000 // 128 KB diff --git a/config/chips/F412.chip b/config/chips/F412.chip index 6e7aefd19..a04268349 100644 --- a/config/chips/F412.chip +++ b/config/chips/F412.chip @@ -3,7 +3,7 @@ dev_type STM32F412 ref_manual_id 0402 chip_id 0x441 // STM32_CHIPID_F412 -flash_type 3 // STM32_FLASH_TYPE_F2_F4 +flash_type F2_F4 flash_size_reg 0x1fff7a22 flash_pagesize 0x4000 // 16 KB sram_size 0x40000 // 256 KB diff --git a/config/chips/F413_F423.chip b/config/chips/F413_F423.chip index 3a865d304..bb5dd5880 100644 --- a/config/chips/F413_F423.chip +++ b/config/chips/F413_F423.chip @@ -3,7 +3,7 @@ dev_type STM32F413_F423 ref_manual_id 0430 // RM0430 (Rev 2) chip_id 0x463 // STM32_CHIPID_F413 -flash_type 3 // STM32_FLASH_TYPE_F2_F4 +flash_type F2_F4 flash_size_reg 0x1fff7a22 flash_pagesize 0x4000 // 16 KB sram_size 0x50000 // 320 KB diff --git a/config/chips/F42x_F43x.chip b/config/chips/F42x_F43x.chip index 64f459064..4452780b3 100644 --- a/config/chips/F42x_F43x.chip +++ b/config/chips/F42x_F43x.chip @@ -3,7 +3,7 @@ dev_type STM32F42x_F43x ref_manual_id 0090 // RM0090 (Rev. 2) chip_id 0x463 // STM32_CHIPID_F4_HD -flash_type 3 // STM32_FLASH_TYPE_F2_F4 +flash_type F2_F4 flash_size_reg 0x1fff7a22 flash_pagesize 0x4000 // 16 KB sram_size 0x40000 // 256 KB diff --git a/config/chips/F446.chip b/config/chips/F446.chip index 51ee52517..e4d0bdec2 100644 --- a/config/chips/F446.chip +++ b/config/chips/F446.chip @@ -3,7 +3,7 @@ dev_type STM32F446 ref_manual_id 0390 chip_id 0x421 // STM32_CHIPID_F446 -flash_type 3 // STM32_FLASH_TYPE_F2_F4 +flash_type F2_F4 flash_size_reg 0x1fff7a22 flash_pagesize 0x20000 // 128 KB sram_size 0x20000 // 128 KB diff --git a/config/chips/F46x_F47x.chip b/config/chips/F46x_F47x.chip index 4d3931091..f20715ded 100644 --- a/config/chips/F46x_F47x.chip +++ b/config/chips/F46x_F47x.chip @@ -3,7 +3,7 @@ dev_type STM32F46x_F47x ref_manual_id 0090 // RM0090 (Rev. 2) chip_id 0x434 // STM32_CHIPID_F4_DSI -flash_type 3 // STM32_FLASH_TYPE_F2_F4 +flash_type F2_F4 flash_size_reg 0x1fff7a22 flash_pagesize 0x4000 // 16 KB sram_size 0x40000 // 256 KB diff --git a/config/chips/F4x5_F4x7.chip b/config/chips/F4x5_F4x7.chip index f65281272..586ff0b8f 100644 --- a/config/chips/F4x5_F4x7.chip +++ b/config/chips/F4x5_F4x7.chip @@ -3,7 +3,7 @@ dev_type STM32F4x5_F4x7 ref_manual_id 0090 // RM0090 (Rev. 2) chip_id 0x413 // STM32_CHIPID_F4 -flash_type 3 // STM32_FLASH_TYPE_F2_F4 +flash_type F2_F4 flash_size_reg 0x1fff7a22 flash_pagesize 0x4000 // 16 KB sram_size 0x30000 // 192 KB diff --git a/config/chips/F72x_F73x.chip b/config/chips/F72x_F73x.chip index acd411bed..04af2bb3e 100644 --- a/config/chips/F72x_F73x.chip +++ b/config/chips/F72x_F73x.chip @@ -3,7 +3,7 @@ dev_type STM32F72x_F73x ref_manual_id 0431 chip_id 0x452 // STM32_CHIPID_F72xxx -flash_type 4 // STM32_FLASH_TYPE_F7 +flash_type F7 flash_size_reg 0x1ff07a22 flash_pagesize 0x800 // 2 KB sram_size 0x40000 // 256 KB diff --git a/config/chips/F74x_F75x.chip b/config/chips/F74x_F75x.chip index e081da39d..0664bb2d0 100644 --- a/config/chips/F74x_F75x.chip +++ b/config/chips/F74x_F75x.chip @@ -3,7 +3,7 @@ dev_type STM32F74x_F75x ref_manual_id 0385 chip_id 0x449 // STM32_CHIPID_F7 -flash_type 4 // STM32_FLASH_TYPE_F7 +flash_type F7 flash_size_reg 0x1ff0f442 flash_pagesize 0x800 // 2 KB sram_size 0x50000 // 320 KB diff --git a/config/chips/F76x_F77x.chip b/config/chips/F76x_F77x.chip index c6d04ff78..dfc983254 100644 --- a/config/chips/F76x_F77x.chip +++ b/config/chips/F76x_F77x.chip @@ -3,7 +3,7 @@ dev_type STM32F76x_F77x ref_manual_id 0410 chip_id 0x451 // STM32_CHIPID_F76xxx -flash_type 4 // STM32_FLASH_TYPE_F7 +flash_type F7 flash_size_reg 0x1ff0f442 flash_pagesize 0x800 // 2 KB sram_size 0x80000 // 512 KB diff --git a/config/chips/G03x_G04x.chip b/config/chips/G03x_G04x.chip index fd6dc3bcf..a414b52ab 100644 --- a/config/chips/G03x_G04x.chip +++ b/config/chips/G03x_G04x.chip @@ -3,7 +3,7 @@ dev_type STM32G03x_G04x ref_manual_id 0444 // also RM454 chip_id 0x466 // STM32_CHIPID_G0_CAT1 -flash_type 5 // STM32_FLASH_TYPE_G0 +flash_type G0 flash_size_reg 0x1fff75e0 flash_pagesize 0x800 // 2 KB sram_size 0x2000 // 8 KB diff --git a/config/chips/G05x_G06x.chip b/config/chips/G05x_G06x.chip index ce5e52de4..ae074e584 100644 --- a/config/chips/G05x_G06x.chip +++ b/config/chips/G05x_G06x.chip @@ -3,7 +3,7 @@ dev_type STM32G05x_G06x ref_manual_id 0444 chip_id 0x456 // STM32_CHIPID_G0_CAT4 -flash_type 5 // STM32_FLASH_TYPE_G0 +flash_type G0 flash_size_reg 0x1fff75e0 flash_pagesize 0x800 // 2 KB sram_size 0x9000 // 36 KB diff --git a/config/chips/G07x_G08x.chip b/config/chips/G07x_G08x.chip index 7a10fc052..82b3992c2 100644 --- a/config/chips/G07x_G08x.chip +++ b/config/chips/G07x_G08x.chip @@ -3,7 +3,7 @@ dev_type STM32G07x_G08x ref_manual_id 0444 chip_id 0x460 // STM32_CHIPID_G0_CAT2 -flash_type 5 // STM32_FLASH_TYPE_G0 +flash_type G0 flash_size_reg 0x1fff75e0 flash_pagesize 0x800 // 2 KB sram_size 0x9000 // 36 KB diff --git a/config/chips/G0Bx_G0Cx.chip b/config/chips/G0Bx_G0Cx.chip index 6ab8ca55a..f21fd65a0 100644 --- a/config/chips/G0Bx_G0Cx.chip +++ b/config/chips/G0Bx_G0Cx.chip @@ -3,7 +3,7 @@ dev_type STM32G0Bx_G0Cx ref_manual_id 0444 chip_id 0x467 // STM32_CHIPID_G0_CAT3 -flash_type 5 // STM32_FLASH_TYPE_G0 +flash_type G0 flash_size_reg 0x1fff75e0 flash_pagesize 0x800 // 2 KB sram_size 0x9000 // 36 KB diff --git a/config/chips/G43x_G44x.chip b/config/chips/G43x_G44x.chip index a7eb86d34..26d1b2f1f 100644 --- a/config/chips/G43x_G44x.chip +++ b/config/chips/G43x_G44x.chip @@ -3,7 +3,7 @@ dev_type STM32G43x_G44x ref_manual_id 0440 chip_id 0x468 // STM32_CHIPID_G4_CAT2 -flash_type 6 // STM32_FLASH_TYPE_G4 +flash_type G4 flash_size_reg 0x1fff75e0 flash_pagesize 0x800 // 2 KB sram_size 0x8000 // 32 KB diff --git a/config/chips/G47x_G48x.chip b/config/chips/G47x_G48x.chip index 1b2b386fd..707727aca 100644 --- a/config/chips/G47x_G48x.chip +++ b/config/chips/G47x_G48x.chip @@ -3,7 +3,7 @@ dev_type STM32G47x_G48x ref_manual_id 0440 chip_id 0x469 // STM32_CHIPID_G4_CAT3 -flash_type 6 // STM32_FLASH_TYPE_G4 +flash_type G4 flash_size_reg 0x1fff75e0 flash_pagesize 0x800 // 2 KB sram_size 0x20000 // 128 KB diff --git a/config/chips/G49x_G4Ax.chip b/config/chips/G49x_G4Ax.chip index 1defbfff8..3e8aacf4b 100644 --- a/config/chips/G49x_G4Ax.chip +++ b/config/chips/G49x_G4Ax.chip @@ -3,7 +3,7 @@ dev_type STM32G49x_G4Ax ref_manual_id 0440 chip_id 0x479 // STM32_CHIPID_G4_CAT4 -flash_type 6 // STM32_FLASH_TYPE_G4 +flash_type G4 flash_size_reg 0x1fff75e0 flash_pagesize 0x800 // 2 KB sram_size 0x1c000 // 112 KB diff --git a/config/chips/H72x_H73x.chip b/config/chips/H72x_H73x.chip index 50925fdcd..194b740d4 100644 --- a/config/chips/H72x_H73x.chip +++ b/config/chips/H72x_H73x.chip @@ -3,7 +3,7 @@ dev_type STM32H72x_H73x ref_manual_id 0468 chip_id 0x483 // STM32_CHIPID_H72x -flash_type 7 // STM32_FLASH_TYPE_H7 +flash_type H7 flash_size_reg 0x1ff1e880 flash_pagesize 0x20000 // 128 KB sram_size 0x20000 // 128 KB "DTCM" diff --git a/config/chips/H74x_H75x.chip b/config/chips/H74x_H75x.chip index 20bfcd2cb..2b829f792 100644 --- a/config/chips/H74x_H75x.chip +++ b/config/chips/H74x_H75x.chip @@ -3,7 +3,7 @@ dev_type STM32H74x_H75x ref_manual_id 0433 chip_id 0x450 // STM32_CHIPID_H74xxx -flash_type 7 // STM32_FLASH_TYPE_H7 +flash_type H7 flash_size_reg 0x1ff1e880 flash_pagesize 0x20000 // 128 KB sram_size 0x20000 // 128 KB "DTCM" diff --git a/config/chips/H7Ax_H7Bx.chip b/config/chips/H7Ax_H7Bx.chip index b31e4fb88..0f66d2c77 100644 --- a/config/chips/H7Ax_H7Bx.chip +++ b/config/chips/H7Ax_H7Bx.chip @@ -3,7 +3,7 @@ dev_type STM32H7Ax_H7Bx ref_manual_id 0455 chip_id 0x480 // STM32_CHIPID_H7Ax -flash_type 7 // STM32_FLASH_TYPE_H7 +flash_type H7 flash_size_reg 0x08fff80c flash_pagesize 0x2000 // 8 KB sram_size 0x20000 // 128 KB "DTCM" diff --git a/config/chips/L0xxx_Cat_1.chip b/config/chips/L0xxx_Cat_1.chip index d612143d5..2cce4e23c 100644 --- a/config/chips/L0xxx_Cat_1.chip +++ b/config/chips/L0xxx_Cat_1.chip @@ -3,7 +3,7 @@ dev_type STM32L0xxx_Cat_1 ref_manual_id 0451 // also RM0377 chip_id 0x457 // STM32_CHIPID_L011 -flash_type 8 // STM32_FLASH_TYPE_L0_L1 +flash_type L0_L1 flash_size_reg 0x1ff8007c flash_pagesize 0x80 // 128 B sram_size 0x2000 // 8 KB diff --git a/config/chips/L0xxx_Cat_2.chip b/config/chips/L0xxx_Cat_2.chip index 49d3e8b07..aae0fac7b 100644 --- a/config/chips/L0xxx_Cat_2.chip +++ b/config/chips/L0xxx_Cat_2.chip @@ -3,7 +3,7 @@ dev_type STM32L0xxx_Cat_2 ref_manual_id 0451 // also RM0377 chip_id 0x425 // STM32_CHIPID_L0_CAT2 -flash_type 8 // STM32_FLASH_TYPE_L0_L1 +flash_type L0_L1 flash_size_reg 0x1ff8007c flash_pagesize 0x80 // 128 B sram_size 0x2000 // 8 KB diff --git a/config/chips/L0xxx_Cat_3.chip b/config/chips/L0xxx_Cat_3.chip index c1b6c3bf4..a04dc8376 100644 --- a/config/chips/L0xxx_Cat_3.chip +++ b/config/chips/L0xxx_Cat_3.chip @@ -3,7 +3,7 @@ dev_type STM32L0xxx_Cat_3 ref_manual_id 0451 // also RM0367 & RM0377 chip_id 0x417 // STM32_CHIPID_L0 -flash_type 8 // STM32_FLASH_TYPE_L0_L1 +flash_type L0_L1 flash_size_reg 0x1ff8007c flash_pagesize 0x80 // 128 B sram_size 0x2000 // 8 KB diff --git a/config/chips/L0xxx_Cat_5.chip b/config/chips/L0xxx_Cat_5.chip index 94e14dfe0..22cbb200a 100644 --- a/config/chips/L0xxx_Cat_5.chip +++ b/config/chips/L0xxx_Cat_5.chip @@ -3,7 +3,7 @@ dev_type STM32L0xxx_Cat_5 ref_manual_id 0451 // also RM0367 & RM0377 chip_id 0x447 // STM32_CHIPID_L0_CAT5 -flash_type 8 // STM32_FLASH_TYPE_L0_L1 +flash_type L0_L1 flash_size_reg 0x1ff8007c flash_pagesize 0x80 // 128 B sram_size 0x5000 // 20 KB diff --git a/config/chips/L1xx_Cat_1.chip b/config/chips/L1xx_Cat_1.chip index 16f2ff8c9..b1b3e85e7 100644 --- a/config/chips/L1xx_Cat_1.chip +++ b/config/chips/L1xx_Cat_1.chip @@ -3,7 +3,7 @@ dev_type STM32L1xx_Cat_1 ref_manual_id 0038 chip_id 0x416 // STM32_CHIPID_L1_MD -flash_type 8 // STM32_FLASH_TYPE_L0_L1 +flash_type L0_L1 flash_size_reg 0x1ff8004c flash_pagesize 0x100 // 128 B sram_size 0x4000 // 16 KB diff --git a/config/chips/L1xx_Cat_2.chip b/config/chips/L1xx_Cat_2.chip index 82d7dfe44..695f60d7f 100644 --- a/config/chips/L1xx_Cat_2.chip +++ b/config/chips/L1xx_Cat_2.chip @@ -3,7 +3,7 @@ dev_type STM32L1xx_Cat_2 ref_manual_id 0038 chip_id 0x429 // STM32_CHIPID_L1_CAT2 -flash_type 8 // STM32_FLASH_TYPE_L0_L1 +flash_type L0_L1 flash_size_reg 0x1ff8004c flash_pagesize 0x100 // 128 B sram_size 0x8000 // 32 KB diff --git a/config/chips/L1xx_Cat_3.chip b/config/chips/L1xx_Cat_3.chip index 2241e5bde..43e21f517 100644 --- a/config/chips/L1xx_Cat_3.chip +++ b/config/chips/L1xx_Cat_3.chip @@ -3,7 +3,7 @@ dev_type STM32L1xx_Cat_3 ref_manual_id 0038 chip_id 0x427 // STM32_CHIPID_L1_MD_PLUS -flash_type 8 // STM32_FLASH_TYPE_L0_L1 +flash_type L0_L1 flash_size_reg 0x1ff800cc flash_pagesize 0x100 // 128 B sram_size 0x8000 // 32 KB diff --git a/config/chips/L1xx_Cat_4.chip b/config/chips/L1xx_Cat_4.chip index 7933d7121..a36118937 100644 --- a/config/chips/L1xx_Cat_4.chip +++ b/config/chips/L1xx_Cat_4.chip @@ -3,7 +3,7 @@ dev_type STM32L1xx_Cat_4 ref_manual_id 0038 chip_id 0x436 // STM32_CHIPID_L1_MD_PLUS_HD -flash_type 8 // STM32_FLASH_TYPE_L0_L1 +flash_type L0_L1 flash_size_reg 0x1ff800cc flash_pagesize 0x100 // 128 B sram_size 0xc000 // 48 KB diff --git a/config/chips/L1xx_Cat_5.chip b/config/chips/L1xx_Cat_5.chip index 0e95e54e8..a487b22bc 100644 --- a/config/chips/L1xx_Cat_5.chip +++ b/config/chips/L1xx_Cat_5.chip @@ -3,7 +3,7 @@ dev_type STM32L1xx_Cat_5 ref_manual_id 0038 chip_id 0x437 // STM32_CHIPID_L152_RE -flash_type 8 // STM32_FLASH_TYPE_L0_L1 +flash_type L0_L1 flash_size_reg 0x1ff800cc flash_pagesize 0x100 // 128 B sram_size 0x14000 // 80 KB diff --git a/config/chips/L41x_L42x.chip b/config/chips/L41x_L42x.chip index 726645552..11e545bb7 100644 --- a/config/chips/L41x_L42x.chip +++ b/config/chips/L41x_L42x.chip @@ -3,7 +3,7 @@ dev_type STM32L41x_L42x ref_manual_id 0394 chip_id 0x464 // STM32_CHIPID_L41x_L42x -flash_type 9 // STM32_FLASH_TYPE_L4_L4P +flash_type L4_L4P flash_size_reg 0x1fff75e0 flash_pagesize 0x800 // 2 KB sram_size 0xa000 // 40 KB diff --git a/config/chips/L43x_L44x.chip b/config/chips/L43x_L44x.chip index baba13e55..f0a959693 100644 --- a/config/chips/L43x_L44x.chip +++ b/config/chips/L43x_L44x.chip @@ -3,7 +3,7 @@ dev_type STM32L41x_L42x ref_manual_id 0392 chip_id 0x435 // STM32_CHIPID_L43x_L44x -flash_type 9 // STM32_FLASH_TYPE_L4_L4P +flash_type L4_L4P flash_size_reg 0x1fff75e0 flash_pagesize 0x800 // 2 KB sram_size 0xc000 // 48 KB diff --git a/config/chips/L45x_L46x.chip b/config/chips/L45x_L46x.chip index 8886633e2..267122f87 100644 --- a/config/chips/L45x_L46x.chip +++ b/config/chips/L45x_L46x.chip @@ -3,7 +3,7 @@ dev_type STM32L45x_L46x ref_manual_id 0394 chip_id 0x462 // STM32_CHIPID_L45x_L46x -flash_type 9 // STM32_FLASH_TYPE_L4_L4P +flash_type L4_L4P flash_size_reg 0x1fff75e0 flash_pagesize 0x800 // 2 KB sram_size 0x20000 // 128 KB diff --git a/config/chips/L47x_L48x.chip b/config/chips/L47x_L48x.chip index df96ee2fb..421663e58 100644 --- a/config/chips/L47x_L48x.chip +++ b/config/chips/L47x_L48x.chip @@ -3,7 +3,7 @@ dev_type STM32L47x_L48x ref_manual_id 0351 chip_id 0x415 // STM32_CHIPID_L4 -flash_type 9 // STM32_FLASH_TYPE_L4_L4P +flash_type L4_L4P flash_size_reg 0x1fff75e0 flash_pagesize 0x800 // 2 KB sram_size 0x18000 // 96 KB diff --git a/config/chips/L496x_L4A6x.chip b/config/chips/L496x_L4A6x.chip index 0f4bd285d..df1f084ff 100644 --- a/config/chips/L496x_L4A6x.chip +++ b/config/chips/L496x_L4A6x.chip @@ -3,7 +3,7 @@ dev_type STM32L496x_L4A6x ref_manual_id 0351 chip_id 0x461 // STM32_CHIPID_L496x_L4A6x -flash_type 9 // STM32_FLASH_TYPE_L4_L4P +flash_type L4_L4P flash_size_reg 0x1fff75e0 flash_pagesize 0x800 // 2 KB sram_size 0x40000 // 256 KB diff --git a/config/chips/L4Px.chip b/config/chips/L4Px.chip index 2d1a59806..39788eabe 100644 --- a/config/chips/L4Px.chip +++ b/config/chips/L4Px.chip @@ -3,7 +3,7 @@ dev_type STM32L4Px ref_manual_id 0432 chip_id 0x471 // STM32_CHIPID_L4PX -flash_type 9 // STM32_FLASH_TYPE_L4_L4P +flash_type L4_L4P flash_size_reg 0x1fff75e0 flash_pagesize 0x1000 // 4 KB sram_size 0xa0000 // 640 KB diff --git a/config/chips/L4Rx.chip b/config/chips/L4Rx.chip index f0593a97e..b5c2d0d80 100644 --- a/config/chips/L4Rx.chip +++ b/config/chips/L4Rx.chip @@ -3,7 +3,7 @@ dev_type STM32L4Rx ref_manual_id 0432 chip_id 0x470 // STM32_CHIPID_L4RX -flash_type 9 // STM32_FLASH_TYPE_L4_L4P +flash_type L4_L4P flash_size_reg 0x1fff75e0 flash_pagesize 0x1000 // 4 KB sram_size 0xa0000 // 640 KB diff --git a/config/chips/L5x5.chip b/config/chips/L5x5.chip.txt similarity index 85% rename from config/chips/L5x5.chip rename to config/chips/L5x5.chip.txt index 9a5b2fdbf..ce268148b 100644 --- a/config/chips/L5x5.chip +++ b/config/chips/L5x5.chip.txt @@ -3,7 +3,7 @@ dev_type STM32L5x2 ref_manual_id 0438 chip_id 0x0 // (temporary setting only!) -flash_type 10 // (temporary setting only!) +flash_type 0 // (temporary setting only!) flash_size_reg 0x0bfa07a0 flash_pagesize 0x2000 // 8 KB sram_size 0x40000 // 256 KB diff --git a/config/chips/U5x5.chip b/config/chips/U5x5.chip.txt similarity index 85% rename from config/chips/U5x5.chip rename to config/chips/U5x5.chip.txt index 55dfdaf7d..177359cc3 100644 --- a/config/chips/U5x5.chip +++ b/config/chips/U5x5.chip.txt @@ -3,7 +3,7 @@ dev_type STM32U5x5 ref_manual_id 0456 chip_id 0x0 // (temporary setting only!) -flash_type 10 // (temporary setting only!) +flash_type 0 // (temporary setting only!) flash_size_reg 0x0bfa07a0 flash_pagesize 0x2000 // 8 KB sram_size 0xc4800 // 786 KB diff --git a/config/chips/WBx0_WBx5.chip b/config/chips/WBx0_WBx5.chip index 3d27edd6d..2747386f8 100644 --- a/config/chips/WBx0_WBx5.chip +++ b/config/chips/WBx0_WBx5.chip @@ -3,7 +3,7 @@ dev_type STM32WBx0_WBx5 ref_manual_id 0434 // also RM0471 chip_id 0x495 // STM32_CHIPID_WB55 -flash_type 11 // STM32_FLASH_TYPE_WB_WL +flash_type WB_WL flash_size_reg 0x1fff75e0 flash_pagesize 0x1000 // 4 KB sram_size 0x40000 // 256 KB diff --git a/config/chips/WLx5.chip b/config/chips/WLx5.chip index 9669fe27f..5bc9d90dc 100644 --- a/config/chips/WLx5.chip +++ b/config/chips/WLx5.chip @@ -3,7 +3,7 @@ dev_type STM32WLEx ref_manual_id 0033 chip_id 0x497 // STM32_CHIPID_WLE -flash_type 11 // STM32_FLASH_TYPE_WB_WL +flash_type WB_WL flash_size_reg 0x1fff75e0 flash_pagesize 0x800 // 2 KB sram_size 0x10000 // 64 KB diff --git a/config/chips/unknown_device.chip b/config/chips/unknown_device.chip index bc50e7a00..4eb0c6cbf 100644 --- a/config/chips/unknown_device.chip +++ b/config/chips/unknown_device.chip @@ -3,7 +3,7 @@ dev_type unknown ref_manual_id 0000 chip_id 0x0 // STM32_CHIPID_UNKNOWN -flash_type 0 // STM32_FLASH_TYPE_UNKNOWN +flash_type UNKNOWN flash_size_reg 0x0 flash_pagesize 0x0 sram_size 0x0 diff --git a/inc/stm32.h b/inc/stm32.h index 56176bd6f..d6bbe506c 100644 --- a/inc/stm32.h +++ b/inc/stm32.h @@ -8,47 +8,39 @@ #define STM32_H /* STM32 Cortex-M core ids (CPUTAPID) */ -#define STM32_CORE_ID_M0_SWD 0x0bb11477 // (RM0091 Section 32.5.3) F0 SW-DP +enum stm32_core_id { + STM32_CORE_ID_M0_SWD = 0x0bb11477, // (RM0091 Section 32.5.3) F0 SW-DP // (RM0444 Section 40.5.3) G0 SW-DP - -#define STM32_CORE_ID_M0P_SWD 0x0bc11477 // (RM0385 Section 27.5.3) L0 SW-DP - -#define STM32_CORE_ID_M3_r1p1_SWD 0x1ba01477 // (RM0008 Section 31.8.3) F1 SW-DP -#define STM32_CORE_ID_M3_r1p1_JTAG 0x3ba00477 // (RM0008 Section 31.6.3) F1 JTAG - -#define STM32_CORE_ID_M3_r2p0_SWD 0x2ba01477 // (RM0033 Section 32.8.3) F2 SW-DP + STM32_CORE_ID_M0P_SWD = 0x0bc11477, // (RM0385 Section 27.5.3) L0 SW-DP + STM32_CORE_ID_M3_r1p1_SWD = 0x1ba01477, // (RM0008 Section 31.8.3) F1 SW-DP + STM32_CORE_ID_M3_r1p1_JTAG = 0x3ba00477, // (RM0008 Section 31.6.3) F1 JTAG + STM32_CORE_ID_M3_r2p0_SWD = 0x2ba01477, // (RM0033 Section 32.8.3) F2 SW-DP // (RM0038 Section 30.8.3) L1 SW-DP -#define STM32_CORE_ID_M3_r2p0_JTAG 0x0ba00477 // (RM0033 Section 32.6.3) F2 JTAG + STM32_CORE_ID_M3_r2p0_JTAG = 0x0ba00477, // (RM0033 Section 32.6.3) F2 JTAG // (RM0038 Section 30.6.2) L1 JTAG - -#define STM32_CORE_ID_M4_r0p1_SWD 0x1ba01477 // (RM0316 Section 33.8.3) F3 SW-DP + STM32_CORE_ID_M4_r0p1_SWD = 0x1ba01477, // (RM0316 Section 33.8.3) F3 SW-DP // (RM0351 Section 48.8.3) L4 SW-DP // (RM0432 Section 57.8.3) L4+ SW-DP -#define STM32_CORE_ID_M4_r0p1_JTAG 0x4ba00477 // (RM0316 Section 33.6.3) F3 JTAG + STM32_CORE_ID_M4_r0p1_JTAG = 0x4ba00477, // (RM0316 Section 33.6.3) F3 JTAG // (RM0351 Section 48.6.3) L4 JTAG // (RM0432 Section 57.6.3) L4+ JTAG - -#define STM32_CORE_ID_M4F_r0p1_SWD 0x2ba01477 // (RM0090 Section 38.8.3) F4 SW-DP + STM32_CORE_ID_M4F_r0p1_SWD = 0x2ba01477, // (RM0090 Section 38.8.3) F4 SW-DP // (RM0090 Section 47.8.3) G4 SW-DP -#define STM32_CORE_ID_M4F_r0p1_JTAG 0x4ba00477 // (RM0090 Section 38.6.3) F4 JTAG + STM32_CORE_ID_M4F_r0p1_JTAG = 0x4ba00477, // (RM0090 Section 38.6.3) F4 JTAG // (RM0090 Section 47.6.3) G4 JTAG - -#define STM32_CORE_ID_M7F_SWD 0x5ba02477 // (RM0385 Section 40.8.3) F7 SW-DP -#define STM32_CORE_ID_M7F_JTAG 0x5ba00477 // (RM0385 Section 40.6.3) F7 JTAG - -#define STM32_CORE_ID_M7F_H7_SWD 0x6ba02477 // (RM0433 Section 60.4.1) H7 SW-DP -#define STM32_CORE_ID_M7F_H7_JTAG 0x6ba00477 // (RM0433 Section 60.4.1) H7 JTAG - -#define STM32_CORE_ID_M33_SWD 0x0be02477 // (RM0438 Section 52.2.10) L5 SW-DP + STM32_CORE_ID_M7F_SWD = 0x5ba02477, // (RM0385 Section 40.8.3) F7 SW-DP + STM32_CORE_ID_M7F_JTAG = 0x5ba00477, // (RM0385 Section 40.6.3) F7 JTAG + STM32_CORE_ID_M7F_H7_SWD = 0x6ba02477, // (RM0433 Section 60.4.1) H7 SW-DP + STM32_CORE_ID_M7F_H7_JTAG = 0x6ba00477, // (RM0433 Section 60.4.1) H7 JTAG + STM32_CORE_ID_M33_SWD = 0x0be02477, // (RM0438 Section 52.2.10) L5 SW-DP // (RM0456 Section 65.3.3) U5 SW-DP -#define STM32_CORE_ID_M33_JTAGD 0x0be01477 // (RM0438 Section 52.2.10) L5 JTAG-DP + STM32_CORE_ID_M33_JTAGD = 0x0be01477, // (RM0438 Section 52.2.10) L5 JTAG-DP // (RM0456 Section 65.3.3) U5 JTAG-DP -#define STM32_CORE_ID_M33_JTAG 0x0ba04477 // (RM0438 Section 52.2.8) L5 JTAG + STM32_CORE_ID_M33_JTAG = 0x0ba04477, // (RM0438 Section 52.2.8) L5 JTAG // (RM0456 Section 56.3.1) U5 JTAG +}; /* STM32 flash types */ -// New flash type definitions must go before STM32_FLASH_TYPE_UNDEFINED -// with the latter updated to the highest enum value. enum stm32_flash_type { STM32_FLASH_TYPE_UNKNOWN = 0, STM32_FLASH_TYPE_F0_F1_F3 = 1, @@ -62,7 +54,6 @@ enum stm32_flash_type { STM32_FLASH_TYPE_L4_L4P = 9, STM32_FLASH_TYPE_L5_U5 = 10, STM32_FLASH_TYPE_WB_WL = 11, - STM32_FLASH_TYPE_UNDEFINED = 12, // max. value exceeded }; /* STM32 chip-ids */ @@ -70,7 +61,7 @@ enum stm32_flash_type { // stm32 chipids, only lower 12 bits... enum stm32_chipids { - STM32_CHIPID_UNKNOWN = 0x000, + STM32_CHIPID_UNKNOWN = 0x000, STM32_CHIPID_F1_MD = 0x410, /* medium density */ STM32_CHIPID_F2 = 0x411, diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index dbfd2882d..e68f6e371 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -1,3 +1,4 @@ +#include #include #include "chipid.h" @@ -7,7 +8,6 @@ #include #include - static struct stlink_chipid_params *devicelist; void dump_a_chip (FILE *fp, struct stlink_chipid_params *dev) { @@ -28,7 +28,6 @@ void dump_a_chip (FILE *fp, struct stlink_chipid_params *dev) { struct stlink_chipid_params *stlink_chipid_get_params(uint32_t chip_id) { struct stlink_chipid_params *params = NULL; -// struct stlink_chipid_params *p2; for (params = devicelist; params != NULL; params = params->next) if (params->chip_id == chip_id) { fprintf(stderr, "\ndetected chip_id parametres\n\n"); @@ -74,7 +73,7 @@ void process_chipfile(char *fname) { buf[strlen(p) - 1] = 0; // chomp newline sscanf(p, "%*s %n", &nc); ts->dev_type = strdup(p + nc); - } else if (strcmp (word, "ref_manual_id") == 0) { + } else if (strcmp(word, "ref_manual_id") == 0) { // ts->ref_manual_id = strdup (value); buf[strlen(p) - 1] = 0; // chomp newline sscanf(p, "%*s %n", &nc); @@ -83,59 +82,80 @@ void process_chipfile(char *fname) { if (sscanf(value, "%i", &ts->chip_id) < 1) { fprintf(stderr, "Failed to parse chip-id\n"); } - } else if (strcmp (word, "flash_type") == 0) { - if (sscanf(value, "%i", (int *)&ts->flash_type) < 1) { - fprintf(stderr, "Failed to parse flash type\n"); - } else if ((ts->flash_type < STM32_FLASH_TYPE_UNKNOWN) || (ts->flash_type >= STM32_FLASH_TYPE_UNDEFINED)) { - fprintf(stderr, "Unrecognized flash type\n"); + } else if (strcmp(word, "flash_type") == 0) { + if (strcmp(value, "F0_F1_F3") == 0) { + ts->flash_type = STM32_FLASH_TYPE_F0_F1_F3; + } else if (strcmp(value, "F1_XL") == 0) { + ts->flash_type = STM32_FLASH_TYPE_F1_XL; + } else if (strcmp(value, "F2_F4") == 0) { + ts->flash_type = STM32_FLASH_TYPE_F2_F4; + } else if (strcmp(value, "F7") == 0) { + ts->flash_type = STM32_FLASH_TYPE_F7; + } else if (strcmp(value, "G0") == 0) { + ts->flash_type = STM32_FLASH_TYPE_G0; + } else if (strcmp(value, "G4") == 0) { + ts->flash_type = STM32_FLASH_TYPE_G4; + } else if (strcmp(value, "H7") == 0) { + ts->flash_type = STM32_FLASH_TYPE_H7; + } else if (strcmp(value, "L0_L1") == 0) { + ts->flash_type = STM32_FLASH_TYPE_L0_L1; + } else if (strcmp(value, "L4_L4P") == 0) { + ts->flash_type = STM32_FLASH_TYPE_L4_L4P; + } else if (strcmp(value, "L5_U5") == 0) { + ts->flash_type = STM32_FLASH_TYPE_L5_U5; + } else if (strcmp(value, "WB_WL") == 0) { + ts->flash_type = STM32_FLASH_TYPE_WB_WL; + } else { + ts->flash_type = STM32_FLASH_TYPE_UNKNOWN; + fprintf(stderr, "Failed to parse flash type or unrecognized flash type\n"); } - } else if (strcmp (word, "flash_size_reg") == 0) { + } else if (strcmp(word, "flash_size_reg") == 0) { if (sscanf(value, "%i", &ts->flash_size_reg) < 1) { fprintf(stderr, "Failed to parse flash size reg\n"); } - } else if (strcmp (word, "flash_pagesize") == 0) { + } else if (strcmp(word, "flash_pagesize") == 0) { if (sscanf(value, "%i", &ts->flash_pagesize) < 1) { fprintf(stderr, "Failed to parse flash page size\n"); } - } else if (strcmp (word, "sram_size") == 0) { + } else if (strcmp(word, "sram_size") == 0) { if (sscanf(value, "%i", &ts->sram_size) < 1) { fprintf(stderr, "Failed to parse SRAM size\n"); } - } else if (strcmp (word, "bootrom_base") == 0) { + } else if (strcmp(word, "bootrom_base") == 0) { if (sscanf(value, "%i", &ts->bootrom_base) < 1) { fprintf(stderr, "Failed to parse BootROM base\n"); } - } else if (strcmp (word, "bootrom_size") == 0) { + } else if (strcmp(word, "bootrom_size") == 0) { if (sscanf(value, "%i", &ts->bootrom_size) < 1) { fprintf(stderr, "Failed to parse BootROM size\n"); } - } else if (strcmp (word, "option_base") == 0) { + } else if (strcmp(word, "option_base") == 0) { if (sscanf(value, "%i", &ts->option_base) < 1) { fprintf(stderr, "Failed to parse option base\n"); } - } else if (strcmp (word, "option_size") == 0) { + } else if (strcmp(word, "option_size") == 0) { if (sscanf(value, "%i", &ts->option_size) < 1) { fprintf(stderr, "Failed to parse option size\n"); } - } else if (strcmp (word, "flags") == 0) { + } else if (strcmp(word, "flags") == 0) { pp = strtok (p, " \t\n"); while ((pp = strtok (NULL, " \t\n"))) { - if (strcmp (pp, "none") == 0) { + if (strcmp(pp, "none") == 0) { // NOP - } else if (strcmp (pp, "dualbank") == 0) { + } else if (strcmp(pp, "dualbank") == 0) { ts->flags |= CHIP_F_HAS_DUAL_BANK; - } else if (strcmp (pp, "swo") == 0) { + } else if (strcmp(pp, "swo") == 0) { ts->flags |= CHIP_F_HAS_SWO_TRACING; } else { - fprintf (stderr, "Unknown flags word in %s: '%s'\n", + fprintf(stderr, "Unknown flags word in %s: '%s'\n", fname, pp); } } sscanf(value, "%x", &ts->flags); } else { - fprintf (stderr, "Unknown keyword in %s: %s\n", + fprintf(stderr, "Unknown keyword in %s: %s\n", fname, word); } } @@ -156,7 +176,6 @@ void init_chipids(char *dir_to_scan) { } devicelist = NULL; - // dump_chips (); d = opendir(dir_to_scan); if (d) { From fecd2baeae8afc4c69d3dce19ab99fff5ee37bef Mon Sep 17 00:00:00 2001 From: hydroconstructor Date: Fri, 21 Jan 2022 23:26:44 +0400 Subject: [PATCH 361/503] Refactoring common.c Added forgotten defines --- inc/stm32.h | 40 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/inc/stm32.h b/inc/stm32.h index 21da2f563..17b27918c 100644 --- a/inc/stm32.h +++ b/inc/stm32.h @@ -35,4 +35,44 @@ #define STM32_F3_OPTION_BYTES_BASE ((uint32_t)0x1FFFF800) #define STM32_G4_OPTION_BYTES_BASE ((uint32_t)0x1FFFF800) +#define STM32F0_DBGMCU_CR 0xE0042004 +#define STM32F0_DBGMCU_CR_IWDG_STOP 8 +#define STM32F0_DBGMCU_CR_WWDG_STOP 9 + +#define STM32F4_DBGMCU_APB1FZR1 0xE0042008 +#define STM32F4_DBGMCU_APB1FZR1_WWDG_STOP 11 +#define STM32F4_DBGMCU_APB1FZR1_IWDG_STOP 12 + +#define STM32L0_DBGMCU_APB1_FZ 0x40015808 +#define STM32L0_DBGMCU_APB1_FZ_WWDG_STOP 11 +#define STM32L0_DBGMCU_APB1_FZ_IWDG_STOP 12 + +#define STM32H7_DBGMCU_APB1HFZ 0x5C001054 +#define STM32H7_DBGMCU_APB1HFZ_IWDG_STOP 18 + +#define STM32WB_DBGMCU_APB1FZR1 0xE004203C +#define STM32WB_DBGMCU_APB1FZR1_WWDG_STOP 11 +#define STM32WB_DBGMCU_APB1FZR1_IWDG_STOP 12 + +#define STM32F1_RCC_AHBENR 0x40021014 +#define STM32F1_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN + +#define STM32F4_RCC_AHB1ENR 0x40023830 +#define STM32F4_RCC_DMAEN 0x00600000 // DMA2EN | DMA1EN + +#define STM32G0_RCC_AHBENR 0x40021038 +#define STM32G0_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN + +#define STM32G4_RCC_AHB1ENR 0x40021048 +#define STM32G4_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN + +#define STM32L0_RCC_AHBENR 0x40021030 +#define STM32L0_RCC_DMAEN 0x00000001 // DMAEN + +#define STM32H7_RCC_AHB1ENR 0x58024538 +#define STM32H7_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN + +#define STM32WB_RCC_AHB1ENR 0x58000048 +#define STM32WB_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN + #endif // STM32_H From da3d9e3f1e1a6d116df5830cf506f30ff56196b3 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Fri, 21 Jan 2022 21:31:54 +0100 Subject: [PATCH 362/503] Formatting and whitespace clean-up --- src/stlink-lib/chipid.c | 1 + src/stlink-lib/chipid.h | 2 -- src/stlink-lib/flash_loader.c | 18 +++++++++--------- src/stlink-lib/flash_loader.h | 3 +-- src/stlink-lib/libusb_settings.h | 28 +++++++++++++--------------- src/stlink-lib/logging.c | 1 + src/stlink-lib/sg.c | 1 - src/stlink-lib/sg.h | 2 -- src/stlink-lib/usb.h | 2 +- src/win32/mmap.h | 2 -- src/win32/sys_time.c | 1 + src/win32/sys_time.h | 1 - src/win32/win32_socket.c | 6 ++++-- src/win32/win32_socket.h | 6 ++++-- 14 files changed, 35 insertions(+), 39 deletions(-) diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index e68f6e371..06e8571aa 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -228,4 +228,5 @@ void init_chipids(char *dir_to_scan) { FindClose(hFind); } + #endif //defined(_WIN32) && !defined(STLINK_HAVE_DIRENT_H) diff --git a/src/stlink-lib/chipid.h b/src/stlink-lib/chipid.h index 8efcd653e..458e7c3e2 100644 --- a/src/stlink-lib/chipid.h +++ b/src/stlink-lib/chipid.h @@ -4,7 +4,6 @@ #include #include - /** Chipid parametres */ struct stlink_chipid_params { char *dev_type; @@ -25,5 +24,4 @@ struct stlink_chipid_params { struct stlink_chipid_params *stlink_chipid_get_params(uint32_t chipid); void init_chipids(char *dir_to_scan); - #endif // STLINK_CHIPID_H_ diff --git a/src/stlink-lib/flash_loader.c b/src/stlink-lib/flash_loader.c index 2b47c1114..94978a51f 100644 --- a/src/stlink-lib/flash_loader.c +++ b/src/stlink-lib/flash_loader.c @@ -7,17 +7,16 @@ #include #include "flash_loader.h" -#define FLASH_REGS_BANK2_OFS 0x40 -#define FLASH_BANK2_START_ADDR 0x08080000 +#define FLASH_REGS_BANK2_OFS 0x40 +#define FLASH_BANK2_START_ADDR 0x08080000 #define STM32F0_WDG_KR 0x40003000 #define STM32H7_WDG_KR 0x58004800 #define STM32F0_WDG_KR_KEY_RELOAD 0xAAAA -/* !!! - * !!! DO NOT MODIFY FLASH LOADERS DIRECTLY! - * !!! +/* + * !!! DO NOT MODIFY FLASH LOADERS DIRECTLY !!! * * Edit assembly files in the '/flashloaders' instead. The sizes of binary * flash loaders must be aligned by 4 (it's written by stlink_write_mem32) @@ -155,8 +154,7 @@ int stlink_flash_loader_init(stlink_t *sl, flash_loader_t *fl) { size_t size = 0; uint32_t dfsr, cfsr, hfsr; - /* Interrupt masking. - * According to DDI0419C, Table C1-7 firstly force halt */ + /* Interrupt masking according to DDI0419C, Table C1-7 firstly force halt */ stlink_write_debug32(sl, STLINK_REG_DHCSR, STLINK_REG_DHCSR_DBGKEY | STLINK_REG_DHCSR_C_DEBUGEN | STLINK_REG_DHCSR_C_HALT); @@ -354,7 +352,8 @@ int stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t targe /* Run loader */ stlink_run(sl, RUN_FLASH_LOADER); -/* This piece of code used to try to spin for .1 second by waiting doing 10000 rounds of 10 µs. +/* + * This piece of code used to try to spin for .1 second by waiting doing 10000 rounds of 10 µs. * But because this usually runs on Unix-like OSes, the 10 µs get rounded up to the "tick" * (actually almost two ticks) of the system. 1 ms. Thus, the ten thousand attempts, when * "something goes wrong" that requires the error message "flash loader run error" would wait @@ -383,7 +382,8 @@ int stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t targe // check written byte count stlink_read_reg(sl, 2, &rr); - /* The chunk size for loading is not rounded. The flash loader + /* + * The chunk size for loading is not rounded. The flash loader * subtracts the size of the written block (1-8 bytes) from * the remaining size each time. A negative value may mean that * several bytes garbage has been written due to the unaligned diff --git a/src/stlink-lib/flash_loader.h b/src/stlink-lib/flash_loader.h index bac99bdb4..85b92bef3 100644 --- a/src/stlink-lib/flash_loader.h +++ b/src/stlink-lib/flash_loader.h @@ -4,6 +4,7 @@ * This should contain all the common top level stlink interfaces, * regardless of how the backend does the work.... */ + #ifndef STLINK_FLASH_LOADER_H_ #define STLINK_FLASH_LOADER_H_ @@ -12,10 +13,8 @@ #include - int stlink_flash_loader_init(stlink_t *sl, flash_loader_t* fl); int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size); int stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, const uint8_t* buf, size_t size); - #endif // STLINK_FLASH_LOADER_H_ diff --git a/src/stlink-lib/libusb_settings.h b/src/stlink-lib/libusb_settings.h index a2dfc6d26..cc44736f9 100644 --- a/src/stlink-lib/libusb_settings.h +++ b/src/stlink-lib/libusb_settings.h @@ -4,21 +4,19 @@ #include /* - - libusb ver | LIBUSB_API_VERSION - -----------+-------------------- - v1.0.13 | 0x01000100 - v1.0.14 | 0x010000FF - v1.0.15 | 0x01000101 - v1.0.16 | 0x01000102 - v1.0.17 | 0x01000102 - v1.0.18 | 0x01000102 - v1.0.19 | 0x01000103 - v1.0.20 | 0x01000104 - v1.0.21 | 0x01000105 - v1.0.22 | 0x01000106 - v1.0.23 | 0x01000107 - + * libusb ver | LIBUSB_API_VERSION + * -----------+-------------------- + * v1.0.13 | 0x01000100 + * v1.0.14 | 0x010000FF + * v1.0.15 | 0x01000101 + * v1.0.16 | 0x01000102 + * v1.0.17 | 0x01000102 + * v1.0.18 | 0x01000102 + * v1.0.19 | 0x01000103 + * v1.0.20 | 0x01000104 + * v1.0.21 | 0x01000105 + * v1.0.22 | 0x01000106 + * v1.0.23 | 0x01000107 */ #if defined (__FreeBSD__) diff --git a/src/stlink-lib/logging.c b/src/stlink-lib/logging.c index 817f3d68e..79924fc20 100644 --- a/src/stlink-lib/logging.c +++ b/src/stlink-lib/logging.c @@ -4,6 +4,7 @@ * Slow, yet another wheel reinvented, but enough to make the rest of our code * pretty enough. */ + #include #include #include diff --git a/src/stlink-lib/sg.c b/src/stlink-lib/sg.c index 18792c89f..feab40c13 100644 --- a/src/stlink-lib/sg.c +++ b/src/stlink-lib/sg.c @@ -74,7 +74,6 @@ * part to an existing options line for usb-storage). */ - #define __USE_GNU #include #include diff --git a/src/stlink-lib/sg.h b/src/stlink-lib/sg.h index 4161d3967..212d03b27 100644 --- a/src/stlink-lib/sg.h +++ b/src/stlink-lib/sg.h @@ -9,7 +9,6 @@ #include #include - /* Device access */ #define RDWR 0 #define RO 1 @@ -57,5 +56,4 @@ struct stlink_libsg { stlink_t* stlink_v1_open(const int verbose, int reset); - #endif // STLINK_SG_H diff --git a/src/stlink-lib/usb.h b/src/stlink-lib/usb.h index d04ef2dca..885e8cfc5 100644 --- a/src/stlink-lib/usb.h +++ b/src/stlink-lib/usb.h @@ -66,9 +66,9 @@ struct stlink_libusb { * @retval NULL Error while opening the stlink * @retval !NULL Stlink found and ready to use */ + stlink_t *stlink_open_usb(enum ugly_loglevel verbose, enum connect_type connect, char serial[STLINK_SERIAL_BUFFER_SIZE], int freq); size_t stlink_probe_usb(stlink_t **stdevs[], enum connect_type connect, int freq); void stlink_probe_usb_free(stlink_t **stdevs[], size_t size); - #endif // STLINK_USB_H diff --git a/src/win32/mmap.h b/src/win32/mmap.h index 67558b0cc..06079a9bc 100644 --- a/src/win32/mmap.h +++ b/src/win32/mmap.h @@ -13,11 +13,9 @@ #define MAP_ANONYMOUS (1 << 5) #define MAP_FAILED ((void *)-1) - void *mmap(void *addr, size_t len, int prot, int flags, int fd, long long offset); int munmap(void *addr, size_t len); - #endif /* HAVE_SYS_MMAN_H */ #endif /* STLINK_MMAP_H */ diff --git a/src/win32/sys_time.c b/src/win32/sys_time.c index 08da60b85..422731b3f 100644 --- a/src/win32/sys_time.c +++ b/src/win32/sys_time.c @@ -30,4 +30,5 @@ int gettimeofday(struct timeval *tv, struct timezone *tz) { return 0; } + #endif //STLINK_HAVE_SYS_TIME_H diff --git a/src/win32/sys_time.h b/src/win32/sys_time.h index 3f35390c3..d314509b7 100644 --- a/src/win32/sys_time.h +++ b/src/win32/sys_time.h @@ -14,7 +14,6 @@ struct timezone { int gettimeofday(struct timeval *tv, struct timezone *tz); - #endif /* STLINK_HAVE_SYS_TIME_H */ #endif /* STLINK_TIME_H */ diff --git a/src/win32/win32_socket.c b/src/win32/win32_socket.c index bfdcac5ce..3f4d28bbd 100644 --- a/src/win32/win32_socket.c +++ b/src/win32/win32_socket.c @@ -123,7 +123,8 @@ static void set_socket_errno(int winsock_err) { } } -/* A wrapper around the socket() function. +/* + * A wrapper around the socket() function. * The purpose of this wrapper is to ensure that the global errno symbol is set if an error occurs, * even if we are using winsock. */ @@ -135,7 +136,8 @@ SOCKET win32_socket(int domain, int type, int protocol) { return(fd); } -/* A wrapper around the connect() function. +/* + * A wrapper around the connect() function. * The purpose of this wrapper is to ensure that the global errno symbol is set if an error occurs, * even if we are using winsock. */ diff --git a/src/win32/win32_socket.h b/src/win32/win32_socket.h index 5f8f09589..614046a6f 100644 --- a/src/win32/win32_socket.h +++ b/src/win32/win32_socket.h @@ -20,7 +20,8 @@ #pragma warning(pop) #endif -/* winsock doesn't feature poll(), so there is a version implemented in terms of select() in win32_socket.c. +/* + * winsock doesn't feature poll(), so there is a version implemented in terms of select() in win32_socket.c. * The following definitions are copied from linux man pages. * A poll() macro is defined to call the version in win32_socket.c. */ @@ -40,7 +41,8 @@ struct pollfd { #endif #define poll(x, y, z) win32_poll(x, y, z) -/* These wrappers do nothing special except set the global errno variable if an error occurs +/* + * These wrappers do nothing special except set the global errno variable if an error occurs * (winsock doesn't do this by default). * They set errno to unix-like values (i.e. WSAEWOULDBLOCK is mapped to EAGAIN), * so code outside of this file "shouldn't" have to worry about winsock specific error handling. From 3f5d9bd0f616060f284aced40fbc8153ef0c0801 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 23 Jan 2022 13:13:57 +0100 Subject: [PATCH 363/503] Bugfixes and minor additions - Fixed wrong chip id for F42x_F43x boards. - Added support note for STM32 clones. - Minor formatting improvements. - Updated libusb API_VERSION list. --- config/chips/F42x_F43x.chip | 2 +- doc/devices_boards.md | 4 ++-- src/st-info/info.c | 8 +++----- src/stlink-lib/libusb_settings.h | 1 + src/stlink-lib/usb.h | 1 - 5 files changed, 7 insertions(+), 9 deletions(-) diff --git a/config/chips/F42x_F43x.chip b/config/chips/F42x_F43x.chip index 4452780b3..9dc81a120 100644 --- a/config/chips/F42x_F43x.chip +++ b/config/chips/F42x_F43x.chip @@ -2,7 +2,7 @@ # dev_type STM32F42x_F43x ref_manual_id 0090 // RM0090 (Rev. 2) -chip_id 0x463 // STM32_CHIPID_F4_HD +chip_id 0x419 // STM32_CHIPID_F4_HD flash_type F2_F4 flash_size_reg 0x1fff7a22 flash_pagesize 0x4000 // 16 KB diff --git a/doc/devices_boards.md b/doc/devices_boards.md index 63569881a..51b9a0739 100644 --- a/doc/devices_boards.md +++ b/doc/devices_boards.md @@ -51,7 +51,7 @@ Tested non-official ST boards [incl. STLINK programmers]: | ------- | ------------ | ------------- | | 0x411 | STM32F2yyxx | (all devices) | -## STM32F1 Clone / ARM Cortex M3 (Core-ID: 0x2ba01477) +## STM32F1 Clone / ARM Cortex M3 (Core-ID: 0x2ba01477) [may work, but without support!] | Product-Code | Chip-ID | STLink
Programmer | Boards | | ------------- | ------- | ---------------------- | ----------------------------------------------------------------------------------------------- | @@ -85,7 +85,7 @@ Tested non-official ST boards [incl. STLINK programmers]: | 0x446 | _N/A_ | xD xE | | F302 | F303 | | | 0x446 | _N/A_ | - | | | | F398 | -## STM32F3 Clone / ARM Cortex M4F (Core-ID: 0x2ba01477) +## STM32F3 Clone / ARM Cortex M4F (Core-ID: 0x2ba01477) [may work, but without support!] | Product-Code | Chip-ID | STLINK
Programmer | Boards | | ------------ | ------- | ---------------------- | ---------------------------------- | diff --git a/src/st-info/info.c b/src/st-info/info.c index 416d27f56..618046ddd 100644 --- a/src/st-info/info.c +++ b/src/st-info/info.c @@ -33,13 +33,11 @@ static void stlink_print_info(stlink_t *sl) { if (!sl) { return; } - printf(" version: "); - stlink_print_version(sl); + printf(" version: "); stlink_print_version(sl); printf(" serial: %s\n", sl->serial); - printf(" flash: %u (pagesize: %u)\n", - (uint32_t)sl->flash_size, (uint32_t)sl->flash_pgsz); + printf(" flash: %u (pagesize: %u)\n", (uint32_t)sl->flash_size, (uint32_t)sl->flash_pgsz); printf(" sram: %u\n", (uint32_t)sl->sram_size); - printf(" chipid: 0x%.4x\n", sl->chip_id); + printf(" chipid: 0x%.3x\n", sl->chip_id); params = stlink_chipid_get_params(sl->chip_id); if (params) { printf(" dev-type: %s\n", params->dev_type); } diff --git a/src/stlink-lib/libusb_settings.h b/src/stlink-lib/libusb_settings.h index cc44736f9..c7562e290 100644 --- a/src/stlink-lib/libusb_settings.h +++ b/src/stlink-lib/libusb_settings.h @@ -17,6 +17,7 @@ * v1.0.21 | 0x01000105 * v1.0.22 | 0x01000106 * v1.0.23 | 0x01000107 + * v1.0.24 | 0x01000108 */ #if defined (__FreeBSD__) diff --git a/src/stlink-lib/usb.h b/src/stlink-lib/usb.h index 885e8cfc5..3f4b71e51 100644 --- a/src/stlink-lib/usb.h +++ b/src/stlink-lib/usb.h @@ -12,7 +12,6 @@ #include #include "logging.h" - #define STLINK_USB_VID_ST 0x0483 #define STLINK_USB_PID_STLINK 0x3744 #define STLINK_USB_PID_STLINK_32L 0x3748 From f6cfd1bfe3eb50b90befe03293808727c66cb8bd Mon Sep 17 00:00:00 2001 From: hydroconstructor Date: Sun, 23 Jan 2022 23:22:05 +0400 Subject: [PATCH 364/503] user gszy comment Comment was: removing the MAX_FILE_SIZE ifdef/define/endif, replacing the st.st_size > (off_t)SSIZE_MAX test with st.st_size > (intmax_t) SIZE_MAX, perhaps removing the sizeof(st.st_size) != sizeof(size_t) test as well. done here --- src/common.c | 15 ++++----------- 1 file changed, 4 insertions(+), 11 deletions(-) diff --git a/src/common.c b/src/common.c index 32f718c02..d562f0f00 100644 --- a/src/common.c +++ b/src/common.c @@ -27,10 +27,6 @@ #define O_BINARY 0 #endif -#ifndef MAX_FILE_SIZE -#define MAX_FILE_SIZE (1<<20) // signed long int max value -#endif - #ifdef _MSC_VER #define __attribute__(x) #endif @@ -2202,15 +2198,12 @@ static int map_file(mapped_file_t *mf, const char *path) { goto on_error; } - if (sizeof(st.st_size) != sizeof(size_t)) { - // on 32 bit systems, check if there is an overflow - if (st.st_size > (off_t)MAX_FILE_SIZE /*1 GB*/ ) { - // limit file size to 1 GB - fprintf(stderr, "mmap() file %s too big\n", path); - goto on_error; - } + if (st.st_size > (intmax_t) SIZE_MAX ) { + fprintf(stderr, "mmap() file %s too big\n", path); + goto on_error; } + mf->base = (uint8_t *)mmap(NULL, (size_t)(st.st_size), PROT_READ, MAP_SHARED, fd, 0); From d0ed1253cea96e286d02470f0c2d90d5cb352465 Mon Sep 17 00:00:00 2001 From: hydroconstructor <96923701+hydroconstructor@users.noreply.github.com> Date: Sun, 23 Jan 2022 23:28:07 +0400 Subject: [PATCH 365/503] Update doc/man/st-util.1 Co-authored-by: Grzegorz Szymaszek --- doc/man/st-util.1 | 1 - 1 file changed, 1 deletion(-) diff --git a/doc/man/st-util.1 b/doc/man/st-util.1 index 2f718bb2b..bb2e36f5c 100644 --- a/doc/man/st-util.1 +++ b/doc/man/st-util.1 @@ -18,7 +18,6 @@ option, the default \f[B]4242\f[R] port will be used. .PP Stlink version 2 is used by default unless the option \f[B]\[en]stlinkv1\f[R] is given. -.PP .SH OPTIONS .TP .B \-h, \-\-help From 618a03a5dfe4a91d4174dba1b2bfcdcf75ae4d7d Mon Sep 17 00:00:00 2001 From: hydroconstructor Date: Sat, 29 Jan 2022 00:36:16 +0400 Subject: [PATCH 366/503] common c refactor Try to resolve conflicts with chipid_cleanup branch --- CHANGELOG.md | 18 +- CMakeLists.txt | 10 +- README.md | 2 +- cmake/modules/Findlibusb.cmake | 2 +- cmake/packaging/cpack_config.cmake | 2 +- cmake/packaging/deb/control | 2 +- contributors.txt | 3 - doc/compiling.md | 4 +- doc/version_support.md | 155 +- inc/stlink.h | 8 +- inc/stm32.h | 345 +- inc/stm32flash.h | 338 ++ src/calculate.c | 74 + src/calculate.h | 15 + src/common.c | 5380 ++++------------- src/common.h | 15 + src/common_flash.c | 1375 +++++ src/common_flash.h | 27 + src/flashloader.c | 482 ++ src/map_file.c | 62 + src/map_file.h | 32 + src/option.c | 1027 ++++ src/read_write.c | 143 + src/stlink-lib/chipid.h | 5 +- src/stlink-lib/usb.c | 41 +- src/stlink-lib/usb.c.bak | 1410 +++++ src/win32/unistd/unistd.h | 2 +- src/win32/unistd/unistd.h.bak | 76 + ...1\201\320\260\320\275\320\270\320\265.txt" | 129 + stlinkv1_macos_driver/install.sh | 3 + .../Contents/Info.plist | 82 + .../Contents/MacOS/stlink_shield_10_14 | Bin 0 -> 33840 bytes .../stlink_shield_10_14.kext/Contents/PkgInfo | 1 + .../Contents/_CodeSignature/CodeResources | 115 + .../stlink_shield.xcodeproj/project.pbxproj | 50 + 35 files changed, 6671 insertions(+), 4764 deletions(-) create mode 100644 inc/stm32flash.h create mode 100644 src/calculate.c create mode 100644 src/calculate.h create mode 100644 src/common.h create mode 100644 src/common_flash.c create mode 100644 src/common_flash.h create mode 100644 src/flashloader.c create mode 100644 src/map_file.c create mode 100644 src/map_file.h create mode 100644 src/option.c create mode 100644 src/read_write.c create mode 100644 src/stlink-lib/usb.c.bak create mode 100644 src/win32/unistd/unistd.h.bak create mode 100644 "src/\320\236\320\277\320\270\321\201\320\260\320\275\320\270\320\265.txt" create mode 100644 stlinkv1_macos_driver/stlink_shield_10_14.kext/Contents/Info.plist create mode 100644 stlinkv1_macos_driver/stlink_shield_10_14.kext/Contents/MacOS/stlink_shield_10_14 create mode 100644 stlinkv1_macos_driver/stlink_shield_10_14.kext/Contents/PkgInfo create mode 100644 stlinkv1_macos_driver/stlink_shield_10_14.kext/Contents/_CodeSignature/CodeResources diff --git a/CHANGELOG.md b/CHANGELOG.md index d744ff564..06f995d21 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -2,14 +2,10 @@ # v1.7.1 -Release date: 2022-xx-xx +Release date: 2021-xx-xx This release drops support for some older operating systems. Check project README for details. - -Updated system requirements: -- `cmake` >= 3.10.2 -- `libusb` >= 1.0.21 -- `libgtk-dev` >= 3.22.30 +Updated system requirements: Raised minimum version for `cmake` to 3.7.2. Features: @@ -19,9 +15,6 @@ Features: - Expanded and revised list of chips ([#1145](https://github.com/stlink-org/stlink/pull/1145), [#1164](https://github.com/stlink-org/stlink/pull/1164)) - [STM32H72X/3X]: Added full access to all device memory ([#1158](https://github.com/stlink-org/stlink/pull/1158), [#1159](https://github.com/stlink-org/stlink/pull/1159)) - Added support for STM32WLEx ([#1173](https://github.com/stlink-org/stlink/pull/1173)) -- Added support for STLINK-V3 devices with no MSD ([#1185](https://github.com/stlink-org/stlink/pull/1185)) -- Updated gdb-server.c to allow external memory access on STM32H73xx ([#1196](https://github.com/stlink-org/stlink/pull/1196), [#1197](https://github.com/stlink-org/stlink/pull/1197)) -- Erase addr size / section of the flash memory with st-flash ([#1213](https://github.com/stlink-org/stlink/pull/1213)) Updates & changes: @@ -29,12 +22,10 @@ Updates & changes: - Added instructions for bug-reports and feature-requests to contribution guidelines ([#906](https://github.com/stlink-org/stlink/pull/906)) - Added travis CI configuration for macOS 10.14 to maintain capability for 32-bit compilation ([#f5ada94](https://github.com/stlink-org/stlink/commit/f5ada9474cdb87ff37de0d4eb9e75622b5870646)) - Updated description of chip id 0x0457 to L01x/L02x ([#1143](https://github.com/stlink-org/stlink/pull/1143), [#1144](https://github.com/stlink-org/stlink/pull/1144)) -- Dropped execute bits from source code files ([#1167](https://github.com/stlink-org/stlink/pull/1167)) +- Drop execute bits from source code files ([#1167](https://github.com/stlink-org/stlink/pull/1167)) - Use proper Markdown headers for supported MCUs ([#1168](https://github.com/stlink-org/stlink/pull/1168)) - Removed redundant array ([#1178](https://github.com/stlink-org/stlink/pull/1178)) - Updated chip config files from the library structs ([#1181](https://github.com/stlink-org/stlink/pull/1181)) -- [doc] Corrected file path in tutorial ([#1186](https://github.com/stlink-org/stlink/pull/1186)) -- Improved chipid checks and printouts ([#1188](https://github.com/stlink-org/stlink/pull/1188)) Fixes: - cmake: Install shared libraries in proper directories ([#1142](https://github.com/stlink-org/stlink/pull/1142)) @@ -50,9 +41,6 @@ Fixes: - Fixed few warnings for msvc about type conversion with possible lost data ([#1179](https://github.com/stlink-org/stlink/pull/1179)) - st-flash and other utilities search for chip files in the wrong directory ([#1180](https://github.com/stlink-org/stlink/pull/1180), commit [#c8fc656](https://github.com/stlink-org/stlink/commit/c8fc6561fead79ad49c09d82bab864745086792c)) - Fixed broken build on 32 bit systems ([#985](https://github.com/stlink-org/stlink/pull/985), [#1175](https://github.com/stlink-org/stlink/pull/1175), commit [#c8fc656](https://github.com/stlink-org/stlink/commit/c8fc6561fead79ad49c09d82bab864745086792c)) -- Define 'SSIZE_MAX' if not defined ([#1183](https://github.com/stlink-org/stlink/pull/1183)) -- Fixed compliation for OpenBSD 7.0 ([#1202](https://github.com/stlink-org/stlink/pull/1202)) -- Included 'SSIZE_MAX' from 'limits.h' in 'src/common.c' ([#1207](https://github.com/stlink-org/stlink/pull/1207)) # v1.7.0 diff --git a/CMakeLists.txt b/CMakeLists.txt index 66bf34e3e..a3338df71 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -2,7 +2,7 @@ # General cmake settings ### -cmake_minimum_required(VERSION 3.10.2) +cmake_minimum_required(VERSION 3.7.2) cmake_policy(SET CMP0042 NEW) set(CMAKE_MODULE_PATH ${CMAKE_SOURCE_DIR}/cmake/modules) set(CMAKE_ARCHIVE_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}/lib) @@ -110,6 +110,8 @@ add_subdirectory(inc) set(STLINK_HEADERS inc/backend.h inc/stlink.h + src/common_flash.h + src/calculate.h src/stlink-lib/commands.h src/stlink-lib/libusb_settings.h src/stlink-lib/reg.h @@ -123,7 +125,13 @@ set(STLINK_HEADERS ) set(STLINK_SOURCE + src/read_write.c src/common.c + src/option.c + src/common_flash.c + src/map_file.c + src/flashloader.c + src/calculate.c src/stlink-lib/chipid.c src/stlink-lib/flash_loader.c src/stlink-lib/logging.c diff --git a/README.md b/README.md index bc491189e..7f797a7d9 100644 --- a/README.md +++ b/README.md @@ -38,7 +38,7 @@ It supports several so called STLINK programmer boards (and clones thereof) whic - stand-alone programmer (STLINK-V3SET, STLINK-V3MINI, STLINK-V3MODS) - on-board on some STM32 Nucleo boards (STLINK-V3E) -_\*)_ *Note: Support for the STLINK/V1 on macOS is limited to 10.15. Due to the deprecation and removal of macOS Kernel Extensions (KEXT) there will be no support for this programmer on macOS 11 or any later version.* +_\*)_ **Note: Support for the STLINK/V1 on macOS is limited to 10.14 - 10.15. Due to the deprecation and removal of macOS Kernel Extensions (KEXT) there will be no support for this programmer on macOS 11 or any later version.** On the user level there is no difference in handling or operation between these different revisions. diff --git a/cmake/modules/Findlibusb.cmake b/cmake/modules/Findlibusb.cmake index bc04f848d..cd52026f5 100644 --- a/cmake/modules/Findlibusb.cmake +++ b/cmake/modules/Findlibusb.cmake @@ -72,7 +72,7 @@ elseif (WIN32 OR (EXISTS "/etc/debian_version" AND MINGW)) # Windows or MinGW-to if (WIN32 AND NOT EXISTS "/etc/debian_version") # Skip this for Debian... # Preparations for installing libusb library - set(LIBUSB_WIN_VERSION 1.0.24) # set libusb version + set(LIBUSB_WIN_VERSION 1.0.23) # set libusb version set(LIBUSB_WIN_ARCHIVE libusb-${LIBUSB_WIN_VERSION}.7z) if (WIN32 AND NOT EXISTS "/etc/debian_version") # ... on native Windows systems set(LIBUSB_WIN_ARCHIVE_PATH ${CMAKE_BINARY_DIR}/${LIBUSB_WIN_ARCHIVE}) diff --git a/cmake/packaging/cpack_config.cmake b/cmake/packaging/cpack_config.cmake index 587ff5fb5..acd5630fa 100644 --- a/cmake/packaging/cpack_config.cmake +++ b/cmake/packaging/cpack_config.cmake @@ -53,7 +53,7 @@ elseif (EXISTS "/etc/debian_version" AND NOT EXISTS WIN32) # Package-build is av set(CPACK_DEBIAN_PACKAGE_RELEASE "1") # CPACK_DEBIAN_PACKAGE_ARCHITECTURE --> Default: Output of dpkg --print-architecture - set(CPACK_DEBIAN_PACKAGE_DEPENDS "pkg-config, build-essential, debhelper (>=9), cmake (>= 3.10.2), libusb-1.0-0-dev (>= 1.0.21)") + set(CPACK_DEBIAN_PACKAGE_DEPENDS "pkg-config, build-essential, debhelper (>=9), cmake (>= 3.4.2), libusb-1.0-0-dev (>= 1.0.20)") set(CPACK_DEBIAN_PACKAGE_MAINTAINER "Nightwalker-87 ") # CPACK_DEBIAN_PACKAGE_DESCRIPTION --> Default: CPACK_DEBIAN_PACKAGE_DESCRIPTION (as it is set) # CPACK_DEBIAN_PACKAGE_SECTION --> Default: “devel” diff --git a/cmake/packaging/deb/control b/cmake/packaging/deb/control index 7c8d13e47..ef51a6cea 100644 --- a/cmake/packaging/deb/control +++ b/cmake/packaging/deb/control @@ -1,7 +1,7 @@ Source: stlink Priority: optional Maintainer: Nightwalker-87 -Build-Depends: cmake (>= 3.10.2), dh-cmake, debhelper (>= 9), libusb-1.0-0-dev (>= 1.0.21), libgtk-3-dev (>= 3.22.30) +Build-Depends: cmake, dh-cmake, debhelper (>= 9), libusb-1.0-0-dev, libgtk-3-dev Standards-Version: 4.5.0 Rules-Requires-Root: no Section: electronics diff --git a/contributors.txt b/contributors.txt index cffef89f6..bcaa0b538 100644 --- a/contributors.txt +++ b/contributors.txt @@ -7,8 +7,6 @@ Andrea Mucignat Andrew Andrianov [necromant] Andrey Yurovsky Andy Isaacson -Andreas Sandberg [andysan] -Antoine Faure [antoinefaure] Anton [Ant-ON] Áron Radics A. Sheaff @@ -26,7 +24,6 @@ Chris Samuelson Christian Deussen [nullsub] Christophe Levantis Craig Lilley -Crest [Crest] Dan Dev Dan Hepler Daniel Campoverde [alx741] diff --git a/doc/compiling.md b/doc/compiling.md index 0931c278a..eef207f95 100644 --- a/doc/compiling.md +++ b/doc/compiling.md @@ -7,7 +7,7 @@ On Windows users should ensure that the following software is installed: - `git` (_optional, but recommended_) -- `cmake` +- `cmake` (3.17.0 or later) - `MinGW-w64` (7.0.0 or later) with GCC toolchain 8.1.0 ### Installation @@ -95,7 +95,7 @@ Install the following packages from your package repository: - `git` - `gcc` or `clang` or `mingw32-gcc` or `mingw64-gcc` (C-compiler; very likely gcc is already present) - `build-essential` (on Debian based distros (Debian, Ubuntu)) -- `cmake` +- `cmake` (3.4.2 or later, use the latest version available from the repository) - `rpm` (on Debian based distros (Debian, Ubuntu), needed for package build with `make package`) - `libusb-1.0` - `libusb-1.0-0-dev` (development headers for building) diff --git a/doc/version_support.md b/doc/version_support.md index d7ba5c102..2c5df7461 100644 --- a/doc/version_support.md +++ b/doc/version_support.md @@ -1,104 +1,97 @@ -_Source:_ [pkgs.org](https://pkgs.org/search) - libusb, cmake, gtk, libgtk) (as of Jan 2022) +_Source:_ pkgs.org - [libusb](https://pkgs.org/search/?q=libusb); [cmake](https://pkgs.org/search/?q=cmake); [gtk](https://pkgs.org/search/?q=gtk) (as of May 2021) ## Supported Operating Systems ### Microsoft Windows -On Windows users should ensure that cmake **3.10.2** or any later version is installed.
-Up on compiling c-make will **automatically** download and install the latest compatible version of `libusb`. +On Windows users should ensure that cmake 3.20.2 or any later version is installed.
+Up on compiling c-make will **automatically** download and install the latest compatible version of `libusb` (1.0.23 at the time of writing). - Windows 10 - Windows 8.1 ### Apple macOS -| Package Repository | libusb | cmake | gtk-3-dev | Supported macOS versions | -| ------------------ | ------ | ------ | ------------------ | ------------------------ | -| homebrew | 1.0.24 | 3.22.1 | 3.24.30
gtk+3 | **10.10 - 12.x** | -| MacPorts | 1.0.24 | 3.22.1 | 3.24.31
gtk3 | **10.4 - 12.x** | +| Package Repository | libusb
version | cmake
version | gtk-3
version | Supported macOS versions | +| ------------------ | ------------------- | ------------------ | ------------------ | ------------------------ | +| homebrew | 1.0.24 | 3.20.2 | 3.24.29
gtk+3 | 10.9 - 11.x | +| MacPorts | 1.0.24 | 3.20.2 | 3.24.29
gtk3 | 10.4 - 11.x | -NOTE: In order to use a STLINK/V1 programmer on macOS, version 10.15 is required. +NOTE: In order to use a STLINK/V1 programmer on macOS, versions 10.14 or 10.15 are required. ### Linux-/Unix-based: -| Operating System | libusb | cmake | libgtk-dev | Notes | -| ------------------------- | ------------------------------ | ---------- | ----------- | ------------------------ | -| Debian Sid | 1.0.24 | 3.22.1 | 3.24.31 | | -| Debian 11 (Bullseye) | 1.0.24 | 3.18.4 | 3.24.24 | | -| Debian 10 (Buster) | 1.0.**22** | **3.13.4** | 3.24.**5** | | -| | | | | | -| Ubuntu 20.04 LTS (Focal) | 1.0.23 | 3.16.3 | 3.24.**18** | | -| Ubuntu 18.04 LTS (Bionic) | 1.0.**21** | **3.10.2** | 3.**22.30** | End of Support: Apr 2023 | -| | | | | | -| Fedora Rawhide [x64] | 1.0.24 | 3.22.3 | 3.24.31 | | -| Fedora 35 [x64] | 1.0.24 | 3.21.3 | 3.24.30 | | -| Fedora 34 [x64] | 1.0.24 (`libusbx`) | 3.19.7 | 3.24.28 | | -| | | | | | -| openSUSE Tumbleweed [x64] | 1.0.24 | 3.22.1 | 3.24.31 | | -| openSUSE Leap 15.3 [x64] | 1.0.**21** | 3.17.0 | 3.24.20 | End of Support: Dec 2022 | -| | | | | | -| Alpine 3.15 | 1.0.24 | 3.21.3 | 3.24.30 | | -| Alpine 3.14 | 1.0.24 | 3.20.3 | 3.24.28 | | -| Alpine 3.13 | 1.0.24 | 3.18.4 | 3.24.23 | End of Support: Nov 2022 | -| Alpine 3.12 | 1.0.23 | 3.17.2 | 3.24.22 | End of Support: May 2022 | -| | | | | | -| FreeBSD 13.x | 1.0.**16-18** (API 0x01000102) | 3.22.1 | 3.24.31 | | -| FreeBSD 12.x | 1.0.**16-18** (API 0x01000102) | 3.22.1 | 3.24.31 | | -| | | | | | -| NetBSD 9.x | 1.0.24 | 3.21.2 | 3.24.30 | | -| NetBSD 8.x | 1.0.24 | 3.19.7 | 3.24.27 | | -| | | | | | -| CentOS 9 Stream [x64] | 1.0.24 (`libusbx`) | 3.20.3 | 3.24.30 | | -| CentOS 8 Stream [x64] | 1.0.23 (`libusbx`) | 3.20.2 | 3.**22.30** | | -| | | | | | -| ALT Linux Sisyphus | 1.0.24 | 3.22.1 | 3.24.31 | | -| ALT Linux P10 | 1.0.24 | 3.20.5 | 3.24.31 | | -| ALT Linux P9 | 1.0.**22** | 3.16.3 | 3.24.29 | | -| | | | | | -| OpenMandriva Rolling | 1.0.24 | 3.22.1 | 3.24.31 | | -| OpenMandriva Cooker | 1.0.24 | 3.22.1 | 3.24.31 | | -| OpenMandriva Lx 4.2 | 1.0.24 | 3.19.3 | 3.24.24 | | -| | | | | | -| Arch Linux | 1.0.24 | 3.22.1 | - | | -| KaOS [x64] | 1.0.24 | 3.22.1 | 3.24.31 | | -| Mageia Cauldron | 1.0.24 | 3.22.1 | 3.24.31 | | -| PCLinuxOS [x64] | ? | 3.22.1 | 3.24.31 | | -| Solus [x64] | 1.0.24 | 3.22.1 | 3.24.30 | | -| Void Linux | 1.0.24 | 3.22.1 | 3.24.31 | | -| Slackware Current | 1.0.24 | 3.21.4 | 3.24.31 | | -| AlmaLinux 8 | 1.0.23 (`libusbx`) | 3.20.2 | 3.**22.30** | | -| Rocky Linux 8 [x64] | 1.0.23 | 3.20.2 | 3.**22.30** | | -| Mageia 8 | 1.0.24 | 3.19.2 | 3.24.24 | End of Support: Aug 2022 | -| Adélie 1.0 | 1.0.23 | 3.16.4 | 3.24.23 | | +| Operating System | libusb | cmake | gtk-3 | Notes | +| ------------------------- | -------------------------------- | --------- | ----------- | ------------------------ | +| Debian Sid | 1.0.24 | 3.18.4 | 3.24.24 | | +| Debian 11 (Bullseye) | 1.0.24 | 3.18.4 | 3.24.24 | | +| Debian 10 (Buster) | 1.0.**22** | 3.13.4 | 3.24.**5** | | +| Debian 9 (Stretch) | 1.0.**21** | **3.7.2** | **3.22.11** | End of Support: Jun 2022 | +| | | | | | +| Ubuntu 21.04 (Hirsute) | 1.0.24 | 3.18.4 | 3.24.25 | End of Support: Jan 2022 | +| Ubuntu 20.04 LTS (Focal) | 1.0.23 | 3.16.3 | 3.24.**18** | | +| Ubuntu 18.04 LTS (Bionic) | 1.0.**21** | 3.10.2 | **3.22.30** | End of Support: Apr 2023 | +| | | | | | +| Fedora Rawhide [x64] | 1.0.24 (`libusbx`) | 3.20.2 | 3.24.29 | | +| Fedora 34 [x64] | 1.0.24 (`libusbx`) | 3.19.7 | 3.24.28 | | +| Fedora 33 [x64] | 1.0.23 (`libusbx`) | 3.18.3 | 3.24.23 | | +| | | | | | +| openSUSE Tumbleweed [x64] | 1.0.24 | 3.20.1 | 3.24.29 | | +| openSUSE Leap 15.3 [x64] | 1.0.**21** | 3.17.0 | 3.24.20 | | +| openSUSE Leap 15.2 [x64] | 1.0.**21** | 3.17.0 | 3.24.**14** | End of Support: Dec 2021 | +| | | | | | +| Alpine 3.14 | 1.0.24 | 3.20.3 | 4.2.1 | | +| Alpine 3.13 | 1.0.24 | 3.18.4 | 3.24.23 | End of Support: Nov 2022 | +| Alpine 3.12 | 1.0.23 | 3.17.2 | 3.24.22 | End of Support: May 2022 | +| Alpine 3.11 | 1.0.23 | 3.15.5 | 3.24.**13** | End of Support: Nov 2021 | +| | | | | | +| FreeBSD 13.x | 1.0.**16 - 18** (API 0x01000102) | 3.20.2 | 3.24.27 | | +| FreeBSD 12.x | 1.0.**16 - 18** (API 0x01000102) | 3.19.6 | 3.24.27 | | +| FreeBSD 11.x | 1.0.**16 - 18** (API 0x01000102) | 3.15.5 | 3.24.27 | End of Support: Sep 2021 | +| | | | | | +| Arch Linux | 1.0.24 | 3.20.2 | 3.24.29 | | +| KaOS [x64] | 1.0.24 | 3.20.2 | 3.24.29 | | +| Mageia Cauldron | 1.0.24 | 3.20.2 | 3.24.29 | | +| OpenMandriva Cooker | 1.0.24 | 3.20.2 | 3.24.29 | | +| PCLinuxOS [x64] | 1.0.24 | 3.20.2 | 3.24.29 | | +| Slackware Current | 1.0.24 | 3.20.2 | 3.24.28 | | +| Solus [x64] | 1.0.24 | 3.20.2 | 3.24.29 | | +| ALT Linux Sisyphus | 1.0.24 | 3.19.7 | 3.24.29 | | +| NetBSD 9.x | 1.0.24 | 3.19.7 | 3.24.27 | | +| NetBSD 8.x | 1.0.24 | 3.19.7 | 3.24.27 | | +| OpenMandriva Lx 4.2 | 1.0.24 | 3.19.3 | 3.24.24 | | +| Mageia 8 | 1.0.24 | 3.19.2 | 3.24.24 | End of Support: Aug 2022 | +| CentOS 8 Stream [x64] | 1.0.23 (`libusbx`) | 3.18.2 | **3.22.30** | | +| Adélie 1.0 | 1.0.23 | 3.16.4 | 3.24.23 | | +| ALT Linux P9 | 1.0.**22** | 3.16.3 | 3.24.**11** | | +| AlmaLinux 8 | 1.0.23 (`libusbx`) | 3.11.4 | 3.24.32 | | +| CentOS 8 [x64] | 1.0.23 (`libusbx`) | 3.11.4 | **3.22.30** | End of Support: Dec 2021 | ## Unsupported Operating Systems (as of Release v1.7.1) Systems with highlighted versions remain compatible with this toolset. -| Operating System | libusb | cmake | End of
OS-Support | -| ------------------------ | ------------------------------ | ---------- | ---------------------- | -| CentOS 8 [x64] | 1.0.**23** (`libusbx`) | 3.**20.3** | Dec 2021 | -| Ubuntu 21.04 (Hirsute) | 1.0.**24** | 3.**18.4** | Jan 2022 | -| Fedora 33 [x64] | 1.0.**23** (`libusbx`) | 3.**18.3** | Nov 2021 | -| Fedora 32 [x64] | 1.0.**23** (`libusbx`) | 3.**17.0** | May 2021 | -| openSUSE Leap 15.2 [x64] | 1.0.**21** | 3.**17.0** | Dec 2021 | -| Ubuntu 20.10 (Groovy) | 1.0.**23** | 3.**16.3** | Jul 2021 | -| NetBSD 7.x | 1.0.**22** | 3.**16.1** | Jun 2020 | -| Alpine 3.11 | 1.0.**23** | 3.**15.5** | Nov 2021 | -| FreeBSD 11.x | 1.0.**16-18** (API 0x01000102) | 3.**15.5** | Sep 2021 | -| Alpine 3.10 | 1.0.**22** | 3.**14.5** | May 2021 | -| Fedora 31 [x64] | 1.0.**22**(`libusbx`) | 3.**14.5** | Nov 2020 | -| Mageia 7.1 | 1.0.**22** | 3.**14.3** | Jun 2021 | -| Fedora 30 | 1.0.**22**(`libusbx`) | 3.**14.2** | May 2020 | -| Ubuntu 19.10 (Eoan) | 1.0.**23** | 3.**13.4** | Jul 2020 | -| Alpine 3.9 | 1.0.**22** | 3.**13.0** | Jan 2021 | -| openSUSE Leap 15.1 [x64] | 1.0.**21** | 3.**10.2** | Jan 2021 | -| Debian 9 (Stretch) | 1.0.**21** | 3.7.2 | Jun 2022 | -| Slackware 14.2 | 1.0.20 | 3.5.2 | | -| OpenMandriva Lx 3.0x | 1.0.20 | 3.4.2 | | -| CentOS 7 [x64] | 1.0.**21** (`libusbx`) | 2.8.12.2 | Jun 2024 | -| Slackware 14.1 | 1.0.9 | 2.8.12 | | -| Slackware 14.0 | 1.0.9 | 2.8.8 | | +| Operating System | libusb | cmake | End of
OS-Support | +| ------------------------- | ---------------------- | ---------- | ---------------------- | +| Fedora 32 [x64] | **1.0.23** (`libusbx`) | **3.17.0** | May 2021 | +| Ubuntu 20.10 (Groovy) | **1.0.23** | **3.16.3** | Jul 2021 | +| NetBSD 7.x | **1.0.22** | **3.16.1** | Jun 2020 | +| Alpine 3.10 | **1.0.22** | **3.14.5** | May 2021 | +| Fedora 31 [x64] | **1.0.22** (`libusbx`) | **3.14.5** | Nov 2020 | +| Mageia 7.1 | **1.0.22** | **3.14.3** | Jun 2021 | +| Fedora 30 | **1.0.22** (`libusbx`) | **3.14.2** | May 2020 | +| Ubuntu 19.10 (Eoan) | **1.0.23** | **3.13.4** | Jul 2020 | +| Alpine 3.9 | **1.0.22** | **3.13.0** | Jan 2021 | +| openSUSE Leap 15.1 [x64] | **1.0.21** | **3.10.2** | Jan 2021 | +| Slackware 14.2 | 1.0.20 | 3.5.2 | | +| Ubuntu 16.04 LTS (Xenial) | 1.0.20 | 3.5.1 | Apr 2021 | +| OpenMandriva Lx 3.0x | 1.0.20 | 3.4.2 | | +| Debian 8 (Jessie) | 1.0.19 | 3.0.2 | Jun 2020 | +| CentOS 7 [x64] | 1.0.21 (`libusbx`) | 2.8.12.2 | Jun 2024 | +| Ubuntu 14.04 LTS (Trusty) | 1.0.17 | 2.8.12.2 | Apr 2019 | +| CentOS 6 | 1.0.9 (`libusbx`) | 2.8.12.2 | Nov 2020 | +| Slackware 14.1 | 1.0.9 | 2.8.12 | | +| Slackware 14.0 | 1.0.9 | 2.8.8 | | _All other operating systems which are not listed are unsupported._ diff --git a/inc/stlink.h b/inc/stlink.h index 2d0fa5007..e3fd632f2 100644 --- a/inc/stlink.h +++ b/inc/stlink.h @@ -1,6 +1,5 @@ /* * File: stlink.h - * * This should contain all the common top level stlink interfaces, * regardless of how the backend does the work.... */ @@ -13,6 +12,7 @@ #include #include "stm32.h" +#include "stm32flash.h" #ifdef __cplusplus extern "C" { @@ -183,7 +183,7 @@ enum run_type { typedef struct _stlink stlink_t; -#include +#include // Is it really need? #include struct _stlink { @@ -274,7 +274,7 @@ int stlink_mwrite_sram(stlink_t *sl, uint8_t* data, uint32_t length, stm32_addr_ int stlink_fwrite_sram(stlink_t *sl, const char* path, stm32_addr_t addr); int stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, uint32_t length); -int stlink_chip_id(stlink_t *sl, uint32_t *chip_id); +//int stlink_chip_id(stlink_t *sl, uint32_t *chip_id); int stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid); int stlink_erase_flash_page(stlink_t* sl, stm32_addr_t flashaddr); @@ -282,7 +282,7 @@ uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr); int stlink_check_address_range_validity(stlink_t *sl, stm32_addr_t addr, size_t size); int stlink_check_address_alignment(stlink_t *sl, stm32_addr_t addr); uint16_t read_uint16(const unsigned char *c, const int pt); -void stlink_core_stat(stlink_t *sl); +//void stlink_core_stat(stlink_t *sl); void stlink_print_data(stlink_t *sl); unsigned int is_bigendian(void); uint32_t read_uint32(const unsigned char *c, const int pt); diff --git a/inc/stm32.h b/inc/stm32.h index d6bbe506c..19ba3fca0 100644 --- a/inc/stm32.h +++ b/inc/stm32.h @@ -149,345 +149,11 @@ enum stm32_chipids { /* ============ */ /* Constant STM32 memory address */ -#define STM32_SRAM_BASE ((uint32_t)0x20000000) -#define STM32_FLASH_BASE ((uint32_t)0x08000000) +#define STM32_SRAM_BASE ((uint32_t)0x20000000) +#define STM32_FLASH_BASE ((uint32_t)0x08000000) -#define STM32_F1_FLASH_BANK2_BASE ((uint32_t)0x08080000) -#define STM32_H7_FLASH_BANK2_BASE ((uint32_t)0x08100000) - -/* stm32f FPEC flash controller interface, pm0063 manual */ -// STM32F05x is identical, based on RM0091 (DM00031936, Doc ID 018940 Rev 2, August 2012) -#define FLASH_REGS_ADDR 0x40022000 -#define FLASH_REGS_SIZE 0x28 - -#define FLASH_ACR (FLASH_REGS_ADDR + 0x00) -#define FLASH_KEYR (FLASH_REGS_ADDR + 0x04) -#define FLASH_OPTKEYR (FLASH_REGS_ADDR + 0x08) -#define FLASH_SR (FLASH_REGS_ADDR + 0x0c) -#define FLASH_CR (FLASH_REGS_ADDR + 0x10) -#define FLASH_AR (FLASH_REGS_ADDR + 0x14) -#define FLASH_OBR (FLASH_REGS_ADDR + 0x1c) -#define FLASH_WRPR (FLASH_REGS_ADDR + 0x20) - -// STM32F10x_XL has two flash memory banks with separate registers to control -// the second bank. -#define FLASH_KEYR2 (FLASH_REGS_ADDR + 0x44) -#define FLASH_SR2 (FLASH_REGS_ADDR + 0x4c) -#define FLASH_CR2 (FLASH_REGS_ADDR + 0x50) -#define FLASH_AR2 (FLASH_REGS_ADDR + 0x54) - -// For STM32F05x, the RDPTR_KEY may be wrong, but as it is not used anywhere... -#define FLASH_RDPTR_KEY 0x00a5 -#define FLASH_KEY1 0x45670123 -#define FLASH_KEY2 0xcdef89ab - -#define FLASH_L0_PRGKEY1 0x8c9daebf -#define FLASH_L0_PRGKEY2 0x13141516 - -#define FLASH_L0_PEKEY1 0x89abcdef -#define FLASH_L0_PEKEY2 0x02030405 - -#define FLASH_OPTKEY1 0x08192A3B -#define FLASH_OPTKEY2 0x4C5D6E7F - -#define FLASH_F0_OPTKEY1 0x45670123 -#define FLASH_F0_OPTKEY2 0xCDEF89AB - -#define FLASH_L0_OPTKEY1 0xFBEAD9C8 -#define FLASH_L0_OPTKEY2 0x24252627 - -#define FLASH_SR_BSY 0 -#define FLASH_SR_PG_ERR 2 -#define FLASH_SR_WRPRT_ERR 4 -#define FLASH_SR_EOP 5 - -#define FLASH_SR_ERROR_MASK ((1 << FLASH_SR_PG_ERR) | (1 << FLASH_SR_WRPRT_ERR)) - -#define FLASH_CR_PG 0 -#define FLASH_CR_PER 1 -#define FLASH_CR_MER 2 -#define FLASH_CR_OPTPG 4 -#define FLASH_CR_OPTER 5 -#define FLASH_CR_STRT 6 -#define FLASH_CR_LOCK 7 -#define FLASH_CR_OPTWRE 9 -#define FLASH_CR_OBL_LAUNCH 13 - -#define STM32L_FLASH_REGS_ADDR ((uint32_t)0x40023c00) -#define STM32L_FLASH_ACR (STM32L_FLASH_REGS_ADDR + 0x00) -#define STM32L_FLASH_PECR (STM32L_FLASH_REGS_ADDR + 0x04) -#define STM32L_FLASH_PDKEYR (STM32L_FLASH_REGS_ADDR + 0x08) -#define STM32L_FLASH_PEKEYR (STM32L_FLASH_REGS_ADDR + 0x0c) -#define STM32L_FLASH_PRGKEYR (STM32L_FLASH_REGS_ADDR + 0x10) -#define STM32L_FLASH_OPTKEYR (STM32L_FLASH_REGS_ADDR + 0x14) -#define STM32L_FLASH_SR (STM32L_FLASH_REGS_ADDR + 0x18) -#define STM32L_FLASH_OBR (STM32L_FLASH_REGS_ADDR + 0x1c) -#define STM32L_FLASH_WRPR (STM32L_FLASH_REGS_ADDR + 0x20) -#define FLASH_L1_FPRG 10 -#define FLASH_L1_PROG 3 - -// Flash registers common to STM32G0 and STM32G4 series. -#define STM32Gx_FLASH_REGS_ADDR ((uint32_t)0x40022000) -#define STM32Gx_FLASH_ACR (STM32Gx_FLASH_REGS_ADDR + 0x00) -#define STM32Gx_FLASH_KEYR (STM32Gx_FLASH_REGS_ADDR + 0x08) -#define STM32Gx_FLASH_OPTKEYR (STM32Gx_FLASH_REGS_ADDR + 0x0c) -#define STM32Gx_FLASH_SR (STM32Gx_FLASH_REGS_ADDR + 0x10) -#define STM32Gx_FLASH_CR (STM32Gx_FLASH_REGS_ADDR + 0x14) -#define STM32Gx_FLASH_ECCR (STM32Gx_FLASH_REGS_ADDR + 0x18) -#define STM32Gx_FLASH_OPTR (STM32Gx_FLASH_REGS_ADDR + 0x20) - -// G0 (RM0444 Table 1, sec 3.7) -// Mostly the same as G4 chips, but the notation -// varies a bit after the 'OPTR' register. -#define STM32G0_FLASH_REGS_ADDR (STM32Gx_FLASH_REGS_ADDR) -#define STM32G0_FLASH_PCROP1ASR (STM32G0_FLASH_REGS_ADDR + 0x24) -#define STM32G0_FLASH_PCROP1AER (STM32G0_FLASH_REGS_ADDR + 0x28) -#define STM32G0_FLASH_WRP1AR (STM32G0_FLASH_REGS_ADDR + 0x2C) -#define STM32G0_FLASH_WRP1BR (STM32G0_FLASH_REGS_ADDR + 0x30) -#define STM32G0_FLASH_PCROP1BSR (STM32G0_FLASH_REGS_ADDR + 0x34) -#define STM32G0_FLASH_PCROP1BER (STM32G0_FLASH_REGS_ADDR + 0x38) -#define STM32G0_FLASH_SECR (STM32G0_FLASH_REGS_ADDR + 0x80) - -// G4 (RM0440 Table 17, sec 3.7.19) -// Mostly the same as STM32G0 chips, but there are a few extra -// registers because 'cat 3' devices can have two Flash banks. -#define STM32G4_FLASH_REGS_ADDR (STM32Gx_FLASH_REGS_ADDR) -#define STM32G4_FLASH_PDKEYR (STM32G4_FLASH_REGS_ADDR + 0x04) -#define STM32G4_FLASH_PCROP1SR (STM32G4_FLASH_REGS_ADDR + 0x24) -#define STM32G4_FLASH_PCROP1ER (STM32G4_FLASH_REGS_ADDR + 0x28) -#define STM32G4_FLASH_WRP1AR (STM32G4_FLASH_REGS_ADDR + 0x2C) -#define STM32G4_FLASH_WRP1BR (STM32G4_FLASH_REGS_ADDR + 0x30) -#define STM32G4_FLASH_PCROP2SR (STM32G4_FLASH_REGS_ADDR + 0x44) -#define STM32G4_FLASH_PCROP2ER (STM32G4_FLASH_REGS_ADDR + 0x48) -#define STM32G4_FLASH_WRP2AR (STM32G4_FLASH_REGS_ADDR + 0x4C) -#define STM32G4_FLASH_WRP2BR (STM32G4_FLASH_REGS_ADDR + 0x50) -#define STM32G4_FLASH_SEC1R (STM32G4_FLASH_REGS_ADDR + 0x70) -#define STM32G4_FLASH_SEC2R (STM32G4_FLASH_REGS_ADDR + 0x74) - -// G0/G4 FLASH control register -#define STM32Gx_FLASH_CR_PG (0) /* Program */ -#define STM32Gx_FLASH_CR_PER (1) /* Page erase */ -#define STM32Gx_FLASH_CR_MER1 (2) /* Mass erase */ -#define STM32Gx_FLASH_CR_PNB (3) /* Page number */ -#define STM32G0_FLASH_CR_PNG_LEN (5) /* STM32G0: 5 page number bits */ -#define STM32G4_FLASH_CR_PNG_LEN (7) /* STM32G4: 7 page number bits */ -#define STM32Gx_FLASH_CR_MER2 (15) /* Mass erase (2nd bank)*/ -#define STM32Gx_FLASH_CR_STRT (16) /* Start */ -#define STM32Gx_FLASH_CR_OPTSTRT \ - (17) /* Start of modification of option bytes */ -#define STM32Gx_FLASH_CR_FSTPG (18) /* Fast programming */ -#define STM32Gx_FLASH_CR_EOPIE (24) /* End of operation interrupt enable */ -#define STM32Gx_FLASH_CR_ERRIE (25) /* Error interrupt enable */ -#define STM32Gx_FLASH_CR_OBL_LAUNCH (27) /* Forces the option byte loading */ -#define STM32Gx_FLASH_CR_OPTLOCK (30) /* Options Lock */ -#define STM32Gx_FLASH_CR_LOCK (31) /* FLASH_CR Lock */ - -// G0/G4 FLASH status register -#define STM32Gx_FLASH_SR_ERROR_MASK (0x3fa) -#define STM32Gx_FLASH_SR_PROGERR (3) -#define STM32Gx_FLASH_SR_WRPERR (4) -#define STM32Gx_FLASH_SR_PGAERR (5) -#define STM32Gx_FLASH_SR_BSY (16) /* FLASH_SR Busy */ -#define STM32Gx_FLASH_SR_EOP (0) /* FLASH_EOP End of Operation */ - -// G4 FLASH option register -#define STM32G4_FLASH_OPTR_DBANK (22) /* FLASH_OPTR Dual Bank Mode */ - -// WB (RM0434) -#define STM32WB_FLASH_REGS_ADDR ((uint32_t)0x58004000) -#define STM32WB_FLASH_ACR (STM32WB_FLASH_REGS_ADDR + 0x00) -#define STM32WB_FLASH_KEYR (STM32WB_FLASH_REGS_ADDR + 0x08) -#define STM32WB_FLASH_OPT_KEYR (STM32WB_FLASH_REGS_ADDR + 0x0C) -#define STM32WB_FLASH_SR (STM32WB_FLASH_REGS_ADDR + 0x10) -#define STM32WB_FLASH_CR (STM32WB_FLASH_REGS_ADDR + 0x14) -#define STM32WB_FLASH_ECCR (STM32WB_FLASH_REGS_ADDR + 0x18) -#define STM32WB_FLASH_OPTR (STM32WB_FLASH_REGS_ADDR + 0x20) -#define STM32WB_FLASH_PCROP1ASR (STM32WB_FLASH_REGS_ADDR + 0x24) -#define STM32WB_FLASH_PCROP1AER (STM32WB_FLASH_REGS_ADDR + 0x28) -#define STM32WB_FLASH_WRP1AR (STM32WB_FLASH_REGS_ADDR + 0x2C) -#define STM32WB_FLASH_WRP1BR (STM32WB_FLASH_REGS_ADDR + 0x30) -#define STM32WB_FLASH_PCROP1BSR (STM32WB_FLASH_REGS_ADDR + 0x34) -#define STM32WB_FLASH_PCROP1BER (STM32WB_FLASH_REGS_ADDR + 0x38) -#define STM32WB_FLASH_IPCCBR (STM32WB_FLASH_REGS_ADDR + 0x3C) -#define STM32WB_FLASH_C2ACR (STM32WB_FLASH_REGS_ADDR + 0x5C) -#define STM32WB_FLASH_C2SR (STM32WB_FLASH_REGS_ADDR + 0x60) -#define STM32WB_FLASH_C2CR (STM32WB_FLASH_REGS_ADDR + 0x64) -#define STM32WB_FLASH_SFR (STM32WB_FLASH_REGS_ADDR + 0x80) -#define STM32WB_FLASH_SRRVR (STM32WB_FLASH_REGS_ADDR + 0x84) - -// WB Flash control register. -#define STM32WB_FLASH_CR_STRT (16) /* Start */ -#define STM32WB_FLASH_CR_OPTLOCK (30) /* Option Lock */ -#define STM32WB_FLASH_CR_LOCK (31) /* Lock */ -// WB Flash status register. -#define STM32WB_FLASH_SR_ERROR_MASK (0x3f8) /* SR [9:3] */ -#define STM32WB_FLASH_SR_PROGERR (3) /* Programming alignment error */ -#define STM32WB_FLASH_SR_WRPERR (4) /* Write protection error */ -#define STM32WB_FLASH_SR_PGAERR (5) /* Programming error */ -#define STM32WB_FLASH_SR_BSY (16) /* Busy */ - -// 32L4 register base is at FLASH_REGS_ADDR (0x40022000) -#define STM32L4_FLASH_KEYR (FLASH_REGS_ADDR + 0x08) -#define STM32L4_FLASH_OPTKEYR (FLASH_REGS_ADDR + 0x0C) -#define STM32L4_FLASH_SR (FLASH_REGS_ADDR + 0x10) -#define STM32L4_FLASH_CR (FLASH_REGS_ADDR + 0x14) -#define STM32L4_FLASH_OPTR (FLASH_REGS_ADDR + 0x20) - -#define STM32L4_FLASH_SR_ERROR_MASK 0x3f8 /* SR [9:3] */ -#define STM32L4_FLASH_SR_PROGERR 3 -#define STM32L4_FLASH_SR_WRPERR 4 -#define STM32L4_FLASH_SR_PGAERR 5 -#define STM32L4_FLASH_SR_BSY 16 - -#define STM32L4_FLASH_CR_LOCK 31 /* Lock control register */ -#define STM32L4_FLASH_CR_OPTLOCK 30 /* Lock option bytes */ -#define STM32L4_FLASH_CR_PG 0 /* Program */ -#define STM32L4_FLASH_CR_PER 1 /* Page erase */ -#define STM32L4_FLASH_CR_MER1 2 /* Bank 1 erase */ -#define STM32L4_FLASH_CR_MER2 15 /* Bank 2 erase */ -#define STM32L4_FLASH_CR_STRT 16 /* Start command */ -#define STM32L4_FLASH_CR_OPTSTRT 17 /* Start writing option bytes */ -#define STM32L4_FLASH_CR_BKER 11 /* Bank select for page erase */ -#define STM32L4_FLASH_CR_PNB 3 /* Page number (8 bits) */ -#define STM32L4_FLASH_CR_OBL_LAUNCH 27 /* Option bytes reload */ -// Bits requesting flash operations (useful when we want to clear them) -#define STM32L4_FLASH_CR_OPBITS \ - (uint32_t)((1lu << STM32L4_FLASH_CR_PG) | (1lu << STM32L4_FLASH_CR_PER) | \ - (1lu << STM32L4_FLASH_CR_MER1) | (1lu << STM32L4_FLASH_CR_MER1)) -// Page is fully specified by BKER and PNB -#define STM32L4_FLASH_CR_PAGEMASK (uint32_t)(0x1fflu << STM32L4_FLASH_CR_PNB) - -#define STM32L4_FLASH_OPTR_DUALBANK 21 - -// STM32L0x flash register base and offsets RM0090 - DM00031020.pdf -#define STM32L0_FLASH_REGS_ADDR ((uint32_t)0x40022000) - -#define STM32L0_FLASH_PELOCK (0) -#define STM32L0_FLASH_OPTLOCK (2) -#define STM32L0_FLASH_OBL_LAUNCH (18) - -#define STM32L0_FLASH_SR_ERROR_MASK 0x00013F00 -#define STM32L0_FLASH_SR_WRPERR 8 -#define STM32L0_FLASH_SR_PGAERR 9 -#define STM32L0_FLASH_SR_NOTZEROERR 16 - -#define FLASH_ACR_OFF ((uint32_t)0x00) -#define FLASH_PECR_OFF ((uint32_t)0x04) -#define FLASH_PDKEYR_OFF ((uint32_t)0x08) -#define FLASH_PEKEYR_OFF ((uint32_t)0x0c) -#define FLASH_PRGKEYR_OFF ((uint32_t)0x10) -#define FLASH_OPTKEYR_OFF ((uint32_t)0x14) -#define FLASH_SR_OFF ((uint32_t)0x18) -#define FLASH_OBR_OFF ((uint32_t)0x1c) -#define FLASH_WRPR_OFF ((uint32_t)0x20) - -// STM32F7 -#define FLASH_F7_REGS_ADDR ((uint32_t)0x40023c00) -#define FLASH_F7_KEYR (FLASH_F7_REGS_ADDR + 0x04) -#define FLASH_F7_OPT_KEYR (FLASH_F7_REGS_ADDR + 0x08) -#define FLASH_F7_SR (FLASH_F7_REGS_ADDR + 0x0c) -#define FLASH_F7_CR (FLASH_F7_REGS_ADDR + 0x10) -#define FLASH_F7_OPTCR (FLASH_F7_REGS_ADDR + 0x14) -#define FLASH_F7_OPTCR1 (FLASH_F7_REGS_ADDR + 0x18) -#define FLASH_F7_OPTCR_LOCK 0 -#define FLASH_F7_OPTCR_START 1 -#define FLASH_F7_CR_STRT 16 -#define FLASH_F7_CR_LOCK 31 -#define FLASH_F7_CR_SER 1 -#define FLASH_F7_CR_SNB 3 -#define FLASH_F7_CR_SNB_MASK 0xf8 -#define FLASH_F7_SR_BSY 16 -#define FLASH_F7_SR_ERS_ERR 7 /* Erase Sequence Error */ -#define FLASH_F7_SR_PGP_ERR 6 /* Programming parallelism error */ -#define FLASH_F7_SR_PGA_ERR 5 /* Programming alignment error */ -#define FLASH_F7_SR_WRP_ERR 4 /* Write protection error */ -#define FLASH_F7_SR_OP_ERR 1 /* Operation error */ -#define FLASH_F7_SR_EOP 0 /* End of operation */ -#define FLASH_F7_OPTCR1_BOOT_ADD0 0 -#define FLASH_F7_OPTCR1_BOOT_ADD1 16 - -#define FLASH_F7_SR_ERROR_MASK \ - ((1 << FLASH_F7_SR_ERS_ERR) | (1 << FLASH_F7_SR_PGP_ERR) | \ - (1 << FLASH_F7_SR_PGA_ERR) | (1 << FLASH_F7_SR_WRP_ERR) | \ - (1 << FLASH_F7_SR_OP_ERR)) - -// STM32F4 -#define FLASH_F4_REGS_ADDR ((uint32_t)0x40023c00) -#define FLASH_F4_KEYR (FLASH_F4_REGS_ADDR + 0x04) -#define FLASH_F4_OPT_KEYR (FLASH_F4_REGS_ADDR + 0x08) -#define FLASH_F4_SR (FLASH_F4_REGS_ADDR + 0x0c) -#define FLASH_F4_CR (FLASH_F4_REGS_ADDR + 0x10) -#define FLASH_F4_OPTCR (FLASH_F4_REGS_ADDR + 0x14) -#define FLASH_F4_OPTCR_LOCK 0 -#define FLASH_F4_OPTCR_START 1 -#define FLASH_F4_CR_STRT 16 -#define FLASH_F4_CR_LOCK 31 -#define FLASH_F4_CR_SER 1 -#define FLASH_F4_CR_SNB 3 -#define FLASH_F4_CR_SNB_MASK 0xf8 -#define FLASH_F4_SR_ERROR_MASK 0x000000F0 -#define FLASH_F4_SR_PGAERR 5 -#define FLASH_F4_SR_WRPERR 4 -#define FLASH_F4_SR_BSY 16 - -// STM32F2 -#define FLASH_F2_REGS_ADDR ((uint32_t)0x40023c00) -#define FLASH_F2_KEYR (FLASH_F2_REGS_ADDR + 0x04) -#define FLASH_F2_OPT_KEYR (FLASH_F2_REGS_ADDR + 0x08) -#define FLASH_F2_SR (FLASH_F2_REGS_ADDR + 0x0c) -#define FLASH_F2_CR (FLASH_F2_REGS_ADDR + 0x10) -#define FLASH_F2_OPT_CR (FLASH_F2_REGS_ADDR + 0x14) -#define FLASH_F2_OPT_LOCK_BIT (1u << 0) -#define FLASH_F2_CR_STRT 16 -#define FLASH_F2_CR_LOCK 31 - -#define FLASH_F2_CR_SER 1 -#define FLASH_F2_CR_SNB 3 -#define FLASH_F2_CR_SNB_MASK 0x78 -#define FLASH_F2_SR_BSY 16 - -// STM32H7xx -#define FLASH_H7_CR_LOCK 0 -#define FLASH_H7_CR_PG 1 -#define FLASH_H7_CR_SER 2 -#define FLASH_H7_CR_BER 3 -#define FLASH_H7_CR_PSIZE 4 -#define FLASH_H7_CR_START(chipid) (chipid == STM32_CHIPID_H7Ax ? 5 : 7) -#define FLASH_H7_CR_SNB 8 -#define FLASH_H7_CR_SNB_MASK 0x700 - -#define FLASH_H7_SR_QW 2 -#define FLASH_H7_SR_WRPERR 17 -#define FLASH_H7_SR_PGSERR 18 -#define FLASH_H7_SR_STRBERR 19 -#define FLASH_H7_SR_ERROR_MASK \ - ((1 << FLASH_H7_SR_PGSERR) | (1 << FLASH_H7_SR_STRBERR) | \ - (1 << FLASH_H7_SR_WRPERR)) - -#define FLASH_H7_OPTCR_OPTLOCK 0 -#define FLASH_H7_OPTCR_OPTSTART 1 -#define FLASH_H7_OPTCR_MER 4 - -#define FLASH_H7_OPTSR_OPT_BUSY 0 -#define FLASH_H7_OPTSR_OPTCHANGEERR 30 - -#define FLASH_H7_OPTCCR_CLR_OPTCHANGEERR 30 - -#define FLASH_H7_REGS_ADDR ((uint32_t)0x52002000) -#define FLASH_H7_KEYR1 (FLASH_H7_REGS_ADDR + 0x04) -#define FLASH_H7_KEYR2 (FLASH_H7_REGS_ADDR + 0x104) -#define FLASH_H7_OPT_KEYR (FLASH_H7_REGS_ADDR + 0x08) -#define FLASH_H7_OPT_KEYR2 (FLASH_H7_REGS_ADDR + 0x108) -#define FLASH_H7_CR1 (FLASH_H7_REGS_ADDR + 0x0c) -#define FLASH_H7_CR2 (FLASH_H7_REGS_ADDR + 0x10c) -#define FLASH_H7_SR1 (FLASH_H7_REGS_ADDR + 0x10) -#define FLASH_H7_SR2 (FLASH_H7_REGS_ADDR + 0x110) -#define FLASH_H7_CCR1 (FLASH_H7_REGS_ADDR + 0x14) -#define FLASH_H7_CCR2 (FLASH_H7_REGS_ADDR + 0x114) -#define FLASH_H7_OPTCR (FLASH_H7_REGS_ADDR + 0x18) -#define FLASH_H7_OPTCR2 (FLASH_H7_REGS_ADDR + 0x118) -#define FLASH_H7_OPTSR_CUR (FLASH_H7_REGS_ADDR + 0x1c) -#define FLASH_H7_OPTCCR (FLASH_H7_REGS_ADDR + 0x24) +#define STM32_F1_FLASH_BANK2_BASE ((uint32_t)0x08080000) +#define STM32_H7_FLASH_BANK2_BASE ((uint32_t)0x08100000) #define STM32F0_DBGMCU_CR 0xE0042004 #define STM32F0_DBGMCU_CR_IWDG_STOP 8 @@ -529,7 +195,4 @@ enum stm32_chipids { #define STM32WB_RCC_AHB1ENR 0x58000048 #define STM32WB_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN -#define L1_WRITE_BLOCK_SIZE 0x80 -#define L0_WRITE_BLOCK_SIZE 0x40 - #endif // STM32_H diff --git a/inc/stm32flash.h b/inc/stm32flash.h new file mode 100644 index 000000000..c28d67c28 --- /dev/null +++ b/inc/stm32flash.h @@ -0,0 +1,338 @@ +#ifndef STM32FLASH_H +#define STM32FLASH_H + +/* stm32f FPEC flash controller interface, pm0063 manual */ +// STM32F05x is identical, based on RM0091 (DM00031936, Doc ID 018940 Rev 2, August 2012) +#define FLASH_REGS_ADDR 0x40022000 +#define FLASH_REGS_SIZE 0x28 + +#define FLASH_ACR (FLASH_REGS_ADDR + 0x00) +#define FLASH_KEYR (FLASH_REGS_ADDR + 0x04) +#define FLASH_OPTKEYR (FLASH_REGS_ADDR + 0x08) +#define FLASH_SR (FLASH_REGS_ADDR + 0x0c) +#define FLASH_CR (FLASH_REGS_ADDR + 0x10) +#define FLASH_AR (FLASH_REGS_ADDR + 0x14) +#define FLASH_OBR (FLASH_REGS_ADDR + 0x1c) +#define FLASH_WRPR (FLASH_REGS_ADDR + 0x20) + +// STM32F10x_XL has two flash memory banks with separate registers to control +// the second bank. +#define FLASH_KEYR2 (FLASH_REGS_ADDR + 0x44) +#define FLASH_SR2 (FLASH_REGS_ADDR + 0x4c) +#define FLASH_CR2 (FLASH_REGS_ADDR + 0x50) +#define FLASH_AR2 (FLASH_REGS_ADDR + 0x54) + +// For STM32F05x, the RDPTR_KEY may be wrong, but as it is not used anywhere... +#define FLASH_RDPTR_KEY 0x00a5 +#define FLASH_KEY1 0x45670123 +#define FLASH_KEY2 0xcdef89ab + +#define FLASH_L0_PRGKEY1 0x8c9daebf +#define FLASH_L0_PRGKEY2 0x13141516 + +#define FLASH_L0_PEKEY1 0x89abcdef +#define FLASH_L0_PEKEY2 0x02030405 + +#define FLASH_OPTKEY1 0x08192A3B +#define FLASH_OPTKEY2 0x4C5D6E7F + +#define FLASH_F0_OPTKEY1 0x45670123 +#define FLASH_F0_OPTKEY2 0xCDEF89AB + +#define FLASH_L0_OPTKEY1 0xFBEAD9C8 +#define FLASH_L0_OPTKEY2 0x24252627 + +#define FLASH_SR_BSY 0 +#define FLASH_SR_PG_ERR 2 +#define FLASH_SR_WRPRT_ERR 4 +#define FLASH_SR_EOP 5 + +#define FLASH_SR_ERROR_MASK ((1 << FLASH_SR_PG_ERR) | (1 << FLASH_SR_WRPRT_ERR)) + +#define FLASH_CR_PG 0 +#define FLASH_CR_PER 1 +#define FLASH_CR_MER 2 +#define FLASH_CR_OPTPG 4 +#define FLASH_CR_OPTER 5 +#define FLASH_CR_STRT 6 +#define FLASH_CR_LOCK 7 +#define FLASH_CR_OPTWRE 9 +#define FLASH_CR_OBL_LAUNCH 13 + +#define STM32L_FLASH_REGS_ADDR ((uint32_t)0x40023c00) +#define STM32L_FLASH_ACR (STM32L_FLASH_REGS_ADDR + 0x00) +#define STM32L_FLASH_PECR (STM32L_FLASH_REGS_ADDR + 0x04) +#define STM32L_FLASH_PDKEYR (STM32L_FLASH_REGS_ADDR + 0x08) +#define STM32L_FLASH_PEKEYR (STM32L_FLASH_REGS_ADDR + 0x0c) +#define STM32L_FLASH_PRGKEYR (STM32L_FLASH_REGS_ADDR + 0x10) +#define STM32L_FLASH_OPTKEYR (STM32L_FLASH_REGS_ADDR + 0x14) +#define STM32L_FLASH_SR (STM32L_FLASH_REGS_ADDR + 0x18) +#define STM32L_FLASH_OBR (STM32L_FLASH_REGS_ADDR + 0x1c) +#define STM32L_FLASH_WRPR (STM32L_FLASH_REGS_ADDR + 0x20) +#define FLASH_L1_FPRG 10 +#define FLASH_L1_PROG 3 + +// Flash registers common to STM32G0 and STM32G4 series. +#define STM32Gx_FLASH_REGS_ADDR ((uint32_t)0x40022000) +#define STM32Gx_FLASH_ACR (STM32Gx_FLASH_REGS_ADDR + 0x00) +#define STM32Gx_FLASH_KEYR (STM32Gx_FLASH_REGS_ADDR + 0x08) +#define STM32Gx_FLASH_OPTKEYR (STM32Gx_FLASH_REGS_ADDR + 0x0c) +#define STM32Gx_FLASH_SR (STM32Gx_FLASH_REGS_ADDR + 0x10) +#define STM32Gx_FLASH_CR (STM32Gx_FLASH_REGS_ADDR + 0x14) +#define STM32Gx_FLASH_ECCR (STM32Gx_FLASH_REGS_ADDR + 0x18) +#define STM32Gx_FLASH_OPTR (STM32Gx_FLASH_REGS_ADDR + 0x20) + +// G0 (RM0444 Table 1, sec 3.7) +// Mostly the same as G4 chips, but the notation +// varies a bit after the 'OPTR' register. +#define STM32G0_FLASH_REGS_ADDR (STM32Gx_FLASH_REGS_ADDR) +#define STM32G0_FLASH_PCROP1ASR (STM32G0_FLASH_REGS_ADDR + 0x24) +#define STM32G0_FLASH_PCROP1AER (STM32G0_FLASH_REGS_ADDR + 0x28) +#define STM32G0_FLASH_WRP1AR (STM32G0_FLASH_REGS_ADDR + 0x2C) +#define STM32G0_FLASH_WRP1BR (STM32G0_FLASH_REGS_ADDR + 0x30) +#define STM32G0_FLASH_PCROP1BSR (STM32G0_FLASH_REGS_ADDR + 0x34) +#define STM32G0_FLASH_PCROP1BER (STM32G0_FLASH_REGS_ADDR + 0x38) +#define STM32G0_FLASH_SECR (STM32G0_FLASH_REGS_ADDR + 0x80) + +// G4 (RM0440 Table 17, sec 3.7.19) +// Mostly the same as STM32G0 chips, but there are a few extra +// registers because 'cat 3' devices can have two Flash banks. +#define STM32G4_FLASH_REGS_ADDR (STM32Gx_FLASH_REGS_ADDR) +#define STM32G4_FLASH_PDKEYR (STM32G4_FLASH_REGS_ADDR + 0x04) +#define STM32G4_FLASH_PCROP1SR (STM32G4_FLASH_REGS_ADDR + 0x24) +#define STM32G4_FLASH_PCROP1ER (STM32G4_FLASH_REGS_ADDR + 0x28) +#define STM32G4_FLASH_WRP1AR (STM32G4_FLASH_REGS_ADDR + 0x2C) +#define STM32G4_FLASH_WRP1BR (STM32G4_FLASH_REGS_ADDR + 0x30) +#define STM32G4_FLASH_PCROP2SR (STM32G4_FLASH_REGS_ADDR + 0x44) +#define STM32G4_FLASH_PCROP2ER (STM32G4_FLASH_REGS_ADDR + 0x48) +#define STM32G4_FLASH_WRP2AR (STM32G4_FLASH_REGS_ADDR + 0x4C) +#define STM32G4_FLASH_WRP2BR (STM32G4_FLASH_REGS_ADDR + 0x50) +#define STM32G4_FLASH_SEC1R (STM32G4_FLASH_REGS_ADDR + 0x70) +#define STM32G4_FLASH_SEC2R (STM32G4_FLASH_REGS_ADDR + 0x74) + +// G0/G4 FLASH control register +#define STM32Gx_FLASH_CR_PG (0) /* Program */ +#define STM32Gx_FLASH_CR_PER (1) /* Page erase */ +#define STM32Gx_FLASH_CR_MER1 (2) /* Mass erase */ +#define STM32Gx_FLASH_CR_PNB (3) /* Page number */ +#define STM32G0_FLASH_CR_PNG_LEN (5) /* STM32G0: 5 page number bits */ +#define STM32G4_FLASH_CR_PNG_LEN (7) /* STM32G4: 7 page number bits */ +#define STM32Gx_FLASH_CR_MER2 (15) /* Mass erase (2nd bank)*/ +#define STM32Gx_FLASH_CR_STRT (16) /* Start */ +#define STM32Gx_FLASH_CR_OPTSTRT \ + (17) /* Start of modification of option bytes */ +#define STM32Gx_FLASH_CR_FSTPG (18) /* Fast programming */ +#define STM32Gx_FLASH_CR_EOPIE (24) /* End of operation interrupt enable */ +#define STM32Gx_FLASH_CR_ERRIE (25) /* Error interrupt enable */ +#define STM32Gx_FLASH_CR_OBL_LAUNCH (27) /* Forces the option byte loading */ +#define STM32Gx_FLASH_CR_OPTLOCK (30) /* Options Lock */ +#define STM32Gx_FLASH_CR_LOCK (31) /* FLASH_CR Lock */ + +// G0/G4 FLASH status register +#define STM32Gx_FLASH_SR_ERROR_MASK (0x3fa) +#define STM32Gx_FLASH_SR_PROGERR (3) +#define STM32Gx_FLASH_SR_WRPERR (4) +#define STM32Gx_FLASH_SR_PGAERR (5) +#define STM32Gx_FLASH_SR_BSY (16) /* FLASH_SR Busy */ +#define STM32Gx_FLASH_SR_EOP (0) /* FLASH_EOP End of Operation */ + +// G4 FLASH option register +#define STM32G4_FLASH_OPTR_DBANK (22) /* FLASH_OPTR Dual Bank Mode */ + +// WB (RM0434) +#define STM32WB_FLASH_REGS_ADDR ((uint32_t)0x58004000) +#define STM32WB_FLASH_ACR (STM32WB_FLASH_REGS_ADDR + 0x00) +#define STM32WB_FLASH_KEYR (STM32WB_FLASH_REGS_ADDR + 0x08) +#define STM32WB_FLASH_OPT_KEYR (STM32WB_FLASH_REGS_ADDR + 0x0C) +#define STM32WB_FLASH_SR (STM32WB_FLASH_REGS_ADDR + 0x10) +#define STM32WB_FLASH_CR (STM32WB_FLASH_REGS_ADDR + 0x14) +#define STM32WB_FLASH_ECCR (STM32WB_FLASH_REGS_ADDR + 0x18) +#define STM32WB_FLASH_OPTR (STM32WB_FLASH_REGS_ADDR + 0x20) +#define STM32WB_FLASH_PCROP1ASR (STM32WB_FLASH_REGS_ADDR + 0x24) +#define STM32WB_FLASH_PCROP1AER (STM32WB_FLASH_REGS_ADDR + 0x28) +#define STM32WB_FLASH_WRP1AR (STM32WB_FLASH_REGS_ADDR + 0x2C) +#define STM32WB_FLASH_WRP1BR (STM32WB_FLASH_REGS_ADDR + 0x30) +#define STM32WB_FLASH_PCROP1BSR (STM32WB_FLASH_REGS_ADDR + 0x34) +#define STM32WB_FLASH_PCROP1BER (STM32WB_FLASH_REGS_ADDR + 0x38) +#define STM32WB_FLASH_IPCCBR (STM32WB_FLASH_REGS_ADDR + 0x3C) +#define STM32WB_FLASH_C2ACR (STM32WB_FLASH_REGS_ADDR + 0x5C) +#define STM32WB_FLASH_C2SR (STM32WB_FLASH_REGS_ADDR + 0x60) +#define STM32WB_FLASH_C2CR (STM32WB_FLASH_REGS_ADDR + 0x64) +#define STM32WB_FLASH_SFR (STM32WB_FLASH_REGS_ADDR + 0x80) +#define STM32WB_FLASH_SRRVR (STM32WB_FLASH_REGS_ADDR + 0x84) + +// WB Flash control register. +#define STM32WB_FLASH_CR_STRT (16) /* Start */ +#define STM32WB_FLASH_CR_OPTLOCK (30) /* Option Lock */ +#define STM32WB_FLASH_CR_LOCK (31) /* Lock */ +// WB Flash status register. +#define STM32WB_FLASH_SR_ERROR_MASK (0x3f8) /* SR [9:3] */ +#define STM32WB_FLASH_SR_PROGERR (3) /* Programming alignment error */ +#define STM32WB_FLASH_SR_WRPERR (4) /* Write protection error */ +#define STM32WB_FLASH_SR_PGAERR (5) /* Programming error */ +#define STM32WB_FLASH_SR_BSY (16) /* Busy */ + +// 32L4 register base is at FLASH_REGS_ADDR (0x40022000) +#define STM32L4_FLASH_KEYR (FLASH_REGS_ADDR + 0x08) +#define STM32L4_FLASH_OPTKEYR (FLASH_REGS_ADDR + 0x0C) +#define STM32L4_FLASH_SR (FLASH_REGS_ADDR + 0x10) +#define STM32L4_FLASH_CR (FLASH_REGS_ADDR + 0x14) +#define STM32L4_FLASH_OPTR (FLASH_REGS_ADDR + 0x20) + +#define STM32L4_FLASH_SR_ERROR_MASK 0x3f8 /* SR [9:3] */ +#define STM32L4_FLASH_SR_PROGERR 3 +#define STM32L4_FLASH_SR_WRPERR 4 +#define STM32L4_FLASH_SR_PGAERR 5 +#define STM32L4_FLASH_SR_BSY 16 + +#define STM32L4_FLASH_CR_LOCK 31 /* Lock control register */ +#define STM32L4_FLASH_CR_OPTLOCK 30 /* Lock option bytes */ +#define STM32L4_FLASH_CR_PG 0 /* Program */ +#define STM32L4_FLASH_CR_PER 1 /* Page erase */ +#define STM32L4_FLASH_CR_MER1 2 /* Bank 1 erase */ +#define STM32L4_FLASH_CR_MER2 15 /* Bank 2 erase */ +#define STM32L4_FLASH_CR_STRT 16 /* Start command */ +#define STM32L4_FLASH_CR_OPTSTRT 17 /* Start writing option bytes */ +#define STM32L4_FLASH_CR_BKER 11 /* Bank select for page erase */ +#define STM32L4_FLASH_CR_PNB 3 /* Page number (8 bits) */ +#define STM32L4_FLASH_CR_OBL_LAUNCH 27 /* Option bytes reload */ +// Bits requesting flash operations (useful when we want to clear them) +#define STM32L4_FLASH_CR_OPBITS \ + (uint32_t)((1lu << STM32L4_FLASH_CR_PG) | (1lu << STM32L4_FLASH_CR_PER) | \ + (1lu << STM32L4_FLASH_CR_MER1) | (1lu << STM32L4_FLASH_CR_MER1)) +// Page is fully specified by BKER and PNB +#define STM32L4_FLASH_CR_PAGEMASK (uint32_t)(0x1fflu << STM32L4_FLASH_CR_PNB) + +#define STM32L4_FLASH_OPTR_DUALBANK 21 + +// STM32L0x flash register base and offsets RM0090 - DM00031020.pdf +#define STM32L0_FLASH_REGS_ADDR ((uint32_t)0x40022000) + +#define STM32L0_FLASH_PELOCK (0) +#define STM32L0_FLASH_OPTLOCK (2) +#define STM32L0_FLASH_OBL_LAUNCH (18) + +#define STM32L0_FLASH_SR_ERROR_MASK 0x00013F00 +#define STM32L0_FLASH_SR_WRPERR 8 +#define STM32L0_FLASH_SR_PGAERR 9 +#define STM32L0_FLASH_SR_NOTZEROERR 16 + +#define FLASH_ACR_OFF ((uint32_t)0x00) +#define FLASH_PECR_OFF ((uint32_t)0x04) +#define FLASH_PDKEYR_OFF ((uint32_t)0x08) +#define FLASH_PEKEYR_OFF ((uint32_t)0x0c) +#define FLASH_PRGKEYR_OFF ((uint32_t)0x10) +#define FLASH_OPTKEYR_OFF ((uint32_t)0x14) +#define FLASH_SR_OFF ((uint32_t)0x18) +#define FLASH_OBR_OFF ((uint32_t)0x1c) +#define FLASH_WRPR_OFF ((uint32_t)0x20) + +// STM32F7 +#define FLASH_F7_REGS_ADDR ((uint32_t)0x40023c00) +#define FLASH_F7_KEYR (FLASH_F7_REGS_ADDR + 0x04) +#define FLASH_F7_OPT_KEYR (FLASH_F7_REGS_ADDR + 0x08) +#define FLASH_F7_SR (FLASH_F7_REGS_ADDR + 0x0c) +#define FLASH_F7_CR (FLASH_F7_REGS_ADDR + 0x10) +#define FLASH_F7_OPTCR (FLASH_F7_REGS_ADDR + 0x14) +#define FLASH_F7_OPTCR1 (FLASH_F7_REGS_ADDR + 0x18) +#define FLASH_F7_OPTCR_LOCK 0 +#define FLASH_F7_OPTCR_START 1 +#define FLASH_F7_CR_STRT 16 +#define FLASH_F7_CR_LOCK 31 +#define FLASH_F7_CR_SER 1 +#define FLASH_F7_CR_SNB 3 +#define FLASH_F7_CR_SNB_MASK 0xf8 +#define FLASH_F7_SR_BSY 16 +#define FLASH_F7_SR_ERS_ERR 7 /* Erase Sequence Error */ +#define FLASH_F7_SR_PGP_ERR 6 /* Programming parallelism error */ +#define FLASH_F7_SR_PGA_ERR 5 /* Programming alignment error */ +#define FLASH_F7_SR_WRP_ERR 4 /* Write protection error */ +#define FLASH_F7_SR_OP_ERR 1 /* Operation error */ +#define FLASH_F7_SR_EOP 0 /* End of operation */ +#define FLASH_F7_OPTCR1_BOOT_ADD0 0 +#define FLASH_F7_OPTCR1_BOOT_ADD1 16 + +#define FLASH_F7_SR_ERROR_MASK \ + ((1 << FLASH_F7_SR_ERS_ERR) | (1 << FLASH_F7_SR_PGP_ERR) | \ + (1 << FLASH_F7_SR_PGA_ERR) | (1 << FLASH_F7_SR_WRP_ERR) | \ + (1 << FLASH_F7_SR_OP_ERR)) + +// STM32F4 +#define FLASH_F4_REGS_ADDR ((uint32_t)0x40023c00) +#define FLASH_F4_KEYR (FLASH_F4_REGS_ADDR + 0x04) +#define FLASH_F4_OPT_KEYR (FLASH_F4_REGS_ADDR + 0x08) +#define FLASH_F4_SR (FLASH_F4_REGS_ADDR + 0x0c) +#define FLASH_F4_CR (FLASH_F4_REGS_ADDR + 0x10) +#define FLASH_F4_OPTCR (FLASH_F4_REGS_ADDR + 0x14) +#define FLASH_F4_OPTCR_LOCK 0 +#define FLASH_F4_OPTCR_START 1 +#define FLASH_F4_CR_STRT 16 +#define FLASH_F4_CR_LOCK 31 +#define FLASH_F4_CR_SER 1 +#define FLASH_F4_CR_SNB 3 +#define FLASH_F4_CR_SNB_MASK 0xf8 +#define FLASH_F4_SR_ERROR_MASK 0x000000F0 +#define FLASH_F4_SR_PGAERR 5 +#define FLASH_F4_SR_WRPERR 4 +#define FLASH_F4_SR_BSY 16 + +// STM32F2 +#define FLASH_F2_REGS_ADDR ((uint32_t)0x40023c00) +#define FLASH_F2_KEYR (FLASH_F2_REGS_ADDR + 0x04) +#define FLASH_F2_OPT_KEYR (FLASH_F2_REGS_ADDR + 0x08) +#define FLASH_F2_SR (FLASH_F2_REGS_ADDR + 0x0c) +#define FLASH_F2_CR (FLASH_F2_REGS_ADDR + 0x10) +#define FLASH_F2_OPT_CR (FLASH_F2_REGS_ADDR + 0x14) +#define FLASH_F2_OPT_LOCK_BIT (1u << 0) +#define FLASH_F2_CR_STRT 16 +#define FLASH_F2_CR_LOCK 31 + +#define FLASH_F2_CR_SER 1 +#define FLASH_F2_CR_SNB 3 +#define FLASH_F2_CR_SNB_MASK 0x78 +#define FLASH_F2_SR_BSY 16 + +// STM32H7xx +#define FLASH_H7_CR_LOCK 0 +#define FLASH_H7_CR_PG 1 +#define FLASH_H7_CR_SER 2 +#define FLASH_H7_CR_BER 3 +#define FLASH_H7_CR_PSIZE 4 +#define FLASH_H7_CR_START(chipid) (chipid == STM32_CHIPID_H7Ax ? 5 : 7) +#define FLASH_H7_CR_SNB 8 +#define FLASH_H7_CR_SNB_MASK 0x700 + +#define FLASH_H7_SR_QW 2 +#define FLASH_H7_SR_WRPERR 17 +#define FLASH_H7_SR_PGSERR 18 +#define FLASH_H7_SR_STRBERR 19 +#define FLASH_H7_SR_ERROR_MASK \ + ((1 << FLASH_H7_SR_PGSERR) | (1 << FLASH_H7_SR_STRBERR) | \ + (1 << FLASH_H7_SR_WRPERR)) + +#define FLASH_H7_OPTCR_OPTLOCK 0 +#define FLASH_H7_OPTCR_OPTSTART 1 +#define FLASH_H7_OPTCR_MER 4 + +#define FLASH_H7_OPTSR_OPT_BUSY 0 +#define FLASH_H7_OPTSR_OPTCHANGEERR 30 + +#define FLASH_H7_OPTCCR_CLR_OPTCHANGEERR 30 + +#define FLASH_H7_REGS_ADDR ((uint32_t)0x52002000) +#define FLASH_H7_KEYR1 (FLASH_H7_REGS_ADDR + 0x04) +#define FLASH_H7_KEYR2 (FLASH_H7_REGS_ADDR + 0x104) +#define FLASH_H7_OPT_KEYR (FLASH_H7_REGS_ADDR + 0x08) +#define FLASH_H7_OPT_KEYR2 (FLASH_H7_REGS_ADDR + 0x108) +#define FLASH_H7_CR1 (FLASH_H7_REGS_ADDR + 0x0c) +#define FLASH_H7_CR2 (FLASH_H7_REGS_ADDR + 0x10c) +#define FLASH_H7_SR1 (FLASH_H7_REGS_ADDR + 0x10) +#define FLASH_H7_SR2 (FLASH_H7_REGS_ADDR + 0x110) +#define FLASH_H7_CCR1 (FLASH_H7_REGS_ADDR + 0x14) +#define FLASH_H7_CCR2 (FLASH_H7_REGS_ADDR + 0x114) +#define FLASH_H7_OPTCR (FLASH_H7_REGS_ADDR + 0x18) +#define FLASH_H7_OPTCR2 (FLASH_H7_REGS_ADDR + 0x118) +#define FLASH_H7_OPTSR_CUR (FLASH_H7_REGS_ADDR + 0x1c) +#define FLASH_H7_OPTCCR (FLASH_H7_REGS_ADDR + 0x24) + +#endif // STM32FLASH_H diff --git a/src/calculate.c b/src/calculate.c new file mode 100644 index 000000000..ed3b65873 --- /dev/null +++ b/src/calculate.c @@ -0,0 +1,74 @@ +#include +#include "calculate.h" +#include "common_flash.h" + +uint32_t calculate_F4_sectornum(uint32_t flashaddr) { + uint32_t offset = 0; + flashaddr &= ~STM32_FLASH_BASE; // page now holding the actual flash address + + if (flashaddr >= 0x100000) { + offset = 12; + flashaddr -= 0x100000; + } + + if (flashaddr < 0x4000) { + return (offset + 0); + } else if (flashaddr < 0x8000) { + return (offset + 1); + } else if (flashaddr < 0xc000) { + return (offset + 2); + } else if (flashaddr < 0x10000) { + return (offset + 3); + } else if (flashaddr < 0x20000) { + return (offset + 4); + } else { + return (offset + (flashaddr / 0x20000) + 4); + } +} + +uint32_t calculate_F7_sectornum(uint32_t flashaddr) { + flashaddr &= ~STM32_FLASH_BASE; // Page now holding the actual flash address + + if (flashaddr < 0x20000) { + return (flashaddr / 0x8000); + } else if (flashaddr < 0x40000) { + return (4); + } else { + return ((flashaddr / 0x40000) + 4); + } +} + +uint32_t calculate_H7_sectornum(stlink_t *sl, uint32_t flashaddr, + unsigned bank) { + flashaddr &= + ~((bank == BANK_1) + ? STM32_FLASH_BASE + : STM32_H7_FLASH_BANK2_BASE); // sector holding the flash address + return (flashaddr / sl->flash_pgsz); +} + +// returns BKER:PNB for the given page address +uint32_t calculate_L4_page(stlink_t *sl, uint32_t flashaddr) { + uint32_t bker = 0; + uint32_t flashopt; + stlink_read_debug32(sl, STM32L4_FLASH_OPTR, &flashopt); + flashaddr -= STM32_FLASH_BASE; + + if (sl->chip_id == STM32_CHIPID_L4 || + sl->chip_id == STM32_CHIPID_L496x_L4A6x || + sl->chip_id == STM32_CHIPID_L4Rx) { + // this chip use dual banked flash + if (flashopt & (uint32_t)(1lu << STM32L4_FLASH_OPTR_DUALBANK)) { + uint32_t banksize = (uint32_t)sl->flash_size / 2; + + if (flashaddr >= banksize) { + flashaddr -= banksize; + bker = 0x100; + } + } + } + + // For 1MB chips without the dual-bank option set, the page address will + // overflow into the BKER bit, which gives us the correct bank:page value. + return (bker | flashaddr / (uint32_t)sl->flash_pgsz); +} diff --git a/src/calculate.h b/src/calculate.h new file mode 100644 index 000000000..68c1fb988 --- /dev/null +++ b/src/calculate.h @@ -0,0 +1,15 @@ +/* + * File: calculate.h + * + * TODO: add a description + */ + +#ifndef CALCULATE_H +#define CALCULATE_H + +uint32_t calculate_F4_sectornum(uint32_t); +uint32_t calculate_F7_sectornum(uint32_t); +uint32_t calculate_H7_sectornum(stlink_t *, uint32_t, unsigned); +uint32_t calculate_L4_page(stlink_t *, uint32_t); + +#endif // CALCULATE_H diff --git a/src/common.c b/src/common.c index 266722b91..97f41a533 100644 --- a/src/common.c +++ b/src/common.c @@ -1,4576 +1,1406 @@ -#define DEBUG_FLASH 0 -#include -#include -#include -#include -#include - -#include +#include #include -#include #include #include #include - -#include -#include +#include #include -#include #include - -#ifdef STLINK_HAVE_SYS_MMAN_H -#include -#else -#include -#endif - -#ifndef O_BINARY -#define O_BINARY 0 -#endif +#include +#include +#include +#include "common_flash.h" +#include "calculate.h" +#include "map_file.h" +#include "common.h" #ifdef _MSC_VER #define __attribute__(x) #endif -#define BANK_1 0 -#define BANK_2 1 +// Private structs and functions defines +struct stlink_fread_worker_arg { + int fd; +}; +struct stlink_fread_ihex_worker_arg { + FILE *file; + uint32_t addr; + uint32_t lba; + uint8_t buf[16]; + uint8_t buf_pos; +}; +typedef bool (*save_block_fn)(void *arg, uint8_t *block, ssize_t len); -// Endianness -// https://commandcenter.blogspot.com/2012/04/byte-order-fallacy.html -// These functions encode and decode little endian uint16 and uint32 values. +static void stop_wdg_in_debug(stlink_t *); +int stlink_jtag_reset(stlink_t *, int); +int stlink_soft_reset(stlink_t *, int); +void _parse_version(stlink_t *, stlink_version_t *); +static uint8_t stlink_parse_hex(const char *); +static int stlink_read(stlink_t *, stm32_addr_t, size_t, save_block_fn, void *); +static bool stlink_fread_ihex_init(struct stlink_fread_ihex_worker_arg *, int, stm32_addr_t); +static bool stlink_fread_ihex_worker(void *, uint8_t *, ssize_t); +static bool stlink_fread_ihex_finalize(struct stlink_fread_ihex_worker_arg *); +static bool stlink_fread_worker(void *, uint8_t *, ssize_t); +// End of private structs and functions defines + +// Functions below are defined in stlink.h (see line num before function) +// 252 +void stlink_close(stlink_t *sl) { + DLOG("*** stlink_close ***\n"); -void write_uint32(unsigned char *buf, uint32_t ui) { - buf[0] = ui; - buf[1] = ui >> 8; - buf[2] = ui >> 16; - buf[3] = ui >> 24; -} + if (!sl) { + return; + } -void write_uint16(unsigned char *buf, uint16_t ui) { - buf[0] = (uint8_t)ui; - buf[1] = (uint8_t)(ui >> 8); + sl->backend->close(sl); + free(sl); } +// 250 +int stlink_exit_debug_mode(stlink_t *sl) { + DLOG("*** stlink_exit_debug_mode ***\n"); -uint32_t read_uint32(const unsigned char *c, const int pt) { - return ((uint32_t)c[pt]) | ((uint32_t)c[pt + 1] << 8) | - ((uint32_t)c[pt + 2] << 16) | ((uint32_t)c[pt + 3] << 24); -} + if (sl->flash_type != STM32_FLASH_TYPE_UNKNOWN && + sl->core_stat != TARGET_RESET) { + // stop debugging if the target has been identified + stlink_write_debug32(sl, STLINK_REG_DHCSR, STLINK_REG_DHCSR_DBGKEY); + } -uint16_t read_uint16(const unsigned char *c, const int pt) { - return ((uint16_t)c[pt]) | ((uint16_t)c[pt + 1] << 8); + return (sl->backend->exit_debug_mode(sl)); } - -static uint32_t get_stm32l0_flash_base(stlink_t *sl) { - switch (sl->chip_id) { - case STM32_CHIPID_L0: - case STM32_CHIPID_L0_CAT5: - case STM32_CHIPID_L0_CAT2: - case STM32_CHIPID_L011: - return (STM32L0_FLASH_REGS_ADDR); - - case STM32_CHIPID_L1_CAT2: - case STM32_CHIPID_L1_MD: - case STM32_CHIPID_L1_MD_PLUS: - case STM32_CHIPID_L1_MD_PLUS_HD: - return (STM32L_FLASH_REGS_ADDR); - - default: - WLOG("Flash base use default L0 address\n"); - return (STM32L0_FLASH_REGS_ADDR); +//248 +int stlink_enter_swd_mode(stlink_t *sl) { + DLOG("*** stlink_enter_swd_mode ***\n"); + return (sl->backend->enter_swd_mode(sl)); +} +// 271 +// Force the core into the debug mode -> halted state. +int stlink_force_debug(stlink_t *sl) { + DLOG("*** stlink_force_debug_mode ***\n"); + int res = sl->backend->force_debug(sl); + if (res) { + return (res); } + // Stop the watchdogs in the halted state for suppress target reboot + stop_wdg_in_debug(sl); + return (0); } - -static uint32_t __attribute__((unused)) read_flash_rdp(stlink_t *sl) { - uint32_t rdp; - stlink_read_debug32(sl, FLASH_WRPR, &rdp); - return (rdp & 0xff); +// 251 +int stlink_exit_dfu_mode(stlink_t *sl) { + DLOG("*** stlink_exit_dfu_mode ***\n"); + return (sl->backend->exit_dfu_mode(sl)); } +// 253 +int stlink_core_id(stlink_t *sl) { + int ret; -static inline uint32_t read_flash_cr(stlink_t *sl, unsigned bank) { - uint32_t reg, res; - - if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { - reg = FLASH_F4_CR; - } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { - reg = FLASH_F7_CR; - } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { - reg = STM32L4_FLASH_CR; - } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || - sl->flash_type == STM32_FLASH_TYPE_G4) { - reg = STM32Gx_FLASH_CR; - } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { - reg = STM32WB_FLASH_CR; - } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { - reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; - } else { - reg = (bank == BANK_1) ? FLASH_CR : FLASH_CR2; - } - - stlink_read_debug32(sl, reg, &res); + DLOG("*** stlink_core_id ***\n"); + ret = sl->backend->core_id(sl); -#if DEBUG_FLASH - fprintf(stdout, "CR:0x%x\n", res); -#endif - return (res); -} + if (ret == -1) { + ELOG("Failed to read core_id\n"); + return (ret); + } -static inline unsigned int is_flash_locked(stlink_t *sl) { - /* return non zero for true */ - uint32_t cr_lock_shift; - uint32_t cr_reg; - uint32_t n; - - if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || - (sl->flash_type == STM32_FLASH_TYPE_F1_XL)) { - cr_reg = FLASH_CR; - cr_lock_shift = FLASH_CR_LOCK; - } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { - cr_reg = FLASH_F4_CR; - cr_lock_shift = FLASH_F4_CR_LOCK; - } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { - cr_reg = FLASH_F7_CR; - cr_lock_shift = FLASH_F7_CR_LOCK; - } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { - cr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF; - cr_lock_shift = STM32L0_FLASH_PELOCK; - } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { - cr_reg = STM32L4_FLASH_CR; - cr_lock_shift = STM32L4_FLASH_CR_LOCK; - } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || - sl->flash_type == STM32_FLASH_TYPE_G4) { - cr_reg = STM32Gx_FLASH_CR; - cr_lock_shift = STM32Gx_FLASH_CR_LOCK; - } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { - cr_reg = STM32WB_FLASH_CR; - cr_lock_shift = STM32WB_FLASH_CR_LOCK; - } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { - cr_reg = FLASH_H7_CR1; - cr_lock_shift = FLASH_H7_CR_LOCK; - } else { - ELOG("unsupported flash method, abort\n"); - return (-1); + if (sl->verbose > 2) { + stlink_print_data(sl); } - stlink_read_debug32(sl, cr_reg, &n); - return (n & (1u << cr_lock_shift)); + DLOG("core_id = 0x%08x\n", sl->core_id); + return (ret); } -static void unlock_flash(stlink_t *sl) { - uint32_t key_reg, key2_reg = 0; - uint32_t flash_key1 = FLASH_KEY1; - uint32_t flash_key2 = FLASH_KEY2; - /* The unlock sequence consists of 2 write cycles where 2 key values are - * written to the FLASH_KEYR register. An invalid sequence results in a - * definitive lock of the FPEC block until next reset. - */ +// stlink_chip_id() is called by stlink_load_device_params() +// do not call this procedure directly. +int stlink_chip_id(stlink_t *sl, uint32_t *chip_id) { + int ret; + cortex_m3_cpuid_t cpu_id; - if (sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) { - key_reg = FLASH_KEYR; - } else if (sl->flash_type == STM32_FLASH_TYPE_F1_XL) { - key_reg = FLASH_KEYR; - key2_reg = FLASH_KEYR2; - } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { - key_reg = FLASH_F4_KEYR; - } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { - key_reg = FLASH_F7_KEYR; - } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { - key_reg = get_stm32l0_flash_base(sl) + FLASH_PEKEYR_OFF; - flash_key1 = FLASH_L0_PEKEY1; - flash_key2 = FLASH_L0_PEKEY2; - } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { - key_reg = STM32L4_FLASH_KEYR; - } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || - sl->flash_type == STM32_FLASH_TYPE_G4) { - key_reg = STM32Gx_FLASH_KEYR; - } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { - key_reg = STM32WB_FLASH_KEYR; - } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { - key_reg = FLASH_H7_KEYR1; - if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { - key2_reg = FLASH_H7_KEYR2; - } - } else { - ELOG("unsupported flash method, abort\n"); - return; + // Read the CPU ID to determine where to read the core id + if (stlink_cpu_id(sl, &cpu_id) || + cpu_id.implementer_id != STLINK_REG_CMx_CPUID_IMPL_ARM) { + ELOG("Can not connect to target. Please use \'connect under reset\' and " + "try again\n"); + return -1; } - stlink_write_debug32(sl, key_reg, flash_key1); - stlink_write_debug32(sl, key_reg, flash_key2); - - if (key2_reg) { - stlink_write_debug32(sl, key2_reg, flash_key1); - stlink_write_debug32(sl, key2_reg, flash_key2); - } -} + /* + * the chip_id register in the reference manual have + * DBGMCU_IDCODE / DBG_IDCODE name + * + */ -/* unlock flash if already locked */ -static int unlock_flash_if(stlink_t *sl) { - if (is_flash_locked(sl)) { - unlock_flash(sl); + if ((sl->core_id == STM32_CORE_ID_M7F_H7_SWD || sl->core_id == STM32_CORE_ID_M7F_H7_JTAG) && + cpu_id.part == STLINK_REG_CMx_CPUID_PARTNO_CM7) { + // STM32H7 chipid in 0x5c001000 (RM0433 pg3189) + ret = stlink_read_debug32(sl, 0x5c001000, chip_id); + } else if (cpu_id.part == STLINK_REG_CMx_CPUID_PARTNO_CM0 || + cpu_id.part == STLINK_REG_CMx_CPUID_PARTNO_CM0P) { + // STM32F0 (RM0091, pg914; RM0360, pg713) + // STM32L0 (RM0377, pg813; RM0367, pg915; RM0376, pg917) + // STM32G0 (RM0444, pg1367) + ret = stlink_read_debug32(sl, 0x40015800, chip_id); + } else if (cpu_id.part == STLINK_REG_CMx_CPUID_PARTNO_CM33) { + // STM32L5 (RM0438, pg2157) + ret = stlink_read_debug32(sl, 0xE0044000, chip_id); + } else /* СM3, СM4, CM7 */ { + // default chipid address - if (is_flash_locked(sl)) { - WLOG("Failed to unlock flash!\n"); - return (-1); - } + // STM32F1 (RM0008, pg1087; RM0041, pg681) + // STM32F2 (RM0033, pg1326) + // STM32F3 (RM0316, pg1095; RM0313, pg874) + // STM32F7 (RM0385, pg1676; RM0410, pg1912) + // STM32L1 (RM0038, pg861) + // STM32L4 (RM0351, pg1840; RM0394, pg1560) + // STM32G4 (RM0440, pg2086) + // STM32WB (RM0434, pg1406) + ret = stlink_read_debug32(sl, 0xE0042000, chip_id); } - DLOG("Successfully unlocked flash\n"); - return (0); -} + if (ret || !(*chip_id)) { + *chip_id = 0; + ret = ret?ret:-1; + ELOG("Could not find chip id!\n"); + } else { + *chip_id = (*chip_id) & 0xfff; -static void lock_flash(stlink_t *sl) { - uint32_t cr_lock_shift, cr_reg, n, cr2_reg = 0; - uint32_t cr_mask = 0xffffffffu; - - if (sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) { - cr_reg = FLASH_CR; - cr_lock_shift = FLASH_CR_LOCK; - } else if (sl->flash_type == STM32_FLASH_TYPE_F1_XL) { - cr_reg = FLASH_CR; - cr2_reg = FLASH_CR2; - cr_lock_shift = FLASH_CR_LOCK; - } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { - cr_reg = FLASH_F4_CR; - cr_lock_shift = FLASH_F4_CR_LOCK; - } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { - cr_reg = FLASH_F7_CR; - cr_lock_shift = FLASH_F7_CR_LOCK; - } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { - cr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF; - cr_lock_shift = STM32L0_FLASH_PELOCK; - } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { - cr_reg = STM32L4_FLASH_CR; - cr_lock_shift = STM32L4_FLASH_CR_LOCK; - } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || - sl->flash_type == STM32_FLASH_TYPE_G4) { - cr_reg = STM32Gx_FLASH_CR; - cr_lock_shift = STM32Gx_FLASH_CR_LOCK; - } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { - cr_reg = STM32WB_FLASH_CR; - cr_lock_shift = STM32WB_FLASH_CR_LOCK; - } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { - cr_reg = FLASH_H7_CR1; - if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { - cr2_reg = FLASH_H7_CR2; + // Fix chip_id for F4 rev A errata, read CPU ID, as CoreID is the same for + // F2/F4 + if (*chip_id == 0x411 && cpu_id.part == STLINK_REG_CMx_CPUID_PARTNO_CM4) { + *chip_id = 0x413; } - cr_lock_shift = FLASH_H7_CR_LOCK; - cr_mask = ~(1u << FLASH_H7_CR_SER); - } else { - ELOG("unsupported flash method, abort\n"); - return; } - stlink_read_debug32(sl, cr_reg, &n); - n &= cr_mask; - n |= (1u << cr_lock_shift); - stlink_write_debug32(sl, cr_reg, n); - - if (cr2_reg) { - n = read_flash_cr(sl, BANK_2) | (1u << cr_lock_shift); - stlink_write_debug32(sl, cr2_reg, n); - } + return (ret); } -static bool is_flash_option_locked(stlink_t *sl) { - uint32_t optlock_shift, optcr_reg; - int active_bit_level = 1; - uint32_t n; - - switch (sl->flash_type) { - case STM32_FLASH_TYPE_F0_F1_F3: - case STM32_FLASH_TYPE_F1_XL: - optcr_reg = FLASH_CR; - optlock_shift = FLASH_CR_OPTWRE; - active_bit_level = 0; /* bit is "option write enable", not lock */ - break; - case STM32_FLASH_TYPE_F2_F4: - optcr_reg = FLASH_F4_OPTCR; - optlock_shift = FLASH_F4_OPTCR_LOCK; - break; - case STM32_FLASH_TYPE_F7: - optcr_reg = FLASH_F7_OPTCR; - optlock_shift = FLASH_F7_OPTCR_LOCK; - break; - case STM32_FLASH_TYPE_L0_L1: - optcr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF; - optlock_shift = STM32L0_FLASH_OPTLOCK; - break; - case STM32_FLASH_TYPE_L4_L4P: - optcr_reg = STM32L4_FLASH_CR; - optlock_shift = STM32L4_FLASH_CR_OPTLOCK; - break; - case STM32_FLASH_TYPE_G0: - case STM32_FLASH_TYPE_G4: - optcr_reg = STM32Gx_FLASH_CR; - optlock_shift = STM32Gx_FLASH_CR_OPTLOCK; - break; - case STM32_FLASH_TYPE_WB_WL: - optcr_reg = STM32WB_FLASH_CR; - optlock_shift = STM32WB_FLASH_CR_OPTLOCK; - break; - case STM32_FLASH_TYPE_H7: - optcr_reg = FLASH_H7_OPTCR; - optlock_shift = FLASH_H7_OPTCR_OPTLOCK; - break; - default: - ELOG("unsupported flash method, abort\n"); - return -1; - } - - stlink_read_debug32(sl, optcr_reg, &n); +/** + * Cortex M tech ref manual, CPUID register description + * @param sl stlink context + * @param cpuid pointer to the result object + */ +int stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid) { + uint32_t raw; - if (active_bit_level == 0) { - return (!(n & (1u << optlock_shift))); + if (stlink_read_debug32(sl, STLINK_REG_CM3_CPUID, &raw)) { + cpuid->implementer_id = 0; + cpuid->variant = 0; + cpuid->part = 0; + cpuid->revision = 0; + return (-1); } - return (n & (1u << optlock_shift)); + cpuid->implementer_id = (raw >> 24) & 0x7f; + cpuid->variant = (raw >> 20) & 0xf; + cpuid->part = (raw >> 4) & 0xfff; + cpuid->revision = raw & 0xf; + return (0); } +// 303 +/** + * Reads and decodes the flash parameters, as dynamically as possible + * @param sl + * @return 0 for success, or -1 for unsupported core type. + */ + int stlink_load_device_params(stlink_t *sl) { + // This seems to normally work so is unnecessary info for a normal user. + // Demoted to debug. -- REW + DLOG("Loading device parameters....\n"); + const struct stlink_chipid_params *params = NULL; + stlink_core_id(sl); + uint32_t flash_size; + + if (stlink_chip_id(sl, &sl->chip_id)) { + return (-1); + } + + params = stlink_chipid_get_params(sl->chip_id); + + if (params == NULL) { + WLOG("unknown chip id! %#x\n", sl->chip_id); + return (-1); + } + + if (params->flash_type == STM32_FLASH_TYPE_UNKNOWN) { + WLOG("Invalid flash type, please check device declaration\n"); + sl->flash_size = 0; + return (0); + } + + // These are fixed... + sl->flash_base = STM32_FLASH_BASE; + sl->sram_base = STM32_SRAM_BASE; + stlink_read_debug32(sl, (params->flash_size_reg) & ~3, &flash_size); + + if (params->flash_size_reg & 2) { + flash_size = flash_size >> 16; + } + + flash_size = flash_size & 0xffff; + + if ((sl->chip_id == STM32_CHIPID_L1_MD || + sl->chip_id == STM32_CHIPID_F1_VL_MD_LD || + sl->chip_id == STM32_CHIPID_L1_MD_PLUS) && + (flash_size == 0)) { + sl->flash_size = 128 * 1024; + } else if (sl->chip_id == STM32_CHIPID_L1_CAT2) { + sl->flash_size = (flash_size & 0xff) * 1024; + } else if ((sl->chip_id & 0xFFF) == STM32_CHIPID_L1_MD_PLUS_HD) { + // 0 is 384k and 1 is 256k + if (flash_size == 0) { + sl->flash_size = 384 * 1024; + } else { + sl->flash_size = 256 * 1024; + } + } else { + sl->flash_size = flash_size * 1024; + } + + sl->flash_type = params->flash_type; + sl->flash_pgsz = params->flash_pagesize; + sl->sram_size = params->sram_size; + sl->sys_base = params->bootrom_base; + sl->sys_size = params->bootrom_size; + sl->option_base = params->option_base; + sl->option_size = params->option_size; + sl->chip_flags = params->flags; + + // medium and low devices have the same chipid. ram size depends on flash + // size. STM32F100xx datasheet Doc ID 16455 Table 2 + if (sl->chip_id == STM32_CHIPID_F1_VL_MD_LD && + sl->flash_size < 64 * 1024) { + sl->sram_size = 0x1000; + } + + if (sl->chip_id == STM32_CHIPID_G4_CAT3) { + uint32_t flash_optr; + stlink_read_debug32(sl, STM32Gx_FLASH_OPTR, &flash_optr); + + if (!(flash_optr & (1 << STM32G4_FLASH_OPTR_DBANK))) { + sl->flash_pgsz <<= 1; + } + } + + // H7 devices with small flash has one bank + if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK && + sl->flash_type == STM32_FLASH_TYPE_H7) { + if ((sl->flash_size / sl->flash_pgsz) <= 1) + sl->chip_flags &= ~CHIP_F_HAS_DUAL_BANK; + } + + ILOG("%s: %u KiB SRAM, %u KiB flash in at least %u %s pages.\n", + params->dev_type, (unsigned)(sl->sram_size / 1024), + (unsigned)(sl->flash_size / 1024), + (sl->flash_pgsz < 1024) ? (unsigned)(sl->flash_pgsz) + : (unsigned)(sl->flash_pgsz / 1024), + (sl->flash_pgsz < 1024) ? "byte" : "KiB"); + + return (0); + } -static int lock_flash_option(stlink_t *sl) { - uint32_t optlock_shift, optcr_reg, n, optcr2_reg = 0; - int active_bit_level = 1; +int stlink_reset(stlink_t *sl, enum reset_type type) { + uint32_t dhcsr; + unsigned timeout; - switch (sl->flash_type) { - case STM32_FLASH_TYPE_F0_F1_F3: - case STM32_FLASH_TYPE_F1_XL: - optcr_reg = FLASH_CR; - optlock_shift = FLASH_CR_OPTWRE; - active_bit_level = 0; - break; - case STM32_FLASH_TYPE_F2_F4: - optcr_reg = FLASH_F4_OPTCR; - optlock_shift = FLASH_F4_OPTCR_LOCK; - break; - case STM32_FLASH_TYPE_F7: - optcr_reg = FLASH_F7_OPTCR; - optlock_shift = FLASH_F7_OPTCR_LOCK; - break; - case STM32_FLASH_TYPE_L0_L1: - optcr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF; - optlock_shift = STM32L0_FLASH_OPTLOCK; - break; - case STM32_FLASH_TYPE_L4_L4P: - optcr_reg = STM32L4_FLASH_CR; - optlock_shift = STM32L4_FLASH_CR_OPTLOCK; - break; - case STM32_FLASH_TYPE_G0: - case STM32_FLASH_TYPE_G4: - optcr_reg = STM32Gx_FLASH_CR; - optlock_shift = STM32Gx_FLASH_CR_OPTLOCK; - break; - case STM32_FLASH_TYPE_WB_WL: - optcr_reg = STM32WB_FLASH_CR; - optlock_shift = STM32WB_FLASH_CR_OPTLOCK; - break; - case STM32_FLASH_TYPE_H7: - optcr_reg = FLASH_H7_OPTCR; - optlock_shift = FLASH_H7_OPTCR_OPTLOCK; - if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) - optcr2_reg = FLASH_H7_OPTCR2; - break; - default: - ELOG("unsupported flash method, abort\n"); - return -1; - } + DLOG("*** stlink_reset ***\n"); - stlink_read_debug32(sl, optcr_reg, &n); + sl->core_stat = TARGET_RESET; - if (active_bit_level == 0) { - n &= ~(1u << optlock_shift); - } else { - n |= (1u << optlock_shift); + if (type == RESET_AUTO) { + // clear S_RESET_ST in DHCSR register for reset state detection + stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); } - stlink_write_debug32(sl, optcr_reg, n); - - if (optcr2_reg) { - stlink_read_debug32(sl, optcr2_reg, &n); - - if (active_bit_level == 0) { - n &= ~(1u << optlock_shift); - } else { - n |= (1u << optlock_shift); + if (type == RESET_HARD || type == RESET_AUTO) { + // hardware target reset + if (sl->version.stlink_v > 1) { + stlink_jtag_reset(sl, STLINK_DEBUG_APIV2_DRIVE_NRST_LOW); + // minimum reset pulse duration of 20 us (RM0008, 8.1.2 Power reset) + usleep(100); + stlink_jtag_reset(sl, STLINK_DEBUG_APIV2_DRIVE_NRST_HIGH); } - - stlink_write_debug32(sl, optcr2_reg, n); + sl->backend->reset(sl); + usleep(10000); } - return (0); -} + if (type == RESET_AUTO) { + /* Check if the S_RESET_ST bit is set in DHCSR + * This means that a reset has occurred + * DDI0337E, p. 10-4, Debug Halting Control and Status Register */ -static int unlock_flash_option(stlink_t *sl) { - uint32_t optkey_reg, optkey2_reg = 0; - uint32_t optkey1 = FLASH_OPTKEY1; - uint32_t optkey2 = FLASH_OPTKEY2; + dhcsr = 0; + int res = stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); + if ((dhcsr & STLINK_REG_DHCSR_S_RESET_ST) == 0 && !res) { + // reset not done yet + // try reset through AIRCR so that NRST does not need to be connected + + WLOG("NRST is not connected\n"); + DLOG("Using reset through SYSRESETREQ\n"); + return stlink_soft_reset(sl, 0); + } + + // waiting for reset the S_RESET_ST bit within 500ms + timeout = time_ms() + 500; + while (time_ms() < timeout) { + dhcsr = STLINK_REG_DHCSR_S_RESET_ST; + stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); + if ((dhcsr & STLINK_REG_DHCSR_S_RESET_ST) == 0) { + return (0); + } + } - switch (sl->flash_type) { - case STM32_FLASH_TYPE_F0_F1_F3: - case STM32_FLASH_TYPE_F1_XL: - optkey_reg = FLASH_OPTKEYR; - optkey1 = FLASH_F0_OPTKEY1; - optkey2 = FLASH_F0_OPTKEY2; - break; - case STM32_FLASH_TYPE_F2_F4: - optkey_reg = FLASH_F4_OPT_KEYR; - break; - case STM32_FLASH_TYPE_F7: - optkey_reg = FLASH_F7_OPT_KEYR; - break; - case STM32_FLASH_TYPE_L0_L1: - optkey_reg = get_stm32l0_flash_base(sl) + FLASH_OPTKEYR_OFF; - optkey1 = FLASH_L0_OPTKEY1; - optkey2 = FLASH_L0_OPTKEY2; - break; - case STM32_FLASH_TYPE_L4_L4P: - optkey_reg = STM32L4_FLASH_OPTKEYR; - break; - case STM32_FLASH_TYPE_G0: - case STM32_FLASH_TYPE_G4: - optkey_reg = STM32Gx_FLASH_OPTKEYR; - break; - case STM32_FLASH_TYPE_WB_WL: - optkey_reg = STM32WB_FLASH_OPT_KEYR; - break; - case STM32_FLASH_TYPE_H7: - optkey_reg = FLASH_H7_OPT_KEYR; - if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) - optkey2_reg = FLASH_H7_OPT_KEYR2; - break; - default: - ELOG("unsupported flash method, abort\n"); return (-1); } - stlink_write_debug32(sl, optkey_reg, optkey1); - stlink_write_debug32(sl, optkey_reg, optkey2); - - if (optkey2_reg) { - stlink_write_debug32(sl, optkey2_reg, optkey1); - stlink_write_debug32(sl, optkey2_reg, optkey2); + if (type == RESET_SOFT || type == RESET_SOFT_AND_HALT) { + return stlink_soft_reset(sl, (type == RESET_SOFT_AND_HALT)); } return (0); } +// 255 +int stlink_run(stlink_t *sl, enum run_type type) { + struct stlink_reg rr; + DLOG("*** stlink_run ***\n"); -static int unlock_flash_option_if(stlink_t *sl) { - if (is_flash_option_locked(sl)) { - if (unlock_flash_option(sl)) { - ELOG("Could not unlock flash option!\n"); - return (-1); - } - - if (is_flash_option_locked(sl)) { - ELOG("Failed to unlock flash option!\n"); - return (-1); - } + /* Make sure we are in Thumb mode + * Cortex-M chips don't support ARM mode instructions + * xPSR may be incorrect if the vector table has invalid data */ + stlink_read_reg(sl, 16, &rr); + if ((rr.xpsr & (1 << 24)) == 0) { + ILOG("Go to Thumb mode\n"); + stlink_write_reg(sl, rr.xpsr | (1 << 24), 16); } - DLOG("Successfully unlocked flash option\n"); - return (0); + return (sl->backend->run(sl, type)); } - -static void set_flash_cr_pg(stlink_t *sl, unsigned bank) { - uint32_t cr_reg, x; - - x = read_flash_cr(sl, bank); - - if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { - cr_reg = FLASH_F4_CR; - x |= 1 << FLASH_CR_PG; - } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { - cr_reg = FLASH_F7_CR; - x |= 1 << FLASH_CR_PG; - } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { - cr_reg = STM32L4_FLASH_CR; - x &= ~STM32L4_FLASH_CR_OPBITS; - x |= (1 << STM32L4_FLASH_CR_PG); - } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || - sl->flash_type == STM32_FLASH_TYPE_G4) { - cr_reg = STM32Gx_FLASH_CR; - x |= (1 << FLASH_CR_PG); - } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { - cr_reg = STM32WB_FLASH_CR; - x |= (1 << FLASH_CR_PG); - } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { - cr_reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; - x |= (1 << FLASH_H7_CR_PG); - } else { - cr_reg = FLASH_CR; - x = (1 << FLASH_CR_PG); +// 273 +int stlink_set_swdclk(stlink_t *sl, int freq_khz) { + DLOG("*** set_swdclk ***\n"); + return (sl->backend->set_swdclk(sl, freq_khz)); +} +// 293 +// this function is called by stlink_status() +// do not call stlink_core_stat() directly, always use stlink_status() +void stlink_core_stat(stlink_t *sl) { + switch (sl->core_stat) { + case TARGET_RUNNING: + DLOG(" core status: running\n"); + return; + case TARGET_HALTED: + DLOG(" core status: halted\n"); + return; + case TARGET_RESET: + DLOG(" core status: reset\n"); + return; + case TARGET_DEBUG_RUNNING: + DLOG(" core status: debug running\n"); + return; + default: + DLOG(" core status: unknown\n"); } +} +// 256 +int stlink_status(stlink_t *sl) { + int ret; - stlink_write_debug32(sl, cr_reg, x); + DLOG("*** stlink_status ***\n"); + ret = sl->backend->status(sl); + stlink_core_stat(sl); + return (ret); } +// 257 +int stlink_version(stlink_t *sl) { + DLOG("*** looking up stlink version\n"); -static void clear_flash_cr_pg(stlink_t *sl, unsigned bank) { - uint32_t cr_reg, n; - uint32_t bit = FLASH_CR_PG; - - if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { - cr_reg = FLASH_F4_CR; - } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { - cr_reg = FLASH_F7_CR; - } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { - cr_reg = STM32L4_FLASH_CR; - } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || - sl->flash_type == STM32_FLASH_TYPE_G4) { - cr_reg = STM32Gx_FLASH_CR; - } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { - cr_reg = STM32WB_FLASH_CR; - } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { - cr_reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; - bit = FLASH_H7_CR_PG; - } else { - cr_reg = FLASH_CR; + if (sl->backend->version(sl)) { + return (-1); } - n = read_flash_cr(sl, bank) & ~(1 << bit); - stlink_write_debug32(sl, cr_reg, n); -} + _parse_version(sl, &sl->version); -static void set_flash_cr_per(stlink_t *sl, unsigned bank) { - uint32_t cr_reg, val; + DLOG("st vid = 0x%04x (expect 0x%04x)\n", sl->version.st_vid, + STLINK_USB_VID_ST); + DLOG("stlink pid = 0x%04x\n", sl->version.stlink_pid); + DLOG("stlink version = 0x%x\n", sl->version.stlink_v); + DLOG("jtag version = 0x%x\n", sl->version.jtag_v); + DLOG("swim version = 0x%x\n", sl->version.swim_v); - if (sl->flash_type == STM32_FLASH_TYPE_G0 || - sl->flash_type == STM32_FLASH_TYPE_G4) { - cr_reg = STM32Gx_FLASH_CR; - } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { - cr_reg = STM32WB_FLASH_CR; - } else { - cr_reg = (bank == BANK_1) ? FLASH_CR : FLASH_CR2; + if (sl->version.jtag_v == 0) { + WLOG(" warning: stlink doesn't support JTAG/SWD interface\n"); } - stlink_read_debug32(sl, cr_reg, &val); - val |= (1 << FLASH_CR_PER); - stlink_write_debug32(sl, cr_reg, val); + return (0); } +// 272 +int stlink_target_voltage(stlink_t *sl) { + int voltage = -1; + DLOG("*** reading target voltage\n"); -static void clear_flash_cr_per(stlink_t *sl, unsigned bank) { - uint32_t cr_reg; + if (sl->backend->target_voltage != NULL) { + voltage = sl->backend->target_voltage(sl); - if (sl->flash_type == STM32_FLASH_TYPE_G0 || - sl->flash_type == STM32_FLASH_TYPE_G4) { - cr_reg = STM32Gx_FLASH_CR; - } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { - cr_reg = STM32WB_FLASH_CR; + if (voltage != -1) { + DLOG("target voltage = %imV\n", voltage); + } else { + DLOG("error reading target voltage\n"); + } } else { - cr_reg = (bank == BANK_1) ? FLASH_CR : FLASH_CR2; + DLOG("reading voltage not supported by backend\n"); } - const uint32_t n = read_flash_cr(sl, bank) & ~(1 << FLASH_CR_PER); - stlink_write_debug32(sl, cr_reg, n); + return (voltage); } +// 299 +bool stlink_is_core_halted(stlink_t *sl) { + stlink_status(sl); + return (sl->core_stat == TARGET_HALTED); +} +// 269 +int stlink_step(stlink_t *sl) { + DLOG("*** stlink_step ***\n"); + return (sl->backend->step(sl)); +} +// 270 +int stlink_current_mode(stlink_t *sl) { + int mode = sl->backend->current_mode(sl); -static void set_flash_cr_mer(stlink_t *sl, bool v, unsigned bank) { - uint32_t val, cr_reg, cr_mer, cr_pg; - - if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { - cr_reg = FLASH_F4_CR; - cr_mer = 1 << FLASH_CR_MER; - cr_pg = 1 << FLASH_CR_PG; - } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { - cr_reg = FLASH_F7_CR; - cr_mer = 1 << FLASH_CR_MER; - cr_pg = 1 << FLASH_CR_PG; - } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { - cr_reg = STM32L4_FLASH_CR; - cr_mer = (1 << STM32L4_FLASH_CR_MER1) | (1 << STM32L4_FLASH_CR_MER2); - cr_pg = (1 << STM32L4_FLASH_CR_PG); - } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || - sl->flash_type == STM32_FLASH_TYPE_G4) { - cr_reg = STM32Gx_FLASH_CR; - cr_mer = (1 << STM32Gx_FLASH_CR_MER1); - - if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { - cr_mer |= (1 << STM32Gx_FLASH_CR_MER2); - } - - cr_pg = (1 << FLASH_CR_PG); - } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { - cr_reg = STM32WB_FLASH_CR; - cr_mer = (1 << FLASH_CR_MER); - cr_pg = (1 << FLASH_CR_PG); - } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { - cr_reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; - cr_mer = (1 << FLASH_H7_CR_BER); - cr_pg = (1 << FLASH_H7_CR_PG); - } else { - cr_reg = (bank == BANK_1) ? FLASH_CR : FLASH_CR2; - cr_mer = (1 << FLASH_CR_MER); - cr_pg = (1 << FLASH_CR_PG); + switch (mode) { + case STLINK_DEV_DFU_MODE: + DLOG("stlink current mode: dfu\n"); + return (mode); + case STLINK_DEV_DEBUG_MODE: + DLOG("stlink current mode: debug (jtag or swd)\n"); + return (mode); + case STLINK_DEV_MASS_MODE: + DLOG("stlink current mode: mass\n"); + return (mode); } - stlink_read_debug32(sl, cr_reg, &val); - - if (val & cr_pg) { - // STM32F030 will drop MER bit if PG was set - val &= ~cr_pg; - stlink_write_debug32(sl, cr_reg, val); + DLOG("stlink mode: unknown!\n"); + return (STLINK_DEV_UNKNOWN_MODE); +} +// 274 +int stlink_trace_enable(stlink_t *sl, uint32_t frequency) { + DLOG("*** stlink_trace_enable ***\n"); + return (sl->backend->trace_enable(sl, frequency)); +} +// 275 +int stlink_trace_disable(stlink_t *sl) { + DLOG("*** stlink_trace_disable ***\n"); + return (sl->backend->trace_disable(sl)); +} +// 276 +int stlink_trace_read(stlink_t *sl, uint8_t *buf, size_t size) { + return (sl->backend->trace_read(sl, buf, size)); +} +// 294 +void stlink_print_data(stlink_t *sl) { + if (sl->q_len <= 0 || sl->verbose < UDEBUG) { + return; } - if (v) { - val |= cr_mer; - } else { - val &= ~cr_mer; + if (sl->verbose > 2) { + DLOG("data_len = %d 0x%x\n", sl->q_len, sl->q_len); } - stlink_write_debug32(sl, cr_reg, val); + for (int i = 0; i < sl->q_len; i++) { + if (i % 16 == 0) { + /* + if (sl->q_data_dir == Q_DATA_OUT) { + fprintf(stdout, "\n<- 0x%08x ", sl->q_addr + i); + } else { + fprintf(stdout, "\n-> 0x%08x ", sl->q_addr + i); + } + */ + } + // DLOG(" %02x", (unsigned int) sl->q_buf[i]); + fprintf(stderr, " %02x", (unsigned int)sl->q_buf[i]); + } + // DLOG("\n\n"); + fprintf(stderr, "\n"); } +// 283 +int stlink_mwrite_sram(stlink_t *sl, uint8_t *data, uint32_t length, + stm32_addr_t addr) { + // write the file in sram at addr -static void set_flash_cr_strt(stlink_t *sl, unsigned bank) { - uint32_t val, cr_reg, cr_strt; - - if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { - cr_reg = FLASH_F4_CR; - cr_strt = 1 << FLASH_F4_CR_STRT; - } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { - cr_reg = FLASH_F7_CR; - cr_strt = 1 << FLASH_F7_CR_STRT; - } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { - cr_reg = STM32L4_FLASH_CR; - cr_strt = (1 << STM32L4_FLASH_CR_STRT); - } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || - sl->flash_type == STM32_FLASH_TYPE_G4) { - cr_reg = STM32Gx_FLASH_CR; - cr_strt = (1 << STM32Gx_FLASH_CR_STRT); - } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { - cr_reg = STM32WB_FLASH_CR; - cr_strt = (1 << STM32WB_FLASH_CR_STRT); - } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { - cr_reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; - cr_strt = 1 << FLASH_H7_CR_START(sl->chip_id); - } else { - cr_reg = (bank == BANK_1) ? FLASH_CR : FLASH_CR2; - cr_strt = (1 << FLASH_CR_STRT); + int error = -1; + size_t off; + size_t len; + + // check addr range is inside the sram + if (addr < sl->sram_base) { + fprintf(stderr, "addr too low\n"); + goto on_error; + } else if ((addr + length) < addr) { + fprintf(stderr, "addr overruns\n"); + goto on_error; + } else if ((addr + length) > (sl->sram_base + sl->sram_size)) { + fprintf(stderr, "addr too high\n"); + goto on_error; + } else if (addr & 3) { + fprintf(stderr, "unaligned addr\n"); + goto on_error; } - stlink_read_debug32(sl, cr_reg, &val); - val |= cr_strt; - stlink_write_debug32(sl, cr_reg, val); -} + len = length; -static inline uint32_t read_flash_sr(stlink_t *sl, unsigned bank) { - uint32_t res, sr_reg; - - if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || - (sl->flash_type == STM32_FLASH_TYPE_F1_XL)) { - sr_reg = (bank == BANK_1) ? FLASH_SR : FLASH_SR2; - } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { - sr_reg = get_stm32l0_flash_base(sl) + FLASH_SR_OFF; - } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { - sr_reg = FLASH_F4_SR; - } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { - sr_reg = FLASH_F7_SR; - } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { - sr_reg = STM32L4_FLASH_SR; - } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || - sl->flash_type == STM32_FLASH_TYPE_G4) { - sr_reg = STM32Gx_FLASH_SR; - } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { - sr_reg = STM32WB_FLASH_SR; - } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { - sr_reg = (bank == BANK_1) ? FLASH_H7_SR1 : FLASH_H7_SR2; - } else { - ELOG("method 'read_flash_sr' is unsupported\n"); - return (-1); + if (len & 3) { + len -= len & 3; } - stlink_read_debug32(sl, sr_reg, &res); - return (res); -} + // do the copy by 1kB blocks + for (off = 0; off < len; off += 1024) { + size_t size = 1024; -static inline int write_flash_sr(stlink_t *sl, unsigned bank, uint32_t val) { - uint32_t sr_reg; - - if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || - (sl->flash_type == STM32_FLASH_TYPE_F1_XL)) { - sr_reg = (bank == BANK_1) ? FLASH_SR : FLASH_SR2; - } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { - sr_reg = get_stm32l0_flash_base(sl) + FLASH_SR_OFF; - } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { - sr_reg = FLASH_F4_SR; - } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { - sr_reg = FLASH_F7_SR; - } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { - sr_reg = STM32L4_FLASH_SR; - } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || - sl->flash_type == STM32_FLASH_TYPE_G4) { - sr_reg = STM32Gx_FLASH_SR; - } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { - sr_reg = STM32WB_FLASH_SR; - } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { - sr_reg = (bank == BANK_1) ? FLASH_H7_SR1 : FLASH_H7_SR2; - } else { - ELOG("method 'write_flash_sr' is unsupported\n"); - return (-1); - } + if ((off + size) > len) { + size = len - off; + } - return stlink_write_debug32(sl, sr_reg, val); -} + memcpy(sl->q_buf, data + off, size); -static inline unsigned int is_flash_busy(stlink_t *sl) { - uint32_t sr_busy_shift; - unsigned int res; - - if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || - (sl->flash_type == STM32_FLASH_TYPE_F1_XL) || - (sl->flash_type == STM32_FLASH_TYPE_L0_L1)) { - sr_busy_shift = FLASH_SR_BSY; - } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { - sr_busy_shift = FLASH_F4_SR_BSY; - } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { - sr_busy_shift = FLASH_F7_SR_BSY; - } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { - sr_busy_shift = STM32L4_FLASH_SR_BSY; - } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || - sl->flash_type == STM32_FLASH_TYPE_G4) { - sr_busy_shift = STM32Gx_FLASH_SR_BSY; - } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { - sr_busy_shift = STM32WB_FLASH_SR_BSY; - } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { - sr_busy_shift = FLASH_H7_SR_QW; - } else { - ELOG("method 'is_flash_busy' is unsupported\n"); - return (-1); - } + if (size & 3) { + size += 2; + } // round size if needed - res = read_flash_sr(sl, BANK_1) & (1 << sr_busy_shift); + stlink_write_mem32(sl, addr + (uint32_t)off, (uint16_t)size); + } - if (sl->flash_type == STM32_FLASH_TYPE_F1_XL || - (sl->flash_type == STM32_FLASH_TYPE_H7 && - sl->chip_flags & CHIP_F_HAS_DUAL_BANK)) { - res |= read_flash_sr(sl, BANK_2) & (1 << sr_busy_shift); + if (length > len) { + memcpy(sl->q_buf, data + len, length - len); + stlink_write_mem8(sl, addr + (uint32_t)len, (uint16_t)(length - len)); } - return (res); -} + error = 0; // success + stlink_fwrite_finalize(sl, addr); -static void wait_flash_busy(stlink_t *sl) { - // TODO: add some delays here - while (is_flash_busy(sl)) - ; +on_error: + return (error); } +//284 +int stlink_fwrite_sram(stlink_t *sl, const char *path, stm32_addr_t addr) { + // write the file in sram at addr -static void wait_flash_busy_progress(stlink_t *sl) { - int i = 0; - fprintf(stdout, "Mass erasing"); - fflush(stdout); - - while (is_flash_busy(sl)) { - usleep(10000); - i++; + int error = -1; + size_t off; + size_t len; + mapped_file_t mf = MAPPED_FILE_INITIALIZER; - if (i % 100 == 0) { - fprintf(stdout, "."); - fflush(stdout); - } + if (map_file(&mf, path) == -1) { + fprintf(stderr, "map_file() == -1\n"); + return (-1); } - fprintf(stdout, "\n"); -} + printf("file %s ", path); + md5_calculate(&mf); + stlink_checksum(&mf); -static void clear_flash_error(stlink_t *sl) { - switch (sl->flash_type) { - case STM32_FLASH_TYPE_F0_F1_F3: - write_flash_sr(sl, BANK_1, FLASH_SR_ERROR_MASK); - break; - case STM32_FLASH_TYPE_F2_F4: - write_flash_sr(sl, BANK_1, FLASH_F4_SR_ERROR_MASK); - break; - case STM32_FLASH_TYPE_F7: - write_flash_sr(sl, BANK_1, FLASH_F7_SR_ERROR_MASK); - break; - case STM32_FLASH_TYPE_G0: - case STM32_FLASH_TYPE_G4: - write_flash_sr(sl, BANK_1, STM32Gx_FLASH_SR_ERROR_MASK); - break; - case STM32_FLASH_TYPE_L0_L1: - write_flash_sr(sl, BANK_1, STM32L0_FLASH_SR_ERROR_MASK); - break; - case STM32_FLASH_TYPE_L4_L4P: - write_flash_sr(sl, BANK_1, STM32L4_FLASH_SR_ERROR_MASK); - break; - case STM32_FLASH_TYPE_H7: - write_flash_sr(sl, BANK_1, FLASH_H7_SR_ERROR_MASK); - if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { - write_flash_sr(sl, BANK_2, FLASH_H7_SR_ERROR_MASK); - } - break; - case STM32_FLASH_TYPE_WB_WL: - write_flash_sr(sl, BANK_1, STM32WB_FLASH_SR_ERROR_MASK); - break; - default: - break; + // check if addr range is inside the SRAM + if (addr < sl->sram_base) { + fprintf(stderr, "addr too low\n"); + goto on_error; + } else if ((addr + mf.len) < addr) { + fprintf(stderr, "addr overruns\n"); + goto on_error; + } else if ((addr + mf.len) > (sl->sram_base + sl->sram_size)) { + fprintf(stderr, "addr too high\n"); + goto on_error; + } else if (addr & 3) { + fprintf(stderr, "unaligned addr\n"); + goto on_error; } -} - -static int check_flash_error(stlink_t *sl) { - uint32_t res = 0; - uint32_t WRPERR, PROGERR, PGAERR; - WRPERR = PROGERR = PGAERR = 0; + len = mf.len; - switch (sl->flash_type) { - case STM32_FLASH_TYPE_F0_F1_F3: - case STM32_FLASH_TYPE_F1_XL: - res = read_flash_sr(sl, BANK_1) & FLASH_SR_ERROR_MASK; - if (sl->flash_type == STM32_FLASH_TYPE_F1_XL) { - res |= read_flash_sr(sl, BANK_2) & FLASH_SR_ERROR_MASK; - } - WRPERR = (1 << FLASH_SR_WRPRT_ERR); - PROGERR = (1 << FLASH_SR_PG_ERR); - break; - case STM32_FLASH_TYPE_F2_F4: - res = read_flash_sr(sl, BANK_1) & FLASH_F4_SR_ERROR_MASK; - WRPERR = (1 << FLASH_F4_SR_WRPERR); - PGAERR = (1 << FLASH_F4_SR_PGAERR); - break; - case STM32_FLASH_TYPE_F7: - res = read_flash_sr(sl, BANK_1) & FLASH_F7_SR_ERROR_MASK; - WRPERR = (1 << FLASH_F7_SR_WRP_ERR); - PROGERR = (1 << FLASH_F7_SR_PGP_ERR); - break; - case STM32_FLASH_TYPE_G0: - case STM32_FLASH_TYPE_G4: - res = read_flash_sr(sl, BANK_1) & STM32Gx_FLASH_SR_ERROR_MASK; - WRPERR = (1 << STM32Gx_FLASH_SR_WRPERR); - PROGERR = (1 << STM32Gx_FLASH_SR_PROGERR); - PGAERR = (1 << STM32Gx_FLASH_SR_PGAERR); - break; - case STM32_FLASH_TYPE_L0_L1: - res = read_flash_sr(sl, BANK_1) & STM32L0_FLASH_SR_ERROR_MASK; - WRPERR = (1 << STM32L0_FLASH_SR_WRPERR); - PROGERR = (1 << STM32L0_FLASH_SR_NOTZEROERR); - PGAERR = (1 << STM32L0_FLASH_SR_PGAERR); - break; - case STM32_FLASH_TYPE_L4_L4P: - res = read_flash_sr(sl, BANK_1) & STM32L4_FLASH_SR_ERROR_MASK; - WRPERR = (1 << STM32L4_FLASH_SR_WRPERR); - PROGERR = (1 << STM32L4_FLASH_SR_PROGERR); - PGAERR = (1 << STM32L4_FLASH_SR_PGAERR); - break; - case STM32_FLASH_TYPE_H7: - res = read_flash_sr(sl, BANK_1) & FLASH_H7_SR_ERROR_MASK; - if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { - res |= read_flash_sr(sl, BANK_2) & FLASH_H7_SR_ERROR_MASK; - } - WRPERR = (1 << FLASH_H7_SR_WRPERR); - break; - case STM32_FLASH_TYPE_WB_WL: - res = read_flash_sr(sl, BANK_1) & STM32WB_FLASH_SR_ERROR_MASK; - WRPERR = (1 << STM32WB_FLASH_SR_WRPERR); - PROGERR = (1 << STM32WB_FLASH_SR_PROGERR); - PGAERR = (1 << STM32WB_FLASH_SR_PGAERR); - break; - default: - break; + if (len & 3) { + len -= len & 3; } - if (res) { - if (WRPERR && (WRPERR & res) == WRPERR) { - ELOG("Flash memory is write protected\n"); - res &= ~WRPERR; - } else if (PROGERR && (PROGERR & res) == PROGERR) { - ELOG("Flash memory contains a non-erased value\n"); - res &= ~PROGERR; - } else if (PGAERR && (PGAERR & res) == PGAERR) { - ELOG("Invalid flash address\n"); - res &= ~PGAERR; - } + // do the copy by 1kB blocks + for (off = 0; off < len; off += 1024) { + size_t size = 1024; - if (res) { - ELOG("Flash programming error: %#010x\n", res); + if ((off + size) > len) { + size = len - off; } - return (-1); - } - return (0); -} + memcpy(sl->q_buf, mf.base + off, size); -static void stop_wdg_in_debug(stlink_t *sl) { - uint32_t dbgmcu_cr; - uint32_t set; - uint32_t value; + if (size & 3) { + size += 2; + } // round size if needed - switch (sl->flash_type) { - case STM32_FLASH_TYPE_F0_F1_F3: - case STM32_FLASH_TYPE_F1_XL: - case STM32_FLASH_TYPE_G4: - dbgmcu_cr = STM32F0_DBGMCU_CR; - set = (1 << STM32F0_DBGMCU_CR_IWDG_STOP) | - (1 << STM32F0_DBGMCU_CR_WWDG_STOP); - break; - case STM32_FLASH_TYPE_F2_F4: - case STM32_FLASH_TYPE_F7: - case STM32_FLASH_TYPE_L4_L4P: - dbgmcu_cr = STM32F4_DBGMCU_APB1FZR1; - set = (1 << STM32F4_DBGMCU_APB1FZR1_IWDG_STOP) | - (1 << STM32F4_DBGMCU_APB1FZR1_WWDG_STOP); - break; - case STM32_FLASH_TYPE_L0_L1: - case STM32_FLASH_TYPE_G0: - dbgmcu_cr = STM32L0_DBGMCU_APB1_FZ; - set = (1 << STM32L0_DBGMCU_APB1_FZ_IWDG_STOP) | - (1 << STM32L0_DBGMCU_APB1_FZ_WWDG_STOP); - break; - case STM32_FLASH_TYPE_H7: - dbgmcu_cr = STM32H7_DBGMCU_APB1HFZ; - set = (1 << STM32H7_DBGMCU_APB1HFZ_IWDG_STOP); - break; - case STM32_FLASH_TYPE_WB_WL: - dbgmcu_cr = STM32WB_DBGMCU_APB1FZR1; - set = (1 << STM32WB_DBGMCU_APB1FZR1_IWDG_STOP) | - (1 << STM32WB_DBGMCU_APB1FZR1_WWDG_STOP); - break; - default: - return; + stlink_write_mem32(sl, addr + (uint32_t)off, (uint16_t)size); } - if (!stlink_read_debug32(sl, dbgmcu_cr, &value)) { - stlink_write_debug32(sl, dbgmcu_cr, value | set); + if (mf.len > len) { + memcpy(sl->q_buf, mf.base + len, mf.len - len); + stlink_write_mem8(sl, addr + (uint32_t)len, (uint16_t)(mf.len - len)); } -} -static void set_dma_state(stlink_t *sl, flash_loader_t *fl, int bckpRstr) { - uint32_t rcc, rcc_dma_mask, value; - - rcc = rcc_dma_mask = value = 0; - - switch (sl->flash_type) { - case STM32_FLASH_TYPE_F0_F1_F3: - case STM32_FLASH_TYPE_F1_XL: - rcc = STM32F1_RCC_AHBENR; - rcc_dma_mask = STM32F1_RCC_DMAEN; - break; - case STM32_FLASH_TYPE_F2_F4: - case STM32_FLASH_TYPE_F7: - rcc = STM32F4_RCC_AHB1ENR; - rcc_dma_mask = STM32F4_RCC_DMAEN; - break; - case STM32_FLASH_TYPE_G0: - rcc = STM32G0_RCC_AHBENR; - rcc_dma_mask = STM32G0_RCC_DMAEN; - break; - case STM32_FLASH_TYPE_G4: - case STM32_FLASH_TYPE_L4_L4P: - rcc = STM32G4_RCC_AHB1ENR; - rcc_dma_mask = STM32G4_RCC_DMAEN; - break; - case STM32_FLASH_TYPE_L0_L1: - rcc = STM32L0_RCC_AHBENR; - rcc_dma_mask = STM32L0_RCC_DMAEN; - break; - case STM32_FLASH_TYPE_H7: - rcc = STM32H7_RCC_AHB1ENR; - rcc_dma_mask = STM32H7_RCC_DMAEN; - break; - case STM32_FLASH_TYPE_WB_WL: - rcc = STM32WB_RCC_AHB1ENR; - rcc_dma_mask = STM32WB_RCC_DMAEN; - break; - default: - return; + // check the file has been written + if (check_file(sl, &mf, addr) == -1) { + fprintf(stderr, "check_file() == -1\n"); + goto on_error; } - if (!stlink_read_debug32(sl, rcc, &value)) { - if (bckpRstr) { - value = (value & (~rcc_dma_mask)) | fl->rcc_dma_bkp; - } else { - fl->rcc_dma_bkp = value & rcc_dma_mask; - value &= ~rcc_dma_mask; - } - stlink_write_debug32(sl, rcc, value); - } -} + error = 0; // success + stlink_fwrite_finalize(sl, addr); -static inline void write_flash_ar(stlink_t *sl, uint32_t n, unsigned bank) { - stlink_write_debug32(sl, (bank == BANK_1) ? FLASH_AR : FLASH_AR2, n); +on_error: + unmap_file(&mf); + return (error); } +// 302 +int stlink_fread(stlink_t *sl, const char *path, bool is_ihex, + stm32_addr_t addr, size_t size) { + // read size bytes from addr to file + ILOG("read from address %#010x size %u\n", addr, (unsigned)size); -static inline void write_flash_cr_psiz(stlink_t *sl, uint32_t n, - unsigned bank) { - uint32_t cr_reg, psize_shift; - uint32_t x = read_flash_cr(sl, bank); + int error; + int fd = open(path, O_RDWR | O_TRUNC | O_CREAT | O_BINARY, 00700); - if (sl->flash_type == STM32_FLASH_TYPE_H7) { - cr_reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; - psize_shift = FLASH_H7_CR_PSIZE; - } else { - cr_reg = FLASH_F4_CR; - psize_shift = 8; + if (fd == -1) { + fprintf(stderr, "open(%s) == -1\n", path); + return (-1); } - x &= ~(0x03 << psize_shift); - x |= (n << psize_shift); -#if DEBUG_FLASH - fprintf(stdout, "PSIZ:0x%x 0x%x\n", x, n); -#endif - stlink_write_debug32(sl, cr_reg, x); -} + if (is_ihex) { + struct stlink_fread_ihex_worker_arg arg; -static inline void write_flash_cr_snb(stlink_t *sl, uint32_t n, unsigned bank) { - uint32_t cr_reg, snb_mask, snb_shift, ser_shift; - uint32_t x = read_flash_cr(sl, bank); + if (stlink_fread_ihex_init(&arg, fd, addr)) { + error = stlink_read(sl, addr, size, &stlink_fread_ihex_worker, &arg); - if (sl->flash_type == STM32_FLASH_TYPE_H7) { - cr_reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; - snb_mask = FLASH_H7_CR_SNB_MASK; - snb_shift = FLASH_H7_CR_SNB; - ser_shift = FLASH_H7_CR_SER; + if (!stlink_fread_ihex_finalize(&arg)) { + error = -1; + } + } else { + error = -1; + } } else { - cr_reg = FLASH_F4_CR; - snb_mask = FLASH_F4_CR_SNB_MASK; - snb_shift = FLASH_F4_CR_SNB; - ser_shift = FLASH_F4_CR_SER; + struct stlink_fread_worker_arg arg = {fd}; + error = stlink_read(sl, addr, size, &stlink_fread_worker, &arg); } - x &= ~snb_mask; - x |= (n << snb_shift); - x |= (1 << ser_shift); -#if DEBUG_FLASH - fprintf(stdout, "SNB:0x%x 0x%x\n", x, n); -#endif - stlink_write_debug32(sl, cr_reg, x); -} - -static inline void write_flash_cr_bker_pnb(stlink_t *sl, uint32_t n) { - stlink_write_debug32(sl, STM32L4_FLASH_SR, - 0xFFFFFFFF & ~(1 << STM32L4_FLASH_SR_BSY)); - uint32_t x = read_flash_cr(sl, BANK_1); - x &= ~STM32L4_FLASH_CR_OPBITS; - x &= ~STM32L4_FLASH_CR_PAGEMASK; - x &= ~(1 << STM32L4_FLASH_CR_MER1); - x &= ~(1 << STM32L4_FLASH_CR_MER2); - x |= (n << STM32L4_FLASH_CR_PNB); - x |= (uint32_t)(1lu << STM32L4_FLASH_CR_PER); -#if DEBUG_FLASH - fprintf(stdout, "BKER:PNB:0x%x 0x%x\n", x, n); -#endif - stlink_write_debug32(sl, STM32L4_FLASH_CR, x); + close(fd); + return (error); } +// 300 +int write_buffer_to_sram(stlink_t *sl, flash_loader_t *fl, const uint8_t *buf, + size_t size) { + // write the buffer right after the loader + int ret = 0; + size_t chunk = size & ~0x3; + size_t rem = size & 0x3; -// Delegates to the backends... - -void stlink_close(stlink_t *sl) { - DLOG("*** stlink_close ***\n"); + if (chunk) { + memcpy(sl->q_buf, buf, chunk); + ret = stlink_write_mem32(sl, fl->buf_addr, (uint16_t)chunk); + } - if (!sl) { - return; + if (rem && !ret) { + memcpy(sl->q_buf, buf + chunk, rem); + ret = stlink_write_mem8(sl, (fl->buf_addr) + (uint32_t)chunk, (uint16_t)rem); } - sl->backend->close(sl); - free(sl); + return (ret); } +// 291 +uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr) { + if ((sl->chip_id == STM32_CHIPID_F2) || + (sl->chip_id == STM32_CHIPID_F4) || + (sl->chip_id == STM32_CHIPID_F4_DE) || + (sl->chip_id == STM32_CHIPID_F4_LP) || + (sl->chip_id == STM32_CHIPID_F4_HD) || + (sl->chip_id == STM32_CHIPID_F411xx) || + (sl->chip_id == STM32_CHIPID_F446) || + (sl->chip_id == STM32_CHIPID_F4_DSI) || + (sl->chip_id == STM32_CHIPID_F72xxx) || + (sl->chip_id == STM32_CHIPID_F412)) { + uint32_t sector = calculate_F4_sectornum(flashaddr); -int stlink_exit_debug_mode(stlink_t *sl) { - DLOG("*** stlink_exit_debug_mode ***\n"); + if (sector >= 12) { + sector -= 12; + } - if (sl->flash_type != STM32_FLASH_TYPE_UNKNOWN && - sl->core_stat != TARGET_RESET) { - // stop debugging if the target has been identified - stlink_write_debug32(sl, STLINK_REG_DHCSR, STLINK_REG_DHCSR_DBGKEY); + if (sector < 4) { + sl->flash_pgsz = 0x4000; + } else if (sector < 5) { + sl->flash_pgsz = 0x10000; + } else { + sl->flash_pgsz = 0x20000; + } + } else if (sl->chip_id == STM32_CHIPID_F7 || + sl->chip_id == STM32_CHIPID_F76xxx) { + uint32_t sector = calculate_F7_sectornum(flashaddr); + + if (sector < 4) { + sl->flash_pgsz = 0x8000; + } else if (sector < 5) { + sl->flash_pgsz = 0x20000; + } else { + sl->flash_pgsz = 0x40000; + } } - return (sl->backend->exit_debug_mode(sl)); + return ((uint32_t)sl->flash_pgsz); } +// 279 +int stlink_parse_ihex(const char *path, uint8_t erased_pattern, uint8_t **mem, + size_t *size, uint32_t *begin) { + int res = 0; + *begin = UINT32_MAX; + uint8_t *data = NULL; + uint32_t end = 0; + bool eof_found = false; -int stlink_enter_swd_mode(stlink_t *sl) { - DLOG("*** stlink_enter_swd_mode ***\n"); - return (sl->backend->enter_swd_mode(sl)); -} + for (int scan = 0; (res == 0) && (scan < 2); ++scan) { + // parse file two times - first to find memory range, second - to fill it + if (scan == 1) { + if (!eof_found) { + ELOG("No EoF recond\n"); + res = -1; + break; + } -// Force the core into the debug mode -> halted state. -int stlink_force_debug(stlink_t *sl) { - DLOG("*** stlink_force_debug_mode ***\n"); - int res = sl->backend->force_debug(sl); - if (res) { - return (res); - } - // Stop the watchdogs in the halted state for suppress target reboot - stop_wdg_in_debug(sl); - return (0); -} - -int stlink_exit_dfu_mode(stlink_t *sl) { - DLOG("*** stlink_exit_dfu_mode ***\n"); - return (sl->backend->exit_dfu_mode(sl)); -} - -int stlink_core_id(stlink_t *sl) { - int ret; - - DLOG("*** stlink_core_id ***\n"); - ret = sl->backend->core_id(sl); - - if (ret == -1) { - ELOG("Failed to read core_id\n"); - return (ret); - } - - if (sl->verbose > 2) { - stlink_print_data(sl); - } - - DLOG("core_id = 0x%08x\n", sl->core_id); - return (ret); -} - -// stlink_chip_id() is called by stlink_load_device_params() -// do not call this procedure directly. -int stlink_chip_id(stlink_t *sl, uint32_t *chip_id) { - int ret; - cortex_m3_cpuid_t cpu_id; - - // Read the CPU ID to determine where to read the core id - if (stlink_cpu_id(sl, &cpu_id) || - cpu_id.implementer_id != STLINK_REG_CMx_CPUID_IMPL_ARM) { - ELOG("Can not connect to target. Please use \'connect under reset\' and " - "try again\n"); - return -1; - } - - /* - * the chip_id register in the reference manual have - * DBGMCU_IDCODE / DBG_IDCODE name - * - */ - - if ((sl->core_id == STM32_CORE_ID_M7F_H7_SWD || sl->core_id == STM32_CORE_ID_M7F_H7_JTAG) && - cpu_id.part == STLINK_REG_CMx_CPUID_PARTNO_CM7) { - // STM32H7 chipid in 0x5c001000 (RM0433 pg3189) - ret = stlink_read_debug32(sl, 0x5c001000, chip_id); - } else if (cpu_id.part == STLINK_REG_CMx_CPUID_PARTNO_CM0 || - cpu_id.part == STLINK_REG_CMx_CPUID_PARTNO_CM0P) { - // STM32F0 (RM0091, pg914; RM0360, pg713) - // STM32L0 (RM0377, pg813; RM0367, pg915; RM0376, pg917) - // STM32G0 (RM0444, pg1367) - ret = stlink_read_debug32(sl, 0x40015800, chip_id); - } else if (cpu_id.part == STLINK_REG_CMx_CPUID_PARTNO_CM33) { - // STM32L5 (RM0438, pg2157) - ret = stlink_read_debug32(sl, 0xE0044000, chip_id); - } else /* СM3, СM4, CM7 */ { - // default chipid address - - // STM32F1 (RM0008, pg1087; RM0041, pg681) - // STM32F2 (RM0033, pg1326) - // STM32F3 (RM0316, pg1095; RM0313, pg874) - // STM32F7 (RM0385, pg1676; RM0410, pg1912) - // STM32L1 (RM0038, pg861) - // STM32L4 (RM0351, pg1840; RM0394, pg1560) - // STM32G4 (RM0440, pg2086) - // STM32WB (RM0434, pg1406) - ret = stlink_read_debug32(sl, 0xE0042000, chip_id); - } - - if (ret || !(*chip_id)) { - *chip_id = 0; - ret = ret?ret:-1; - ELOG("Could not find chip id!\n"); - } else { - *chip_id = (*chip_id) & 0xfff; - - // Fix chip_id for F4 rev A errata, read CPU ID, as CoreID is the same for - // F2/F4 - if (*chip_id == 0x411 && cpu_id.part == STLINK_REG_CMx_CPUID_PARTNO_CM4) { - *chip_id = 0x413; - } - } - - return (ret); -} - -/** - * Cortex M tech ref manual, CPUID register description - * @param sl stlink context - * @param cpuid pointer to the result object - */ -int stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid) { - uint32_t raw; - - if (stlink_read_debug32(sl, STLINK_REG_CM3_CPUID, &raw)) { - cpuid->implementer_id = 0; - cpuid->variant = 0; - cpuid->part = 0; - cpuid->revision = 0; - return (-1); - } - - cpuid->implementer_id = (raw >> 24) & 0x7f; - cpuid->variant = (raw >> 20) & 0xf; - cpuid->part = (raw >> 4) & 0xfff; - cpuid->revision = raw & 0xf; - return (0); -} - -/** - * Reads and decodes the flash parameters, as dynamically as possible - * @param sl - * @return 0 for success, or -1 for unsupported core type. - */ -int stlink_load_device_params(stlink_t *sl) { - // This seems to normally work so is unnecessary info for a normal user. - // Demoted to debug. -- REW - DLOG("Loading device parameters....\n"); - const struct stlink_chipid_params *params = NULL; - stlink_core_id(sl); - uint32_t flash_size; - - if (stlink_chip_id(sl, &sl->chip_id)) { - return (-1); - } - - params = stlink_chipid_get_params(sl->chip_id); - - if (params == NULL) { - WLOG("unknown chip id! %#x\n", sl->chip_id); - return (-1); - } - - if (params->flash_type == STM32_FLASH_TYPE_UNKNOWN) { - WLOG("Invalid flash type, please check device declaration\n"); - sl->flash_size = 0; - return (0); - } - - // These are fixed... - sl->flash_base = STM32_FLASH_BASE; - sl->sram_base = STM32_SRAM_BASE; - stlink_read_debug32(sl, (params->flash_size_reg) & ~3, &flash_size); - - if (params->flash_size_reg & 2) { - flash_size = flash_size >> 16; - } - - flash_size = flash_size & 0xffff; - - if ((sl->chip_id == STM32_CHIPID_L1_MD || - sl->chip_id == STM32_CHIPID_F1_VL_MD_LD || - sl->chip_id == STM32_CHIPID_L1_MD_PLUS) && - (flash_size == 0)) { - sl->flash_size = 128 * 1024; - } else if (sl->chip_id == STM32_CHIPID_L1_CAT2) { - sl->flash_size = (flash_size & 0xff) * 1024; - } else if ((sl->chip_id & 0xFFF) == STM32_CHIPID_L1_MD_PLUS_HD) { - // 0 is 384k and 1 is 256k - if (flash_size == 0) { - sl->flash_size = 384 * 1024; - } else { - sl->flash_size = 256 * 1024; - } - } else { - sl->flash_size = flash_size * 1024; - } - - sl->flash_type = params->flash_type; - sl->flash_pgsz = params->flash_pagesize; - sl->sram_size = params->sram_size; - sl->sys_base = params->bootrom_base; - sl->sys_size = params->bootrom_size; - sl->option_base = params->option_base; - sl->option_size = params->option_size; - sl->chip_flags = params->flags; - - // medium and low devices have the same chipid. ram size depends on flash - // size. STM32F100xx datasheet Doc ID 16455 Table 2 - if (sl->chip_id == STM32_CHIPID_F1_VL_MD_LD && - sl->flash_size < 64 * 1024) { - sl->sram_size = 0x1000; - } - - if (sl->chip_id == STM32_CHIPID_G4_CAT3) { - uint32_t flash_optr; - stlink_read_debug32(sl, STM32Gx_FLASH_OPTR, &flash_optr); - - if (!(flash_optr & (1 << STM32G4_FLASH_OPTR_DBANK))) { - sl->flash_pgsz <<= 1; - } - } - - // H7 devices with small flash has one bank - if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK && - sl->flash_type == STM32_FLASH_TYPE_H7) { - if ((sl->flash_size / sl->flash_pgsz) <= 1) - sl->chip_flags &= ~CHIP_F_HAS_DUAL_BANK; - } - - ILOG("%s: %u KiB SRAM, %u KiB flash in at least %u %s pages.\n", - params->dev_type, (unsigned)(sl->sram_size / 1024), - (unsigned)(sl->flash_size / 1024), - (sl->flash_pgsz < 1024) ? (unsigned)(sl->flash_pgsz) - : (unsigned)(sl->flash_pgsz / 1024), - (sl->flash_pgsz < 1024) ? "byte" : "KiB"); - - return (0); -} - -int stlink_jtag_reset(stlink_t *sl, int value) { - DLOG("*** stlink_jtag_reset %d ***\n", value); - return (sl->backend->jtag_reset(sl, value)); -} - -int stlink_soft_reset(stlink_t *sl, int halt_on_reset) { - int ret; - unsigned timeout; - uint32_t dhcsr, dfsr; - - DLOG("*** stlink_soft_reset %s***\n", halt_on_reset ? "(halt) " : ""); - - // halt core and enable debugging (if not already done) - // C_DEBUGEN is required to Halt on reset (DDI0337E, p. 10-6) - stlink_write_debug32(sl, STLINK_REG_DHCSR, - STLINK_REG_DHCSR_DBGKEY | STLINK_REG_DHCSR_C_HALT | - STLINK_REG_DHCSR_C_DEBUGEN); - - // enable Halt on reset by set VC_CORERESET and TRCENA (DDI0337E, p. 10-10) - if (halt_on_reset) { - stlink_write_debug32( - sl, STLINK_REG_CM3_DEMCR, - STLINK_REG_CM3_DEMCR_TRCENA | STLINK_REG_CM3_DEMCR_VC_HARDERR | - STLINK_REG_CM3_DEMCR_VC_BUSERR | STLINK_REG_CM3_DEMCR_VC_CORERESET); - - // clear VCATCH in the DFSR register - stlink_write_debug32(sl, STLINK_REG_DFSR, STLINK_REG_DFSR_VCATCH); - } else { - stlink_write_debug32(sl, STLINK_REG_CM3_DEMCR, - STLINK_REG_CM3_DEMCR_TRCENA | - STLINK_REG_CM3_DEMCR_VC_HARDERR | - STLINK_REG_CM3_DEMCR_VC_BUSERR); - } - - // clear S_RESET_ST in the DHCSR register - stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); - - // soft reset (core reset) by SYSRESETREQ (DDI0337E, p. 8-23) - ret = stlink_write_debug32(sl, STLINK_REG_AIRCR, - STLINK_REG_AIRCR_VECTKEY | - STLINK_REG_AIRCR_SYSRESETREQ); - if (ret) { - ELOG("Soft reset failed: error write to AIRCR\n"); - return (ret); - } - - // waiting for a reset within 500ms - // DDI0337E, p. 10-4, Debug Halting Control and Status Register - timeout = time_ms() + 500; - while (time_ms() < timeout) { - // DDI0337E, p. 10-4, Debug Halting Control and Status Register - dhcsr = STLINK_REG_DHCSR_S_RESET_ST; - stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); - if ((dhcsr & STLINK_REG_DHCSR_S_RESET_ST) == 0) { - if (halt_on_reset) { - // waiting halt by the SYSRESETREQ exception - // DDI0403E, p. C1-699, Debug Fault Status Register - dfsr = 0; - stlink_read_debug32(sl, STLINK_REG_DFSR, &dfsr); - if ((dfsr & STLINK_REG_DFSR_VCATCH) == 0) { - continue; - } - } - timeout = 0; - break; - } - } - - // reset DFSR register. DFSR is power-on reset only (DDI0337H, p. 7-5) - stlink_write_debug32(sl, STLINK_REG_DFSR, STLINK_REG_DFSR_CLEAR); - - if (timeout) { - ELOG("Soft reset failed: timeout\n"); - return (-1); - } - - return (0); -} - -int stlink_reset(stlink_t *sl, enum reset_type type) { - uint32_t dhcsr; - unsigned timeout; - - DLOG("*** stlink_reset ***\n"); - - sl->core_stat = TARGET_RESET; - - if (type == RESET_AUTO) { - // clear S_RESET_ST in DHCSR register for reset state detection - stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); - } - - if (type == RESET_HARD || type == RESET_AUTO) { - // hardware target reset - if (sl->version.stlink_v > 1) { - stlink_jtag_reset(sl, STLINK_DEBUG_APIV2_DRIVE_NRST_LOW); - // minimum reset pulse duration of 20 us (RM0008, 8.1.2 Power reset) - usleep(100); - stlink_jtag_reset(sl, STLINK_DEBUG_APIV2_DRIVE_NRST_HIGH); - } - sl->backend->reset(sl); - usleep(10000); - } - - if (type == RESET_AUTO) { - /* Check if the S_RESET_ST bit is set in DHCSR - * This means that a reset has occurred - * DDI0337E, p. 10-4, Debug Halting Control and Status Register */ - - dhcsr = 0; - int res = stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); - if ((dhcsr & STLINK_REG_DHCSR_S_RESET_ST) == 0 && !res) { - // reset not done yet - // try reset through AIRCR so that NRST does not need to be connected - - WLOG("NRST is not connected\n"); - DLOG("Using reset through SYSRESETREQ\n"); - return stlink_soft_reset(sl, 0); - } - - // waiting for reset the S_RESET_ST bit within 500ms - timeout = time_ms() + 500; - while (time_ms() < timeout) { - dhcsr = STLINK_REG_DHCSR_S_RESET_ST; - stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); - if ((dhcsr & STLINK_REG_DHCSR_S_RESET_ST) == 0) { - return (0); - } - } - - return (-1); - } - - if (type == RESET_SOFT || type == RESET_SOFT_AND_HALT) { - return stlink_soft_reset(sl, (type == RESET_SOFT_AND_HALT)); - } - - return (0); -} - -int stlink_run(stlink_t *sl, enum run_type type) { - struct stlink_reg rr; - DLOG("*** stlink_run ***\n"); - - /* Make sure we are in Thumb mode - * Cortex-M chips don't support ARM mode instructions - * xPSR may be incorrect if the vector table has invalid data */ - stlink_read_reg(sl, 16, &rr); - if ((rr.xpsr & (1 << 24)) == 0) { - ILOG("Go to Thumb mode\n"); - stlink_write_reg(sl, rr.xpsr | (1 << 24), 16); - } - - return (sl->backend->run(sl, type)); -} - -int stlink_set_swdclk(stlink_t *sl, int freq_khz) { - DLOG("*** set_swdclk ***\n"); - return (sl->backend->set_swdclk(sl, freq_khz)); -} - -int stlink_status(stlink_t *sl) { - int ret; - - DLOG("*** stlink_status ***\n"); - ret = sl->backend->status(sl); - stlink_core_stat(sl); - return (ret); -} - -/** - * Decode the version bits, originally from -sg, verified with usb - * @param sl stlink context, assumed to contain valid data in the buffer - * @param slv output parsed version object - */ -void _parse_version(stlink_t *sl, stlink_version_t *slv) { - sl->version.flags = 0; - - if (sl->version.stlink_v < 3) { - uint32_t b0 = sl->q_buf[0]; // lsb - uint32_t b1 = sl->q_buf[1]; - uint32_t b2 = sl->q_buf[2]; - uint32_t b3 = sl->q_buf[3]; - uint32_t b4 = sl->q_buf[4]; - uint32_t b5 = sl->q_buf[5]; // msb - - // b0 b1 || b2 b3 | b4 b5 - // 4b | 6b | 6b || 2B | 2B - // stlink_v | jtag_v | swim_v || st_vid | stlink_pid - - slv->stlink_v = (b0 & 0xf0) >> 4; - slv->jtag_v = ((b0 & 0x0f) << 2) | ((b1 & 0xc0) >> 6); - slv->swim_v = b1 & 0x3f; - slv->st_vid = (b3 << 8) | b2; - slv->stlink_pid = (b5 << 8) | b4; - - // ST-LINK/V1 from J11 switch to api-v2 (and support SWD) - if (slv->stlink_v == 1) { - slv->jtag_api = - slv->jtag_v > 11 ? STLINK_JTAG_API_V2 : STLINK_JTAG_API_V1; - } else { - slv->jtag_api = STLINK_JTAG_API_V2; - - // preferred API to get last R/W status from J15 - if (sl->version.jtag_v >= 15) { - sl->version.flags |= STLINK_F_HAS_GETLASTRWSTATUS2; - } - - if (sl->version.jtag_v >= 13) { - sl->version.flags |= STLINK_F_HAS_TRACE; - sl->max_trace_freq = STLINK_V2_MAX_TRACE_FREQUENCY; - } - } - } else { - // V3 uses different version format, for reference see OpenOCD source - // (that was written from docs available from ST under NDA): - // https://github.com/ntfreak/openocd/blob/a6dacdff58ef36fcdac00c53ec27f19de1fbce0d/src/jtag/drivers/stlink_usb.c#L965 - slv->stlink_v = sl->q_buf[0]; - slv->swim_v = sl->q_buf[1]; - slv->jtag_v = sl->q_buf[2]; - slv->st_vid = (uint32_t)((sl->q_buf[9] << 8) | sl->q_buf[8]); - slv->stlink_pid = (uint32_t)((sl->q_buf[11] << 8) | sl->q_buf[10]); - slv->jtag_api = STLINK_JTAG_API_V3; - /* preferred API to get last R/W status */ - sl->version.flags |= STLINK_F_HAS_GETLASTRWSTATUS2; - sl->version.flags |= STLINK_F_HAS_TRACE; - sl->max_trace_freq = STLINK_V3_MAX_TRACE_FREQUENCY; - } - - return; -} - -int stlink_version(stlink_t *sl) { - DLOG("*** looking up stlink version\n"); - - if (sl->backend->version(sl)) { - return (-1); - } - - _parse_version(sl, &sl->version); - - DLOG("st vid = 0x%04x (expect 0x%04x)\n", sl->version.st_vid, - STLINK_USB_VID_ST); - DLOG("stlink pid = 0x%04x\n", sl->version.stlink_pid); - DLOG("stlink version = 0x%x\n", sl->version.stlink_v); - DLOG("jtag version = 0x%x\n", sl->version.jtag_v); - DLOG("swim version = 0x%x\n", sl->version.swim_v); - - if (sl->version.jtag_v == 0) { - WLOG(" warning: stlink doesn't support JTAG/SWD interface\n"); - } - - return (0); -} - -int stlink_target_voltage(stlink_t *sl) { - int voltage = -1; - DLOG("*** reading target voltage\n"); - - if (sl->backend->target_voltage != NULL) { - voltage = sl->backend->target_voltage(sl); - - if (voltage != -1) { - DLOG("target voltage = %imV\n", voltage); - } else { - DLOG("error reading target voltage\n"); - } - } else { - DLOG("reading voltage not supported by backend\n"); - } - - return (voltage); -} - -int stlink_read_debug32(stlink_t *sl, uint32_t addr, uint32_t *data) { - int ret; - - ret = sl->backend->read_debug32(sl, addr, data); - if (!ret) - DLOG("*** stlink_read_debug32 %#010x at %#010x\n", *data, addr); - - return (ret); -} - -int stlink_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data) { - DLOG("*** stlink_write_debug32 %#010x to %#010x\n", data, addr); - return sl->backend->write_debug32(sl, addr, data); -} - -int stlink_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { - DLOG("*** stlink_write_mem32 %u bytes to %#x\n", len, addr); - - if (len % 4 != 0) { - ELOG("Data length doesn't have a 32 bit alignment: +%d byte.\n", len % 4); - return (-1); - } - - return (sl->backend->write_mem32(sl, addr, len)); -} - -int stlink_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { - DLOG("*** stlink_read_mem32 ***\n"); - - if (len % 4 != 0) { // !!! never ever: fw gives just wrong values - ELOG("Data length doesn't have a 32 bit alignment: +%d byte.\n", len % 4); - return (-1); - } - - return (sl->backend->read_mem32(sl, addr, len)); -} - -int stlink_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len) { - DLOG("*** stlink_write_mem8 ***\n"); - return (sl->backend->write_mem8(sl, addr, len)); -} - -int stlink_read_all_regs(stlink_t *sl, struct stlink_reg *regp) { - DLOG("*** stlink_read_all_regs ***\n"); - return (sl->backend->read_all_regs(sl, regp)); -} - -int stlink_read_all_unsupported_regs(stlink_t *sl, struct stlink_reg *regp) { - DLOG("*** stlink_read_all_unsupported_regs ***\n"); - return (sl->backend->read_all_unsupported_regs(sl, regp)); -} - -int stlink_write_reg(stlink_t *sl, uint32_t reg, int idx) { - DLOG("*** stlink_write_reg\n"); - return (sl->backend->write_reg(sl, reg, idx)); -} - -int stlink_read_reg(stlink_t *sl, int r_idx, struct stlink_reg *regp) { - DLOG("*** stlink_read_reg\n"); - DLOG(" (%d) ***\n", r_idx); - - if (r_idx > 20 || r_idx < 0) { - fprintf(stderr, "Error: register index must be in [0..20]\n"); - return (-1); - } - - return (sl->backend->read_reg(sl, r_idx, regp)); -} - -int stlink_read_unsupported_reg(stlink_t *sl, int r_idx, - struct stlink_reg *regp) { - int r_convert; - - DLOG("*** stlink_read_unsupported_reg\n"); - DLOG(" (%d) ***\n", r_idx); - - /* Convert to values used by STLINK_REG_DCRSR */ - if (r_idx >= 0x1C && - r_idx <= 0x1F) { // primask, basepri, faultmask, or control - r_convert = 0x14; - } else if (r_idx == 0x40) { // FPSCR - r_convert = 0x21; - } else if (r_idx >= 0x20 && r_idx < 0x40) { - r_convert = 0x40 + (r_idx - 0x20); - } else { - fprintf(stderr, "Error: register address must be in [0x1C..0x40]\n"); - return (-1); - } - - return (sl->backend->read_unsupported_reg(sl, r_convert, regp)); -} - -int stlink_write_unsupported_reg(stlink_t *sl, uint32_t val, int r_idx, - struct stlink_reg *regp) { - int r_convert; - - DLOG("*** stlink_write_unsupported_reg\n"); - DLOG(" (%d) ***\n", r_idx); - - /* Convert to values used by STLINK_REG_DCRSR */ - if (r_idx >= 0x1C && - r_idx <= 0x1F) { /* primask, basepri, faultmask, or control */ - r_convert = r_idx; // the backend function handles this - } else if (r_idx == 0x40) { // FPSCR - r_convert = 0x21; - } else if (r_idx >= 0x20 && r_idx < 0x40) { - r_convert = 0x40 + (r_idx - 0x20); - } else { - fprintf(stderr, "Error: register address must be in [0x1C..0x40]\n"); - return (-1); - } - - return (sl->backend->write_unsupported_reg(sl, val, r_convert, regp)); -} - -bool stlink_is_core_halted(stlink_t *sl) { - stlink_status(sl); - return (sl->core_stat == TARGET_HALTED); -} - -int stlink_step(stlink_t *sl) { - DLOG("*** stlink_step ***\n"); - return (sl->backend->step(sl)); -} - -int stlink_current_mode(stlink_t *sl) { - int mode = sl->backend->current_mode(sl); - - switch (mode) { - case STLINK_DEV_DFU_MODE: - DLOG("stlink current mode: dfu\n"); - return (mode); - case STLINK_DEV_DEBUG_MODE: - DLOG("stlink current mode: debug (jtag or swd)\n"); - return (mode); - case STLINK_DEV_MASS_MODE: - DLOG("stlink current mode: mass\n"); - return (mode); - } - - DLOG("stlink mode: unknown!\n"); - return (STLINK_DEV_UNKNOWN_MODE); -} - -int stlink_trace_enable(stlink_t *sl, uint32_t frequency) { - DLOG("*** stlink_trace_enable ***\n"); - return (sl->backend->trace_enable(sl, frequency)); -} - -int stlink_trace_disable(stlink_t *sl) { - DLOG("*** stlink_trace_disable ***\n"); - return (sl->backend->trace_disable(sl)); -} - -int stlink_trace_read(stlink_t *sl, uint8_t *buf, size_t size) { - return (sl->backend->trace_read(sl, buf, size)); -} - -// End of delegates.... Common code below here... - -// same as above with entrypoint. - -void stlink_run_at(stlink_t *sl, stm32_addr_t addr) { - stlink_write_reg(sl, addr, 15); /* pc register */ - stlink_run(sl, RUN_NORMAL); - - while (stlink_is_core_halted(sl)) { - usleep(3000000); - } -} - -// this function is called by stlink_status() -// do not call stlink_core_stat() directly, always use stlink_status() -void stlink_core_stat(stlink_t *sl) { - switch (sl->core_stat) { - case TARGET_RUNNING: - DLOG(" core status: running\n"); - return; - case TARGET_HALTED: - DLOG(" core status: halted\n"); - return; - case TARGET_RESET: - DLOG(" core status: reset\n"); - return; - case TARGET_DEBUG_RUNNING: - DLOG(" core status: debug running\n"); - return; - default: - DLOG(" core status: unknown\n"); - } -} - -void stlink_print_data(stlink_t *sl) { - if (sl->q_len <= 0 || sl->verbose < UDEBUG) { - return; - } - - if (sl->verbose > 2) { - DLOG("data_len = %d 0x%x\n", sl->q_len, sl->q_len); - } - - for (int i = 0; i < sl->q_len; i++) { - if (i % 16 == 0) { - /* - if (sl->q_data_dir == Q_DATA_OUT) { - fprintf(stdout, "\n<- 0x%08x ", sl->q_addr + i); - } else { - fprintf(stdout, "\n-> 0x%08x ", sl->q_addr + i); - } - */ - } - // DLOG(" %02x", (unsigned int) sl->q_buf[i]); - fprintf(stderr, " %02x", (unsigned int)sl->q_buf[i]); - } - // DLOG("\n\n"); - fprintf(stderr, "\n"); -} - -/* Memory mapped file */ -typedef struct mapped_file { - uint8_t *base; - size_t len; -} mapped_file_t; - -#define MAPPED_FILE_INITIALIZER \ - { NULL, 0 } - -static int map_file(mapped_file_t *mf, const char *path) { - int error = -1; - struct stat st; - - const int fd = open(path, O_RDONLY | O_BINARY); - - if (fd == -1) { - fprintf(stderr, "open(%s) == -1\n", path); - return (-1); - } - - if (fstat(fd, &st) == -1) { - fprintf(stderr, "fstat(%s) == -1\n", path); - goto on_error; - } - - if (sizeof(st.st_size) != sizeof(size_t)) { - // on 32 bit systems, check if there is an overflow - if (st.st_size > (off_t)SSIZE_MAX) { - fprintf(stderr, "mmap() size_t overflow for file %s\n", path); - goto on_error; - } - } - - mf->base = - (uint8_t *)mmap(NULL, (size_t)(st.st_size), PROT_READ, MAP_SHARED, fd, 0); - - if (mf->base == MAP_FAILED) { - fprintf(stderr, "mmap() == MAP_FAILED for file %s\n", path); - goto on_error; - } - - mf->len = (size_t)st.st_size; - error = 0; // success - -on_error: - close(fd); - return (error); -} - -static void unmap_file(mapped_file_t *mf) { - munmap((void *)mf->base, mf->len); - mf->base = (unsigned char *)MAP_FAILED; - mf->len = 0; -} - -/* Limit the block size to compare to 0x1800 as anything larger will stall the - * STLINK2 Maybe STLINK V1 needs smaller value! - */ -static int check_file(stlink_t *sl, mapped_file_t *mf, stm32_addr_t addr) { - size_t off; - size_t n_cmp = sl->flash_pgsz; - - if (n_cmp > 0x1800) { - n_cmp = 0x1800; - } - - for (off = 0; off < mf->len; off += n_cmp) { - size_t aligned_size; - - size_t cmp_size = n_cmp; // adjust last page size - - if ((off + n_cmp) > mf->len) { - cmp_size = mf->len - off; - } - - aligned_size = cmp_size; - - if (aligned_size & (4 - 1)) { - aligned_size = (cmp_size + 4) & ~(4 - 1); - } - - stlink_read_mem32(sl, addr + (uint32_t)off, (uint16_t)aligned_size); - - if (memcmp(sl->q_buf, mf->base + off, cmp_size)) { - return (-1); - } - } - - return (0); -} - -static void md5_calculate(mapped_file_t *mf) { - // calculate md5 checksum of given binary file - Md5Context md5Context; - MD5_HASH md5Hash; - Md5Initialise(&md5Context); - Md5Update(&md5Context, mf->base, (uint32_t)mf->len); - Md5Finalise(&md5Context, &md5Hash); - printf("md5 checksum: "); - - for (int i = 0; i < (int)sizeof(md5Hash); i++) { - printf("%x", md5Hash.bytes[i]); - } - - printf(", "); -} - -static void stlink_checksum(mapped_file_t *mp) { - /* checksum that backward compatible with official ST tools */ - uint32_t sum = 0; - uint8_t *mp_byte = (uint8_t *)mp->base; - - for (size_t i = 0; i < mp->len; ++i) { - sum += mp_byte[i]; - } - - printf("stlink checksum: 0x%08x\n", sum); -} - -static void stlink_fwrite_finalize(stlink_t *sl, stm32_addr_t addr) { - unsigned int val; - // set PC to the reset routine - stlink_read_debug32(sl, addr + 4, &val); - stlink_write_reg(sl, val, 15); - stlink_run(sl, RUN_NORMAL); -} - -int stlink_mwrite_sram(stlink_t *sl, uint8_t *data, uint32_t length, - stm32_addr_t addr) { - // write the file in sram at addr - - int error = -1; - size_t off; - size_t len; - - // check addr range is inside the sram - if (addr < sl->sram_base) { - fprintf(stderr, "addr too low\n"); - goto on_error; - } else if ((addr + length) < addr) { - fprintf(stderr, "addr overruns\n"); - goto on_error; - } else if ((addr + length) > (sl->sram_base + sl->sram_size)) { - fprintf(stderr, "addr too high\n"); - goto on_error; - } else if (addr & 3) { - fprintf(stderr, "unaligned addr\n"); - goto on_error; - } - - len = length; - - if (len & 3) { - len -= len & 3; - } - - // do the copy by 1kB blocks - for (off = 0; off < len; off += 1024) { - size_t size = 1024; - - if ((off + size) > len) { - size = len - off; - } - - memcpy(sl->q_buf, data + off, size); - - if (size & 3) { - size += 2; - } // round size if needed - - stlink_write_mem32(sl, addr + (uint32_t)off, (uint16_t)size); - } - - if (length > len) { - memcpy(sl->q_buf, data + len, length - len); - stlink_write_mem8(sl, addr + (uint32_t)len, (uint16_t)(length - len)); - } - - error = 0; // success - stlink_fwrite_finalize(sl, addr); - -on_error: - return (error); -} - -int stlink_fwrite_sram(stlink_t *sl, const char *path, stm32_addr_t addr) { - // write the file in sram at addr - - int error = -1; - size_t off; - size_t len; - mapped_file_t mf = MAPPED_FILE_INITIALIZER; - - if (map_file(&mf, path) == -1) { - fprintf(stderr, "map_file() == -1\n"); - return (-1); - } - - printf("file %s ", path); - md5_calculate(&mf); - stlink_checksum(&mf); - - // check if addr range is inside the SRAM - if (addr < sl->sram_base) { - fprintf(stderr, "addr too low\n"); - goto on_error; - } else if ((addr + mf.len) < addr) { - fprintf(stderr, "addr overruns\n"); - goto on_error; - } else if ((addr + mf.len) > (sl->sram_base + sl->sram_size)) { - fprintf(stderr, "addr too high\n"); - goto on_error; - } else if (addr & 3) { - fprintf(stderr, "unaligned addr\n"); - goto on_error; - } - - len = mf.len; - - if (len & 3) { - len -= len & 3; - } - - // do the copy by 1kB blocks - for (off = 0; off < len; off += 1024) { - size_t size = 1024; - - if ((off + size) > len) { - size = len - off; - } - - memcpy(sl->q_buf, mf.base + off, size); - - if (size & 3) { - size += 2; - } // round size if needed - - stlink_write_mem32(sl, addr + (uint32_t)off, (uint16_t)size); - } - - if (mf.len > len) { - memcpy(sl->q_buf, mf.base + len, mf.len - len); - stlink_write_mem8(sl, addr + (uint32_t)len, (uint16_t)(mf.len - len)); - } - - // check the file has been written - if (check_file(sl, &mf, addr) == -1) { - fprintf(stderr, "check_file() == -1\n"); - goto on_error; - } - - error = 0; // success - stlink_fwrite_finalize(sl, addr); - -on_error: - unmap_file(&mf); - return (error); -} - -typedef bool (*save_block_fn)(void *arg, uint8_t *block, ssize_t len); - -static int stlink_read(stlink_t *sl, stm32_addr_t addr, size_t size, - save_block_fn fn, void *fn_arg) { - - int error = -1; - - if (size < 1) { - size = sl->flash_size; - } - - if (size > sl->flash_size) { - size = sl->flash_size; - } - - size_t cmp_size = (sl->flash_pgsz > 0x1800) ? 0x1800 : sl->flash_pgsz; - - for (size_t off = 0; off < size; off += cmp_size) { - size_t aligned_size; - - // adjust last page size - if ((off + cmp_size) > size) { - cmp_size = size - off; - } - - aligned_size = cmp_size; - - if (aligned_size & (4 - 1)) { - aligned_size = (cmp_size + 4) & ~(4 - 1); - } - - stlink_read_mem32(sl, addr + (uint32_t)off, (uint16_t)aligned_size); - - if (!fn(fn_arg, sl->q_buf, aligned_size)) { - goto on_error; - } - } - - error = 0; // success - -on_error: - return (error); -} - -struct stlink_fread_worker_arg { - int fd; -}; - -static bool stlink_fread_worker(void *arg, uint8_t *block, ssize_t len) { - struct stlink_fread_worker_arg *the_arg = - (struct stlink_fread_worker_arg *)arg; - - if (write(the_arg->fd, block, len) != len) { - fprintf(stderr, "write() != aligned_size\n"); - return (false); - } else { - return (true); - } -} - -struct stlink_fread_ihex_worker_arg { - FILE *file; - uint32_t addr; - uint32_t lba; - uint8_t buf[16]; - uint8_t buf_pos; -}; - -static bool -stlink_fread_ihex_newsegment(struct stlink_fread_ihex_worker_arg *the_arg) { - uint32_t addr = the_arg->addr; - uint8_t sum = 2 + 4 + (uint8_t)((addr & 0xFF000000) >> 24) + - (uint8_t)((addr & 0x00FF0000) >> 16); - - if (17 != fprintf(the_arg->file, ":02000004%04X%02X\r\n", - (addr & 0xFFFF0000) >> 16, (uint8_t)(0x100 - sum))) { - return (false); - } - - the_arg->lba = (addr & 0xFFFF0000); - return (true); -} - -static bool -stlink_fread_ihex_writeline(struct stlink_fread_ihex_worker_arg *the_arg) { - uint8_t count = the_arg->buf_pos; - - if (count == 0) { - return (true); - } - - uint32_t addr = the_arg->addr; - - if (the_arg->lba != (addr & 0xFFFF0000)) { // segment changed - if (!stlink_fread_ihex_newsegment(the_arg)) { - return (false); - } - } - - uint8_t sum = count + (uint8_t)((addr & 0x0000FF00) >> 8) + - (uint8_t)(addr & 0x000000FF); - - if (9 != fprintf(the_arg->file, ":%02X%04X00", count, (addr & 0x0000FFFF))) { - return (false); - } - - for (uint8_t i = 0; i < count; ++i) { - uint8_t b = the_arg->buf[i]; - sum += b; - - if (2 != fprintf(the_arg->file, "%02X", b)) { - return (false); - } - } - - if (4 != fprintf(the_arg->file, "%02X\r\n", (uint8_t)(0x100 - sum))) { - return (false); - } - - the_arg->addr += count; - the_arg->buf_pos = 0; - - return (true); -} - -static bool stlink_fread_ihex_init(struct stlink_fread_ihex_worker_arg *the_arg, - int fd, stm32_addr_t addr) { - the_arg->file = fdopen(fd, "w"); - the_arg->addr = addr; - the_arg->lba = 0; - the_arg->buf_pos = 0; - - return (the_arg->file != NULL); -} - -static bool stlink_fread_ihex_worker(void *arg, uint8_t *block, ssize_t len) { - struct stlink_fread_ihex_worker_arg *the_arg = - (struct stlink_fread_ihex_worker_arg *)arg; - - for (ssize_t i = 0; i < len; ++i) { - if (the_arg->buf_pos == sizeof(the_arg->buf)) { // line is full - if (!stlink_fread_ihex_writeline(the_arg)) { - return (false); - } - } - - the_arg->buf[the_arg->buf_pos++] = block[i]; - } - - return (true); -} - -static bool -stlink_fread_ihex_finalize(struct stlink_fread_ihex_worker_arg *the_arg) { - if (!stlink_fread_ihex_writeline(the_arg)) { - return (false); - } - - // FIXME: do we need the Start Linear Address? - - if (13 != fprintf(the_arg->file, ":00000001FF\r\n")) { // EoF - return (false); - } - - return (0 == fclose(the_arg->file)); -} - -int stlink_fread(stlink_t *sl, const char *path, bool is_ihex, - stm32_addr_t addr, size_t size) { - // read size bytes from addr to file - ILOG("read from address %#010x size %u\n", addr, (unsigned)size); - - int error; - int fd = open(path, O_RDWR | O_TRUNC | O_CREAT | O_BINARY, 00700); - - if (fd == -1) { - fprintf(stderr, "open(%s) == -1\n", path); - return (-1); - } - - if (is_ihex) { - struct stlink_fread_ihex_worker_arg arg; - - if (stlink_fread_ihex_init(&arg, fd, addr)) { - error = stlink_read(sl, addr, size, &stlink_fread_ihex_worker, &arg); - - if (!stlink_fread_ihex_finalize(&arg)) { - error = -1; - } - } else { - error = -1; - } - } else { - struct stlink_fread_worker_arg arg = {fd}; - error = stlink_read(sl, addr, size, &stlink_fread_worker, &arg); - } - - close(fd); - return (error); -} - -int write_buffer_to_sram(stlink_t *sl, flash_loader_t *fl, const uint8_t *buf, - size_t size) { - // write the buffer right after the loader - int ret = 0; - size_t chunk = size & ~0x3; - size_t rem = size & 0x3; - - if (chunk) { - memcpy(sl->q_buf, buf, chunk); - ret = stlink_write_mem32(sl, fl->buf_addr, (uint16_t)chunk); - } - - if (rem && !ret) { - memcpy(sl->q_buf, buf + chunk, rem); - ret = stlink_write_mem8(sl, (fl->buf_addr) + (uint32_t)chunk, (uint16_t)rem); - } - - return (ret); -} - -uint32_t calculate_F4_sectornum(uint32_t flashaddr) { - uint32_t offset = 0; - flashaddr &= ~STM32_FLASH_BASE; // page now holding the actual flash address - - if (flashaddr >= 0x100000) { - offset = 12; - flashaddr -= 0x100000; - } - - if (flashaddr < 0x4000) { - return (offset + 0); - } else if (flashaddr < 0x8000) { - return (offset + 1); - } else if (flashaddr < 0xc000) { - return (offset + 2); - } else if (flashaddr < 0x10000) { - return (offset + 3); - } else if (flashaddr < 0x20000) { - return (offset + 4); - } else { - return (offset + (flashaddr / 0x20000) + 4); - } -} - -uint32_t calculate_F7_sectornum(uint32_t flashaddr) { - flashaddr &= ~STM32_FLASH_BASE; // Page now holding the actual flash address - - if (flashaddr < 0x20000) { - return (flashaddr / 0x8000); - } else if (flashaddr < 0x40000) { - return (4); - } else { - return ((flashaddr / 0x40000) + 4); - } -} - -uint32_t calculate_H7_sectornum(stlink_t *sl, uint32_t flashaddr, - unsigned bank) { - flashaddr &= - ~((bank == BANK_1) - ? STM32_FLASH_BASE - : STM32_H7_FLASH_BANK2_BASE); // sector holding the flash address - return (flashaddr / sl->flash_pgsz); -} - -// returns BKER:PNB for the given page address -uint32_t calculate_L4_page(stlink_t *sl, uint32_t flashaddr) { - uint32_t bker = 0; - uint32_t flashopt; - stlink_read_debug32(sl, STM32L4_FLASH_OPTR, &flashopt); - flashaddr -= STM32_FLASH_BASE; - - if (sl->chip_id == STM32_CHIPID_L4 || - sl->chip_id == STM32_CHIPID_L496x_L4A6x || - sl->chip_id == STM32_CHIPID_L4Rx) { - // this chip use dual banked flash - if (flashopt & (uint32_t)(1lu << STM32L4_FLASH_OPTR_DUALBANK)) { - uint32_t banksize = (uint32_t)sl->flash_size / 2; - - if (flashaddr >= banksize) { - flashaddr -= banksize; - bker = 0x100; - } - } - } - - // For 1MB chips without the dual-bank option set, the page address will - // overflow into the BKER bit, which gives us the correct bank:page value. - return (bker | flashaddr / (uint32_t)sl->flash_pgsz); -} - -uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr) { - if ((sl->chip_id == STM32_CHIPID_F2) || - (sl->chip_id == STM32_CHIPID_F4) || - (sl->chip_id == STM32_CHIPID_F4_DE) || - (sl->chip_id == STM32_CHIPID_F4_LP) || - (sl->chip_id == STM32_CHIPID_F4_HD) || - (sl->chip_id == STM32_CHIPID_F411xx) || - (sl->chip_id == STM32_CHIPID_F446) || - (sl->chip_id == STM32_CHIPID_F4_DSI) || - (sl->chip_id == STM32_CHIPID_F72xxx) || - (sl->chip_id == STM32_CHIPID_F412)) { - uint32_t sector = calculate_F4_sectornum(flashaddr); - - if (sector >= 12) { - sector -= 12; - } - - if (sector < 4) { - sl->flash_pgsz = 0x4000; - } else if (sector < 5) { - sl->flash_pgsz = 0x10000; - } else { - sl->flash_pgsz = 0x20000; - } - } else if (sl->chip_id == STM32_CHIPID_F7 || - sl->chip_id == STM32_CHIPID_F76xxx) { - uint32_t sector = calculate_F7_sectornum(flashaddr); - - if (sector < 4) { - sl->flash_pgsz = 0x8000; - } else if (sector < 5) { - sl->flash_pgsz = 0x20000; - } else { - sl->flash_pgsz = 0x40000; - } - } - - return ((uint32_t)sl->flash_pgsz); -} - -/** - * Erase a page of flash, assumes sl is fully populated with things like - * chip/core ids - * @param sl stlink context - * @param flashaddr an address in the flash page to erase - * @return 0 on success -ve on failure - */ -int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { - // wait for ongoing op to finish - wait_flash_busy(sl); - // clear flash IO errors - clear_flash_error(sl); - - if (sl->flash_type == STM32_FLASH_TYPE_F2_F4 || - sl->flash_type == STM32_FLASH_TYPE_F7 || - sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { - // unlock if locked - unlock_flash_if(sl); - - // select the page to erase - if ((sl->chip_id == STM32_CHIPID_L4) || - (sl->chip_id == STM32_CHIPID_L43x_L44x) || - (sl->chip_id == STM32_CHIPID_L45x_L46x) || - (sl->chip_id == STM32_CHIPID_L496x_L4A6x) || - (sl->chip_id == STM32_CHIPID_L4Rx)) { - // calculate the actual bank+page from the address - uint32_t page = calculate_L4_page(sl, flashaddr); - - fprintf(stderr, "EraseFlash - Page:0x%x Size:0x%x ", page, - stlink_calculate_pagesize(sl, flashaddr)); - - write_flash_cr_bker_pnb(sl, page); - } else if (sl->chip_id == STM32_CHIPID_F7 || - sl->chip_id == STM32_CHIPID_F76xxx) { - // calculate the actual page from the address - uint32_t sector = calculate_F7_sectornum(flashaddr); - - fprintf(stderr, "EraseFlash - Sector:0x%x Size:0x%x ", sector, - stlink_calculate_pagesize(sl, flashaddr)); - write_flash_cr_snb(sl, sector, BANK_1); - } else { - // calculate the actual page from the address - uint32_t sector = calculate_F4_sectornum(flashaddr); - - fprintf(stderr, "EraseFlash - Sector:0x%x Size:0x%x ", sector, - stlink_calculate_pagesize(sl, flashaddr)); - - // the SNB values for flash sectors in the second bank do not directly - // follow the values for the first bank on 2mb devices... - if (sector >= 12) { - sector += 4; - } - - write_flash_cr_snb(sl, sector, BANK_1); - } - - set_flash_cr_strt(sl, BANK_1); // start erase operation - wait_flash_busy(sl); // wait for completion - lock_flash(sl); // TODO: fails to program if this is in -#if DEBUG_FLASH - fprintf(stdout, "Erase Final CR:0x%x\n", read_flash_cr(sl, BANK_1)); -#endif - } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { - - uint32_t val; - uint32_t flash_regs_base = get_stm32l0_flash_base(sl); - - // check if the locks are set - stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); - - if ((val & (1 << 0)) || (val & (1 << 1))) { - // disable pecr protection - stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, - FLASH_L0_PEKEY1); - stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, - FLASH_L0_PEKEY2); - - // check pecr.pelock is cleared - stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); - - if (val & (1 << 0)) { - WLOG("pecr.pelock not clear (%#x)\n", val); - return (-1); - } - - // unlock program memory - stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, - FLASH_L0_PRGKEY1); - stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, - FLASH_L0_PRGKEY2); - - // check pecr.prglock is cleared - stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); - - if (val & (1 << 1)) { - WLOG("pecr.prglock not clear (%#x)\n", val); - return (-1); - } - } - - // set pecr.{erase,prog} - val |= (1 << 9) | (1 << 3); - stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); - - // write 0 to the first word of the page to be erased - stlink_write_debug32(sl, flashaddr, 0); - - /* MP: It is better to wait for clearing the busy bit after issuing page - * erase command, even though PM0062 recommends to wait before it. - * Test shows that a few iterations is performed in the following loop - * before busy bit is cleared. - */ - wait_flash_busy(sl); - - // reset lock bits - stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); - val |= (1 << 0) | (1 << 1) | (1 << 2); - stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); - } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL || - sl->flash_type == STM32_FLASH_TYPE_G0 || - sl->flash_type == STM32_FLASH_TYPE_G4) { - uint32_t val; - unlock_flash_if(sl); - set_flash_cr_per(sl, BANK_1); // set the 'enable Flash erase' bit - - // set the page to erase - if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { - uint32_t flash_page = - ((flashaddr - STM32_FLASH_BASE) / (uint32_t)(sl->flash_pgsz)); - stlink_read_debug32(sl, STM32WB_FLASH_CR, &val); - - // sec 3.10.5 - PNB[7:0] is offset by 3. - val &= ~(0xFF << 3); // Clear previously set page number (if any) - val |= ((flash_page & 0xFF) << 3); - - stlink_write_debug32(sl, STM32WB_FLASH_CR, val); - } else if (sl->flash_type == STM32_FLASH_TYPE_G0) { - uint32_t flash_page = - ((flashaddr - STM32_FLASH_BASE) / (uint32_t)(sl->flash_pgsz)); - stlink_read_debug32(sl, STM32Gx_FLASH_CR, &val); - // sec 3.7.5 - PNB[5:0] is offset by 3. PER is 0x2. - val &= ~(0x3F << 3); - val |= ((flash_page & 0x3F) << 3) | (1 << FLASH_CR_PER); - stlink_write_debug32(sl, STM32Gx_FLASH_CR, val); - } else if (sl->flash_type == STM32_FLASH_TYPE_G4) { - uint32_t flash_page = - ((flashaddr - STM32_FLASH_BASE) / (uint32_t)(sl->flash_pgsz)); - stlink_read_debug32(sl, STM32Gx_FLASH_CR, &val); - // sec 3.7.5 - PNB[6:0] is offset by 3. PER is 0x2. - val &= ~(0x7F << 3); - val |= ((flash_page & 0x7F) << 3) | (1 << FLASH_CR_PER); - stlink_write_debug32(sl, STM32Gx_FLASH_CR, val); - } - - set_flash_cr_strt(sl, BANK_1); // set the 'start operation' bit - wait_flash_busy(sl); // wait for the 'busy' bit to clear - clear_flash_cr_per(sl, BANK_1); // clear the 'enable page erase' bit - lock_flash(sl); - } else if (sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3 || - sl->flash_type == STM32_FLASH_TYPE_F1_XL) { - unsigned bank = (flashaddr < STM32_F1_FLASH_BANK2_BASE) ? BANK_1 : BANK_2; - unlock_flash_if(sl); - clear_flash_cr_pg(sl, bank); // clear the pg bit - set_flash_cr_per(sl, bank); // set the page erase bit - write_flash_ar(sl, flashaddr, bank); // select the page to erase - set_flash_cr_strt(sl, - bank); // start erase operation, reset by hw with busy bit - wait_flash_busy(sl); - clear_flash_cr_per(sl, bank); // clear the page erase bit - lock_flash(sl); - } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { - unsigned bank = (flashaddr < STM32_H7_FLASH_BANK2_BASE) ? BANK_1 : BANK_2; - unlock_flash_if(sl); // unlock if locked - uint32_t sector = calculate_H7_sectornum( - sl, flashaddr, bank); // calculate the actual page from the address - write_flash_cr_snb(sl, sector, bank); // select the page to erase - set_flash_cr_strt(sl, bank); // start erase operation - wait_flash_busy(sl); // wait for completion - lock_flash(sl); - } else { - WLOG("unknown coreid %x, page erase failed\n", sl->core_id); - return (-1); - } - - return check_flash_error(sl); -} - -// Check if an address and size are within the flash -int stlink_check_address_range_validity(stlink_t *sl, stm32_addr_t addr, size_t size) { - if (addr < sl->flash_base || addr >= (sl->flash_base + sl->flash_size)) { - ELOG("Invalid address, it should be within 0x%08x - 0x%08lx\n", sl->flash_base, (sl->flash_base + sl->flash_size -1)); - return (-1); - } - if ((addr + size) > (sl->flash_base + sl->flash_size)) { - ELOG("The size exceeds the size of the flash (0x%08lx bytes available)\n", (sl->flash_base + sl->flash_size - addr)); - return (-1); - } - return 0; -} - -// Check if an address is aligned with the beginning of a page -int stlink_check_address_alignment(stlink_t *sl, stm32_addr_t addr) { - stm32_addr_t page = sl->flash_base; - - while (page < addr) { - page += stlink_calculate_pagesize(sl, page); - } - - if (page != addr) { - return -1; - } - - return 0; -} - -int stlink_erase_flash_section(stlink_t *sl, stm32_addr_t base_addr, size_t size, bool align_size) { - // Check the address and size validity - if (stlink_check_address_range_validity(sl, base_addr, size) < 0) { - return -1; - } - - // Make sure the requested address is aligned with the beginning of a page - if (stlink_check_address_alignment(sl, base_addr) < 0) { - ELOG("The address to erase is not aligned with the beginning of a page\n"); - return -1; - } - - stm32_addr_t addr = base_addr; - do { - size_t page_size = stlink_calculate_pagesize(sl, addr); - - // Check if size is aligned with a page, unless we want to completely erase the last page - if ((addr + page_size) > (base_addr + size) && !align_size) { - ELOG("Invalid size (not aligned with a page). Page size at address %#x is %#lx\n", addr, page_size); - return -1; - } - - if (stlink_erase_flash_page(sl, addr)) { - WLOG("Failed to erase_flash_page(%#x) == -1\n", addr); - return (-1); - } - - fprintf(stdout, "-> Flash page at %#x erased (size: %#lx)\n", addr, page_size); - fflush(stdout); - - // check the next page is within the range to erase - addr += page_size; - } while (addr < (base_addr + size)); - - fprintf(stdout, "\n"); - return 0; -} - -int stlink_erase_flash_mass(stlink_t *sl) { - int err = 0; - - // TODO: User MER bit to mass-erase WB series. - if (sl->flash_type == STM32_FLASH_TYPE_L0_L1 || - sl->flash_type == STM32_FLASH_TYPE_WB_WL) { - - err = stlink_erase_flash_section(sl, sl->flash_base, sl->flash_size, false); - - } else { - wait_flash_busy(sl); - clear_flash_error(sl); - unlock_flash_if(sl); - - if (sl->flash_type == STM32_FLASH_TYPE_H7 && - sl->chip_id != STM32_CHIPID_H7Ax) { - // set parallelism - write_flash_cr_psiz(sl, 3 /*64it*/, BANK_1); - if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { - write_flash_cr_psiz(sl, 3 /*64bit*/, BANK_2); - } - } - - set_flash_cr_mer(sl, 1, BANK_1); // set the mass erase bit - set_flash_cr_strt( - sl, BANK_1); // start erase operation, reset by hw with busy bit - - if (sl->flash_type == STM32_FLASH_TYPE_F1_XL || - (sl->flash_type == STM32_FLASH_TYPE_H7 && - sl->chip_flags & CHIP_F_HAS_DUAL_BANK)) { - set_flash_cr_mer(sl, 1, BANK_2); // set the mass erase bit in bank 2 - set_flash_cr_strt(sl, BANK_2); // start erase operation in bank 2 - } - - wait_flash_busy_progress(sl); - lock_flash(sl); - - // reset the mass erase bit - set_flash_cr_mer(sl, 0, BANK_1); - if (sl->flash_type == STM32_FLASH_TYPE_F1_XL || - (sl->flash_type == STM32_FLASH_TYPE_H7 && - sl->chip_flags & CHIP_F_HAS_DUAL_BANK)) { - set_flash_cr_mer(sl, 0, BANK_2); - } - - err = check_flash_error(sl); - } - - return (err); -} - -int stlink_fcheck_flash(stlink_t *sl, const char *path, stm32_addr_t addr) { - // check the contents of path are at addr - - int res; - mapped_file_t mf = MAPPED_FILE_INITIALIZER; - - if (map_file(&mf, path) == -1) { - return (-1); - } - - res = check_file(sl, &mf, addr); - unmap_file(&mf); - return (res); -} - -/** - * Verify addr..addr+len is binary identical to base...base+len - * @param sl stlink context - * @param address stm device address - * @param data host side buffer to check against - * @param length how much - * @return 0 for success, -ve for failure - */ -int stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, - unsigned length) { - size_t off; - size_t cmp_size = (sl->flash_pgsz > 0x1800) ? 0x1800 : sl->flash_pgsz; - ILOG("Starting verification of write complete\n"); - - for (off = 0; off < length; off += cmp_size) { - size_t aligned_size; - - // adjust last page size - if ((off + cmp_size) > length) { - cmp_size = length - off; - } - - aligned_size = cmp_size; - - if (aligned_size & (4 - 1)) { - aligned_size = (cmp_size + 4) & ~(4 - 1); - } - - stlink_read_mem32(sl, address + (uint32_t)off, (uint16_t)aligned_size); - - if (memcmp(sl->q_buf, data + off, cmp_size)) { - ELOG("Verification of flash failed at offset: %u\n", (unsigned int)off); - return (-1); - } - } - - ILOG("Flash written and verified! jolly good!\n"); - return (0); -} - -int stm32l1_write_half_pages(stlink_t *sl, stm32_addr_t addr, uint8_t *base, - uint32_t len, uint32_t pagesize) { - unsigned int count, off; - unsigned int num_half_pages = len / pagesize; - uint32_t val; - uint32_t flash_regs_base = get_stm32l0_flash_base(sl); - flash_loader_t fl; - bool use_loader = true; - int ret = 0; - - // enable half page write - stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); - val |= (1 << FLASH_L1_FPRG); - stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); - val |= (1 << FLASH_L1_PROG); - stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); - - wait_flash_busy(sl); - - for (count = 0; count < num_half_pages; count++) { - if (use_loader) { - ret = stlink_flash_loader_run(sl, &fl, addr + count * pagesize, - base + count * pagesize, pagesize); - if (ret && count == 0) { - /* It seems that stm32lx devices have a problem when it is blank */ - WLOG("Failed to use flash loader, fallback to soft write\n"); - use_loader = false; - } - } - if (!use_loader) { - ret = 0; - for (off = 0; off < pagesize && !ret; off += 64) { - size_t chunk = (pagesize - off > 64) ? 64 : pagesize - off; - memcpy(sl->q_buf, base + count * pagesize + off, chunk); - ret = stlink_write_mem32(sl, addr + count * pagesize + off, (uint16_t)chunk); - } - } - - if (ret) { - WLOG("l1_stlink_flash_loader_run(%#x) failed! == -1\n", - addr + count * pagesize); - break; - } - - if (sl->verbose >= 1) { - // show progress; writing procedure is slow and previous errors are - // misleading - fprintf(stdout, "\r%3u/%u halfpages written", count + 1, num_half_pages); - fflush(stdout); - } - - // wait for sr.busy to be cleared - wait_flash_busy(sl); - } - - // disable half page write - stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); - val &= ~((1 << FLASH_L1_FPRG) | (1 << FLASH_L1_PROG)); - stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); - return (ret); -} - -int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { - // disable DMA - set_dma_state(sl, fl, 0); - - // wait for ongoing op to finish - wait_flash_busy(sl); - // Clear errors - clear_flash_error(sl); - - if ((sl->flash_type == STM32_FLASH_TYPE_F2_F4) || - (sl->flash_type == STM32_FLASH_TYPE_F7) || - (sl->flash_type == STM32_FLASH_TYPE_L4_L4P)) { - ILOG("Starting Flash write for F2/F4/F7/L4\n"); - - // Flash loader initialisation - if (stlink_flash_loader_init(sl, fl) == -1) { - ELOG("stlink_flash_loader_init() == -1\n"); - return (-1); - } - - unlock_flash_if(sl); // first unlock the cr - - int voltage; - if (sl->version.stlink_v == 1) { - WLOG("STLINK V1 cannot read voltage, use default voltage 3.2V\n"); - voltage = 3200; - } else { - voltage = stlink_target_voltage(sl); - } - - if (voltage == -1) { - ELOG("Failed to read Target voltage\n"); - return (-1); - } - - if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { - // L4 does not have a byte-write mode - if (voltage < 1710) { - ELOG("Target voltage (%d mV) too low for flash writes!\n", voltage); - return (-1); - } - } else { - if (voltage > 2700) { - ILOG("enabling 32-bit flash writes\n"); - write_flash_cr_psiz(sl, 2, BANK_1); - } else { - ILOG("Target voltage (%d mV) too low for 32-bit flash, " - "using 8-bit flash writes\n", - voltage); - write_flash_cr_psiz(sl, 0, BANK_1); - } - } - - // set programming mode - set_flash_cr_pg(sl, BANK_1); - } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL || - sl->flash_type == STM32_FLASH_TYPE_G0 || - sl->flash_type == STM32_FLASH_TYPE_G4) { - ILOG("Starting Flash write for WB/G0/G4\n"); - - unlock_flash_if(sl); // unlock flash if necessary - set_flash_cr_pg(sl, BANK_1); // set PG 'allow programming' bit - } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { - ILOG("Starting Flash write for L0\n"); - - uint32_t val; - uint32_t flash_regs_base = get_stm32l0_flash_base(sl); - - // disable pecr protection - stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, - FLASH_L0_PEKEY1); - stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, - FLASH_L0_PEKEY2); - - // check pecr.pelock is cleared - stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); - if (val & (1 << 0)) { - ELOG("pecr.pelock not clear\n"); - return (-1); - } - - // unlock program memory - stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, - FLASH_L0_PRGKEY1); - stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, - FLASH_L0_PRGKEY2); - - // check pecr.prglock is cleared - stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); - if (val & (1 << 1)) { - ELOG("pecr.prglock not clear\n"); - return (-1); - } - - /* Flash loader initialisation */ - if (stlink_flash_loader_init(sl, fl) == -1) { - // L0/L1 have fallback to soft write - WLOG("stlink_flash_loader_init() == -1\n"); - } - } else if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || - (sl->flash_type == STM32_FLASH_TYPE_F1_XL)) { - ILOG("Starting Flash write for VL/F0/F3/F1_XL\n"); - - // flash loader initialisation - if (stlink_flash_loader_init(sl, fl) == -1) { - ELOG("stlink_flash_loader_init() == -1\n"); - return (-1); - } - - // unlock flash - unlock_flash_if(sl); - - // set programming mode - set_flash_cr_pg(sl, BANK_1); - if (sl->flash_type == STM32_FLASH_TYPE_F1_XL) { - set_flash_cr_pg(sl, BANK_2); - } - } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { - ILOG("Starting Flash write for H7\n"); - - unlock_flash_if(sl); // unlock the cr - set_flash_cr_pg(sl, BANK_1); // set programming mode - if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { - set_flash_cr_pg(sl, BANK_2); - } - if (sl->chip_id != STM32_CHIPID_H7Ax) { - // set parallelism - write_flash_cr_psiz(sl, 3 /*64it*/, BANK_1); - if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { - write_flash_cr_psiz(sl, 3 /*64bit*/, BANK_2); - } - } - } else { - ELOG("unknown coreid, not sure how to write: %x\n", sl->core_id); - return (-1); - } - - return (0); -} - -int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, - stm32_addr_t addr, uint8_t *base, uint32_t len) { - size_t off; - if ((sl->flash_type == STM32_FLASH_TYPE_F2_F4) || - (sl->flash_type == STM32_FLASH_TYPE_F7) || - (sl->flash_type == STM32_FLASH_TYPE_L4_L4P)) { - size_t buf_size = (sl->sram_size > 0x8000) ? 0x8000 : 0x4000; - for (off = 0; off < len;) { - size_t size = len - off > buf_size ? buf_size : len - off; - if (stlink_flash_loader_run(sl, fl, addr + (uint32_t)off, base + off, - size) == -1) { - ELOG("stlink_flash_loader_run(%#x) failed! == -1\n", - (unsigned)(addr + off)); - check_flash_error(sl); - return (-1); - } - - off += size; - } - } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL || - sl->flash_type == STM32_FLASH_TYPE_G0 || - sl->flash_type == STM32_FLASH_TYPE_G4) { - DLOG("Starting %3u page write\r\n", (unsigned int)(len / sl->flash_pgsz)); - for (off = 0; off < len; off += sizeof(uint32_t)) { - uint32_t data; - - if ((off % sl->flash_pgsz) > (sl->flash_pgsz - 5)) { - fprintf(stdout, "\r%3u/%3u pages written", - (unsigned int)(off / sl->flash_pgsz), - (unsigned int)(len / sl->flash_pgsz)); - fflush(stdout); - } - - write_uint32((unsigned char *)&data, *(uint32_t *)(base + off)); - stlink_write_debug32(sl, addr + (uint32_t)off, data); - wait_flash_busy(sl); // wait for 'busy' bit in FLASH_SR to clear - } - fprintf(stdout, "\n"); - - // flash writes happen as 2 words at a time - if ((off / sizeof(uint32_t)) % 2 != 0) { - stlink_write_debug32(sl, addr + (uint32_t)off, - 0); // write a single word of zeros - wait_flash_busy(sl); // wait for 'busy' bit in FLASH_SR to clear - } - } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { - uint32_t val; - uint32_t flash_regs_base = get_stm32l0_flash_base(sl); - uint32_t pagesize = (flash_regs_base==STM32L0_FLASH_REGS_ADDR)? - L0_WRITE_BLOCK_SIZE:L1_WRITE_BLOCK_SIZE; - - DLOG("Starting %3u page write\r\n", (unsigned int)(len / sl->flash_pgsz)); - - off = 0; - - if (len > pagesize) { - if (stm32l1_write_half_pages(sl, addr, base, len, pagesize)) { - return (-1); - } else { - off = (size_t)(len / pagesize) * pagesize; - } - } - - // write remaining word in program memory - for (; off < len; off += sizeof(uint32_t)) { - uint32_t data; - - if ((off % sl->flash_pgsz) > (sl->flash_pgsz - 5)) { - fprintf(stdout, "\r%3u/%3u pages written", - (unsigned int)(off / sl->flash_pgsz), - (unsigned int)(len / sl->flash_pgsz)); - fflush(stdout); - } - - write_uint32((unsigned char *)&data, *(uint32_t *)(base + off)); - stlink_write_debug32(sl, addr + (uint32_t)off, data); - - // wait for sr.busy to be cleared - do { - stlink_read_debug32(sl, flash_regs_base + FLASH_SR_OFF, &val); - } while ((val & (1 << 0)) != 0); - - // TODO: check redo write operation - } - fprintf(stdout, "\n"); - } else if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || - (sl->flash_type == STM32_FLASH_TYPE_F1_XL)) { - int write_block_count = 0; - for (off = 0; off < len; off += sl->flash_pgsz) { - // adjust last write size - size_t size = len - off > sl->flash_pgsz ? sl->flash_pgsz : len - off; - - // unlock and set programming mode - unlock_flash_if(sl); - - DLOG("Finished unlocking flash, running loader!\n"); - - if (stlink_flash_loader_run(sl, fl, addr + (uint32_t)off, base + off, - size) == -1) { - ELOG("stlink_flash_loader_run(%#x) failed! == -1\n", - (unsigned)(addr + off)); - check_flash_error(sl); - return (-1); - } - - lock_flash(sl); - - if (sl->verbose >= 1) { - // show progress; writing procedure is slow and previous errors are - // misleading - fprintf(stdout, "\r%3u/%3u pages written", ++write_block_count, - (unsigned int)((len + sl->flash_pgsz - 1) / sl->flash_pgsz)); - fflush(stdout); - } - } - if (sl->verbose >= 1) { - fprintf(stdout, "\n"); - } - } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { - for (off = 0; off < len;) { - // Program STM32H7x with 64-byte Flash words - size_t chunk = (len - off > 64) ? 64 : len - off; - memcpy(sl->q_buf, base + off, chunk); - stlink_write_mem32(sl, addr + (uint32_t)off, 64); - wait_flash_busy(sl); - - off += chunk; - - if (sl->verbose >= 1) { - // show progress - fprintf(stdout, "\r%u/%u bytes written", (unsigned int)off, - (unsigned int)len); - fflush(stdout); - } - } - if (sl->verbose >= 1) { - fprintf(stdout, "\n"); - } - } else { - return (-1); - } - - return check_flash_error(sl); -} - -int stlink_flashloader_stop(stlink_t *sl, flash_loader_t *fl) { - uint32_t dhcsr; - - if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || - (sl->flash_type == STM32_FLASH_TYPE_F1_XL) || - (sl->flash_type == STM32_FLASH_TYPE_F2_F4) || - (sl->flash_type == STM32_FLASH_TYPE_F7) || - (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) || - (sl->flash_type == STM32_FLASH_TYPE_WB_WL) || - (sl->flash_type == STM32_FLASH_TYPE_G0) || - (sl->flash_type == STM32_FLASH_TYPE_G4) || - (sl->flash_type == STM32_FLASH_TYPE_H7)) { - - clear_flash_cr_pg(sl, BANK_1); - if ((sl->flash_type == STM32_FLASH_TYPE_H7 && - sl->chip_flags & CHIP_F_HAS_DUAL_BANK) || - sl->flash_type == STM32_FLASH_TYPE_F1_XL) { - clear_flash_cr_pg(sl, BANK_2); - } - lock_flash(sl); - } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { - uint32_t val; - uint32_t flash_regs_base = get_stm32l0_flash_base(sl); - - // reset lock bits - stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); - val |= (1 << 0) | (1 << 1) | (1 << 2); - stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); - } - - // enable interrupt - if (!stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr)) { - stlink_write_debug32(sl, STLINK_REG_DHCSR, - STLINK_REG_DHCSR_DBGKEY | STLINK_REG_DHCSR_C_DEBUGEN | - (dhcsr & (~STLINK_REG_DHCSR_C_MASKINTS))); - } - - // restore DMA state - set_dma_state(sl, fl, 1); - - return (0); -} - -int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t *base, - uint32_t len, uint8_t eraseonly) { - int ret; - flash_loader_t fl; - ILOG("Attempting to write %d (%#x) bytes to stm32 address: %u (%#x)\n", len, - len, addr, addr); - // check addr range is inside the flash - stlink_calculate_pagesize(sl, addr); - - // Check the address and size validity - if (stlink_check_address_range_validity(sl, addr, len) < 0) { - return (-1); - } else if (len & 1) { - WLOG("unaligned len 0x%x -- padding with zero\n", len); - len += 1; - } else if (stlink_check_address_alignment(sl, addr) < 0) { - ELOG("addr not a multiple of current pagesize (%u bytes), not supported, " - "check page start address and compare with flash module organisation " - "in related ST reference manual of your device.\n", - (unsigned)(sl->flash_pgsz)); - return (-1); - } - - // make sure we've loaded the context with the chip details - stlink_core_id(sl); - - // Erase this section of the flash - if (stlink_erase_flash_section(sl, addr, len, true) < 0) { - ELOG("Failed to erase the flash prior to writing\n"); - return (-1); - } - - if (eraseonly) { - return (0); - } - - ret = stlink_flashloader_start(sl, &fl); - if (ret) - return ret; - ret = stlink_flashloader_write(sl, &fl, addr, base, len); - if (ret) - return ret; - ret = stlink_flashloader_stop(sl, &fl); - if (ret) - return ret; - - return (stlink_verify_write_flash(sl, addr, base, len)); -} - -// TODO: length not checked -static uint8_t stlink_parse_hex(const char *hex) { - uint8_t d[2]; - - for (int i = 0; i < 2; ++i) { - char c = *(hex + i); - - if (c >= '0' && c <= '9') { - d[i] = c - '0'; - } else if (c >= 'A' && c <= 'F') { - d[i] = c - 'A' + 10; - } else if (c >= 'a' && c <= 'f') { - d[i] = c - 'a' + 10; - } else { - return (0); // error - } - } - - return ((d[0] << 4) | (d[1])); -} - -int stlink_parse_ihex(const char *path, uint8_t erased_pattern, uint8_t **mem, - size_t *size, uint32_t *begin) { - int res = 0; - *begin = UINT32_MAX; - uint8_t *data = NULL; - uint32_t end = 0; - bool eof_found = false; - - for (int scan = 0; (res == 0) && (scan < 2); ++scan) { - // parse file two times - first to find memory range, second - to fill it - if (scan == 1) { - if (!eof_found) { - ELOG("No EoF recond\n"); - res = -1; - break; - } - - if (*begin >= end) { - ELOG("No data found in file\n"); - res = -1; - break; - } - - *size = (end - *begin) + 1; - data = calloc(*size, 1); // use calloc to get NULL if out of memory - - if (!data) { - ELOG("Cannot allocate %u bytes\n", (unsigned)(*size)); - res = -1; - break; - } - - memset(data, erased_pattern, *size); - } - - FILE *file = fopen(path, "r"); - - if (!file) { - ELOG("Cannot open file\n"); - res = -1; - break; - } - - uint32_t lba = 0; - char line[1 + 5 * 2 + 255 * 2 + 2]; - - while (fgets(line, sizeof(line), file)) { - if (line[0] == '\n' || line[0] == '\r') { - continue; - } // skip empty lines - - if (line[0] != ':') { // no marker - wrong file format - ELOG("Wrong file format - no marker\n"); - res = -1; - break; - } - - size_t l = strlen(line); - - while (l > 0 && (line[l - 1] == '\n' || line[l - 1] == '\r')) { - --l; - } // trim EoL - - if ((l < 11) || - (l == - (sizeof(line) - 1))) { // line too short or long - wrong file format - ELOG("Wrong file format - wrong line length\n"); - res = -1; - break; - } - - uint8_t chksum = 0; // check sum - - for (size_t i = 1; i < l; i += 2) { - chksum += stlink_parse_hex(line + i); - } - - if (chksum != 0) { - ELOG("Wrong file format - checksum mismatch\n"); - res = -1; - break; - } - - uint8_t reclen = stlink_parse_hex(line + 1); - - if (((uint32_t)reclen + 5) * 2 + 1 != l) { - ELOG("Wrong file format - record length mismatch\n"); - res = -1; - break; - } - - uint16_t offset = ((uint16_t)stlink_parse_hex(line + 3) << 8) | - ((uint16_t)stlink_parse_hex(line + 5)); - uint8_t rectype = stlink_parse_hex(line + 7); - - switch (rectype) { - case 0: /* Data */ - if (scan == 0) { - uint32_t b = lba + offset; - uint32_t e = b + reclen - 1; - - if (b < *begin) { - *begin = b; - } - - if (e > end) { - end = e; - } - } else { - for (uint8_t i = 0; i < reclen; ++i) { - uint8_t b = stlink_parse_hex(line + 9 + i * 2); - uint32_t addr = lba + offset + i; - - if (addr >= *begin && addr <= end) { - data[addr - *begin] = b; - } - } - } - break; - case 1: /* EoF */ - eof_found = true; - break; - case 2: /* Extended Segment Address, unexpected */ - res = -1; - break; - case 3: /* Start Segment Address, unexpected */ - res = -1; - break; - case 4: /* Extended Linear Address */ - if (reclen == 2) { - lba = ((uint32_t)stlink_parse_hex(line + 9) << 24) | - ((uint32_t)stlink_parse_hex(line + 11) << 16); - } else { - ELOG("Wrong file format - wrong LBA length\n"); - res = -1; - } - break; - case 5: /* Start Linear Address - expected, but ignore */ - break; - default: - ELOG("Wrong file format - unexpected record type %d\n", rectype); - res = -1; - } - - if (res != 0) { - break; - } - } - - fclose(file); - } - - if (res == 0) { - *mem = data; - } else { - free(data); - } - - return (res); -} - -uint8_t stlink_get_erased_pattern(stlink_t *sl) { - if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { - return (0x00); - } else { - return (0xff); - } -} - -int stlink_mwrite_flash(stlink_t *sl, uint8_t *data, uint32_t length, - stm32_addr_t addr) { - /* Write the block in flash at addr */ - int err; - unsigned int num_empty, idx; - uint8_t erased_pattern = stlink_get_erased_pattern(sl); - - /* - * This optimisation may cause unexpected garbage data remaining. - * Therfore it is turned off by default. - */ - if (sl->opt) { - idx = (unsigned int)length; - - for (num_empty = 0; num_empty != length; ++num_empty) - if (data[--idx] != erased_pattern) { - break; - } - - num_empty -= (num_empty & 3); // Round down to words - - if (num_empty != 0) { - ILOG("Ignoring %d bytes of 0x%02x at end of file\n", num_empty, - erased_pattern); - } - } else { - num_empty = 0; - } - - /* - * TODO: investigate a kind of weird behaviour here: - * If the file is identified to be all-empty and four-bytes aligned, - * still flash the whole file even if ignoring message is printed. - */ - err = stlink_write_flash(sl, addr, data, - (num_empty == length) ? (uint32_t)length - : (uint32_t)length - num_empty, - num_empty == length); - stlink_fwrite_finalize(sl, addr); - return (err); -} - -/** - * Write the given binary file into flash at address "addr" - * @param sl - * @param path readable file path, should be binary image - * @param addr where to start writing - * @return 0 on success, -ve on failure. - */ -int stlink_fwrite_flash(stlink_t *sl, const char *path, stm32_addr_t addr) { - /* Write the file in flash at addr */ - int err; - unsigned int num_empty, idx; - uint8_t erased_pattern = stlink_get_erased_pattern(sl); - mapped_file_t mf = MAPPED_FILE_INITIALIZER; - - if (map_file(&mf, path) == -1) { - ELOG("map_file() == -1\n"); - return (-1); - } - - printf("file %s ", path); - md5_calculate(&mf); - stlink_checksum(&mf); - - if (sl->opt) { - idx = (unsigned int)mf.len; - - for (num_empty = 0; num_empty != mf.len; ++num_empty) { - if (mf.base[--idx] != erased_pattern) { - break; - } - } - - num_empty -= (num_empty & 3); // round down to words - - if (num_empty != 0) { - ILOG("Ignoring %d bytes of 0x%02x at end of file\n", num_empty, - erased_pattern); - } - } else { - num_empty = 0; - } - - /* - * TODO: investigate a kind of weird behaviour here: - * If the file is identified to be all-empty and four-bytes aligned, - * still flash the whole file even if ignoring message is printed. - */ - err = stlink_write_flash(sl, addr, mf.base, - (num_empty == mf.len) ? (uint32_t)mf.len - : (uint32_t)mf.len - num_empty, - num_empty == mf.len); - stlink_fwrite_finalize(sl, addr); - unmap_file(&mf); - return (err); -} - -/** - * Write option bytes - * @param sl - * @param base option bytes to write - * @param addr of the memory mapped option bytes - * @param len of options bytes to write - * @return 0 on success, -ve on failure. - */ -static int stlink_write_option_bytes_f0( - stlink_t *sl, uint8_t* base, stm32_addr_t addr, uint32_t len) { - int ret = 0; - - if (len < 12 || addr != STM32_F0_OPTION_BYTES_BASE) { - WLOG("Only full write of option bytes area is supported\n"); - return -1; - } - - clear_flash_error(sl); - - WLOG("Erasing option bytes\n"); - - /* erase option bytes */ - stlink_write_debug32(sl, FLASH_CR, (1 << FLASH_CR_OPTER) | (1 << FLASH_CR_OPTWRE)); - ret = stlink_write_debug32(sl, FLASH_CR, (1 << FLASH_CR_OPTER) | (1 << FLASH_CR_STRT) | (1 << FLASH_CR_OPTWRE)); - if (ret) { - return ret; - } - - wait_flash_busy(sl); - - ret = check_flash_error(sl); - if (ret) { - return ret; - } - - WLOG("Writing option bytes to %#10x\n", addr); - - /* Set the Option PG bit to enable programming */ - stlink_write_debug32(sl, FLASH_CR, (1 << FLASH_CR_OPTPG) | (1 << FLASH_CR_OPTWRE)); - - /* Use flash loader for write OP - * because flash memory writable by half word */ - flash_loader_t fl; - ret = stlink_flash_loader_init(sl, &fl); - if (ret) { - return ret; - } - ret = stlink_flash_loader_run(sl, &fl, addr, base, len); - if (ret) { - return ret; - } - - /* Reload option bytes */ - stlink_write_debug32(sl, FLASH_CR, (1 << FLASH_CR_OBL_LAUNCH)); - - return check_flash_error(sl); -} - -/** - * Write option bytes - * @param sl - * @param addr of the memory mapped option bytes - * @param base option bytes to write - * @return 0 on success, -ve on failure. - */ -static int stlink_write_option_bytes_gx(stlink_t *sl, uint8_t *base, - stm32_addr_t addr, uint32_t len) { - /* Write options bytes */ - uint32_t val; - int ret = 0; - (void)len; - uint32_t data; - - clear_flash_error(sl); - - write_uint32((unsigned char *)&data, *(uint32_t *)(base)); - WLOG("Writing option bytes %#10x to %#10x\n", data, addr); - stlink_write_debug32(sl, STM32Gx_FLASH_OPTR, data); - - // Set Options Start bit - stlink_read_debug32(sl, STM32Gx_FLASH_CR, &val); - val |= (1 << STM32Gx_FLASH_CR_OPTSTRT); - stlink_write_debug32(sl, STM32Gx_FLASH_CR, val); - - wait_flash_busy(sl); - - ret = check_flash_error(sl); - - // Reload options - stlink_read_debug32(sl, STM32Gx_FLASH_CR, &val); - val |= (1 << STM32Gx_FLASH_CR_OBL_LAUNCH); - stlink_write_debug32(sl, STM32Gx_FLASH_CR, val); - - return (ret); -} - -/** - * Write option bytes - * @param sl - * @param addr of the memory mapped option bytes - * @param base option bytes to write - * @return 0 on success, -ve on failure. - */ -static int stlink_write_option_bytes_l0(stlink_t *sl, uint8_t *base, - stm32_addr_t addr, uint32_t len) { - uint32_t flash_base = get_stm32l0_flash_base(sl); - uint32_t val; - uint32_t data; - int ret = 0; - - // Clear errors - clear_flash_error(sl); - - while (len != 0) { - write_uint32((unsigned char *)&data, - *(uint32_t *)(base)); // write options bytes - - WLOG("Writing option bytes %#10x to %#10x\n", data, addr); - stlink_write_debug32(sl, addr, data); - wait_flash_busy(sl); - - if ((ret = check_flash_error(sl))) { - break; - } - - len -= 4; - addr += 4; - base += 4; - } - - // Reload options - stlink_read_debug32(sl, flash_base + FLASH_PECR_OFF, &val); - val |= (1 << STM32L0_FLASH_OBL_LAUNCH); - stlink_write_debug32(sl, flash_base + FLASH_PECR_OFF, val); - - return (ret); -} - -/** - * Write option bytes - * @param sl - * @param addr of the memory mapped option bytes - * @param base option bytes to write - * @return 0 on success, -ve on failure. - */ -static int stlink_write_option_bytes_l4(stlink_t *sl, uint8_t *base, - stm32_addr_t addr, uint32_t len) { - - uint32_t val; - int ret = 0; - (void)addr; - (void)len; - - // Clear errors - clear_flash_error(sl); - - // write options bytes - uint32_t data; - write_uint32((unsigned char *)&data, *(uint32_t *)(base)); - WLOG("Writing option bytes 0x%04x\n", data); - stlink_write_debug32(sl, STM32L4_FLASH_OPTR, data); - - // set options start bit - stlink_read_debug32(sl, STM32L4_FLASH_CR, &val); - val |= (1 << STM32L4_FLASH_CR_OPTSTRT); - stlink_write_debug32(sl, STM32L4_FLASH_CR, val); - - wait_flash_busy(sl); - ret = check_flash_error(sl); - - // apply options bytes immediate - stlink_read_debug32(sl, STM32L4_FLASH_CR, &val); - val |= (1 << STM32L4_FLASH_CR_OBL_LAUNCH); - stlink_write_debug32(sl, STM32L4_FLASH_CR, val); - - return (ret); -} - -/** - * Write option bytes - * @param sl - * @param option_byte value to write - * @return 0 on success, -ve on failure. - */ -static int stlink_write_option_bytes_f4(stlink_t *sl, uint8_t *base, - stm32_addr_t addr, uint32_t len) { - uint32_t option_byte; - int ret = 0; - (void)addr; - (void)len; - - // Clear errors - clear_flash_error(sl); - - write_uint32((unsigned char *)&option_byte, *(uint32_t *)(base)); - - // write option byte, ensuring we dont lock opt, and set strt bit - stlink_write_debug32(sl, FLASH_F4_OPTCR, - (option_byte & ~(1 << FLASH_F4_OPTCR_LOCK)) | - (1 << FLASH_F4_OPTCR_START)); - - wait_flash_busy(sl); - ret = check_flash_error(sl); - - // option bytes are reloaded at reset only, no obl. */ - return (ret); -} - -/** - * Write option bytes - * @param sl - * @param option_byte value to write - * @return 0 on success, -ve on failure. - */ -static int stlink_write_option_bytes_f7(stlink_t *sl, uint8_t *base, - stm32_addr_t addr, uint32_t len) { - uint32_t option_byte; - int ret = 0; - - // Clear errors - clear_flash_error(sl); - - ILOG("Asked to write option byte %#10x to %#010x.\n", *(uint32_t *)(base), - addr); - write_uint32((unsigned char *)&option_byte, *(uint32_t *)(base)); - ILOG("Write %d option bytes %#010x to %#010x!\n", len, option_byte, addr); - - if (addr == 0) { - addr = FLASH_F7_OPTCR; - ILOG("No address provided, using %#10x\n", addr); - } - - if (addr == FLASH_F7_OPTCR) { - /* write option byte, ensuring we dont lock opt, and set strt bit */ - stlink_write_debug32(sl, FLASH_F7_OPTCR, - (option_byte & ~(1 << FLASH_F7_OPTCR_LOCK)) | - (1 << FLASH_F7_OPTCR_START)); - } else if (addr == FLASH_F7_OPTCR1) { - // Read FLASH_F7_OPTCR - uint32_t oldvalue; - stlink_read_debug32(sl, FLASH_F7_OPTCR, &oldvalue); - /* write option byte */ - stlink_write_debug32(sl, FLASH_F7_OPTCR1, option_byte); - // Write FLASH_F7_OPTCR lock and start address - stlink_write_debug32(sl, FLASH_F7_OPTCR, - (oldvalue & ~(1 << FLASH_F7_OPTCR_LOCK)) | - (1 << FLASH_F7_OPTCR_START)); - } else { - WLOG("WIP: write %#010x to address %#010x\n", option_byte, addr); - stlink_write_debug32(sl, addr, option_byte); - } - - wait_flash_busy(sl); - - ret = check_flash_error(sl); - if (!ret) - ILOG("Wrote %d option bytes %#010x to %#010x!\n", len, *(uint32_t *)base, - addr); - - /* option bytes are reloaded at reset only, no obl. */ - - return ret; -} - -/** - * Write STM32H7xx option bytes - * @param sl - * @param base option bytes to write - * @param addr of the memory mapped option bytes - * @param len number of bytes to write (must be multiple of 4) - * @return 0 on success, -ve on failure. - */ -static int stlink_write_option_bytes_h7(stlink_t *sl, uint8_t *base, - stm32_addr_t addr, uint32_t len) { - uint32_t val; - uint32_t data; - - // Wait until previous flash option has completed - wait_flash_busy(sl); - - // Clear previous error - stlink_write_debug32(sl, FLASH_H7_OPTCCR, - 1 << FLASH_H7_OPTCCR_CLR_OPTCHANGEERR); - - while (len != 0) { - switch (addr) { - case FLASH_H7_REGS_ADDR + 0x20: // FLASH_OPTSR_PRG - case FLASH_H7_REGS_ADDR + 0x2c: // FLASH_PRAR_PRG1 - case FLASH_H7_REGS_ADDR + 0x34: // FLASH_SCAR_PRG1 - case FLASH_H7_REGS_ADDR + 0x3c: // FLASH_WPSN_PRG1 - case FLASH_H7_REGS_ADDR + 0x44: // FLASH_BOOT_PRG - /* Write to FLASH_xxx_PRG registers */ - write_uint32((unsigned char *)&data, - *(uint32_t *)(base)); // write options bytes - - WLOG("Writing option bytes %#10x to %#10x\n", data, addr); - - /* Skip if the value in the CUR register is identical */ - stlink_read_debug32(sl, addr - 4, &val); - if (val == data) { + if (*begin >= end) { + ELOG("No data found in file\n"); + res = -1; break; } - /* Write new option byte values and start modification */ - stlink_write_debug32(sl, addr, data); - stlink_read_debug32(sl, FLASH_H7_OPTCR, &val); - val |= (1 << FLASH_H7_OPTCR_OPTSTART); - stlink_write_debug32(sl, FLASH_H7_OPTCR, val); - - /* Wait for the option bytes modification to complete */ - do { - stlink_read_debug32(sl, FLASH_H7_OPTSR_CUR, &val); - } while ((val & (1 << FLASH_H7_OPTSR_OPT_BUSY)) != 0); - - /* Check for errors */ - if ((val & (1 << FLASH_H7_OPTSR_OPTCHANGEERR)) != 0) { - stlink_write_debug32(sl, FLASH_H7_OPTCCR, - 1 << FLASH_H7_OPTCCR_CLR_OPTCHANGEERR); - return -1; + *size = (end - *begin) + 1; + data = calloc(*size, 1); // use calloc to get NULL if out of memory + + if (!data) { + ELOG("Cannot allocate %u bytes\n", (unsigned)(*size)); + res = -1; + break; } - break; - default: - /* Skip non-programmable registers */ - break; + memset(data, erased_pattern, *size); } - len -= 4; - addr += 4; - base += 4; - } - - return 0; -} - -/** - * Read option bytes - * @param sl - * @param option_byte value to write - * @return 0 on success, -ve on failure. - */ -int stlink_read_option_control_register_Gx(stlink_t *sl, - uint32_t *option_byte) { - return stlink_read_debug32(sl, STM32Gx_FLASH_OPTR, option_byte); -} - -/** - * Read option bytes - * @param sl - * @param option_byte value to write - * @return 0 on success, -ve on failure. - */ -int stlink_read_option_bytes_Gx(stlink_t *sl, uint32_t *option_byte) { - return stlink_read_option_control_register_Gx(sl, option_byte); -} - -/** - * Read option bytes - * @param sl - * @param option_byte value to write - * @return 0 on success, -ve on failure. - */ -int stlink_read_option_control_register_f2(stlink_t *sl, - uint32_t *option_byte) { - return stlink_read_debug32(sl, FLASH_F2_OPT_CR, option_byte); -} - -/** - * Read option bytes - * @param sl - * @param option_byte value to write - * @return 0 on success, -ve on failure. - */ -int stlink_read_option_bytes_f2(stlink_t *sl, uint32_t *option_byte) { - return stlink_read_option_control_register_f2(sl, option_byte); -} - -/** - * Read option bytes - * @param sl - * @param option_byte value to read - * @return 0 on success, -ve on failure. - */ -int stlink_read_option_control_register_f4(stlink_t *sl, - uint32_t *option_byte) { - return stlink_read_debug32(sl, FLASH_F4_OPTCR, option_byte); -} + FILE *file = fopen(path, "r"); -/** - * Read option bytes - * @param sl - * @param option_byte value to read - * @return 0 on success, -ve on failure. - */ -int stlink_read_option_bytes_f4(stlink_t *sl, uint32_t *option_byte) { - return stlink_read_option_control_register_f4(sl, option_byte); -} + if (!file) { + ELOG("Cannot open file\n"); + res = -1; + break; + } -/** - * Read option bytes - * @param sl - * @param option_byte value to read - * @return 0 on success, -ve on failure. - */ -int stlink_read_option_control_register_f7(stlink_t *sl, - uint32_t *option_byte) { - DLOG("@@@@ Read option control register byte from %#10x\n", FLASH_F7_OPTCR); - return stlink_read_debug32(sl, FLASH_F7_OPTCR, option_byte); -} + uint32_t lba = 0; + char line[1 + 5 * 2 + 255 * 2 + 2]; -/** - * Read option bytes - * @param sl - * @param option_byte value to read - * @return 0 on success, -ve on failure. - */ -int stlink_read_option_control_register_f0(stlink_t *sl, - uint32_t *option_byte) { - DLOG("@@@@ Read option control register byte from %#10x\n", FLASH_OBR); - return stlink_read_debug32(sl, FLASH_OBR, option_byte); -} + while (fgets(line, sizeof(line), file)) { + if (line[0] == '\n' || line[0] == '\r') { + continue; + } // skip empty lines -/** - * Read option bytes - * @param sl - * @param option_byte value to read - * @return 0 on success, -ve on failure. - */ -int stlink_read_option_control_register1_f7(stlink_t *sl, - uint32_t *option_byte) { - DLOG("@@@@ Read option control register 1 byte from %#10x\n", - FLASH_F7_OPTCR1); - return stlink_read_debug32(sl, FLASH_F7_OPTCR1, option_byte); -} + if (line[0] != ':') { // no marker - wrong file format + ELOG("Wrong file format - no marker\n"); + res = -1; + break; + } -/** - * Read option bytes - * @param sl - * @param option_byte value to read - * @return 0 on success, -ve on failure. - */ -int stlink_read_option_bytes_boot_add_f7(stlink_t *sl, uint32_t *option_byte) { - DLOG("@@@@ Read option byte boot address\n"); - return stlink_read_option_control_register1_f7(sl, option_byte); -} + size_t l = strlen(line); -/** - * Read option bytes - * @param sl - * @param option_byte value to read - * @return 0 on success, -ve on failure. - * - * Since multiple bytes can be read, we read and print all but one here - * and then return the last one just like other devices - */ -int stlink_read_option_bytes_f7(stlink_t *sl, uint32_t *option_byte) { - int err = -1; - for (uint32_t counter = 0; counter < (sl->option_size / 4 - 1); counter++) { - err = stlink_read_debug32(sl, sl->option_base + counter * sizeof(uint32_t), - option_byte); - if (err == -1) { - return err; - } else { - printf("%08x\n", *option_byte); - } - } + while (l > 0 && (line[l - 1] == '\n' || line[l - 1] == '\r')) { + --l; + } // trim EoL - return stlink_read_debug32( - sl, - sl->option_base + (uint32_t)(sl->option_size / 4 - 1) * sizeof(uint32_t), - option_byte); -} + if ((l < 11) || + (l == + (sizeof(line) - 1))) { // line too short or long - wrong file format + ELOG("Wrong file format - wrong line length\n"); + res = -1; + break; + } -/** - * Read first option bytes - * @param sl - * @param option_byte option value - * @return 0 on success, -ve on failure. - */ -int stlink_read_option_bytes_generic(stlink_t *sl, uint32_t *option_byte) { - DLOG("@@@@ Read option bytes boot address from %#10x\n", sl->option_base); - return stlink_read_debug32(sl, sl->option_base, option_byte); -} + uint8_t chksum = 0; // check sum -/** - * Read option bytes - * @param sl - * @param option_byte value to read - * @return 0 on success, -ve on failure. - */ -// int stlink_read_option_bytes_boot_add_generic(stlink_t *sl, uint32_t* -// option_byte) { -// DLOG("@@@@ Read option bytes boot address from %#10x\n", sl->option_base); -// return stlink_read_debug32(sl, sl->option_base, option_byte); -//} + for (size_t i = 1; i < l; i += 2) { + chksum += stlink_parse_hex(line + i); + } -/** - * Read option bytes - * @param sl - * @param option_byte value to read - * @return 0 on success, -ve on failure. - */ -// int stlink_read_option_control_register_generic(stlink_t *sl, uint32_t* -// option_byte) { -// DLOG("@@@@ Read option control register byte from %#10x\n", -// sl->option_base); return stlink_read_debug32(sl, sl->option_base, -// option_byte); -//} + if (chksum != 0) { + ELOG("Wrong file format - checksum mismatch\n"); + res = -1; + break; + } -/** - * Read option bytes - * @param sl - * @param option_byte value to read - * @return 0 on success, -ve on failure. - */ -// int stlink_read_option_control_register1_generic(stlink_t *sl, uint32_t* -// option_byte) { -// DLOG("@@@@ Read option control register 1 byte from %#10x\n", -// sl->option_base); return stlink_read_debug32(sl, sl->option_base, -// option_byte); -//} + uint8_t reclen = stlink_parse_hex(line + 1); -/** - * Read option bytes - * @param sl - * @param option_byte option value - * @return 0 on success, -ve on failure. - */ -int stlink_read_option_bytes32(stlink_t *sl, uint32_t *option_byte) { - if (sl->option_base == 0) { - ELOG("Option bytes read is currently not supported for connected chip\n"); - return (-1); - } + if (((uint32_t)reclen + 5) * 2 + 1 != l) { + ELOG("Wrong file format - record length mismatch\n"); + res = -1; + break; + } - switch (sl->chip_id) { - case STM32_CHIPID_F2: - return stlink_read_option_bytes_f2(sl, option_byte); - case STM32_CHIPID_F4: - case STM32_CHIPID_F446: - return stlink_read_option_bytes_f4(sl, option_byte); - case STM32_CHIPID_F76xxx: - return stlink_read_option_bytes_f7(sl, option_byte); - case STM32_CHIPID_G0_CAT1: - case STM32_CHIPID_G0_CAT2: - case STM32_CHIPID_G4_CAT2: - case STM32_CHIPID_G4_CAT3: - return stlink_read_option_bytes_Gx(sl, option_byte); - default: - return stlink_read_option_bytes_generic(sl, option_byte); - } -} + uint16_t offset = ((uint16_t)stlink_parse_hex(line + 3) << 8) | + ((uint16_t)stlink_parse_hex(line + 5)); + uint8_t rectype = stlink_parse_hex(line + 7); -/** - * Read option bytes - * @param sl - * @param option_byte option value - * @return 0 on success, -ve on failure. - */ -int stlink_read_option_bytes_boot_add32(stlink_t *sl, uint32_t *option_byte) { - if (sl->option_base == 0) { - ELOG("Option bytes boot address read is currently not supported for " - "connected chip\n"); - return -1; - } + switch (rectype) { + case 0: /* Data */ + if (scan == 0) { + uint32_t b = lba + offset; + uint32_t e = b + reclen - 1; - switch (sl->flash_type) { - case STM32_FLASH_TYPE_F7: - return stlink_read_option_bytes_boot_add_f7(sl, option_byte); - default: - return -1; - // return stlink_read_option_bytes_boot_add_generic(sl, option_byte); - } -} + if (b < *begin) { + *begin = b; + } -/** - * Read option bytes - * @param sl - * @param option_byte option value - * @return 0 on success, -ve on failure. - */ -int stlink_read_option_control_register32(stlink_t *sl, uint32_t *option_byte) { - if (sl->option_base == 0) { - ELOG("Option bytes read is currently not supported for connected chip\n"); - return -1; - } + if (e > end) { + end = e; + } + } else { + for (uint8_t i = 0; i < reclen; ++i) { + uint8_t b = stlink_parse_hex(line + 9 + i * 2); + uint32_t addr = lba + offset + i; - switch (sl->flash_type) { - case STM32_FLASH_TYPE_F0_F1_F3: - case STM32_FLASH_TYPE_F1_XL: - return stlink_read_option_control_register_f0(sl, option_byte); - case STM32_FLASH_TYPE_F7: - return stlink_read_option_control_register_f7(sl, option_byte); - default: - return -1; - } -} + if (addr >= *begin && addr <= end) { + data[addr - *begin] = b; + } + } + } + break; + case 1: /* EoF */ + eof_found = true; + break; + case 2: /* Extended Segment Address, unexpected */ + res = -1; + break; + case 3: /* Start Segment Address, unexpected */ + res = -1; + break; + case 4: /* Extended Linear Address */ + if (reclen == 2) { + lba = ((uint32_t)stlink_parse_hex(line + 9) << 24) | + ((uint32_t)stlink_parse_hex(line + 11) << 16); + } else { + ELOG("Wrong file format - wrong LBA length\n"); + res = -1; + } + break; + case 5: /* Start Linear Address - expected, but ignore */ + break; + default: + ELOG("Wrong file format - unexpected record type %d\n", rectype); + res = -1; + } -/** - * Read option bytes - * @param sl - * @param option_byte option value - * @return 0 on success, -ve on failure. - */ -int stlink_read_option_control_register1_32(stlink_t *sl, - uint32_t *option_byte) { - if (sl->option_base == 0) { - ELOG("Option bytes read is currently not supported for connected chip\n"); - return -1; + if (res != 0) { + break; + } + } + + fclose(file); } - switch (sl->flash_type) { - case STM32_FLASH_TYPE_F7: - return stlink_read_option_control_register1_f7(sl, option_byte); - default: - return -1; - // return stlink_read_option_control_register1_generic(sl, option_byte); + if (res == 0) { + *mem = data; + } else { + free(data); } + + return (res); } -/** - * Write option bytes - * @param sl - * @param option_byte value to write - * @return 0 on success, -ve on failure. - */ -int stlink_write_option_bytes32(stlink_t *sl, uint32_t option_byte) { - WLOG("About to write option byte %#10x to %#10x.\n", option_byte, - sl->option_base); - return stlink_write_option_bytes(sl, sl->option_base, (uint8_t *)&option_byte, - 4); +uint8_t stlink_get_erased_pattern(stlink_t *sl) { + if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { + return (0x00); + } else { + return (0xff); + } } -/** - * Write option bytes - * @param sl - * @param addr of the memory mapped option bytes - * @param base option bytes to write - * @return 0 on success, -ve on failure. - */ -int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t *base, - uint32_t len) { - int ret = -1; +int stlink_target_connect(stlink_t *sl, enum connect_type connect) { + if (connect == CONNECT_UNDER_RESET) { + stlink_enter_swd_mode(sl); - if (sl->option_base == 0) { - ELOG( - "Option bytes writing is currently not supported for connected chip\n"); - return (-1); + stlink_jtag_reset(sl, STLINK_DEBUG_APIV2_DRIVE_NRST_LOW); + + // try to halt the core before reset + // this is useful if the NRST pin is not connected + sl->backend->force_debug(sl); + + // minimum reset pulse duration of 20 us (RM0008, 8.1.2 Power reset) + usleep(20); + + stlink_jtag_reset(sl, STLINK_DEBUG_APIV2_DRIVE_NRST_HIGH); + + // try to halt the core after reset + unsigned timeout = time_ms() + 10; + while (time_ms() < timeout) { + sl->backend->force_debug(sl); + usleep(100); + } + + // check NRST connection + uint32_t dhcsr = 0; + stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); + if ((dhcsr & STLINK_REG_DHCSR_S_RESET_ST) == 0) { + WLOG("NRST is not connected\n"); + } + + // addition soft reset for halt before the first instruction + stlink_soft_reset(sl, 1 /* halt on reset */); } - if ((addr < sl->option_base) || addr > sl->option_base + sl->option_size) { - ELOG("Option bytes start address out of Option bytes range\n"); - return (-1); + if (stlink_current_mode(sl) != STLINK_DEV_DEBUG_MODE && + stlink_enter_swd_mode(sl)) { + printf("Failed to enter SWD mode\n"); + return -1; } - if (addr + len > sl->option_base + sl->option_size) { - ELOG("Option bytes data too long\n"); - return (-1); + if (connect == CONNECT_NORMAL) { + stlink_reset(sl, RESET_AUTO); } - wait_flash_busy(sl); + return stlink_load_device_params(sl); +} - if (unlock_flash_if(sl)) { - ELOG("Flash unlock failed! System reset required to be able to unlock it " - "again!\n"); - return (-1); - } +// End of delegates.... functions below are private to this module +// same as above with entrypoint. - if (unlock_flash_option_if(sl)) { - ELOG("Flash option unlock failed!\n"); - return (-1); - } +static void stop_wdg_in_debug(stlink_t *sl) { + uint32_t dbgmcu_cr; + uint32_t set; + uint32_t value; switch (sl->flash_type) { case STM32_FLASH_TYPE_F0_F1_F3: case STM32_FLASH_TYPE_F1_XL: - ret = stlink_write_option_bytes_f0(sl, base, addr, len); + case STM32_FLASH_TYPE_G4: + dbgmcu_cr = STM32F0_DBGMCU_CR; + set = (1 << STM32F0_DBGMCU_CR_IWDG_STOP) | + (1 << STM32F0_DBGMCU_CR_WWDG_STOP); break; case STM32_FLASH_TYPE_F2_F4: - ret = stlink_write_option_bytes_f4(sl, base, addr, len); - break; case STM32_FLASH_TYPE_F7: - ret = stlink_write_option_bytes_f7(sl, base, addr, len); - break; - case STM32_FLASH_TYPE_L0_L1: - ret = stlink_write_option_bytes_l0(sl, base, addr, len); - break; case STM32_FLASH_TYPE_L4_L4P: - ret = stlink_write_option_bytes_l4(sl, base, addr, len); + dbgmcu_cr = STM32F4_DBGMCU_APB1FZR1; + set = (1 << STM32F4_DBGMCU_APB1FZR1_IWDG_STOP) | + (1 << STM32F4_DBGMCU_APB1FZR1_WWDG_STOP); break; + case STM32_FLASH_TYPE_L0_L1: case STM32_FLASH_TYPE_G0: - case STM32_FLASH_TYPE_G4: - ret = stlink_write_option_bytes_gx(sl, base, addr, len); + dbgmcu_cr = STM32L0_DBGMCU_APB1_FZ; + set = (1 << STM32L0_DBGMCU_APB1_FZ_IWDG_STOP) | + (1 << STM32L0_DBGMCU_APB1_FZ_WWDG_STOP); break; case STM32_FLASH_TYPE_H7: - ret = stlink_write_option_bytes_h7(sl, base, addr, len); + dbgmcu_cr = STM32H7_DBGMCU_APB1HFZ; + set = (1 << STM32H7_DBGMCU_APB1HFZ_IWDG_STOP); break; - default: - ELOG("Option bytes writing is currently not implemented for connected " - "chip\n"); + case STM32_FLASH_TYPE_WB_WL: + dbgmcu_cr = STM32WB_DBGMCU_APB1FZR1; + set = (1 << STM32WB_DBGMCU_APB1FZR1_IWDG_STOP) | + (1 << STM32WB_DBGMCU_APB1FZR1_WWDG_STOP); break; + default: + return; } - if (ret) { - ELOG("Flash option write failed!\n"); - } else { - ILOG("Wrote %d option bytes to %#010x!\n", len, addr); + if (!stlink_read_debug32(sl, dbgmcu_cr, &value)) { + stlink_write_debug32(sl, dbgmcu_cr, value | set); } +} - /* Re-lock flash. */ - lock_flash_option(sl); - lock_flash(sl); - - return ret; +int stlink_jtag_reset(stlink_t *sl, int value) { + DLOG("*** stlink_jtag_reset %d ***\n", value); + return (sl->backend->jtag_reset(sl, value)); } -/** - * Write option bytes - * @param sl - * @param option_byte value to write - * @return 0 on success, -ve on failure. - */ -static int -stlink_write_option_control_register_f7(stlink_t *sl, - uint32_t option_control_register) { - int ret = 0; +int stlink_soft_reset(stlink_t *sl, int halt_on_reset) { + int ret; + unsigned timeout; + uint32_t dhcsr, dfsr; + + DLOG("*** stlink_soft_reset %s***\n", halt_on_reset ? "(halt) " : ""); + + // halt core and enable debugging (if not already done) + // C_DEBUGEN is required to Halt on reset (DDI0337E, p. 10-6) + stlink_write_debug32(sl, STLINK_REG_DHCSR, + STLINK_REG_DHCSR_DBGKEY | STLINK_REG_DHCSR_C_HALT | + STLINK_REG_DHCSR_C_DEBUGEN); - // Clear errors - clear_flash_error(sl); + // enable Halt on reset by set VC_CORERESET and TRCENA (DDI0337E, p. 10-10) + if (halt_on_reset) { + stlink_write_debug32( + sl, STLINK_REG_CM3_DEMCR, + STLINK_REG_CM3_DEMCR_TRCENA | STLINK_REG_CM3_DEMCR_VC_HARDERR | + STLINK_REG_CM3_DEMCR_VC_BUSERR | STLINK_REG_CM3_DEMCR_VC_CORERESET); - ILOG("Asked to write option control register 1 %#10x to %#010x.\n", - option_control_register, FLASH_F7_OPTCR); + // clear VCATCH in the DFSR register + stlink_write_debug32(sl, STLINK_REG_DFSR, STLINK_REG_DFSR_VCATCH); + } else { + stlink_write_debug32(sl, STLINK_REG_CM3_DEMCR, + STLINK_REG_CM3_DEMCR_TRCENA | + STLINK_REG_CM3_DEMCR_VC_HARDERR | + STLINK_REG_CM3_DEMCR_VC_BUSERR); + } - /* write option byte, ensuring we dont lock opt, and set strt bit */ - stlink_write_debug32(sl, FLASH_F7_OPTCR, - (option_control_register & ~(1 << FLASH_F7_OPTCR_LOCK)) | - (1 << FLASH_F7_OPTCR_START)); + // clear S_RESET_ST in the DHCSR register + stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); - wait_flash_busy(sl); + // soft reset (core reset) by SYSRESETREQ (DDI0337E, p. 8-23) + ret = stlink_write_debug32(sl, STLINK_REG_AIRCR, + STLINK_REG_AIRCR_VECTKEY | + STLINK_REG_AIRCR_SYSRESETREQ); + if (ret) { + ELOG("Soft reset failed: error write to AIRCR\n"); + return (ret); + } - ret = check_flash_error(sl); - if (!ret) - ILOG("Wrote option bytes %#010x to %#010x!\n", option_control_register, - FLASH_F7_OPTCR); + // waiting for a reset within 500ms + // DDI0337E, p. 10-4, Debug Halting Control and Status Register + timeout = time_ms() + 500; + while (time_ms() < timeout) { + // DDI0337E, p. 10-4, Debug Halting Control and Status Register + dhcsr = STLINK_REG_DHCSR_S_RESET_ST; + stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); + if ((dhcsr & STLINK_REG_DHCSR_S_RESET_ST) == 0) { + if (halt_on_reset) { + // waiting halt by the SYSRESETREQ exception + // DDI0403E, p. C1-699, Debug Fault Status Register + dfsr = 0; + stlink_read_debug32(sl, STLINK_REG_DFSR, &dfsr); + if ((dfsr & STLINK_REG_DFSR_VCATCH) == 0) { + continue; + } + } + timeout = 0; + break; + } + } - return ret; -} + // reset DFSR register. DFSR is power-on reset only (DDI0337H, p. 7-5) + stlink_write_debug32(sl, STLINK_REG_DFSR, STLINK_REG_DFSR_CLEAR); + if (timeout) { + ELOG("Soft reset failed: timeout\n"); + return (-1); + } + return (0); +} /** - * Write option bytes - * @param sl - * @param option_byte value to write - * @return 0 on success, -ve on failure. + * Decode the version bits, originally from -sg, verified with usb + * @param sl stlink context, assumed to contain valid data in the buffer + * @param slv output parsed version object */ -static int -stlink_write_option_control_register_f0(stlink_t *sl, - uint32_t option_control_register) { - int ret = 0; - uint16_t opt_val[8]; - unsigned protection, optiondata; - uint16_t user_options, user_data, rdp; - unsigned option_offset, user_data_offset; +void _parse_version(stlink_t *sl, stlink_version_t *slv) { + sl->version.flags = 0; + + if (sl->version.stlink_v < 3) { + uint32_t b0 = sl->q_buf[0]; // lsb + uint32_t b1 = sl->q_buf[1]; + uint32_t b2 = sl->q_buf[2]; + uint32_t b3 = sl->q_buf[3]; + uint32_t b4 = sl->q_buf[4]; + uint32_t b5 = sl->q_buf[5]; // msb - ILOG("Asked to write option control register %#10x to %#010x.\n", - option_control_register, FLASH_OBR); + // b0 b1 || b2 b3 | b4 b5 + // 4b | 6b | 6b || 2B | 2B + // stlink_v | jtag_v | swim_v || st_vid | stlink_pid - /* Clear errors */ - clear_flash_error(sl); + slv->stlink_v = (b0 & 0xf0) >> 4; + slv->jtag_v = ((b0 & 0x0f) << 2) | ((b1 & 0xc0) >> 6); + slv->swim_v = b1 & 0x3f; + slv->st_vid = (b3 << 8) | b2; + slv->stlink_pid = (b5 << 8) | b4; - /* Retrieve current values */ - ret = stlink_read_debug32(sl, FLASH_OBR, &optiondata); - if (ret) { - return ret; + // ST-LINK/V1 from J11 switch to api-v2 (and support SWD) + if (slv->stlink_v == 1) { + slv->jtag_api = + slv->jtag_v > 11 ? STLINK_JTAG_API_V2 : STLINK_JTAG_API_V1; + } else { + slv->jtag_api = STLINK_JTAG_API_V2; + + // preferred API to get last R/W status from J15 + if (sl->version.jtag_v >= 15) { + sl->version.flags |= STLINK_F_HAS_GETLASTRWSTATUS2; + } + + if (sl->version.jtag_v >= 13) { + sl->version.flags |= STLINK_F_HAS_TRACE; + sl->max_trace_freq = STLINK_V2_MAX_TRACE_FREQUENCY; + } + } + } else { + // V3 uses different version format, for reference see OpenOCD source + // (that was written from docs available from ST under NDA): + // https://github.com/ntfreak/openocd/blob/a6dacdff58ef36fcdac00c53ec27f19de1fbce0d/src/jtag/drivers/stlink_usb.c#L965 + slv->stlink_v = sl->q_buf[0]; + slv->swim_v = sl->q_buf[1]; + slv->jtag_v = sl->q_buf[2]; + slv->st_vid = (uint32_t)((sl->q_buf[9] << 8) | sl->q_buf[8]); + slv->stlink_pid = (uint32_t)((sl->q_buf[11] << 8) | sl->q_buf[10]); + slv->jtag_api = STLINK_JTAG_API_V3; + /* preferred API to get last R/W status */ + sl->version.flags |= STLINK_F_HAS_GETLASTRWSTATUS2; + sl->version.flags |= STLINK_F_HAS_TRACE; + sl->max_trace_freq = STLINK_V3_MAX_TRACE_FREQUENCY; } - ret = stlink_read_debug32(sl, FLASH_WRPR, &protection); - if (ret) { - return ret; + + return; +} + +void stlink_run_at(stlink_t *sl, stm32_addr_t addr) { + stlink_write_reg(sl, addr, 15); /* pc register */ + stlink_run(sl, RUN_NORMAL); + + while (stlink_is_core_halted(sl)) { + usleep(3000000); } +} - /* Translate OBR value to flash store structure - * F0: RM0091, Option byte description, pp. 75-78 - * F1: PM0075, Option byte description, pp. 19-22 - * F3: RM0316, Option byte description, pp. 85-87 */ - switch(sl->chip_id) - { - case 0x422: /* STM32F30x */ - case 0x432: /* STM32F37x */ - case 0x438: /* STM32F303x6/8 and STM32F328 */ - case 0x446: /* STM32F303xD/E and STM32F398xE */ - case 0x439: /* STM32F302x6/8 */ - case 0x440: /* STM32F05x */ - case 0x444: /* STM32F03x */ - case 0x445: /* STM32F04x */ - case 0x448: /* STM32F07x */ - case 0x442: /* STM32F09x */ - option_offset = 6; - user_data_offset = 16; - rdp = 0x55AA; - break; - default: - option_offset = 0; - user_data_offset = 10; - rdp = 0x5AA5; - break; +/* Limit the block size to compare to 0x1800 as anything larger will stall the + * STLINK2 Maybe STLINK V1 needs smaller value! + */ +int check_file(stlink_t *sl, mapped_file_t *mf, stm32_addr_t addr) { + size_t off; + size_t n_cmp = sl->flash_pgsz; + + if (n_cmp > 0x1800) { + n_cmp = 0x1800; } - user_options = (option_control_register >> option_offset >> 2) & 0xFFFF; - user_data = (option_control_register >> user_data_offset) & 0xFFFF; + for (off = 0; off < mf->len; off += n_cmp) { + size_t aligned_size; + + size_t cmp_size = n_cmp; // adjust last page size -#define VAL_WITH_COMPLEMENT(v) (uint16_t)(((v)&0xFF) | (((~(v))<<8)&0xFF00)) + if ((off + n_cmp) > mf->len) { + cmp_size = mf->len - off; + } - opt_val[0] = (option_control_register & (1 << 1/*OPT_READOUT*/)) ? 0xFFFF : rdp; - opt_val[1] = VAL_WITH_COMPLEMENT(user_options); - opt_val[2] = VAL_WITH_COMPLEMENT(user_data); - opt_val[3] = VAL_WITH_COMPLEMENT(user_data >> 8); - opt_val[4] = VAL_WITH_COMPLEMENT(protection); - opt_val[5] = VAL_WITH_COMPLEMENT(protection >> 8); - opt_val[6] = VAL_WITH_COMPLEMENT(protection >> 16); - opt_val[7] = VAL_WITH_COMPLEMENT(protection >> 24); + aligned_size = cmp_size; -#undef VAL_WITH_COMPLEMENT + if (aligned_size & (4 - 1)) { + aligned_size = (cmp_size + 4) & ~(4 - 1); + } - /* Write bytes and check errors */ - ret = stlink_write_option_bytes_f0(sl, (uint8_t*)opt_val, STM32_F0_OPTION_BYTES_BASE, sizeof(opt_val)); - if (ret) - return ret; + stlink_read_mem32(sl, addr + (uint32_t)off, (uint16_t)aligned_size); - ret = check_flash_error(sl); - if (!ret) { - ILOG("Wrote option bytes %#010x to %#010x!\n", option_control_register, - FLASH_OBR); + if (memcmp(sl->q_buf, mf->base + off, cmp_size)) { + return (-1); + } } - return ret; + return (0); } -/** - * Write option bytes - * @param sl - * @param option_byte value to write - * @return 0 on success, -ve on failure. - */ -static int -stlink_write_option_control_register1_f7(stlink_t *sl, - uint32_t option_control_register1) { - int ret = 0; - - // Clear errors - clear_flash_error(sl); - - ILOG("Asked to write option control register 1 %#010x to %#010x.\n", - option_control_register1, FLASH_F7_OPTCR1); +void md5_calculate(mapped_file_t *mf) { + // calculate md5 checksum of given binary file + Md5Context md5Context; + MD5_HASH md5Hash; + Md5Initialise(&md5Context); + Md5Update(&md5Context, mf->base, (uint32_t)mf->len); + Md5Finalise(&md5Context, &md5Hash); + printf("md5 checksum: "); - /* write option byte, ensuring we dont lock opt, and set strt bit */ - uint32_t current_control_register_value; - stlink_read_debug32(sl, FLASH_F7_OPTCR, ¤t_control_register_value); + for (int i = 0; i < (int)sizeof(md5Hash); i++) { + printf("%x", md5Hash.bytes[i]); + } - /* write option byte */ - stlink_write_debug32(sl, FLASH_F7_OPTCR1, option_control_register1); - stlink_write_debug32( - sl, FLASH_F7_OPTCR, - (current_control_register_value & ~(1 << FLASH_F7_OPTCR_LOCK)) | - (1 << FLASH_F7_OPTCR_START)); + printf(", "); +} - wait_flash_busy(sl); +void stlink_checksum(mapped_file_t *mp) { + /* checksum that backward compatible with official ST tools */ + uint32_t sum = 0; + uint8_t *mp_byte = (uint8_t *)mp->base; - ret = check_flash_error(sl); - if (!ret) - ILOG("Wrote option bytes %#010x to %#010x!\n", option_control_register1, - FLASH_F7_OPTCR1); + for (size_t i = 0; i < mp->len; ++i) { + sum += mp_byte[i]; + } - return ret; + printf("stlink checksum: 0x%08x\n", sum); } -/** - * Write option bytes - * @param sl - * @param option_byte value to write - * @return 0 on success, -ve on failure. - */ -static int -stlink_write_option_bytes_boot_add_f7(stlink_t *sl, - uint32_t option_byte_boot_add) { - ILOG("Asked to write option byte boot add %#010x.\n", option_byte_boot_add); - return stlink_write_option_control_register1_f7(sl, option_byte_boot_add); +void stlink_fwrite_finalize(stlink_t *sl, stm32_addr_t addr) { + unsigned int val; + // set PC to the reset routine + stlink_read_debug32(sl, addr + 4, &val); + stlink_write_reg(sl, val, 15); + stlink_run(sl, RUN_NORMAL); } -/** - * Write option bytes - * @param sl - * @param option bytes boot address to write - * @return 0 on success, -ve on failure. - */ -int stlink_write_option_bytes_boot_add32(stlink_t *sl, - uint32_t option_bytes_boot_add) { - int ret = -1; - - wait_flash_busy(sl); +static int stlink_read(stlink_t *sl, stm32_addr_t addr, size_t size, + save_block_fn fn, void *fn_arg) { - if (unlock_flash_if(sl)) { - ELOG("Flash unlock failed! System reset required to be able to unlock it " - "again!\n"); - return -1; - } + int error = -1; - if (unlock_flash_option_if(sl)) { - ELOG("Flash option unlock failed!\n"); - return -1; + if (size < 1) { + size = sl->flash_size; } - switch (sl->flash_type) { - case STM32_FLASH_TYPE_F7: - ret = stlink_write_option_bytes_boot_add_f7(sl, option_bytes_boot_add); - break; - default: - ELOG("Option bytes boot address writing is currently not implemented for " - "connected chip\n"); - break; + if (size > sl->flash_size) { + size = sl->flash_size; } - if (ret) - ELOG("Flash option write failed!\n"); - else - ILOG("Wrote option bytes boot address %#010x!\n", option_bytes_boot_add); + size_t cmp_size = (sl->flash_pgsz > 0x1800) ? 0x1800 : sl->flash_pgsz; - /* Re-lock flash. */ - lock_flash_option(sl); - lock_flash(sl); + for (size_t off = 0; off < size; off += cmp_size) { + size_t aligned_size; - return ret; -} + // adjust last page size + if ((off + cmp_size) > size) { + cmp_size = size - off; + } -/** - * Write option bytes - * @param sl - * @param option bytes boot address to write - * @return 0 on success, -ve on failure. - */ -int stlink_write_option_control_register32(stlink_t *sl, - uint32_t option_control_register) { - int ret = -1; + aligned_size = cmp_size; - wait_flash_busy(sl); + if (aligned_size & (4 - 1)) { + aligned_size = (cmp_size + 4) & ~(4 - 1); + } - if (unlock_flash_if(sl)) { - ELOG("Flash unlock failed! System reset required to be able to unlock it " - "again!\n"); - return -1; - } + stlink_read_mem32(sl, addr + (uint32_t)off, (uint16_t)aligned_size); - if (unlock_flash_option_if(sl)) { - ELOG("Flash option unlock failed!\n"); - return -1; + if (!fn(fn_arg, sl->q_buf, aligned_size)) { + goto on_error; + } } - switch (sl->flash_type) { - case STM32_FLASH_TYPE_F0_F1_F3: - case STM32_FLASH_TYPE_F1_XL: - ret = stlink_write_option_control_register_f0(sl, option_control_register); - break; - case STM32_FLASH_TYPE_F7: - ret = stlink_write_option_control_register_f7(sl, option_control_register); - break; - default: - ELOG("Option control register writing is currently not implemented for " - "connected chip\n"); - break; - } + error = 0; // success - if (ret) - ELOG("Flash option write failed!\n"); - else - ILOG("Wrote option control register %#010x!\n", option_control_register); +on_error: + return (error); +} - /* Re-lock flash. */ - lock_flash_option(sl); - lock_flash(sl); +static bool stlink_fread_worker(void *arg, uint8_t *block, ssize_t len) { + struct stlink_fread_worker_arg *the_arg = + (struct stlink_fread_worker_arg *)arg; - return ret; + if (write(the_arg->fd, block, len) != len) { + fprintf(stderr, "write() != aligned_size\n"); + return (false); + } else { + return (true); + } } -/** - * Write option bytes - * @param sl - * @param option bytes boot address to write - * @return 0 on success, -ve on failure. - */ -int stlink_write_option_control_register1_32( - stlink_t *sl, uint32_t option_control_register1) { - int ret = -1; +// TODO: length not checked +static uint8_t stlink_parse_hex(const char *hex) { + uint8_t d[2]; - wait_flash_busy(sl); + for (int i = 0; i < 2; ++i) { + char c = *(hex + i); - if (unlock_flash_if(sl)) { - ELOG("Flash unlock failed! System reset required to be able to unlock it " - "again!\n"); - return -1; + if (c >= '0' && c <= '9') { + d[i] = c - '0'; + } else if (c >= 'A' && c <= 'F') { + d[i] = c - 'A' + 10; + } else if (c >= 'a' && c <= 'f') { + d[i] = c - 'a' + 10; + } else { + return (0); // error + } } - if (unlock_flash_option_if(sl)) { - ELOG("Flash option unlock failed!\n"); - return -1; - } + return ((d[0] << 4) | (d[1])); +} - switch (sl->flash_type) { - case STM32_FLASH_TYPE_F7: - ret = - stlink_write_option_control_register1_f7(sl, option_control_register1); - break; - default: - ELOG("Option control register 1 writing is currently not implemented for " - "connected chip\n"); - break; +static bool +stlink_fread_ihex_newsegment(struct stlink_fread_ihex_worker_arg *the_arg) { + uint32_t addr = the_arg->addr; + uint8_t sum = 2 + 4 + (uint8_t)((addr & 0xFF000000) >> 24) + + (uint8_t)((addr & 0x00FF0000) >> 16); + + if (17 != fprintf(the_arg->file, ":02000004%04X%02X\r\n", + (addr & 0xFFFF0000) >> 16, (uint8_t)(0x100 - sum))) { + return (false); } - if (ret) - ELOG("Flash option write failed!\n"); - else - ILOG("Wrote option control register 1 %#010x!\n", option_control_register1); + the_arg->lba = (addr & 0xFFFF0000); + return (true); +} - lock_flash_option(sl); - lock_flash(sl); +static bool +stlink_fread_ihex_writeline(struct stlink_fread_ihex_worker_arg *the_arg) { + uint8_t count = the_arg->buf_pos; - return (ret); -} + if (count == 0) { + return (true); + } -/** - * Write the given binary file with option bytes - * @param sl - * @param path readable file path, should be binary image - * @param addr of the memory mapped option bytes - * @return 0 on success, -ve on failure. - */ -int stlink_fwrite_option_bytes(stlink_t *sl, const char *path, - stm32_addr_t addr) { - /* Write the file in flash at addr */ - int err; - mapped_file_t mf = MAPPED_FILE_INITIALIZER; + uint32_t addr = the_arg->addr; - if (map_file(&mf, path) == -1) { - ELOG("map_file() == -1\n"); - return (-1); + if (the_arg->lba != (addr & 0xFFFF0000)) { // segment changed + if (!stlink_fread_ihex_newsegment(the_arg)) { + return (false); + } } - printf("file %s ", path); - md5_calculate(&mf); - stlink_checksum(&mf); + uint8_t sum = count + (uint8_t)((addr & 0x0000FF00) >> 8) + + (uint8_t)(addr & 0x000000FF); - err = stlink_write_option_bytes(sl, addr, mf.base, (uint32_t)mf.len); - stlink_fwrite_finalize(sl, addr); - unmap_file(&mf); + if (9 != fprintf(the_arg->file, ":%02X%04X00", count, (addr & 0x0000FFFF))) { + return (false); + } - return (err); -} + for (uint8_t i = 0; i < count; ++i) { + uint8_t b = the_arg->buf[i]; + sum += b; -int stlink_target_connect(stlink_t *sl, enum connect_type connect) { - if (connect == CONNECT_UNDER_RESET) { - stlink_enter_swd_mode(sl); + if (2 != fprintf(the_arg->file, "%02X", b)) { + return (false); + } + } - stlink_jtag_reset(sl, STLINK_DEBUG_APIV2_DRIVE_NRST_LOW); + if (4 != fprintf(the_arg->file, "%02X\r\n", (uint8_t)(0x100 - sum))) { + return (false); + } - // try to halt the core before reset - // this is useful if the NRST pin is not connected - sl->backend->force_debug(sl); + the_arg->addr += count; + the_arg->buf_pos = 0; - // minimum reset pulse duration of 20 us (RM0008, 8.1.2 Power reset) - usleep(20); + return (true); +} - stlink_jtag_reset(sl, STLINK_DEBUG_APIV2_DRIVE_NRST_HIGH); +static bool stlink_fread_ihex_init(struct stlink_fread_ihex_worker_arg *the_arg, + int fd, stm32_addr_t addr) { + the_arg->file = fdopen(fd, "w"); + the_arg->addr = addr; + the_arg->lba = 0; + the_arg->buf_pos = 0; - // try to halt the core after reset - unsigned timeout = time_ms() + 10; - while (time_ms() < timeout) { - sl->backend->force_debug(sl); - usleep(100); - } + return (the_arg->file != NULL); +} - // check NRST connection - uint32_t dhcsr = 0; - stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); - if ((dhcsr & STLINK_REG_DHCSR_S_RESET_ST) == 0) { - WLOG("NRST is not connected\n"); +static bool stlink_fread_ihex_worker(void *arg, uint8_t *block, ssize_t len) { + struct stlink_fread_ihex_worker_arg *the_arg = + (struct stlink_fread_ihex_worker_arg *)arg; + + for (ssize_t i = 0; i < len; ++i) { + if (the_arg->buf_pos == sizeof(the_arg->buf)) { // line is full + if (!stlink_fread_ihex_writeline(the_arg)) { + return (false); + } } - // addition soft reset for halt before the first instruction - stlink_soft_reset(sl, 1 /* halt on reset */); + the_arg->buf[the_arg->buf_pos++] = block[i]; } - if (stlink_current_mode(sl) != STLINK_DEV_DEBUG_MODE && - stlink_enter_swd_mode(sl)) { - printf("Failed to enter SWD mode\n"); - return -1; + return (true); +} + +static bool +stlink_fread_ihex_finalize(struct stlink_fread_ihex_worker_arg *the_arg) { + if (!stlink_fread_ihex_writeline(the_arg)) { + return (false); } - if (connect == CONNECT_NORMAL) { - stlink_reset(sl, RESET_AUTO); + // FIXME: do we need the Start Linear Address? + + if (13 != fprintf(the_arg->file, ":00000001FF\r\n")) { // EoF + return (false); } - return stlink_load_device_params(sl); + return (0 == fclose(the_arg->file)); } diff --git a/src/common.h b/src/common.h new file mode 100644 index 000000000..6c22d58c0 --- /dev/null +++ b/src/common.h @@ -0,0 +1,15 @@ +/* + * File: common.h + * + * TODO: add a description + */ + +#ifndef COMMON_H +#define COMMON_H + +int check_file(stlink_t *, mapped_file_t *, stm32_addr_t); +void md5_calculate(mapped_file_t *); +void stlink_checksum(mapped_file_t *); +void stlink_fwrite_finalize(stlink_t *, stm32_addr_t); + +#endif // COMMON_H diff --git a/src/common_flash.c b/src/common_flash.c new file mode 100644 index 000000000..e2a9ebbc3 --- /dev/null +++ b/src/common_flash.c @@ -0,0 +1,1375 @@ +#include +#include +#include +#include +#include "calculate.h" +#include "common_flash.h" +#include "map_file.h" +#include "common.h" + +#define DEBUG_FLASH 0 + +uint32_t get_stm32l0_flash_base(stlink_t *sl) { + switch (sl->chip_id) { + case STM32_CHIPID_L0: + case STM32_CHIPID_L0_CAT5: + case STM32_CHIPID_L0_CAT2: + case STM32_CHIPID_L011: + return (STM32L0_FLASH_REGS_ADDR); + + case STM32_CHIPID_L1_CAT2: + case STM32_CHIPID_L1_MD: + case STM32_CHIPID_L1_MD_PLUS: + case STM32_CHIPID_L1_MD_PLUS_HD: + return (STM32L_FLASH_REGS_ADDR); + + default: + WLOG("Flash base use default L0 address\n"); + return (STM32L0_FLASH_REGS_ADDR); + } +} + +uint32_t read_flash_cr(stlink_t *sl, unsigned bank) { + uint32_t reg, res; + + if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { + reg = FLASH_F4_CR; + } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { + reg = FLASH_F7_CR; + } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { + reg = STM32L4_FLASH_CR; + } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4) { + reg = STM32Gx_FLASH_CR; + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { + reg = STM32WB_FLASH_CR; + } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { + reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; + } else { + reg = (bank == BANK_1) ? FLASH_CR : FLASH_CR2; + } + + stlink_read_debug32(sl, reg, &res); + +#if DEBUG_FLASH + fprintf(stdout, "CR:0x%x\n", res); +#endif + return (res); +} + +void lock_flash(stlink_t *sl) { + uint32_t cr_lock_shift, cr_reg, n, cr2_reg = 0; + uint32_t cr_mask = 0xffffffffu; + + if (sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) { + cr_reg = FLASH_CR; + cr_lock_shift = FLASH_CR_LOCK; + } else if (sl->flash_type == STM32_FLASH_TYPE_F1_XL) { + cr_reg = FLASH_CR; + cr2_reg = FLASH_CR2; + cr_lock_shift = FLASH_CR_LOCK; + } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { + cr_reg = FLASH_F4_CR; + cr_lock_shift = FLASH_F4_CR_LOCK; + } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { + cr_reg = FLASH_F7_CR; + cr_lock_shift = FLASH_F7_CR_LOCK; + } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { + cr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF; + cr_lock_shift = STM32L0_FLASH_PELOCK; + } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { + cr_reg = STM32L4_FLASH_CR; + cr_lock_shift = STM32L4_FLASH_CR_LOCK; + } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4) { + cr_reg = STM32Gx_FLASH_CR; + cr_lock_shift = STM32Gx_FLASH_CR_LOCK; + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { + cr_reg = STM32WB_FLASH_CR; + cr_lock_shift = STM32WB_FLASH_CR_LOCK; + } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { + cr_reg = FLASH_H7_CR1; + if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { + cr2_reg = FLASH_H7_CR2; + } + cr_lock_shift = FLASH_H7_CR_LOCK; + cr_mask = ~(1u << FLASH_H7_CR_SER); + } else { + ELOG("unsupported flash method, abort\n"); + return; + } + + stlink_read_debug32(sl, cr_reg, &n); + n &= cr_mask; + n |= (1u << cr_lock_shift); + stlink_write_debug32(sl, cr_reg, n); + + if (cr2_reg) { + n = read_flash_cr(sl, BANK_2) | (1u << cr_lock_shift); + stlink_write_debug32(sl, cr2_reg, n); + } +} + +static inline int write_flash_sr(stlink_t *sl, unsigned bank, uint32_t val) { + uint32_t sr_reg; + + if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || + (sl->flash_type == STM32_FLASH_TYPE_F1_XL)) { + sr_reg = (bank == BANK_1) ? FLASH_SR : FLASH_SR2; + } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { + sr_reg = get_stm32l0_flash_base(sl) + FLASH_SR_OFF; + } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { + sr_reg = FLASH_F4_SR; + } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { + sr_reg = FLASH_F7_SR; + } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { + sr_reg = STM32L4_FLASH_SR; + } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4) { + sr_reg = STM32Gx_FLASH_SR; + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { + sr_reg = STM32WB_FLASH_SR; + } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { + sr_reg = (bank == BANK_1) ? FLASH_H7_SR1 : FLASH_H7_SR2; + } else { + ELOG("method 'write_flash_sr' is unsupported\n"); + return (-1); + } + + return stlink_write_debug32(sl, sr_reg, val); +} + +void clear_flash_error(stlink_t *sl) { + switch (sl->flash_type) { + case STM32_FLASH_TYPE_F0_F1_F3: + write_flash_sr(sl, BANK_1, FLASH_SR_ERROR_MASK); + break; + case STM32_FLASH_TYPE_F2_F4: + write_flash_sr(sl, BANK_1, FLASH_F4_SR_ERROR_MASK); + break; + case STM32_FLASH_TYPE_F7: + write_flash_sr(sl, BANK_1, FLASH_F7_SR_ERROR_MASK); + break; + case STM32_FLASH_TYPE_G0: + case STM32_FLASH_TYPE_G4: + write_flash_sr(sl, BANK_1, STM32Gx_FLASH_SR_ERROR_MASK); + break; + case STM32_FLASH_TYPE_L0_L1: + write_flash_sr(sl, BANK_1, STM32L0_FLASH_SR_ERROR_MASK); + break; + case STM32_FLASH_TYPE_L4_L4P: + write_flash_sr(sl, BANK_1, STM32L4_FLASH_SR_ERROR_MASK); + break; + case STM32_FLASH_TYPE_H7: + write_flash_sr(sl, BANK_1, FLASH_H7_SR_ERROR_MASK); + if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { + write_flash_sr(sl, BANK_2, FLASH_H7_SR_ERROR_MASK); + } + break; + case STM32_FLASH_TYPE_WB_WL: + write_flash_sr(sl, BANK_1, STM32WB_FLASH_SR_ERROR_MASK); + break; + default: + break; + } +} + +uint32_t read_flash_sr(stlink_t *sl, unsigned bank) { + uint32_t res, sr_reg; + + if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || + (sl->flash_type == STM32_FLASH_TYPE_F1_XL)) { + sr_reg = (bank == BANK_1) ? FLASH_SR : FLASH_SR2; + } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { + sr_reg = get_stm32l0_flash_base(sl) + FLASH_SR_OFF; + } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { + sr_reg = FLASH_F4_SR; + } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { + sr_reg = FLASH_F7_SR; + } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { + sr_reg = STM32L4_FLASH_SR; + } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4) { + sr_reg = STM32Gx_FLASH_SR; + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { + sr_reg = STM32WB_FLASH_SR; + } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { + sr_reg = (bank == BANK_1) ? FLASH_H7_SR1 : FLASH_H7_SR2; + } else { + ELOG("method 'read_flash_sr' is unsupported\n"); + return (-1); + } + + stlink_read_debug32(sl, sr_reg, &res); + return (res); +} + +unsigned int is_flash_busy(stlink_t *sl) { + uint32_t sr_busy_shift; + unsigned int res; + + if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || + (sl->flash_type == STM32_FLASH_TYPE_F1_XL) || + (sl->flash_type == STM32_FLASH_TYPE_L0_L1)) { + sr_busy_shift = FLASH_SR_BSY; + } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { + sr_busy_shift = FLASH_F4_SR_BSY; + } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { + sr_busy_shift = FLASH_F7_SR_BSY; + } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { + sr_busy_shift = STM32L4_FLASH_SR_BSY; + } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4) { + sr_busy_shift = STM32Gx_FLASH_SR_BSY; + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { + sr_busy_shift = STM32WB_FLASH_SR_BSY; + } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { + sr_busy_shift = FLASH_H7_SR_QW; + } else { + ELOG("method 'is_flash_busy' is unsupported\n"); + return (-1); + } + + res = read_flash_sr(sl, BANK_1) & (1 << sr_busy_shift); + + if (sl->flash_type == STM32_FLASH_TYPE_F1_XL || + (sl->flash_type == STM32_FLASH_TYPE_H7 && + sl->chip_flags & CHIP_F_HAS_DUAL_BANK)) { + res |= read_flash_sr(sl, BANK_2) & (1 << sr_busy_shift); + } + + return (res); +} + +void wait_flash_busy(stlink_t *sl) { + // TODO: add some delays here + while (is_flash_busy(sl)) + ; +} + +int check_flash_error(stlink_t *sl) { + uint32_t res = 0; + uint32_t WRPERR, PROGERR, PGAERR; + + WRPERR = PROGERR = PGAERR = 0; + + switch (sl->flash_type) { + case STM32_FLASH_TYPE_F0_F1_F3: + case STM32_FLASH_TYPE_F1_XL: + res = read_flash_sr(sl, BANK_1) & FLASH_SR_ERROR_MASK; + if (sl->flash_type == STM32_FLASH_TYPE_F1_XL) { + res |= read_flash_sr(sl, BANK_2) & FLASH_SR_ERROR_MASK; + } + WRPERR = (1 << FLASH_SR_WRPRT_ERR); + PROGERR = (1 << FLASH_SR_PG_ERR); + break; + case STM32_FLASH_TYPE_F2_F4: + res = read_flash_sr(sl, BANK_1) & FLASH_F4_SR_ERROR_MASK; + WRPERR = (1 << FLASH_F4_SR_WRPERR); + PGAERR = (1 << FLASH_F4_SR_PGAERR); + break; + case STM32_FLASH_TYPE_F7: + res = read_flash_sr(sl, BANK_1) & FLASH_F7_SR_ERROR_MASK; + WRPERR = (1 << FLASH_F7_SR_WRP_ERR); + PROGERR = (1 << FLASH_F7_SR_PGP_ERR); + break; + case STM32_FLASH_TYPE_G0: + case STM32_FLASH_TYPE_G4: + res = read_flash_sr(sl, BANK_1) & STM32Gx_FLASH_SR_ERROR_MASK; + WRPERR = (1 << STM32Gx_FLASH_SR_WRPERR); + PROGERR = (1 << STM32Gx_FLASH_SR_PROGERR); + PGAERR = (1 << STM32Gx_FLASH_SR_PGAERR); + break; + case STM32_FLASH_TYPE_L0_L1: + res = read_flash_sr(sl, BANK_1) & STM32L0_FLASH_SR_ERROR_MASK; + WRPERR = (1 << STM32L0_FLASH_SR_WRPERR); + PROGERR = (1 << STM32L0_FLASH_SR_NOTZEROERR); + PGAERR = (1 << STM32L0_FLASH_SR_PGAERR); + break; + case STM32_FLASH_TYPE_L4_L4P: + res = read_flash_sr(sl, BANK_1) & STM32L4_FLASH_SR_ERROR_MASK; + WRPERR = (1 << STM32L4_FLASH_SR_WRPERR); + PROGERR = (1 << STM32L4_FLASH_SR_PROGERR); + PGAERR = (1 << STM32L4_FLASH_SR_PGAERR); + break; + case STM32_FLASH_TYPE_H7: + res = read_flash_sr(sl, BANK_1) & FLASH_H7_SR_ERROR_MASK; + if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { + res |= read_flash_sr(sl, BANK_2) & FLASH_H7_SR_ERROR_MASK; + } + WRPERR = (1 << FLASH_H7_SR_WRPERR); + break; + case STM32_FLASH_TYPE_WB_WL: + res = read_flash_sr(sl, BANK_1) & STM32WB_FLASH_SR_ERROR_MASK; + WRPERR = (1 << STM32WB_FLASH_SR_WRPERR); + PROGERR = (1 << STM32WB_FLASH_SR_PROGERR); + PGAERR = (1 << STM32WB_FLASH_SR_PGAERR); + break; + default: + break; + } + + if (res) { + if (WRPERR && (WRPERR & res) == WRPERR) { + ELOG("Flash memory is write protected\n"); + res &= ~WRPERR; + } else if (PROGERR && (PROGERR & res) == PROGERR) { + ELOG("Flash memory contains a non-erased value\n"); + res &= ~PROGERR; + } else if (PGAERR && (PGAERR & res) == PGAERR) { + ELOG("Invalid flash address\n"); + res &= ~PGAERR; + } + + if (res) { + ELOG("Flash programming error: %#010x\n", res); + } + return (-1); + } + + return (0); +} + +static inline unsigned int is_flash_locked(stlink_t *sl) { + /* return non zero for true */ + uint32_t cr_lock_shift; + uint32_t cr_reg; + uint32_t n; + + if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || + (sl->flash_type == STM32_FLASH_TYPE_F1_XL)) { + cr_reg = FLASH_CR; + cr_lock_shift = FLASH_CR_LOCK; + } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { + cr_reg = FLASH_F4_CR; + cr_lock_shift = FLASH_F4_CR_LOCK; + } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { + cr_reg = FLASH_F7_CR; + cr_lock_shift = FLASH_F7_CR_LOCK; + } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { + cr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF; + cr_lock_shift = STM32L0_FLASH_PELOCK; + } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { + cr_reg = STM32L4_FLASH_CR; + cr_lock_shift = STM32L4_FLASH_CR_LOCK; + } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4) { + cr_reg = STM32Gx_FLASH_CR; + cr_lock_shift = STM32Gx_FLASH_CR_LOCK; + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { + cr_reg = STM32WB_FLASH_CR; + cr_lock_shift = STM32WB_FLASH_CR_LOCK; + } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { + cr_reg = FLASH_H7_CR1; + cr_lock_shift = FLASH_H7_CR_LOCK; + } else { + ELOG("unsupported flash method, abort\n"); + return (-1); + } + + stlink_read_debug32(sl, cr_reg, &n); + return (n & (1u << cr_lock_shift)); +} + +static void unlock_flash(stlink_t *sl) { + uint32_t key_reg, key2_reg = 0; + uint32_t flash_key1 = FLASH_KEY1; + uint32_t flash_key2 = FLASH_KEY2; + /* The unlock sequence consists of 2 write cycles where 2 key values are + * written to the FLASH_KEYR register. An invalid sequence results in a + * definitive lock of the FPEC block until next reset. + */ + + if (sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) { + key_reg = FLASH_KEYR; + } else if (sl->flash_type == STM32_FLASH_TYPE_F1_XL) { + key_reg = FLASH_KEYR; + key2_reg = FLASH_KEYR2; + } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { + key_reg = FLASH_F4_KEYR; + } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { + key_reg = FLASH_F7_KEYR; + } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { + key_reg = get_stm32l0_flash_base(sl) + FLASH_PEKEYR_OFF; + flash_key1 = FLASH_L0_PEKEY1; + flash_key2 = FLASH_L0_PEKEY2; + } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { + key_reg = STM32L4_FLASH_KEYR; + } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4) { + key_reg = STM32Gx_FLASH_KEYR; + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { + key_reg = STM32WB_FLASH_KEYR; + } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { + key_reg = FLASH_H7_KEYR1; + if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { + key2_reg = FLASH_H7_KEYR2; + } + } else { + ELOG("unsupported flash method, abort\n"); + return; + } + + stlink_write_debug32(sl, key_reg, flash_key1); + stlink_write_debug32(sl, key_reg, flash_key2); + + if (key2_reg) { + stlink_write_debug32(sl, key2_reg, flash_key1); + stlink_write_debug32(sl, key2_reg, flash_key2); + } +} + +/* unlock flash if already locked */ +int unlock_flash_if(stlink_t *sl) { + if (is_flash_locked(sl)) { + unlock_flash(sl); + + if (is_flash_locked(sl)) { + WLOG("Failed to unlock flash!\n"); + return (-1); + } + } + + DLOG("Successfully unlocked flash\n"); + return (0); +} + +int lock_flash_option(stlink_t *sl) { + uint32_t optlock_shift, optcr_reg, n, optcr2_reg = 0; + int active_bit_level = 1; + + switch (sl->flash_type) { + case STM32_FLASH_TYPE_F0_F1_F3: + case STM32_FLASH_TYPE_F1_XL: + optcr_reg = FLASH_CR; + optlock_shift = FLASH_CR_OPTWRE; + active_bit_level = 0; + break; + case STM32_FLASH_TYPE_F2_F4: + optcr_reg = FLASH_F4_OPTCR; + optlock_shift = FLASH_F4_OPTCR_LOCK; + break; + case STM32_FLASH_TYPE_F7: + optcr_reg = FLASH_F7_OPTCR; + optlock_shift = FLASH_F7_OPTCR_LOCK; + break; + case STM32_FLASH_TYPE_L0_L1: + optcr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF; + optlock_shift = STM32L0_FLASH_OPTLOCK; + break; + case STM32_FLASH_TYPE_L4_L4P: + optcr_reg = STM32L4_FLASH_CR; + optlock_shift = STM32L4_FLASH_CR_OPTLOCK; + break; + case STM32_FLASH_TYPE_G0: + case STM32_FLASH_TYPE_G4: + optcr_reg = STM32Gx_FLASH_CR; + optlock_shift = STM32Gx_FLASH_CR_OPTLOCK; + break; + case STM32_FLASH_TYPE_WB_WL: + optcr_reg = STM32WB_FLASH_CR; + optlock_shift = STM32WB_FLASH_CR_OPTLOCK; + break; + case STM32_FLASH_TYPE_H7: + optcr_reg = FLASH_H7_OPTCR; + optlock_shift = FLASH_H7_OPTCR_OPTLOCK; + if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) + optcr2_reg = FLASH_H7_OPTCR2; + break; + default: + ELOG("unsupported flash method, abort\n"); + return -1; + } + + stlink_read_debug32(sl, optcr_reg, &n); + + if (active_bit_level == 0) { + n &= ~(1u << optlock_shift); + } else { + n |= (1u << optlock_shift); + } + + stlink_write_debug32(sl, optcr_reg, n); + + if (optcr2_reg) { + stlink_read_debug32(sl, optcr2_reg, &n); + + if (active_bit_level == 0) { + n &= ~(1u << optlock_shift); + } else { + n |= (1u << optlock_shift); + } + + stlink_write_debug32(sl, optcr2_reg, n); + } + + return (0); +} + +static bool is_flash_option_locked(stlink_t *sl) { + uint32_t optlock_shift, optcr_reg; + int active_bit_level = 1; + uint32_t n; + + switch (sl->flash_type) { + case STM32_FLASH_TYPE_F0_F1_F3: + case STM32_FLASH_TYPE_F1_XL: + optcr_reg = FLASH_CR; + optlock_shift = FLASH_CR_OPTWRE; + active_bit_level = 0; /* bit is "option write enable", not lock */ + break; + case STM32_FLASH_TYPE_F2_F4: + optcr_reg = FLASH_F4_OPTCR; + optlock_shift = FLASH_F4_OPTCR_LOCK; + break; + case STM32_FLASH_TYPE_F7: + optcr_reg = FLASH_F7_OPTCR; + optlock_shift = FLASH_F7_OPTCR_LOCK; + break; + case STM32_FLASH_TYPE_L0_L1: + optcr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF; + optlock_shift = STM32L0_FLASH_OPTLOCK; + break; + case STM32_FLASH_TYPE_L4_L4P: + optcr_reg = STM32L4_FLASH_CR; + optlock_shift = STM32L4_FLASH_CR_OPTLOCK; + break; + case STM32_FLASH_TYPE_G0: + case STM32_FLASH_TYPE_G4: + optcr_reg = STM32Gx_FLASH_CR; + optlock_shift = STM32Gx_FLASH_CR_OPTLOCK; + break; + case STM32_FLASH_TYPE_WB_WL: + optcr_reg = STM32WB_FLASH_CR; + optlock_shift = STM32WB_FLASH_CR_OPTLOCK; + break; + case STM32_FLASH_TYPE_H7: + optcr_reg = FLASH_H7_OPTCR; + optlock_shift = FLASH_H7_OPTCR_OPTLOCK; + break; + default: + ELOG("unsupported flash method, abort\n"); + return -1; + } + + stlink_read_debug32(sl, optcr_reg, &n); + + if (active_bit_level == 0) { + return (!(n & (1u << optlock_shift))); + } + + return (n & (1u << optlock_shift)); +} + +static int unlock_flash_option(stlink_t *sl) { + uint32_t optkey_reg, optkey2_reg = 0; + uint32_t optkey1 = FLASH_OPTKEY1; + uint32_t optkey2 = FLASH_OPTKEY2; + + switch (sl->flash_type) { + case STM32_FLASH_TYPE_F0_F1_F3: + case STM32_FLASH_TYPE_F1_XL: + optkey_reg = FLASH_OPTKEYR; + optkey1 = FLASH_F0_OPTKEY1; + optkey2 = FLASH_F0_OPTKEY2; + break; + case STM32_FLASH_TYPE_F2_F4: + optkey_reg = FLASH_F4_OPT_KEYR; + break; + case STM32_FLASH_TYPE_F7: + optkey_reg = FLASH_F7_OPT_KEYR; + break; + case STM32_FLASH_TYPE_L0_L1: + optkey_reg = get_stm32l0_flash_base(sl) + FLASH_OPTKEYR_OFF; + optkey1 = FLASH_L0_OPTKEY1; + optkey2 = FLASH_L0_OPTKEY2; + break; + case STM32_FLASH_TYPE_L4_L4P: + optkey_reg = STM32L4_FLASH_OPTKEYR; + break; + case STM32_FLASH_TYPE_G0: + case STM32_FLASH_TYPE_G4: + optkey_reg = STM32Gx_FLASH_OPTKEYR; + break; + case STM32_FLASH_TYPE_WB_WL: + optkey_reg = STM32WB_FLASH_OPT_KEYR; + break; + case STM32_FLASH_TYPE_H7: + optkey_reg = FLASH_H7_OPT_KEYR; + if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) + optkey2_reg = FLASH_H7_OPT_KEYR2; + break; + default: + ELOG("unsupported flash method, abort\n"); + return (-1); + } + + stlink_write_debug32(sl, optkey_reg, optkey1); + stlink_write_debug32(sl, optkey_reg, optkey2); + + if (optkey2_reg) { + stlink_write_debug32(sl, optkey2_reg, optkey1); + stlink_write_debug32(sl, optkey2_reg, optkey2); + } + + return (0); +} + +int unlock_flash_option_if(stlink_t *sl) { + if (is_flash_option_locked(sl)) { + if (unlock_flash_option(sl)) { + ELOG("Could not unlock flash option!\n"); + return (-1); + } + + if (is_flash_option_locked(sl)) { + ELOG("Failed to unlock flash option!\n"); + return (-1); + } + } + + DLOG("Successfully unlocked flash option\n"); + return (0); +} + +void write_flash_cr_psiz(stlink_t *sl, uint32_t n, + unsigned bank) { + uint32_t cr_reg, psize_shift; + uint32_t x = read_flash_cr(sl, bank); + + if (sl->flash_type == STM32_FLASH_TYPE_H7) { + cr_reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; + psize_shift = FLASH_H7_CR_PSIZE; + } else { + cr_reg = FLASH_F4_CR; + psize_shift = 8; + } + + x &= ~(0x03 << psize_shift); + x |= (n << psize_shift); +#if DEBUG_FLASH + fprintf(stdout, "PSIZ:0x%x 0x%x\n", x, n); +#endif + stlink_write_debug32(sl, cr_reg, x); +} + +void clear_flash_cr_pg(stlink_t *sl, unsigned bank) { + uint32_t cr_reg, n; + uint32_t bit = FLASH_CR_PG; + + if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { + cr_reg = FLASH_F4_CR; + } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { + cr_reg = FLASH_F7_CR; + } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { + cr_reg = STM32L4_FLASH_CR; + } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4) { + cr_reg = STM32Gx_FLASH_CR; + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { + cr_reg = STM32WB_FLASH_CR; + } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { + cr_reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; + bit = FLASH_H7_CR_PG; + } else { + cr_reg = FLASH_CR; + } + + n = read_flash_cr(sl, bank) & ~(1 << bit); + stlink_write_debug32(sl, cr_reg, n); +} +/* ------------------------------------------------------------------------ */ + +static void wait_flash_busy_progress(stlink_t *sl) { + int i = 0; + fprintf(stdout, "Mass erasing"); + fflush(stdout); + + while (is_flash_busy(sl)) { + usleep(10000); + i++; + + if (i % 100 == 0) { + fprintf(stdout, "."); + fflush(stdout); + } + } + + fprintf(stdout, "\n"); +} + +static inline void write_flash_ar(stlink_t *sl, uint32_t n, unsigned bank) { + stlink_write_debug32(sl, (bank == BANK_1) ? FLASH_AR : FLASH_AR2, n); +} + +static inline void write_flash_cr_snb(stlink_t *sl, uint32_t n, unsigned bank) { + uint32_t cr_reg, snb_mask, snb_shift, ser_shift; + uint32_t x = read_flash_cr(sl, bank); + + if (sl->flash_type == STM32_FLASH_TYPE_H7) { + cr_reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; + snb_mask = FLASH_H7_CR_SNB_MASK; + snb_shift = FLASH_H7_CR_SNB; + ser_shift = FLASH_H7_CR_SER; + } else { + cr_reg = FLASH_F4_CR; + snb_mask = FLASH_F4_CR_SNB_MASK; + snb_shift = FLASH_F4_CR_SNB; + ser_shift = FLASH_F4_CR_SER; + } + + x &= ~snb_mask; + x |= (n << snb_shift); + x |= (1 << ser_shift); +#if DEBUG_FLASH + fprintf(stdout, "SNB:0x%x 0x%x\n", x, n); +#endif + stlink_write_debug32(sl, cr_reg, x); +} + +static void set_flash_cr_per(stlink_t *sl, unsigned bank) { + uint32_t cr_reg, val; + + if (sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4) { + cr_reg = STM32Gx_FLASH_CR; + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { + cr_reg = STM32WB_FLASH_CR; + } else { + cr_reg = (bank == BANK_1) ? FLASH_CR : FLASH_CR2; + } + + stlink_read_debug32(sl, cr_reg, &val); + val |= (1 << FLASH_CR_PER); + stlink_write_debug32(sl, cr_reg, val); +} + +static void clear_flash_cr_per(stlink_t *sl, unsigned bank) { + uint32_t cr_reg; + + if (sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4) { + cr_reg = STM32Gx_FLASH_CR; + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { + cr_reg = STM32WB_FLASH_CR; + } else { + cr_reg = (bank == BANK_1) ? FLASH_CR : FLASH_CR2; + } + + const uint32_t n = read_flash_cr(sl, bank) & ~(1 << FLASH_CR_PER); + stlink_write_debug32(sl, cr_reg, n); +} + +static inline void write_flash_cr_bker_pnb(stlink_t *sl, uint32_t n) { + stlink_write_debug32(sl, STM32L4_FLASH_SR, + 0xFFFFFFFF & ~(1 << STM32L4_FLASH_SR_BSY)); + uint32_t x = read_flash_cr(sl, BANK_1); + x &= ~STM32L4_FLASH_CR_OPBITS; + x &= ~STM32L4_FLASH_CR_PAGEMASK; + x &= ~(1 << STM32L4_FLASH_CR_MER1); + x &= ~(1 << STM32L4_FLASH_CR_MER2); + x |= (n << STM32L4_FLASH_CR_PNB); + x |= (uint32_t)(1lu << STM32L4_FLASH_CR_PER); +#if DEBUG_FLASH + fprintf(stdout, "BKER:PNB:0x%x 0x%x\n", x, n); +#endif + stlink_write_debug32(sl, STM32L4_FLASH_CR, x); +} + +static void set_flash_cr_strt(stlink_t *sl, unsigned bank) { + uint32_t val, cr_reg, cr_strt; + + if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { + cr_reg = FLASH_F4_CR; + cr_strt = 1 << FLASH_F4_CR_STRT; + } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { + cr_reg = FLASH_F7_CR; + cr_strt = 1 << FLASH_F7_CR_STRT; + } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { + cr_reg = STM32L4_FLASH_CR; + cr_strt = (1 << STM32L4_FLASH_CR_STRT); + } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4) { + cr_reg = STM32Gx_FLASH_CR; + cr_strt = (1 << STM32Gx_FLASH_CR_STRT); + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { + cr_reg = STM32WB_FLASH_CR; + cr_strt = (1 << STM32WB_FLASH_CR_STRT); + } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { + cr_reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; + cr_strt = 1 << FLASH_H7_CR_START(sl->chip_id); + } else { + cr_reg = (bank == BANK_1) ? FLASH_CR : FLASH_CR2; + cr_strt = (1 << FLASH_CR_STRT); + } + + stlink_read_debug32(sl, cr_reg, &val); + val |= cr_strt; + stlink_write_debug32(sl, cr_reg, val); +} + +static void set_flash_cr_mer(stlink_t *sl, bool v, unsigned bank) { + uint32_t val, cr_reg, cr_mer, cr_pg; + + if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { + cr_reg = FLASH_F4_CR; + cr_mer = 1 << FLASH_CR_MER; + cr_pg = 1 << FLASH_CR_PG; + } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { + cr_reg = FLASH_F7_CR; + cr_mer = 1 << FLASH_CR_MER; + cr_pg = 1 << FLASH_CR_PG; + } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { + cr_reg = STM32L4_FLASH_CR; + cr_mer = (1 << STM32L4_FLASH_CR_MER1) | (1 << STM32L4_FLASH_CR_MER2); + cr_pg = (1 << STM32L4_FLASH_CR_PG); + } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4) { + cr_reg = STM32Gx_FLASH_CR; + cr_mer = (1 << STM32Gx_FLASH_CR_MER1); + + if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { + cr_mer |= (1 << STM32Gx_FLASH_CR_MER2); + } + + cr_pg = (1 << FLASH_CR_PG); + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { + cr_reg = STM32WB_FLASH_CR; + cr_mer = (1 << FLASH_CR_MER); + cr_pg = (1 << FLASH_CR_PG); + } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { + cr_reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; + cr_mer = (1 << FLASH_H7_CR_BER); + cr_pg = (1 << FLASH_H7_CR_PG); + } else { + cr_reg = (bank == BANK_1) ? FLASH_CR : FLASH_CR2; + cr_mer = (1 << FLASH_CR_MER); + cr_pg = (1 << FLASH_CR_PG); + } + + stlink_read_debug32(sl, cr_reg, &val); + + if (val & cr_pg) { + // STM32F030 will drop MER bit if PG was set + val &= ~cr_pg; + stlink_write_debug32(sl, cr_reg, val); + } + + if (v) { + val |= cr_mer; + } else { + val &= ~cr_mer; + } + + stlink_write_debug32(sl, cr_reg, val); +} + +/** + * Erase a page of flash, assumes sl is fully populated with things like + * chip/core ids + * @param sl stlink context + * @param flashaddr an address in the flash page to erase + * @return 0 on success -ve on failure + */ +int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { + // wait for ongoing op to finish + wait_flash_busy(sl); + // clear flash IO errors + clear_flash_error(sl); + + if (sl->flash_type == STM32_FLASH_TYPE_F2_F4 || + sl->flash_type == STM32_FLASH_TYPE_F7 || + sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { + // unlock if locked + unlock_flash_if(sl); + + // select the page to erase + if ((sl->chip_id == STM32_CHIPID_L4) || + (sl->chip_id == STM32_CHIPID_L43x_L44x) || + (sl->chip_id == STM32_CHIPID_L45x_L46x) || + (sl->chip_id == STM32_CHIPID_L496x_L4A6x) || + (sl->chip_id == STM32_CHIPID_L4Rx)) { + // calculate the actual bank+page from the address + uint32_t page = calculate_L4_page(sl, flashaddr); + + fprintf(stderr, "EraseFlash - Page:0x%x Size:0x%x ", page, + stlink_calculate_pagesize(sl, flashaddr)); + + write_flash_cr_bker_pnb(sl, page); + } else if (sl->chip_id == STM32_CHIPID_F7 || + sl->chip_id == STM32_CHIPID_F76xxx) { + // calculate the actual page from the address + uint32_t sector = calculate_F7_sectornum(flashaddr); + + fprintf(stderr, "EraseFlash - Sector:0x%x Size:0x%x ", sector, + stlink_calculate_pagesize(sl, flashaddr)); + write_flash_cr_snb(sl, sector, BANK_1); + } else { + // calculate the actual page from the address + uint32_t sector = calculate_F4_sectornum(flashaddr); + + fprintf(stderr, "EraseFlash - Sector:0x%x Size:0x%x ", sector, + stlink_calculate_pagesize(sl, flashaddr)); + + // the SNB values for flash sectors in the second bank do not directly + // follow the values for the first bank on 2mb devices... + if (sector >= 12) { + sector += 4; + } + + write_flash_cr_snb(sl, sector, BANK_1); + } + + set_flash_cr_strt(sl, BANK_1); // start erase operation + wait_flash_busy(sl); // wait for completion + lock_flash(sl); // TODO: fails to program if this is in +#if DEBUG_FLASH + fprintf(stdout, "Erase Final CR:0x%x\n", read_flash_cr(sl, BANK_1)); +#endif + } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { + + uint32_t val; + uint32_t flash_regs_base = get_stm32l0_flash_base(sl); + + // check if the locks are set + stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); + + if ((val & (1 << 0)) || (val & (1 << 1))) { + // disable pecr protection + stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, + FLASH_L0_PEKEY1); + stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, + FLASH_L0_PEKEY2); + + // check pecr.pelock is cleared + stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); + + if (val & (1 << 0)) { + WLOG("pecr.pelock not clear (%#x)\n", val); + return (-1); + } + + // unlock program memory + stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, + FLASH_L0_PRGKEY1); + stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, + FLASH_L0_PRGKEY2); + + // check pecr.prglock is cleared + stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); + + if (val & (1 << 1)) { + WLOG("pecr.prglock not clear (%#x)\n", val); + return (-1); + } + } + + // set pecr.{erase,prog} + val |= (1 << 9) | (1 << 3); + stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); + + // write 0 to the first word of the page to be erased + stlink_write_debug32(sl, flashaddr, 0); + + /* MP: It is better to wait for clearing the busy bit after issuing page + * erase command, even though PM0062 recommends to wait before it. + * Test shows that a few iterations is performed in the following loop + * before busy bit is cleared. + */ + wait_flash_busy(sl); + + // reset lock bits + stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); + val |= (1 << 0) | (1 << 1) | (1 << 2); + stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL || + sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4) { + uint32_t val; + unlock_flash_if(sl); + set_flash_cr_per(sl, BANK_1); // set the 'enable Flash erase' bit + + // set the page to erase + if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { + uint32_t flash_page = + ((flashaddr - STM32_FLASH_BASE) / (uint32_t)(sl->flash_pgsz)); + stlink_read_debug32(sl, STM32WB_FLASH_CR, &val); + + // sec 3.10.5 - PNB[7:0] is offset by 3. + val &= ~(0xFF << 3); // Clear previously set page number (if any) + val |= ((flash_page & 0xFF) << 3); + + stlink_write_debug32(sl, STM32WB_FLASH_CR, val); + } else if (sl->flash_type == STM32_FLASH_TYPE_G0) { + uint32_t flash_page = + ((flashaddr - STM32_FLASH_BASE) / (uint32_t)(sl->flash_pgsz)); + stlink_read_debug32(sl, STM32Gx_FLASH_CR, &val); + // sec 3.7.5 - PNB[5:0] is offset by 3. PER is 0x2. + val &= ~(0x3F << 3); + val |= ((flash_page & 0x3F) << 3) | (1 << FLASH_CR_PER); + stlink_write_debug32(sl, STM32Gx_FLASH_CR, val); + } else if (sl->flash_type == STM32_FLASH_TYPE_G4) { + uint32_t flash_page = + ((flashaddr - STM32_FLASH_BASE) / (uint32_t)(sl->flash_pgsz)); + stlink_read_debug32(sl, STM32Gx_FLASH_CR, &val); + // sec 3.7.5 - PNB[6:0] is offset by 3. PER is 0x2. + val &= ~(0x7F << 3); + val |= ((flash_page & 0x7F) << 3) | (1 << FLASH_CR_PER); + stlink_write_debug32(sl, STM32Gx_FLASH_CR, val); + } + + set_flash_cr_strt(sl, BANK_1); // set the 'start operation' bit + wait_flash_busy(sl); // wait for the 'busy' bit to clear + clear_flash_cr_per(sl, BANK_1); // clear the 'enable page erase' bit + lock_flash(sl); + } else if (sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3 || + sl->flash_type == STM32_FLASH_TYPE_F1_XL) { + unsigned bank = (flashaddr < STM32_F1_FLASH_BANK2_BASE) ? BANK_1 : BANK_2; + unlock_flash_if(sl); + clear_flash_cr_pg(sl, bank); // clear the pg bit + set_flash_cr_per(sl, bank); // set the page erase bit + write_flash_ar(sl, flashaddr, bank); // select the page to erase + set_flash_cr_strt(sl, + bank); // start erase operation, reset by hw with busy bit + wait_flash_busy(sl); + clear_flash_cr_per(sl, bank); // clear the page erase bit + lock_flash(sl); + } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { + unsigned bank = (flashaddr < STM32_H7_FLASH_BANK2_BASE) ? BANK_1 : BANK_2; + unlock_flash_if(sl); // unlock if locked + uint32_t sector = calculate_H7_sectornum( + sl, flashaddr, bank); // calculate the actual page from the address + write_flash_cr_snb(sl, sector, bank); // select the page to erase + set_flash_cr_strt(sl, bank); // start erase operation + wait_flash_busy(sl); // wait for completion + lock_flash(sl); + } else { + WLOG("unknown coreid %x, page erase failed\n", sl->core_id); + return (-1); + } + + return check_flash_error(sl); +} + +int stlink_erase_flash_section(stlink_t *sl, stm32_addr_t base_addr, size_t size, bool align_size) { + // Check the address and size validity + if (stlink_check_address_range_validity(sl, base_addr, size) < 0) { + return -1; + } + + // Make sure the requested address is aligned with the beginning of a page + if (stlink_check_address_alignment(sl, base_addr) < 0) { + ELOG("The address to erase is not aligned with the beginning of a page\n"); + return -1; + } + + stm32_addr_t addr = base_addr; + do { + long unsigned int page_size = stlink_calculate_pagesize(sl, addr); + + // Check if size is aligned with a page, unless we want to completely erase the last page + if ((addr + page_size) > (base_addr + size) && !align_size) { + ELOG("Invalid size (not aligned with a page). Page size at address %#x is %#lx\n", addr, page_size); + return -1; + } + + if (stlink_erase_flash_page(sl, addr)) { + WLOG("Failed to erase_flash_page(%#x) == -1\n", addr); + return (-1); + } + + fprintf(stdout, "-> Flash page at %#x erased (size: %#lx)\n", addr, page_size); + fflush(stdout); + + // check the next page is within the range to erase + addr += page_size; + } while (addr < (base_addr + size)); + + fprintf(stdout, "\n"); + return 0; +} + +int stlink_erase_flash_mass(stlink_t *sl) { + int err = 0; + + // TODO: User MER bit to mass-erase WB series. + if (sl->flash_type == STM32_FLASH_TYPE_L0_L1 || + sl->flash_type == STM32_FLASH_TYPE_WB_WL) { + + err = stlink_erase_flash_section(sl, sl->flash_base, sl->flash_size, false); + + } else { + wait_flash_busy(sl); + clear_flash_error(sl); + unlock_flash_if(sl); + + if (sl->flash_type == STM32_FLASH_TYPE_H7 && + sl->chip_id != STM32_CHIPID_H7Ax) { + // set parallelism + write_flash_cr_psiz(sl, 3 /*64it*/, BANK_1); + if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { + write_flash_cr_psiz(sl, 3 /*64bit*/, BANK_2); + } + } + + set_flash_cr_mer(sl, 1, BANK_1); // set the mass erase bit + set_flash_cr_strt( + sl, BANK_1); // start erase operation, reset by hw with busy bit + + if (sl->flash_type == STM32_FLASH_TYPE_F1_XL || + (sl->flash_type == STM32_FLASH_TYPE_H7 && + sl->chip_flags & CHIP_F_HAS_DUAL_BANK)) { + set_flash_cr_mer(sl, 1, BANK_2); // set the mass erase bit in bank 2 + set_flash_cr_strt(sl, BANK_2); // start erase operation in bank 2 + } + + wait_flash_busy_progress(sl); + lock_flash(sl); + + // reset the mass erase bit + set_flash_cr_mer(sl, 0, BANK_1); + if (sl->flash_type == STM32_FLASH_TYPE_F1_XL || + (sl->flash_type == STM32_FLASH_TYPE_H7 && + sl->chip_flags & CHIP_F_HAS_DUAL_BANK)) { + set_flash_cr_mer(sl, 0, BANK_2); + } + + err = check_flash_error(sl); + } + + return (err); +} + +int stlink_mwrite_flash(stlink_t *sl, uint8_t *data, uint32_t length, + stm32_addr_t addr) { + /* Write the block in flash at addr */ + int err; + unsigned int num_empty, idx; + uint8_t erased_pattern = stlink_get_erased_pattern(sl); + + /* + * This optimisation may cause unexpected garbage data remaining. + * Therfore it is turned off by default. + */ + if (sl->opt) { + idx = (unsigned int)length; + + for (num_empty = 0; num_empty != length; ++num_empty) + if (data[--idx] != erased_pattern) { + break; + } + + num_empty -= (num_empty & 3); // Round down to words + + if (num_empty != 0) { + ILOG("Ignoring %d bytes of 0x%02x at end of file\n", num_empty, + erased_pattern); + } + } else { + num_empty = 0; + } + + /* + * TODO: investigate a kind of weird behaviour here: + * If the file is identified to be all-empty and four-bytes aligned, + * still flash the whole file even if ignoring message is printed. + */ + err = stlink_write_flash(sl, addr, data, + (num_empty == length) ? (uint32_t)length + : (uint32_t)length - num_empty, + num_empty == length); + stlink_fwrite_finalize(sl, addr); + return (err); +} + +/** + * Write the given binary file into flash at address "addr" + * @param sl + * @param path readable file path, should be binary image + * @param addr where to start writing + * @return 0 on success, -ve on failure. + */ +int stlink_fwrite_flash(stlink_t *sl, const char *path, stm32_addr_t addr) { + /* Write the file in flash at addr */ + int err; + unsigned int num_empty, idx; + uint8_t erased_pattern = stlink_get_erased_pattern(sl); + mapped_file_t mf = MAPPED_FILE_INITIALIZER; + + if (map_file(&mf, path) == -1) { + ELOG("map_file() == -1\n"); + return (-1); + } + + printf("file %s ", path); + md5_calculate(&mf); + stlink_checksum(&mf); + + if (sl->opt) { + idx = (unsigned int)mf.len; + + for (num_empty = 0; num_empty != mf.len; ++num_empty) { + if (mf.base[--idx] != erased_pattern) { + break; + } + } + + num_empty -= (num_empty & 3); // round down to words + + if (num_empty != 0) { + ILOG("Ignoring %d bytes of 0x%02x at end of file\n", num_empty, + erased_pattern); + } + } else { + num_empty = 0; + } + + /* + * TODO: investigate a kind of weird behaviour here: + * If the file is identified to be all-empty and four-bytes aligned, + * still flash the whole file even if ignoring message is printed. + */ + err = stlink_write_flash(sl, addr, mf.base, + (num_empty == mf.len) ? (uint32_t)mf.len + : (uint32_t)mf.len - num_empty, + num_empty == mf.len); + stlink_fwrite_finalize(sl, addr); + unmap_file(&mf); + return (err); +} + + +int stlink_fcheck_flash(stlink_t *sl, const char *path, stm32_addr_t addr) { + // check the contents of path are at addr + + int res; + mapped_file_t mf = MAPPED_FILE_INITIALIZER; + + if (map_file(&mf, path) == -1) { + return (-1); + } + + res = check_file(sl, &mf, addr); + unmap_file(&mf); + return (res); +} + +/** + * Verify addr..addr+len is binary identical to base...base+len + * @param sl stlink context + * @param address stm device address + * @param data host side buffer to check against + * @param length how much + * @return 0 for success, -ve for failure + */ +int stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, + unsigned length) { + size_t off; + size_t cmp_size = (sl->flash_pgsz > 0x1800) ? 0x1800 : sl->flash_pgsz; + ILOG("Starting verification of write complete\n"); + + for (off = 0; off < length; off += cmp_size) { + size_t aligned_size; + + // adjust last page size + if ((off + cmp_size) > length) { + cmp_size = length - off; + } + + aligned_size = cmp_size; + + if (aligned_size & (4 - 1)) { + aligned_size = (cmp_size + 4) & ~(4 - 1); + } + + stlink_read_mem32(sl, address + (uint32_t)off, (uint16_t)aligned_size); + + if (memcmp(sl->q_buf, data + off, cmp_size)) { + ELOG("Verification of flash failed at offset: %u\n", (unsigned int)off); + return (-1); + } + } + + ILOG("Flash written and verified! jolly good!\n"); + return (0); +} + +// Check if an address and size are within the flash +int stlink_check_address_range_validity(stlink_t *sl, stm32_addr_t addr, size_t size) { + long unsigned int logvar; + if (addr < sl->flash_base || addr >= (sl->flash_base + sl->flash_size)) { + logvar = sl->flash_base + sl->flash_size - 1; + ELOG("Invalid address, it should be within 0x%08x - 0x%08lx\n", sl->flash_base, logvar); + return (-1); + } + if ((addr + size) > (sl->flash_base + sl->flash_size)) { + logvar = sl->flash_base + sl->flash_size - addr; + ELOG("The size exceeds the size of the flash (0x%08lx bytes available)\n", logvar); + return (-1); + } + return 0; +} + +// Check if an address is aligned with the beginning of a page +int stlink_check_address_alignment(stlink_t *sl, stm32_addr_t addr) { + stm32_addr_t page = sl->flash_base; + + while (page < addr) { + page += stlink_calculate_pagesize(sl, page); + } + + if (page != addr) { + return -1; + } + + return 0; +} + +int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t *base, + uint32_t len, uint8_t eraseonly) { + int ret; + flash_loader_t fl; + ILOG("Attempting to write %d (%#x) bytes to stm32 address: %u (%#x)\n", len, + len, addr, addr); + // check addr range is inside the flash + stlink_calculate_pagesize(sl, addr); + + // Check the address and size validity + if (stlink_check_address_range_validity(sl, addr, len) < 0) { + return (-1); + } else if (len & 1) { + WLOG("unaligned len 0x%x -- padding with zero\n", len); + len += 1; + } else if (stlink_check_address_alignment(sl, addr) < 0) { + ELOG("addr not a multiple of current pagesize (%u bytes), not supported, " + "check page start address and compare with flash module organisation " + "in related ST reference manual of your device.\n", + (unsigned)(sl->flash_pgsz)); + return (-1); + } + + // make sure we've loaded the context with the chip details + stlink_core_id(sl); + + // Erase this section of the flash + if (stlink_erase_flash_section(sl, addr, len, true) < 0) { + ELOG("Failed to erase the flash prior to writing\n"); + return (-1); + } + + if (eraseonly) { + return (0); + } + + ret = stlink_flashloader_start(sl, &fl); + if (ret) + return ret; + ret = stlink_flashloader_write(sl, &fl, addr, base, len); + if (ret) + return ret; + ret = stlink_flashloader_stop(sl, &fl); + if (ret) + return ret; + + return (stlink_verify_write_flash(sl, addr, base, len)); +} diff --git a/src/common_flash.h b/src/common_flash.h new file mode 100644 index 000000000..70a6f0e04 --- /dev/null +++ b/src/common_flash.h @@ -0,0 +1,27 @@ +/* + * File: common_flash.h + * + * TODO: add a description + */ + +#ifndef COMMON_FLASH_H +#define COMMON_FLASH_H + +void lock_flash(stlink_t *); +void clear_flash_error(stlink_t *); +void wait_flash_busy(stlink_t *); +int check_flash_error(stlink_t *); +int unlock_flash_if(stlink_t *); +int lock_flash_option(stlink_t *); +int unlock_flash_option_if(stlink_t *); +void write_flash_cr_psiz(stlink_t *, uint32_t, unsigned); +void clear_flash_cr_pg(stlink_t *, unsigned); + +// TODO: move to private defines if possible + +#define BANK_1 0 +#define BANK_2 1 + +uint32_t read_flash_cr(stlink_t *, unsigned); +uint32_t get_stm32l0_flash_base(stlink_t *); +#endif // STLINK_H diff --git a/src/flashloader.c b/src/flashloader.c new file mode 100644 index 000000000..ce230d7ab --- /dev/null +++ b/src/flashloader.c @@ -0,0 +1,482 @@ +#include +#include +#include +#include "common_flash.h" + +#define L1_WRITE_BLOCK_SIZE 0x80 +#define L0_WRITE_BLOCK_SIZE 0x40 + +int stm32l1_write_half_pages(stlink_t *sl, stm32_addr_t addr, uint8_t *base, + uint32_t len, uint32_t pagesize) { + unsigned int count, off; + unsigned int num_half_pages = len / pagesize; + uint32_t val; + uint32_t flash_regs_base = get_stm32l0_flash_base(sl); + flash_loader_t fl; + bool use_loader = true; + int ret = 0; + + // enable half page write + stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); + val |= (1 << FLASH_L1_FPRG); + stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); + val |= (1 << FLASH_L1_PROG); + stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); + + wait_flash_busy(sl); + + for (count = 0; count < num_half_pages; count++) { + if (use_loader) { + ret = stlink_flash_loader_run(sl, &fl, addr + count * pagesize, + base + count * pagesize, pagesize); + if (ret && count == 0) { + /* It seems that stm32lx devices have a problem when it is blank */ + WLOG("Failed to use flash loader, fallback to soft write\n"); + use_loader = false; + } + } + if (!use_loader) { + ret = 0; + for (off = 0; off < pagesize && !ret; off += 64) { + size_t chunk = (pagesize - off > 64) ? 64 : pagesize - off; + memcpy(sl->q_buf, base + count * pagesize + off, chunk); + ret = stlink_write_mem32(sl, addr + count * pagesize + off, (uint16_t)chunk); + } + } + + if (ret) { + WLOG("l1_stlink_flash_loader_run(%#x) failed! == -1\n", + addr + count * pagesize); + break; + } + + if (sl->verbose >= 1) { + // show progress; writing procedure is slow and previous errors are + // misleading + fprintf(stdout, "\r%3u/%u halfpages written", count + 1, num_half_pages); + fflush(stdout); + } + + // wait for sr.busy to be cleared + wait_flash_busy(sl); + } + + // disable half page write + stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); + val &= ~((1 << FLASH_L1_FPRG) | (1 << FLASH_L1_PROG)); + stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); + return (ret); +} + +static void set_flash_cr_pg(stlink_t *sl, unsigned bank) { + uint32_t cr_reg, x; + + x = read_flash_cr(sl, bank); + + if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { + cr_reg = FLASH_F4_CR; + x |= 1 << FLASH_CR_PG; + } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { + cr_reg = FLASH_F7_CR; + x |= 1 << FLASH_CR_PG; + } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { + cr_reg = STM32L4_FLASH_CR; + x &= ~STM32L4_FLASH_CR_OPBITS; + x |= (1 << STM32L4_FLASH_CR_PG); + } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4) { + cr_reg = STM32Gx_FLASH_CR; + x |= (1 << FLASH_CR_PG); + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { + cr_reg = STM32WB_FLASH_CR; + x |= (1 << FLASH_CR_PG); + } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { + cr_reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; + x |= (1 << FLASH_H7_CR_PG); + } else { + cr_reg = FLASH_CR; + x = (1 << FLASH_CR_PG); + } + + stlink_write_debug32(sl, cr_reg, x); +} + +static void set_dma_state(stlink_t *sl, flash_loader_t *fl, int bckpRstr) { + uint32_t rcc, rcc_dma_mask, value; + + rcc = rcc_dma_mask = value = 0; + + switch (sl->flash_type) { + case STM32_FLASH_TYPE_F0_F1_F3: + case STM32_FLASH_TYPE_F1_XL: + rcc = STM32F1_RCC_AHBENR; + rcc_dma_mask = STM32F1_RCC_DMAEN; + break; + case STM32_FLASH_TYPE_F2_F4: + case STM32_FLASH_TYPE_F7: + rcc = STM32F4_RCC_AHB1ENR; + rcc_dma_mask = STM32F4_RCC_DMAEN; + break; + case STM32_FLASH_TYPE_G0: + rcc = STM32G0_RCC_AHBENR; + rcc_dma_mask = STM32G0_RCC_DMAEN; + break; + case STM32_FLASH_TYPE_G4: + case STM32_FLASH_TYPE_L4_L4P: + rcc = STM32G4_RCC_AHB1ENR; + rcc_dma_mask = STM32G4_RCC_DMAEN; + break; + case STM32_FLASH_TYPE_L0_L1: + rcc = STM32L0_RCC_AHBENR; + rcc_dma_mask = STM32L0_RCC_DMAEN; + break; + case STM32_FLASH_TYPE_H7: + rcc = STM32H7_RCC_AHB1ENR; + rcc_dma_mask = STM32H7_RCC_DMAEN; + break; + case STM32_FLASH_TYPE_WB_WL: + rcc = STM32WB_RCC_AHB1ENR; + rcc_dma_mask = STM32WB_RCC_DMAEN; + break; + default: + return; + } + + if (!stlink_read_debug32(sl, rcc, &value)) { + if (bckpRstr) { + value = (value & (~rcc_dma_mask)) | fl->rcc_dma_bkp; + } else { + fl->rcc_dma_bkp = value & rcc_dma_mask; + value &= ~rcc_dma_mask; + } + stlink_write_debug32(sl, rcc, value); + } +} + +int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { + // disable DMA + set_dma_state(sl, fl, 0); + + // wait for ongoing op to finish + wait_flash_busy(sl); + // Clear errors + clear_flash_error(sl); + + if ((sl->flash_type == STM32_FLASH_TYPE_F2_F4) || + (sl->flash_type == STM32_FLASH_TYPE_F7) || + (sl->flash_type == STM32_FLASH_TYPE_L4_L4P)) { + ILOG("Starting Flash write for F2/F4/F7/L4\n"); + + // Flash loader initialisation + if (stlink_flash_loader_init(sl, fl) == -1) { + ELOG("stlink_flash_loader_init() == -1\n"); + return (-1); + } + + unlock_flash_if(sl); // first unlock the cr + + int voltage; + if (sl->version.stlink_v == 1) { + WLOG("STLINK V1 cannot read voltage, use default voltage 3.2V\n"); + voltage = 3200; + } else { + voltage = stlink_target_voltage(sl); + } + + if (voltage == -1) { + ELOG("Failed to read Target voltage\n"); + return (-1); + } + + if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { + // L4 does not have a byte-write mode + if (voltage < 1710) { + ELOG("Target voltage (%d mV) too low for flash writes!\n", voltage); + return (-1); + } + } else { + if (voltage > 2700) { + ILOG("enabling 32-bit flash writes\n"); + write_flash_cr_psiz(sl, 2, BANK_1); + } else { + ILOG("Target voltage (%d mV) too low for 32-bit flash, " + "using 8-bit flash writes\n", + voltage); + write_flash_cr_psiz(sl, 0, BANK_1); + } + } + + // set programming mode + set_flash_cr_pg(sl, BANK_1); + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL || + sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4) { + ILOG("Starting Flash write for WB/G0/G4\n"); + + unlock_flash_if(sl); // unlock flash if necessary + set_flash_cr_pg(sl, BANK_1); // set PG 'allow programming' bit + } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { + ILOG("Starting Flash write for L0\n"); + + uint32_t val; + uint32_t flash_regs_base = get_stm32l0_flash_base(sl); + + // disable pecr protection + stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, + FLASH_L0_PEKEY1); + stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, + FLASH_L0_PEKEY2); + + // check pecr.pelock is cleared + stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); + if (val & (1 << 0)) { + ELOG("pecr.pelock not clear\n"); + return (-1); + } + + // unlock program memory + stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, + FLASH_L0_PRGKEY1); + stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, + FLASH_L0_PRGKEY2); + + // check pecr.prglock is cleared + stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); + if (val & (1 << 1)) { + ELOG("pecr.prglock not clear\n"); + return (-1); + } + + /* Flash loader initialisation */ + if (stlink_flash_loader_init(sl, fl) == -1) { + // L0/L1 have fallback to soft write + WLOG("stlink_flash_loader_init() == -1\n"); + } + } else if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || + (sl->flash_type == STM32_FLASH_TYPE_F1_XL)) { + ILOG("Starting Flash write for VL/F0/F3/F1_XL\n"); + + // flash loader initialisation + if (stlink_flash_loader_init(sl, fl) == -1) { + ELOG("stlink_flash_loader_init() == -1\n"); + return (-1); + } + + // unlock flash + unlock_flash_if(sl); + + // set programming mode + set_flash_cr_pg(sl, BANK_1); + if (sl->flash_type == STM32_FLASH_TYPE_F1_XL) { + set_flash_cr_pg(sl, BANK_2); + } + } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { + ILOG("Starting Flash write for H7\n"); + + unlock_flash_if(sl); // unlock the cr + set_flash_cr_pg(sl, BANK_1); // set programming mode + if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { + set_flash_cr_pg(sl, BANK_2); + } + if (sl->chip_id != STM32_CHIPID_H7Ax) { + // set parallelism + write_flash_cr_psiz(sl, 3 /*64it*/, BANK_1); + if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { + write_flash_cr_psiz(sl, 3 /*64bit*/, BANK_2); + } + } + } else { + ELOG("unknown coreid, not sure how to write: %x\n", sl->core_id); + return (-1); + } + + return (0); +} + +int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, + stm32_addr_t addr, uint8_t *base, uint32_t len) { + size_t off; + if ((sl->flash_type == STM32_FLASH_TYPE_F2_F4) || + (sl->flash_type == STM32_FLASH_TYPE_F7) || + (sl->flash_type == STM32_FLASH_TYPE_L4_L4P)) { + size_t buf_size = (sl->sram_size > 0x8000) ? 0x8000 : 0x4000; + for (off = 0; off < len;) { + size_t size = len - off > buf_size ? buf_size : len - off; + if (stlink_flash_loader_run(sl, fl, addr + (uint32_t)off, base + off, + size) == -1) { + ELOG("stlink_flash_loader_run(%#x) failed! == -1\n", + (unsigned)(addr + off)); + check_flash_error(sl); + return (-1); + } + + off += size; + } + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL || + sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4) { + DLOG("Starting %3u page write\r\n", (unsigned int)(len / sl->flash_pgsz)); + for (off = 0; off < len; off += sizeof(uint32_t)) { + uint32_t data; + + if ((off % sl->flash_pgsz) > (sl->flash_pgsz - 5)) { + fprintf(stdout, "\r%3u/%3u pages written", + (unsigned int)(off / sl->flash_pgsz), + (unsigned int)(len / sl->flash_pgsz)); + fflush(stdout); + } + + write_uint32((unsigned char *)&data, *(uint32_t *)(base + off)); + stlink_write_debug32(sl, addr + (uint32_t)off, data); + wait_flash_busy(sl); // wait for 'busy' bit in FLASH_SR to clear + } + fprintf(stdout, "\n"); + + // flash writes happen as 2 words at a time + if ((off / sizeof(uint32_t)) % 2 != 0) { + stlink_write_debug32(sl, addr + (uint32_t)off, + 0); // write a single word of zeros + wait_flash_busy(sl); // wait for 'busy' bit in FLASH_SR to clear + } + } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { + uint32_t val; + uint32_t flash_regs_base = get_stm32l0_flash_base(sl); + uint32_t pagesize = (flash_regs_base==STM32L0_FLASH_REGS_ADDR)? + L0_WRITE_BLOCK_SIZE:L1_WRITE_BLOCK_SIZE; + + DLOG("Starting %3u page write\r\n", (unsigned int)(len / sl->flash_pgsz)); + + off = 0; + + if (len > pagesize) { + if (stm32l1_write_half_pages(sl, addr, base, len, pagesize)) { + return (-1); + } else { + off = (size_t)(len / pagesize) * pagesize; + } + } + + // write remaining word in program memory + for (; off < len; off += sizeof(uint32_t)) { + uint32_t data; + + if ((off % sl->flash_pgsz) > (sl->flash_pgsz - 5)) { + fprintf(stdout, "\r%3u/%3u pages written", + (unsigned int)(off / sl->flash_pgsz), + (unsigned int)(len / sl->flash_pgsz)); + fflush(stdout); + } + + write_uint32((unsigned char *)&data, *(uint32_t *)(base + off)); + stlink_write_debug32(sl, addr + (uint32_t)off, data); + + // wait for sr.busy to be cleared + do { + stlink_read_debug32(sl, flash_regs_base + FLASH_SR_OFF, &val); + } while ((val & (1 << 0)) != 0); + + // TODO: check redo write operation + } + fprintf(stdout, "\n"); + } else if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || + (sl->flash_type == STM32_FLASH_TYPE_F1_XL)) { + int write_block_count = 0; + for (off = 0; off < len; off += sl->flash_pgsz) { + // adjust last write size + size_t size = len - off > sl->flash_pgsz ? sl->flash_pgsz : len - off; + + // unlock and set programming mode + unlock_flash_if(sl); + + DLOG("Finished unlocking flash, running loader!\n"); + + if (stlink_flash_loader_run(sl, fl, addr + (uint32_t)off, base + off, + size) == -1) { + ELOG("stlink_flash_loader_run(%#x) failed! == -1\n", + (unsigned)(addr + off)); + check_flash_error(sl); + return (-1); + } + + lock_flash(sl); + + if (sl->verbose >= 1) { + // show progress; writing procedure is slow and previous errors are + // misleading + fprintf(stdout, "\r%3u/%3u pages written", ++write_block_count, + (unsigned int)((len + sl->flash_pgsz - 1) / sl->flash_pgsz)); + fflush(stdout); + } + } + if (sl->verbose >= 1) { + fprintf(stdout, "\n"); + } + } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { + for (off = 0; off < len;) { + // Program STM32H7x with 64-byte Flash words + size_t chunk = (len - off > 64) ? 64 : len - off; + memcpy(sl->q_buf, base + off, chunk); + stlink_write_mem32(sl, addr + (uint32_t)off, 64); + wait_flash_busy(sl); + + off += chunk; + + if (sl->verbose >= 1) { + // show progress + fprintf(stdout, "\r%u/%u bytes written", (unsigned int)off, + (unsigned int)len); + fflush(stdout); + } + } + if (sl->verbose >= 1) { + fprintf(stdout, "\n"); + } + } else { + return (-1); + } + + return check_flash_error(sl); +} + +int stlink_flashloader_stop(stlink_t *sl, flash_loader_t *fl) { + uint32_t dhcsr; + + if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || + (sl->flash_type == STM32_FLASH_TYPE_F1_XL) || + (sl->flash_type == STM32_FLASH_TYPE_F2_F4) || + (sl->flash_type == STM32_FLASH_TYPE_F7) || + (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) || + (sl->flash_type == STM32_FLASH_TYPE_WB_WL) || + (sl->flash_type == STM32_FLASH_TYPE_G0) || + (sl->flash_type == STM32_FLASH_TYPE_G4) || + (sl->flash_type == STM32_FLASH_TYPE_H7)) { + + clear_flash_cr_pg(sl, BANK_1); + if ((sl->flash_type == STM32_FLASH_TYPE_H7 && + sl->chip_flags & CHIP_F_HAS_DUAL_BANK) || + sl->flash_type == STM32_FLASH_TYPE_F1_XL) { + clear_flash_cr_pg(sl, BANK_2); + } + lock_flash(sl); + } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { + uint32_t val; + uint32_t flash_regs_base = get_stm32l0_flash_base(sl); + + // reset lock bits + stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); + val |= (1 << 0) | (1 << 1) | (1 << 2); + stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); + } + + // enable interrupt + if (!stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr)) { + stlink_write_debug32(sl, STLINK_REG_DHCSR, + STLINK_REG_DHCSR_DBGKEY | STLINK_REG_DHCSR_C_DEBUGEN | + (dhcsr & (~STLINK_REG_DHCSR_C_MASKINTS))); + } + + // restore DMA state + set_dma_state(sl, fl, 1); + + return (0); +} diff --git a/src/map_file.c b/src/map_file.c new file mode 100644 index 000000000..17697c1da --- /dev/null +++ b/src/map_file.c @@ -0,0 +1,62 @@ +#include +#include +#include +#include +#include + +#include "map_file.h" + +#ifndef MAX_FILE_SIZE +#define MAX_FILE_SIZE (1<<20) // 1 GB max file size +#endif + +#ifndef O_BINARY +#define O_BINARY 0 +#endif + +int map_file(mapped_file_t *mf, const char *path) { + int error = -1; + struct stat st; + + const int fd = open(path, O_RDONLY | O_BINARY); + + if (fd == -1) { + fprintf(stderr, "open(%s) == -1\n", path); + return (-1); + } + + if (fstat(fd, &st) == -1) { + fprintf(stderr, "fstat(%s) == -1\n", path); + goto on_error; + } + + if (sizeof(st.st_size) != sizeof(size_t)) { + // on 32 bit systems, check if there is an overflow + if (st.st_size > (off_t)MAX_FILE_SIZE /*1 GB*/ ) { + // limit file size to 1 GB + fprintf(stderr, "mmap() size_t overflow for file %s\n", path); + goto on_error; + } + } + + mf->base = + (uint8_t *)mmap(NULL, (size_t)(st.st_size), PROT_READ, MAP_SHARED, fd, 0); + + if (mf->base == MAP_FAILED) { + fprintf(stderr, "mmap() == MAP_FAILED for file %s\n", path); + goto on_error; + } + + mf->len = (size_t)st.st_size; + error = 0; // success + +on_error: + close(fd); + return (error); +} + +void unmap_file(mapped_file_t *mf) { + munmap((void *)mf->base, mf->len); + mf->base = (unsigned char *)MAP_FAILED; + mf->len = 0; +} diff --git a/src/map_file.h b/src/map_file.h new file mode 100644 index 000000000..9cdd745e6 --- /dev/null +++ b/src/map_file.h @@ -0,0 +1,32 @@ +/* + * File: map_file.h + * + * TODO: add a description + */ + +#ifndef MAP_FILE_H +#define MAP_FILE_H + +#ifndef O_BINARY +#define O_BINARY 0 +#endif + +#ifdef STLINK_HAVE_SYS_MMAN_H +#include +#else +#include +#endif + +/* Memory mapped file */ +typedef struct mapped_file { + uint8_t *base; + size_t len; +} mapped_file_t; + +#define MAPPED_FILE_INITIALIZER \ + { NULL, 0 } + +int map_file(mapped_file_t *, const char *); +void unmap_file(mapped_file_t *); + +#endif // MAP_FILE_H diff --git a/src/option.c b/src/option.c new file mode 100644 index 000000000..bd792b4a9 --- /dev/null +++ b/src/option.c @@ -0,0 +1,1027 @@ +#include +#include +#include +#include "common_flash.h" +#include "map_file.h" +#include "common.h" + +/** + * Read option bytes + * @param sl + * @param option_byte value to write + * @return 0 on success, -ve on failure. + */ +int stlink_read_option_control_register_Gx(stlink_t *sl, + uint32_t *option_byte) { + return stlink_read_debug32(sl, STM32Gx_FLASH_OPTR, option_byte); +} + +/** + * Read option bytes + * @param sl + * @param option_byte value to write + * @return 0 on success, -ve on failure. + */ +int stlink_read_option_bytes_Gx(stlink_t *sl, uint32_t *option_byte) { + return stlink_read_option_control_register_Gx(sl, option_byte); +} + +/** + * Read first option bytes + * @param sl + * @param option_byte option value + * @return 0 on success, -ve on failure. + */ +int stlink_read_option_bytes_generic(stlink_t *sl, uint32_t *option_byte) { + DLOG("@@@@ Read option bytes boot address from %#10x\n", sl->option_base); + return stlink_read_debug32(sl, sl->option_base, option_byte); +} + +/** + * Read option bytes + * @param sl + * @param option_byte value to write + * @return 0 on success, -ve on failure. + */ +int stlink_read_option_control_register_f2(stlink_t *sl, + uint32_t *option_byte) { + return stlink_read_debug32(sl, FLASH_F2_OPT_CR, option_byte); +} + +/** + * Read option bytes + * @param sl + * @param option_byte value to write + * @return 0 on success, -ve on failure. + */ +int stlink_read_option_bytes_f2(stlink_t *sl, uint32_t *option_byte) { + return stlink_read_option_control_register_f2(sl, option_byte); +} + +/** + * Read option bytes + * @param sl + * @param option_byte value to read + * @return 0 on success, -ve on failure. + */ +int stlink_read_option_control_register_f4(stlink_t *sl, + uint32_t *option_byte) { + return stlink_read_debug32(sl, FLASH_F4_OPTCR, option_byte); +} + +/** + * Read option bytes + * @param sl + * @param option_byte value to read + * @return 0 on success, -ve on failure. + */ +int stlink_read_option_bytes_f4(stlink_t *sl, uint32_t *option_byte) { + return stlink_read_option_control_register_f4(sl, option_byte); +} + +/** + * Read option bytes + * @param sl + * @param option_byte value to read + * @return 0 on success, -ve on failure. + * + * Since multiple bytes can be read, we read and print all but one here + * and then return the last one just like other devices + */ +int stlink_read_option_bytes_f7(stlink_t *sl, uint32_t *option_byte) { + int err = -1; + for (uint32_t counter = 0; counter < (sl->option_size / 4 - 1); counter++) { + err = stlink_read_debug32(sl, sl->option_base + counter * sizeof(uint32_t), + option_byte); + if (err == -1) { + return err; + } else { + printf("%08x\n", *option_byte); + } + } + + return stlink_read_debug32( + sl, + sl->option_base + (uint32_t)(sl->option_size / 4 - 1) * sizeof(uint32_t), + option_byte); +} + +/** + * Read option bytes + * @param sl + * @param option_byte option value + * @return 0 on success, -ve on failure. + */ +int stlink_read_option_bytes32(stlink_t *sl, uint32_t *option_byte) { + if (sl->option_base == 0) { + ELOG("Option bytes read is currently not supported for connected chip\n"); + return (-1); + } + + switch (sl->chip_id) { + case STM32_CHIPID_F2: + return stlink_read_option_bytes_f2(sl, option_byte); + case STM32_CHIPID_F4: + case STM32_CHIPID_F446: + return stlink_read_option_bytes_f4(sl, option_byte); + case STM32_CHIPID_F76xxx: + return stlink_read_option_bytes_f7(sl, option_byte); + case STM32_CHIPID_G0_CAT1: + case STM32_CHIPID_G0_CAT2: + case STM32_CHIPID_G4_CAT2: + case STM32_CHIPID_G4_CAT3: + return stlink_read_option_bytes_Gx(sl, option_byte); + default: + return stlink_read_option_bytes_generic(sl, option_byte); + } +} + + +/** + * Write option bytes + * @param sl + * @param base option bytes to write + * @param addr of the memory mapped option bytes + * @param len of options bytes to write + * @return 0 on success, -ve on failure. + */ +static int stlink_write_option_bytes_f0( + stlink_t *sl, uint8_t* base, stm32_addr_t addr, uint32_t len) { + int ret = 0; + + if (len < 12 || addr != STM32_F0_OPTION_BYTES_BASE) { + WLOG("Only full write of option bytes area is supported\n"); + return -1; + } + + clear_flash_error(sl); + + WLOG("Erasing option bytes\n"); + + /* erase option bytes */ + stlink_write_debug32(sl, FLASH_CR, (1 << FLASH_CR_OPTER) | (1 << FLASH_CR_OPTWRE)); + ret = stlink_write_debug32(sl, FLASH_CR, (1 << FLASH_CR_OPTER) | (1 << FLASH_CR_STRT) | (1 << FLASH_CR_OPTWRE)); + if (ret) { + return ret; + } + + wait_flash_busy(sl); + + ret = check_flash_error(sl); + if (ret) { + return ret; + } + + WLOG("Writing option bytes to %#10x\n", addr); + + /* Set the Option PG bit to enable programming */ + stlink_write_debug32(sl, FLASH_CR, (1 << FLASH_CR_OPTPG) | (1 << FLASH_CR_OPTWRE)); + + /* Use flash loader for write OP + * because flash memory writable by half word */ + flash_loader_t fl; + ret = stlink_flash_loader_init(sl, &fl); + if (ret) { + return ret; + } + ret = stlink_flash_loader_run(sl, &fl, addr, base, len); + if (ret) { + return ret; + } + + /* Reload option bytes */ + stlink_write_debug32(sl, FLASH_CR, (1 << FLASH_CR_OBL_LAUNCH)); + + return check_flash_error(sl); +} + +/** + * Write option bytes + * @param sl + * @param addr of the memory mapped option bytes + * @param base option bytes to write + * @return 0 on success, -ve on failure. + */ +static int stlink_write_option_bytes_gx(stlink_t *sl, uint8_t *base, + stm32_addr_t addr, uint32_t len) { + /* Write options bytes */ + uint32_t val; + int ret = 0; + (void)len; + uint32_t data; + + clear_flash_error(sl); + + write_uint32((unsigned char *)&data, *(uint32_t *)(base)); + WLOG("Writing option bytes %#10x to %#10x\n", data, addr); + stlink_write_debug32(sl, STM32Gx_FLASH_OPTR, data); + + // Set Options Start bit + stlink_read_debug32(sl, STM32Gx_FLASH_CR, &val); + val |= (1 << STM32Gx_FLASH_CR_OPTSTRT); + stlink_write_debug32(sl, STM32Gx_FLASH_CR, val); + + wait_flash_busy(sl); + + ret = check_flash_error(sl); + + // Reload options + stlink_read_debug32(sl, STM32Gx_FLASH_CR, &val); + val |= (1 << STM32Gx_FLASH_CR_OBL_LAUNCH); + stlink_write_debug32(sl, STM32Gx_FLASH_CR, val); + + return (ret); +} + +/** + * Write option bytes + * @param sl + * @param addr of the memory mapped option bytes + * @param base option bytes to write + * @return 0 on success, -ve on failure. + */ +static int stlink_write_option_bytes_l0(stlink_t *sl, uint8_t *base, + stm32_addr_t addr, uint32_t len) { + uint32_t flash_base = get_stm32l0_flash_base(sl); + uint32_t val; + uint32_t data; + int ret = 0; + + // Clear errors + clear_flash_error(sl); + + while (len != 0) { + write_uint32((unsigned char *)&data, + *(uint32_t *)(base)); // write options bytes + + WLOG("Writing option bytes %#10x to %#10x\n", data, addr); + stlink_write_debug32(sl, addr, data); + wait_flash_busy(sl); + + if ((ret = check_flash_error(sl))) { + break; + } + + len -= 4; + addr += 4; + base += 4; + } + + // Reload options + stlink_read_debug32(sl, flash_base + FLASH_PECR_OFF, &val); + val |= (1 << STM32L0_FLASH_OBL_LAUNCH); + stlink_write_debug32(sl, flash_base + FLASH_PECR_OFF, val); + + return (ret); +} + +/** + * Write option bytes + * @param sl + * @param addr of the memory mapped option bytes + * @param base option bytes to write + * @return 0 on success, -ve on failure. + */ +static int stlink_write_option_bytes_l4(stlink_t *sl, uint8_t *base, + stm32_addr_t addr, uint32_t len) { + + uint32_t val; + int ret = 0; + (void)addr; + (void)len; + + // Clear errors + clear_flash_error(sl); + + // write options bytes + uint32_t data; + write_uint32((unsigned char *)&data, *(uint32_t *)(base)); + WLOG("Writing option bytes 0x%04x\n", data); + stlink_write_debug32(sl, STM32L4_FLASH_OPTR, data); + + // set options start bit + stlink_read_debug32(sl, STM32L4_FLASH_CR, &val); + val |= (1 << STM32L4_FLASH_CR_OPTSTRT); + stlink_write_debug32(sl, STM32L4_FLASH_CR, val); + + wait_flash_busy(sl); + ret = check_flash_error(sl); + + // apply options bytes immediate + stlink_read_debug32(sl, STM32L4_FLASH_CR, &val); + val |= (1 << STM32L4_FLASH_CR_OBL_LAUNCH); + stlink_write_debug32(sl, STM32L4_FLASH_CR, val); + + return (ret); +} + +/** + * Write option bytes + * @param sl + * @param option_byte value to write + * @return 0 on success, -ve on failure. + */ +static int stlink_write_option_bytes_f4(stlink_t *sl, uint8_t *base, + stm32_addr_t addr, uint32_t len) { + uint32_t option_byte; + int ret = 0; + (void)addr; + (void)len; + + // Clear errors + clear_flash_error(sl); + + write_uint32((unsigned char *)&option_byte, *(uint32_t *)(base)); + + // write option byte, ensuring we dont lock opt, and set strt bit + stlink_write_debug32(sl, FLASH_F4_OPTCR, + (option_byte & ~(1 << FLASH_F4_OPTCR_LOCK)) | + (1 << FLASH_F4_OPTCR_START)); + + wait_flash_busy(sl); + ret = check_flash_error(sl); + + // option bytes are reloaded at reset only, no obl. */ + return (ret); +} + +/** + * Write option bytes + * @param sl + * @param option_byte value to write + * @return 0 on success, -ve on failure. + */ +static int stlink_write_option_bytes_f7(stlink_t *sl, uint8_t *base, + stm32_addr_t addr, uint32_t len) { + uint32_t option_byte; + int ret = 0; + + // Clear errors + clear_flash_error(sl); + + ILOG("Asked to write option byte %#10x to %#010x.\n", *(uint32_t *)(base), + addr); + write_uint32((unsigned char *)&option_byte, *(uint32_t *)(base)); + ILOG("Write %d option bytes %#010x to %#010x!\n", len, option_byte, addr); + + if (addr == 0) { + addr = FLASH_F7_OPTCR; + ILOG("No address provided, using %#10x\n", addr); + } + + if (addr == FLASH_F7_OPTCR) { + /* write option byte, ensuring we dont lock opt, and set strt bit */ + stlink_write_debug32(sl, FLASH_F7_OPTCR, + (option_byte & ~(1 << FLASH_F7_OPTCR_LOCK)) | + (1 << FLASH_F7_OPTCR_START)); + } else if (addr == FLASH_F7_OPTCR1) { + // Read FLASH_F7_OPTCR + uint32_t oldvalue; + stlink_read_debug32(sl, FLASH_F7_OPTCR, &oldvalue); + /* write option byte */ + stlink_write_debug32(sl, FLASH_F7_OPTCR1, option_byte); + // Write FLASH_F7_OPTCR lock and start address + stlink_write_debug32(sl, FLASH_F7_OPTCR, + (oldvalue & ~(1 << FLASH_F7_OPTCR_LOCK)) | + (1 << FLASH_F7_OPTCR_START)); + } else { + WLOG("WIP: write %#010x to address %#010x\n", option_byte, addr); + stlink_write_debug32(sl, addr, option_byte); + } + + wait_flash_busy(sl); + + ret = check_flash_error(sl); + if (!ret) + ILOG("Wrote %d option bytes %#010x to %#010x!\n", len, *(uint32_t *)base, + addr); + + /* option bytes are reloaded at reset only, no obl. */ + + return ret; +} + +/** + * Write STM32H7xx option bytes + * @param sl + * @param base option bytes to write + * @param addr of the memory mapped option bytes + * @param len number of bytes to write (must be multiple of 4) + * @return 0 on success, -ve on failure. + */ +static int stlink_write_option_bytes_h7(stlink_t *sl, uint8_t *base, + stm32_addr_t addr, uint32_t len) { + uint32_t val; + uint32_t data; + + // Wait until previous flash option has completed + wait_flash_busy(sl); + + // Clear previous error + stlink_write_debug32(sl, FLASH_H7_OPTCCR, + 1 << FLASH_H7_OPTCCR_CLR_OPTCHANGEERR); + + while (len != 0) { + switch (addr) { + case FLASH_H7_REGS_ADDR + 0x20: // FLASH_OPTSR_PRG + case FLASH_H7_REGS_ADDR + 0x2c: // FLASH_PRAR_PRG1 + case FLASH_H7_REGS_ADDR + 0x34: // FLASH_SCAR_PRG1 + case FLASH_H7_REGS_ADDR + 0x3c: // FLASH_WPSN_PRG1 + case FLASH_H7_REGS_ADDR + 0x44: // FLASH_BOOT_PRG + /* Write to FLASH_xxx_PRG registers */ + write_uint32((unsigned char *)&data, + *(uint32_t *)(base)); // write options bytes + + WLOG("Writing option bytes %#10x to %#10x\n", data, addr); + + /* Skip if the value in the CUR register is identical */ + stlink_read_debug32(sl, addr - 4, &val); + if (val == data) { + break; + } + + /* Write new option byte values and start modification */ + stlink_write_debug32(sl, addr, data); + stlink_read_debug32(sl, FLASH_H7_OPTCR, &val); + val |= (1 << FLASH_H7_OPTCR_OPTSTART); + stlink_write_debug32(sl, FLASH_H7_OPTCR, val); + + /* Wait for the option bytes modification to complete */ + do { + stlink_read_debug32(sl, FLASH_H7_OPTSR_CUR, &val); + } while ((val & (1 << FLASH_H7_OPTSR_OPT_BUSY)) != 0); + + /* Check for errors */ + if ((val & (1 << FLASH_H7_OPTSR_OPTCHANGEERR)) != 0) { + stlink_write_debug32(sl, FLASH_H7_OPTCCR, + 1 << FLASH_H7_OPTCCR_CLR_OPTCHANGEERR); + return -1; + } + break; + + default: + /* Skip non-programmable registers */ + break; + } + + len -= 4; + addr += 4; + base += 4; + } + + return 0; +} + +/** + * Write option bytes + * @param sl + * @param addr of the memory mapped option bytes + * @param base option bytes to write + * @return 0 on success, -ve on failure. + */ +int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t *base, + uint32_t len) { + int ret = -1; + + if (sl->option_base == 0) { + ELOG( + "Option bytes writing is currently not supported for connected chip\n"); + return (-1); + } + + if ((addr < sl->option_base) || addr > sl->option_base + sl->option_size) { + ELOG("Option bytes start address out of Option bytes range\n"); + return (-1); + } + + if (addr + len > sl->option_base + sl->option_size) { + ELOG("Option bytes data too long\n"); + return (-1); + } + + wait_flash_busy(sl); + + if (unlock_flash_if(sl)) { + ELOG("Flash unlock failed! System reset required to be able to unlock it " + "again!\n"); + return (-1); + } + + if (unlock_flash_option_if(sl)) { + ELOG("Flash option unlock failed!\n"); + return (-1); + } + + switch (sl->flash_type) { + case STM32_FLASH_TYPE_F0_F1_F3: + case STM32_FLASH_TYPE_F1_XL: + ret = stlink_write_option_bytes_f0(sl, base, addr, len); + break; + case STM32_FLASH_TYPE_F2_F4: + ret = stlink_write_option_bytes_f4(sl, base, addr, len); + break; + case STM32_FLASH_TYPE_F7: + ret = stlink_write_option_bytes_f7(sl, base, addr, len); + break; + case STM32_FLASH_TYPE_L0_L1: + ret = stlink_write_option_bytes_l0(sl, base, addr, len); + break; + case STM32_FLASH_TYPE_L4_L4P: + ret = stlink_write_option_bytes_l4(sl, base, addr, len); + break; + case STM32_FLASH_TYPE_G0: + case STM32_FLASH_TYPE_G4: + ret = stlink_write_option_bytes_gx(sl, base, addr, len); + break; + case STM32_FLASH_TYPE_H7: + ret = stlink_write_option_bytes_h7(sl, base, addr, len); + break; + default: + ELOG("Option bytes writing is currently not implemented for connected " + "chip\n"); + break; + } + + if (ret) { + ELOG("Flash option write failed!\n"); + } else { + ILOG("Wrote %d option bytes to %#010x!\n", len, addr); + } + + /* Re-lock flash. */ + lock_flash_option(sl); + lock_flash(sl); + + return ret; +} + + +/** + * Write option bytes + * @param sl + * @param option_byte value to write + * @return 0 on success, -ve on failure. + */ +static int +stlink_write_option_control_register_f0(stlink_t *sl, + uint32_t option_control_register) { + int ret = 0; + uint16_t opt_val[8]; + unsigned protection, optiondata; + uint16_t user_options, user_data, rdp; + unsigned option_offset, user_data_offset; + + ILOG("Asked to write option control register %#10x to %#010x.\n", + option_control_register, FLASH_OBR); + + /* Clear errors */ + clear_flash_error(sl); + + /* Retrieve current values */ + ret = stlink_read_debug32(sl, FLASH_OBR, &optiondata); + if (ret) { + return ret; + } + ret = stlink_read_debug32(sl, FLASH_WRPR, &protection); + if (ret) { + return ret; + } + + /* Translate OBR value to flash store structure + * F0: RM0091, Option byte description, pp. 75-78 + * F1: PM0075, Option byte description, pp. 19-22 + * F3: RM0316, Option byte description, pp. 85-87 */ + switch(sl->chip_id) + { + case 0x422: /* STM32F30x */ + case 0x432: /* STM32F37x */ + case 0x438: /* STM32F303x6/8 and STM32F328 */ + case 0x446: /* STM32F303xD/E and STM32F398xE */ + case 0x439: /* STM32F302x6/8 */ + case 0x440: /* STM32F05x */ + case 0x444: /* STM32F03x */ + case 0x445: /* STM32F04x */ + case 0x448: /* STM32F07x */ + case 0x442: /* STM32F09x */ + option_offset = 6; + user_data_offset = 16; + rdp = 0x55AA; + break; + default: + option_offset = 0; + user_data_offset = 10; + rdp = 0x5AA5; + break; + } + + user_options = (option_control_register >> option_offset >> 2) & 0xFFFF; + user_data = (option_control_register >> user_data_offset) & 0xFFFF; + +#define VAL_WITH_COMPLEMENT(v) (uint16_t)(((v)&0xFF) | (((~(v))<<8)&0xFF00)) + + opt_val[0] = (option_control_register & (1 << 1/*OPT_READOUT*/)) ? 0xFFFF : rdp; + opt_val[1] = VAL_WITH_COMPLEMENT(user_options); + opt_val[2] = VAL_WITH_COMPLEMENT(user_data); + opt_val[3] = VAL_WITH_COMPLEMENT(user_data >> 8); + opt_val[4] = VAL_WITH_COMPLEMENT(protection); + opt_val[5] = VAL_WITH_COMPLEMENT(protection >> 8); + opt_val[6] = VAL_WITH_COMPLEMENT(protection >> 16); + opt_val[7] = VAL_WITH_COMPLEMENT(protection >> 24); + +#undef VAL_WITH_COMPLEMENT + + /* Write bytes and check errors */ + ret = stlink_write_option_bytes_f0(sl, (uint8_t*)opt_val, STM32_F0_OPTION_BYTES_BASE, sizeof(opt_val)); + if (ret) + return ret; + + ret = check_flash_error(sl); + if (!ret) { + ILOG("Wrote option bytes %#010x to %#010x!\n", option_control_register, + FLASH_OBR); + } + + return ret; +} + + +/** + * Write option bytes + * @param sl + * @param option_byte value to write + * @return 0 on success, -ve on failure. + */ +static int +stlink_write_option_control_register1_f7(stlink_t *sl, + uint32_t option_control_register1) { + int ret = 0; + + // Clear errors + clear_flash_error(sl); + + ILOG("Asked to write option control register 1 %#010x to %#010x.\n", + option_control_register1, FLASH_F7_OPTCR1); + + /* write option byte, ensuring we dont lock opt, and set strt bit */ + uint32_t current_control_register_value; + stlink_read_debug32(sl, FLASH_F7_OPTCR, ¤t_control_register_value); + + /* write option byte */ + stlink_write_debug32(sl, FLASH_F7_OPTCR1, option_control_register1); + stlink_write_debug32( + sl, FLASH_F7_OPTCR, + (current_control_register_value & ~(1 << FLASH_F7_OPTCR_LOCK)) | + (1 << FLASH_F7_OPTCR_START)); + + wait_flash_busy(sl); + + ret = check_flash_error(sl); + if (!ret) + ILOG("Wrote option bytes %#010x to %#010x!\n", option_control_register1, + FLASH_F7_OPTCR1); + + return ret; +} + +/** + * Write option bytes + * @param sl + * @param option_byte value to write + * @return 0 on success, -ve on failure. + */ +static int +stlink_write_option_control_register_f7(stlink_t *sl, + uint32_t option_control_register) { + int ret = 0; + + // Clear errors + clear_flash_error(sl); + + ILOG("Asked to write option control register 1 %#10x to %#010x.\n", + option_control_register, FLASH_F7_OPTCR); + + /* write option byte, ensuring we dont lock opt, and set strt bit */ + stlink_write_debug32(sl, FLASH_F7_OPTCR, + (option_control_register & ~(1 << FLASH_F7_OPTCR_LOCK)) | + (1 << FLASH_F7_OPTCR_START)); + + wait_flash_busy(sl); + + ret = check_flash_error(sl); + if (!ret) + ILOG("Wrote option bytes %#010x to %#010x!\n", option_control_register, + FLASH_F7_OPTCR); + + return ret; +} + +/** + * Write option bytes + * @param sl + * @param option bytes boot address to write + * @return 0 on success, -ve on failure. + */ +int stlink_write_option_control_register32(stlink_t *sl, + uint32_t option_control_register) { + int ret = -1; + + wait_flash_busy(sl); + + if (unlock_flash_if(sl)) { + ELOG("Flash unlock failed! System reset required to be able to unlock it " + "again!\n"); + return -1; + } + + if (unlock_flash_option_if(sl)) { + ELOG("Flash option unlock failed!\n"); + return -1; + } + + switch (sl->flash_type) { + case STM32_FLASH_TYPE_F0_F1_F3: + case STM32_FLASH_TYPE_F1_XL: + ret = stlink_write_option_control_register_f0(sl, option_control_register); + break; + case STM32_FLASH_TYPE_F7: + ret = stlink_write_option_control_register_f7(sl, option_control_register); + break; + default: + ELOG("Option control register writing is currently not implemented for " + "connected chip\n"); + break; + } + + if (ret) + ELOG("Flash option write failed!\n"); + else + ILOG("Wrote option control register %#010x!\n", option_control_register); + + /* Re-lock flash. */ + lock_flash_option(sl); + lock_flash(sl); + + return ret; +} + +/** + * Write option bytes + * @param sl + * @param option bytes boot address to write + * @return 0 on success, -ve on failure. + */ +int stlink_write_option_control_register1_32( + stlink_t *sl, uint32_t option_control_register1) { + int ret = -1; + + wait_flash_busy(sl); + + if (unlock_flash_if(sl)) { + ELOG("Flash unlock failed! System reset required to be able to unlock it " + "again!\n"); + return -1; + } + + if (unlock_flash_option_if(sl)) { + ELOG("Flash option unlock failed!\n"); + return -1; + } + + switch (sl->flash_type) { + case STM32_FLASH_TYPE_F7: + ret = + stlink_write_option_control_register1_f7(sl, option_control_register1); + break; + default: + ELOG("Option control register 1 writing is currently not implemented for " + "connected chip\n"); + break; + } + + if (ret) + ELOG("Flash option write failed!\n"); + else + ILOG("Wrote option control register 1 %#010x!\n", option_control_register1); + + lock_flash_option(sl); + lock_flash(sl); + + return (ret); +} + + +/** + * Write option bytes + * @param sl + * @param option_byte value to write + * @return 0 on success, -ve on failure. + */ +static int +stlink_write_option_bytes_boot_add_f7(stlink_t *sl, + uint32_t option_byte_boot_add) { + ILOG("Asked to write option byte boot add %#010x.\n", option_byte_boot_add); + return stlink_write_option_control_register1_f7(sl, option_byte_boot_add); +} + +/** + * Write option bytes + * @param sl + * @param option bytes boot address to write + * @return 0 on success, -ve on failure. + */ +int stlink_write_option_bytes_boot_add32(stlink_t *sl, + uint32_t option_bytes_boot_add) { + int ret = -1; + + wait_flash_busy(sl); + + if (unlock_flash_if(sl)) { + ELOG("Flash unlock failed! System reset required to be able to unlock it " + "again!\n"); + return -1; + } + + if (unlock_flash_option_if(sl)) { + ELOG("Flash option unlock failed!\n"); + return -1; + } + + switch (sl->flash_type) { + case STM32_FLASH_TYPE_F7: + ret = stlink_write_option_bytes_boot_add_f7(sl, option_bytes_boot_add); + break; + default: + ELOG("Option bytes boot address writing is currently not implemented for " + "connected chip\n"); + break; + } + + if (ret) + ELOG("Flash option write failed!\n"); + else + ILOG("Wrote option bytes boot address %#010x!\n", option_bytes_boot_add); + + /* Re-lock flash. */ + lock_flash_option(sl); + lock_flash(sl); + + return ret; +} + +/** + * Write option bytes + * @param sl + * @param option_byte value to write + * @return 0 on success, -ve on failure. + */ +int stlink_write_option_bytes32(stlink_t *sl, uint32_t option_byte) { + WLOG("About to write option byte %#10x to %#10x.\n", option_byte, + sl->option_base); + return stlink_write_option_bytes(sl, sl->option_base, (uint8_t *)&option_byte, + 4); +} + +/** + * Write the given binary file with option bytes + * @param sl + * @param path readable file path, should be binary image + * @param addr of the memory mapped option bytes + * @return 0 on success, -ve on failure. + */ +int stlink_fwrite_option_bytes(stlink_t *sl, const char *path, + stm32_addr_t addr) { + /* Write the file in flash at addr */ + int err; + mapped_file_t mf = MAPPED_FILE_INITIALIZER; + + if (map_file(&mf, path) == -1) { + ELOG("map_file() == -1\n"); + return (-1); + } + + printf("file %s ", path); + md5_calculate(&mf); + stlink_checksum(&mf); + + err = stlink_write_option_bytes(sl, addr, mf.base, (uint32_t)mf.len); + stlink_fwrite_finalize(sl, addr); + unmap_file(&mf); + + return (err); +} + +/** + * Read option bytes + * @param sl + * @param option_byte value to read + * @return 0 on success, -ve on failure. + */ +int stlink_read_option_control_register1_f7(stlink_t *sl, + uint32_t *option_byte) { + DLOG("@@@@ Read option control register 1 byte from %#10x\n", + FLASH_F7_OPTCR1); + return stlink_read_debug32(sl, FLASH_F7_OPTCR1, option_byte); +} + +/** + * Read option bytes + * @param sl + * @param option_byte option value + * @return 0 on success, -ve on failure. + */ +int stlink_read_option_control_register1_32(stlink_t *sl, + uint32_t *option_byte) { + if (sl->option_base == 0) { + ELOG("Option bytes read is currently not supported for connected chip\n"); + return -1; + } + + switch (sl->flash_type) { + case STM32_FLASH_TYPE_F7: + return stlink_read_option_control_register1_f7(sl, option_byte); + default: + return -1; + // return stlink_read_option_control_register1_generic(sl, option_byte); + } +} + + +/** + * Read option bytes + * @param sl + * @param option_byte value to read + * @return 0 on success, -ve on failure. + */ +int stlink_read_option_bytes_boot_add_f7(stlink_t *sl, uint32_t *option_byte) { + DLOG("@@@@ Read option byte boot address\n"); + return stlink_read_option_control_register1_f7(sl, option_byte); +} + +/** + * Read option bytes + * @param sl + * @param option_byte option value + * @return 0 on success, -ve on failure. + */ +int stlink_read_option_bytes_boot_add32(stlink_t *sl, uint32_t *option_byte) { + if (sl->option_base == 0) { + ELOG("Option bytes boot address read is currently not supported for " + "connected chip\n"); + return -1; + } + + switch (sl->flash_type) { + case STM32_FLASH_TYPE_F7: + return stlink_read_option_bytes_boot_add_f7(sl, option_byte); + default: + return -1; + // return stlink_read_option_bytes_boot_add_generic(sl, option_byte); + } +} + +/** + * Read option bytes + * @param sl + * @param option_byte value to read + * @return 0 on success, -ve on failure. + */ +int stlink_read_option_control_register_f7(stlink_t *sl, + uint32_t *option_byte) { + DLOG("@@@@ Read option control register byte from %#10x\n", FLASH_F7_OPTCR); + return stlink_read_debug32(sl, FLASH_F7_OPTCR, option_byte); +} + +/** + * Read option bytes + * @param sl + * @param option_byte value to read + * @return 0 on success, -ve on failure. + */ +int stlink_read_option_control_register_f0(stlink_t *sl, + uint32_t *option_byte) { + DLOG("@@@@ Read option control register byte from %#10x\n", FLASH_OBR); + return stlink_read_debug32(sl, FLASH_OBR, option_byte); +} + +/** + * Read option bytes + * @param sl + * @param option_byte option value + * @return 0 on success, -ve on failure. + */ +int stlink_read_option_control_register32(stlink_t *sl, uint32_t *option_byte) { + if (sl->option_base == 0) { + ELOG("Option bytes read is currently not supported for connected chip\n"); + return -1; + } + + switch (sl->flash_type) { + case STM32_FLASH_TYPE_F0_F1_F3: + case STM32_FLASH_TYPE_F1_XL: + return stlink_read_option_control_register_f0(sl, option_byte); + case STM32_FLASH_TYPE_F7: + return stlink_read_option_control_register_f7(sl, option_byte); + default: + return -1; + } +} diff --git a/src/read_write.c b/src/read_write.c new file mode 100644 index 000000000..f20d76aab --- /dev/null +++ b/src/read_write.c @@ -0,0 +1,143 @@ +#include +#include +#include + +// Endianness +// https://commandcenter.blogspot.com/2012/04/byte-order-fallacy.html +// These functions encode and decode little endian uint16 and uint32 values. + +void write_uint32(unsigned char *buf, uint32_t ui) { + buf[0] = ui; + buf[1] = ui >> 8; + buf[2] = ui >> 16; + buf[3] = ui >> 24; +} + +void write_uint16(unsigned char *buf, uint16_t ui) { + buf[0] = (uint8_t)ui; + buf[1] = (uint8_t)(ui >> 8); +} + +uint32_t read_uint32(const unsigned char *c, const int pt) { + return ((uint32_t)c[pt]) | ((uint32_t)c[pt + 1] << 8) | + ((uint32_t)c[pt + 2] << 16) | ((uint32_t)c[pt + 3] << 24); +} + +uint16_t read_uint16(const unsigned char *c, const int pt) { + return ((uint16_t)c[pt]) | ((uint16_t)c[pt + 1] << 8); +} + +int stlink_read_debug32(stlink_t *sl, uint32_t addr, uint32_t *data) { + int ret; + + ret = sl->backend->read_debug32(sl, addr, data); + if (!ret) + DLOG("*** stlink_read_debug32 %#010x at %#010x\n", *data, addr); + + return (ret); +} + +int stlink_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data) { + DLOG("*** stlink_write_debug32 %#010x to %#010x\n", data, addr); + return sl->backend->write_debug32(sl, addr, data); +} + +int stlink_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { + DLOG("*** stlink_write_mem32 %u bytes to %#x\n", len, addr); + + if (len % 4 != 0) { + ELOG("Data length doesn't have a 32 bit alignment: +%d byte.\n", len % 4); + return (-1); + } + + return (sl->backend->write_mem32(sl, addr, len)); +} + +int stlink_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { + DLOG("*** stlink_read_mem32 ***\n"); + + if (len % 4 != 0) { // !!! never ever: fw gives just wrong values + ELOG("Data length doesn't have a 32 bit alignment: +%d byte.\n", len % 4); + return (-1); + } + + return (sl->backend->read_mem32(sl, addr, len)); +} + +int stlink_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len) { + DLOG("*** stlink_write_mem8 ***\n"); + return (sl->backend->write_mem8(sl, addr, len)); +} + +int stlink_read_all_regs(stlink_t *sl, struct stlink_reg *regp) { + DLOG("*** stlink_read_all_regs ***\n"); + return (sl->backend->read_all_regs(sl, regp)); +} + +int stlink_read_all_unsupported_regs(stlink_t *sl, struct stlink_reg *regp) { + DLOG("*** stlink_read_all_unsupported_regs ***\n"); + return (sl->backend->read_all_unsupported_regs(sl, regp)); +} + +int stlink_write_reg(stlink_t *sl, uint32_t reg, int idx) { + DLOG("*** stlink_write_reg\n"); + return (sl->backend->write_reg(sl, reg, idx)); +} + +int stlink_read_reg(stlink_t *sl, int r_idx, struct stlink_reg *regp) { + DLOG("*** stlink_read_reg\n"); + DLOG(" (%d) ***\n", r_idx); + + if (r_idx > 20 || r_idx < 0) { + fprintf(stderr, "Error: register index must be in [0..20]\n"); + return (-1); + } + + return (sl->backend->read_reg(sl, r_idx, regp)); +} + +int stlink_read_unsupported_reg(stlink_t *sl, int r_idx, + struct stlink_reg *regp) { + int r_convert; + + DLOG("*** stlink_read_unsupported_reg\n"); + DLOG(" (%d) ***\n", r_idx); + + /* Convert to values used by STLINK_REG_DCRSR */ + if (r_idx >= 0x1C && + r_idx <= 0x1F) { // primask, basepri, faultmask, or control + r_convert = 0x14; + } else if (r_idx == 0x40) { // FPSCR + r_convert = 0x21; + } else if (r_idx >= 0x20 && r_idx < 0x40) { + r_convert = 0x40 + (r_idx - 0x20); + } else { + fprintf(stderr, "Error: register address must be in [0x1C..0x40]\n"); + return (-1); + } + + return (sl->backend->read_unsupported_reg(sl, r_convert, regp)); +} + +int stlink_write_unsupported_reg(stlink_t *sl, uint32_t val, int r_idx, + struct stlink_reg *regp) { + int r_convert; + + DLOG("*** stlink_write_unsupported_reg\n"); + DLOG(" (%d) ***\n", r_idx); + + /* Convert to values used by STLINK_REG_DCRSR */ + if (r_idx >= 0x1C && + r_idx <= 0x1F) { /* primask, basepri, faultmask, or control */ + r_convert = r_idx; // the backend function handles this + } else if (r_idx == 0x40) { // FPSCR + r_convert = 0x21; + } else if (r_idx >= 0x20 && r_idx < 0x40) { + r_convert = 0x40 + (r_idx - 0x20); + } else { + fprintf(stderr, "Error: register address must be in [0x1C..0x40]\n"); + return (-1); + } + + return (sl->backend->write_unsupported_reg(sl, val, r_convert, regp)); +} diff --git a/src/stlink-lib/chipid.h b/src/stlink-lib/chipid.h index 458e7c3e2..f8e1b3444 100644 --- a/src/stlink-lib/chipid.h +++ b/src/stlink-lib/chipid.h @@ -4,7 +4,8 @@ #include #include -/** Chipid parametres */ + +/** Chipid parameters */ struct stlink_chipid_params { char *dev_type; char *ref_manual_id; @@ -22,6 +23,6 @@ struct stlink_chipid_params { }; struct stlink_chipid_params *stlink_chipid_get_params(uint32_t chipid); - void init_chipids(char *dir_to_scan); + void init_chipids(char *dir_to_scan); #endif // STLINK_CHIPID_H_ diff --git a/src/stlink-lib/usb.c b/src/stlink-lib/usb.c index e07918800..2e99e82be 100644 --- a/src/stlink-lib/usb.c +++ b/src/stlink-lib/usb.c @@ -1134,33 +1134,8 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, enum connect_type connect, #endif libusb_device **list = NULL; - // TODO: We should use ssize_t and use it as a counter if > 0. - // As per libusb API: ssize_t libusb_get_device_list (libusb_context *ctx, libusb_device ***list) - int cnt = (int)libusb_get_device_list(slu->libusb_ctx, &list); + ssize_t cnt = libusb_get_device_list(slu->libusb_ctx, &list); struct libusb_device_descriptor desc; - int devBus = 0; - int devAddr = 0; - - // TODO: Reading a environment variable in a usb open function is not very nice, this should - // be refactored and moved into the CLI tools, and instead of giving USB_BUS:USB_ADDR a real - // stlink serial string should be passed to this function. Probably people are using this - // but this is very odd because as programmer can change to multiple busses and it is better - // to detect them based on serial. - char *device = getenv("STLINK_DEVICE"); - - if (device) { - char *c = strchr(device, ':'); - - if (c == NULL) { - WLOG("STLINK_DEVICE must be : format\n"); - goto on_error; - } - - devBus = atoi(device); - *c++ = 0; - devAddr = atoi(c); - ILOG("bus %03d dev %03d\n", devBus, devAddr); - } while (cnt-- > 0) { struct libusb_device_handle *handle; @@ -1169,13 +1144,6 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, enum connect_type connect, if (desc.idVendor != STLINK_USB_VID_ST) { continue; } - if (devBus && devAddr) { - if ((libusb_get_bus_number(list[cnt]) != devBus) || - (libusb_get_device_address(list[cnt]) != devAddr)) { - continue; - } - } - ret = libusb_open(list[cnt], &handle); if (ret) { continue; } // could not open device @@ -1202,7 +1170,7 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, enum connect_type connect, } if (cnt < 0) { - WLOG ("Couldn't find %s ST-Link devices\n", (devBus && devAddr) ? "matched" : "any"); + WLOG ("Couldn't find any ST-Link devices\n"); libusb_free_device_list(list, 1); goto on_error; } else { @@ -1221,6 +1189,8 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, enum connect_type connect, libusb_free_device_list(list, 1); +// libusb_kernel_driver_active is not available on Windows. +#if !defined(_WIN32) if (libusb_kernel_driver_active(slu->usb_handle, 0) == 1) { ret = libusb_detach_kernel_driver(slu->usb_handle, 0); @@ -1229,6 +1199,7 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, enum connect_type connect, goto on_libusb_error; } } +#endif if (libusb_get_configuration(slu->usb_handle, &config)) { // this may fail for a previous configured device @@ -1287,7 +1258,7 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, enum connect_type connect, // the NRST pin must be pull down before selecting the SWD/JTAG mode if (mode == STLINK_DEV_DEBUG_MODE) { DLOG("-- exit_debug_mode\n"); - _stlink_usb_exit_dfu_mode(sl); + _stlink_usb_exit_debug_mode(sl); } _stlink_usb_jtag_reset(sl, STLINK_DEBUG_APIV2_DRIVE_NRST_LOW); diff --git a/src/stlink-lib/usb.c.bak b/src/stlink-lib/usb.c.bak new file mode 100644 index 000000000..32ceff71f --- /dev/null +++ b/src/stlink-lib/usb.c.bak @@ -0,0 +1,1410 @@ +#include +#include +#include +#include +#include + +#if !defined(_MSC_VER) +#include +#endif + +#include +#include +#include + +#if defined(_WIN32) +#include +#endif + +#include +#include +#include "usb.h" + +enum SCSI_Generic_Direction {SG_DXFER_TO_DEV = 0, SG_DXFER_FROM_DEV = 0x80}; + +static inline uint32_t le_to_h_u32(const uint8_t* buf) { + return((uint32_t)((uint32_t)buf[0] | (uint32_t)buf[1] << 8 | (uint32_t)buf[2] << 16 | (uint32_t)buf[3] << 24)); +} + +static int _stlink_match_speed_map(const uint32_t *map, unsigned int map_size, uint32_t khz) { + unsigned int i; + int speed_index = -1; + int speed_diff = INT_MAX; + int last_valid_speed = -1; + bool match = true; + + for (i = 0; i < map_size; i++) { + if (!map[i]) { continue; } + + last_valid_speed = i; + + if (khz == map[i]) { + speed_index = i; + break; + } else { + int current_diff = khz - map[i]; + // get abs value for comparison + current_diff = (current_diff > 0) ? current_diff : -current_diff; + + if (current_diff < speed_diff) { + speed_diff = current_diff; + speed_index = i; + } + } + } + + if (speed_index == -1) { + // This will only be here if we cannot match the slow speed. + // Use the slowest speed we support. + speed_index = last_valid_speed; + match = false; + } else if (i == map_size) { + match = false; + } + + if (!match) { + ILOG("Unable to match requested speed %d kHz, using %d kHz\n", khz, map[speed_index]); + } + + return(speed_index); +} + +void _stlink_usb_close(stlink_t* sl) { + if (!sl) { return; } + + struct stlink_libusb * const handle = sl->backend_data; + + // maybe we couldn't even get the usb device? + if (handle != NULL) { + if (handle->usb_handle != NULL) { libusb_close(handle->usb_handle); } + + libusb_exit(handle->libusb_ctx); + free(handle); + } +} + +ssize_t send_recv(struct stlink_libusb* handle, int terminate, + unsigned char* txbuf, size_t txsize, unsigned char* rxbuf, + size_t rxsize, int check_error, const char *cmd) { + // Note: txbuf and rxbuf can point to the same area + int res, t, retry = 0; + + while (1) { + res = 0; + t = libusb_bulk_transfer(handle->usb_handle, handle->ep_req, txbuf, (int)txsize, &res, 3000); + + if (t) { + ELOG("%s send request failed: %s\n", cmd, libusb_error_name(t)); + return(-1); + } else if ((size_t)res != txsize) { + ELOG("%s send request wrote %u bytes, instead of %u\n", + cmd, (unsigned int)res, (unsigned int)txsize); + } + + if (rxsize != 0) { + t = libusb_bulk_transfer(handle->usb_handle, handle->ep_rep, rxbuf, (int)rxsize, &res, 3000); + + if (t) { + ELOG("%s read reply failed: %s\n", cmd, libusb_error_name(t)); + return(-1); + } + + /* Checking the command execution status stored in the first byte of the response */ + if (handle->protocoll != 1 && check_error >= CMD_CHECK_STATUS && + rxbuf[0] != STLINK_DEBUG_ERR_OK) { + switch(rxbuf[0]) { + case STLINK_DEBUG_ERR_AP_WAIT: + case STLINK_DEBUG_ERR_DP_WAIT: + if (check_error == CMD_CHECK_RETRY && retry < 3) { + unsigned int delay_us = (1<protocoll == 1) && terminate) { + // read the SG reply + unsigned char sg_buf[13]; + t = libusb_bulk_transfer(handle->usb_handle, handle->ep_rep, sg_buf, 13, &res, 3000); + + if (t) { + ELOG("%s read storage failed: %s\n", cmd, libusb_error_name(t)); + return(-1); + } + + // The STLink doesn't seem to evaluate the sequence number. + handle->sg_transfer_idx++; + } + + return(res); + } +} + +static inline int send_only(struct stlink_libusb* handle, int terminate, + unsigned char* txbuf, size_t txsize, + const char *cmd) { + return((int)send_recv(handle, terminate, txbuf, txsize, NULL, 0, CMD_CHECK_NO, cmd)); +} + + +static int fill_command(stlink_t * sl, enum SCSI_Generic_Direction dir, uint32_t len) { + struct stlink_libusb * const slu = sl->backend_data; + unsigned char* const cmd = sl->c_buf; + int i = 0; + memset(cmd, 0, sizeof(sl->c_buf)); + + if (slu->protocoll == 1) { + cmd[i++] = 'U'; + cmd[i++] = 'S'; + cmd[i++] = 'B'; + cmd[i++] = 'C'; + write_uint32(&cmd[i], slu->sg_transfer_idx); + write_uint32(&cmd[i + 4], len); + i += 8; + cmd[i++] = (dir == SG_DXFER_FROM_DEV) ? 0x80 : 0; + cmd[i++] = 0; // logical unit + cmd[i++] = 0xa; // command length + } + return(i); +} + +int _stlink_usb_version(stlink_t *sl) { + struct stlink_libusb * const slu = sl->backend_data; + unsigned char* const data = sl->q_buf; + unsigned char* const cmd = sl->c_buf; + ssize_t size; + uint32_t rep_len; + int i; + + if (sl->version.stlink_v == 3) { + // STLINK-V3 version is determined by another command + rep_len = 12; + i = fill_command(sl, SG_DXFER_FROM_DEV, 16); + cmd[i++] = STLINK_GET_VERSION_APIV3; + } else { + rep_len = 6; + i = fill_command(sl, SG_DXFER_FROM_DEV, 6); + cmd[i++] = STLINK_GET_VERSION; + } + + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_REP_LEN, "GET_VERSION"); + + return(size<0?-1:0); +} + +int32_t _stlink_usb_target_voltage(stlink_t *sl) { + struct stlink_libusb * const slu = sl->backend_data; + unsigned char* const rdata = sl->q_buf; + unsigned char* const cmd = sl->c_buf; + ssize_t size; + uint32_t rep_len = 8; + int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); + uint32_t factor, reading; + int voltage; + + cmd[i++] = STLINK_GET_TARGET_VOLTAGE; + + size = send_recv(slu, 1, cmd, slu->cmd_len, rdata, rep_len, CMD_CHECK_REP_LEN, "GET_TARGET_VOLTAGE"); + + if (size < 0) { + return(-1); + } + + factor = (rdata[3] << 24) | (rdata[2] << 16) | (rdata[1] << 8) | (rdata[0] << 0); + reading = (rdata[7] << 24) | (rdata[6] << 16) | (rdata[5] << 8) | (rdata[4] << 0); + voltage = 2400 * reading / factor; + + return(voltage); +} + +int _stlink_usb_read_debug32(stlink_t *sl, uint32_t addr, uint32_t *data) { + struct stlink_libusb * const slu = sl->backend_data; + unsigned char* const rdata = sl->q_buf; + unsigned char* const cmd = sl->c_buf; + ssize_t size; + const int rep_len = 8; + + int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); + cmd[i++] = STLINK_DEBUG_COMMAND; + cmd[i++] = STLINK_DEBUG_APIV2_READDEBUGREG; + write_uint32(&cmd[i], addr); + size = send_recv(slu, 1, cmd, slu->cmd_len, rdata, rep_len, CMD_CHECK_RETRY, "READDEBUGREG"); + + if (size < 0) { + return(-1); + } + + *data = read_uint32(rdata, 4); + + return(0); +} + +int _stlink_usb_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data) { + struct stlink_libusb * const slu = sl->backend_data; + unsigned char* const rdata = sl->q_buf; + unsigned char* const cmd = sl->c_buf; + ssize_t size; + const int rep_len = 2; + + int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); + cmd[i++] = STLINK_DEBUG_COMMAND; + cmd[i++] = STLINK_DEBUG_APIV2_WRITEDEBUGREG; + write_uint32(&cmd[i], addr); + write_uint32(&cmd[i + 4], data); + size = send_recv(slu, 1, cmd, slu->cmd_len, rdata, rep_len, CMD_CHECK_RETRY, "WRITEDEBUGREG"); + + return(size<0?-1:0); +} + +int _stlink_usb_get_rw_status(stlink_t *sl) { + if (sl->version.jtag_api == STLINK_JTAG_API_V1) { return(0); } + + unsigned char* const rdata = sl->q_buf; + struct stlink_libusb * const slu = sl->backend_data; + unsigned char* const cmd = sl->c_buf; + int i; + int16_t ret = 0; + + i = fill_command(sl, SG_DXFER_FROM_DEV, 12); + cmd[i++] = STLINK_DEBUG_COMMAND; + + if (sl->version.flags & STLINK_F_HAS_GETLASTRWSTATUS2) { + cmd[i++] = STLINK_DEBUG_APIV2_GETLASTRWSTATUS2; + ret = send_recv(slu, 1, cmd, slu->cmd_len, rdata, 12, CMD_CHECK_STATUS, "GETLASTRWSTATUS2"); + } else { + cmd[i++] = STLINK_DEBUG_APIV2_GETLASTRWSTATUS; + ret = send_recv(slu, 1, cmd, slu->cmd_len, rdata, 2, CMD_CHECK_STATUS, "GETLASTRWSTATUS"); + } + + return(ret<0?-1:0); +} + +int _stlink_usb_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { + struct stlink_libusb * const slu = sl->backend_data; + unsigned char* const data = sl->q_buf; + unsigned char* const cmd = sl->c_buf; + int i, ret; + + i = fill_command(sl, SG_DXFER_TO_DEV, len); + cmd[i++] = STLINK_DEBUG_COMMAND; + cmd[i++] = STLINK_DEBUG_WRITEMEM_32BIT; + write_uint32(&cmd[i], addr); + write_uint16(&cmd[i + 4], len); + ret = send_only(slu, 0, cmd, slu->cmd_len, "WRITEMEM_32BIT"); + + if (ret == -1) { return(ret); } + + ret = send_only(slu, 1, data, len, "WRITEMEM_32BIT"); + + if (ret == -1) { return(ret); } + + return(_stlink_usb_get_rw_status(sl)); +} + +int _stlink_usb_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len) { + struct stlink_libusb * const slu = sl->backend_data; + unsigned char* const data = sl->q_buf; + unsigned char* const cmd = sl->c_buf; + int i, ret; + + if ((sl->version.jtag_api < STLINK_JTAG_API_V3 && len > 64) || + (sl->version.jtag_api >= STLINK_JTAG_API_V3 && len > 512)) { + ELOG("WRITEMEM_8BIT: bulk packet limits exceeded (data len %d byte)\n", len); + return (-1); + } + + i = fill_command(sl, SG_DXFER_TO_DEV, 0); + cmd[i++] = STLINK_DEBUG_COMMAND; + cmd[i++] = STLINK_DEBUG_WRITEMEM_8BIT; + write_uint32(&cmd[i], addr); + write_uint16(&cmd[i + 4], len); + ret = send_only(slu, 0, cmd, slu->cmd_len, "WRITEMEM_8BIT"); + + if (ret == -1) { return(ret); } + + ret = send_only(slu, 1, data, len, "WRITEMEM_8BIT"); + + if (ret == -1) { return(ret); } + + return(0); +} + + +int _stlink_usb_current_mode(stlink_t * sl) { + struct stlink_libusb * const slu = sl->backend_data; + unsigned char* const cmd = sl->c_buf; + unsigned char* const data = sl->q_buf; + ssize_t size; + int rep_len = 2; + int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); + + cmd[i++] = STLINK_GET_CURRENT_MODE; + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_NO, "GET_CURRENT_MODE"); + + if (size < 0) { + return(-1); + } + + return(sl->q_buf[0]); +} + +int _stlink_usb_core_id(stlink_t * sl) { + struct stlink_libusb * const slu = sl->backend_data; + unsigned char* const cmd = sl->c_buf; + unsigned char* const data = sl->q_buf; + ssize_t size; + int offset, rep_len = sl->version.jtag_api == STLINK_JTAG_API_V1 ? 4 : 12; + int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); + + cmd[i++] = STLINK_DEBUG_COMMAND; + + if (sl->version.jtag_api == STLINK_JTAG_API_V1) { + cmd[i++] = STLINK_DEBUG_READCOREID; + offset = 0; + } else { + cmd[i++] = STLINK_DEBUG_APIV2_READ_IDCODES; + offset = 4; + } + + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_STATUS, "READ_IDCODES"); + + if (size < 0) { + return(-1); + } + + sl->core_id = read_uint32(data, offset); + + return(0); +} + +int _stlink_usb_status_v2(stlink_t *sl) { + int result; + uint32_t status = 0; + + result = _stlink_usb_read_debug32(sl, STLINK_REG_DHCSR, &status); + DLOG("core status: %08X\n", status); + + if (result != 0) { + sl->core_stat = TARGET_UNKNOWN; + } else { + if (status & STLINK_REG_DHCSR_C_HALT) { + sl->core_stat = TARGET_HALTED; + } else if (status & STLINK_REG_DHCSR_S_RESET_ST) { + sl->core_stat = TARGET_RESET; + } else { + sl->core_stat = TARGET_RUNNING; + } + } + + return(result); +} + +int _stlink_usb_status(stlink_t * sl) { + if (sl->version.jtag_api != STLINK_JTAG_API_V1) { return(_stlink_usb_status_v2(sl)); } + + struct stlink_libusb * const slu = sl->backend_data; + unsigned char* const data = sl->q_buf; + unsigned char* const cmd = sl->c_buf; + ssize_t size; + int rep_len = 2; + int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); + + cmd[i++] = STLINK_DEBUG_COMMAND; + cmd[i++] = STLINK_DEBUG_GETSTATUS; + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_NO, "GETSTATUS"); + + if (size > 1) { + if (sl->q_buf[0] == STLINK_CORE_RUNNING) { + sl->core_stat = TARGET_RUNNING; + } else if (sl->q_buf[0] == STLINK_CORE_HALTED) { + sl->core_stat = TARGET_HALTED; + } else { + sl->core_stat = TARGET_UNKNOWN; + } + } else { + sl->core_stat = TARGET_UNKNOWN; + } + + return(size<0?-1:0); +} + +int _stlink_usb_force_debug(stlink_t *sl) { + struct stlink_libusb *slu = sl->backend_data; + + int res; + + if (sl->version.jtag_api != STLINK_JTAG_API_V1) { + res = _stlink_usb_write_debug32(sl, STLINK_REG_DHCSR, STLINK_REG_DHCSR_DBGKEY | STLINK_REG_DHCSR_C_HALT | STLINK_REG_DHCSR_C_DEBUGEN); + return(res); + } + + unsigned char* const data = sl->q_buf; + unsigned char* const cmd = sl->c_buf; + ssize_t size; + int rep_len = 2; + int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); + + cmd[i++] = STLINK_DEBUG_COMMAND; + cmd[i++] = STLINK_DEBUG_FORCEDEBUG; + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_RETRY, "FORCEDEBUG"); + + return(size<0?-1:0); +} + +int _stlink_usb_enter_swd_mode(stlink_t * sl) { + struct stlink_libusb * const slu = sl->backend_data; + unsigned char* const cmd = sl->c_buf; + ssize_t size; + unsigned char* const data = sl->q_buf; + const uint32_t rep_len = sl->version.jtag_api == STLINK_JTAG_API_V1 ? 0 : 2; + int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); + + cmd[i++] = STLINK_DEBUG_COMMAND; + // select correct API-Version for entering SWD mode: V1 API (0x20) or V2 API (0x30). + cmd[i++] = sl->version.jtag_api == STLINK_JTAG_API_V1 ? STLINK_DEBUG_APIV1_ENTER : STLINK_DEBUG_APIV2_ENTER; + cmd[i++] = STLINK_DEBUG_ENTER_SWD; + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_RETRY, "ENTER_SWD"); + + return(size<0?-1:0); +} + +int _stlink_usb_exit_dfu_mode(stlink_t* sl) { + struct stlink_libusb * const slu = sl->backend_data; + unsigned char* const cmd = sl->c_buf; + ssize_t size; + int i = fill_command(sl, SG_DXFER_FROM_DEV, 0); + + cmd[i++] = STLINK_DFU_COMMAND; + cmd[i++] = STLINK_DFU_EXIT; + size = send_only(slu, 1, cmd, slu->cmd_len, "DFU_EXIT"); + + return(size<0?-1:0); +} + + +int _stlink_usb_reset(stlink_t * sl) { + struct stlink_libusb * const slu = sl->backend_data; + unsigned char* const data = sl->q_buf; + unsigned char* const cmd = sl->c_buf; + ssize_t size; + int i, rep_len = 2; + + // send reset command + i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); + cmd[i++] = STLINK_DEBUG_COMMAND; + + if (sl->version.jtag_api == STLINK_JTAG_API_V1) { + cmd[i++] = STLINK_DEBUG_APIV1_RESETSYS; + } else { + cmd[i++] = STLINK_DEBUG_APIV2_RESETSYS; + } + + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_RETRY, "RESETSYS"); + + return(size<0?-1:0); +} + +int _stlink_usb_jtag_reset(stlink_t * sl, int value) { + struct stlink_libusb * const slu = sl->backend_data; + unsigned char* const data = sl->q_buf; + unsigned char* const cmd = sl->c_buf; + ssize_t size; + int rep_len = 2; + int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); + + cmd[i++] = STLINK_DEBUG_COMMAND; + cmd[i++] = STLINK_DEBUG_APIV2_DRIVE_NRST; + cmd[i++] = value; + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_RETRY, "DRIVE_NRST"); + + return(size<0?-1:0); +} + + +int _stlink_usb_step(stlink_t* sl) { + struct stlink_libusb * const slu = sl->backend_data; + + if (sl->version.jtag_api != STLINK_JTAG_API_V1) { + // emulates the JTAG v1 API by using DHCSR + _stlink_usb_write_debug32(sl, STLINK_REG_DHCSR, STLINK_REG_DHCSR_DBGKEY | STLINK_REG_DHCSR_C_HALT | + STLINK_REG_DHCSR_C_MASKINTS | STLINK_REG_DHCSR_C_DEBUGEN); + _stlink_usb_write_debug32(sl, STLINK_REG_DHCSR, STLINK_REG_DHCSR_DBGKEY | STLINK_REG_DHCSR_C_STEP | + STLINK_REG_DHCSR_C_MASKINTS | STLINK_REG_DHCSR_C_DEBUGEN); + return _stlink_usb_write_debug32(sl, STLINK_REG_DHCSR, STLINK_REG_DHCSR_DBGKEY | STLINK_REG_DHCSR_C_HALT | + STLINK_REG_DHCSR_C_DEBUGEN); + } + + unsigned char* const data = sl->q_buf; + unsigned char* const cmd = sl->c_buf; + ssize_t size; + int rep_len = 2; + int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); + + cmd[i++] = STLINK_DEBUG_COMMAND; + cmd[i++] = STLINK_DEBUG_STEPCORE; + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_RETRY, "STEPCORE"); + + return(size<0?-1:0); +} + +/** + * This seems to do a good job of restarting things from the beginning? + * @param sl + * @param type + */ +int _stlink_usb_run(stlink_t* sl, enum run_type type) { + struct stlink_libusb * const slu = sl->backend_data; + + int res; + + if (sl->version.jtag_api != STLINK_JTAG_API_V1) { + res = _stlink_usb_write_debug32(sl, STLINK_REG_DHCSR, + STLINK_REG_DHCSR_DBGKEY | STLINK_REG_DHCSR_C_DEBUGEN | + ((type==RUN_FLASH_LOADER)?STLINK_REG_DHCSR_C_MASKINTS:0)); + return(res); + } + + + unsigned char* const data = sl->q_buf; + unsigned char* const cmd = sl->c_buf; + ssize_t size; + int rep_len = 2; + int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); + + cmd[i++] = STLINK_DEBUG_COMMAND; + cmd[i++] = STLINK_DEBUG_RUNCORE; + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_RETRY, "RUNCORE"); + + return(size<0?-1:0); +} + +int _stlink_usb_set_swdclk(stlink_t* sl, int clk_freq) { + struct stlink_libusb * const slu = sl->backend_data; + unsigned char* const data = sl->q_buf; + unsigned char* const cmd = sl->c_buf; + ssize_t size; + int rep_len = 2; + int i; + + // clock speed only supported by stlink/v2 and for firmware >= 22 + if (sl->version.stlink_v == 2 && sl->version.jtag_v >= 22) { + uint16_t clk_divisor; + if (clk_freq) { + const uint32_t map[] = {5, 15, 25, 50, 100, 125, 240, 480, 950, 1200, 1800, 4000}; + int speed_index = _stlink_match_speed_map(map, STLINK_ARRAY_SIZE(map), clk_freq); + switch (map[speed_index]) { + case 5: clk_divisor = STLINK_SWDCLK_5KHZ_DIVISOR; break; + case 15: clk_divisor = STLINK_SWDCLK_15KHZ_DIVISOR; break; + case 25: clk_divisor = STLINK_SWDCLK_25KHZ_DIVISOR; break; + case 50: clk_divisor = STLINK_SWDCLK_50KHZ_DIVISOR; break; + case 100: clk_divisor = STLINK_SWDCLK_100KHZ_DIVISOR; break; + case 125: clk_divisor = STLINK_SWDCLK_125KHZ_DIVISOR; break; + case 240: clk_divisor = STLINK_SWDCLK_240KHZ_DIVISOR; break; + case 480: clk_divisor = STLINK_SWDCLK_480KHZ_DIVISOR; break; + case 950: clk_divisor = STLINK_SWDCLK_950KHZ_DIVISOR; break; + case 1200: clk_divisor = STLINK_SWDCLK_1P2MHZ_DIVISOR; break; + default: + case 1800: clk_divisor = STLINK_SWDCLK_1P8MHZ_DIVISOR; break; + case 4000: clk_divisor = STLINK_SWDCLK_4MHZ_DIVISOR; break; + } + } else + clk_divisor = STLINK_SWDCLK_1P8MHZ_DIVISOR; + + i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); + + cmd[i++] = STLINK_DEBUG_COMMAND; + cmd[i++] = STLINK_DEBUG_APIV2_SWD_SET_FREQ; + cmd[i++] = clk_divisor & 0xFF; + cmd[i++] = (clk_divisor >> 8) & 0xFF; + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_RETRY, "SWD_SET_FREQ"); + + return(size<0?-1:0); + } else if (sl->version.stlink_v == 3) { + int speed_index; + uint32_t map[STLINK_V3_MAX_FREQ_NB]; + i = fill_command(sl, SG_DXFER_FROM_DEV, 16); + + cmd[i++] = STLINK_DEBUG_COMMAND; + cmd[i++] = STLINK_DEBUG_APIV3_GET_COM_FREQ; + cmd[i++] = 0; // SWD mode + size = send_recv(slu, 1, cmd, slu->cmd_len, data, 52, CMD_CHECK_STATUS, "GET_COM_FREQ"); + + if (size < 0) { + return(-1); + } + + int speeds_size = data[8]; + if (speeds_size > STLINK_V3_MAX_FREQ_NB) { + speeds_size = STLINK_V3_MAX_FREQ_NB; + } + + for (i = 0; i < speeds_size; i++) map[i] = le_to_h_u32(&data[12 + 4 * i]); + + // Set to zero all the next entries + for (i = speeds_size; i < STLINK_V3_MAX_FREQ_NB; i++) map[i] = 0; + + if (!clk_freq) clk_freq = 1000; // set default frequency + speed_index = _stlink_match_speed_map(map, STLINK_ARRAY_SIZE(map), clk_freq); + + i = fill_command(sl, SG_DXFER_FROM_DEV, 16); + + cmd[i++] = STLINK_DEBUG_COMMAND; + cmd[i++] = STLINK_DEBUG_APIV3_SET_COM_FREQ; + cmd[i++] = 0; // SWD mode + cmd[i++] = 0; + cmd[i++] = (uint8_t)((map[speed_index] >> 0) & 0xFF); + cmd[i++] = (uint8_t)((map[speed_index] >> 8) & 0xFF); + cmd[i++] = (uint8_t)((map[speed_index] >> 16) & 0xFF); + cmd[i++] = (uint8_t)((map[speed_index] >> 24) & 0xFF); + + size = send_recv(slu, 1, cmd, slu->cmd_len, data, 8, CMD_CHECK_STATUS, "SET_COM_FREQ"); + + return(size<0?-1:0); + } else if (clk_freq) { + WLOG("ST-Link firmware does not support frequency setup\n"); + } + + return(-1); +} + +int _stlink_usb_exit_debug_mode(stlink_t *sl) { + struct stlink_libusb * const slu = sl->backend_data; + unsigned char* const cmd = sl->c_buf; + ssize_t size; + int i = fill_command(sl, SG_DXFER_FROM_DEV, 0); + + cmd[i++] = STLINK_DEBUG_COMMAND; + cmd[i++] = STLINK_DEBUG_EXIT; + + size = send_only(slu, 1, cmd, slu->cmd_len, "DEBUG_EXIT"); + + return(size<0?-1:0); +} + +int _stlink_usb_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { + struct stlink_libusb * const slu = sl->backend_data; + unsigned char* const data = sl->q_buf; + unsigned char* const cmd = sl->c_buf; + ssize_t size; + int i = fill_command(sl, SG_DXFER_FROM_DEV, len); + + cmd[i++] = STLINK_DEBUG_COMMAND; + cmd[i++] = STLINK_DEBUG_READMEM_32BIT; + write_uint32(&cmd[i], addr); + write_uint16(&cmd[i + 4], len); + size = send_recv(slu, 1, cmd, slu->cmd_len, data, len, CMD_CHECK_NO, "READMEM_32BIT"); + + if (size < 0) { + return(-1); + } + + sl->q_len = (int)size; + stlink_print_data(sl); + + return(0); +} + +int _stlink_usb_read_all_regs(stlink_t *sl, struct stlink_reg *regp) { + struct stlink_libusb * const slu = sl->backend_data; + unsigned char* const cmd = sl->c_buf; + unsigned char* const data = sl->q_buf; + ssize_t size; + uint32_t rep_len = sl->version.jtag_api == STLINK_JTAG_API_V1 ? 84 : 88; + int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); + + cmd[i++] = STLINK_DEBUG_COMMAND; + + if (sl->version.jtag_api == STLINK_JTAG_API_V1) { + cmd[i++] = STLINK_DEBUG_APIV1_READALLREGS; + } else { + cmd[i++] = STLINK_DEBUG_APIV2_READALLREGS; + } + + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_STATUS, "READALLREGS"); + + if (size < 0) { + return(-1); + } + + /* V1: regs data from offset 0 */ + /* V2: status at offset 0, regs data from offset 4 */ + int reg_offset = sl->version.jtag_api == STLINK_JTAG_API_V1 ? 0 : 4; + sl->q_len = (int)size; + stlink_print_data(sl); + + for (i = 0; i < 16; i++) regp->r[i] = read_uint32(sl->q_buf, reg_offset + i * 4); + + regp->xpsr = read_uint32(sl->q_buf, reg_offset + 64); + regp->main_sp = read_uint32(sl->q_buf, reg_offset + 68); + regp->process_sp = read_uint32(sl->q_buf, reg_offset + 72); + regp->rw = read_uint32(sl->q_buf, reg_offset + 76); + regp->rw2 = read_uint32(sl->q_buf, reg_offset + 80); + + if (sl->verbose < 2) { return(0); } + + DLOG("xpsr = 0x%08x\n", regp->xpsr); + DLOG("main_sp = 0x%08x\n", regp->main_sp); + DLOG("process_sp = 0x%08x\n", regp->process_sp); + DLOG("rw = 0x%08x\n", regp->rw); + DLOG("rw2 = 0x%08x\n", regp->rw2); + + return(0); +} + +int _stlink_usb_read_reg(stlink_t *sl, int r_idx, struct stlink_reg *regp) { + struct stlink_libusb * const slu = sl->backend_data; + unsigned char* const data = sl->q_buf; + unsigned char* const cmd = sl->c_buf; + ssize_t size; + uint32_t r; + uint32_t rep_len = sl->version.jtag_api == STLINK_JTAG_API_V1 ? 4 : 8; + int reg_offset = sl->version.jtag_api == STLINK_JTAG_API_V1 ? 0 : 4; + int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); + + cmd[i++] = STLINK_DEBUG_COMMAND; + + if (sl->version.jtag_api == STLINK_JTAG_API_V1) { + cmd[i++] = STLINK_DEBUG_APIV1_READREG; + } else { + cmd[i++] = STLINK_DEBUG_APIV2_READREG; + } + + cmd[i++] = (uint8_t)r_idx; + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_RETRY, "READREG"); + + if (size < 0) { + return(-1); + } + + sl->q_len = (int)size; + stlink_print_data(sl); + r = read_uint32(sl->q_buf, reg_offset); + DLOG("r_idx (%2d) = 0x%08x\n", r_idx, r); + + switch (r_idx) { + case 16: + regp->xpsr = r; + break; + case 17: + regp->main_sp = r; + break; + case 18: + regp->process_sp = r; + break; + case 19: + regp->rw = r; // XXX ?(primask, basemask etc.) + break; + case 20: + regp->rw2 = r; // XXX ?(primask, basemask etc.) + break; + default: + regp->r[r_idx] = r; + } + + return(0); +} + +/* See section C1.6 of the ARMv7-M Architecture Reference Manual */ +int _stlink_usb_read_unsupported_reg(stlink_t *sl, int r_idx, struct stlink_reg *regp) { + uint32_t r; + int ret; + + sl->q_buf[0] = (unsigned char)r_idx; + + for (int i = 1; i < 4; i++) sl->q_buf[i] = 0; + + ret = _stlink_usb_write_mem32(sl, STLINK_REG_DCRSR, 4); + + if (ret == -1) { return(ret); } + + ret = _stlink_usb_read_mem32(sl, STLINK_REG_DCRDR, 4); + + if (ret == -1) { return(ret); } + + r = read_uint32(sl->q_buf, 0); + DLOG("r_idx (%2d) = 0x%08x\n", r_idx, r); + + switch (r_idx) { + case 0x14: + regp->primask = (uint8_t)(r & 0xFF); + regp->basepri = (uint8_t)((r >> 8) & 0xFF); + regp->faultmask = (uint8_t)((r >> 16) & 0xFF); + regp->control = (uint8_t)((r >> 24) & 0xFF); + break; + case 0x21: + regp->fpscr = r; + break; + default: + regp->s[r_idx - 0x40] = r; + break; + } + + return(0); +} + +int _stlink_usb_read_all_unsupported_regs(stlink_t *sl, struct stlink_reg *regp) { + int ret; + + ret = _stlink_usb_read_unsupported_reg(sl, 0x14, regp); + + if (ret == -1) { return(ret); } + + ret = _stlink_usb_read_unsupported_reg(sl, 0x21, regp); + + if (ret == -1) { return(ret); } + + for (int i = 0; i < 32; i++) { + ret = _stlink_usb_read_unsupported_reg(sl, 0x40 + i, regp); + + if (ret == -1) { return(ret); } + } + + return(0); +} + +/* See section C1.6 of the ARMv7-M Architecture Reference Manual */ +int _stlink_usb_write_unsupported_reg(stlink_t *sl, uint32_t val, int r_idx, struct stlink_reg *regp) { + int ret; + + if (r_idx >= 0x1C && r_idx <= 0x1F) { // primask, basepri, faultmask, or control + /* These are held in the same register */ + ret = _stlink_usb_read_unsupported_reg(sl, 0x14, regp); + + if (ret == -1) { return(ret); } + + val = (uint8_t)(val >> 24); + + switch (r_idx) { + case 0x1C: /* control */ + val = (((uint32_t)val) << 24) | + (((uint32_t)regp->faultmask) << 16) | + (((uint32_t)regp->basepri) << 8) | + ((uint32_t)regp->primask); + break; + case 0x1D: /* faultmask */ + val = (((uint32_t)regp->control) << 24) | + (((uint32_t)val) << 16) | + (((uint32_t)regp->basepri) << 8) | + ((uint32_t)regp->primask); + break; + case 0x1E: /* basepri */ + val = (((uint32_t)regp->control) << 24) | + (((uint32_t)regp->faultmask) << 16) | + (((uint32_t)val) << 8) | + ((uint32_t)regp->primask); + break; + case 0x1F: /* primask */ + val = (((uint32_t)regp->control) << 24) | + (((uint32_t)regp->faultmask) << 16) | + (((uint32_t)regp->basepri) << 8) | + ((uint32_t)val); + break; + } + + r_idx = 0x14; + } + + write_uint32(sl->q_buf, val); + + ret = _stlink_usb_write_mem32(sl, STLINK_REG_DCRDR, 4); + + if (ret == -1) { return(ret); } + + sl->q_buf[0] = (unsigned char)r_idx; + sl->q_buf[1] = 0; + sl->q_buf[2] = 0x01; + sl->q_buf[3] = 0; + + return(_stlink_usb_write_mem32(sl, STLINK_REG_DCRSR, 4)); +} + +int _stlink_usb_write_reg(stlink_t *sl, uint32_t reg, int idx) { + struct stlink_libusb * const slu = sl->backend_data; + unsigned char* const data = sl->q_buf; + unsigned char* const cmd = sl->c_buf; + ssize_t size; + uint32_t rep_len = 2; + int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); + + cmd[i++] = STLINK_DEBUG_COMMAND; + + if (sl->version.jtag_api == STLINK_JTAG_API_V1) { + cmd[i++] = STLINK_DEBUG_APIV1_WRITEREG; + } else { + cmd[i++] = STLINK_DEBUG_APIV2_WRITEREG; + } + + cmd[i++] = idx; + write_uint32(&cmd[i], reg); + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_RETRY, "WRITEREG"); + + return(size<0?-1:0); +} + +int _stlink_usb_enable_trace(stlink_t* sl, uint32_t frequency) { + struct stlink_libusb * const slu = sl->backend_data; + unsigned char* const data = sl->q_buf; + unsigned char* const cmd = sl->c_buf; + ssize_t size; + uint32_t rep_len = 2; + + int i = fill_command(sl, SG_DXFER_TO_DEV, rep_len); + cmd[i++] = STLINK_DEBUG_COMMAND; + cmd[i++] = STLINK_DEBUG_APIV2_START_TRACE_RX; + write_uint16(&cmd[i + 0], 2 * STLINK_TRACE_BUF_LEN); + write_uint32(&cmd[i + 2], frequency); + + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_STATUS, "START_TRACE_RX"); + + return(size<0?-1:0); +} + +int _stlink_usb_disable_trace(stlink_t* sl) { + struct stlink_libusb * const slu = sl->backend_data; + unsigned char* const data = sl->q_buf; + unsigned char* const cmd = sl->c_buf; + ssize_t size; + uint32_t rep_len = 2; + + int i = fill_command(sl, SG_DXFER_TO_DEV, rep_len); + cmd[i++] = STLINK_DEBUG_COMMAND; + cmd[i++] = STLINK_DEBUG_APIV2_STOP_TRACE_RX; + + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_STATUS, "STOP_TRACE_RX"); + + return(size<0?-1:0); +} + +int _stlink_usb_read_trace(stlink_t* sl, uint8_t* buf, size_t size) { + struct stlink_libusb * const slu = sl->backend_data; + unsigned char* const data = sl->q_buf; + unsigned char* const cmd = sl->c_buf; + uint32_t rep_len = 2; + int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); + + cmd[i++] = STLINK_DEBUG_COMMAND; + cmd[i++] = STLINK_DEBUG_APIV2_GET_TRACE_NB; + ssize_t send_size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_NO, "GET_TRACE_NB"); + + if (send_size < 0) { + return(-1); + } else if (send_size != 2) { + ELOG("STLINK_DEBUG_APIV2_GET_TRACE_NB reply size %d\n", (int)send_size); + return(-1); + } + + uint16_t trace_count = read_uint16(sl->q_buf, 0); + + if (trace_count > size) { + ELOG("read_trace insufficient buffer length\n"); + return -1; + } + + if (trace_count != 0) { + int res = 0; + int t = libusb_bulk_transfer(slu->usb_handle, slu->ep_trace, buf, trace_count, &res, 3000); + + if (t || res != (int)trace_count) { + ELOG("read_trace read error %d\n", t); + return(-1); + } + } + + return trace_count; +} + +static stlink_backend_t _stlink_usb_backend = { + _stlink_usb_close, + _stlink_usb_exit_debug_mode, + _stlink_usb_enter_swd_mode, + NULL, // don't enter_jtag_mode here... + _stlink_usb_exit_dfu_mode, + _stlink_usb_core_id, + _stlink_usb_reset, + _stlink_usb_jtag_reset, + _stlink_usb_run, + _stlink_usb_status, + _stlink_usb_version, + _stlink_usb_read_debug32, + _stlink_usb_read_mem32, + _stlink_usb_write_debug32, + _stlink_usb_write_mem32, + _stlink_usb_write_mem8, + _stlink_usb_read_all_regs, + _stlink_usb_read_reg, + _stlink_usb_read_all_unsupported_regs, + _stlink_usb_read_unsupported_reg, + _stlink_usb_write_unsupported_reg, + _stlink_usb_write_reg, + _stlink_usb_step, + _stlink_usb_current_mode, + _stlink_usb_force_debug, + _stlink_usb_target_voltage, + _stlink_usb_set_swdclk, + _stlink_usb_enable_trace, + _stlink_usb_disable_trace, + _stlink_usb_read_trace +}; + +/* return the length of serial or (0) in case of errors */ +size_t stlink_serial(struct libusb_device_handle *handle, struct libusb_device_descriptor *desc, char *serial) { + unsigned char desc_serial[(STLINK_SERIAL_LENGTH) * 2]; + + /* truncate the string in the serial buffer */ + serial[0] = '\0'; + + /* get the LANGID from String Descriptor Zero */ + int ret = libusb_get_string_descriptor(handle, 0, 0, desc_serial, sizeof(desc_serial)); + if (ret < 4) return 0; + + uint32_t langid = desc_serial[2] | (desc_serial[3] << 8); + + /* get the serial */ + ret = libusb_get_string_descriptor(handle, desc->iSerialNumber, langid, desc_serial, + sizeof(desc_serial)); + if (ret < 0) return 0; // could not read serial + + unsigned char len = desc_serial[0]; + + if (len == ((STLINK_SERIAL_LENGTH + 1) * 2)) { /* len == 50 */ + /* good ST-Link adapter */ + ret = libusb_get_string_descriptor_ascii( + handle, desc->iSerialNumber, (unsigned char *)serial, STLINK_SERIAL_BUFFER_SIZE); + if (ret < 0) return 0; + } else if (len == ((STLINK_SERIAL_LENGTH / 2 + 1) * 2)) { /* len == 26 */ + /* fix-up the buggy serial */ + for (unsigned int i = 0; i < STLINK_SERIAL_LENGTH; i += 2) + sprintf(serial + i, "%02X", desc_serial[i + 2]); + serial[STLINK_SERIAL_LENGTH] = '\0'; + } else { + return 0; + } + + return strlen(serial); +} + +stlink_t *stlink_open_usb(enum ugly_loglevel verbose, enum connect_type connect, char serial[STLINK_SERIAL_BUFFER_SIZE], int freq) { + stlink_t* sl = NULL; + struct stlink_libusb* slu = NULL; + int ret = -1; + int config; + + sl = calloc(1, sizeof(stlink_t)); + if (sl == NULL) { goto on_malloc_error; } + + slu = calloc(1, sizeof(struct stlink_libusb)); + if (slu == NULL) { goto on_malloc_error; } + + ugly_init(verbose); + sl->backend = &_stlink_usb_backend; + sl->backend_data = slu; + + sl->core_stat = TARGET_UNKNOWN; + + if (libusb_init(&(slu->libusb_ctx))) { + WLOG("failed to init libusb context, wrong version of libraries?\n"); + goto on_error; + } + +#if LIBUSB_API_VERSION < 0x01000106 + libusb_set_debug(slu->libusb_ctx, ugly_libusb_log_level(verbose)); +#else + libusb_set_option(slu->libusb_ctx, LIBUSB_OPTION_LOG_LEVEL, ugly_libusb_log_level(verbose)); +#endif + + libusb_device **list = NULL; + // TODO: We should use ssize_t and use it as a counter if > 0. + // As per libusb API: ssize_t libusb_get_device_list (libusb_context *ctx, libusb_device ***list) + ssize_t cnt = libusb_get_device_list(slu->libusb_ctx, &list); + struct libusb_device_descriptor desc; + + while (cnt-- > 0) { + struct libusb_device_handle *handle; + + libusb_get_device_descriptor(list[cnt], &desc); + + if (desc.idVendor != STLINK_USB_VID_ST) { continue; } + + ret = libusb_open(list[cnt], &handle); + + if (ret) { continue; } // could not open device + + size_t serial_len = stlink_serial(handle, &desc, sl->serial); + + libusb_close(handle); + + if (serial_len != STLINK_SERIAL_LENGTH) { continue; } // could not read the serial + + // if no serial provided, or if serial match device, fixup version and protocol + if (((serial == NULL) || (*serial == 0)) || (memcmp(serial, &sl->serial, STLINK_SERIAL_LENGTH) == 0)) { + if (STLINK_V1_USB_PID(desc.idProduct)) { + slu->protocoll = 1; + sl->version.stlink_v = 1; + } else if (STLINK_V2_USB_PID(desc.idProduct) || STLINK_V2_1_USB_PID(desc.idProduct)) { + sl->version.stlink_v = 2; + } else if (STLINK_V3_USB_PID(desc.idProduct)) { + sl->version.stlink_v = 3; + } + + break; + } + } + + if (cnt < 0) { + WLOG ("Couldn't find any ST-Link devices\n"); + libusb_free_device_list(list, 1); + goto on_error; + } else { + ret = libusb_open(list[cnt], &slu->usb_handle); + + if (ret != 0) { + WLOG("Error %d (%s) opening ST-Link v%d device %03d:%03d\n", ret, + strerror(errno), + sl->version.stlink_v, + libusb_get_bus_number(list[cnt]), + libusb_get_device_address(list[cnt])); + libusb_free_device_list(list, 1); + goto on_error; + } + } + + libusb_free_device_list(list, 1); + +// libusb_kernel_driver_active is not available on Windows. +#if !defined(_WIN32) + if (libusb_kernel_driver_active(slu->usb_handle, 0) == 1) { + ret = libusb_detach_kernel_driver(slu->usb_handle, 0); + + if (ret < 0) { + WLOG("libusb_detach_kernel_driver(() error %s\n", strerror(-ret)); + goto on_libusb_error; + } + } +#endif + + if (libusb_get_configuration(slu->usb_handle, &config)) { + // this may fail for a previous configured device + WLOG("libusb_get_configuration()\n"); + goto on_libusb_error; + } + + if (config != 1) { + printf("setting new configuration (%d -> 1)\n", config); + + if (libusb_set_configuration(slu->usb_handle, 1)) { + // this may fail for a previous configured device + WLOG("libusb_set_configuration() failed\n"); + goto on_libusb_error; + } + } + + if (libusb_claim_interface(slu->usb_handle, 0)) { + WLOG("Stlink usb device found, but unable to claim (probably already in use?)\n"); + goto on_libusb_error; + } + + // TODO: Could use the scanning technique from STM8 code here... + slu->ep_rep = 1 /* ep rep */ | LIBUSB_ENDPOINT_IN; + + if (desc.idProduct == STLINK_USB_PID_STLINK_NUCLEO || + desc.idProduct == STLINK_USB_PID_STLINK_32L_AUDIO || + desc.idProduct == STLINK_USB_PID_STLINK_V2_1 || + desc.idProduct == STLINK_USB_PID_STLINK_V3_USBLOADER || + desc.idProduct == STLINK_USB_PID_STLINK_V3E_PID || + desc.idProduct == STLINK_USB_PID_STLINK_V3S_PID || + desc.idProduct == STLINK_USB_PID_STLINK_V3_2VCP_PID || + desc.idProduct == STLINK_USB_PID_STLINK_V3_NO_MSD_PID) { + slu->ep_req = 1 /* ep req */ | LIBUSB_ENDPOINT_OUT; + slu->ep_trace = 2 | LIBUSB_ENDPOINT_IN; + } else { + slu->ep_req = 2 /* ep req */ | LIBUSB_ENDPOINT_OUT; + slu->ep_trace = 3 | LIBUSB_ENDPOINT_IN; + } + + slu->sg_transfer_idx = 0; + slu->cmd_len = (slu->protocoll == 1) ? STLINK_SG_SIZE : STLINK_CMD_SIZE; + + // initialize stlink version (sl->version) + stlink_version(sl); + + int mode = stlink_current_mode(sl); + if (mode == STLINK_DEV_DFU_MODE) { + DLOG("-- exit_dfu_mode\n"); + _stlink_usb_exit_dfu_mode(sl); + } + + if (connect == CONNECT_UNDER_RESET) { + // for the connect under reset only + // OpenOСD says (official documentation is not available) that + // the NRST pin must be pull down before selecting the SWD/JTAG mode + if (mode == STLINK_DEV_DEBUG_MODE) { + DLOG("-- exit_debug_mode\n"); + _stlink_usb_exit_debug_mode(sl); + } + + _stlink_usb_jtag_reset(sl, STLINK_DEBUG_APIV2_DRIVE_NRST_LOW); + } + + sl->freq = freq; + // set the speed before entering the mode as the chip discovery phase + // should be done at this speed too + // set the stlink clock speed (default is 1800kHz) + DLOG("JTAG/SWD freq set to %d\n", freq); + _stlink_usb_set_swdclk(sl, freq); + + stlink_target_connect(sl, connect); + return(sl); + +on_libusb_error: + stlink_close(sl); + return(NULL); + +on_error: + if (slu->libusb_ctx) { libusb_exit(slu->libusb_ctx); } + +on_malloc_error: + if (sl != NULL) { free(sl); } + if (slu != NULL) { free(slu); } + + return(NULL); +} + +static size_t stlink_probe_usb_devs(libusb_device **devs, stlink_t **sldevs[], enum connect_type connect, int freq) { + stlink_t **_sldevs; + libusb_device *dev; + int i = 0; + size_t slcnt = 0; + size_t slcur = 0; + + /* Count STLINKs */ + while ((dev = devs[i++]) != NULL) { + struct libusb_device_descriptor desc; + int ret = libusb_get_device_descriptor(dev, &desc); + + if (ret < 0) { + WLOG("failed to get libusb device descriptor (libusb error: %d)\n", ret); + break; + } + + if (desc.idVendor != STLINK_USB_VID_ST) { continue; } + + if (!STLINK_SUPPORTED_USB_PID(desc.idProduct)) { + WLOG("skipping ST device : %#04x:%#04x)\n", desc.idVendor, desc.idProduct); + continue; + } + + slcnt++; + } + + _sldevs = calloc(slcnt, sizeof(stlink_t *)); // allocate list of pointers + + if (!_sldevs) { + *sldevs = NULL; + return(0); + } + + /* Open STLINKS and attach them to list */ + i = 0; + + while ((dev = devs[i++]) != NULL) { + struct libusb_device_descriptor desc; + int ret = libusb_get_device_descriptor(dev, &desc); + + if (ret < 0) { + WLOG("failed to get libusb device descriptor (libusb error: %d)\n", ret); + break; + } + + if (!STLINK_SUPPORTED_USB_PID(desc.idProduct)) { continue; } + + struct libusb_device_handle* handle; + char serial[STLINK_SERIAL_BUFFER_SIZE] = {0, }; + + ret = libusb_open(dev, &handle); + + if (ret < 0) { + if (ret == LIBUSB_ERROR_ACCESS) { + ELOG("Could not open USB device %#06x:%#06x, access error.\n", desc.idVendor, desc.idProduct); + } else { + ELOG("Failed to open USB device %#06x:%#06x, libusb error: %d)\n", desc.idVendor, desc.idProduct, ret); + } + + break; + } + + size_t serial_len = stlink_serial(handle, &desc, serial); + + libusb_close(handle); + + if (serial_len != STLINK_SERIAL_LENGTH) { continue; } + + stlink_t *sl = stlink_open_usb(0, connect, serial, freq); + + if (!sl) { + ELOG("Failed to open USB device %#06x:%#06x\n", desc.idVendor, desc.idProduct); + continue; + } + + _sldevs[slcur++] = sl; + } + + *sldevs = _sldevs; + + return(slcur); +} + +size_t stlink_probe_usb(stlink_t **stdevs[], enum connect_type connect, int freq) { + libusb_device **devs; + stlink_t **sldevs; + + size_t slcnt = 0; + int r; + ssize_t cnt; + + r = libusb_init(NULL); + + if (r < 0) { return(0); } + + cnt = libusb_get_device_list(NULL, &devs); + + if (cnt < 0) { return(0); } + + slcnt = stlink_probe_usb_devs(devs, &sldevs, connect, freq); + libusb_free_device_list(devs, 1); + + libusb_exit(NULL); + + *stdevs = sldevs; + + return(slcnt); +} + +void stlink_probe_usb_free(stlink_t ***stdevs, size_t size) { + if (stdevs == NULL || *stdevs == NULL || size == 0) { return; } + + for (size_t n = 0; n < size; n++) { stlink_close((*stdevs)[n]); } + + free(*stdevs); + *stdevs = NULL; +} diff --git a/src/win32/unistd/unistd.h b/src/win32/unistd/unistd.h index 389c44664..cb6da4b8a 100644 --- a/src/win32/unistd/unistd.h +++ b/src/win32/unistd/unistd.h @@ -52,7 +52,7 @@ #define ssize_t int #ifndef SSIZE_MAX -#define SSIZE_MAX ((sizeof(ssize_t) == 4) ? 2147483647 : 9223372036854775807) +#define SSIZE_MAX ((sizeof(ssize_t) == 4) ? 1073741824 : ‭4611686018427387904‬) #endif #define STDIN_FILENO 0 diff --git a/src/win32/unistd/unistd.h.bak b/src/win32/unistd/unistd.h.bak new file mode 100644 index 000000000..47967e45e --- /dev/null +++ b/src/win32/unistd/unistd.h.bak @@ -0,0 +1,76 @@ +#ifndef _UNISTD_H +#define _UNISTD_H 1 + +/* + * This file intended to serve as a drop-in replacement for unistd.h on Windows + * Please add functionality as needed. + */ + +#include +#include + +#if defined(_MSC_VER) +#pragma warning(push) +#pragma warning(disable: 4820) +#endif + +#include + +#if defined(_MSC_VER) +#pragma warning(pop) +#endif + +#include // getopt at: https://gist.github.com/ashelly/7776712 +#include // for getpid() and the exec..() family +#include // for _getcwd() and _chdir() + +#define srandom srand +#define random rand + +/* Values for the second argument to access. These may be OR'd together. */ +#define R_OK 4 // Test for read permission +#define W_OK 2 // Test for write permission +// #define X_OK 1 // execute permission - unsupported in windows +#define F_OK 0 // Test for existence + +#define access _access +#define dup2 _dup2 +#define execve _execve +#define ftruncate _chsize +#define unlink _unlink +#define fileno _fileno +#define getcwd _getcwd +#define chdir _chdir +#define isatty _isatty +#define lseek _lseek + +/* + * Read, write, and close are NOT being defined here, + * because while there are file handle specific versions for Windows, they probably don't work for sockets. + * You need to look at your app and consider whether to call e.g. closesocket(). + */ + +#define ssize_t int +#ifndef SSIZE_MAX +//#define SSIZE_MAX ((sizeof(ssize_t) == 4) ? 2147483647 : 9223372036854775807) +#define SSIZE_MAX ((sizeof(ssize_t) == 4) ? 1073741824 : ‭4611686018427387904‬) +#endif + +#define STDIN_FILENO 0 +#define STDOUT_FILENO 1 +#define STDERR_FILENO 2 +// should be in some equivalent to +typedef __int8 int8_t; +typedef __int16 int16_t; +typedef __int32 int32_t; +typedef __int64 int64_t; +typedef unsigned __int8 uint8_t; +typedef unsigned __int16 uint16_t; +typedef unsigned __int32 uint32_t; +typedef unsigned __int64 uint64_t; + +#ifndef STLINK_HAVE_UNISTD_H +int usleep(unsigned int waitTime); +#endif + +#endif // _UNISTD_H diff --git "a/src/\320\236\320\277\320\270\321\201\320\260\320\275\320\270\320\265.txt" "b/src/\320\236\320\277\320\270\321\201\320\260\320\275\320\270\320\265.txt" new file mode 100644 index 000000000..d4111a8b2 --- /dev/null +++ "b/src/\320\236\320\277\320\270\321\201\320\260\320\275\320\270\320\265.txt" @@ -0,0 +1,129 @@ +--------------------------------------------------------------------------------- +Файл info.c: + +main: +- проверяю количество параметров +- инициализирую список структур devicelist, объявленный в файле chipid.c +- вызываю функцию print_data (и передаю ей параметры программы). + +print_data: +Смотрю, какие параметры переданы программе. +Если параметр --probe - вызываю функцию stlink_probe с параметрами по умолчанию +(connect: NORMAL, freq: 0) + +stlink_probe: +Объявляю список структур для каждого подключенного ST-LINK'a +(stdevs: указатель на список указателей, указывающих на структуры). +Вызываю stlink_probe_usb с параметрами: +- адрес stdevs'а (тройной указатель), +- connect, +- freq + +Функция stlink_probe_usb заполняет stdevs и возвращает его размер. +Для каждого указателя вызываю функцию stlink_print_info. + +Потом освобождаю память, отведённую под stdevs. + +stlink_print_info: просто печатаю в терминал информацию из переданной структуры +ST-LINK'а. + +--------------------------------------------------------------------------------- +Файл usb.c: + +stlink_probe_usb: +Инициализирую libusb +Получаю список USB-устройств (libusb_get_device_list). +Для полученного списка вызываю функцию stlink_probe_usb_devs. +Передаю ей: +- указатель на список указателей на структуры libusb_device (двойной указатель) devs +- адрес указателя на список указателей на структуры ST-LINK (тройной указатель) sldevs +- connect, freq. +Потом освобождаю память, занятую структурами libusb_device. +Список указателей на структуры ST-LINK возвращаю на выход (в функцию stlink_probe). + +stlink_probe_usb_devs: +Определяю количество подключенных ST-LINK'ов: +Прохожу по списку USB-устройств. +Для каждого USB-устройства получаю дескриптор desc. +Если в дескрипторе указаны idVendor и idProduct, соответствующие ST-LINK'у - увеличиваю счётчик. +Выделяю память под нужное количество структур ST-LINK'ов. + +Ещё раз прохожу по списку USB-устройств и получаю дескриптор каждого. +Если idProduct соответствует ST-LINK'у: +- открываю ST-LINK (libusb_open), +- читаю его серийник (stlink_serial); +- закрываю (libusb_close). + +Если длина серийника правильная - открываю его функцией stlink_open_usb. +Она возвращает ссылку на структуру stlink_t. Пристёгиваю эту ссылку к списку структур. +Перехожу к следюущему USB-устройству. Потом записываю ссылку на список структур stlink_t +в указатель и возвращаю количество структур по списку. + +stlink_serial: +Получаю дескриптор нулевой строки USB-устройства, беру из него LANGID (libusb_get_string_descriptor). +Получаю дескриптор строки серийника (для него нужен LANGID) (libusb_get_string_descriptor). +Если серийник длиной 50 символов - беру его же в формате ascii. +Если серийник длиной 26 символов - для каждого символа выполняю строку: +sprintf(serial + i, "%02X", desc_serial[i + 2]) +В конце ставлю ноль. +Возвращаю длину серийника и сам серийник, записанный в память по адресу из параметра. + +stlink_open_usb: +Выделяю в куче память под структуры sl (stlink_t) и slu (stlink_libusb). +Записываю в sl ссылку на список каких-то функций и ссылку на slu, указываю статус ядра +целевого MCU: TARGET_UNKNOWN. +Инициализирую libusb с контекстом, указываю LOG_LEVEL. +Получаю список USB-устройств. +Для каждого устройства получаю дескриптор и проверяю его idVendor. +Открываю устройство и пытаюсь получить серийник. +Если не получил серийник либо получил серийник, соответствующий заданному в параметре - +- выставляю в структуре sl версию и протокол по idProduct, после чего заканчиваю просмотр +устройств USB. + +Просмотрев все устройства, открываю найденный ST-LINK и освобождаю память, занятую +списком USB-устройств. + +Читаю конфигурацию ST-LINK'а, потом устанавливаю её. Делаю заявку на интерфейс (libusb_claim_interface). +Потом выставляю поля ep_rep, ep_req, ep_trace, sg_transfer_idx и cmd_len. +Инициализирую версию ST-LINK'а (stlink_version). +Получаю режим работы ST-LINK'а. Если он в режиме dfu - выхожу из него. +Если CONNECT_UNDER_RESET: выхожу из debug mode, если в нём. Выполняю JTAG reset. +Выставляю поле freq по параметру функции, устанавливаю SWD clock (_stlink_usb_set_swdclk). +Выполняю stlink_target_connect и возвращаю структуру sl. + +_stlink_usb_version: +Заполняю структуру stlink командой fill_command (по-разному для ST-LINK v. 3 и предыдущих версий) +Выполняю функцию send_recv + + +_stlink_usb_current_mode: +Заполняю структуру stlink командой fill_command, ставлю в i-тую позицию команду STLINK_GET_CURRENT_MODE +Вызываю функцию send_recv +Возвращаю первый символ буфера, или -1 при ошибке. + +_stlink_usb_exit_debug_mode, _stlink_usb_exit_debug_mode: +Заполняю структуру stlink командой fill_command, ставлю в i-тую позицию команды: +STLINK_DFU_COMMAND +STLINK_DFU_EXIT +Вызываю функцию send_only +Возвращаю 0, или -1 при ошибке. +То же самое для debug + +fill_command: +Для ST-LINK v. 1 заполняю поле c_buf структуры stlink. Для всех остальных заполняю его нулями. + +send_recv: +Отправляю функцией libusb_bulk_transfer данные в параметре txbuf и команду в cmd. +Проверяю ответ на ошибки и если указан rxsize - принимаю данные той же функцией. +Возвращаю количество принятого после проверки на ошибки. + +--------------------------------------------------------------------------------- +Файл common.c: + +stlink_version: +Запускаю функцию version из backend (вызывается _stlink_usb_version из usb.c) +Выполняю _parse_version. + +stlink_current_mode: +возвращаю результат выполнения функции sl->backend->current_mode(sl) после проверки на ошибки. +При этом запускается функция _stlink_usb_current_mode. \ No newline at end of file diff --git a/stlinkv1_macos_driver/install.sh b/stlinkv1_macos_driver/install.sh index f9878bd46..5716281a1 100644 --- a/stlinkv1_macos_driver/install.sh +++ b/stlinkv1_macos_driver/install.sh @@ -2,6 +2,9 @@ ISMACOS=$(sw_vers -productVersion) case $ISMACOS in +10.14*) + KEXT="stlink_shield_10_14.kext" + ;; 10.15*) KEXT="stlink_shield_10_15.kext" ;; diff --git a/stlinkv1_macos_driver/stlink_shield_10_14.kext/Contents/Info.plist b/stlinkv1_macos_driver/stlink_shield_10_14.kext/Contents/Info.plist new file mode 100644 index 000000000..fd424ea93 --- /dev/null +++ b/stlinkv1_macos_driver/stlink_shield_10_14.kext/Contents/Info.plist @@ -0,0 +1,82 @@ + + + + + BuildMachineOSBuild + 18G7016 + CFBundleDevelopmentRegion + English + CFBundleIdentifier + com.libusb.stlink-shield + CFBundleInfoDictionaryVersion + 6.0 + CFBundlePackageType + KEXT + CFBundleSignature + ???? + CFBundleSupportedPlatforms + + MacOSX + + CFBundleVersion + 1.0.0 + DTCompiler + com.apple.compilers.llvm.clang.1_0 + DTPlatformBuild + 11C504 + DTPlatformVersion + GM + DTSDKBuild + 19B90 + DTSDKName + macosx10.15 + DTXcode + 1130 + DTXcodeBuild + 11C504 + IOKitPersonalities + + DeviceDriver + + CFBundleIdentifier + com.apple.kpi.iokit + IOClass + IOService + IOProviderClass + IOUSBDevice + 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nested + + weight + 10 + + ^.* + + ^Info\.plist$ + + omit + + weight + 20 + + ^PkgInfo$ + + omit + + weight + 20 + + ^Resources/ + + weight + 20 + + ^Resources/.*\.lproj/ + + optional + + weight + 1000 + + ^Resources/.*\.lproj/locversion.plist$ + + omit + + weight + 1100 + + ^Resources/Base\.lproj/ + + weight + 1010 + + ^[^/]+$ + + nested + + weight + 10 + + ^embedded\.provisionprofile$ + + weight + 20 + + ^version\.plist$ + + weight + 20 + + + + diff --git a/stlinkv1_macos_driver/stlink_shield_xcode/stlink_shield.xcodeproj/project.pbxproj b/stlinkv1_macos_driver/stlink_shield_xcode/stlink_shield.xcodeproj/project.pbxproj index 373600c64..4f2b80254 100644 --- a/stlinkv1_macos_driver/stlink_shield_xcode/stlink_shield.xcodeproj/project.pbxproj +++ b/stlinkv1_macos_driver/stlink_shield_xcode/stlink_shield.xcodeproj/project.pbxproj @@ -8,6 +8,7 @@ /* Begin PBXFileReference section */ 8CD33C31149BB80D0033D618 /* Info.plist */ = {isa = PBXFileReference; lastKnownFileType = text.plist.xml; path = Info.plist; sourceTree = ""; }; + 8F9084FD24786F0F009109AD /* stlink_shield_10_14.kext */ = {isa = PBXFileReference; explicitFileType = wrapper.cfbundle; includeInIndex = 0; path = stlink_shield_10_14.kext; sourceTree = BUILT_PRODUCTS_DIR; }; 8F90850924786F39009109AD /* stlink_shield_10_15.kext */ = {isa = PBXFileReference; explicitFileType = wrapper.cfbundle; includeInIndex = 0; path = stlink_shield_10_15.kext; sourceTree = BUILT_PRODUCTS_DIR; }; /* End PBXFileReference section */ @@ -33,6 +34,7 @@ 19C28FB6FE9D52B211CA2CBB /* Products */ = { isa = PBXGroup; children = ( + 8F9084FD24786F0F009109AD /* stlink_shield_10_14.kext */, 8F90850924786F39009109AD /* stlink_shield_10_15.kext */, ); name = Products; @@ -58,6 +60,26 @@ /* End PBXHeadersBuildPhase section */ /* Begin PBXNativeTarget section */ + 8F9084F324786F0F009109AD /* stlink_shield_10_14 */ = { + isa = PBXNativeTarget; + buildConfigurationList = 8F9084FA24786F0F009109AD /* Build configuration list for PBXNativeTarget "stlink_shield_10_14" */; + buildPhases = ( + 8F9084F424786F0F009109AD /* ShellScript */, + 8F9084F524786F0F009109AD /* Headers */, + 8F9084F624786F0F009109AD /* Resources */, + 8F9084F824786F0F009109AD /* Sources */, + 8F9084F924786F0F009109AD /* ShellScript */, + ); + buildRules = ( + ); + dependencies = ( + ); + name = stlink_shield_10_14; + productInstallPath = "$(SYSTEM_LIBRARY_DIR)/Extensions"; + productName = NanosMouse; + productReference = 8F9084FD24786F0F009109AD /* stlink_shield_10_14.kext */; + productType = "com.apple.product-type.kernel-extension.iokit"; + }; 8F9084FF24786F39009109AD /* stlink_shield_10_15 */ = { isa = PBXNativeTarget; buildConfigurationList = 8F90850624786F39009109AD /* Build configuration list for PBXNativeTarget "stlink_shield_10_15" */; @@ -98,6 +120,7 @@ projectDirPath = ""; projectRoot = ""; targets = ( + 8F9084F324786F0F009109AD /* stlink_shield_10_14 */, 8F9084FF24786F39009109AD /* stlink_shield_10_15 */, ); }; @@ -435,6 +458,24 @@ }; name = Release; }; + 8F9084FB24786F0F009109AD /* Debug */ = { + isa = XCBuildConfiguration; + buildSettings = { + CODE_SIGN_IDENTITY = "-"; + MACOSX_DEPLOYMENT_TARGET = 10.14; + PRODUCT_NAME = "$(TARGET_NAME)"; + }; + name = Debug; + }; + 8F9084FC24786F0F009109AD /* Release */ = { + isa = XCBuildConfiguration; + buildSettings = { + CODE_SIGN_IDENTITY = "-"; + MACOSX_DEPLOYMENT_TARGET = 10.14; + PRODUCT_NAME = "$(TARGET_NAME)"; + }; + name = Release; + }; 8F90850724786F39009109AD /* Debug */ = { isa = XCBuildConfiguration; buildSettings = { @@ -465,6 +506,15 @@ defaultConfigurationIsVisible = 0; defaultConfigurationName = Release; }; + 8F9084FA24786F0F009109AD /* Build configuration list for PBXNativeTarget "stlink_shield_10_14" */ = { + isa = XCConfigurationList; + buildConfigurations = ( + 8F9084FB24786F0F009109AD /* Debug */, + 8F9084FC24786F0F009109AD /* Release */, + ); + defaultConfigurationIsVisible = 0; + defaultConfigurationName = Release; + }; 8F90850624786F39009109AD /* Build configuration list for PBXNativeTarget "stlink_shield_10_15" */ = { isa = XCConfigurationList; buildConfigurations = ( From 5b320357a64458d102e190e4aeff2d58a3011e60 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sat, 29 Jan 2022 17:56:26 +0100 Subject: [PATCH 367/503] Minor formatting fixes & clean-up --- CMakeLists.txt | 6 +- src/calculate.h | 2 +- src/common.h | 2 +- src/common_flash.h | 2 +- src/map_file.h | 2 +- src/{option.c => option_bytes.c} | 0 ...1\201\320\260\320\275\320\270\320\265.txt" | 129 ------------------ 7 files changed, 7 insertions(+), 136 deletions(-) rename src/{option.c => option_bytes.c} (100%) delete mode 100644 "src/\320\236\320\277\320\270\321\201\320\260\320\275\320\270\320\265.txt" diff --git a/CMakeLists.txt b/CMakeLists.txt index a3338df71..abfc0be47 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -2,7 +2,7 @@ # General cmake settings ### -cmake_minimum_required(VERSION 3.7.2) +cmake_minimum_required(VERSION 3.10.2) cmake_policy(SET CMP0042 NEW) set(CMAKE_MODULE_PATH ${CMAKE_SOURCE_DIR}/cmake/modules) set(CMAKE_ARCHIVE_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}/lib) @@ -127,8 +127,8 @@ set(STLINK_HEADERS set(STLINK_SOURCE src/read_write.c src/common.c - src/option.c - src/common_flash.c + src/option_bytes.c + src/common_flash.c src/map_file.c src/flashloader.c src/calculate.c diff --git a/src/calculate.h b/src/calculate.h index 68c1fb988..64dfb51b2 100644 --- a/src/calculate.h +++ b/src/calculate.h @@ -1,7 +1,7 @@ /* * File: calculate.h * - * TODO: add a description + * Calculation of sector numbers and pages */ #ifndef CALCULATE_H diff --git a/src/common.h b/src/common.h index 6c22d58c0..dd6cf95b2 100644 --- a/src/common.h +++ b/src/common.h @@ -1,7 +1,7 @@ /* * File: common.h * - * TODO: add a description + * General helper functions */ #ifndef COMMON_H diff --git a/src/common_flash.h b/src/common_flash.h index 70a6f0e04..3b6b0404a 100644 --- a/src/common_flash.h +++ b/src/common_flash.h @@ -1,7 +1,7 @@ /* * File: common_flash.h * - * TODO: add a description + * Flash operations */ #ifndef COMMON_FLASH_H diff --git a/src/map_file.h b/src/map_file.h index 9cdd745e6..f50a201f0 100644 --- a/src/map_file.h +++ b/src/map_file.h @@ -1,7 +1,7 @@ /* * File: map_file.h * - * TODO: add a description + * File mapping */ #ifndef MAP_FILE_H diff --git a/src/option.c b/src/option_bytes.c similarity index 100% rename from src/option.c rename to src/option_bytes.c diff --git "a/src/\320\236\320\277\320\270\321\201\320\260\320\275\320\270\320\265.txt" "b/src/\320\236\320\277\320\270\321\201\320\260\320\275\320\270\320\265.txt" deleted file mode 100644 index d4111a8b2..000000000 --- "a/src/\320\236\320\277\320\270\321\201\320\260\320\275\320\270\320\265.txt" +++ /dev/null @@ -1,129 +0,0 @@ ---------------------------------------------------------------------------------- -Файл info.c: - -main: -- проверяю количество параметров -- инициализирую список структур devicelist, объявленный в файле chipid.c -- вызываю функцию print_data (и передаю ей параметры программы). - -print_data: -Смотрю, какие параметры переданы программе. -Если параметр --probe - вызываю функцию stlink_probe с параметрами по умолчанию -(connect: NORMAL, freq: 0) - -stlink_probe: -Объявляю список структур для каждого подключенного ST-LINK'a -(stdevs: указатель на список указателей, указывающих на структуры). -Вызываю stlink_probe_usb с параметрами: -- адрес stdevs'а (тройной указатель), -- connect, -- freq - -Функция stlink_probe_usb заполняет stdevs и возвращает его размер. -Для каждого указателя вызываю функцию stlink_print_info. - -Потом освобождаю память, отведённую под stdevs. - -stlink_print_info: просто печатаю в терминал информацию из переданной структуры -ST-LINK'а. - ---------------------------------------------------------------------------------- -Файл usb.c: - -stlink_probe_usb: -Инициализирую libusb -Получаю список USB-устройств (libusb_get_device_list). -Для полученного списка вызываю функцию stlink_probe_usb_devs. -Передаю ей: -- указатель на список указателей на структуры libusb_device (двойной указатель) devs -- адрес указателя на список указателей на структуры ST-LINK (тройной указатель) sldevs -- connect, freq. -Потом освобождаю память, занятую структурами libusb_device. -Список указателей на структуры ST-LINK возвращаю на выход (в функцию stlink_probe). - -stlink_probe_usb_devs: -Определяю количество подключенных ST-LINK'ов: -Прохожу по списку USB-устройств. -Для каждого USB-устройства получаю дескриптор desc. -Если в дескрипторе указаны idVendor и idProduct, соответствующие ST-LINK'у - увеличиваю счётчик. -Выделяю память под нужное количество структур ST-LINK'ов. - -Ещё раз прохожу по списку USB-устройств и получаю дескриптор каждого. -Если idProduct соответствует ST-LINK'у: -- открываю ST-LINK (libusb_open), -- читаю его серийник (stlink_serial); -- закрываю (libusb_close). - -Если длина серийника правильная - открываю его функцией stlink_open_usb. -Она возвращает ссылку на структуру stlink_t. Пристёгиваю эту ссылку к списку структур. -Перехожу к следюущему USB-устройству. Потом записываю ссылку на список структур stlink_t -в указатель и возвращаю количество структур по списку. - -stlink_serial: -Получаю дескриптор нулевой строки USB-устройства, беру из него LANGID (libusb_get_string_descriptor). -Получаю дескриптор строки серийника (для него нужен LANGID) (libusb_get_string_descriptor). -Если серийник длиной 50 символов - беру его же в формате ascii. -Если серийник длиной 26 символов - для каждого символа выполняю строку: -sprintf(serial + i, "%02X", desc_serial[i + 2]) -В конце ставлю ноль. -Возвращаю длину серийника и сам серийник, записанный в память по адресу из параметра. - -stlink_open_usb: -Выделяю в куче память под структуры sl (stlink_t) и slu (stlink_libusb). -Записываю в sl ссылку на список каких-то функций и ссылку на slu, указываю статус ядра -целевого MCU: TARGET_UNKNOWN. -Инициализирую libusb с контекстом, указываю LOG_LEVEL. -Получаю список USB-устройств. -Для каждого устройства получаю дескриптор и проверяю его idVendor. -Открываю устройство и пытаюсь получить серийник. -Если не получил серийник либо получил серийник, соответствующий заданному в параметре - -- выставляю в структуре sl версию и протокол по idProduct, после чего заканчиваю просмотр -устройств USB. - -Просмотрев все устройства, открываю найденный ST-LINK и освобождаю память, занятую -списком USB-устройств. - -Читаю конфигурацию ST-LINK'а, потом устанавливаю её. Делаю заявку на интерфейс (libusb_claim_interface). -Потом выставляю поля ep_rep, ep_req, ep_trace, sg_transfer_idx и cmd_len. -Инициализирую версию ST-LINK'а (stlink_version). -Получаю режим работы ST-LINK'а. Если он в режиме dfu - выхожу из него. -Если CONNECT_UNDER_RESET: выхожу из debug mode, если в нём. Выполняю JTAG reset. -Выставляю поле freq по параметру функции, устанавливаю SWD clock (_stlink_usb_set_swdclk). -Выполняю stlink_target_connect и возвращаю структуру sl. - -_stlink_usb_version: -Заполняю структуру stlink командой fill_command (по-разному для ST-LINK v. 3 и предыдущих версий) -Выполняю функцию send_recv - - -_stlink_usb_current_mode: -Заполняю структуру stlink командой fill_command, ставлю в i-тую позицию команду STLINK_GET_CURRENT_MODE -Вызываю функцию send_recv -Возвращаю первый символ буфера, или -1 при ошибке. - -_stlink_usb_exit_debug_mode, _stlink_usb_exit_debug_mode: -Заполняю структуру stlink командой fill_command, ставлю в i-тую позицию команды: -STLINK_DFU_COMMAND -STLINK_DFU_EXIT -Вызываю функцию send_only -Возвращаю 0, или -1 при ошибке. -То же самое для debug - -fill_command: -Для ST-LINK v. 1 заполняю поле c_buf структуры stlink. Для всех остальных заполняю его нулями. - -send_recv: -Отправляю функцией libusb_bulk_transfer данные в параметре txbuf и команду в cmd. -Проверяю ответ на ошибки и если указан rxsize - принимаю данные той же функцией. -Возвращаю количество принятого после проверки на ошибки. - ---------------------------------------------------------------------------------- -Файл common.c: - -stlink_version: -Запускаю функцию version из backend (вызывается _stlink_usb_version из usb.c) -Выполняю _parse_version. - -stlink_current_mode: -возвращаю результат выполнения функции sl->backend->current_mode(sl) после проверки на ошибки. -При этом запускается функция _stlink_usb_current_mode. \ No newline at end of file From d98d3a50edbbf984b1fe842908e1420d26c3ff0f Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sat, 29 Jan 2022 17:56:26 +0100 Subject: [PATCH 368/503] Minor formatting fixes & clean-up --- CMakeLists.txt | 6 +++--- src/calculate.h | 2 +- src/common.h | 2 +- src/common_flash.h | 2 +- src/map_file.h | 2 +- src/{option.c => option_bytes.c} | 0 6 files changed, 7 insertions(+), 7 deletions(-) rename src/{option.c => option_bytes.c} (100%) diff --git a/CMakeLists.txt b/CMakeLists.txt index a3338df71..abfc0be47 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -2,7 +2,7 @@ # General cmake settings ### -cmake_minimum_required(VERSION 3.7.2) +cmake_minimum_required(VERSION 3.10.2) cmake_policy(SET CMP0042 NEW) set(CMAKE_MODULE_PATH ${CMAKE_SOURCE_DIR}/cmake/modules) set(CMAKE_ARCHIVE_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}/lib) @@ -127,8 +127,8 @@ set(STLINK_HEADERS set(STLINK_SOURCE src/read_write.c src/common.c - src/option.c - src/common_flash.c + src/option_bytes.c + src/common_flash.c src/map_file.c src/flashloader.c src/calculate.c diff --git a/src/calculate.h b/src/calculate.h index 68c1fb988..64dfb51b2 100644 --- a/src/calculate.h +++ b/src/calculate.h @@ -1,7 +1,7 @@ /* * File: calculate.h * - * TODO: add a description + * Calculation of sector numbers and pages */ #ifndef CALCULATE_H diff --git a/src/common.h b/src/common.h index 6c22d58c0..dd6cf95b2 100644 --- a/src/common.h +++ b/src/common.h @@ -1,7 +1,7 @@ /* * File: common.h * - * TODO: add a description + * General helper functions */ #ifndef COMMON_H diff --git a/src/common_flash.h b/src/common_flash.h index 70a6f0e04..3b6b0404a 100644 --- a/src/common_flash.h +++ b/src/common_flash.h @@ -1,7 +1,7 @@ /* * File: common_flash.h * - * TODO: add a description + * Flash operations */ #ifndef COMMON_FLASH_H diff --git a/src/map_file.h b/src/map_file.h index b35f24ad0..08cf98b6c 100644 --- a/src/map_file.h +++ b/src/map_file.h @@ -1,7 +1,7 @@ /* * File: map_file.h * - * TODO: add a description + * File mapping */ #ifndef MAP_FILE_H diff --git a/src/option.c b/src/option_bytes.c similarity index 100% rename from src/option.c rename to src/option_bytes.c From e2dcf074d51aaf2ec2a77617475a8a5e8ffebd6f Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sat, 29 Jan 2022 19:33:19 +0100 Subject: [PATCH 369/503] Fixed defines (CHIPID + COREID) & duplicates --- inc/stm32.h | 374 --------------------------------------------- inc/stm32flash.h | 4 +- src/calculate.c | 6 +- src/common.c | 46 +++--- src/common_flash.c | 368 ++++++++++++++++++++++---------------------- src/flashloader.c | 104 ++++++------- src/option_bytes.c | 54 +++---- 7 files changed, 291 insertions(+), 665 deletions(-) diff --git a/inc/stm32.h b/inc/stm32.h index 08cd3cd2a..d764e2f97 100644 --- a/inc/stm32.h +++ b/inc/stm32.h @@ -155,340 +155,6 @@ enum stm32_chipids { #define STM32_F1_FLASH_BANK2_BASE ((uint32_t)0x08080000) #define STM32_H7_FLASH_BANK2_BASE ((uint32_t)0x08100000) -/* stm32f FPEC flash controller interface, pm0063 manual */ -// STM32F05x is identical, based on RM0091 (DM00031936, Doc ID 018940 Rev 2, August 2012) -#define FLASH_REGS_ADDR 0x40022000 -#define FLASH_REGS_SIZE 0x28 - -#define FLASH_ACR (FLASH_REGS_ADDR + 0x00) -#define FLASH_KEYR (FLASH_REGS_ADDR + 0x04) -#define FLASH_OPTKEYR (FLASH_REGS_ADDR + 0x08) -#define FLASH_SR (FLASH_REGS_ADDR + 0x0c) -#define FLASH_CR (FLASH_REGS_ADDR + 0x10) -#define FLASH_AR (FLASH_REGS_ADDR + 0x14) -#define FLASH_OBR (FLASH_REGS_ADDR + 0x1c) -#define FLASH_WRPR (FLASH_REGS_ADDR + 0x20) - -// STM32F10x_XL has two flash memory banks with separate registers to control -// the second bank. -#define FLASH_KEYR2 (FLASH_REGS_ADDR + 0x44) -#define FLASH_SR2 (FLASH_REGS_ADDR + 0x4c) -#define FLASH_CR2 (FLASH_REGS_ADDR + 0x50) -#define FLASH_AR2 (FLASH_REGS_ADDR + 0x54) - -// For STM32F05x, the RDPTR_KEY may be wrong, but as it is not used anywhere... -#define FLASH_RDPTR_KEY 0x00a5 -#define FLASH_KEY1 0x45670123 -#define FLASH_KEY2 0xcdef89ab - -#define FLASH_L0_PRGKEY1 0x8c9daebf -#define FLASH_L0_PRGKEY2 0x13141516 - -#define FLASH_L0_PEKEY1 0x89abcdef -#define FLASH_L0_PEKEY2 0x02030405 - -#define FLASH_OPTKEY1 0x08192A3B -#define FLASH_OPTKEY2 0x4C5D6E7F - -#define FLASH_F0_OPTKEY1 0x45670123 -#define FLASH_F0_OPTKEY2 0xCDEF89AB - -#define FLASH_L0_OPTKEY1 0xFBEAD9C8 -#define FLASH_L0_OPTKEY2 0x24252627 - -#define FLASH_SR_BSY 0 -#define FLASH_SR_PG_ERR 2 -#define FLASH_SR_WRPRT_ERR 4 -#define FLASH_SR_EOP 5 - -#define FLASH_SR_ERROR_MASK ((1 << FLASH_SR_PG_ERR) | (1 << FLASH_SR_WRPRT_ERR)) - -#define FLASH_CR_PG 0 -#define FLASH_CR_PER 1 -#define FLASH_CR_MER 2 -#define FLASH_CR_OPTPG 4 -#define FLASH_CR_OPTER 5 -#define FLASH_CR_STRT 6 -#define FLASH_CR_LOCK 7 -#define FLASH_CR_OPTWRE 9 -#define FLASH_CR_OBL_LAUNCH 13 - -#define STM32L_FLASH_REGS_ADDR ((uint32_t)0x40023c00) -#define STM32L_FLASH_ACR (STM32L_FLASH_REGS_ADDR + 0x00) -#define STM32L_FLASH_PECR (STM32L_FLASH_REGS_ADDR + 0x04) -#define STM32L_FLASH_PDKEYR (STM32L_FLASH_REGS_ADDR + 0x08) -#define STM32L_FLASH_PEKEYR (STM32L_FLASH_REGS_ADDR + 0x0c) -#define STM32L_FLASH_PRGKEYR (STM32L_FLASH_REGS_ADDR + 0x10) -#define STM32L_FLASH_OPTKEYR (STM32L_FLASH_REGS_ADDR + 0x14) -#define STM32L_FLASH_SR (STM32L_FLASH_REGS_ADDR + 0x18) -#define STM32L_FLASH_OBR (STM32L_FLASH_REGS_ADDR + 0x1c) -#define STM32L_FLASH_WRPR (STM32L_FLASH_REGS_ADDR + 0x20) -#define FLASH_L1_FPRG 10 -#define FLASH_L1_PROG 3 - -// Flash registers common to STM32G0 and STM32G4 series. -#define STM32Gx_FLASH_REGS_ADDR ((uint32_t)0x40022000) -#define STM32Gx_FLASH_ACR (STM32Gx_FLASH_REGS_ADDR + 0x00) -#define STM32Gx_FLASH_KEYR (STM32Gx_FLASH_REGS_ADDR + 0x08) -#define STM32Gx_FLASH_OPTKEYR (STM32Gx_FLASH_REGS_ADDR + 0x0c) -#define STM32Gx_FLASH_SR (STM32Gx_FLASH_REGS_ADDR + 0x10) -#define STM32Gx_FLASH_CR (STM32Gx_FLASH_REGS_ADDR + 0x14) -#define STM32Gx_FLASH_ECCR (STM32Gx_FLASH_REGS_ADDR + 0x18) -#define STM32Gx_FLASH_OPTR (STM32Gx_FLASH_REGS_ADDR + 0x20) - -// G0 (RM0444 Table 1, sec 3.7) -// Mostly the same as G4 chips, but the notation -// varies a bit after the 'OPTR' register. -#define STM32G0_FLASH_REGS_ADDR (STM32Gx_FLASH_REGS_ADDR) -#define STM32G0_FLASH_PCROP1ASR (STM32G0_FLASH_REGS_ADDR + 0x24) -#define STM32G0_FLASH_PCROP1AER (STM32G0_FLASH_REGS_ADDR + 0x28) -#define STM32G0_FLASH_WRP1AR (STM32G0_FLASH_REGS_ADDR + 0x2C) -#define STM32G0_FLASH_WRP1BR (STM32G0_FLASH_REGS_ADDR + 0x30) -#define STM32G0_FLASH_PCROP1BSR (STM32G0_FLASH_REGS_ADDR + 0x34) -#define STM32G0_FLASH_PCROP1BER (STM32G0_FLASH_REGS_ADDR + 0x38) -#define STM32G0_FLASH_SECR (STM32G0_FLASH_REGS_ADDR + 0x80) - -// G4 (RM0440 Table 17, sec 3.7.19) -// Mostly the same as STM32G0 chips, but there are a few extra -// registers because 'cat 3' devices can have two Flash banks. -#define STM32G4_FLASH_REGS_ADDR (STM32Gx_FLASH_REGS_ADDR) -#define STM32G4_FLASH_PDKEYR (STM32G4_FLASH_REGS_ADDR + 0x04) -#define STM32G4_FLASH_PCROP1SR (STM32G4_FLASH_REGS_ADDR + 0x24) -#define STM32G4_FLASH_PCROP1ER (STM32G4_FLASH_REGS_ADDR + 0x28) -#define STM32G4_FLASH_WRP1AR (STM32G4_FLASH_REGS_ADDR + 0x2C) -#define STM32G4_FLASH_WRP1BR (STM32G4_FLASH_REGS_ADDR + 0x30) -#define STM32G4_FLASH_PCROP2SR (STM32G4_FLASH_REGS_ADDR + 0x44) -#define STM32G4_FLASH_PCROP2ER (STM32G4_FLASH_REGS_ADDR + 0x48) -#define STM32G4_FLASH_WRP2AR (STM32G4_FLASH_REGS_ADDR + 0x4C) -#define STM32G4_FLASH_WRP2BR (STM32G4_FLASH_REGS_ADDR + 0x50) -#define STM32G4_FLASH_SEC1R (STM32G4_FLASH_REGS_ADDR + 0x70) -#define STM32G4_FLASH_SEC2R (STM32G4_FLASH_REGS_ADDR + 0x74) - -// G0/G4 FLASH control register -#define STM32Gx_FLASH_CR_PG (0) /* Program */ -#define STM32Gx_FLASH_CR_PER (1) /* Page erase */ -#define STM32Gx_FLASH_CR_MER1 (2) /* Mass erase */ -#define STM32Gx_FLASH_CR_PNB (3) /* Page number */ -#define STM32G0_FLASH_CR_PNG_LEN (5) /* STM32G0: 5 page number bits */ -#define STM32G4_FLASH_CR_PNG_LEN (7) /* STM32G4: 7 page number bits */ -#define STM32Gx_FLASH_CR_MER2 (15) /* Mass erase (2nd bank)*/ -#define STM32Gx_FLASH_CR_STRT (16) /* Start */ -#define STM32Gx_FLASH_CR_OPTSTRT \ - (17) /* Start of modification of option bytes */ -#define STM32Gx_FLASH_CR_FSTPG (18) /* Fast programming */ -#define STM32Gx_FLASH_CR_EOPIE (24) /* End of operation interrupt enable */ -#define STM32Gx_FLASH_CR_ERRIE (25) /* Error interrupt enable */ -#define STM32Gx_FLASH_CR_OBL_LAUNCH (27) /* Forces the option byte loading */ -#define STM32Gx_FLASH_CR_OPTLOCK (30) /* Options Lock */ -#define STM32Gx_FLASH_CR_LOCK (31) /* FLASH_CR Lock */ - -// G0/G4 FLASH status register -#define STM32Gx_FLASH_SR_ERROR_MASK (0x3fa) -#define STM32Gx_FLASH_SR_PROGERR (3) -#define STM32Gx_FLASH_SR_WRPERR (4) -#define STM32Gx_FLASH_SR_PGAERR (5) -#define STM32Gx_FLASH_SR_BSY (16) /* FLASH_SR Busy */ -#define STM32Gx_FLASH_SR_EOP (0) /* FLASH_EOP End of Operation */ - -// G4 FLASH option register -#define STM32G4_FLASH_OPTR_DBANK (22) /* FLASH_OPTR Dual Bank Mode */ - -// WB (RM0434) -#define STM32WB_FLASH_REGS_ADDR ((uint32_t)0x58004000) -#define STM32WB_FLASH_ACR (STM32WB_FLASH_REGS_ADDR + 0x00) -#define STM32WB_FLASH_KEYR (STM32WB_FLASH_REGS_ADDR + 0x08) -#define STM32WB_FLASH_OPT_KEYR (STM32WB_FLASH_REGS_ADDR + 0x0C) -#define STM32WB_FLASH_SR (STM32WB_FLASH_REGS_ADDR + 0x10) -#define STM32WB_FLASH_CR (STM32WB_FLASH_REGS_ADDR + 0x14) -#define STM32WB_FLASH_ECCR (STM32WB_FLASH_REGS_ADDR + 0x18) -#define STM32WB_FLASH_OPTR (STM32WB_FLASH_REGS_ADDR + 0x20) -#define STM32WB_FLASH_PCROP1ASR (STM32WB_FLASH_REGS_ADDR + 0x24) -#define STM32WB_FLASH_PCROP1AER (STM32WB_FLASH_REGS_ADDR + 0x28) -#define STM32WB_FLASH_WRP1AR (STM32WB_FLASH_REGS_ADDR + 0x2C) -#define STM32WB_FLASH_WRP1BR (STM32WB_FLASH_REGS_ADDR + 0x30) -#define STM32WB_FLASH_PCROP1BSR (STM32WB_FLASH_REGS_ADDR + 0x34) -#define STM32WB_FLASH_PCROP1BER (STM32WB_FLASH_REGS_ADDR + 0x38) -#define STM32WB_FLASH_IPCCBR (STM32WB_FLASH_REGS_ADDR + 0x3C) -#define STM32WB_FLASH_C2ACR (STM32WB_FLASH_REGS_ADDR + 0x5C) -#define STM32WB_FLASH_C2SR (STM32WB_FLASH_REGS_ADDR + 0x60) -#define STM32WB_FLASH_C2CR (STM32WB_FLASH_REGS_ADDR + 0x64) -#define STM32WB_FLASH_SFR (STM32WB_FLASH_REGS_ADDR + 0x80) -#define STM32WB_FLASH_SRRVR (STM32WB_FLASH_REGS_ADDR + 0x84) - -// WB Flash control register. -#define STM32WB_FLASH_CR_STRT (16) /* Start */ -#define STM32WB_FLASH_CR_OPTLOCK (30) /* Option Lock */ -#define STM32WB_FLASH_CR_LOCK (31) /* Lock */ -// WB Flash status register. -#define STM32WB_FLASH_SR_ERROR_MASK (0x3f8) /* SR [9:3] */ -#define STM32WB_FLASH_SR_PROGERR (3) /* Programming alignment error */ -#define STM32WB_FLASH_SR_WRPERR (4) /* Write protection error */ -#define STM32WB_FLASH_SR_PGAERR (5) /* Programming error */ -#define STM32WB_FLASH_SR_BSY (16) /* Busy */ - -// 32L4 register base is at FLASH_REGS_ADDR (0x40022000) -#define STM32L4_FLASH_KEYR (FLASH_REGS_ADDR + 0x08) -#define STM32L4_FLASH_OPTKEYR (FLASH_REGS_ADDR + 0x0C) -#define STM32L4_FLASH_SR (FLASH_REGS_ADDR + 0x10) -#define STM32L4_FLASH_CR (FLASH_REGS_ADDR + 0x14) -#define STM32L4_FLASH_OPTR (FLASH_REGS_ADDR + 0x20) - -#define STM32L4_FLASH_SR_ERROR_MASK 0x3f8 /* SR [9:3] */ -#define STM32L4_FLASH_SR_PROGERR 3 -#define STM32L4_FLASH_SR_WRPERR 4 -#define STM32L4_FLASH_SR_PGAERR 5 -#define STM32L4_FLASH_SR_BSY 16 - -#define STM32L4_FLASH_CR_LOCK 31 /* Lock control register */ -#define STM32L4_FLASH_CR_OPTLOCK 30 /* Lock option bytes */ -#define STM32L4_FLASH_CR_PG 0 /* Program */ -#define STM32L4_FLASH_CR_PER 1 /* Page erase */ -#define STM32L4_FLASH_CR_MER1 2 /* Bank 1 erase */ -#define STM32L4_FLASH_CR_MER2 15 /* Bank 2 erase */ -#define STM32L4_FLASH_CR_STRT 16 /* Start command */ -#define STM32L4_FLASH_CR_OPTSTRT 17 /* Start writing option bytes */ -#define STM32L4_FLASH_CR_BKER 11 /* Bank select for page erase */ -#define STM32L4_FLASH_CR_PNB 3 /* Page number (8 bits) */ -#define STM32L4_FLASH_CR_OBL_LAUNCH 27 /* Option bytes reload */ -// Bits requesting flash operations (useful when we want to clear them) -#define STM32L4_FLASH_CR_OPBITS \ - (uint32_t)((1lu << STM32L4_FLASH_CR_PG) | (1lu << STM32L4_FLASH_CR_PER) | \ - (1lu << STM32L4_FLASH_CR_MER1) | (1lu << STM32L4_FLASH_CR_MER1)) -// Page is fully specified by BKER and PNB -#define STM32L4_FLASH_CR_PAGEMASK (uint32_t)(0x1fflu << STM32L4_FLASH_CR_PNB) - -#define STM32L4_FLASH_OPTR_DUALBANK 21 - -// STM32L0x flash register base and offsets RM0090 - DM00031020.pdf -#define STM32L0_FLASH_REGS_ADDR ((uint32_t)0x40022000) - -#define STM32L0_FLASH_PELOCK (0) -#define STM32L0_FLASH_OPTLOCK (2) -#define STM32L0_FLASH_OBL_LAUNCH (18) - -#define STM32L0_FLASH_SR_ERROR_MASK 0x00013F00 -#define STM32L0_FLASH_SR_WRPERR 8 -#define STM32L0_FLASH_SR_PGAERR 9 -#define STM32L0_FLASH_SR_NOTZEROERR 16 - -#define FLASH_ACR_OFF ((uint32_t)0x00) -#define FLASH_PECR_OFF ((uint32_t)0x04) -#define FLASH_PDKEYR_OFF ((uint32_t)0x08) -#define FLASH_PEKEYR_OFF ((uint32_t)0x0c) -#define FLASH_PRGKEYR_OFF ((uint32_t)0x10) -#define FLASH_OPTKEYR_OFF ((uint32_t)0x14) -#define FLASH_SR_OFF ((uint32_t)0x18) -#define FLASH_OBR_OFF ((uint32_t)0x1c) -#define FLASH_WRPR_OFF ((uint32_t)0x20) - -// STM32F7 -#define FLASH_F7_REGS_ADDR ((uint32_t)0x40023c00) -#define FLASH_F7_KEYR (FLASH_F7_REGS_ADDR + 0x04) -#define FLASH_F7_OPT_KEYR (FLASH_F7_REGS_ADDR + 0x08) -#define FLASH_F7_SR (FLASH_F7_REGS_ADDR + 0x0c) -#define FLASH_F7_CR (FLASH_F7_REGS_ADDR + 0x10) -#define FLASH_F7_OPTCR (FLASH_F7_REGS_ADDR + 0x14) -#define FLASH_F7_OPTCR1 (FLASH_F7_REGS_ADDR + 0x18) -#define FLASH_F7_OPTCR_LOCK 0 -#define FLASH_F7_OPTCR_START 1 -#define FLASH_F7_CR_STRT 16 -#define FLASH_F7_CR_LOCK 31 -#define FLASH_F7_CR_SER 1 -#define FLASH_F7_CR_SNB 3 -#define FLASH_F7_CR_SNB_MASK 0xf8 -#define FLASH_F7_SR_BSY 16 -#define FLASH_F7_SR_ERS_ERR 7 /* Erase Sequence Error */ -#define FLASH_F7_SR_PGP_ERR 6 /* Programming parallelism error */ -#define FLASH_F7_SR_PGA_ERR 5 /* Programming alignment error */ -#define FLASH_F7_SR_WRP_ERR 4 /* Write protection error */ -#define FLASH_F7_SR_OP_ERR 1 /* Operation error */ -#define FLASH_F7_SR_EOP 0 /* End of operation */ -#define FLASH_F7_OPTCR1_BOOT_ADD0 0 -#define FLASH_F7_OPTCR1_BOOT_ADD1 16 - -#define FLASH_F7_SR_ERROR_MASK \ - ((1 << FLASH_F7_SR_ERS_ERR) | (1 << FLASH_F7_SR_PGP_ERR) | \ - (1 << FLASH_F7_SR_PGA_ERR) | (1 << FLASH_F7_SR_WRP_ERR) | \ - (1 << FLASH_F7_SR_OP_ERR)) - -// STM32F4 -#define FLASH_F4_REGS_ADDR ((uint32_t)0x40023c00) -#define FLASH_F4_KEYR (FLASH_F4_REGS_ADDR + 0x04) -#define FLASH_F4_OPT_KEYR (FLASH_F4_REGS_ADDR + 0x08) -#define FLASH_F4_SR (FLASH_F4_REGS_ADDR + 0x0c) -#define FLASH_F4_CR (FLASH_F4_REGS_ADDR + 0x10) -#define FLASH_F4_OPTCR (FLASH_F4_REGS_ADDR + 0x14) -#define FLASH_F4_OPTCR_LOCK 0 -#define FLASH_F4_OPTCR_START 1 -#define FLASH_F4_CR_STRT 16 -#define FLASH_F4_CR_LOCK 31 -#define FLASH_F4_CR_SER 1 -#define FLASH_F4_CR_SNB 3 -#define FLASH_F4_CR_SNB_MASK 0xf8 -#define FLASH_F4_SR_ERROR_MASK 0x000000F0 -#define FLASH_F4_SR_PGAERR 5 -#define FLASH_F4_SR_WRPERR 4 -#define FLASH_F4_SR_BSY 16 - -// STM32F2 -#define FLASH_F2_REGS_ADDR ((uint32_t)0x40023c00) -#define FLASH_F2_KEYR (FLASH_F2_REGS_ADDR + 0x04) -#define FLASH_F2_OPT_KEYR (FLASH_F2_REGS_ADDR + 0x08) -#define FLASH_F2_SR (FLASH_F2_REGS_ADDR + 0x0c) -#define FLASH_F2_CR (FLASH_F2_REGS_ADDR + 0x10) -#define FLASH_F2_OPT_CR (FLASH_F2_REGS_ADDR + 0x14) -#define FLASH_F2_OPT_LOCK_BIT (1u << 0) -#define FLASH_F2_CR_STRT 16 -#define FLASH_F2_CR_LOCK 31 - -#define FLASH_F2_CR_SER 1 -#define FLASH_F2_CR_SNB 3 -#define FLASH_F2_CR_SNB_MASK 0x78 -#define FLASH_F2_SR_BSY 16 - -// STM32H7xx -#define FLASH_H7_CR_LOCK 0 -#define FLASH_H7_CR_PG 1 -#define FLASH_H7_CR_SER 2 -#define FLASH_H7_CR_BER 3 -#define FLASH_H7_CR_PSIZE 4 -#define FLASH_H7_CR_START(chipid) (chipid == STM32_CHIPID_H7Ax ? 5 : 7) -#define FLASH_H7_CR_SNB 8 -#define FLASH_H7_CR_SNB_MASK 0x700 - -#define FLASH_H7_SR_QW 2 -#define FLASH_H7_SR_WRPERR 17 -#define FLASH_H7_SR_PGSERR 18 -#define FLASH_H7_SR_STRBERR 19 -#define FLASH_H7_SR_ERROR_MASK \ - ((1 << FLASH_H7_SR_PGSERR) | (1 << FLASH_H7_SR_STRBERR) | \ - (1 << FLASH_H7_SR_WRPERR)) - -#define FLASH_H7_OPTCR_OPTLOCK 0 -#define FLASH_H7_OPTCR_OPTSTART 1 -#define FLASH_H7_OPTCR_MER 4 - -#define FLASH_H7_OPTSR_OPT_BUSY 0 -#define FLASH_H7_OPTSR_OPTCHANGEERR 30 - -#define FLASH_H7_OPTCCR_CLR_OPTCHANGEERR 30 - -#define FLASH_H7_REGS_ADDR ((uint32_t)0x52002000) -#define FLASH_H7_KEYR1 (FLASH_H7_REGS_ADDR + 0x04) -#define FLASH_H7_KEYR2 (FLASH_H7_REGS_ADDR + 0x104) -#define FLASH_H7_OPT_KEYR (FLASH_H7_REGS_ADDR + 0x08) -#define FLASH_H7_OPT_KEYR2 (FLASH_H7_REGS_ADDR + 0x108) -#define FLASH_H7_CR1 (FLASH_H7_REGS_ADDR + 0x0c) -#define FLASH_H7_CR2 (FLASH_H7_REGS_ADDR + 0x10c) -#define FLASH_H7_SR1 (FLASH_H7_REGS_ADDR + 0x10) -#define FLASH_H7_SR2 (FLASH_H7_REGS_ADDR + 0x110) -#define FLASH_H7_CCR1 (FLASH_H7_REGS_ADDR + 0x14) -#define FLASH_H7_CCR2 (FLASH_H7_REGS_ADDR + 0x114) -#define FLASH_H7_OPTCR (FLASH_H7_REGS_ADDR + 0x18) -#define FLASH_H7_OPTCR2 (FLASH_H7_REGS_ADDR + 0x118) -#define FLASH_H7_OPTSR_CUR (FLASH_H7_REGS_ADDR + 0x1c) -#define FLASH_H7_OPTCCR (FLASH_H7_REGS_ADDR + 0x24) - #define STM32F0_DBGMCU_CR 0xE0042004 #define STM32F0_DBGMCU_CR_IWDG_STOP 8 #define STM32F0_DBGMCU_CR_WWDG_STOP 9 @@ -532,44 +198,4 @@ enum stm32_chipids { #define L1_WRITE_BLOCK_SIZE 0x80 #define L0_WRITE_BLOCK_SIZE 0x40 -#define STM32F0_DBGMCU_CR 0xE0042004 -#define STM32F0_DBGMCU_CR_IWDG_STOP 8 -#define STM32F0_DBGMCU_CR_WWDG_STOP 9 - -#define STM32F4_DBGMCU_APB1FZR1 0xE0042008 -#define STM32F4_DBGMCU_APB1FZR1_WWDG_STOP 11 -#define STM32F4_DBGMCU_APB1FZR1_IWDG_STOP 12 - -#define STM32L0_DBGMCU_APB1_FZ 0x40015808 -#define STM32L0_DBGMCU_APB1_FZ_WWDG_STOP 11 -#define STM32L0_DBGMCU_APB1_FZ_IWDG_STOP 12 - -#define STM32H7_DBGMCU_APB1HFZ 0x5C001054 -#define STM32H7_DBGMCU_APB1HFZ_IWDG_STOP 18 - -#define STM32WB_DBGMCU_APB1FZR1 0xE004203C -#define STM32WB_DBGMCU_APB1FZR1_WWDG_STOP 11 -#define STM32WB_DBGMCU_APB1FZR1_IWDG_STOP 12 - -#define STM32F1_RCC_AHBENR 0x40021014 -#define STM32F1_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN - -#define STM32F4_RCC_AHB1ENR 0x40023830 -#define STM32F4_RCC_DMAEN 0x00600000 // DMA2EN | DMA1EN - -#define STM32G0_RCC_AHBENR 0x40021038 -#define STM32G0_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN - -#define STM32G4_RCC_AHB1ENR 0x40021048 -#define STM32G4_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN - -#define STM32L0_RCC_AHBENR 0x40021030 -#define STM32L0_RCC_DMAEN 0x00000001 // DMAEN - -#define STM32H7_RCC_AHB1ENR 0x58024538 -#define STM32H7_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN - -#define STM32WB_RCC_AHB1ENR 0x58000048 -#define STM32WB_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN - #endif // STM32_H diff --git a/inc/stm32flash.h b/inc/stm32flash.h index 01c76946c..73d1bbc21 100644 --- a/inc/stm32flash.h +++ b/inc/stm32flash.h @@ -300,7 +300,7 @@ #define FLASH_H7_CR_SER 2 #define FLASH_H7_CR_BER 3 #define FLASH_H7_CR_PSIZE 4 -#define FLASH_H7_CR_START(chipid) (chipid == STLINK_CHIPID_STM32_H7Ax ? 5 : 7) +#define FLASH_H7_CR_START(chipid) (chipid == STM32_CHIPID_H7Ax ? 5 : 7) #define FLASH_H7_CR_SNB 8 #define FLASH_H7_CR_SNB_MASK 0x700 @@ -337,4 +337,4 @@ #define FLASH_H7_OPTSR_CUR (FLASH_H7_REGS_ADDR + 0x1c) #define FLASH_H7_OPTCCR (FLASH_H7_REGS_ADDR + 0x24) -#endif // STM32FLASH_H \ No newline at end of file +#endif // STM32FLASH_H diff --git a/src/calculate.c b/src/calculate.c index 22f6e3a5b..ed3b65873 100644 --- a/src/calculate.c +++ b/src/calculate.c @@ -54,9 +54,9 @@ uint32_t calculate_L4_page(stlink_t *sl, uint32_t flashaddr) { stlink_read_debug32(sl, STM32L4_FLASH_OPTR, &flashopt); flashaddr -= STM32_FLASH_BASE; - if (sl->chip_id == STLINK_CHIPID_STM32_L4 || - sl->chip_id == STLINK_CHIPID_STM32_L496x_L4A6x || - sl->chip_id == STLINK_CHIPID_STM32_L4Rx) { + if (sl->chip_id == STM32_CHIPID_L4 || + sl->chip_id == STM32_CHIPID_L496x_L4A6x || + sl->chip_id == STM32_CHIPID_L4Rx) { // this chip use dual banked flash if (flashopt & (uint32_t)(1lu << STM32L4_FLASH_OPTR_DUALBANK)) { uint32_t banksize = (uint32_t)sl->flash_size / 2; diff --git a/src/common.c b/src/common.c index 7b4f1e14b..4e5052522 100644 --- a/src/common.c +++ b/src/common.c @@ -134,7 +134,7 @@ int stlink_chip_id(stlink_t *sl, uint32_t *chip_id) { * */ - if ((sl->core_id == STM32H7_CORE_ID || sl->core_id == STM32H7_CORE_ID_JTAG) && + if ((sl->core_id == STM32_CORE_ID_M7F_H7_SWD || sl->core_id == STM32_CORE_ID_M7F_H7_JTAG) && cpu_id.part == STLINK_REG_CMx_CPUID_PARTNO_CM7) { // STM32H7 chipid in 0x5c001000 (RM0433 pg3189) ret = stlink_read_debug32(sl, 0x5c001000, chip_id); @@ -242,14 +242,14 @@ int stlink_load_device_params(stlink_t *sl) { flash_size = flash_size & 0xffff; - if ((sl->chip_id == STLINK_CHIPID_STM32_L1_MD || - sl->chip_id == STLINK_CHIPID_STM32_F1_VL_MD_LD || - sl->chip_id == STLINK_CHIPID_STM32_L1_MD_PLUS) && + if ((sl->chip_id == STM32_CHIPID_L1_MD || + sl->chip_id == STM32_CHIPID_F1_VL_MD_LD || + sl->chip_id == STM32_CHIPID_L1_MD_PLUS) && (flash_size == 0)) { sl->flash_size = 128 * 1024; - } else if (sl->chip_id == STLINK_CHIPID_STM32_L1_CAT2) { + } else if (sl->chip_id == STM32_CHIPID_L1_CAT2) { sl->flash_size = (flash_size & 0xff) * 1024; - } else if ((sl->chip_id & 0xFFF) == STLINK_CHIPID_STM32_L1_MD_PLUS_HD) { + } else if ((sl->chip_id & 0xFFF) == STM32_CHIPID_L1_MD_PLUS_HD) { // 0 is 384k and 1 is 256k if (flash_size == 0) { sl->flash_size = 384 * 1024; @@ -271,12 +271,12 @@ int stlink_load_device_params(stlink_t *sl) { // medium and low devices have the same chipid. ram size depends on flash // size. STM32F100xx datasheet Doc ID 16455 Table 2 - if (sl->chip_id == STLINK_CHIPID_STM32_F1_VL_MD_LD && + if (sl->chip_id == STM32_CHIPID_F1_VL_MD_LD && sl->flash_size < 64 * 1024) { sl->sram_size = 0x1000; } - if (sl->chip_id == STLINK_CHIPID_STM32_G4_CAT3) { + if (sl->chip_id == STM32_CHIPID_G4_CAT3) { uint32_t flash_optr; stlink_read_debug32(sl, STM32Gx_FLASH_OPTR, &flash_optr); @@ -293,7 +293,7 @@ int stlink_load_device_params(stlink_t *sl) { } ILOG("%s: %u KiB SRAM, %u KiB flash in at least %u %s pages.\n", - params->description, (unsigned)(sl->sram_size / 1024), + params->dev_type, (unsigned)(sl->sram_size / 1024), (unsigned)(sl->flash_size / 1024), (sl->flash_pgsz < 1024) ? (unsigned)(sl->flash_pgsz) : (unsigned)(sl->flash_pgsz / 1024), @@ -712,16 +712,16 @@ int write_buffer_to_sram(stlink_t *sl, flash_loader_t *fl, const uint8_t *buf, } // 291 uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr) { - if ((sl->chip_id == STLINK_CHIPID_STM32_F2) || - (sl->chip_id == STLINK_CHIPID_STM32_F4) || - (sl->chip_id == STLINK_CHIPID_STM32_F4_DE) || - (sl->chip_id == STLINK_CHIPID_STM32_F4_LP) || - (sl->chip_id == STLINK_CHIPID_STM32_F4_HD) || - (sl->chip_id == STLINK_CHIPID_STM32_F411xx) || - (sl->chip_id == STLINK_CHIPID_STM32_F446) || - (sl->chip_id == STLINK_CHIPID_STM32_F4_DSI) || - (sl->chip_id == STLINK_CHIPID_STM32_F72xxx) || - (sl->chip_id == STLINK_CHIPID_STM32_F412)) { + if ((sl->chip_id == STM32_CHIPID_F2) || + (sl->chip_id == STM32_CHIPID_F4) || + (sl->chip_id == STM32_CHIPID_F4_DE) || + (sl->chip_id == STM32_CHIPID_F4_LP) || + (sl->chip_id == STM32_CHIPID_F4_HD) || + (sl->chip_id == STM32_CHIPID_F411xx) || + (sl->chip_id == STM32_CHIPID_F446) || + (sl->chip_id == STM32_CHIPID_F4_DSI) || + (sl->chip_id == STM32_CHIPID_F72xxx) || + (sl->chip_id == STM32_CHIPID_F412)) { uint32_t sector = calculate_F4_sectornum(flashaddr); if (sector >= 12) { @@ -735,8 +735,8 @@ uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr) { } else { sl->flash_pgsz = 0x20000; } - } else if (sl->chip_id == STLINK_CHIPID_STM32_F7 || - sl->chip_id == STLINK_CHIPID_STM32_F76xxx) { + } else if (sl->chip_id == STM32_CHIPID_F7 || + sl->chip_id == STM32_CHIPID_F76xxx) { uint32_t sector = calculate_F7_sectornum(flashaddr); if (sector < 4) { @@ -984,7 +984,7 @@ static void stop_wdg_in_debug(stlink_t *sl) { break; case STM32_FLASH_TYPE_F2_F4: case STM32_FLASH_TYPE_F7: - case STM32_FLASH_TYPE_L4: + case STM32_FLASH_TYPE_L4_L4P: dbgmcu_cr = STM32F4_DBGMCU_APB1FZR1; set = (1 << STM32F4_DBGMCU_APB1FZR1_IWDG_STOP) | (1 << STM32F4_DBGMCU_APB1FZR1_WWDG_STOP); @@ -999,7 +999,7 @@ static void stop_wdg_in_debug(stlink_t *sl) { dbgmcu_cr = STM32H7_DBGMCU_APB1HFZ; set = (1 << STM32H7_DBGMCU_APB1HFZ_IWDG_STOP); break; - case STM32_FLASH_TYPE_WB: + case STM32_FLASH_TYPE_WB_WL: dbgmcu_cr = STM32WB_DBGMCU_APB1FZR1; set = (1 << STM32WB_DBGMCU_APB1FZR1_IWDG_STOP) | (1 << STM32WB_DBGMCU_APB1FZR1_WWDG_STOP); diff --git a/src/common_flash.c b/src/common_flash.c index 1f438c74f..e2a9ebbc3 100644 --- a/src/common_flash.c +++ b/src/common_flash.c @@ -11,16 +11,16 @@ uint32_t get_stm32l0_flash_base(stlink_t *sl) { switch (sl->chip_id) { - case STLINK_CHIPID_STM32_L0: - case STLINK_CHIPID_STM32_L0_CAT5: - case STLINK_CHIPID_STM32_L0_CAT2: - case STLINK_CHIPID_STM32_L011: + case STM32_CHIPID_L0: + case STM32_CHIPID_L0_CAT5: + case STM32_CHIPID_L0_CAT2: + case STM32_CHIPID_L011: return (STM32L0_FLASH_REGS_ADDR); - case STLINK_CHIPID_STM32_L1_CAT2: - case STLINK_CHIPID_STM32_L1_MD: - case STLINK_CHIPID_STM32_L1_MD_PLUS: - case STLINK_CHIPID_STM32_L1_MD_PLUS_HD: + case STM32_CHIPID_L1_CAT2: + case STM32_CHIPID_L1_MD: + case STM32_CHIPID_L1_MD_PLUS: + case STM32_CHIPID_L1_MD_PLUS_HD: return (STM32L_FLASH_REGS_ADDR); default: @@ -32,18 +32,18 @@ uint32_t get_stm32l0_flash_base(stlink_t *sl) { uint32_t read_flash_cr(stlink_t *sl, unsigned bank) { uint32_t reg, res; - if (sl->flash_type == STLINK_FLASH_TYPE_F4) { + if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { reg = FLASH_F4_CR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { + } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { reg = FLASH_F7_CR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { reg = STM32L4_FLASH_CR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4) { reg = STM32Gx_FLASH_CR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { reg = STM32WB_FLASH_CR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; } else { reg = (bank == BANK_1) ? FLASH_CR : FLASH_CR2; @@ -61,33 +61,33 @@ void lock_flash(stlink_t *sl) { uint32_t cr_lock_shift, cr_reg, n, cr2_reg = 0; uint32_t cr_mask = 0xffffffffu; - if (sl->flash_type == STLINK_FLASH_TYPE_F0) { + if (sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) { cr_reg = FLASH_CR; cr_lock_shift = FLASH_CR_LOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL) { + } else if (sl->flash_type == STM32_FLASH_TYPE_F1_XL) { cr_reg = FLASH_CR; cr2_reg = FLASH_CR2; cr_lock_shift = FLASH_CR_LOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { cr_reg = FLASH_F4_CR; cr_lock_shift = FLASH_F4_CR_LOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { + } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { cr_reg = FLASH_F7_CR; cr_lock_shift = FLASH_F7_CR_LOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { cr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF; cr_lock_shift = STM32L0_FLASH_PELOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { cr_reg = STM32L4_FLASH_CR; cr_lock_shift = STM32L4_FLASH_CR_LOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4) { cr_reg = STM32Gx_FLASH_CR; cr_lock_shift = STM32Gx_FLASH_CR_LOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { cr_reg = STM32WB_FLASH_CR; cr_lock_shift = STM32WB_FLASH_CR_LOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { cr_reg = FLASH_H7_CR1; if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { cr2_reg = FLASH_H7_CR2; @@ -113,23 +113,23 @@ void lock_flash(stlink_t *sl) { static inline int write_flash_sr(stlink_t *sl, unsigned bank, uint32_t val) { uint32_t sr_reg; - if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || - (sl->flash_type == STLINK_FLASH_TYPE_F1_XL)) { + if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || + (sl->flash_type == STM32_FLASH_TYPE_F1_XL)) { sr_reg = (bank == BANK_1) ? FLASH_SR : FLASH_SR2; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { sr_reg = get_stm32l0_flash_base(sl) + FLASH_SR_OFF; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { sr_reg = FLASH_F4_SR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { + } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { sr_reg = FLASH_F7_SR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { sr_reg = STM32L4_FLASH_SR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4) { sr_reg = STM32Gx_FLASH_SR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { sr_reg = STM32WB_FLASH_SR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { sr_reg = (bank == BANK_1) ? FLASH_H7_SR1 : FLASH_H7_SR2; } else { ELOG("method 'write_flash_sr' is unsupported\n"); @@ -141,32 +141,32 @@ static inline int write_flash_sr(stlink_t *sl, unsigned bank, uint32_t val) { void clear_flash_error(stlink_t *sl) { switch (sl->flash_type) { - case STLINK_FLASH_TYPE_F0: + case STM32_FLASH_TYPE_F0_F1_F3: write_flash_sr(sl, BANK_1, FLASH_SR_ERROR_MASK); break; - case STLINK_FLASH_TYPE_F4: + case STM32_FLASH_TYPE_F2_F4: write_flash_sr(sl, BANK_1, FLASH_F4_SR_ERROR_MASK); break; - case STLINK_FLASH_TYPE_F7: + case STM32_FLASH_TYPE_F7: write_flash_sr(sl, BANK_1, FLASH_F7_SR_ERROR_MASK); break; - case STLINK_FLASH_TYPE_G0: - case STLINK_FLASH_TYPE_G4: + case STM32_FLASH_TYPE_G0: + case STM32_FLASH_TYPE_G4: write_flash_sr(sl, BANK_1, STM32Gx_FLASH_SR_ERROR_MASK); break; - case STLINK_FLASH_TYPE_L0: + case STM32_FLASH_TYPE_L0_L1: write_flash_sr(sl, BANK_1, STM32L0_FLASH_SR_ERROR_MASK); break; - case STLINK_FLASH_TYPE_L4: + case STM32_FLASH_TYPE_L4_L4P: write_flash_sr(sl, BANK_1, STM32L4_FLASH_SR_ERROR_MASK); break; - case STLINK_FLASH_TYPE_H7: + case STM32_FLASH_TYPE_H7: write_flash_sr(sl, BANK_1, FLASH_H7_SR_ERROR_MASK); if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { write_flash_sr(sl, BANK_2, FLASH_H7_SR_ERROR_MASK); } break; - case STLINK_FLASH_TYPE_WB: + case STM32_FLASH_TYPE_WB_WL: write_flash_sr(sl, BANK_1, STM32WB_FLASH_SR_ERROR_MASK); break; default: @@ -177,23 +177,23 @@ void clear_flash_error(stlink_t *sl) { uint32_t read_flash_sr(stlink_t *sl, unsigned bank) { uint32_t res, sr_reg; - if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || - (sl->flash_type == STLINK_FLASH_TYPE_F1_XL)) { + if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || + (sl->flash_type == STM32_FLASH_TYPE_F1_XL)) { sr_reg = (bank == BANK_1) ? FLASH_SR : FLASH_SR2; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { sr_reg = get_stm32l0_flash_base(sl) + FLASH_SR_OFF; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { sr_reg = FLASH_F4_SR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { + } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { sr_reg = FLASH_F7_SR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { sr_reg = STM32L4_FLASH_SR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4) { sr_reg = STM32Gx_FLASH_SR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { sr_reg = STM32WB_FLASH_SR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { sr_reg = (bank == BANK_1) ? FLASH_H7_SR1 : FLASH_H7_SR2; } else { ELOG("method 'read_flash_sr' is unsupported\n"); @@ -208,22 +208,22 @@ unsigned int is_flash_busy(stlink_t *sl) { uint32_t sr_busy_shift; unsigned int res; - if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || - (sl->flash_type == STLINK_FLASH_TYPE_F1_XL) || - (sl->flash_type == STLINK_FLASH_TYPE_L0)) { + if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || + (sl->flash_type == STM32_FLASH_TYPE_F1_XL) || + (sl->flash_type == STM32_FLASH_TYPE_L0_L1)) { sr_busy_shift = FLASH_SR_BSY; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { sr_busy_shift = FLASH_F4_SR_BSY; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { + } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { sr_busy_shift = FLASH_F7_SR_BSY; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { sr_busy_shift = STM32L4_FLASH_SR_BSY; - } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4) { sr_busy_shift = STM32Gx_FLASH_SR_BSY; - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { sr_busy_shift = STM32WB_FLASH_SR_BSY; - } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { sr_busy_shift = FLASH_H7_SR_QW; } else { ELOG("method 'is_flash_busy' is unsupported\n"); @@ -232,8 +232,8 @@ unsigned int is_flash_busy(stlink_t *sl) { res = read_flash_sr(sl, BANK_1) & (1 << sr_busy_shift); - if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL || - (sl->flash_type == STLINK_FLASH_TYPE_H7 && + if (sl->flash_type == STM32_FLASH_TYPE_F1_XL || + (sl->flash_type == STM32_FLASH_TYPE_H7 && sl->chip_flags & CHIP_F_HAS_DUAL_BANK)) { res |= read_flash_sr(sl, BANK_2) & (1 << sr_busy_shift); } @@ -254,52 +254,52 @@ int check_flash_error(stlink_t *sl) { WRPERR = PROGERR = PGAERR = 0; switch (sl->flash_type) { - case STLINK_FLASH_TYPE_F0: - case STLINK_FLASH_TYPE_F1_XL: + case STM32_FLASH_TYPE_F0_F1_F3: + case STM32_FLASH_TYPE_F1_XL: res = read_flash_sr(sl, BANK_1) & FLASH_SR_ERROR_MASK; - if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL) { + if (sl->flash_type == STM32_FLASH_TYPE_F1_XL) { res |= read_flash_sr(sl, BANK_2) & FLASH_SR_ERROR_MASK; } WRPERR = (1 << FLASH_SR_WRPRT_ERR); PROGERR = (1 << FLASH_SR_PG_ERR); break; - case STLINK_FLASH_TYPE_F4: + case STM32_FLASH_TYPE_F2_F4: res = read_flash_sr(sl, BANK_1) & FLASH_F4_SR_ERROR_MASK; WRPERR = (1 << FLASH_F4_SR_WRPERR); PGAERR = (1 << FLASH_F4_SR_PGAERR); break; - case STLINK_FLASH_TYPE_F7: + case STM32_FLASH_TYPE_F7: res = read_flash_sr(sl, BANK_1) & FLASH_F7_SR_ERROR_MASK; WRPERR = (1 << FLASH_F7_SR_WRP_ERR); PROGERR = (1 << FLASH_F7_SR_PGP_ERR); break; - case STLINK_FLASH_TYPE_G0: - case STLINK_FLASH_TYPE_G4: + case STM32_FLASH_TYPE_G0: + case STM32_FLASH_TYPE_G4: res = read_flash_sr(sl, BANK_1) & STM32Gx_FLASH_SR_ERROR_MASK; WRPERR = (1 << STM32Gx_FLASH_SR_WRPERR); PROGERR = (1 << STM32Gx_FLASH_SR_PROGERR); PGAERR = (1 << STM32Gx_FLASH_SR_PGAERR); break; - case STLINK_FLASH_TYPE_L0: + case STM32_FLASH_TYPE_L0_L1: res = read_flash_sr(sl, BANK_1) & STM32L0_FLASH_SR_ERROR_MASK; WRPERR = (1 << STM32L0_FLASH_SR_WRPERR); PROGERR = (1 << STM32L0_FLASH_SR_NOTZEROERR); PGAERR = (1 << STM32L0_FLASH_SR_PGAERR); break; - case STLINK_FLASH_TYPE_L4: + case STM32_FLASH_TYPE_L4_L4P: res = read_flash_sr(sl, BANK_1) & STM32L4_FLASH_SR_ERROR_MASK; WRPERR = (1 << STM32L4_FLASH_SR_WRPERR); PROGERR = (1 << STM32L4_FLASH_SR_PROGERR); PGAERR = (1 << STM32L4_FLASH_SR_PGAERR); break; - case STLINK_FLASH_TYPE_H7: + case STM32_FLASH_TYPE_H7: res = read_flash_sr(sl, BANK_1) & FLASH_H7_SR_ERROR_MASK; if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { res |= read_flash_sr(sl, BANK_2) & FLASH_H7_SR_ERROR_MASK; } WRPERR = (1 << FLASH_H7_SR_WRPERR); break; - case STLINK_FLASH_TYPE_WB: + case STM32_FLASH_TYPE_WB_WL: res = read_flash_sr(sl, BANK_1) & STM32WB_FLASH_SR_ERROR_MASK; WRPERR = (1 << STM32WB_FLASH_SR_WRPERR); PROGERR = (1 << STM32WB_FLASH_SR_PROGERR); @@ -336,30 +336,30 @@ static inline unsigned int is_flash_locked(stlink_t *sl) { uint32_t cr_reg; uint32_t n; - if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || - (sl->flash_type == STLINK_FLASH_TYPE_F1_XL)) { + if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || + (sl->flash_type == STM32_FLASH_TYPE_F1_XL)) { cr_reg = FLASH_CR; cr_lock_shift = FLASH_CR_LOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { cr_reg = FLASH_F4_CR; cr_lock_shift = FLASH_F4_CR_LOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { + } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { cr_reg = FLASH_F7_CR; cr_lock_shift = FLASH_F7_CR_LOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { cr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF; cr_lock_shift = STM32L0_FLASH_PELOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { cr_reg = STM32L4_FLASH_CR; cr_lock_shift = STM32L4_FLASH_CR_LOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4) { cr_reg = STM32Gx_FLASH_CR; cr_lock_shift = STM32Gx_FLASH_CR_LOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { cr_reg = STM32WB_FLASH_CR; cr_lock_shift = STM32WB_FLASH_CR_LOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { cr_reg = FLASH_H7_CR1; cr_lock_shift = FLASH_H7_CR_LOCK; } else { @@ -380,27 +380,27 @@ static void unlock_flash(stlink_t *sl) { * definitive lock of the FPEC block until next reset. */ - if (sl->flash_type == STLINK_FLASH_TYPE_F0) { + if (sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) { key_reg = FLASH_KEYR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL) { + } else if (sl->flash_type == STM32_FLASH_TYPE_F1_XL) { key_reg = FLASH_KEYR; key2_reg = FLASH_KEYR2; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { key_reg = FLASH_F4_KEYR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { + } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { key_reg = FLASH_F7_KEYR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { key_reg = get_stm32l0_flash_base(sl) + FLASH_PEKEYR_OFF; flash_key1 = FLASH_L0_PEKEY1; flash_key2 = FLASH_L0_PEKEY2; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { key_reg = STM32L4_FLASH_KEYR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4) { key_reg = STM32Gx_FLASH_KEYR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { key_reg = STM32WB_FLASH_KEYR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { key_reg = FLASH_H7_KEYR1; if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { key2_reg = FLASH_H7_KEYR2; @@ -439,38 +439,38 @@ int lock_flash_option(stlink_t *sl) { int active_bit_level = 1; switch (sl->flash_type) { - case STLINK_FLASH_TYPE_F0: - case STLINK_FLASH_TYPE_F1_XL: + case STM32_FLASH_TYPE_F0_F1_F3: + case STM32_FLASH_TYPE_F1_XL: optcr_reg = FLASH_CR; optlock_shift = FLASH_CR_OPTWRE; active_bit_level = 0; break; - case STLINK_FLASH_TYPE_F4: + case STM32_FLASH_TYPE_F2_F4: optcr_reg = FLASH_F4_OPTCR; optlock_shift = FLASH_F4_OPTCR_LOCK; break; - case STLINK_FLASH_TYPE_F7: + case STM32_FLASH_TYPE_F7: optcr_reg = FLASH_F7_OPTCR; optlock_shift = FLASH_F7_OPTCR_LOCK; break; - case STLINK_FLASH_TYPE_L0: + case STM32_FLASH_TYPE_L0_L1: optcr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF; optlock_shift = STM32L0_FLASH_OPTLOCK; break; - case STLINK_FLASH_TYPE_L4: + case STM32_FLASH_TYPE_L4_L4P: optcr_reg = STM32L4_FLASH_CR; optlock_shift = STM32L4_FLASH_CR_OPTLOCK; break; - case STLINK_FLASH_TYPE_G0: - case STLINK_FLASH_TYPE_G4: + case STM32_FLASH_TYPE_G0: + case STM32_FLASH_TYPE_G4: optcr_reg = STM32Gx_FLASH_CR; optlock_shift = STM32Gx_FLASH_CR_OPTLOCK; break; - case STLINK_FLASH_TYPE_WB: + case STM32_FLASH_TYPE_WB_WL: optcr_reg = STM32WB_FLASH_CR; optlock_shift = STM32WB_FLASH_CR_OPTLOCK; break; - case STLINK_FLASH_TYPE_H7: + case STM32_FLASH_TYPE_H7: optcr_reg = FLASH_H7_OPTCR; optlock_shift = FLASH_H7_OPTCR_OPTLOCK; if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) @@ -512,38 +512,38 @@ static bool is_flash_option_locked(stlink_t *sl) { uint32_t n; switch (sl->flash_type) { - case STLINK_FLASH_TYPE_F0: - case STLINK_FLASH_TYPE_F1_XL: + case STM32_FLASH_TYPE_F0_F1_F3: + case STM32_FLASH_TYPE_F1_XL: optcr_reg = FLASH_CR; optlock_shift = FLASH_CR_OPTWRE; active_bit_level = 0; /* bit is "option write enable", not lock */ break; - case STLINK_FLASH_TYPE_F4: + case STM32_FLASH_TYPE_F2_F4: optcr_reg = FLASH_F4_OPTCR; optlock_shift = FLASH_F4_OPTCR_LOCK; break; - case STLINK_FLASH_TYPE_F7: + case STM32_FLASH_TYPE_F7: optcr_reg = FLASH_F7_OPTCR; optlock_shift = FLASH_F7_OPTCR_LOCK; break; - case STLINK_FLASH_TYPE_L0: + case STM32_FLASH_TYPE_L0_L1: optcr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF; optlock_shift = STM32L0_FLASH_OPTLOCK; break; - case STLINK_FLASH_TYPE_L4: + case STM32_FLASH_TYPE_L4_L4P: optcr_reg = STM32L4_FLASH_CR; optlock_shift = STM32L4_FLASH_CR_OPTLOCK; break; - case STLINK_FLASH_TYPE_G0: - case STLINK_FLASH_TYPE_G4: + case STM32_FLASH_TYPE_G0: + case STM32_FLASH_TYPE_G4: optcr_reg = STM32Gx_FLASH_CR; optlock_shift = STM32Gx_FLASH_CR_OPTLOCK; break; - case STLINK_FLASH_TYPE_WB: + case STM32_FLASH_TYPE_WB_WL: optcr_reg = STM32WB_FLASH_CR; optlock_shift = STM32WB_FLASH_CR_OPTLOCK; break; - case STLINK_FLASH_TYPE_H7: + case STM32_FLASH_TYPE_H7: optcr_reg = FLASH_H7_OPTCR; optlock_shift = FLASH_H7_OPTCR_OPTLOCK; break; @@ -567,34 +567,34 @@ static int unlock_flash_option(stlink_t *sl) { uint32_t optkey2 = FLASH_OPTKEY2; switch (sl->flash_type) { - case STLINK_FLASH_TYPE_F0: - case STLINK_FLASH_TYPE_F1_XL: + case STM32_FLASH_TYPE_F0_F1_F3: + case STM32_FLASH_TYPE_F1_XL: optkey_reg = FLASH_OPTKEYR; optkey1 = FLASH_F0_OPTKEY1; optkey2 = FLASH_F0_OPTKEY2; break; - case STLINK_FLASH_TYPE_F4: + case STM32_FLASH_TYPE_F2_F4: optkey_reg = FLASH_F4_OPT_KEYR; break; - case STLINK_FLASH_TYPE_F7: + case STM32_FLASH_TYPE_F7: optkey_reg = FLASH_F7_OPT_KEYR; break; - case STLINK_FLASH_TYPE_L0: + case STM32_FLASH_TYPE_L0_L1: optkey_reg = get_stm32l0_flash_base(sl) + FLASH_OPTKEYR_OFF; optkey1 = FLASH_L0_OPTKEY1; optkey2 = FLASH_L0_OPTKEY2; break; - case STLINK_FLASH_TYPE_L4: + case STM32_FLASH_TYPE_L4_L4P: optkey_reg = STM32L4_FLASH_OPTKEYR; break; - case STLINK_FLASH_TYPE_G0: - case STLINK_FLASH_TYPE_G4: + case STM32_FLASH_TYPE_G0: + case STM32_FLASH_TYPE_G4: optkey_reg = STM32Gx_FLASH_OPTKEYR; break; - case STLINK_FLASH_TYPE_WB: + case STM32_FLASH_TYPE_WB_WL: optkey_reg = STM32WB_FLASH_OPT_KEYR; break; - case STLINK_FLASH_TYPE_H7: + case STM32_FLASH_TYPE_H7: optkey_reg = FLASH_H7_OPT_KEYR; if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) optkey2_reg = FLASH_H7_OPT_KEYR2; @@ -637,7 +637,7 @@ void write_flash_cr_psiz(stlink_t *sl, uint32_t n, uint32_t cr_reg, psize_shift; uint32_t x = read_flash_cr(sl, bank); - if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + if (sl->flash_type == STM32_FLASH_TYPE_H7) { cr_reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; psize_shift = FLASH_H7_CR_PSIZE; } else { @@ -657,18 +657,18 @@ void clear_flash_cr_pg(stlink_t *sl, unsigned bank) { uint32_t cr_reg, n; uint32_t bit = FLASH_CR_PG; - if (sl->flash_type == STLINK_FLASH_TYPE_F4) { + if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { cr_reg = FLASH_F4_CR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { + } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { cr_reg = FLASH_F7_CR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { cr_reg = STM32L4_FLASH_CR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4) { cr_reg = STM32Gx_FLASH_CR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { cr_reg = STM32WB_FLASH_CR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { cr_reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; bit = FLASH_H7_CR_PG; } else { @@ -706,7 +706,7 @@ static inline void write_flash_cr_snb(stlink_t *sl, uint32_t n, unsigned bank) { uint32_t cr_reg, snb_mask, snb_shift, ser_shift; uint32_t x = read_flash_cr(sl, bank); - if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + if (sl->flash_type == STM32_FLASH_TYPE_H7) { cr_reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; snb_mask = FLASH_H7_CR_SNB_MASK; snb_shift = FLASH_H7_CR_SNB; @@ -730,10 +730,10 @@ static inline void write_flash_cr_snb(stlink_t *sl, uint32_t n, unsigned bank) { static void set_flash_cr_per(stlink_t *sl, unsigned bank) { uint32_t cr_reg, val; - if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { + if (sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4) { cr_reg = STM32Gx_FLASH_CR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { cr_reg = STM32WB_FLASH_CR; } else { cr_reg = (bank == BANK_1) ? FLASH_CR : FLASH_CR2; @@ -747,10 +747,10 @@ static void set_flash_cr_per(stlink_t *sl, unsigned bank) { static void clear_flash_cr_per(stlink_t *sl, unsigned bank) { uint32_t cr_reg; - if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { + if (sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4) { cr_reg = STM32Gx_FLASH_CR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { cr_reg = STM32WB_FLASH_CR; } else { cr_reg = (bank == BANK_1) ? FLASH_CR : FLASH_CR2; @@ -779,23 +779,23 @@ static inline void write_flash_cr_bker_pnb(stlink_t *sl, uint32_t n) { static void set_flash_cr_strt(stlink_t *sl, unsigned bank) { uint32_t val, cr_reg, cr_strt; - if (sl->flash_type == STLINK_FLASH_TYPE_F4) { + if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { cr_reg = FLASH_F4_CR; cr_strt = 1 << FLASH_F4_CR_STRT; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { + } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { cr_reg = FLASH_F7_CR; cr_strt = 1 << FLASH_F7_CR_STRT; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { cr_reg = STM32L4_FLASH_CR; cr_strt = (1 << STM32L4_FLASH_CR_STRT); - } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4) { cr_reg = STM32Gx_FLASH_CR; cr_strt = (1 << STM32Gx_FLASH_CR_STRT); - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { cr_reg = STM32WB_FLASH_CR; cr_strt = (1 << STM32WB_FLASH_CR_STRT); - } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { cr_reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; cr_strt = 1 << FLASH_H7_CR_START(sl->chip_id); } else { @@ -811,20 +811,20 @@ static void set_flash_cr_strt(stlink_t *sl, unsigned bank) { static void set_flash_cr_mer(stlink_t *sl, bool v, unsigned bank) { uint32_t val, cr_reg, cr_mer, cr_pg; - if (sl->flash_type == STLINK_FLASH_TYPE_F4) { + if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { cr_reg = FLASH_F4_CR; cr_mer = 1 << FLASH_CR_MER; cr_pg = 1 << FLASH_CR_PG; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { + } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { cr_reg = FLASH_F7_CR; cr_mer = 1 << FLASH_CR_MER; cr_pg = 1 << FLASH_CR_PG; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { cr_reg = STM32L4_FLASH_CR; cr_mer = (1 << STM32L4_FLASH_CR_MER1) | (1 << STM32L4_FLASH_CR_MER2); cr_pg = (1 << STM32L4_FLASH_CR_PG); - } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4) { cr_reg = STM32Gx_FLASH_CR; cr_mer = (1 << STM32Gx_FLASH_CR_MER1); @@ -833,11 +833,11 @@ static void set_flash_cr_mer(stlink_t *sl, bool v, unsigned bank) { } cr_pg = (1 << FLASH_CR_PG); - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { cr_reg = STM32WB_FLASH_CR; cr_mer = (1 << FLASH_CR_MER); cr_pg = (1 << FLASH_CR_PG); - } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { cr_reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; cr_mer = (1 << FLASH_H7_CR_BER); cr_pg = (1 << FLASH_H7_CR_PG); @@ -877,18 +877,18 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { // clear flash IO errors clear_flash_error(sl); - if (sl->flash_type == STLINK_FLASH_TYPE_F4 || - sl->flash_type == STLINK_FLASH_TYPE_F7 || - sl->flash_type == STLINK_FLASH_TYPE_L4) { + if (sl->flash_type == STM32_FLASH_TYPE_F2_F4 || + sl->flash_type == STM32_FLASH_TYPE_F7 || + sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { // unlock if locked unlock_flash_if(sl); // select the page to erase - if ((sl->chip_id == STLINK_CHIPID_STM32_L4) || - (sl->chip_id == STLINK_CHIPID_STM32_L43x_L44x) || - (sl->chip_id == STLINK_CHIPID_STM32_L45x_L46x) || - (sl->chip_id == STLINK_CHIPID_STM32_L496x_L4A6x) || - (sl->chip_id == STLINK_CHIPID_STM32_L4Rx)) { + if ((sl->chip_id == STM32_CHIPID_L4) || + (sl->chip_id == STM32_CHIPID_L43x_L44x) || + (sl->chip_id == STM32_CHIPID_L45x_L46x) || + (sl->chip_id == STM32_CHIPID_L496x_L4A6x) || + (sl->chip_id == STM32_CHIPID_L4Rx)) { // calculate the actual bank+page from the address uint32_t page = calculate_L4_page(sl, flashaddr); @@ -896,8 +896,8 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { stlink_calculate_pagesize(sl, flashaddr)); write_flash_cr_bker_pnb(sl, page); - } else if (sl->chip_id == STLINK_CHIPID_STM32_F7 || - sl->chip_id == STLINK_CHIPID_STM32_F76xxx) { + } else if (sl->chip_id == STM32_CHIPID_F7 || + sl->chip_id == STM32_CHIPID_F76xxx) { // calculate the actual page from the address uint32_t sector = calculate_F7_sectornum(flashaddr); @@ -926,7 +926,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { #if DEBUG_FLASH fprintf(stdout, "Erase Final CR:0x%x\n", read_flash_cr(sl, BANK_1)); #endif - } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { uint32_t val; uint32_t flash_regs_base = get_stm32l0_flash_base(sl); @@ -982,15 +982,15 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); val |= (1 << 0) | (1 << 1) | (1 << 2); stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB || - sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL || + sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4) { uint32_t val; unlock_flash_if(sl); set_flash_cr_per(sl, BANK_1); // set the 'enable Flash erase' bit // set the page to erase - if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { uint32_t flash_page = ((flashaddr - STM32_FLASH_BASE) / (uint32_t)(sl->flash_pgsz)); stlink_read_debug32(sl, STM32WB_FLASH_CR, &val); @@ -1000,7 +1000,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { val |= ((flash_page & 0xFF) << 3); stlink_write_debug32(sl, STM32WB_FLASH_CR, val); - } else if (sl->flash_type == STLINK_FLASH_TYPE_G0) { + } else if (sl->flash_type == STM32_FLASH_TYPE_G0) { uint32_t flash_page = ((flashaddr - STM32_FLASH_BASE) / (uint32_t)(sl->flash_pgsz)); stlink_read_debug32(sl, STM32Gx_FLASH_CR, &val); @@ -1008,7 +1008,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { val &= ~(0x3F << 3); val |= ((flash_page & 0x3F) << 3) | (1 << FLASH_CR_PER); stlink_write_debug32(sl, STM32Gx_FLASH_CR, val); - } else if (sl->flash_type == STLINK_FLASH_TYPE_G4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_G4) { uint32_t flash_page = ((flashaddr - STM32_FLASH_BASE) / (uint32_t)(sl->flash_pgsz)); stlink_read_debug32(sl, STM32Gx_FLASH_CR, &val); @@ -1022,8 +1022,8 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { wait_flash_busy(sl); // wait for the 'busy' bit to clear clear_flash_cr_per(sl, BANK_1); // clear the 'enable page erase' bit lock_flash(sl); - } else if (sl->flash_type == STLINK_FLASH_TYPE_F0 || - sl->flash_type == STLINK_FLASH_TYPE_F1_XL) { + } else if (sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3 || + sl->flash_type == STM32_FLASH_TYPE_F1_XL) { unsigned bank = (flashaddr < STM32_F1_FLASH_BANK2_BASE) ? BANK_1 : BANK_2; unlock_flash_if(sl); clear_flash_cr_pg(sl, bank); // clear the pg bit @@ -1034,7 +1034,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { wait_flash_busy(sl); clear_flash_cr_per(sl, bank); // clear the page erase bit lock_flash(sl); - } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { unsigned bank = (flashaddr < STM32_H7_FLASH_BANK2_BASE) ? BANK_1 : BANK_2; unlock_flash_if(sl); // unlock if locked uint32_t sector = calculate_H7_sectornum( @@ -1093,8 +1093,8 @@ int stlink_erase_flash_mass(stlink_t *sl) { int err = 0; // TODO: User MER bit to mass-erase WB series. - if (sl->flash_type == STLINK_FLASH_TYPE_L0 || - sl->flash_type == STLINK_FLASH_TYPE_WB) { + if (sl->flash_type == STM32_FLASH_TYPE_L0_L1 || + sl->flash_type == STM32_FLASH_TYPE_WB_WL) { err = stlink_erase_flash_section(sl, sl->flash_base, sl->flash_size, false); @@ -1103,8 +1103,8 @@ int stlink_erase_flash_mass(stlink_t *sl) { clear_flash_error(sl); unlock_flash_if(sl); - if (sl->flash_type == STLINK_FLASH_TYPE_H7 && - sl->chip_id != STLINK_CHIPID_STM32_H7Ax) { + if (sl->flash_type == STM32_FLASH_TYPE_H7 && + sl->chip_id != STM32_CHIPID_H7Ax) { // set parallelism write_flash_cr_psiz(sl, 3 /*64it*/, BANK_1); if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { @@ -1116,8 +1116,8 @@ int stlink_erase_flash_mass(stlink_t *sl) { set_flash_cr_strt( sl, BANK_1); // start erase operation, reset by hw with busy bit - if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL || - (sl->flash_type == STLINK_FLASH_TYPE_H7 && + if (sl->flash_type == STM32_FLASH_TYPE_F1_XL || + (sl->flash_type == STM32_FLASH_TYPE_H7 && sl->chip_flags & CHIP_F_HAS_DUAL_BANK)) { set_flash_cr_mer(sl, 1, BANK_2); // set the mass erase bit in bank 2 set_flash_cr_strt(sl, BANK_2); // start erase operation in bank 2 @@ -1128,8 +1128,8 @@ int stlink_erase_flash_mass(stlink_t *sl) { // reset the mass erase bit set_flash_cr_mer(sl, 0, BANK_1); - if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL || - (sl->flash_type == STLINK_FLASH_TYPE_H7 && + if (sl->flash_type == STM32_FLASH_TYPE_F1_XL || + (sl->flash_type == STM32_FLASH_TYPE_H7 && sl->chip_flags & CHIP_F_HAS_DUAL_BANK)) { set_flash_cr_mer(sl, 0, BANK_2); } diff --git a/src/flashloader.c b/src/flashloader.c index f84e16ef0..e4c7d7200 100644 --- a/src/flashloader.c +++ b/src/flashloader.c @@ -73,24 +73,24 @@ static void set_flash_cr_pg(stlink_t *sl, unsigned bank) { x = read_flash_cr(sl, bank); - if (sl->flash_type == STLINK_FLASH_TYPE_F4) { + if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { cr_reg = FLASH_F4_CR; x |= 1 << FLASH_CR_PG; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { + } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { cr_reg = FLASH_F7_CR; x |= 1 << FLASH_CR_PG; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { cr_reg = STM32L4_FLASH_CR; x &= ~STM32L4_FLASH_CR_OPBITS; x |= (1 << STM32L4_FLASH_CR_PG); - } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4) { cr_reg = STM32Gx_FLASH_CR; x |= (1 << FLASH_CR_PG); - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { cr_reg = STM32WB_FLASH_CR; x |= (1 << FLASH_CR_PG); - } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { cr_reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; x |= (1 << FLASH_H7_CR_PG); } else { @@ -107,34 +107,34 @@ static void set_dma_state(stlink_t *sl, flash_loader_t *fl, int bckpRstr) { rcc = rcc_dma_mask = value = 0; switch (sl->flash_type) { - case STLINK_FLASH_TYPE_F0: - case STLINK_FLASH_TYPE_F1_XL: + case STM32_FLASH_TYPE_F0_F1_F3: + case STM32_FLASH_TYPE_F1_XL: rcc = STM32F1_RCC_AHBENR; rcc_dma_mask = STM32F1_RCC_DMAEN; break; - case STLINK_FLASH_TYPE_F4: - case STLINK_FLASH_TYPE_F7: + case STM32_FLASH_TYPE_F2_F4: + case STM32_FLASH_TYPE_F7: rcc = STM32F4_RCC_AHB1ENR; rcc_dma_mask = STM32F4_RCC_DMAEN; break; - case STLINK_FLASH_TYPE_G0: + case STM32_FLASH_TYPE_G0: rcc = STM32G0_RCC_AHBENR; rcc_dma_mask = STM32G0_RCC_DMAEN; break; - case STLINK_FLASH_TYPE_G4: - case STLINK_FLASH_TYPE_L4: + case STM32_FLASH_TYPE_G4: + case STM32_FLASH_TYPE_L4_L4P: rcc = STM32G4_RCC_AHB1ENR; rcc_dma_mask = STM32G4_RCC_DMAEN; break; - case STLINK_FLASH_TYPE_L0: + case STM32_FLASH_TYPE_L0_L1: rcc = STM32L0_RCC_AHBENR; rcc_dma_mask = STM32L0_RCC_DMAEN; break; - case STLINK_FLASH_TYPE_H7: + case STM32_FLASH_TYPE_H7: rcc = STM32H7_RCC_AHB1ENR; rcc_dma_mask = STM32H7_RCC_DMAEN; break; - case STLINK_FLASH_TYPE_WB: + case STM32_FLASH_TYPE_WB_WL: rcc = STM32WB_RCC_AHB1ENR; rcc_dma_mask = STM32WB_RCC_DMAEN; break; @@ -162,9 +162,9 @@ int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { // Clear errors clear_flash_error(sl); - if ((sl->flash_type == STLINK_FLASH_TYPE_F4) || - (sl->flash_type == STLINK_FLASH_TYPE_F7) || - (sl->flash_type == STLINK_FLASH_TYPE_L4)) { + if ((sl->flash_type == STM32_FLASH_TYPE_F2_F4) || + (sl->flash_type == STM32_FLASH_TYPE_F7) || + (sl->flash_type == STM32_FLASH_TYPE_L4_L4P)) { ILOG("Starting Flash write for F2/F4/F7/L4\n"); // Flash loader initialisation @@ -188,7 +188,7 @@ int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { return (-1); } - if (sl->flash_type == STLINK_FLASH_TYPE_L4) { + if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { // L4 does not have a byte-write mode if (voltage < 1710) { ELOG("Target voltage (%d mV) too low for flash writes!\n", voltage); @@ -208,14 +208,14 @@ int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { // set programming mode set_flash_cr_pg(sl, BANK_1); - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB || - sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL || + sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4) { ILOG("Starting Flash write for WB/G0/G4\n"); unlock_flash_if(sl); // unlock flash if necessary set_flash_cr_pg(sl, BANK_1); // set PG 'allow programming' bit - } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { ILOG("Starting Flash write for L0\n"); uint32_t val; @@ -252,8 +252,8 @@ int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { // L0/L1 have fallback to soft write WLOG("stlink_flash_loader_init() == -1\n"); } - } else if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || - (sl->flash_type == STLINK_FLASH_TYPE_F1_XL)) { + } else if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || + (sl->flash_type == STM32_FLASH_TYPE_F1_XL)) { ILOG("Starting Flash write for VL/F0/F3/F1_XL\n"); // flash loader initialisation @@ -267,10 +267,10 @@ int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { // set programming mode set_flash_cr_pg(sl, BANK_1); - if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL) { + if (sl->flash_type == STM32_FLASH_TYPE_F1_XL) { set_flash_cr_pg(sl, BANK_2); } - } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { ILOG("Starting Flash write for H7\n"); unlock_flash_if(sl); // unlock the cr @@ -278,7 +278,7 @@ int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { set_flash_cr_pg(sl, BANK_2); } - if (sl->chip_id != STLINK_CHIPID_STM32_H7Ax) { + if (sl->chip_id != STM32_CHIPID_H7Ax) { // set parallelism write_flash_cr_psiz(sl, 3 /*64it*/, BANK_1); if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { @@ -296,9 +296,9 @@ int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t addr, uint8_t *base, uint32_t len) { size_t off; - if ((sl->flash_type == STLINK_FLASH_TYPE_F4) || - (sl->flash_type == STLINK_FLASH_TYPE_F7) || - (sl->flash_type == STLINK_FLASH_TYPE_L4)) { + if ((sl->flash_type == STM32_FLASH_TYPE_F2_F4) || + (sl->flash_type == STM32_FLASH_TYPE_F7) || + (sl->flash_type == STM32_FLASH_TYPE_L4_L4P)) { size_t buf_size = (sl->sram_size > 0x8000) ? 0x8000 : 0x4000; for (off = 0; off < len;) { size_t size = len - off > buf_size ? buf_size : len - off; @@ -312,9 +312,9 @@ int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, off += size; } - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB || - sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL || + sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4) { DLOG("Starting %3u page write\r\n", (unsigned int)(len / sl->flash_pgsz)); for (off = 0; off < len; off += sizeof(uint32_t)) { uint32_t data; @@ -338,7 +338,7 @@ int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, 0); // write a single word of zeros wait_flash_busy(sl); // wait for 'busy' bit in FLASH_SR to clear } - } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { uint32_t val; uint32_t flash_regs_base = get_stm32l0_flash_base(sl); uint32_t pagesize = (flash_regs_base==STM32L0_FLASH_REGS_ADDR)? @@ -378,8 +378,8 @@ int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, // TODO: check redo write operation } fprintf(stdout, "\n"); - } else if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || - (sl->flash_type == STLINK_FLASH_TYPE_F1_XL)) { + } else if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || + (sl->flash_type == STM32_FLASH_TYPE_F1_XL)) { int write_block_count = 0; for (off = 0; off < len; off += sl->flash_pgsz) { // adjust last write size @@ -411,7 +411,7 @@ int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, if (sl->verbose >= 1) { fprintf(stdout, "\n"); } - } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { for (off = 0; off < len;) { // Program STM32H7x with 64-byte Flash words size_t chunk = (len - off > 64) ? 64 : len - off; @@ -441,24 +441,24 @@ int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, int stlink_flashloader_stop(stlink_t *sl, flash_loader_t *fl) { uint32_t dhcsr; - if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || - (sl->flash_type == STLINK_FLASH_TYPE_F1_XL) || - (sl->flash_type == STLINK_FLASH_TYPE_F4) || - (sl->flash_type == STLINK_FLASH_TYPE_F7) || - (sl->flash_type == STLINK_FLASH_TYPE_L4) || - (sl->flash_type == STLINK_FLASH_TYPE_WB) || - (sl->flash_type == STLINK_FLASH_TYPE_G0) || - (sl->flash_type == STLINK_FLASH_TYPE_G4) || - (sl->flash_type == STLINK_FLASH_TYPE_H7)) { + if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || + (sl->flash_type == STM32_FLASH_TYPE_F1_XL) || + (sl->flash_type == STM32_FLASH_TYPE_F2_F4) || + (sl->flash_type == STM32_FLASH_TYPE_F7) || + (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) || + (sl->flash_type == STM32_FLASH_TYPE_WB_WL) || + (sl->flash_type == STM32_FLASH_TYPE_G0) || + (sl->flash_type == STM32_FLASH_TYPE_G4) || + (sl->flash_type == STM32_FLASH_TYPE_H7)) { clear_flash_cr_pg(sl, BANK_1); - if ((sl->flash_type == STLINK_FLASH_TYPE_H7 && + if ((sl->flash_type == STM32_FLASH_TYPE_H7 && sl->chip_flags & CHIP_F_HAS_DUAL_BANK) || - sl->flash_type == STLINK_FLASH_TYPE_F1_XL) { + sl->flash_type == STM32_FLASH_TYPE_F1_XL) { clear_flash_cr_pg(sl, BANK_2); } lock_flash(sl); - } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { uint32_t val; uint32_t flash_regs_base = get_stm32l0_flash_base(sl); diff --git a/src/option_bytes.c b/src/option_bytes.c index ed9ee4f39..f5d8c00a0 100644 --- a/src/option_bytes.c +++ b/src/option_bytes.c @@ -119,17 +119,17 @@ int stlink_read_option_bytes32(stlink_t *sl, uint32_t *option_byte) { } switch (sl->chip_id) { - case STLINK_CHIPID_STM32_F2: + case STM32_CHIPID_F2: return stlink_read_option_bytes_f2(sl, option_byte); - case STLINK_CHIPID_STM32_F4: - case STLINK_CHIPID_STM32_F446: + case STM32_CHIPID_F4: + case STM32_CHIPID_F446: return stlink_read_option_bytes_f4(sl, option_byte); - case STLINK_CHIPID_STM32_F76xxx: + case STM32_CHIPID_F76xxx: return stlink_read_option_bytes_f7(sl, option_byte); - case STLINK_CHIPID_STM32_G0_CAT1: - case STLINK_CHIPID_STM32_G0_CAT2: - case STLINK_CHIPID_STM32_G4_CAT2: - case STLINK_CHIPID_STM32_G4_CAT3: + case STM32_CHIPID_G0_CAT1: + case STM32_CHIPID_G0_CAT2: + case STM32_CHIPID_G4_CAT2: + case STM32_CHIPID_G4_CAT3: return stlink_read_option_bytes_Gx(sl, option_byte); default: return stlink_read_option_bytes_generic(sl, option_byte); @@ -513,27 +513,27 @@ int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t *base, } switch (sl->flash_type) { - case STLINK_FLASH_TYPE_F0: - case STLINK_FLASH_TYPE_F1_XL: + case STM32_FLASH_TYPE_F0_F1_F3: + case STM32_FLASH_TYPE_F1_XL: ret = stlink_write_option_bytes_f0(sl, base, addr, len); break; - case STLINK_FLASH_TYPE_F4: + case STM32_FLASH_TYPE_F2_F4: ret = stlink_write_option_bytes_f4(sl, base, addr, len); break; - case STLINK_FLASH_TYPE_F7: + case STM32_FLASH_TYPE_F7: ret = stlink_write_option_bytes_f7(sl, base, addr, len); break; - case STLINK_FLASH_TYPE_L0: + case STM32_FLASH_TYPE_L0_L1: ret = stlink_write_option_bytes_l0(sl, base, addr, len); break; - case STLINK_FLASH_TYPE_L4: + case STM32_FLASH_TYPE_L4_L4P: ret = stlink_write_option_bytes_l4(sl, base, addr, len); break; - case STLINK_FLASH_TYPE_G0: - case STLINK_FLASH_TYPE_G4: + case STM32_FLASH_TYPE_G0: + case STM32_FLASH_TYPE_G4: ret = stlink_write_option_bytes_gx(sl, base, addr, len); break; - case STLINK_FLASH_TYPE_H7: + case STM32_FLASH_TYPE_H7: ret = stlink_write_option_bytes_h7(sl, base, addr, len); break; default: @@ -739,11 +739,11 @@ int stlink_write_option_control_register32(stlink_t *sl, } switch (sl->flash_type) { - case STLINK_FLASH_TYPE_F0: - case STLINK_FLASH_TYPE_F1_XL: + case STM32_FLASH_TYPE_F0_F1_F3: + case STM32_FLASH_TYPE_F1_XL: ret = stlink_write_option_control_register_f0(sl, option_control_register); break; - case STLINK_FLASH_TYPE_F7: + case STM32_FLASH_TYPE_F7: ret = stlink_write_option_control_register_f7(sl, option_control_register); break; default: @@ -788,7 +788,7 @@ int stlink_write_option_control_register1_32( } switch (sl->flash_type) { - case STLINK_FLASH_TYPE_F7: + case STM32_FLASH_TYPE_F7: ret = stlink_write_option_control_register1_f7(sl, option_control_register1); break; @@ -847,7 +847,7 @@ int stlink_write_option_bytes_boot_add32(stlink_t *sl, } switch (sl->flash_type) { - case STLINK_FLASH_TYPE_F7: + case STM32_FLASH_TYPE_F7: ret = stlink_write_option_bytes_boot_add_f7(sl, option_bytes_boot_add); break; default: @@ -937,7 +937,7 @@ int stlink_read_option_control_register1_32(stlink_t *sl, } switch (sl->flash_type) { - case STLINK_FLASH_TYPE_F7: + case STM32_FLASH_TYPE_F7: return stlink_read_option_control_register1_f7(sl, option_byte); default: return -1; @@ -971,7 +971,7 @@ int stlink_read_option_bytes_boot_add32(stlink_t *sl, uint32_t *option_byte) { } switch (sl->flash_type) { - case STLINK_FLASH_TYPE_F7: + case STM32_FLASH_TYPE_F7: return stlink_read_option_bytes_boot_add_f7(sl, option_byte); default: return -1; @@ -1016,10 +1016,10 @@ int stlink_read_option_control_register32(stlink_t *sl, uint32_t *option_byte) { } switch (sl->flash_type) { - case STLINK_FLASH_TYPE_F0: - case STLINK_FLASH_TYPE_F1_XL: + case STM32_FLASH_TYPE_F0_F1_F3: + case STM32_FLASH_TYPE_F1_XL: return stlink_read_option_control_register_f0(sl, option_byte); - case STLINK_FLASH_TYPE_F7: + case STM32_FLASH_TYPE_F7: return stlink_read_option_control_register_f7(sl, option_byte); default: return -1; From 935c6af9b48fe5fbe730c6801cf3720a4d8ae3f4 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 30 Jan 2022 14:54:46 +0100 Subject: [PATCH 370/503] Updated description for F1 CL chip --- config/chips/F1xx_CL.chip | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/config/chips/F1xx_CL.chip b/config/chips/F1xx_CL.chip index d774412e1..45f06d386 100644 --- a/config/chips/F1xx_CL.chip +++ b/config/chips/F1xx_CL.chip @@ -1,4 +1,4 @@ -# Chip-ID file for STM32F1xx Connectivity Line device +# Chip-ID file for STM32F1xx Connectivity Line device (F105 / F107) # dev_type STM32F1xx_CL ref_manual_id 0008 From 0011064797cd710f9b684e07c0083b5464e9a031 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 30 Jan 2022 15:47:55 +0100 Subject: [PATCH 371/503] Rolled-back deletion of recent changes --- CHANGELOG.md | 18 +- README.md | 2 +- cmake/modules/Findlibusb.cmake | 2 +- cmake/packaging/cpack_config.cmake | 2 +- cmake/packaging/deb/control | 2 +- contributors.txt | 3 + doc/compiling.md | 4 +- doc/version_support.md | 155 +- inc/stlink.h | 3 +- inc/stm32.h | 8 +- src/stlink-lib/chipid.h | 3 +- src/stlink-lib/usb.c.bak | 1410 ----------------- src/win32/unistd/unistd.h | 2 +- src/win32/unistd/unistd.h.bak | 76 - stlinkv1_macos_driver/install.sh | 3 - .../Contents/Info.plist | 82 - .../Contents/MacOS/stlink_shield_10_14 | Bin 33840 -> 0 bytes .../stlink_shield_10_14.kext/Contents/PkgInfo | 1 - .../Contents/_CodeSignature/CodeResources | 115 -- .../stlink_shield.xcodeproj/project.pbxproj | 50 - 20 files changed, 113 insertions(+), 1828 deletions(-) delete mode 100644 src/stlink-lib/usb.c.bak delete mode 100644 src/win32/unistd/unistd.h.bak delete mode 100644 stlinkv1_macos_driver/stlink_shield_10_14.kext/Contents/Info.plist delete mode 100644 stlinkv1_macos_driver/stlink_shield_10_14.kext/Contents/MacOS/stlink_shield_10_14 delete mode 100644 stlinkv1_macos_driver/stlink_shield_10_14.kext/Contents/PkgInfo delete mode 100644 stlinkv1_macos_driver/stlink_shield_10_14.kext/Contents/_CodeSignature/CodeResources diff --git a/CHANGELOG.md b/CHANGELOG.md index 06f995d21..71188afb0 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -2,10 +2,14 @@ # v1.7.1 -Release date: 2021-xx-xx +Release date: 2022-xx-xx This release drops support for some older operating systems. Check project README for details. -Updated system requirements: Raised minimum version for `cmake` to 3.7.2. + +Updated system requirements: +- `cmake` >= 3.10.2 +- `libusb` >= 1.0.21 +- `libgtk-dev` >= 3.22.30 Features: @@ -15,6 +19,9 @@ Features: - Expanded and revised list of chips ([#1145](https://github.com/stlink-org/stlink/pull/1145), [#1164](https://github.com/stlink-org/stlink/pull/1164)) - [STM32H72X/3X]: Added full access to all device memory ([#1158](https://github.com/stlink-org/stlink/pull/1158), [#1159](https://github.com/stlink-org/stlink/pull/1159)) - Added support for STM32WLEx ([#1173](https://github.com/stlink-org/stlink/pull/1173)) +- Added support for STLINK-V3 devices with no MSD ([#1185](https://github.com/stlink-org/stlink/pull/1185)) +- Updated gdb-server.c to allow external memory access on STM32H73xx ([#1196](https://github.com/stlink-org/stlink/pull/1196), [#1197](https://github.com/stlink-org/stlink/pull/1197)) +- Erase addr size / section of the flash memory with st-flash ([#1213](https://github.com/stlink-org/stlink/pull/1213)) Updates & changes: @@ -22,10 +29,12 @@ Updates & changes: - Added instructions for bug-reports and feature-requests to contribution guidelines ([#906](https://github.com/stlink-org/stlink/pull/906)) - Added travis CI configuration for macOS 10.14 to maintain capability for 32-bit compilation ([#f5ada94](https://github.com/stlink-org/stlink/commit/f5ada9474cdb87ff37de0d4eb9e75622b5870646)) - Updated description of chip id 0x0457 to L01x/L02x ([#1143](https://github.com/stlink-org/stlink/pull/1143), [#1144](https://github.com/stlink-org/stlink/pull/1144)) -- Drop execute bits from source code files ([#1167](https://github.com/stlink-org/stlink/pull/1167)) +- Dropped execute bits from source code files ([#1167](https://github.com/stlink-org/stlink/pull/1167)) - Use proper Markdown headers for supported MCUs ([#1168](https://github.com/stlink-org/stlink/pull/1168)) - Removed redundant array ([#1178](https://github.com/stlink-org/stlink/pull/1178)) - Updated chip config files from the library structs ([#1181](https://github.com/stlink-org/stlink/pull/1181)) +- [doc] Corrected file path in tutorial ([#1186](https://github.com/stlink-org/stlink/pull/1186)) +- Improved chipid checks and printouts ([#1188](https://github.com/stlink-org/stlink/pull/1188)) Fixes: - cmake: Install shared libraries in proper directories ([#1142](https://github.com/stlink-org/stlink/pull/1142)) @@ -41,6 +50,9 @@ Fixes: - Fixed few warnings for msvc about type conversion with possible lost data ([#1179](https://github.com/stlink-org/stlink/pull/1179)) - st-flash and other utilities search for chip files in the wrong directory ([#1180](https://github.com/stlink-org/stlink/pull/1180), commit [#c8fc656](https://github.com/stlink-org/stlink/commit/c8fc6561fead79ad49c09d82bab864745086792c)) - Fixed broken build on 32 bit systems ([#985](https://github.com/stlink-org/stlink/pull/985), [#1175](https://github.com/stlink-org/stlink/pull/1175), commit [#c8fc656](https://github.com/stlink-org/stlink/commit/c8fc6561fead79ad49c09d82bab864745086792c)) +- Define 'SSIZE_MAX' if not defined ([#1183](https://github.com/stlink-org/stlink/pull/1183)) +- Fixed compliation for OpenBSD 7.0 ([#1202](https://github.com/stlink-org/stlink/pull/1202)) +- Included 'SSIZE_MAX' from 'limits.h' in 'src/common.c' ([#1207](https://github.com/stlink-org/stlink/pull/1207)) # v1.7.0 diff --git a/README.md b/README.md index 7f797a7d9..bc491189e 100644 --- a/README.md +++ b/README.md @@ -38,7 +38,7 @@ It supports several so called STLINK programmer boards (and clones thereof) whic - stand-alone programmer (STLINK-V3SET, STLINK-V3MINI, STLINK-V3MODS) - on-board on some STM32 Nucleo boards (STLINK-V3E) -_\*)_ **Note: Support for the STLINK/V1 on macOS is limited to 10.14 - 10.15. Due to the deprecation and removal of macOS Kernel Extensions (KEXT) there will be no support for this programmer on macOS 11 or any later version.** +_\*)_ *Note: Support for the STLINK/V1 on macOS is limited to 10.15. Due to the deprecation and removal of macOS Kernel Extensions (KEXT) there will be no support for this programmer on macOS 11 or any later version.* On the user level there is no difference in handling or operation between these different revisions. diff --git a/cmake/modules/Findlibusb.cmake b/cmake/modules/Findlibusb.cmake index cd52026f5..bc04f848d 100644 --- a/cmake/modules/Findlibusb.cmake +++ b/cmake/modules/Findlibusb.cmake @@ -72,7 +72,7 @@ elseif (WIN32 OR (EXISTS "/etc/debian_version" AND MINGW)) # Windows or MinGW-to if (WIN32 AND NOT EXISTS "/etc/debian_version") # Skip this for Debian... # Preparations for installing libusb library - set(LIBUSB_WIN_VERSION 1.0.23) # set libusb version + set(LIBUSB_WIN_VERSION 1.0.24) # set libusb version set(LIBUSB_WIN_ARCHIVE libusb-${LIBUSB_WIN_VERSION}.7z) if (WIN32 AND NOT EXISTS "/etc/debian_version") # ... on native Windows systems set(LIBUSB_WIN_ARCHIVE_PATH ${CMAKE_BINARY_DIR}/${LIBUSB_WIN_ARCHIVE}) diff --git a/cmake/packaging/cpack_config.cmake b/cmake/packaging/cpack_config.cmake index acd5630fa..587ff5fb5 100644 --- a/cmake/packaging/cpack_config.cmake +++ b/cmake/packaging/cpack_config.cmake @@ -53,7 +53,7 @@ elseif (EXISTS "/etc/debian_version" AND NOT EXISTS WIN32) # Package-build is av set(CPACK_DEBIAN_PACKAGE_RELEASE "1") # CPACK_DEBIAN_PACKAGE_ARCHITECTURE --> Default: Output of dpkg --print-architecture - set(CPACK_DEBIAN_PACKAGE_DEPENDS "pkg-config, build-essential, debhelper (>=9), cmake (>= 3.4.2), libusb-1.0-0-dev (>= 1.0.20)") + set(CPACK_DEBIAN_PACKAGE_DEPENDS "pkg-config, build-essential, debhelper (>=9), cmake (>= 3.10.2), libusb-1.0-0-dev (>= 1.0.21)") set(CPACK_DEBIAN_PACKAGE_MAINTAINER "Nightwalker-87 ") # CPACK_DEBIAN_PACKAGE_DESCRIPTION --> Default: CPACK_DEBIAN_PACKAGE_DESCRIPTION (as it is set) # CPACK_DEBIAN_PACKAGE_SECTION --> Default: “devel” diff --git a/cmake/packaging/deb/control b/cmake/packaging/deb/control index ef51a6cea..7c8d13e47 100644 --- a/cmake/packaging/deb/control +++ b/cmake/packaging/deb/control @@ -1,7 +1,7 @@ Source: stlink Priority: optional Maintainer: Nightwalker-87 -Build-Depends: cmake, dh-cmake, debhelper (>= 9), libusb-1.0-0-dev, libgtk-3-dev +Build-Depends: cmake (>= 3.10.2), dh-cmake, debhelper (>= 9), libusb-1.0-0-dev (>= 1.0.21), libgtk-3-dev (>= 3.22.30) Standards-Version: 4.5.0 Rules-Requires-Root: no Section: electronics diff --git a/contributors.txt b/contributors.txt index bcaa0b538..cffef89f6 100644 --- a/contributors.txt +++ b/contributors.txt @@ -7,6 +7,8 @@ Andrea Mucignat Andrew Andrianov [necromant] Andrey Yurovsky Andy Isaacson +Andreas Sandberg [andysan] +Antoine Faure [antoinefaure] Anton [Ant-ON] Áron Radics A. Sheaff @@ -24,6 +26,7 @@ Chris Samuelson Christian Deussen [nullsub] Christophe Levantis Craig Lilley +Crest [Crest] Dan Dev Dan Hepler Daniel Campoverde [alx741] diff --git a/doc/compiling.md b/doc/compiling.md index eef207f95..0931c278a 100644 --- a/doc/compiling.md +++ b/doc/compiling.md @@ -7,7 +7,7 @@ On Windows users should ensure that the following software is installed: - `git` (_optional, but recommended_) -- `cmake` (3.17.0 or later) +- `cmake` - `MinGW-w64` (7.0.0 or later) with GCC toolchain 8.1.0 ### Installation @@ -95,7 +95,7 @@ Install the following packages from your package repository: - `git` - `gcc` or `clang` or `mingw32-gcc` or `mingw64-gcc` (C-compiler; very likely gcc is already present) - `build-essential` (on Debian based distros (Debian, Ubuntu)) -- `cmake` (3.4.2 or later, use the latest version available from the repository) +- `cmake` - `rpm` (on Debian based distros (Debian, Ubuntu), needed for package build with `make package`) - `libusb-1.0` - `libusb-1.0-0-dev` (development headers for building) diff --git a/doc/version_support.md b/doc/version_support.md index 2c5df7461..d7ba5c102 100644 --- a/doc/version_support.md +++ b/doc/version_support.md @@ -1,97 +1,104 @@ -_Source:_ pkgs.org - [libusb](https://pkgs.org/search/?q=libusb); [cmake](https://pkgs.org/search/?q=cmake); [gtk](https://pkgs.org/search/?q=gtk) (as of May 2021) +_Source:_ [pkgs.org](https://pkgs.org/search) - libusb, cmake, gtk, libgtk) (as of Jan 2022) ## Supported Operating Systems ### Microsoft Windows -On Windows users should ensure that cmake 3.20.2 or any later version is installed.
-Up on compiling c-make will **automatically** download and install the latest compatible version of `libusb` (1.0.23 at the time of writing). +On Windows users should ensure that cmake **3.10.2** or any later version is installed.
+Up on compiling c-make will **automatically** download and install the latest compatible version of `libusb`. - Windows 10 - Windows 8.1 ### Apple macOS -| Package Repository | libusb
version | cmake
version | gtk-3
version | Supported macOS versions | -| ------------------ | ------------------- | ------------------ | ------------------ | ------------------------ | -| homebrew | 1.0.24 | 3.20.2 | 3.24.29
gtk+3 | 10.9 - 11.x | -| MacPorts | 1.0.24 | 3.20.2 | 3.24.29
gtk3 | 10.4 - 11.x | +| Package Repository | libusb | cmake | gtk-3-dev | Supported macOS versions | +| ------------------ | ------ | ------ | ------------------ | ------------------------ | +| homebrew | 1.0.24 | 3.22.1 | 3.24.30
gtk+3 | **10.10 - 12.x** | +| MacPorts | 1.0.24 | 3.22.1 | 3.24.31
gtk3 | **10.4 - 12.x** | -NOTE: In order to use a STLINK/V1 programmer on macOS, versions 10.14 or 10.15 are required. +NOTE: In order to use a STLINK/V1 programmer on macOS, version 10.15 is required. ### Linux-/Unix-based: -| Operating System | libusb | cmake | gtk-3 | Notes | -| ------------------------- | -------------------------------- | --------- | ----------- | ------------------------ | -| Debian Sid | 1.0.24 | 3.18.4 | 3.24.24 | | -| Debian 11 (Bullseye) | 1.0.24 | 3.18.4 | 3.24.24 | | -| Debian 10 (Buster) | 1.0.**22** | 3.13.4 | 3.24.**5** | | -| Debian 9 (Stretch) | 1.0.**21** | **3.7.2** | **3.22.11** | End of Support: Jun 2022 | -| | | | | | -| Ubuntu 21.04 (Hirsute) | 1.0.24 | 3.18.4 | 3.24.25 | End of Support: Jan 2022 | -| Ubuntu 20.04 LTS (Focal) | 1.0.23 | 3.16.3 | 3.24.**18** | | -| Ubuntu 18.04 LTS (Bionic) | 1.0.**21** | 3.10.2 | **3.22.30** | End of Support: Apr 2023 | -| | | | | | -| Fedora Rawhide [x64] | 1.0.24 (`libusbx`) | 3.20.2 | 3.24.29 | | -| Fedora 34 [x64] | 1.0.24 (`libusbx`) | 3.19.7 | 3.24.28 | | -| Fedora 33 [x64] | 1.0.23 (`libusbx`) | 3.18.3 | 3.24.23 | | -| | | | | | -| openSUSE Tumbleweed [x64] | 1.0.24 | 3.20.1 | 3.24.29 | | -| openSUSE Leap 15.3 [x64] | 1.0.**21** | 3.17.0 | 3.24.20 | | -| openSUSE Leap 15.2 [x64] | 1.0.**21** | 3.17.0 | 3.24.**14** | End of Support: Dec 2021 | -| | | | | | -| Alpine 3.14 | 1.0.24 | 3.20.3 | 4.2.1 | | -| Alpine 3.13 | 1.0.24 | 3.18.4 | 3.24.23 | End of Support: Nov 2022 | -| Alpine 3.12 | 1.0.23 | 3.17.2 | 3.24.22 | End of Support: May 2022 | -| Alpine 3.11 | 1.0.23 | 3.15.5 | 3.24.**13** | End of Support: Nov 2021 | -| | | | | | -| FreeBSD 13.x | 1.0.**16 - 18** (API 0x01000102) | 3.20.2 | 3.24.27 | | -| FreeBSD 12.x | 1.0.**16 - 18** (API 0x01000102) | 3.19.6 | 3.24.27 | | -| FreeBSD 11.x | 1.0.**16 - 18** (API 0x01000102) | 3.15.5 | 3.24.27 | End of Support: Sep 2021 | -| | | | | | -| Arch Linux | 1.0.24 | 3.20.2 | 3.24.29 | | -| KaOS [x64] | 1.0.24 | 3.20.2 | 3.24.29 | | -| Mageia Cauldron | 1.0.24 | 3.20.2 | 3.24.29 | | -| OpenMandriva Cooker | 1.0.24 | 3.20.2 | 3.24.29 | | -| PCLinuxOS [x64] | 1.0.24 | 3.20.2 | 3.24.29 | | -| Slackware Current | 1.0.24 | 3.20.2 | 3.24.28 | | -| Solus [x64] | 1.0.24 | 3.20.2 | 3.24.29 | | -| ALT Linux Sisyphus | 1.0.24 | 3.19.7 | 3.24.29 | | -| NetBSD 9.x | 1.0.24 | 3.19.7 | 3.24.27 | | -| NetBSD 8.x | 1.0.24 | 3.19.7 | 3.24.27 | | -| OpenMandriva Lx 4.2 | 1.0.24 | 3.19.3 | 3.24.24 | | -| Mageia 8 | 1.0.24 | 3.19.2 | 3.24.24 | End of Support: Aug 2022 | -| CentOS 8 Stream [x64] | 1.0.23 (`libusbx`) | 3.18.2 | **3.22.30** | | -| Adélie 1.0 | 1.0.23 | 3.16.4 | 3.24.23 | | -| ALT Linux P9 | 1.0.**22** | 3.16.3 | 3.24.**11** | | -| AlmaLinux 8 | 1.0.23 (`libusbx`) | 3.11.4 | 3.24.32 | | -| CentOS 8 [x64] | 1.0.23 (`libusbx`) | 3.11.4 | **3.22.30** | End of Support: Dec 2021 | +| Operating System | libusb | cmake | libgtk-dev | Notes | +| ------------------------- | ------------------------------ | ---------- | ----------- | ------------------------ | +| Debian Sid | 1.0.24 | 3.22.1 | 3.24.31 | | +| Debian 11 (Bullseye) | 1.0.24 | 3.18.4 | 3.24.24 | | +| Debian 10 (Buster) | 1.0.**22** | **3.13.4** | 3.24.**5** | | +| | | | | | +| Ubuntu 20.04 LTS (Focal) | 1.0.23 | 3.16.3 | 3.24.**18** | | +| Ubuntu 18.04 LTS (Bionic) | 1.0.**21** | **3.10.2** | 3.**22.30** | End of Support: Apr 2023 | +| | | | | | +| Fedora Rawhide [x64] | 1.0.24 | 3.22.3 | 3.24.31 | | +| Fedora 35 [x64] | 1.0.24 | 3.21.3 | 3.24.30 | | +| Fedora 34 [x64] | 1.0.24 (`libusbx`) | 3.19.7 | 3.24.28 | | +| | | | | | +| openSUSE Tumbleweed [x64] | 1.0.24 | 3.22.1 | 3.24.31 | | +| openSUSE Leap 15.3 [x64] | 1.0.**21** | 3.17.0 | 3.24.20 | End of Support: Dec 2022 | +| | | | | | +| Alpine 3.15 | 1.0.24 | 3.21.3 | 3.24.30 | | +| Alpine 3.14 | 1.0.24 | 3.20.3 | 3.24.28 | | +| Alpine 3.13 | 1.0.24 | 3.18.4 | 3.24.23 | End of Support: Nov 2022 | +| Alpine 3.12 | 1.0.23 | 3.17.2 | 3.24.22 | End of Support: May 2022 | +| | | | | | +| FreeBSD 13.x | 1.0.**16-18** (API 0x01000102) | 3.22.1 | 3.24.31 | | +| FreeBSD 12.x | 1.0.**16-18** (API 0x01000102) | 3.22.1 | 3.24.31 | | +| | | | | | +| NetBSD 9.x | 1.0.24 | 3.21.2 | 3.24.30 | | +| NetBSD 8.x | 1.0.24 | 3.19.7 | 3.24.27 | | +| | | | | | +| CentOS 9 Stream [x64] | 1.0.24 (`libusbx`) | 3.20.3 | 3.24.30 | | +| CentOS 8 Stream [x64] | 1.0.23 (`libusbx`) | 3.20.2 | 3.**22.30** | | +| | | | | | +| ALT Linux Sisyphus | 1.0.24 | 3.22.1 | 3.24.31 | | +| ALT Linux P10 | 1.0.24 | 3.20.5 | 3.24.31 | | +| ALT Linux P9 | 1.0.**22** | 3.16.3 | 3.24.29 | | +| | | | | | +| OpenMandriva Rolling | 1.0.24 | 3.22.1 | 3.24.31 | | +| OpenMandriva Cooker | 1.0.24 | 3.22.1 | 3.24.31 | | +| OpenMandriva Lx 4.2 | 1.0.24 | 3.19.3 | 3.24.24 | | +| | | | | | +| Arch Linux | 1.0.24 | 3.22.1 | - | | +| KaOS [x64] | 1.0.24 | 3.22.1 | 3.24.31 | | +| Mageia Cauldron | 1.0.24 | 3.22.1 | 3.24.31 | | +| PCLinuxOS [x64] | ? | 3.22.1 | 3.24.31 | | +| Solus [x64] | 1.0.24 | 3.22.1 | 3.24.30 | | +| Void Linux | 1.0.24 | 3.22.1 | 3.24.31 | | +| Slackware Current | 1.0.24 | 3.21.4 | 3.24.31 | | +| AlmaLinux 8 | 1.0.23 (`libusbx`) | 3.20.2 | 3.**22.30** | | +| Rocky Linux 8 [x64] | 1.0.23 | 3.20.2 | 3.**22.30** | | +| Mageia 8 | 1.0.24 | 3.19.2 | 3.24.24 | End of Support: Aug 2022 | +| Adélie 1.0 | 1.0.23 | 3.16.4 | 3.24.23 | | ## Unsupported Operating Systems (as of Release v1.7.1) Systems with highlighted versions remain compatible with this toolset. -| Operating System | libusb | cmake | End of
OS-Support | -| ------------------------- | ---------------------- | ---------- | ---------------------- | -| Fedora 32 [x64] | **1.0.23** (`libusbx`) | **3.17.0** | May 2021 | -| Ubuntu 20.10 (Groovy) | **1.0.23** | **3.16.3** | Jul 2021 | -| NetBSD 7.x | **1.0.22** | **3.16.1** | Jun 2020 | -| Alpine 3.10 | **1.0.22** | **3.14.5** | May 2021 | -| Fedora 31 [x64] | **1.0.22** (`libusbx`) | **3.14.5** | Nov 2020 | -| Mageia 7.1 | **1.0.22** | **3.14.3** | Jun 2021 | -| Fedora 30 | **1.0.22** (`libusbx`) | **3.14.2** | May 2020 | -| Ubuntu 19.10 (Eoan) | **1.0.23** | **3.13.4** | Jul 2020 | -| Alpine 3.9 | **1.0.22** | **3.13.0** | Jan 2021 | -| openSUSE Leap 15.1 [x64] | **1.0.21** | **3.10.2** | Jan 2021 | -| Slackware 14.2 | 1.0.20 | 3.5.2 | | -| Ubuntu 16.04 LTS (Xenial) | 1.0.20 | 3.5.1 | Apr 2021 | -| OpenMandriva Lx 3.0x | 1.0.20 | 3.4.2 | | -| Debian 8 (Jessie) | 1.0.19 | 3.0.2 | Jun 2020 | -| CentOS 7 [x64] | 1.0.21 (`libusbx`) | 2.8.12.2 | Jun 2024 | -| Ubuntu 14.04 LTS (Trusty) | 1.0.17 | 2.8.12.2 | Apr 2019 | -| CentOS 6 | 1.0.9 (`libusbx`) | 2.8.12.2 | Nov 2020 | -| Slackware 14.1 | 1.0.9 | 2.8.12 | | -| Slackware 14.0 | 1.0.9 | 2.8.8 | | +| Operating System | libusb | cmake | End of
OS-Support | +| ------------------------ | ------------------------------ | ---------- | ---------------------- | +| CentOS 8 [x64] | 1.0.**23** (`libusbx`) | 3.**20.3** | Dec 2021 | +| Ubuntu 21.04 (Hirsute) | 1.0.**24** | 3.**18.4** | Jan 2022 | +| Fedora 33 [x64] | 1.0.**23** (`libusbx`) | 3.**18.3** | Nov 2021 | +| Fedora 32 [x64] | 1.0.**23** (`libusbx`) | 3.**17.0** | May 2021 | +| openSUSE Leap 15.2 [x64] | 1.0.**21** | 3.**17.0** | Dec 2021 | +| Ubuntu 20.10 (Groovy) | 1.0.**23** | 3.**16.3** | Jul 2021 | +| NetBSD 7.x | 1.0.**22** | 3.**16.1** | Jun 2020 | +| Alpine 3.11 | 1.0.**23** | 3.**15.5** | Nov 2021 | +| FreeBSD 11.x | 1.0.**16-18** (API 0x01000102) | 3.**15.5** | Sep 2021 | +| Alpine 3.10 | 1.0.**22** | 3.**14.5** | May 2021 | +| Fedora 31 [x64] | 1.0.**22**(`libusbx`) | 3.**14.5** | Nov 2020 | +| Mageia 7.1 | 1.0.**22** | 3.**14.3** | Jun 2021 | +| Fedora 30 | 1.0.**22**(`libusbx`) | 3.**14.2** | May 2020 | +| Ubuntu 19.10 (Eoan) | 1.0.**23** | 3.**13.4** | Jul 2020 | +| Alpine 3.9 | 1.0.**22** | 3.**13.0** | Jan 2021 | +| openSUSE Leap 15.1 [x64] | 1.0.**21** | 3.**10.2** | Jan 2021 | +| Debian 9 (Stretch) | 1.0.**21** | 3.7.2 | Jun 2022 | +| Slackware 14.2 | 1.0.20 | 3.5.2 | | +| OpenMandriva Lx 3.0x | 1.0.20 | 3.4.2 | | +| CentOS 7 [x64] | 1.0.**21** (`libusbx`) | 2.8.12.2 | Jun 2024 | +| Slackware 14.1 | 1.0.9 | 2.8.12 | | +| Slackware 14.0 | 1.0.9 | 2.8.8 | | _All other operating systems which are not listed are unsupported._ diff --git a/inc/stlink.h b/inc/stlink.h index 7dfd8a71e..17601fda8 100644 --- a/inc/stlink.h +++ b/inc/stlink.h @@ -1,6 +1,7 @@ /* * File: stlink.h + * * This should contain all the common top level stlink interfaces, * regardless of how the backend does the work.... */ @@ -184,7 +185,7 @@ enum run_type { typedef struct _stlink stlink_t; -#include // Is it really need? +#include #include struct _stlink { diff --git a/inc/stm32.h b/inc/stm32.h index 19ba3fca0..473f65a56 100644 --- a/inc/stm32.h +++ b/inc/stm32.h @@ -149,11 +149,11 @@ enum stm32_chipids { /* ============ */ /* Constant STM32 memory address */ -#define STM32_SRAM_BASE ((uint32_t)0x20000000) -#define STM32_FLASH_BASE ((uint32_t)0x08000000) +#define STM32_SRAM_BASE ((uint32_t)0x20000000) +#define STM32_FLASH_BASE ((uint32_t)0x08000000) -#define STM32_F1_FLASH_BANK2_BASE ((uint32_t)0x08080000) -#define STM32_H7_FLASH_BANK2_BASE ((uint32_t)0x08100000) +#define STM32_F1_FLASH_BANK2_BASE ((uint32_t)0x08080000) +#define STM32_H7_FLASH_BANK2_BASE ((uint32_t)0x08100000) #define STM32F0_DBGMCU_CR 0xE0042004 #define STM32F0_DBGMCU_CR_IWDG_STOP 8 diff --git a/src/stlink-lib/chipid.h b/src/stlink-lib/chipid.h index f8e1b3444..1eae2cc34 100644 --- a/src/stlink-lib/chipid.h +++ b/src/stlink-lib/chipid.h @@ -4,8 +4,7 @@ #include #include - -/** Chipid parameters */ +/* Chipid parametres */ struct stlink_chipid_params { char *dev_type; char *ref_manual_id; diff --git a/src/stlink-lib/usb.c.bak b/src/stlink-lib/usb.c.bak deleted file mode 100644 index 32ceff71f..000000000 --- a/src/stlink-lib/usb.c.bak +++ /dev/null @@ -1,1410 +0,0 @@ -#include -#include -#include -#include -#include - -#if !defined(_MSC_VER) -#include -#endif - -#include -#include -#include - -#if defined(_WIN32) -#include -#endif - -#include -#include -#include "usb.h" - -enum SCSI_Generic_Direction {SG_DXFER_TO_DEV = 0, SG_DXFER_FROM_DEV = 0x80}; - -static inline uint32_t le_to_h_u32(const uint8_t* buf) { - return((uint32_t)((uint32_t)buf[0] | (uint32_t)buf[1] << 8 | (uint32_t)buf[2] << 16 | (uint32_t)buf[3] << 24)); -} - -static int _stlink_match_speed_map(const uint32_t *map, unsigned int map_size, uint32_t khz) { - unsigned int i; - int speed_index = -1; - int speed_diff = INT_MAX; - int last_valid_speed = -1; - bool match = true; - - for (i = 0; i < map_size; i++) { - if (!map[i]) { continue; } - - last_valid_speed = i; - - if (khz == map[i]) { - speed_index = i; - break; - } else { - int current_diff = khz - map[i]; - // get abs value for comparison - current_diff = (current_diff > 0) ? current_diff : -current_diff; - - if (current_diff < speed_diff) { - speed_diff = current_diff; - speed_index = i; - } - } - } - - if (speed_index == -1) { - // This will only be here if we cannot match the slow speed. - // Use the slowest speed we support. - speed_index = last_valid_speed; - match = false; - } else if (i == map_size) { - match = false; - } - - if (!match) { - ILOG("Unable to match requested speed %d kHz, using %d kHz\n", khz, map[speed_index]); - } - - return(speed_index); -} - -void _stlink_usb_close(stlink_t* sl) { - if (!sl) { return; } - - struct stlink_libusb * const handle = sl->backend_data; - - // maybe we couldn't even get the usb device? - if (handle != NULL) { - if (handle->usb_handle != NULL) { libusb_close(handle->usb_handle); } - - libusb_exit(handle->libusb_ctx); - free(handle); - } -} - -ssize_t send_recv(struct stlink_libusb* handle, int terminate, - unsigned char* txbuf, size_t txsize, unsigned char* rxbuf, - size_t rxsize, int check_error, const char *cmd) { - // Note: txbuf and rxbuf can point to the same area - int res, t, retry = 0; - - while (1) { - res = 0; - t = libusb_bulk_transfer(handle->usb_handle, handle->ep_req, txbuf, (int)txsize, &res, 3000); - - if (t) { - ELOG("%s send request failed: %s\n", cmd, libusb_error_name(t)); - return(-1); - } else if ((size_t)res != txsize) { - ELOG("%s send request wrote %u bytes, instead of %u\n", - cmd, (unsigned int)res, (unsigned int)txsize); - } - - if (rxsize != 0) { - t = libusb_bulk_transfer(handle->usb_handle, handle->ep_rep, rxbuf, (int)rxsize, &res, 3000); - - if (t) { - ELOG("%s read reply failed: %s\n", cmd, libusb_error_name(t)); - return(-1); - } - - /* Checking the command execution status stored in the first byte of the response */ - if (handle->protocoll != 1 && check_error >= CMD_CHECK_STATUS && - rxbuf[0] != STLINK_DEBUG_ERR_OK) { - switch(rxbuf[0]) { - case STLINK_DEBUG_ERR_AP_WAIT: - case STLINK_DEBUG_ERR_DP_WAIT: - if (check_error == CMD_CHECK_RETRY && retry < 3) { - unsigned int delay_us = (1<protocoll == 1) && terminate) { - // read the SG reply - unsigned char sg_buf[13]; - t = libusb_bulk_transfer(handle->usb_handle, handle->ep_rep, sg_buf, 13, &res, 3000); - - if (t) { - ELOG("%s read storage failed: %s\n", cmd, libusb_error_name(t)); - return(-1); - } - - // The STLink doesn't seem to evaluate the sequence number. - handle->sg_transfer_idx++; - } - - return(res); - } -} - -static inline int send_only(struct stlink_libusb* handle, int terminate, - unsigned char* txbuf, size_t txsize, - const char *cmd) { - return((int)send_recv(handle, terminate, txbuf, txsize, NULL, 0, CMD_CHECK_NO, cmd)); -} - - -static int fill_command(stlink_t * sl, enum SCSI_Generic_Direction dir, uint32_t len) { - struct stlink_libusb * const slu = sl->backend_data; - unsigned char* const cmd = sl->c_buf; - int i = 0; - memset(cmd, 0, sizeof(sl->c_buf)); - - if (slu->protocoll == 1) { - cmd[i++] = 'U'; - cmd[i++] = 'S'; - cmd[i++] = 'B'; - cmd[i++] = 'C'; - write_uint32(&cmd[i], slu->sg_transfer_idx); - write_uint32(&cmd[i + 4], len); - i += 8; - cmd[i++] = (dir == SG_DXFER_FROM_DEV) ? 0x80 : 0; - cmd[i++] = 0; // logical unit - cmd[i++] = 0xa; // command length - } - return(i); -} - -int _stlink_usb_version(stlink_t *sl) { - struct stlink_libusb * const slu = sl->backend_data; - unsigned char* const data = sl->q_buf; - unsigned char* const cmd = sl->c_buf; - ssize_t size; - uint32_t rep_len; - int i; - - if (sl->version.stlink_v == 3) { - // STLINK-V3 version is determined by another command - rep_len = 12; - i = fill_command(sl, SG_DXFER_FROM_DEV, 16); - cmd[i++] = STLINK_GET_VERSION_APIV3; - } else { - rep_len = 6; - i = fill_command(sl, SG_DXFER_FROM_DEV, 6); - cmd[i++] = STLINK_GET_VERSION; - } - - size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_REP_LEN, "GET_VERSION"); - - return(size<0?-1:0); -} - -int32_t _stlink_usb_target_voltage(stlink_t *sl) { - struct stlink_libusb * const slu = sl->backend_data; - unsigned char* const rdata = sl->q_buf; - unsigned char* const cmd = sl->c_buf; - ssize_t size; - uint32_t rep_len = 8; - int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); - uint32_t factor, reading; - int voltage; - - cmd[i++] = STLINK_GET_TARGET_VOLTAGE; - - size = send_recv(slu, 1, cmd, slu->cmd_len, rdata, rep_len, CMD_CHECK_REP_LEN, "GET_TARGET_VOLTAGE"); - - if (size < 0) { - return(-1); - } - - factor = (rdata[3] << 24) | (rdata[2] << 16) | (rdata[1] << 8) | (rdata[0] << 0); - reading = (rdata[7] << 24) | (rdata[6] << 16) | (rdata[5] << 8) | (rdata[4] << 0); - voltage = 2400 * reading / factor; - - return(voltage); -} - -int _stlink_usb_read_debug32(stlink_t *sl, uint32_t addr, uint32_t *data) { - struct stlink_libusb * const slu = sl->backend_data; - unsigned char* const rdata = sl->q_buf; - unsigned char* const cmd = sl->c_buf; - ssize_t size; - const int rep_len = 8; - - int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); - cmd[i++] = STLINK_DEBUG_COMMAND; - cmd[i++] = STLINK_DEBUG_APIV2_READDEBUGREG; - write_uint32(&cmd[i], addr); - size = send_recv(slu, 1, cmd, slu->cmd_len, rdata, rep_len, CMD_CHECK_RETRY, "READDEBUGREG"); - - if (size < 0) { - return(-1); - } - - *data = read_uint32(rdata, 4); - - return(0); -} - -int _stlink_usb_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data) { - struct stlink_libusb * const slu = sl->backend_data; - unsigned char* const rdata = sl->q_buf; - unsigned char* const cmd = sl->c_buf; - ssize_t size; - const int rep_len = 2; - - int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); - cmd[i++] = STLINK_DEBUG_COMMAND; - cmd[i++] = STLINK_DEBUG_APIV2_WRITEDEBUGREG; - write_uint32(&cmd[i], addr); - write_uint32(&cmd[i + 4], data); - size = send_recv(slu, 1, cmd, slu->cmd_len, rdata, rep_len, CMD_CHECK_RETRY, "WRITEDEBUGREG"); - - return(size<0?-1:0); -} - -int _stlink_usb_get_rw_status(stlink_t *sl) { - if (sl->version.jtag_api == STLINK_JTAG_API_V1) { return(0); } - - unsigned char* const rdata = sl->q_buf; - struct stlink_libusb * const slu = sl->backend_data; - unsigned char* const cmd = sl->c_buf; - int i; - int16_t ret = 0; - - i = fill_command(sl, SG_DXFER_FROM_DEV, 12); - cmd[i++] = STLINK_DEBUG_COMMAND; - - if (sl->version.flags & STLINK_F_HAS_GETLASTRWSTATUS2) { - cmd[i++] = STLINK_DEBUG_APIV2_GETLASTRWSTATUS2; - ret = send_recv(slu, 1, cmd, slu->cmd_len, rdata, 12, CMD_CHECK_STATUS, "GETLASTRWSTATUS2"); - } else { - cmd[i++] = STLINK_DEBUG_APIV2_GETLASTRWSTATUS; - ret = send_recv(slu, 1, cmd, slu->cmd_len, rdata, 2, CMD_CHECK_STATUS, "GETLASTRWSTATUS"); - } - - return(ret<0?-1:0); -} - -int _stlink_usb_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { - struct stlink_libusb * const slu = sl->backend_data; - unsigned char* const data = sl->q_buf; - unsigned char* const cmd = sl->c_buf; - int i, ret; - - i = fill_command(sl, SG_DXFER_TO_DEV, len); - cmd[i++] = STLINK_DEBUG_COMMAND; - cmd[i++] = STLINK_DEBUG_WRITEMEM_32BIT; - write_uint32(&cmd[i], addr); - write_uint16(&cmd[i + 4], len); - ret = send_only(slu, 0, cmd, slu->cmd_len, "WRITEMEM_32BIT"); - - if (ret == -1) { return(ret); } - - ret = send_only(slu, 1, data, len, "WRITEMEM_32BIT"); - - if (ret == -1) { return(ret); } - - return(_stlink_usb_get_rw_status(sl)); -} - -int _stlink_usb_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len) { - struct stlink_libusb * const slu = sl->backend_data; - unsigned char* const data = sl->q_buf; - unsigned char* const cmd = sl->c_buf; - int i, ret; - - if ((sl->version.jtag_api < STLINK_JTAG_API_V3 && len > 64) || - (sl->version.jtag_api >= STLINK_JTAG_API_V3 && len > 512)) { - ELOG("WRITEMEM_8BIT: bulk packet limits exceeded (data len %d byte)\n", len); - return (-1); - } - - i = fill_command(sl, SG_DXFER_TO_DEV, 0); - cmd[i++] = STLINK_DEBUG_COMMAND; - cmd[i++] = STLINK_DEBUG_WRITEMEM_8BIT; - write_uint32(&cmd[i], addr); - write_uint16(&cmd[i + 4], len); - ret = send_only(slu, 0, cmd, slu->cmd_len, "WRITEMEM_8BIT"); - - if (ret == -1) { return(ret); } - - ret = send_only(slu, 1, data, len, "WRITEMEM_8BIT"); - - if (ret == -1) { return(ret); } - - return(0); -} - - -int _stlink_usb_current_mode(stlink_t * sl) { - struct stlink_libusb * const slu = sl->backend_data; - unsigned char* const cmd = sl->c_buf; - unsigned char* const data = sl->q_buf; - ssize_t size; - int rep_len = 2; - int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); - - cmd[i++] = STLINK_GET_CURRENT_MODE; - size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_NO, "GET_CURRENT_MODE"); - - if (size < 0) { - return(-1); - } - - return(sl->q_buf[0]); -} - -int _stlink_usb_core_id(stlink_t * sl) { - struct stlink_libusb * const slu = sl->backend_data; - unsigned char* const cmd = sl->c_buf; - unsigned char* const data = sl->q_buf; - ssize_t size; - int offset, rep_len = sl->version.jtag_api == STLINK_JTAG_API_V1 ? 4 : 12; - int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); - - cmd[i++] = STLINK_DEBUG_COMMAND; - - if (sl->version.jtag_api == STLINK_JTAG_API_V1) { - cmd[i++] = STLINK_DEBUG_READCOREID; - offset = 0; - } else { - cmd[i++] = STLINK_DEBUG_APIV2_READ_IDCODES; - offset = 4; - } - - size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_STATUS, "READ_IDCODES"); - - if (size < 0) { - return(-1); - } - - sl->core_id = read_uint32(data, offset); - - return(0); -} - -int _stlink_usb_status_v2(stlink_t *sl) { - int result; - uint32_t status = 0; - - result = _stlink_usb_read_debug32(sl, STLINK_REG_DHCSR, &status); - DLOG("core status: %08X\n", status); - - if (result != 0) { - sl->core_stat = TARGET_UNKNOWN; - } else { - if (status & STLINK_REG_DHCSR_C_HALT) { - sl->core_stat = TARGET_HALTED; - } else if (status & STLINK_REG_DHCSR_S_RESET_ST) { - sl->core_stat = TARGET_RESET; - } else { - sl->core_stat = TARGET_RUNNING; - } - } - - return(result); -} - -int _stlink_usb_status(stlink_t * sl) { - if (sl->version.jtag_api != STLINK_JTAG_API_V1) { return(_stlink_usb_status_v2(sl)); } - - struct stlink_libusb * const slu = sl->backend_data; - unsigned char* const data = sl->q_buf; - unsigned char* const cmd = sl->c_buf; - ssize_t size; - int rep_len = 2; - int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); - - cmd[i++] = STLINK_DEBUG_COMMAND; - cmd[i++] = STLINK_DEBUG_GETSTATUS; - size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_NO, "GETSTATUS"); - - if (size > 1) { - if (sl->q_buf[0] == STLINK_CORE_RUNNING) { - sl->core_stat = TARGET_RUNNING; - } else if (sl->q_buf[0] == STLINK_CORE_HALTED) { - sl->core_stat = TARGET_HALTED; - } else { - sl->core_stat = TARGET_UNKNOWN; - } - } else { - sl->core_stat = TARGET_UNKNOWN; - } - - return(size<0?-1:0); -} - -int _stlink_usb_force_debug(stlink_t *sl) { - struct stlink_libusb *slu = sl->backend_data; - - int res; - - if (sl->version.jtag_api != STLINK_JTAG_API_V1) { - res = _stlink_usb_write_debug32(sl, STLINK_REG_DHCSR, STLINK_REG_DHCSR_DBGKEY | STLINK_REG_DHCSR_C_HALT | STLINK_REG_DHCSR_C_DEBUGEN); - return(res); - } - - unsigned char* const data = sl->q_buf; - unsigned char* const cmd = sl->c_buf; - ssize_t size; - int rep_len = 2; - int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); - - cmd[i++] = STLINK_DEBUG_COMMAND; - cmd[i++] = STLINK_DEBUG_FORCEDEBUG; - size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_RETRY, "FORCEDEBUG"); - - return(size<0?-1:0); -} - -int _stlink_usb_enter_swd_mode(stlink_t * sl) { - struct stlink_libusb * const slu = sl->backend_data; - unsigned char* const cmd = sl->c_buf; - ssize_t size; - unsigned char* const data = sl->q_buf; - const uint32_t rep_len = sl->version.jtag_api == STLINK_JTAG_API_V1 ? 0 : 2; - int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); - - cmd[i++] = STLINK_DEBUG_COMMAND; - // select correct API-Version for entering SWD mode: V1 API (0x20) or V2 API (0x30). - cmd[i++] = sl->version.jtag_api == STLINK_JTAG_API_V1 ? STLINK_DEBUG_APIV1_ENTER : STLINK_DEBUG_APIV2_ENTER; - cmd[i++] = STLINK_DEBUG_ENTER_SWD; - size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_RETRY, "ENTER_SWD"); - - return(size<0?-1:0); -} - -int _stlink_usb_exit_dfu_mode(stlink_t* sl) { - struct stlink_libusb * const slu = sl->backend_data; - unsigned char* const cmd = sl->c_buf; - ssize_t size; - int i = fill_command(sl, SG_DXFER_FROM_DEV, 0); - - cmd[i++] = STLINK_DFU_COMMAND; - cmd[i++] = STLINK_DFU_EXIT; - size = send_only(slu, 1, cmd, slu->cmd_len, "DFU_EXIT"); - - return(size<0?-1:0); -} - - -int _stlink_usb_reset(stlink_t * sl) { - struct stlink_libusb * const slu = sl->backend_data; - unsigned char* const data = sl->q_buf; - unsigned char* const cmd = sl->c_buf; - ssize_t size; - int i, rep_len = 2; - - // send reset command - i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); - cmd[i++] = STLINK_DEBUG_COMMAND; - - if (sl->version.jtag_api == STLINK_JTAG_API_V1) { - cmd[i++] = STLINK_DEBUG_APIV1_RESETSYS; - } else { - cmd[i++] = STLINK_DEBUG_APIV2_RESETSYS; - } - - size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_RETRY, "RESETSYS"); - - return(size<0?-1:0); -} - -int _stlink_usb_jtag_reset(stlink_t * sl, int value) { - struct stlink_libusb * const slu = sl->backend_data; - unsigned char* const data = sl->q_buf; - unsigned char* const cmd = sl->c_buf; - ssize_t size; - int rep_len = 2; - int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); - - cmd[i++] = STLINK_DEBUG_COMMAND; - cmd[i++] = STLINK_DEBUG_APIV2_DRIVE_NRST; - cmd[i++] = value; - size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_RETRY, "DRIVE_NRST"); - - return(size<0?-1:0); -} - - -int _stlink_usb_step(stlink_t* sl) { - struct stlink_libusb * const slu = sl->backend_data; - - if (sl->version.jtag_api != STLINK_JTAG_API_V1) { - // emulates the JTAG v1 API by using DHCSR - _stlink_usb_write_debug32(sl, STLINK_REG_DHCSR, STLINK_REG_DHCSR_DBGKEY | STLINK_REG_DHCSR_C_HALT | - STLINK_REG_DHCSR_C_MASKINTS | STLINK_REG_DHCSR_C_DEBUGEN); - _stlink_usb_write_debug32(sl, STLINK_REG_DHCSR, STLINK_REG_DHCSR_DBGKEY | STLINK_REG_DHCSR_C_STEP | - STLINK_REG_DHCSR_C_MASKINTS | STLINK_REG_DHCSR_C_DEBUGEN); - return _stlink_usb_write_debug32(sl, STLINK_REG_DHCSR, STLINK_REG_DHCSR_DBGKEY | STLINK_REG_DHCSR_C_HALT | - STLINK_REG_DHCSR_C_DEBUGEN); - } - - unsigned char* const data = sl->q_buf; - unsigned char* const cmd = sl->c_buf; - ssize_t size; - int rep_len = 2; - int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); - - cmd[i++] = STLINK_DEBUG_COMMAND; - cmd[i++] = STLINK_DEBUG_STEPCORE; - size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_RETRY, "STEPCORE"); - - return(size<0?-1:0); -} - -/** - * This seems to do a good job of restarting things from the beginning? - * @param sl - * @param type - */ -int _stlink_usb_run(stlink_t* sl, enum run_type type) { - struct stlink_libusb * const slu = sl->backend_data; - - int res; - - if (sl->version.jtag_api != STLINK_JTAG_API_V1) { - res = _stlink_usb_write_debug32(sl, STLINK_REG_DHCSR, - STLINK_REG_DHCSR_DBGKEY | STLINK_REG_DHCSR_C_DEBUGEN | - ((type==RUN_FLASH_LOADER)?STLINK_REG_DHCSR_C_MASKINTS:0)); - return(res); - } - - - unsigned char* const data = sl->q_buf; - unsigned char* const cmd = sl->c_buf; - ssize_t size; - int rep_len = 2; - int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); - - cmd[i++] = STLINK_DEBUG_COMMAND; - cmd[i++] = STLINK_DEBUG_RUNCORE; - size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_RETRY, "RUNCORE"); - - return(size<0?-1:0); -} - -int _stlink_usb_set_swdclk(stlink_t* sl, int clk_freq) { - struct stlink_libusb * const slu = sl->backend_data; - unsigned char* const data = sl->q_buf; - unsigned char* const cmd = sl->c_buf; - ssize_t size; - int rep_len = 2; - int i; - - // clock speed only supported by stlink/v2 and for firmware >= 22 - if (sl->version.stlink_v == 2 && sl->version.jtag_v >= 22) { - uint16_t clk_divisor; - if (clk_freq) { - const uint32_t map[] = {5, 15, 25, 50, 100, 125, 240, 480, 950, 1200, 1800, 4000}; - int speed_index = _stlink_match_speed_map(map, STLINK_ARRAY_SIZE(map), clk_freq); - switch (map[speed_index]) { - case 5: clk_divisor = STLINK_SWDCLK_5KHZ_DIVISOR; break; - case 15: clk_divisor = STLINK_SWDCLK_15KHZ_DIVISOR; break; - case 25: clk_divisor = STLINK_SWDCLK_25KHZ_DIVISOR; break; - case 50: clk_divisor = STLINK_SWDCLK_50KHZ_DIVISOR; break; - case 100: clk_divisor = STLINK_SWDCLK_100KHZ_DIVISOR; break; - case 125: clk_divisor = STLINK_SWDCLK_125KHZ_DIVISOR; break; - case 240: clk_divisor = STLINK_SWDCLK_240KHZ_DIVISOR; break; - case 480: clk_divisor = STLINK_SWDCLK_480KHZ_DIVISOR; break; - case 950: clk_divisor = STLINK_SWDCLK_950KHZ_DIVISOR; break; - case 1200: clk_divisor = STLINK_SWDCLK_1P2MHZ_DIVISOR; break; - default: - case 1800: clk_divisor = STLINK_SWDCLK_1P8MHZ_DIVISOR; break; - case 4000: clk_divisor = STLINK_SWDCLK_4MHZ_DIVISOR; break; - } - } else - clk_divisor = STLINK_SWDCLK_1P8MHZ_DIVISOR; - - i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); - - cmd[i++] = STLINK_DEBUG_COMMAND; - cmd[i++] = STLINK_DEBUG_APIV2_SWD_SET_FREQ; - cmd[i++] = clk_divisor & 0xFF; - cmd[i++] = (clk_divisor >> 8) & 0xFF; - size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_RETRY, "SWD_SET_FREQ"); - - return(size<0?-1:0); - } else if (sl->version.stlink_v == 3) { - int speed_index; - uint32_t map[STLINK_V3_MAX_FREQ_NB]; - i = fill_command(sl, SG_DXFER_FROM_DEV, 16); - - cmd[i++] = STLINK_DEBUG_COMMAND; - cmd[i++] = STLINK_DEBUG_APIV3_GET_COM_FREQ; - cmd[i++] = 0; // SWD mode - size = send_recv(slu, 1, cmd, slu->cmd_len, data, 52, CMD_CHECK_STATUS, "GET_COM_FREQ"); - - if (size < 0) { - return(-1); - } - - int speeds_size = data[8]; - if (speeds_size > STLINK_V3_MAX_FREQ_NB) { - speeds_size = STLINK_V3_MAX_FREQ_NB; - } - - for (i = 0; i < speeds_size; i++) map[i] = le_to_h_u32(&data[12 + 4 * i]); - - // Set to zero all the next entries - for (i = speeds_size; i < STLINK_V3_MAX_FREQ_NB; i++) map[i] = 0; - - if (!clk_freq) clk_freq = 1000; // set default frequency - speed_index = _stlink_match_speed_map(map, STLINK_ARRAY_SIZE(map), clk_freq); - - i = fill_command(sl, SG_DXFER_FROM_DEV, 16); - - cmd[i++] = STLINK_DEBUG_COMMAND; - cmd[i++] = STLINK_DEBUG_APIV3_SET_COM_FREQ; - cmd[i++] = 0; // SWD mode - cmd[i++] = 0; - cmd[i++] = (uint8_t)((map[speed_index] >> 0) & 0xFF); - cmd[i++] = (uint8_t)((map[speed_index] >> 8) & 0xFF); - cmd[i++] = (uint8_t)((map[speed_index] >> 16) & 0xFF); - cmd[i++] = (uint8_t)((map[speed_index] >> 24) & 0xFF); - - size = send_recv(slu, 1, cmd, slu->cmd_len, data, 8, CMD_CHECK_STATUS, "SET_COM_FREQ"); - - return(size<0?-1:0); - } else if (clk_freq) { - WLOG("ST-Link firmware does not support frequency setup\n"); - } - - return(-1); -} - -int _stlink_usb_exit_debug_mode(stlink_t *sl) { - struct stlink_libusb * const slu = sl->backend_data; - unsigned char* const cmd = sl->c_buf; - ssize_t size; - int i = fill_command(sl, SG_DXFER_FROM_DEV, 0); - - cmd[i++] = STLINK_DEBUG_COMMAND; - cmd[i++] = STLINK_DEBUG_EXIT; - - size = send_only(slu, 1, cmd, slu->cmd_len, "DEBUG_EXIT"); - - return(size<0?-1:0); -} - -int _stlink_usb_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { - struct stlink_libusb * const slu = sl->backend_data; - unsigned char* const data = sl->q_buf; - unsigned char* const cmd = sl->c_buf; - ssize_t size; - int i = fill_command(sl, SG_DXFER_FROM_DEV, len); - - cmd[i++] = STLINK_DEBUG_COMMAND; - cmd[i++] = STLINK_DEBUG_READMEM_32BIT; - write_uint32(&cmd[i], addr); - write_uint16(&cmd[i + 4], len); - size = send_recv(slu, 1, cmd, slu->cmd_len, data, len, CMD_CHECK_NO, "READMEM_32BIT"); - - if (size < 0) { - return(-1); - } - - sl->q_len = (int)size; - stlink_print_data(sl); - - return(0); -} - -int _stlink_usb_read_all_regs(stlink_t *sl, struct stlink_reg *regp) { - struct stlink_libusb * const slu = sl->backend_data; - unsigned char* const cmd = sl->c_buf; - unsigned char* const data = sl->q_buf; - ssize_t size; - uint32_t rep_len = sl->version.jtag_api == STLINK_JTAG_API_V1 ? 84 : 88; - int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); - - cmd[i++] = STLINK_DEBUG_COMMAND; - - if (sl->version.jtag_api == STLINK_JTAG_API_V1) { - cmd[i++] = STLINK_DEBUG_APIV1_READALLREGS; - } else { - cmd[i++] = STLINK_DEBUG_APIV2_READALLREGS; - } - - size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_STATUS, "READALLREGS"); - - if (size < 0) { - return(-1); - } - - /* V1: regs data from offset 0 */ - /* V2: status at offset 0, regs data from offset 4 */ - int reg_offset = sl->version.jtag_api == STLINK_JTAG_API_V1 ? 0 : 4; - sl->q_len = (int)size; - stlink_print_data(sl); - - for (i = 0; i < 16; i++) regp->r[i] = read_uint32(sl->q_buf, reg_offset + i * 4); - - regp->xpsr = read_uint32(sl->q_buf, reg_offset + 64); - regp->main_sp = read_uint32(sl->q_buf, reg_offset + 68); - regp->process_sp = read_uint32(sl->q_buf, reg_offset + 72); - regp->rw = read_uint32(sl->q_buf, reg_offset + 76); - regp->rw2 = read_uint32(sl->q_buf, reg_offset + 80); - - if (sl->verbose < 2) { return(0); } - - DLOG("xpsr = 0x%08x\n", regp->xpsr); - DLOG("main_sp = 0x%08x\n", regp->main_sp); - DLOG("process_sp = 0x%08x\n", regp->process_sp); - DLOG("rw = 0x%08x\n", regp->rw); - DLOG("rw2 = 0x%08x\n", regp->rw2); - - return(0); -} - -int _stlink_usb_read_reg(stlink_t *sl, int r_idx, struct stlink_reg *regp) { - struct stlink_libusb * const slu = sl->backend_data; - unsigned char* const data = sl->q_buf; - unsigned char* const cmd = sl->c_buf; - ssize_t size; - uint32_t r; - uint32_t rep_len = sl->version.jtag_api == STLINK_JTAG_API_V1 ? 4 : 8; - int reg_offset = sl->version.jtag_api == STLINK_JTAG_API_V1 ? 0 : 4; - int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); - - cmd[i++] = STLINK_DEBUG_COMMAND; - - if (sl->version.jtag_api == STLINK_JTAG_API_V1) { - cmd[i++] = STLINK_DEBUG_APIV1_READREG; - } else { - cmd[i++] = STLINK_DEBUG_APIV2_READREG; - } - - cmd[i++] = (uint8_t)r_idx; - size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_RETRY, "READREG"); - - if (size < 0) { - return(-1); - } - - sl->q_len = (int)size; - stlink_print_data(sl); - r = read_uint32(sl->q_buf, reg_offset); - DLOG("r_idx (%2d) = 0x%08x\n", r_idx, r); - - switch (r_idx) { - case 16: - regp->xpsr = r; - break; - case 17: - regp->main_sp = r; - break; - case 18: - regp->process_sp = r; - break; - case 19: - regp->rw = r; // XXX ?(primask, basemask etc.) - break; - case 20: - regp->rw2 = r; // XXX ?(primask, basemask etc.) - break; - default: - regp->r[r_idx] = r; - } - - return(0); -} - -/* See section C1.6 of the ARMv7-M Architecture Reference Manual */ -int _stlink_usb_read_unsupported_reg(stlink_t *sl, int r_idx, struct stlink_reg *regp) { - uint32_t r; - int ret; - - sl->q_buf[0] = (unsigned char)r_idx; - - for (int i = 1; i < 4; i++) sl->q_buf[i] = 0; - - ret = _stlink_usb_write_mem32(sl, STLINK_REG_DCRSR, 4); - - if (ret == -1) { return(ret); } - - ret = _stlink_usb_read_mem32(sl, STLINK_REG_DCRDR, 4); - - if (ret == -1) { return(ret); } - - r = read_uint32(sl->q_buf, 0); - DLOG("r_idx (%2d) = 0x%08x\n", r_idx, r); - - switch (r_idx) { - case 0x14: - regp->primask = (uint8_t)(r & 0xFF); - regp->basepri = (uint8_t)((r >> 8) & 0xFF); - regp->faultmask = (uint8_t)((r >> 16) & 0xFF); - regp->control = (uint8_t)((r >> 24) & 0xFF); - break; - case 0x21: - regp->fpscr = r; - break; - default: - regp->s[r_idx - 0x40] = r; - break; - } - - return(0); -} - -int _stlink_usb_read_all_unsupported_regs(stlink_t *sl, struct stlink_reg *regp) { - int ret; - - ret = _stlink_usb_read_unsupported_reg(sl, 0x14, regp); - - if (ret == -1) { return(ret); } - - ret = _stlink_usb_read_unsupported_reg(sl, 0x21, regp); - - if (ret == -1) { return(ret); } - - for (int i = 0; i < 32; i++) { - ret = _stlink_usb_read_unsupported_reg(sl, 0x40 + i, regp); - - if (ret == -1) { return(ret); } - } - - return(0); -} - -/* See section C1.6 of the ARMv7-M Architecture Reference Manual */ -int _stlink_usb_write_unsupported_reg(stlink_t *sl, uint32_t val, int r_idx, struct stlink_reg *regp) { - int ret; - - if (r_idx >= 0x1C && r_idx <= 0x1F) { // primask, basepri, faultmask, or control - /* These are held in the same register */ - ret = _stlink_usb_read_unsupported_reg(sl, 0x14, regp); - - if (ret == -1) { return(ret); } - - val = (uint8_t)(val >> 24); - - switch (r_idx) { - case 0x1C: /* control */ - val = (((uint32_t)val) << 24) | - (((uint32_t)regp->faultmask) << 16) | - (((uint32_t)regp->basepri) << 8) | - ((uint32_t)regp->primask); - break; - case 0x1D: /* faultmask */ - val = (((uint32_t)regp->control) << 24) | - (((uint32_t)val) << 16) | - (((uint32_t)regp->basepri) << 8) | - ((uint32_t)regp->primask); - break; - case 0x1E: /* basepri */ - val = (((uint32_t)regp->control) << 24) | - (((uint32_t)regp->faultmask) << 16) | - (((uint32_t)val) << 8) | - ((uint32_t)regp->primask); - break; - case 0x1F: /* primask */ - val = (((uint32_t)regp->control) << 24) | - (((uint32_t)regp->faultmask) << 16) | - (((uint32_t)regp->basepri) << 8) | - ((uint32_t)val); - break; - } - - r_idx = 0x14; - } - - write_uint32(sl->q_buf, val); - - ret = _stlink_usb_write_mem32(sl, STLINK_REG_DCRDR, 4); - - if (ret == -1) { return(ret); } - - sl->q_buf[0] = (unsigned char)r_idx; - sl->q_buf[1] = 0; - sl->q_buf[2] = 0x01; - sl->q_buf[3] = 0; - - return(_stlink_usb_write_mem32(sl, STLINK_REG_DCRSR, 4)); -} - -int _stlink_usb_write_reg(stlink_t *sl, uint32_t reg, int idx) { - struct stlink_libusb * const slu = sl->backend_data; - unsigned char* const data = sl->q_buf; - unsigned char* const cmd = sl->c_buf; - ssize_t size; - uint32_t rep_len = 2; - int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); - - cmd[i++] = STLINK_DEBUG_COMMAND; - - if (sl->version.jtag_api == STLINK_JTAG_API_V1) { - cmd[i++] = STLINK_DEBUG_APIV1_WRITEREG; - } else { - cmd[i++] = STLINK_DEBUG_APIV2_WRITEREG; - } - - cmd[i++] = idx; - write_uint32(&cmd[i], reg); - size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_RETRY, "WRITEREG"); - - return(size<0?-1:0); -} - -int _stlink_usb_enable_trace(stlink_t* sl, uint32_t frequency) { - struct stlink_libusb * const slu = sl->backend_data; - unsigned char* const data = sl->q_buf; - unsigned char* const cmd = sl->c_buf; - ssize_t size; - uint32_t rep_len = 2; - - int i = fill_command(sl, SG_DXFER_TO_DEV, rep_len); - cmd[i++] = STLINK_DEBUG_COMMAND; - cmd[i++] = STLINK_DEBUG_APIV2_START_TRACE_RX; - write_uint16(&cmd[i + 0], 2 * STLINK_TRACE_BUF_LEN); - write_uint32(&cmd[i + 2], frequency); - - size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_STATUS, "START_TRACE_RX"); - - return(size<0?-1:0); -} - -int _stlink_usb_disable_trace(stlink_t* sl) { - struct stlink_libusb * const slu = sl->backend_data; - unsigned char* const data = sl->q_buf; - unsigned char* const cmd = sl->c_buf; - ssize_t size; - uint32_t rep_len = 2; - - int i = fill_command(sl, SG_DXFER_TO_DEV, rep_len); - cmd[i++] = STLINK_DEBUG_COMMAND; - cmd[i++] = STLINK_DEBUG_APIV2_STOP_TRACE_RX; - - size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_STATUS, "STOP_TRACE_RX"); - - return(size<0?-1:0); -} - -int _stlink_usb_read_trace(stlink_t* sl, uint8_t* buf, size_t size) { - struct stlink_libusb * const slu = sl->backend_data; - unsigned char* const data = sl->q_buf; - unsigned char* const cmd = sl->c_buf; - uint32_t rep_len = 2; - int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); - - cmd[i++] = STLINK_DEBUG_COMMAND; - cmd[i++] = STLINK_DEBUG_APIV2_GET_TRACE_NB; - ssize_t send_size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_NO, "GET_TRACE_NB"); - - if (send_size < 0) { - return(-1); - } else if (send_size != 2) { - ELOG("STLINK_DEBUG_APIV2_GET_TRACE_NB reply size %d\n", (int)send_size); - return(-1); - } - - uint16_t trace_count = read_uint16(sl->q_buf, 0); - - if (trace_count > size) { - ELOG("read_trace insufficient buffer length\n"); - return -1; - } - - if (trace_count != 0) { - int res = 0; - int t = libusb_bulk_transfer(slu->usb_handle, slu->ep_trace, buf, trace_count, &res, 3000); - - if (t || res != (int)trace_count) { - ELOG("read_trace read error %d\n", t); - return(-1); - } - } - - return trace_count; -} - -static stlink_backend_t _stlink_usb_backend = { - _stlink_usb_close, - _stlink_usb_exit_debug_mode, - _stlink_usb_enter_swd_mode, - NULL, // don't enter_jtag_mode here... - _stlink_usb_exit_dfu_mode, - _stlink_usb_core_id, - _stlink_usb_reset, - _stlink_usb_jtag_reset, - _stlink_usb_run, - _stlink_usb_status, - _stlink_usb_version, - _stlink_usb_read_debug32, - _stlink_usb_read_mem32, - _stlink_usb_write_debug32, - _stlink_usb_write_mem32, - _stlink_usb_write_mem8, - _stlink_usb_read_all_regs, - _stlink_usb_read_reg, - _stlink_usb_read_all_unsupported_regs, - _stlink_usb_read_unsupported_reg, - _stlink_usb_write_unsupported_reg, - _stlink_usb_write_reg, - _stlink_usb_step, - _stlink_usb_current_mode, - _stlink_usb_force_debug, - _stlink_usb_target_voltage, - _stlink_usb_set_swdclk, - _stlink_usb_enable_trace, - _stlink_usb_disable_trace, - _stlink_usb_read_trace -}; - -/* return the length of serial or (0) in case of errors */ -size_t stlink_serial(struct libusb_device_handle *handle, struct libusb_device_descriptor *desc, char *serial) { - unsigned char desc_serial[(STLINK_SERIAL_LENGTH) * 2]; - - /* truncate the string in the serial buffer */ - serial[0] = '\0'; - - /* get the LANGID from String Descriptor Zero */ - int ret = libusb_get_string_descriptor(handle, 0, 0, desc_serial, sizeof(desc_serial)); - if (ret < 4) return 0; - - uint32_t langid = desc_serial[2] | (desc_serial[3] << 8); - - /* get the serial */ - ret = libusb_get_string_descriptor(handle, desc->iSerialNumber, langid, desc_serial, - sizeof(desc_serial)); - if (ret < 0) return 0; // could not read serial - - unsigned char len = desc_serial[0]; - - if (len == ((STLINK_SERIAL_LENGTH + 1) * 2)) { /* len == 50 */ - /* good ST-Link adapter */ - ret = libusb_get_string_descriptor_ascii( - handle, desc->iSerialNumber, (unsigned char *)serial, STLINK_SERIAL_BUFFER_SIZE); - if (ret < 0) return 0; - } else if (len == ((STLINK_SERIAL_LENGTH / 2 + 1) * 2)) { /* len == 26 */ - /* fix-up the buggy serial */ - for (unsigned int i = 0; i < STLINK_SERIAL_LENGTH; i += 2) - sprintf(serial + i, "%02X", desc_serial[i + 2]); - serial[STLINK_SERIAL_LENGTH] = '\0'; - } else { - return 0; - } - - return strlen(serial); -} - -stlink_t *stlink_open_usb(enum ugly_loglevel verbose, enum connect_type connect, char serial[STLINK_SERIAL_BUFFER_SIZE], int freq) { - stlink_t* sl = NULL; - struct stlink_libusb* slu = NULL; - int ret = -1; - int config; - - sl = calloc(1, sizeof(stlink_t)); - if (sl == NULL) { goto on_malloc_error; } - - slu = calloc(1, sizeof(struct stlink_libusb)); - if (slu == NULL) { goto on_malloc_error; } - - ugly_init(verbose); - sl->backend = &_stlink_usb_backend; - sl->backend_data = slu; - - sl->core_stat = TARGET_UNKNOWN; - - if (libusb_init(&(slu->libusb_ctx))) { - WLOG("failed to init libusb context, wrong version of libraries?\n"); - goto on_error; - } - -#if LIBUSB_API_VERSION < 0x01000106 - libusb_set_debug(slu->libusb_ctx, ugly_libusb_log_level(verbose)); -#else - libusb_set_option(slu->libusb_ctx, LIBUSB_OPTION_LOG_LEVEL, ugly_libusb_log_level(verbose)); -#endif - - libusb_device **list = NULL; - // TODO: We should use ssize_t and use it as a counter if > 0. - // As per libusb API: ssize_t libusb_get_device_list (libusb_context *ctx, libusb_device ***list) - ssize_t cnt = libusb_get_device_list(slu->libusb_ctx, &list); - struct libusb_device_descriptor desc; - - while (cnt-- > 0) { - struct libusb_device_handle *handle; - - libusb_get_device_descriptor(list[cnt], &desc); - - if (desc.idVendor != STLINK_USB_VID_ST) { continue; } - - ret = libusb_open(list[cnt], &handle); - - if (ret) { continue; } // could not open device - - size_t serial_len = stlink_serial(handle, &desc, sl->serial); - - libusb_close(handle); - - if (serial_len != STLINK_SERIAL_LENGTH) { continue; } // could not read the serial - - // if no serial provided, or if serial match device, fixup version and protocol - if (((serial == NULL) || (*serial == 0)) || (memcmp(serial, &sl->serial, STLINK_SERIAL_LENGTH) == 0)) { - if (STLINK_V1_USB_PID(desc.idProduct)) { - slu->protocoll = 1; - sl->version.stlink_v = 1; - } else if (STLINK_V2_USB_PID(desc.idProduct) || STLINK_V2_1_USB_PID(desc.idProduct)) { - sl->version.stlink_v = 2; - } else if (STLINK_V3_USB_PID(desc.idProduct)) { - sl->version.stlink_v = 3; - } - - break; - } - } - - if (cnt < 0) { - WLOG ("Couldn't find any ST-Link devices\n"); - libusb_free_device_list(list, 1); - goto on_error; - } else { - ret = libusb_open(list[cnt], &slu->usb_handle); - - if (ret != 0) { - WLOG("Error %d (%s) opening ST-Link v%d device %03d:%03d\n", ret, - strerror(errno), - sl->version.stlink_v, - libusb_get_bus_number(list[cnt]), - libusb_get_device_address(list[cnt])); - libusb_free_device_list(list, 1); - goto on_error; - } - } - - libusb_free_device_list(list, 1); - -// libusb_kernel_driver_active is not available on Windows. -#if !defined(_WIN32) - if (libusb_kernel_driver_active(slu->usb_handle, 0) == 1) { - ret = libusb_detach_kernel_driver(slu->usb_handle, 0); - - if (ret < 0) { - WLOG("libusb_detach_kernel_driver(() error %s\n", strerror(-ret)); - goto on_libusb_error; - } - } -#endif - - if (libusb_get_configuration(slu->usb_handle, &config)) { - // this may fail for a previous configured device - WLOG("libusb_get_configuration()\n"); - goto on_libusb_error; - } - - if (config != 1) { - printf("setting new configuration (%d -> 1)\n", config); - - if (libusb_set_configuration(slu->usb_handle, 1)) { - // this may fail for a previous configured device - WLOG("libusb_set_configuration() failed\n"); - goto on_libusb_error; - } - } - - if (libusb_claim_interface(slu->usb_handle, 0)) { - WLOG("Stlink usb device found, but unable to claim (probably already in use?)\n"); - goto on_libusb_error; - } - - // TODO: Could use the scanning technique from STM8 code here... - slu->ep_rep = 1 /* ep rep */ | LIBUSB_ENDPOINT_IN; - - if (desc.idProduct == STLINK_USB_PID_STLINK_NUCLEO || - desc.idProduct == STLINK_USB_PID_STLINK_32L_AUDIO || - desc.idProduct == STLINK_USB_PID_STLINK_V2_1 || - desc.idProduct == STLINK_USB_PID_STLINK_V3_USBLOADER || - desc.idProduct == STLINK_USB_PID_STLINK_V3E_PID || - desc.idProduct == STLINK_USB_PID_STLINK_V3S_PID || - desc.idProduct == STLINK_USB_PID_STLINK_V3_2VCP_PID || - desc.idProduct == STLINK_USB_PID_STLINK_V3_NO_MSD_PID) { - slu->ep_req = 1 /* ep req */ | LIBUSB_ENDPOINT_OUT; - slu->ep_trace = 2 | LIBUSB_ENDPOINT_IN; - } else { - slu->ep_req = 2 /* ep req */ | LIBUSB_ENDPOINT_OUT; - slu->ep_trace = 3 | LIBUSB_ENDPOINT_IN; - } - - slu->sg_transfer_idx = 0; - slu->cmd_len = (slu->protocoll == 1) ? STLINK_SG_SIZE : STLINK_CMD_SIZE; - - // initialize stlink version (sl->version) - stlink_version(sl); - - int mode = stlink_current_mode(sl); - if (mode == STLINK_DEV_DFU_MODE) { - DLOG("-- exit_dfu_mode\n"); - _stlink_usb_exit_dfu_mode(sl); - } - - if (connect == CONNECT_UNDER_RESET) { - // for the connect under reset only - // OpenOСD says (official documentation is not available) that - // the NRST pin must be pull down before selecting the SWD/JTAG mode - if (mode == STLINK_DEV_DEBUG_MODE) { - DLOG("-- exit_debug_mode\n"); - _stlink_usb_exit_debug_mode(sl); - } - - _stlink_usb_jtag_reset(sl, STLINK_DEBUG_APIV2_DRIVE_NRST_LOW); - } - - sl->freq = freq; - // set the speed before entering the mode as the chip discovery phase - // should be done at this speed too - // set the stlink clock speed (default is 1800kHz) - DLOG("JTAG/SWD freq set to %d\n", freq); - _stlink_usb_set_swdclk(sl, freq); - - stlink_target_connect(sl, connect); - return(sl); - -on_libusb_error: - stlink_close(sl); - return(NULL); - -on_error: - if (slu->libusb_ctx) { libusb_exit(slu->libusb_ctx); } - -on_malloc_error: - if (sl != NULL) { free(sl); } - if (slu != NULL) { free(slu); } - - return(NULL); -} - -static size_t stlink_probe_usb_devs(libusb_device **devs, stlink_t **sldevs[], enum connect_type connect, int freq) { - stlink_t **_sldevs; - libusb_device *dev; - int i = 0; - size_t slcnt = 0; - size_t slcur = 0; - - /* Count STLINKs */ - while ((dev = devs[i++]) != NULL) { - struct libusb_device_descriptor desc; - int ret = libusb_get_device_descriptor(dev, &desc); - - if (ret < 0) { - WLOG("failed to get libusb device descriptor (libusb error: %d)\n", ret); - break; - } - - if (desc.idVendor != STLINK_USB_VID_ST) { continue; } - - if (!STLINK_SUPPORTED_USB_PID(desc.idProduct)) { - WLOG("skipping ST device : %#04x:%#04x)\n", desc.idVendor, desc.idProduct); - continue; - } - - slcnt++; - } - - _sldevs = calloc(slcnt, sizeof(stlink_t *)); // allocate list of pointers - - if (!_sldevs) { - *sldevs = NULL; - return(0); - } - - /* Open STLINKS and attach them to list */ - i = 0; - - while ((dev = devs[i++]) != NULL) { - struct libusb_device_descriptor desc; - int ret = libusb_get_device_descriptor(dev, &desc); - - if (ret < 0) { - WLOG("failed to get libusb device descriptor (libusb error: %d)\n", ret); - break; - } - - if (!STLINK_SUPPORTED_USB_PID(desc.idProduct)) { continue; } - - struct libusb_device_handle* handle; - char serial[STLINK_SERIAL_BUFFER_SIZE] = {0, }; - - ret = libusb_open(dev, &handle); - - if (ret < 0) { - if (ret == LIBUSB_ERROR_ACCESS) { - ELOG("Could not open USB device %#06x:%#06x, access error.\n", desc.idVendor, desc.idProduct); - } else { - ELOG("Failed to open USB device %#06x:%#06x, libusb error: %d)\n", desc.idVendor, desc.idProduct, ret); - } - - break; - } - - size_t serial_len = stlink_serial(handle, &desc, serial); - - libusb_close(handle); - - if (serial_len != STLINK_SERIAL_LENGTH) { continue; } - - stlink_t *sl = stlink_open_usb(0, connect, serial, freq); - - if (!sl) { - ELOG("Failed to open USB device %#06x:%#06x\n", desc.idVendor, desc.idProduct); - continue; - } - - _sldevs[slcur++] = sl; - } - - *sldevs = _sldevs; - - return(slcur); -} - -size_t stlink_probe_usb(stlink_t **stdevs[], enum connect_type connect, int freq) { - libusb_device **devs; - stlink_t **sldevs; - - size_t slcnt = 0; - int r; - ssize_t cnt; - - r = libusb_init(NULL); - - if (r < 0) { return(0); } - - cnt = libusb_get_device_list(NULL, &devs); - - if (cnt < 0) { return(0); } - - slcnt = stlink_probe_usb_devs(devs, &sldevs, connect, freq); - libusb_free_device_list(devs, 1); - - libusb_exit(NULL); - - *stdevs = sldevs; - - return(slcnt); -} - -void stlink_probe_usb_free(stlink_t ***stdevs, size_t size) { - if (stdevs == NULL || *stdevs == NULL || size == 0) { return; } - - for (size_t n = 0; n < size; n++) { stlink_close((*stdevs)[n]); } - - free(*stdevs); - *stdevs = NULL; -} diff --git a/src/win32/unistd/unistd.h b/src/win32/unistd/unistd.h index cb6da4b8a..389c44664 100644 --- a/src/win32/unistd/unistd.h +++ b/src/win32/unistd/unistd.h @@ -52,7 +52,7 @@ #define ssize_t int #ifndef SSIZE_MAX -#define SSIZE_MAX ((sizeof(ssize_t) == 4) ? 1073741824 : ‭4611686018427387904‬) +#define SSIZE_MAX ((sizeof(ssize_t) == 4) ? 2147483647 : 9223372036854775807) #endif #define STDIN_FILENO 0 diff --git a/src/win32/unistd/unistd.h.bak b/src/win32/unistd/unistd.h.bak deleted file mode 100644 index 47967e45e..000000000 --- a/src/win32/unistd/unistd.h.bak +++ /dev/null @@ -1,76 +0,0 @@ -#ifndef _UNISTD_H -#define _UNISTD_H 1 - -/* - * This file intended to serve as a drop-in replacement for unistd.h on Windows - * Please add functionality as needed. - */ - -#include -#include - -#if defined(_MSC_VER) -#pragma warning(push) -#pragma warning(disable: 4820) -#endif - -#include - -#if defined(_MSC_VER) -#pragma warning(pop) -#endif - -#include // getopt at: https://gist.github.com/ashelly/7776712 -#include // for getpid() and the exec..() family -#include // for _getcwd() and _chdir() - -#define srandom srand -#define random rand - -/* Values for the second argument to access. These may be OR'd together. */ -#define R_OK 4 // Test for read permission -#define W_OK 2 // Test for write permission -// #define X_OK 1 // execute permission - unsupported in windows -#define F_OK 0 // Test for existence - -#define access _access -#define dup2 _dup2 -#define execve _execve -#define ftruncate _chsize -#define unlink _unlink -#define fileno _fileno -#define getcwd _getcwd -#define chdir _chdir -#define isatty _isatty -#define lseek _lseek - -/* - * Read, write, and close are NOT being defined here, - * because while there are file handle specific versions for Windows, they probably don't work for sockets. - * You need to look at your app and consider whether to call e.g. closesocket(). - */ - -#define ssize_t int -#ifndef SSIZE_MAX -//#define SSIZE_MAX ((sizeof(ssize_t) == 4) ? 2147483647 : 9223372036854775807) -#define SSIZE_MAX ((sizeof(ssize_t) == 4) ? 1073741824 : ‭4611686018427387904‬) -#endif - -#define STDIN_FILENO 0 -#define STDOUT_FILENO 1 -#define STDERR_FILENO 2 -// should be in some equivalent to -typedef __int8 int8_t; -typedef __int16 int16_t; -typedef __int32 int32_t; -typedef __int64 int64_t; -typedef unsigned __int8 uint8_t; -typedef unsigned __int16 uint16_t; -typedef unsigned __int32 uint32_t; -typedef unsigned __int64 uint64_t; - -#ifndef STLINK_HAVE_UNISTD_H -int usleep(unsigned int waitTime); -#endif - -#endif // _UNISTD_H diff --git a/stlinkv1_macos_driver/install.sh b/stlinkv1_macos_driver/install.sh index 5716281a1..f9878bd46 100644 --- a/stlinkv1_macos_driver/install.sh +++ b/stlinkv1_macos_driver/install.sh @@ -2,9 +2,6 @@ ISMACOS=$(sw_vers -productVersion) case $ISMACOS in -10.14*) - KEXT="stlink_shield_10_14.kext" - ;; 10.15*) KEXT="stlink_shield_10_15.kext" ;; diff --git a/stlinkv1_macos_driver/stlink_shield_10_14.kext/Contents/Info.plist b/stlinkv1_macos_driver/stlink_shield_10_14.kext/Contents/Info.plist deleted file mode 100644 index fd424ea93..000000000 --- a/stlinkv1_macos_driver/stlink_shield_10_14.kext/Contents/Info.plist +++ /dev/null @@ -1,82 +0,0 @@ - - - - - BuildMachineOSBuild - 18G7016 - CFBundleDevelopmentRegion - English - CFBundleIdentifier - com.libusb.stlink-shield - CFBundleInfoDictionaryVersion - 6.0 - CFBundlePackageType - KEXT - CFBundleSignature - ???? - CFBundleSupportedPlatforms - - MacOSX - - CFBundleVersion - 1.0.0 - DTCompiler - com.apple.compilers.llvm.clang.1_0 - DTPlatformBuild - 11C504 - DTPlatformVersion - GM - DTSDKBuild - 19B90 - DTSDKName - macosx10.15 - DTXcode - 1130 - DTXcodeBuild - 11C504 - IOKitPersonalities - - DeviceDriver - - CFBundleIdentifier - com.apple.kpi.iokit - IOClass - IOService - IOProviderClass - IOUSBDevice - bcdDevice - 256 - idProduct - 14148 - idVendor - 1155 - - InterfaceDriver - - CFBundleIdentifier - com.apple.kpi.iokit - IOClass - IOService - IOProviderClass - IOUSBInterface - bConfigurationValue - 1 - bInterfaceNumber - 0 - idProduct - 14148 - idVendor - 1155 - - - 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zXw5i-S^Q?r*Ump=zW?jTUwH49?P1TCBVNA!H;@+`i zx9!V|hQGDJ|JEP3T>0)Be>eJqSk*4Lw$!ngQKJ{18 z*E%nJJpae{N30uAdi0KsMOPG^xZSZ!dMwa?&bo==CmRjtm(QqpuJ8I6+h2aY>GkN)Ri8Y(zj5ZJ9Y_AO+kfc7Ref*2 zbIRJevgxUH|N6+A`<~oTaNl)rKaly6!Le<}n_bs>X1~5+ - - - - files - - files2 - - rules - - ^Resources/ - - ^Resources/.*\.lproj/ - - optional - - weight - 1000 - - ^Resources/.*\.lproj/locversion.plist$ - - omit - - weight - 1100 - - ^Resources/Base\.lproj/ - - weight - 1010 - - ^version.plist$ - - - rules2 - - .*\.dSYM($|/) - - weight - 11 - - ^(.*/)?\.DS_Store$ - - omit - - weight - 2000 - - ^(Frameworks|SharedFrameworks|PlugIns|Plug-ins|XPCServices|Helpers|MacOS|Library/(Automator|Spotlight|LoginItems))/ - - nested - - weight - 10 - - ^.* - - ^Info\.plist$ - - omit - - weight - 20 - - ^PkgInfo$ - - omit - - weight - 20 - - ^Resources/ - - weight - 20 - - ^Resources/.*\.lproj/ - - optional - - weight - 1000 - - ^Resources/.*\.lproj/locversion.plist$ - - omit - - weight - 1100 - - ^Resources/Base\.lproj/ - - weight - 1010 - - ^[^/]+$ - - nested - - weight - 10 - - ^embedded\.provisionprofile$ - - weight - 20 - - ^version\.plist$ - - weight - 20 - - - - diff --git a/stlinkv1_macos_driver/stlink_shield_xcode/stlink_shield.xcodeproj/project.pbxproj b/stlinkv1_macos_driver/stlink_shield_xcode/stlink_shield.xcodeproj/project.pbxproj index 4f2b80254..373600c64 100644 --- a/stlinkv1_macos_driver/stlink_shield_xcode/stlink_shield.xcodeproj/project.pbxproj +++ b/stlinkv1_macos_driver/stlink_shield_xcode/stlink_shield.xcodeproj/project.pbxproj @@ -8,7 +8,6 @@ /* Begin PBXFileReference section */ 8CD33C31149BB80D0033D618 /* Info.plist */ = {isa = PBXFileReference; lastKnownFileType = text.plist.xml; path = Info.plist; sourceTree = ""; }; - 8F9084FD24786F0F009109AD /* stlink_shield_10_14.kext */ = {isa = PBXFileReference; explicitFileType = wrapper.cfbundle; includeInIndex = 0; path = stlink_shield_10_14.kext; sourceTree = BUILT_PRODUCTS_DIR; }; 8F90850924786F39009109AD /* stlink_shield_10_15.kext */ = {isa = PBXFileReference; explicitFileType = wrapper.cfbundle; includeInIndex = 0; path = stlink_shield_10_15.kext; sourceTree = BUILT_PRODUCTS_DIR; }; /* End PBXFileReference section */ @@ -34,7 +33,6 @@ 19C28FB6FE9D52B211CA2CBB /* Products */ = { isa = PBXGroup; children = ( - 8F9084FD24786F0F009109AD /* stlink_shield_10_14.kext */, 8F90850924786F39009109AD /* stlink_shield_10_15.kext */, ); name = Products; @@ -60,26 +58,6 @@ /* End PBXHeadersBuildPhase section */ /* Begin PBXNativeTarget section */ - 8F9084F324786F0F009109AD /* stlink_shield_10_14 */ = { - isa = PBXNativeTarget; - buildConfigurationList = 8F9084FA24786F0F009109AD /* Build configuration list for PBXNativeTarget "stlink_shield_10_14" */; - buildPhases = ( - 8F9084F424786F0F009109AD /* ShellScript */, - 8F9084F524786F0F009109AD /* Headers */, - 8F9084F624786F0F009109AD /* Resources */, - 8F9084F824786F0F009109AD /* Sources */, - 8F9084F924786F0F009109AD /* ShellScript */, - ); - buildRules = ( - ); - dependencies = ( - ); - name = stlink_shield_10_14; - productInstallPath = "$(SYSTEM_LIBRARY_DIR)/Extensions"; - productName = NanosMouse; - productReference = 8F9084FD24786F0F009109AD /* stlink_shield_10_14.kext */; - productType = "com.apple.product-type.kernel-extension.iokit"; - }; 8F9084FF24786F39009109AD /* stlink_shield_10_15 */ = { isa = PBXNativeTarget; buildConfigurationList = 8F90850624786F39009109AD /* Build configuration list for PBXNativeTarget "stlink_shield_10_15" */; @@ -120,7 +98,6 @@ projectDirPath = ""; projectRoot = ""; targets = ( - 8F9084F324786F0F009109AD /* stlink_shield_10_14 */, 8F9084FF24786F39009109AD /* stlink_shield_10_15 */, ); }; @@ -458,24 +435,6 @@ }; name = Release; }; - 8F9084FB24786F0F009109AD /* Debug */ = { - isa = XCBuildConfiguration; - buildSettings = { - CODE_SIGN_IDENTITY = "-"; - MACOSX_DEPLOYMENT_TARGET = 10.14; - PRODUCT_NAME = "$(TARGET_NAME)"; - }; - name = Debug; - }; - 8F9084FC24786F0F009109AD /* Release */ = { - isa = XCBuildConfiguration; - buildSettings = { - CODE_SIGN_IDENTITY = "-"; - MACOSX_DEPLOYMENT_TARGET = 10.14; - PRODUCT_NAME = "$(TARGET_NAME)"; - }; - name = Release; - }; 8F90850724786F39009109AD /* Debug */ = { isa = XCBuildConfiguration; buildSettings = { @@ -506,15 +465,6 @@ defaultConfigurationIsVisible = 0; defaultConfigurationName = Release; }; - 8F9084FA24786F0F009109AD /* Build configuration list for PBXNativeTarget "stlink_shield_10_14" */ = { - isa = XCConfigurationList; - buildConfigurations = ( - 8F9084FB24786F0F009109AD /* Debug */, - 8F9084FC24786F0F009109AD /* Release */, - ); - defaultConfigurationIsVisible = 0; - defaultConfigurationName = Release; - }; 8F90850624786F39009109AD /* Build configuration list for PBXNativeTarget "stlink_shield_10_15" */ = { isa = XCConfigurationList; buildConfigurations = ( From cf6bdbfe4ba9fa3dd4ea58b81a3d290a39c2a55a Mon Sep 17 00:00:00 2001 From: Oleksiy Slyshyk Date: Mon, 31 Jan 2022 13:01:06 +0200 Subject: [PATCH 372/503] set C standart through cmake variables, remove redundant -Ox options --- CMakeLists.txt | 4 ++++ cmake/modules/c_flags.cmake | 4 ---- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index abfc0be47..52c00ea29 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -9,6 +9,10 @@ set(CMAKE_ARCHIVE_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}/lib) set(CMAKE_LIBRARY_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}/lib) set(CMAKE_RUNTIME_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}/bin) +set(CMAKE_C_STANDARD 11) +set(CMAKE_C_STANDARD_REQUIRED ON) +set(CMAKE_C_EXTENSIONS ON) + ### # General project settings diff --git a/cmake/modules/c_flags.cmake b/cmake/modules/c_flags.cmake index 5ed0c4d7d..44052bba8 100644 --- a/cmake/modules/c_flags.cmake +++ b/cmake/modules/c_flags.cmake @@ -17,8 +17,6 @@ function(add_cflag_if_supported flag) endif () endfunction() -add_cflag_if_supported("-std=gnu11") -add_cflag_if_supported("-std=gnu18") add_cflag_if_supported("-Wall") add_cflag_if_supported("-Wextra") add_cflag_if_supported("-Wshadow") @@ -47,8 +45,6 @@ endif () if (${CMAKE_BUILD_TYPE} MATCHES "Debug") add_cflag_if_supported("-ggdb") - add_cflag_if_supported("-O0") else () - add_cflag_if_supported("-O2") add_cflag_if_supported("-Werror") endif () From 978462d048bbb74842c75dcc0539e8c28da3ebb1 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Fri, 4 Feb 2022 21:53:00 +0100 Subject: [PATCH 373/503] Updated libusb to v1.0.25 (macOS + Windows) --- cmake/modules/Findlibusb.cmake | 2 +- doc/version_support.md | 4 ++-- src/stlink-lib/libusb_settings.h | 9 +++++---- 3 files changed, 8 insertions(+), 7 deletions(-) diff --git a/cmake/modules/Findlibusb.cmake b/cmake/modules/Findlibusb.cmake index bc04f848d..de3712eca 100644 --- a/cmake/modules/Findlibusb.cmake +++ b/cmake/modules/Findlibusb.cmake @@ -72,7 +72,7 @@ elseif (WIN32 OR (EXISTS "/etc/debian_version" AND MINGW)) # Windows or MinGW-to if (WIN32 AND NOT EXISTS "/etc/debian_version") # Skip this for Debian... # Preparations for installing libusb library - set(LIBUSB_WIN_VERSION 1.0.24) # set libusb version + set(LIBUSB_WIN_VERSION 1.0.25) # set libusb version set(LIBUSB_WIN_ARCHIVE libusb-${LIBUSB_WIN_VERSION}.7z) if (WIN32 AND NOT EXISTS "/etc/debian_version") # ... on native Windows systems set(LIBUSB_WIN_ARCHIVE_PATH ${CMAKE_BINARY_DIR}/${LIBUSB_WIN_ARCHIVE}) diff --git a/doc/version_support.md b/doc/version_support.md index d7ba5c102..01d9dddb1 100644 --- a/doc/version_support.md +++ b/doc/version_support.md @@ -14,8 +14,8 @@ Up on compiling c-make will **automatically** download and install the latest co | Package Repository | libusb | cmake | gtk-3-dev | Supported macOS versions | | ------------------ | ------ | ------ | ------------------ | ------------------------ | -| homebrew | 1.0.24 | 3.22.1 | 3.24.30
gtk+3 | **10.10 - 12.x** | -| MacPorts | 1.0.24 | 3.22.1 | 3.24.31
gtk3 | **10.4 - 12.x** | +| homebrew | 1.0.25 | 3.22.1 | 3.24.30
gtk+3 | **10.10 - 12.x** | +| MacPorts | 1.0.25 | 3.22.1 | 3.24.31
gtk3 | **10.4 - 12.x** | NOTE: In order to use a STLINK/V1 programmer on macOS, version 10.15 is required. diff --git a/src/stlink-lib/libusb_settings.h b/src/stlink-lib/libusb_settings.h index c7562e290..2a595238a 100644 --- a/src/stlink-lib/libusb_settings.h +++ b/src/stlink-lib/libusb_settings.h @@ -18,6 +18,7 @@ * v1.0.22 | 0x01000106 * v1.0.23 | 0x01000107 * v1.0.24 | 0x01000108 + * v1.0.25 | 0x01000109 */ #if defined (__FreeBSD__) @@ -31,13 +32,13 @@ #if defined (__FreeBSD__) #define MINIMAL_API_VERSION 0x01000102 // v1.0.16 #elif defined (__OpenBSD__) - #define MINIMAL_API_VERSION 0x01000104 // v1.0.20 + #define MINIMAL_API_VERSION 0x01000105 // v1.0.21 #elif defined (__linux__) - #define MINIMAL_API_VERSION 0x01000104 // v1.0.20 + #define MINIMAL_API_VERSION 0x01000105 // v1.0.21 #elif defined (__APPLE__) - #define MINIMAL_API_VERSION 0x01000104 // v1.0.20 + #define MINIMAL_API_VERSION 0x01000109 // v1.0.25 #elif defined (_WIN32) - #define MINIMAL_API_VERSION 0x01000104 // v1.0.20 + #define MINIMAL_API_VERSION 0x01000109 // v1.0.25 #endif #if (LIBUSB_API_VERSION < MINIMAL_API_VERSION) From 468b1d2daa853b975c33ab69876c486734f2c6a7 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Fri, 4 Feb 2022 22:24:42 +0100 Subject: [PATCH 374/503] [libusb] Added Security framework for macOS --- CMakeLists.txt | 6 ++++-- cmake/packaging/cpack_config.cmake | 2 +- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index 52c00ea29..67f76ec08 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -209,7 +209,8 @@ if (APPLE) # ... with Apple macOS libraries find_library(ObjC objc) find_library(CoreFoundation CoreFoundation) find_library(IOKit IOKit) - target_link_libraries(${STLINK_LIB_SHARED} ${LIBUSB_LIBRARY} ${SSP_LIB} ${ObjC} ${CoreFoundation} ${IOKit}) + find_library(Security Security) + target_link_libraries(${STLINK_LIB_SHARED} ${LIBUSB_LIBRARY} ${SSP_LIB} ${ObjC} ${CoreFoundation} ${IOKit} ${Security}) elseif (WIN32) # ... with Windows libraries target_link_libraries(${STLINK_LIB_SHARED} ${LIBUSB_LIBRARY} ${SSP_LIB} wsock32 ws2_32) else () @@ -251,7 +252,8 @@ if (APPLE) # ... with Apple macOS libraries find_library(ObjC objc) find_library(CoreFoundation CoreFoundation) find_library(IOKit IOKit) - target_link_libraries(${STLINK_LIB_STATIC} ${LIBUSB_LIBRARY} ${SSP_LIB} ${ObjC} ${CoreFoundation} ${IOKit}) + find_library(Security Security) + target_link_libraries(${STLINK_LIB_STATIC} ${LIBUSB_LIBRARY} ${SSP_LIB} ${ObjC} ${CoreFoundation} ${IOKit} ${Security}) elseif (WIN32) # ... with Windows libraries target_link_libraries(${STLINK_LIB_STATIC} ${LIBUSB_LIBRARY} ${SSP_LIB} wsock32 ws2_32) else () diff --git a/cmake/packaging/cpack_config.cmake b/cmake/packaging/cpack_config.cmake index 587ff5fb5..a4f1ae073 100644 --- a/cmake/packaging/cpack_config.cmake +++ b/cmake/packaging/cpack_config.cmake @@ -17,7 +17,7 @@ set(CPACK_OUTPUT_FILE_PREFIX "${CMAKE_BINARY_DIR}/dist") if (APPLE) # macOS set(CPACK_GENERATOR "ZIP") - set(CPACK_PACKAGE_FILE_NAME "${PROJECT_NAME}-${PROJECT_VERSION}-macosx-amd64") + set(CPACK_PACKAGE_FILE_NAME "${PROJECT_NAME}-${PROJECT_VERSION}-macos-amd64") set(CPACK_INSTALL_PREFIX "") elseif (WIN32 AND (NOT EXISTS "/etc/debian_version")) # Windows From 77fff346aa9d075e7fd01668d8418818f9c262ac Mon Sep 17 00:00:00 2001 From: Alex Klimaj Date: Tue, 15 Feb 2022 22:28:19 -0700 Subject: [PATCH 375/503] Add writing and reading STM32WL option bytes --- config/chips/WLx5.chip | 2 +- inc/stm32flash.h | 8 +-- src/option_bytes.c | 108 +++++++++++++++++++++++++++++++++++++++++ 3 files changed, 114 insertions(+), 4 deletions(-) diff --git a/config/chips/WLx5.chip b/config/chips/WLx5.chip index 5bc9d90dc..8337b0aee 100644 --- a/config/chips/WLx5.chip +++ b/config/chips/WLx5.chip @@ -9,6 +9,6 @@ flash_pagesize 0x800 // 2 KB sram_size 0x10000 // 64 KB bootrom_base 0x1fff0000 bootrom_size 0x7000 // 28 KB -option_base 0x1fffc000 +option_base 0x1fff7800 option_size 0x10 // 16 B flags swo diff --git a/inc/stm32flash.h b/inc/stm32flash.h index c28d67c28..7e96d3f70 100644 --- a/inc/stm32flash.h +++ b/inc/stm32flash.h @@ -162,9 +162,11 @@ #define STM32WB_FLASH_SRRVR (STM32WB_FLASH_REGS_ADDR + 0x84) // WB Flash control register. -#define STM32WB_FLASH_CR_STRT (16) /* Start */ -#define STM32WB_FLASH_CR_OPTLOCK (30) /* Option Lock */ -#define STM32WB_FLASH_CR_LOCK (31) /* Lock */ +#define STM32WB_FLASH_CR_STRT (16) /* Start */ +#define STM32WB_FLASH_CR_OPTSTRT (17) /* Start writing option bytes */ +#define STM32WB_FLASH_CR_OBL_LAUNCH (27) /* Forces the option byte loading */ +#define STM32WB_FLASH_CR_OPTLOCK (30) /* Option Lock */ +#define STM32WB_FLASH_CR_LOCK (31) /* Lock */ // WB Flash status register. #define STM32WB_FLASH_SR_ERROR_MASK (0x3f8) /* SR [9:3] */ #define STM32WB_FLASH_SR_PROGERR (3) /* Programming alignment error */ diff --git a/src/option_bytes.c b/src/option_bytes.c index f5d8c00a0..c1a418232 100644 --- a/src/option_bytes.c +++ b/src/option_bytes.c @@ -472,6 +472,57 @@ static int stlink_write_option_bytes_h7(stlink_t *sl, uint8_t *base, return 0; } +/** + * Write option bytes + * @param sl + * @param addr of the memory mapped option bytes + * @param base option bytes to write + * @return 0 on success, -ve on failure. + */ +static int stlink_write_option_bytes_wb(stlink_t *sl, uint8_t *base, + stm32_addr_t addr, uint32_t len) { + /* Write options bytes */ + uint32_t val; + int ret = 0; + (void)len; + uint32_t data; + + clear_flash_error(sl); + + while (len != 0) { + write_uint32((unsigned char *)&data, + *(uint32_t *)(base)); // write options bytes + + WLOG("Writing option bytes %#10x to %#10x\n", data, addr); + stlink_write_debug32(sl, addr, data); + wait_flash_busy(sl); + + if ((ret = check_flash_error(sl))) { + break; + } + + len -= 4; + addr += 4; + base += 4; + } + + // Set Options Start bit + stlink_read_debug32(sl, STM32WB_FLASH_CR, &val); + val |= (1 << STM32WB_FLASH_CR_OPTSTRT); + stlink_write_debug32(sl, STM32WB_FLASH_CR, val); + + wait_flash_busy(sl); + + ret = check_flash_error(sl); + + // Reload options + stlink_read_debug32(sl, STM32WB_FLASH_CR, &val); + val |= (1 << STM32WB_FLASH_CR_OBL_LAUNCH); + stlink_write_debug32(sl, STM32WB_FLASH_CR, val); + + return (ret); +} + /** * Write option bytes * @param sl @@ -536,6 +587,9 @@ int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t *base, case STM32_FLASH_TYPE_H7: ret = stlink_write_option_bytes_h7(sl, base, addr, len); break; + case STM32_FLASH_TYPE_WB_WL: + ret = stlink_write_option_bytes_wb(sl, base, addr, len); + break; default: ELOG("Option bytes writing is currently not implemented for connected " "chip\n"); @@ -715,6 +769,42 @@ stlink_write_option_control_register_f7(stlink_t *sl, return ret; } +/** + * Write option bytes + * @param sl + * @param option_byte value to write + * @return 0 on success, -ve on failure. + */ +static int +stlink_write_option_control_register_wb(stlink_t *sl, + uint32_t option_control_register) { + int ret = 0; + + // Clear errors + clear_flash_error(sl); + + ILOG("Asked to write option control register 1 %#10x to %#010x.\n", + option_control_register, STM32WB_FLASH_OPTR); + + /* write option byte, ensuring we dont lock opt, and set strt bit */ + stlink_write_debug32(sl, STM32WB_FLASH_OPTR, option_control_register); + + wait_flash_busy(sl); + + // Set Options Start bit + uint32_t val = (1 << STM32WB_FLASH_CR_OPTSTRT); + stlink_write_debug32(sl, STM32WB_FLASH_CR, val); + + wait_flash_busy(sl); + + ret = check_flash_error(sl); + if (!ret) + ILOG("Wrote option bytes %#010x to %#010x!\n", option_control_register, + STM32WB_FLASH_OPTR); + + return ret; +} + /** * Write option bytes * @param sl @@ -746,6 +836,10 @@ int stlink_write_option_control_register32(stlink_t *sl, case STM32_FLASH_TYPE_F7: ret = stlink_write_option_control_register_f7(sl, option_control_register); break; + case STM32_FLASH_TYPE_WB_WL: + ret = + stlink_write_option_control_register_wb(sl, option_control_register); + break; default: ELOG("Option control register writing is currently not implemented for " "connected chip\n"); @@ -1003,6 +1097,18 @@ int stlink_read_option_control_register_f0(stlink_t *sl, return stlink_read_debug32(sl, FLASH_OBR, option_byte); } +/** + * Read option bytes + * @param sl + * @param option_byte value to read + * @return 0 on success, -ve on failure. + */ +int stlink_read_option_control_register_wb(stlink_t *sl, + uint32_t *option_byte) { + DLOG("@@@@ Read option control register byte from %#10x\n", STM32WB_FLASH_OPTR); + return stlink_read_debug32(sl, STM32WB_FLASH_OPTR, option_byte); +} + /** * Read option bytes * @param sl @@ -1021,6 +1127,8 @@ int stlink_read_option_control_register32(stlink_t *sl, uint32_t *option_byte) { return stlink_read_option_control_register_f0(sl, option_byte); case STM32_FLASH_TYPE_F7: return stlink_read_option_control_register_f7(sl, option_byte); + case STM32_FLASH_TYPE_WB_WL: + return stlink_read_option_control_register_wb(sl, option_byte); default: return -1; } From a6939cb9d491d8e3aa2aa54d0e35fb72519b7d8f Mon Sep 17 00:00:00 2001 From: Lucas Sinn Date: Tue, 8 Mar 2022 11:21:23 +0100 Subject: [PATCH 376/503] init chipids only when actually interacting with device --- src/st-info/info.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/src/st-info/info.c b/src/st-info/info.c index 618046ddd..a939a03cf 100644 --- a/src/st-info/info.c +++ b/src/st-info/info.c @@ -29,7 +29,6 @@ static void stlink_print_version(stlink_t *sl) { } static void stlink_print_info(stlink_t *sl) { - const struct stlink_chipid_params *params = NULL; if (!sl) { return; } @@ -38,9 +37,6 @@ static void stlink_print_info(stlink_t *sl) { printf(" flash: %u (pagesize: %u)\n", (uint32_t)sl->flash_size, (uint32_t)sl->flash_pgsz); printf(" sram: %u\n", (uint32_t)sl->sram_size); printf(" chipid: 0x%.3x\n", sl->chip_id); - - params = stlink_chipid_get_params(sl->chip_id); - if (params) { printf(" dev-type: %s\n", params->dev_type); } } static void stlink_probe(enum connect_type connect, int freq) { @@ -69,6 +65,8 @@ static int print_data(int ac, char **av) { return(0); } + init_chipids(ETC_STLINK_DIR); + for (int i=2; i Date: Tue, 8 Mar 2022 11:24:06 +0100 Subject: [PATCH 377/503] optimized processing of chipidfile 'moved chip dump to stdout instead of stderr' 'closing open fd after file is fully read' 'reduced file read buffer size' --- src/stlink-lib/chipid.c | 44 ++++++++++++++++++----------------------- 1 file changed, 19 insertions(+), 25 deletions(-) diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index 06e8571aa..8fcaa4100 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -30,8 +30,8 @@ struct stlink_chipid_params *stlink_chipid_get_params(uint32_t chip_id) { struct stlink_chipid_params *params = NULL; for (params = devicelist; params != NULL; params = params->next) if (params->chip_id == chip_id) { - fprintf(stderr, "\ndetected chip_id parametres\n\n"); - dump_a_chip(stderr, params); + fprintf(stdout, "\ndetected chip_id parametres\n\n"); + dump_a_chip(stdout, params); break; } @@ -40,7 +40,7 @@ struct stlink_chipid_params *stlink_chipid_get_params(uint32_t chip_id) { void process_chipfile(char *fname) { FILE *fp; - char *p, *pp, buf[1025]; + char *p, buf[128]; char word[64], value[64]; struct stlink_chipid_params *ts; int nc; @@ -55,29 +55,23 @@ void process_chipfile(char *fname) { ts = calloc(sizeof(struct stlink_chipid_params), 1); - while (fgets(buf, 1024, fp) != NULL) { - for (p = buf; isspace (*p); p++); + while (fgets(buf, sizeof(buf), fp) != NULL) { - if (!*p) { - continue; // we hit end-of-line with only whitespace - } - - if (*p == '#') { + if(strncmp(buf, "#", strlen("#")) == 0) continue; // ignore comments - } - sscanf(p, "%s %s", word, value); + sscanf(buf, "%s %s", word, value); if (strcmp (word, "dev_type") == 0) { // ts->dev_type = strdup (value); - buf[strlen(p) - 1] = 0; // chomp newline - sscanf(p, "%*s %n", &nc); - ts->dev_type = strdup(p + nc); + buf[strlen(buf) - 1] = 0; // chomp newline + sscanf(buf, "%*s %n", &nc); + ts->dev_type = strdup(buf + nc); } else if (strcmp(word, "ref_manual_id") == 0) { // ts->ref_manual_id = strdup (value); - buf[strlen(p) - 1] = 0; // chomp newline - sscanf(p, "%*s %n", &nc); - ts->ref_manual_id = strdup(p + nc); + buf[strlen(buf) - 1] = 0; // chomp newline + sscanf(buf, "%*s %n", &nc); + ts->ref_manual_id = strdup(buf + nc); } else if (strcmp(word, "chip_id") == 0) { if (sscanf(value, "%i", &ts->chip_id) < 1) { fprintf(stderr, "Failed to parse chip-id\n"); @@ -138,18 +132,18 @@ void process_chipfile(char *fname) { fprintf(stderr, "Failed to parse option size\n"); } } else if (strcmp(word, "flags") == 0) { - pp = strtok (p, " \t\n"); + p = strtok (buf, " \t\n"); - while ((pp = strtok (NULL, " \t\n"))) { - if (strcmp(pp, "none") == 0) { + while ((p = strtok (NULL, " \t\n"))) { + if (strcmp(p, "none") == 0) { // NOP - } else if (strcmp(pp, "dualbank") == 0) { + } else if (strcmp(p, "dualbank") == 0) { ts->flags |= CHIP_F_HAS_DUAL_BANK; - } else if (strcmp(pp, "swo") == 0) { + } else if (strcmp(p, "swo") == 0) { ts->flags |= CHIP_F_HAS_SWO_TRACING; } else { fprintf(stderr, "Unknown flags word in %s: '%s'\n", - fname, pp); + fname, p); } } @@ -159,7 +153,7 @@ void process_chipfile(char *fname) { fname, word); } } - + fclose(fp); ts->next = devicelist; devicelist = ts; } From 564434297cfadcea44eb3c275bc4d95c5f210d1d Mon Sep 17 00:00:00 2001 From: Lucas Sinn Date: Mon, 14 Mar 2022 12:47:23 +0100 Subject: [PATCH 378/503] readded get chipid parameters on print info --- src/st-info/info.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/st-info/info.c b/src/st-info/info.c index a939a03cf..d02653bc5 100644 --- a/src/st-info/info.c +++ b/src/st-info/info.c @@ -29,7 +29,7 @@ static void stlink_print_version(stlink_t *sl) { } static void stlink_print_info(stlink_t *sl) { - + const struct stlink_chipid_params *params = NULL; if (!sl) { return; } printf(" version: "); stlink_print_version(sl); @@ -37,6 +37,9 @@ static void stlink_print_info(stlink_t *sl) { printf(" flash: %u (pagesize: %u)\n", (uint32_t)sl->flash_size, (uint32_t)sl->flash_pgsz); printf(" sram: %u\n", (uint32_t)sl->sram_size); printf(" chipid: 0x%.3x\n", sl->chip_id); + + params = stlink_chipid_get_params(sl->chip_id); + if (params) { printf(" dev-type: %s\n", params->dev_type); } } static void stlink_probe(enum connect_type connect, int freq) { From a99a626e6948b684515fe068e7b01b53b74c4678 Mon Sep 17 00:00:00 2001 From: Lucas Sinn Date: Mon, 14 Mar 2022 12:48:47 +0100 Subject: [PATCH 379/503] moved dump_a_chip to debug output, minor code style fix --- src/stlink-lib/chipid.c | 34 +++++++++++++++++----------------- 1 file changed, 17 insertions(+), 17 deletions(-) diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index 8fcaa4100..02b610bb1 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -10,28 +10,28 @@ static struct stlink_chipid_params *devicelist; -void dump_a_chip (FILE *fp, struct stlink_chipid_params *dev) { - fprintf(fp, "# Device Type: %s\n", dev->dev_type); - fprintf(fp, "# Reference Manual: RM%s\n", dev->ref_manual_id); - fprintf(fp, "#\n"); - fprintf(fp, "chip_id 0x%x\n", dev->chip_id); - fprintf(fp, "flash_type %d\n", dev->flash_type); - fprintf(fp, "flash_size_reg 0x%x\n", dev->flash_size_reg); - fprintf(fp, "flash_pagesize 0x%x\n", dev->flash_pagesize); - fprintf(fp, "sram_size 0x%x\n", dev->sram_size); - fprintf(fp, "bootrom_base 0x%x\n", dev->bootrom_base); - fprintf(fp, "bootrom_size 0x%x\n", dev->bootrom_size); - fprintf(fp, "option_base 0x%x\n", dev->option_base); - fprintf(fp, "option_size 0x%x\n", dev->option_size); - fprintf(fp, "flags %d\n\n", dev->flags); +void dump_a_chip (struct stlink_chipid_params *dev) { + DLOG("# Device Type: %s\n", dev->dev_type); + DLOG("# Reference Manual: RM%s\n", dev->ref_manual_id); + DLOG("#\n"); + DLOG("chip_id 0x%x\n", dev->chip_id); + DLOG("flash_type %d\n", dev->flash_type); + DLOG("flash_size_reg 0x%x\n", dev->flash_size_reg); + DLOG("flash_pagesize 0x%x\n", dev->flash_pagesize); + DLOG("sram_size 0x%x\n", dev->sram_size); + DLOG("bootrom_base 0x%x\n", dev->bootrom_base); + DLOG("bootrom_size 0x%x\n", dev->bootrom_size); + DLOG("option_base 0x%x\n", dev->option_base); + DLOG("option_size 0x%x\n", dev->option_size); + DLOG("flags %d\n\n", dev->flags); } struct stlink_chipid_params *stlink_chipid_get_params(uint32_t chip_id) { struct stlink_chipid_params *params = NULL; for (params = devicelist; params != NULL; params = params->next) if (params->chip_id == chip_id) { - fprintf(stdout, "\ndetected chip_id parametres\n\n"); - dump_a_chip(stdout, params); + DLOG("detected chip_id parameters\n\n"); + dump_a_chip(params); break; } @@ -57,7 +57,7 @@ void process_chipfile(char *fname) { while (fgets(buf, sizeof(buf), fp) != NULL) { - if(strncmp(buf, "#", strlen("#")) == 0) + if (strncmp(buf, "#", strlen("#")) == 0) continue; // ignore comments sscanf(buf, "%s %s", word, value); From 86a37544f1c3e98c36432dd8df85c99536ea9acf Mon Sep 17 00:00:00 2001 From: Lucas Sinn Date: Mon, 14 Mar 2022 13:00:07 +0100 Subject: [PATCH 380/503] added option_base, option_size for F401xD_xE --- config/chips/F401xD_xE.chip | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/config/chips/F401xD_xE.chip b/config/chips/F401xD_xE.chip index 39748a604..f817175f4 100644 --- a/config/chips/F401xD_xE.chip +++ b/config/chips/F401xD_xE.chip @@ -9,6 +9,6 @@ flash_pagesize 0x4000 // 16 KB sram_size 0x18000 // 96 KB bootrom_base 0x1fff0000 bootrom_size 0x7800 // 30 KB -option_base 0x0 -option_size 0x0 +option_base 0x40023C14 +option_size 0x4 flags swo From 3b328b26bd5eb0e07f78b8ba48e10c2581a1239a Mon Sep 17 00:00:00 2001 From: Lucas Sinn Date: Wed, 16 Mar 2022 09:31:19 +0100 Subject: [PATCH 381/503] adding additional check if .chip files contain empty lines --- src/stlink-lib/chipid.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index 02b610bb1..fe60ebf64 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -60,6 +60,10 @@ void process_chipfile(char *fname) { if (strncmp(buf, "#", strlen("#")) == 0) continue; // ignore comments + if ((strncmp(buf, "\n", strlen("\n")) == 0) || + (strncmp(buf, " ", strlen(" ")) == 0)) + continue; // ignore empty lines + sscanf(buf, "%s %s", word, value); if (strcmp (word, "dev_type") == 0) { From 8dfb7973e712ab2ed982cd241f9240ac9e432da7 Mon Sep 17 00:00:00 2001 From: Lucas Sinn Date: Mon, 28 Mar 2022 09:18:30 +0200 Subject: [PATCH 382/503] made chipfile buffer size bigger --- src/stlink-lib/chipid.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index fe60ebf64..e36c150a6 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -40,7 +40,7 @@ struct stlink_chipid_params *stlink_chipid_get_params(uint32_t chip_id) { void process_chipfile(char *fname) { FILE *fp; - char *p, buf[128]; + char *p, buf[256]; char word[64], value[64]; struct stlink_chipid_params *ts; int nc; From a5696f2668105aa7ae3f61f77193423617c25099 Mon Sep 17 00:00:00 2001 From: simon-wh Date: Fri, 20 May 2022 11:01:32 +0200 Subject: [PATCH 383/503] Define option byte properties for F1xx_XLD --- config/chips/F1xx_XLD.chip | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/config/chips/F1xx_XLD.chip b/config/chips/F1xx_XLD.chip index 622bd9d02..4f8c9ee27 100644 --- a/config/chips/F1xx_XLD.chip +++ b/config/chips/F1xx_XLD.chip @@ -9,6 +9,6 @@ flash_pagesize 0x800 // 2 KB sram_size 0x18000 // 96 KB bootrom_base 0x1fffe000 bootrom_size 0x1800 // 6 KB -option_base 0x0 -option_size 0x0 +option_base 0x1ffff800 // STM32_F0_OPTION_BYTES_BASE +option_size 0x10 // 16 B flags swo From 9a7805ede51839cb8d76074c595997045c5c1e95 Mon Sep 17 00:00:00 2001 From: simon-wh Date: Fri, 20 May 2022 11:02:50 +0200 Subject: [PATCH 384/503] Include GD32F303CGT6 in devices_boards.md --- doc/devices_boards.md | 1 + 1 file changed, 1 insertion(+) diff --git a/doc/devices_boards.md b/doc/devices_boards.md index 51b9a0739..1a5099b72 100644 --- a/doc/devices_boards.md +++ b/doc/devices_boards.md @@ -90,6 +90,7 @@ Tested non-official ST boards [incl. STLINK programmers]: | Product-Code | Chip-ID | STLINK
Programmer | Boards | | ------------ | ------- | ---------------------- | ---------------------------------- | | GD32F303VGT6 | 0x430 | [v2] | STM32F303 clone from GigaDevice GD | +| GD32F303CGT6 | 0x430 | [v2] | STM32F303 clone from GigaDevice GD | ## STM32F4 / ARM Cortex M4F From f8d1603be40ddf6ed0701061f4aef8bdcc227070 Mon Sep 17 00:00:00 2001 From: John Hall Date: Wed, 8 Jun 2022 13:48:13 -0700 Subject: [PATCH 385/503] Updating to allow frequency units for clock and trace flags. Making sure trace frequency is not less than 1/5 of the system frequency. Showing minimum and maximum available trace speed when out of range. Making sure MCU is stopped after reset to avoid missing data. Making sure variables are intiallized. --- src/st-trace/trace.c | 84 ++++++++++++++++++++++++++++++++++---------- 1 file changed, 65 insertions(+), 19 deletions(-) diff --git a/src/st-trace/trace.c b/src/st-trace/trace.c index 28a585071..8c36ae6f0 100644 --- a/src/st-trace/trace.c +++ b/src/st-trace/trace.c @@ -98,13 +98,52 @@ static void usage(void) { puts(" -V, --version Print this version"); puts(" -vXX, --verbose=XX Specify a specific verbosity level (0..99)"); puts(" -v, --verbose Specify a generally verbose logging"); - puts(" -cXX, --clock=XX Specify the core frequency in MHz"); - puts(" -tXX, --trace=XX Specify the trace frequency in Hz"); + puts(" -cXX, --clock=XX Specify the core frequency, optionally followed by"); + puts(" k=kHz, m=MHz, or g=GHz (eg. --clock=180m)"); + puts(" -tXX, --trace=XX Specify the trace frequency, optionally followed by"); + puts(" k=kHz, m=MHz, or g=GHz (eg. --trace=2m)"); puts(" -n, --no-reset Do not reset board on connection"); puts(" -sXX, --serial=XX Use a specific serial number"); puts(" -f, --force Ignore most initialization errors"); } +static bool parse_frequency(char* text, uint32_t* result) +{ + if (text == NULL) { + ELOG("Invalid frequency.\n"); + return false; + } + + char* suffix = text; + double value = strtod(text, &suffix); + + if (value == 0.0) { + ELOG("Invalid frequency.\n"); + return false; + } + + double scale = 1.0; + if (*suffix == 'k') + scale = 1000; + else if (*suffix == 'm') + scale = 1000000; + else if (*suffix == 'g') + scale = 1000000000; + else if (*suffix != '\0') { + ELOG("Unknown frequency suffix '%s'.\n", suffix); + return false; + } + + value *= scale; + if (value <= 0 || value > 0xFFFFFFFFul) { + ELOG("Frequency is out of valid range.\n"); + return false; + } + + *result = (uint32_t)value; + return true; +} + bool parse_options(int argc, char **argv, st_settings_t *settings) { static struct option long_options[] = { @@ -150,10 +189,12 @@ bool parse_options(int argc, char **argv, st_settings_t *settings) { ugly_init(settings->logging_level); break; case 'c': - settings->core_frequency = atoi(optarg) * 1000000; + if (!parse_frequency(optarg, &settings->core_frequency)) + error = true; break; case 't': - settings->trace_frequency = atoi(optarg); + if (!parse_frequency(optarg, &settings->trace_frequency)) + error = true; break; case 'n': settings->reset_board = false; @@ -200,8 +241,7 @@ static bool enable_trace(stlink_t *stlink, const st_settings_t *settings, if (!settings->force) return false; } - - if (settings->reset_board && stlink_reset(stlink, RESET_AUTO)) { + if (settings->reset_board && stlink_reset(stlink, RESET_SOFT_AND_HALT)) { ELOG("Unable to reset device\n"); if (!settings->force) return false; @@ -268,13 +308,12 @@ static bool enable_trace(stlink_t *stlink, const st_settings_t *settings, STLINK_REG_DWT_CTRL_CYCCNT_ENA); stlink_write_debug32(stlink, STLINK_REG_DEMCR, STLINK_REG_DEMCR_TRCENA); - uint32_t prescaler; - stlink_read_debug32(stlink, STLINK_REG_TPI_ACPR_MAX, &prescaler); + uint32_t prescaler = 0; + stlink_read_debug32(stlink, STLINK_REG_TPI_ACPR, &prescaler); if (prescaler) { uint32_t system_clock_speed = (prescaler + 1) * trace_frequency; - uint32_t system_clock_speed_mhz = (system_clock_speed + 500000) / 1000000; - ILOG("Trace Port Interface configured to expect a %d MHz system clock.\n", - system_clock_speed_mhz); + ILOG("Trace Port Interface configured to expect a %d Hz system clock.\n", + system_clock_speed); } else { WLOG("Trace Port Interface not configured. Specify the system clock with " "a --clock=XX command\n"); @@ -440,13 +479,12 @@ static void check_for_configuration_error(stlink_t *stlink, st_trace_t *trace, } if (error_no_data || error_low_data || error_bad_data) { - uint32_t prescaler; + uint32_t prescaler = 0; stlink_read_debug32(stlink, STLINK_REG_TPI_ACPR, &prescaler); if (prescaler) { uint32_t system_clock_speed = (prescaler + 1) * trace_frequency; - uint32_t system_clock_speed_mhz = (system_clock_speed + 500000) / 1000000; - WLOG("Verify the system clock is running at %d MHz.\n", - system_clock_speed_mhz); + WLOG("Verify the system clock is running at %d Hz.\n", + system_clock_speed); } WLOG("Try specifying the system clock with the --clock=XX command line " "option.\n"); @@ -511,7 +549,6 @@ int main(int argc, char **argv) { } init_chipids (ETC_STLINK_DIR); - DLOG("show_help = %s\n", settings.show_help ? "true" : "false"); DLOG("show_version = %s\n", settings.show_version ? "true" : "false"); DLOG("logging_level = %d\n", settings.logging_level); @@ -563,9 +600,18 @@ int main(int argc, char **argv) { uint32_t trace_frequency = settings.trace_frequency; if (!trace_frequency) trace_frequency = STLINK_DEFAULT_TRACE_FREQUENCY; - if (trace_frequency > stlink->max_trace_freq) { - ELOG("Invalid trace frequency %d (max %d)\n", trace_frequency, - stlink->max_trace_freq); + uint32_t max_trace_freq = stlink->max_trace_freq; + uint32_t min_trace_freq = 0; + + if (settings.core_frequency != 0) { + if (max_trace_freq > settings.core_frequency / 5) + max_trace_freq = settings.core_frequency / 5; + min_trace_freq = settings.core_frequency / (STLINK_REG_TPI_ACPR_MAX + 1); + } + if (trace_frequency > max_trace_freq || + trace_frequency < min_trace_freq) { + ELOG("Invalid trace frequency %d (min %d max %d)\n", trace_frequency, + min_trace_freq, max_trace_freq); if (!settings.force) return APP_RESULT_UNSUPPORTED_TRACE_FREQUENCY; } From 0729558f2c9a5354b3d259cf887b9801678282b0 Mon Sep 17 00:00:00 2001 From: bauen1 Date: Mon, 9 May 2022 22:10:54 +0200 Subject: [PATCH 386/503] L4Rx: fix option byte address --- config/chips/L4Rx.chip | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/config/chips/L4Rx.chip b/config/chips/L4Rx.chip index b5c2d0d80..428a0c21e 100644 --- a/config/chips/L4Rx.chip +++ b/config/chips/L4Rx.chip @@ -9,6 +9,6 @@ flash_pagesize 0x1000 // 4 KB sram_size 0xa0000 // 640 KB bootrom_base 0x1fff0000 bootrom_size 0x7000 // 28 KB -option_base 0x0 -option_size 0x0 +option_base 0x1ff00000 +option_size 0x4 // 4 B flags swo From 54e82342f9b4f2e504fce501e30ab10045e8a166 Mon Sep 17 00:00:00 2001 From: simon-wh Date: Thu, 30 Jun 2022 17:55:27 +0100 Subject: [PATCH 387/503] Fix writing to 'BANK_2' in flash type F1_XL --- src/flashloader.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/flashloader.c b/src/flashloader.c index e4c7d7200..5592db477 100644 --- a/src/flashloader.c +++ b/src/flashloader.c @@ -94,7 +94,7 @@ static void set_flash_cr_pg(stlink_t *sl, unsigned bank) { cr_reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; x |= (1 << FLASH_H7_CR_PG); } else { - cr_reg = FLASH_CR; + cr_reg = (bank == BANK_1) ? FLASH_CR : FLASH_CR2; x = (1 << FLASH_CR_PG); } From 8956051ed5fc8ea124f48259e935aa90d9d95108 Mon Sep 17 00:00:00 2001 From: Jeroen de Bruijn Date: Thu, 14 Jul 2022 11:57:01 +0200 Subject: [PATCH 388/503] add `make install` to the MacOS building instructions This is required to get the `chips` directory in place. References #1237. --- doc/compiling.md | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/doc/compiling.md b/doc/compiling.md index 0931c278a..ec98fa5d5 100644 --- a/doc/compiling.md +++ b/doc/compiling.md @@ -215,7 +215,8 @@ To do this with only one simple command, type: 1. Change into the project source directory: `cd stlink` 2. Run `make clean` to clean remnants of any previous builds. 3. Run `make release` to create the _Release_ target -4. Run `make debug` to create the _Debug_ target (_optional_)
+4. Run `make install` to full install the package with complete system integration. This might require sudo permissions. +5. Run `make debug` to create the _Debug_ target (_optional_)
The debug target is only necessary in order to modify the sources and to run under a debugger. ## Build options From 9f0521016c415e58ce9bd27fd865b33d84aca980 Mon Sep 17 00:00:00 2001 From: Jeroen de Bruijn Date: Thu, 14 Jul 2022 16:34:51 +0200 Subject: [PATCH 389/503] add optional installation folder for macOS to compiling documentation --- doc/compiling.md | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/doc/compiling.md b/doc/compiling.md index ec98fa5d5..ec9d572ff 100644 --- a/doc/compiling.md +++ b/doc/compiling.md @@ -120,12 +120,12 @@ or execute (Debian-based systems only): `apt-get install gcc build-essential cma 1. Change into the project source directory: `cd stlink` 2. Run `make clean` -- required by some linux variants. 3. Run `make release` to create the _Release_ target -4. Run `make install` to full install the package with complete system integration +4. Run `make install` to full install the package with complete system integration. This might require sudo permissions. 5. Run `make debug` to create the _Debug_ target (_optional_)
The debug target is only necessary in order to modify the sources and to run under a debugger. 6. Run `make package`to build a Debian Package. The generated packages can be found in the subdirectory `./build/dist`. -As an option you may also install to an individual user-defined folder e.g `$HOME` with `make install DESTDIR=$HOME`. +> **Note** As an option you may also install to an individual user-defined folder e.g `$HOME` with `make install DESTDIR=$HOME`. #### Removal: @@ -219,6 +219,8 @@ To do this with only one simple command, type: 5. Run `make debug` to create the _Debug_ target (_optional_)
The debug target is only necessary in order to modify the sources and to run under a debugger. +> **Note** As an option you may also install to an individual user-defined folder e.g `$HOME` with `make install DESTDIR=$HOME`. + ## Build options ### Build using a different directory for shared libs From 87b21219a295e5080dcaf9e4b9ca38866eb14b5c Mon Sep 17 00:00:00 2001 From: Jeroen de Bruijn Date: Fri, 15 Jul 2022 08:16:57 +0200 Subject: [PATCH 390/503] remove note block from compiling docs note --- doc/compiling.md | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/doc/compiling.md b/doc/compiling.md index ec9d572ff..a82941e8a 100644 --- a/doc/compiling.md +++ b/doc/compiling.md @@ -125,7 +125,7 @@ or execute (Debian-based systems only): `apt-get install gcc build-essential cma The debug target is only necessary in order to modify the sources and to run under a debugger. 6. Run `make package`to build a Debian Package. The generated packages can be found in the subdirectory `./build/dist`. -> **Note** As an option you may also install to an individual user-defined folder e.g `$HOME` with `make install DESTDIR=$HOME`. +As an option you may also install to an individual user-defined folder e.g `$HOME` with `make install DESTDIR=$HOME`. #### Removal: @@ -219,7 +219,7 @@ To do this with only one simple command, type: 5. Run `make debug` to create the _Debug_ target (_optional_)
The debug target is only necessary in order to modify the sources and to run under a debugger. -> **Note** As an option you may also install to an individual user-defined folder e.g `$HOME` with `make install DESTDIR=$HOME`. +As an option you may also install to an individual user-defined folder e.g `$HOME` with `make install DESTDIR=$HOME`. ## Build options From 0e734a541b96dbf92be7b12c35cc7b2ce5e46569 Mon Sep 17 00:00:00 2001 From: Gwenhael Goavec-Merou Date: Mon, 22 Aug 2022 10:47:05 +0200 Subject: [PATCH 391/503] src/common_flash: fix flash regs addr for STM32L152RET6 --- src/common_flash.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/common_flash.c b/src/common_flash.c index e2a9ebbc3..72a36a288 100644 --- a/src/common_flash.c +++ b/src/common_flash.c @@ -21,6 +21,7 @@ uint32_t get_stm32l0_flash_base(stlink_t *sl) { case STM32_CHIPID_L1_MD: case STM32_CHIPID_L1_MD_PLUS: case STM32_CHIPID_L1_MD_PLUS_HD: + case STM32_CHIPID_L152_RE: return (STM32L_FLASH_REGS_ADDR); default: From c94b74e56a1522766937440c51a89a2cd968aeb2 Mon Sep 17 00:00:00 2001 From: Gwenhael Goavec-Merou Date: Thu, 25 Aug 2022 19:18:31 +0200 Subject: [PATCH 392/503] stm32l1: fix flash, dbgmcu and rcc registers --- inc/stm32.h | 7 +++++++ inc/stm32flash.h | 4 ++++ src/common.c | 12 +++++++++--- src/common_flash.c | 15 ++++++++++++--- src/flashloader.c | 9 +++++++-- 5 files changed, 39 insertions(+), 8 deletions(-) diff --git a/inc/stm32.h b/inc/stm32.h index 473f65a56..2d533eca2 100644 --- a/inc/stm32.h +++ b/inc/stm32.h @@ -167,6 +167,10 @@ enum stm32_chipids { #define STM32L0_DBGMCU_APB1_FZ_WWDG_STOP 11 #define STM32L0_DBGMCU_APB1_FZ_IWDG_STOP 12 +#define STM32L1_DBGMCU_APB1_FZ 0xE0042008 +#define STM32L1_DBGMCU_APB1_FZ_WWDG_STOP 11 +#define STM32L1_DBGMCU_APB1_FZ_IWDG_STOP 12 + #define STM32H7_DBGMCU_APB1HFZ 0x5C001054 #define STM32H7_DBGMCU_APB1HFZ_IWDG_STOP 18 @@ -189,6 +193,9 @@ enum stm32_chipids { #define STM32L0_RCC_AHBENR 0x40021030 #define STM32L0_RCC_DMAEN 0x00000001 // DMAEN +#define STM32L1_RCC_AHBENR 0x4002381C +#define STM32L1_RCC_DMAEN 0x30000000 // DMA2EN | DMA1EN + #define STM32H7_RCC_AHB1ENR 0x58024538 #define STM32H7_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN diff --git a/inc/stm32flash.h b/inc/stm32flash.h index 7e96d3f70..5e7ad2e4a 100644 --- a/inc/stm32flash.h +++ b/inc/stm32flash.h @@ -219,6 +219,10 @@ #define STM32L0_FLASH_SR_PGAERR 9 #define STM32L0_FLASH_SR_NOTZEROERR 16 +#define STM32L1_FLASH_SR_ERROR_MASK 0x00003F00 +#define STM32L1_FLASH_SR_WRPERR 8 +#define STM32L1_FLASH_SR_PGAERR 9 + #define FLASH_ACR_OFF ((uint32_t)0x00) #define FLASH_PECR_OFF ((uint32_t)0x04) #define FLASH_PDKEYR_OFF ((uint32_t)0x08) diff --git a/src/common.c b/src/common.c index c49830154..d360b5d03 100644 --- a/src/common.c +++ b/src/common.c @@ -991,9 +991,15 @@ static void stop_wdg_in_debug(stlink_t *sl) { break; case STM32_FLASH_TYPE_L0_L1: case STM32_FLASH_TYPE_G0: - dbgmcu_cr = STM32L0_DBGMCU_APB1_FZ; - set = (1 << STM32L0_DBGMCU_APB1_FZ_IWDG_STOP) | - (1 << STM32L0_DBGMCU_APB1_FZ_WWDG_STOP); + if (get_stm32l0_flash_base(sl) == STM32L_FLASH_REGS_ADDR) { + dbgmcu_cr = STM32L1_DBGMCU_APB1_FZ; + set = (1 << STM32L1_DBGMCU_APB1_FZ_IWDG_STOP) | + (1 << STM32L1_DBGMCU_APB1_FZ_WWDG_STOP); + } else { + dbgmcu_cr = STM32L0_DBGMCU_APB1_FZ; + set = (1 << STM32L0_DBGMCU_APB1_FZ_IWDG_STOP) | + (1 << STM32L0_DBGMCU_APB1_FZ_WWDG_STOP); + } break; case STM32_FLASH_TYPE_H7: dbgmcu_cr = STM32H7_DBGMCU_APB1HFZ; diff --git a/src/common_flash.c b/src/common_flash.c index e2a9ebbc3..df2619cad 100644 --- a/src/common_flash.c +++ b/src/common_flash.c @@ -155,7 +155,11 @@ void clear_flash_error(stlink_t *sl) { write_flash_sr(sl, BANK_1, STM32Gx_FLASH_SR_ERROR_MASK); break; case STM32_FLASH_TYPE_L0_L1: - write_flash_sr(sl, BANK_1, STM32L0_FLASH_SR_ERROR_MASK); + if (get_stm32l0_flash_base(sl) == STM32L_FLASH_REGS_ADDR) { + write_flash_sr(sl, BANK_1, STM32L1_FLASH_SR_ERROR_MASK); + } else { + write_flash_sr(sl, BANK_1, STM32L0_FLASH_SR_ERROR_MASK); + } break; case STM32_FLASH_TYPE_L4_L4P: write_flash_sr(sl, BANK_1, STM32L4_FLASH_SR_ERROR_MASK); @@ -281,9 +285,14 @@ int check_flash_error(stlink_t *sl) { PGAERR = (1 << STM32Gx_FLASH_SR_PGAERR); break; case STM32_FLASH_TYPE_L0_L1: - res = read_flash_sr(sl, BANK_1) & STM32L0_FLASH_SR_ERROR_MASK; + res = read_flash_sr(sl, BANK_1); + if (get_stm32l0_flash_base(sl) == STM32L_FLASH_REGS_ADDR) { + res &= STM32L1_FLASH_SR_ERROR_MASK; + } else { + res &= STM32L0_FLASH_SR_ERROR_MASK; + PROGERR = (1 << STM32L0_FLASH_SR_NOTZEROERR); + } WRPERR = (1 << STM32L0_FLASH_SR_WRPERR); - PROGERR = (1 << STM32L0_FLASH_SR_NOTZEROERR); PGAERR = (1 << STM32L0_FLASH_SR_PGAERR); break; case STM32_FLASH_TYPE_L4_L4P: diff --git a/src/flashloader.c b/src/flashloader.c index 5592db477..b9c26bf4c 100644 --- a/src/flashloader.c +++ b/src/flashloader.c @@ -127,8 +127,13 @@ static void set_dma_state(stlink_t *sl, flash_loader_t *fl, int bckpRstr) { rcc_dma_mask = STM32G4_RCC_DMAEN; break; case STM32_FLASH_TYPE_L0_L1: - rcc = STM32L0_RCC_AHBENR; - rcc_dma_mask = STM32L0_RCC_DMAEN; + if (get_stm32l0_flash_base(sl) == STM32L_FLASH_REGS_ADDR) { + rcc = STM32L1_RCC_AHBENR; + rcc_dma_mask = STM32L1_RCC_DMAEN; + } else { + rcc = STM32L0_RCC_AHBENR; + rcc_dma_mask = STM32L0_RCC_DMAEN; + } break; case STM32_FLASH_TYPE_H7: rcc = STM32H7_RCC_AHB1ENR; From 43498dedf651260ef34197e512d35e3ad7142401 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sat, 27 Aug 2022 12:23:02 +0200 Subject: [PATCH 393/503] General Project Update - Closes #1263. - Updated CHANGELOG.md - Updated list of contributors --- CHANGELOG.md | 14 +++++++++++++- contributors.txt | 3 +++ doc/compiling.md | 8 ++++++-- 3 files changed, 22 insertions(+), 3 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index 71188afb0..629b53233 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -22,12 +22,16 @@ Features: - Added support for STLINK-V3 devices with no MSD ([#1185](https://github.com/stlink-org/stlink/pull/1185)) - Updated gdb-server.c to allow external memory access on STM32H73xx ([#1196](https://github.com/stlink-org/stlink/pull/1196), [#1197](https://github.com/stlink-org/stlink/pull/1197)) - Erase addr size / section of the flash memory with st-flash ([#1213](https://github.com/stlink-org/stlink/pull/1213)) +- Added writing and reading for STM32WL option bytes ([#1226](https://github.com/stlink-org/stlink/pull/1226), [#1227](https://github.com/stlink-org/stlink/pull/1227)) +- Added parametres option_base, option_size for F401xD_xE ([#1235](https://github.com/stlink-org/stlink/pull/1235)) +- Added support for option bytes to F1xx_XLD (GD32F30x) ([#1250](https://github.com/stlink-org/stlink/pull/1250)) +- Added option byte address for L4Rx devices ([#1254](https://github.com/stlink-org/stlink/pull/1254)) Updates & changes: - [refactoring] Moved chip-specific parameters into separate files ([#237](https://github.com/stlink-org/stlink/pull/237), [#1129](https://github.com/stlink-org/stlink/pull/1129)) - Added instructions for bug-reports and feature-requests to contribution guidelines ([#906](https://github.com/stlink-org/stlink/pull/906)) -- Added travis CI configuration for macOS 10.14 to maintain capability for 32-bit compilation ([#f5ada94](https://github.com/stlink-org/stlink/commit/f5ada9474cdb87ff37de0d4eb9e75622b5870646)) +- Added travis CI configuration for macOS 10.14 to maintain capability for 32-bit compilation (commit [#f5ada94](https://github.com/stlink-org/stlink/commit/f5ada9474cdb87ff37de0d4eb9e75622b5870646)) - Updated description of chip id 0x0457 to L01x/L02x ([#1143](https://github.com/stlink-org/stlink/pull/1143), [#1144](https://github.com/stlink-org/stlink/pull/1144)) - Dropped execute bits from source code files ([#1167](https://github.com/stlink-org/stlink/pull/1167)) - Use proper Markdown headers for supported MCUs ([#1168](https://github.com/stlink-org/stlink/pull/1168)) @@ -35,6 +39,10 @@ Updates & changes: - Updated chip config files from the library structs ([#1181](https://github.com/stlink-org/stlink/pull/1181)) - [doc] Corrected file path in tutorial ([#1186](https://github.com/stlink-org/stlink/pull/1186)) - Improved chipid checks and printouts ([#1188](https://github.com/stlink-org/stlink/pull/1188)) +- [refactoring] Sourcefile 'common.c' ([#1218](https://github.com/stlink-org/stlink/pull/1218), [#1220](https://github.com/stlink-org/stlink/pull/1220)) +- Set C standard through cmake variables ([#1221](https://github.com/stlink-org/stlink/pull/1221)) +- [doc] Added make install to the macOS compiling instructions ([#1259](https://github.com/stlink-org/stlink/pull/1259)) +- [doc] Linux Install from code Documentation improvement ([#1263](https://github.com/stlink-org/stlink/pull/1263), (commit [#2926648](https://github.com/stlink-org/stlink/commit/2926648be78f32919c0624bf1060b17fffde8b0d)) Fixes: - cmake: Install shared libraries in proper directories ([#1142](https://github.com/stlink-org/stlink/pull/1142)) @@ -53,6 +61,10 @@ Fixes: - Define 'SSIZE_MAX' if not defined ([#1183](https://github.com/stlink-org/stlink/pull/1183)) - Fixed compliation for OpenBSD 7.0 ([#1202](https://github.com/stlink-org/stlink/pull/1202)) - Included 'SSIZE_MAX' from 'limits.h' in 'src/common.c' ([#1207](https://github.com/stlink-org/stlink/pull/1207)) +- Fix for libusb_kernel_driver_active & error handling for st.st_size () ([#1210](https://github.com/stlink-org/stlink/pull/1210), [#1211](https://github.com/stlink-org/stlink/pull/1211), [#1214](https://github.com/stlink-org/stlink/pull/1214) +- st-trace: Fixed clock issues ([#1251](https://github.com/stlink-org/stlink/pull/1251), [#1252](https://github.com/stlink-org/stlink/pull/1252)) +- Fixed flash regs addr for STM32L152RET6 in common_flash.c ([#1265](https://github.com/stlink-org/stlink/pull/1265)) +- Fixed flash, dbgmcu and rcc registers for STM32L1 ([#1266](https://github.com/stlink-org/stlink/pull/1266)) # v1.7.0 diff --git a/contributors.txt b/contributors.txt index cffef89f6..2425ae7f0 100644 --- a/contributors.txt +++ b/contributors.txt @@ -51,8 +51,10 @@ Greg Alexander [galexander1] Greg Meiste [meisteg] Grzegorz Szymaszek [gszy] Guillaume Revaillot [grevaillot] +Gwenhael Goavec-Merou [trabucayre] Hakkavélin Halt Hammerzeit +[hydroconstructor] htk Ian Griffiths Jack Peel @@ -115,6 +117,7 @@ Sean Simmons Sergey Alirzaev Simon Derr [sderr] Simon Wright +[simplerobot] Stany Marcel Stefan Misik Sven Wegener diff --git a/doc/compiling.md b/doc/compiling.md index a82941e8a..5d32385bd 100644 --- a/doc/compiling.md +++ b/doc/compiling.md @@ -119,7 +119,7 @@ or execute (Debian-based systems only): `apt-get install gcc build-essential cma 1. Change into the project source directory: `cd stlink` 2. Run `make clean` -- required by some linux variants. -3. Run `make release` to create the _Release_ target +3. Run `make release` to create the _Release_ target. 4. Run `make install` to full install the package with complete system integration. This might require sudo permissions. 5. Run `make debug` to create the _Debug_ target (_optional_)
The debug target is only necessary in order to modify the sources and to run under a debugger. @@ -127,6 +127,10 @@ or execute (Debian-based systems only): `apt-get install gcc build-essential cma As an option you may also install to an individual user-defined folder e.g `$HOME` with `make install DESTDIR=$HOME`. +### How to avoid the error message: "Can not open shared object file" + +When installing system-wide (`sudo make install`) the dynamic library cache needs to be updated with the command `ldconfig`. + #### Removal: 1. Run `make uninstall` to perform a clean uninstall of the package from the system. @@ -216,7 +220,7 @@ To do this with only one simple command, type: 2. Run `make clean` to clean remnants of any previous builds. 3. Run `make release` to create the _Release_ target 4. Run `make install` to full install the package with complete system integration. This might require sudo permissions. -5. Run `make debug` to create the _Debug_ target (_optional_)
+5. Run `make debug` to create the _Debug_ target. (_optional_)
The debug target is only necessary in order to modify the sources and to run under a debugger. As an option you may also install to an individual user-defined folder e.g `$HOME` with `make install DESTDIR=$HOME`. From 8835d387f21755ddb20699c9cece82cf52d54249 Mon Sep 17 00:00:00 2001 From: Robert Jenssen Date: Mon, 29 Aug 2022 10:23:59 +1000 Subject: [PATCH 394/503] Fix compilation with gcc-12 --- cmake/modules/c_flags.cmake | 1 + 1 file changed, 1 insertion(+) diff --git a/cmake/modules/c_flags.cmake b/cmake/modules/c_flags.cmake index 44052bba8..6e22d4ff3 100644 --- a/cmake/modules/c_flags.cmake +++ b/cmake/modules/c_flags.cmake @@ -20,6 +20,7 @@ endfunction() add_cflag_if_supported("-Wall") add_cflag_if_supported("-Wextra") add_cflag_if_supported("-Wshadow") +add_cflag_if_supported("-O") add_cflag_if_supported("-D_FORTIFY_SOURCE=2") add_cflag_if_supported("-fstrict-aliasing") add_cflag_if_supported("-Wundef") From 2087711c23d38280ad5f69c39f23e06e19f8f214 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 23 Oct 2022 20:22:16 +0200 Subject: [PATCH 395/503] General Project Update - Updated CHANGELOG.md - Updated README.md - Removed support for macOS (Closes #1269) --- .github/ISSUE_TEMPLATE/bug-report.md | 2 +- .github/workflows/c-cpp.yml | 82 --- CHANGELOG.md | 3 +- README.md | 14 +- cmake/modules/Findlibusb.cmake | 19 +- cmake/packaging/cpack_config.cmake | 7 +- cmake/packaging/deb/copyright | 1 - doc/compiling.md | 42 -- doc/dev/app-example/CMakeLists.txt | 3 +- doc/version_support.md | 9 - src/win32/getopt/getopt.c | 2 +- stlinkv1_macos_driver/Makefile | 58 --- stlinkv1_macos_driver/README.md | 39 -- stlinkv1_macos_driver/install.sh | 16 - .../Contents/Info.plist | 82 --- .../Contents/MacOS/stlink_shield_10_15 | Bin 33840 -> 0 bytes .../stlink_shield_10_15.kext/Contents/PkgInfo | 1 - .../Contents/_CodeSignature/CodeResources | 115 ----- .../stlink_shield_xcode/Info.plist | 60 --- .../stlink_shield.xcodeproj/project.pbxproj | 480 ------------------ .../contents.xcworkspacedata | 7 - .../xcshareddata/IDEWorkspaceChecks.plist | 8 - .../xcshareddata/WorkspaceSettings.xcsettings | 8 - .../UserInterfaceState.xcuserstate | Bin 187405 -> 0 bytes .../WorkspaceSettings.xcsettings | 24 - .../xcschemes/stlink_shield_10.14.xcscheme | 67 --- .../xcschemes/stlink_shield_10.15.xcscheme | 67 --- .../xcschemes/xcschememanagement.plist | 37 -- 28 files changed, 8 insertions(+), 1245 deletions(-) delete mode 100644 stlinkv1_macos_driver/Makefile delete mode 100644 stlinkv1_macos_driver/README.md delete mode 100644 stlinkv1_macos_driver/install.sh delete mode 100644 stlinkv1_macos_driver/stlink_shield_10_15.kext/Contents/Info.plist delete mode 100644 stlinkv1_macos_driver/stlink_shield_10_15.kext/Contents/MacOS/stlink_shield_10_15 delete mode 100644 stlinkv1_macos_driver/stlink_shield_10_15.kext/Contents/PkgInfo delete mode 100644 stlinkv1_macos_driver/stlink_shield_10_15.kext/Contents/_CodeSignature/CodeResources delete mode 100644 stlinkv1_macos_driver/stlink_shield_xcode/Info.plist delete mode 100644 stlinkv1_macos_driver/stlink_shield_xcode/stlink_shield.xcodeproj/project.pbxproj delete mode 100644 stlinkv1_macos_driver/stlink_shield_xcode/stlink_shield.xcodeproj/project.xcworkspace/contents.xcworkspacedata delete mode 100644 stlinkv1_macos_driver/stlink_shield_xcode/stlink_shield.xcodeproj/project.xcworkspace/xcshareddata/IDEWorkspaceChecks.plist delete mode 100644 stlinkv1_macos_driver/stlink_shield_xcode/stlink_shield.xcodeproj/project.xcworkspace/xcshareddata/WorkspaceSettings.xcsettings delete mode 100644 stlinkv1_macos_driver/stlink_shield_xcode/stlink_shield.xcodeproj/project.xcworkspace/xcuserdata/vm-user.xcuserdatad/UserInterfaceState.xcuserstate delete mode 100644 stlinkv1_macos_driver/stlink_shield_xcode/stlink_shield.xcodeproj/project.xcworkspace/xcuserdata/vm-user.xcuserdatad/WorkspaceSettings.xcsettings delete mode 100644 stlinkv1_macos_driver/stlink_shield_xcode/stlink_shield.xcodeproj/xcshareddata/xcschemes/stlink_shield_10.14.xcscheme delete mode 100644 stlinkv1_macos_driver/stlink_shield_xcode/stlink_shield.xcodeproj/xcshareddata/xcschemes/stlink_shield_10.15.xcscheme delete mode 100644 stlinkv1_macos_driver/stlink_shield_xcode/stlink_shield.xcodeproj/xcuserdata/vm-user.xcuserdatad/xcschemes/xcschememanagement.plist diff --git a/.github/ISSUE_TEMPLATE/bug-report.md b/.github/ISSUE_TEMPLATE/bug-report.md index c733c2c2e..690bceb3e 100644 --- a/.github/ISSUE_TEMPLATE/bug-report.md +++ b/.github/ISSUE_TEMPLATE/bug-report.md @@ -20,7 +20,7 @@ labels: "" In order to allow developers to isolate and target your respective issue, please take some time to select the check boxes below and fill out each of the following items appropriate to your specific problem. - [ ] Programmer/board type: [enter here] (e.g STLINK /V1, /V2, /V2-onboard, /V2-clone, /V3) -- [ ] Operating system an version: [enter here] (e.g Linux, macOS, Windows) +- [ ] Operating system an version: [enter here] (e.g Linux, Windows) - [ ] **stlink tools version** and/or git commit hash: [enter here] (e.g v1.6.1/git-d0416149) - [ ] stlink commandline tool name: [enter here] (e.g `st-info`, `st-flash`, `st-trace`, `st-util`) - [ ] Target chip (and board, if applicable): [enter here] (e.g STM32F103C8T6 (NUCLEO-F103RB)) diff --git a/.github/workflows/c-cpp.yml b/.github/workflows/c-cpp.yml index 442b3ba43..8e798269b 100644 --- a/.github/workflows/c-cpp.yml +++ b/.github/workflows/c-cpp.yml @@ -188,88 +188,6 @@ jobs: run: sudo make package - name: sudo make uninstall run: sudo make uninstall && sudo make clean - - # macOS - - job_macos_10_15_gcc: - name: macos-10.15 gcc - runs-on: macos-10.15 - steps: - - uses: actions/checkout@v2 - - name: Install dependencies - run: brew install gcc libusb gtk+3 - - name: make debug - run: sudo make clean && make debug - - name: make test - run: sudo make clean && make test - - name: make release - run: sudo make clean && make release - - name: sudo make install - run: sudo make clean && sudo make install - - name: sudo make package - run: sudo make package - - name: sudo make uninstall - run: sudo make uninstall && sudo make clean - - job_macos_10_15_clang: - name: macos-10.15 clang - runs-on: macos-10.15 - steps: - - uses: actions/checkout@v2 - - name: Install dependencies - run: brew install llvm libusb gtk+3 - - name: make debug - run: sudo make clean && make debug - - name: make test - run: sudo make clean && make test - - name: make release - run: sudo make clean && make release - - name: sudo make install - run: sudo make clean && sudo make install - - name: sudo make package - run: sudo make package - - name: sudo make uninstall - run: sudo make uninstall && sudo make clean - - # job_macos_11_gcc: - # name: macos-11.0 gcc - # runs-on: macos-11.0 - # steps: - # - uses: actions/checkout@v2 - # - name: Install dependencies - # run: brew install gcc libusb gtk+3 - # - name: make debug - # run: sudo make clean && make debug - # - name: make test - # run: sudo make clean && make test - # - name: make release - # run: sudo make clean && make release - # - name: sudo make install - # run: sudo make clean && sudo make install - # - name: sudo make package - # run: sudo make package - # - name: sudo make uninstall - # run: sudo make uninstall && sudo make clean - # job_macos_11_clang: - # name: macos-11.0 clang - # runs-on: macos-11.0 - # steps: - # - uses: actions/checkout@v2 - # - name: Install dependencies - # run: brew install llvm libusb gtk+3 - # - name: make debug - # run: sudo make clean && make debug - # - name: make test - # run: sudo make clean && make test - # - name: make release - # run: sudo make clean && make release - # - name: sudo make install - # run: sudo make clean && sudo make install - # - name: sudo make package - # run: sudo make package - # - name: sudo make uninstall - # run: sudo make uninstall && sudo make clean - # Linux MinGW cross compliation # job_linux_20_04_cross: diff --git a/CHANGELOG.md b/CHANGELOG.md index 629b53233..f48840c3f 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -42,7 +42,7 @@ Updates & changes: - [refactoring] Sourcefile 'common.c' ([#1218](https://github.com/stlink-org/stlink/pull/1218), [#1220](https://github.com/stlink-org/stlink/pull/1220)) - Set C standard through cmake variables ([#1221](https://github.com/stlink-org/stlink/pull/1221)) - [doc] Added make install to the macOS compiling instructions ([#1259](https://github.com/stlink-org/stlink/pull/1259)) -- [doc] Linux Install from code Documentation improvement ([#1263](https://github.com/stlink-org/stlink/pull/1263), (commit [#2926648](https://github.com/stlink-org/stlink/commit/2926648be78f32919c0624bf1060b17fffde8b0d)) +- [doc] Linux Install from code Documentation improvement ([#1263](https://github.com/stlink-org/stlink/pull/1263), (commit [#43498de](https://github.com/stlink-org/stlink/commit/43498dedf651260ef34197e512d35e3ad7142401)) Fixes: - cmake: Install shared libraries in proper directories ([#1142](https://github.com/stlink-org/stlink/pull/1142)) @@ -63,6 +63,7 @@ Fixes: - Included 'SSIZE_MAX' from 'limits.h' in 'src/common.c' ([#1207](https://github.com/stlink-org/stlink/pull/1207)) - Fix for libusb_kernel_driver_active & error handling for st.st_size () ([#1210](https://github.com/stlink-org/stlink/pull/1210), [#1211](https://github.com/stlink-org/stlink/pull/1211), [#1214](https://github.com/stlink-org/stlink/pull/1214) - st-trace: Fixed clock issues ([#1251](https://github.com/stlink-org/stlink/pull/1251), [#1252](https://github.com/stlink-org/stlink/pull/1252)) +- Fixed compilation with gcc-12 ([#1257](https://github.com/stlink-org/stlink/pull/1257), [#1267](https://github.com/stlink-org/stlink/pull/1267)) - Fixed flash regs addr for STM32L152RET6 in common_flash.c ([#1265](https://github.com/stlink-org/stlink/pull/1265)) - Fixed flash, dbgmcu and rcc registers for STM32L1 ([#1266](https://github.com/stlink-org/stlink/pull/1266)) diff --git a/README.md b/README.md index bc491189e..b889de389 100644 --- a/README.md +++ b/README.md @@ -9,7 +9,6 @@ [![CodeQL](https://github.com/stlink-org/stlink/actions/workflows/codeql-analysis.yml/badge.svg)](https://github.com/stlink-org/stlink/actions/workflows/codeql-analysis.yml) [![C/C++ CI](https://github.com/stlink-org/stlink/actions/workflows/c-cpp.yml/badge.svg?branch=testing)](https://github.com/stlink-org/stlink/actions/workflows/c-cpp.yml) [![Linux Status](https://img.shields.io/travis/stlink-org/stlink/master?env=BADGE=linux&label=linux)](https://travis-ci.org/stlink-org/stlink) -[![macOS Status](https://img.shields.io/travis/stlink-org/stlink/master?env=BADGE=osx&label=osx)](https://travis-ci.org/stlink-org/stlink) Recent new features and bugfixes can be found in the [Changelog](CHANGELOG.md) of this software project. @@ -22,7 +21,7 @@ The stlink library and tools are licensed under the **[BSD-3 License](LICENSE.md stlink is an open source toolset to program and debug STM32 devices and boards manufactured by STMicroelectronics. It supports several so called STLINK programmer boards (and clones thereof) which use a microcontroller chip to translate commands from USB to JTAG/SWD. There are four generations available on the market which are _all_ supported by this toolset: -- **STLINK/V1** _[obsolete as of 21-11-2019, continued support by this toolset] \*)_ +- **STLINK/V1** _[obsolete as of 21-11-2019, continued support by this toolset]_ - transport layer: SCSI passthru commands over USB - stand-alone programmer - on-board on STM32VL Discovery boards @@ -38,8 +37,6 @@ It supports several so called STLINK programmer boards (and clones thereof) whic - stand-alone programmer (STLINK-V3SET, STLINK-V3MINI, STLINK-V3MODS) - on-board on some STM32 Nucleo boards (STLINK-V3E) -_\*)_ *Note: Support for the STLINK/V1 on macOS is limited to 10.15. Due to the deprecation and removal of macOS Kernel Extensions (KEXT) there will be no support for this programmer on macOS 11 or any later version.* - On the user level there is no difference in handling or operation between these different revisions. The STlink toolset includes: @@ -70,15 +67,6 @@ Please ensure to select the correct version for your system (i686 or x86_64). Th Alternatively one may compile and install from source as described in our [compiling manual](doc/compiling.md#Windows). -**macOS**: - -We recommend to install from: - -- [homebrew](https://formulae.brew.sh/formula/stlink) or -- [MacPorts](https://ports.macports.org/port/stlink) - -Alternatively one can compile and install from source as described in our [compiling manual](doc/compiling.md#macOS). - **Linux**: We recommend to install `stlink-tools` from the package repository of the used distribution: diff --git a/cmake/modules/Findlibusb.cmake b/cmake/modules/Findlibusb.cmake index de3712eca..7442c8cc4 100644 --- a/cmake/modules/Findlibusb.cmake +++ b/cmake/modules/Findlibusb.cmake @@ -10,24 +10,7 @@ include(FindPackageHandleStandardArgs) -if (APPLE) # macOS - FIND_PATH( - LIBUSB_INCLUDE_DIR NAMES libusb.h - HINTS /usr /usr/local /opt - PATH_SUFFIXES libusb-1.0 - ) - set(LIBUSB_NAME libusb-1.0.a) - find_library( - LIBUSB_LIBRARY NAMES ${LIBUSB_NAME} - HINTS /usr /usr/local /opt - ) - FIND_PACKAGE_HANDLE_STANDARD_ARGS(libusb DEFAULT_MSG LIBUSB_LIBRARY LIBUSB_INCLUDE_DIR) - mark_as_advanced(LIBUSB_INCLUDE_DIR LIBUSB_LIBRARY) - if (NOT LIBUSB_FOUND) - message(FATAL_ERROR "No libusb library found on your system! Install libusb-1.0 from Homebrew or MacPorts") - endif () - -elseif (CMAKE_SYSTEM_NAME STREQUAL "FreeBSD") # FreeBSD; libusb is integrated into the system +if (CMAKE_SYSTEM_NAME STREQUAL "FreeBSD") # FreeBSD; libusb is integrated into the system FIND_PATH( LIBUSB_INCLUDE_DIR NAMES libusb.h HINTS /usr/include diff --git a/cmake/packaging/cpack_config.cmake b/cmake/packaging/cpack_config.cmake index a4f1ae073..8766fb2e0 100644 --- a/cmake/packaging/cpack_config.cmake +++ b/cmake/packaging/cpack_config.cmake @@ -15,12 +15,7 @@ set(CPACK_SET_DESTDIR "ON") file(MAKE_DIRECTORY ${CMAKE_BINARY_DIR}/dist) set(CPACK_OUTPUT_FILE_PREFIX "${CMAKE_BINARY_DIR}/dist") -if (APPLE) # macOS - set(CPACK_GENERATOR "ZIP") - set(CPACK_PACKAGE_FILE_NAME "${PROJECT_NAME}-${PROJECT_VERSION}-macos-amd64") - set(CPACK_INSTALL_PREFIX "") - -elseif (WIN32 AND (NOT EXISTS "/etc/debian_version")) # Windows +if (WIN32 AND (NOT EXISTS "/etc/debian_version")) # Windows set(CPACK_GENERATOR "ZIP") set(CPACK_PACKAGE_FILE_NAME "${PROJECT_NAME}-${PROJECT_VERSION}-win32") set(CPACK_INSTALL_PREFIX "") diff --git a/cmake/packaging/deb/copyright b/cmake/packaging/deb/copyright index f5dfdc51b..c8ff30973 100644 --- a/cmake/packaging/deb/copyright +++ b/cmake/packaging/deb/copyright @@ -2,7 +2,6 @@ Format: https://www.debian.org/doc/packaging-manuals/copyright-format/1.0/ Upstream-Name: stlink Upstream-Contact: Nightwalker-87 Source: https://github.com/stlink-org/stlink -Files-Excluded: stlinkv1_macos_driver Files: * Copyright: 2011-2020 stlink-org diff --git a/doc/compiling.md b/doc/compiling.md index 5d32385bd..5f6852a93 100644 --- a/doc/compiling.md +++ b/doc/compiling.md @@ -183,48 +183,6 @@ Choose one of the following options _before_ connecting the device to your compu 1. `cp stlink_v1.modprobe.conf /etc/modprobe.d` 2. `modprobe -r usb-storage && modprobe usb-storage` -## macOS - -### Common requirements - -The best and recommended way is to install a package manager for open source software, -either [homebrew](https://brew.sh) or [MacPorts](https://www.macports.org/). - -Then install the following dependencies from the package repository: - -- `git` -- `gcc` or `llvm` (for clang) (C-compiler) -- `cmake` -- `libusb` -- `gtk+3` or `gtk3` (_optional_, needed for `stlink-gui`) - -To do this with only one simple command, type: - -- for homebrew: - - with gcc: `sudo brew install git gcc cmake libusb gtk+3` or - - with clang: `sudo brew install git llvm cmake libusb gtk+3` or -- for MacPorts: - - with gcc: `sudo port install git gcc10 cmake libusb gtk3` or - - with clang: `sudo port install git llvm-10 cmake libusb gtk3` - -### Installation - -1. Open a new terminal window -2. Create a new destination folder at a place of your choice e.g. at `~/git`: `mkdir $HOME/git` -3. Change to this directory: `cd ~/git` -4. Fetch the project sourcefiles by running `git clone https://github.com/stlink-org/stlink.git` - -### Building - -1. Change into the project source directory: `cd stlink` -2. Run `make clean` to clean remnants of any previous builds. -3. Run `make release` to create the _Release_ target -4. Run `make install` to full install the package with complete system integration. This might require sudo permissions. -5. Run `make debug` to create the _Debug_ target. (_optional_)
- The debug target is only necessary in order to modify the sources and to run under a debugger. - -As an option you may also install to an individual user-defined folder e.g `$HOME` with `make install DESTDIR=$HOME`. - ## Build options ### Build using a different directory for shared libs diff --git a/doc/dev/app-example/CMakeLists.txt b/doc/dev/app-example/CMakeLists.txt index 5f71a5d4f..69ba2090e 100644 --- a/doc/dev/app-example/CMakeLists.txt +++ b/doc/dev/app-example/CMakeLists.txt @@ -1,6 +1,5 @@ # Warning: This example assumes that you are building on a host with pkg-config available (e.g. linux). -# The logic required to build under windows/mingw and/or mac was intentionally omitted to keep this -# CMakeLists as small as possible. +# The logic required to build under windows/mingw was intentionally omitted to keep this CMakeLists as small as possible. cmake_minimum_required(VERSION 3.4.2) diff --git a/doc/version_support.md b/doc/version_support.md index 01d9dddb1..0f1849697 100644 --- a/doc/version_support.md +++ b/doc/version_support.md @@ -10,15 +10,6 @@ Up on compiling c-make will **automatically** download and install the latest co - Windows 10 - Windows 8.1 -### Apple macOS - -| Package Repository | libusb | cmake | gtk-3-dev | Supported macOS versions | -| ------------------ | ------ | ------ | ------------------ | ------------------------ | -| homebrew | 1.0.25 | 3.22.1 | 3.24.30
gtk+3 | **10.10 - 12.x** | -| MacPorts | 1.0.25 | 3.22.1 | 3.24.31
gtk3 | **10.4 - 12.x** | - -NOTE: In order to use a STLINK/V1 programmer on macOS, version 10.15 is required. - ### Linux-/Unix-based: | Operating System | libusb | cmake | libgtk-dev | Notes | diff --git a/src/win32/getopt/getopt.c b/src/win32/getopt/getopt.c index 85e8804d8..ff0a2fd91 100644 --- a/src/win32/getopt/getopt.c +++ b/src/win32/getopt/getopt.c @@ -179,7 +179,7 @@ int getopt_long(int argc, if (match->has_arg == required_argument) { /* Only scan the next argv for required arguments. Behavior is not - specified, but has been observed with Ubuntu and macOS. */ + specified, but has been observed with Ubuntu. */ if (optarg == NULL && ++optind < argc) { optarg = argv[optind]; } if (optarg == NULL) { retval = ':'; } diff --git a/stlinkv1_macos_driver/Makefile b/stlinkv1_macos_driver/Makefile deleted file mode 100644 index e6ba6309b..000000000 --- a/stlinkv1_macos_driver/Makefile +++ /dev/null @@ -1,58 +0,0 @@ -### -# Makefile for STlink-v1 support -### - -VPATH=src - -SOURCES_LIB=common.c usb.c sg.c logging.c -OBJS_LIB=$(SOURCES_LIB:.c=.o) -TEST_PROGRAMS=test-flash test-sg test-usb -LDFLAGS=-L. -lstlink -lusb-1.0 - -CFLAGS+=-g -CFLAGS+=-DDEBUG=1 -CFLAGS+=-std=gnu11 -CFLAGS+=-Wall -Wextra - - -LIBRARY=libstlink.a - -all: $(LIBRARY) flash gdbserver $(TEST_PROGRAMS) - -$(LIBRARY): $(OBJS_LIB) - @echo "objs are $(OBJS_LIB)" - $(AR) -cr $@ $^ - @echo "Compilation of library completed." - - -test_sg: test_sg.o $(LIBRARY) - @echo "building test_sg" - $(CC) test_sg.o $(LDFLAGS) -o $@ - -test_usb: test_usb.o $(LIBRARY) - @echo "building test_usb" - $(CC) test_usb.o $(LDFLAGS) -o $@ - @echo "done linking" - -%.o: %.c - @echo "building $^ into $@" - $(CC) $(CFLAGS) -c $^ -o $@ - @echo "done compiling" - -clean: - rm -rf $(OBJS_LIB) - rm -rf $(LIBRARY) - rm -rf test-flash* test-sg* test-usb* - $(MAKE) -C flash clean - $(MAKE) -C gdbserver clean - -flash: - $(MAKE) -C flash - -gdbserver: - $(MAKE) -C gdbserver CONFIG_USE_LIBSG="$(CONFIG_USE_LIBSG)" - -macos_stlink_shield: - ./install.sh - -.PHONY: clean all flash gdbserver diff --git a/stlinkv1_macos_driver/README.md b/stlinkv1_macos_driver/README.md deleted file mode 100644 index e0f9256e8..000000000 --- a/stlinkv1_macos_driver/README.md +++ /dev/null @@ -1,39 +0,0 @@ -# Installation instructions for STLINK/v1 driver - -When connecting to the STLINK/v1 on macOS via USB, the system claims the programmer as a SCSI device. Thus libusb is not able to initialise and establish a connection to it. To solve this issue Marco Cassinerio (marco.cassinerio@gmail.com) has created a so called "codeless driver" which claims the device. It is of higher priority then the default apple mass storage driver, what allows the device to be accessed through libusb. - -To make use of this alternative approach one needs to go through the following steps: - -1) Configure System Integrity Protection (SIP) - -The above system security setting introduced by Apple with OS X El Capitan (10.11) in 2015 is active per default -and prevents the operating system amongst other things to load unsigned Kernel Extension Modules (kext). -Thus the STLINK/v1 driver supplied with the tools, which installs as a kext, remains not functional, -until SIP is fully deactivated. Without SIP-deactivation, st-util would fail to detect a STLINK/v1 device later on. - -In order to deactivate SIP, boot into the recovery mode and run ```csrutil disable``` in a terminal console window. - -2) Reboot the system. - -3) Install the macOS Kernel Extension (kext) (ST-Link-v1 driver): - - Open a terminal console and navigate to this subdirectory `/stlinkv1_macos_driver` - - Use the command ```sudo sh ./install.sh``` to install the appropiate kext for your system version. - This should result in the following output: - -``` -Requesting load of /Library/Extensions/stlink_shield.kext. -/Library/Extensions/stlink_shield.kext loaded successfully (or already loaded). -``` -4) Reboot the system. - -5) Verify correct detection of the STLINK/v1 device with the following input: `st-util -1` -You should then see a similar output like in this example: - -``` -INFO common.c: Loading device parameters.... -INFO common.c: Device connected is: F1 High-density device, id 0x10036414 -INFO common.c: SRAM size: 0x10000 bytes (64 KiB), Flash: 0x80000 bytes (512 KiB) in pages of 2048 bytes -INFO sg.c: Successfully opened a stlink v1 debugger -INFO gdb-server.c: Chip ID is 00000414, Core ID is 1ba01477. -INFO gdb-server.c: Listening at *:4242... -``` diff --git a/stlinkv1_macos_driver/install.sh b/stlinkv1_macos_driver/install.sh deleted file mode 100644 index f9878bd46..000000000 --- a/stlinkv1_macos_driver/install.sh +++ /dev/null @@ -1,16 +0,0 @@ -#!/bin/bash - -ISMACOS=$(sw_vers -productVersion) -case $ISMACOS in -10.15*) - KEXT="stlink_shield_10_15.kext" - ;; -*) - echo "OS X version not supported." - exit 1 - ;; -esac -chown -R root:wheel $KEXT/ -cp -R $KEXT /Library/Extensions/stlink_shield.kext -kextload -v /Library/Extensions/stlink_shield.kext -touch /Library/Extensions diff --git a/stlinkv1_macos_driver/stlink_shield_10_15.kext/Contents/Info.plist b/stlinkv1_macos_driver/stlink_shield_10_15.kext/Contents/Info.plist deleted file mode 100644 index 2077b9c8a..000000000 --- a/stlinkv1_macos_driver/stlink_shield_10_15.kext/Contents/Info.plist +++ /dev/null @@ -1,82 +0,0 @@ - - - - - BuildMachineOSBuild - 18G7016 - CFBundleDevelopmentRegion - English - CFBundleIdentifier - com.libusb.stlink-shield - CFBundleInfoDictionaryVersion - 6.0 - CFBundlePackageType - KEXT - CFBundleSignature - ???? - CFBundleSupportedPlatforms - - MacOSX - - CFBundleVersion - 1.0.0 - DTCompiler - com.apple.compilers.llvm.clang.1_0 - DTPlatformBuild - 11C504 - DTPlatformVersion - GM - DTSDKBuild - 19B90 - DTSDKName - macosx10.15 - DTXcode - 1130 - DTXcodeBuild - 11C504 - IOKitPersonalities - - DeviceDriver - - CFBundleIdentifier - com.apple.kpi.iokit - IOClass - IOService - IOProviderClass - IOUSBDevice - bcdDevice - 256 - idProduct - 14148 - idVendor - 1155 - - InterfaceDriver - - CFBundleIdentifier - com.apple.kpi.iokit - IOClass - IOService - IOProviderClass - IOUSBInterface - bConfigurationValue - 1 - bInterfaceNumber - 0 - idProduct - 14148 - idVendor - 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- IssueFilterStyle - ShowAll - LiveSourceIssuesEnabled - - SharedBuildFolderName - Build - - diff --git a/stlinkv1_macos_driver/stlink_shield_xcode/stlink_shield.xcodeproj/xcshareddata/xcschemes/stlink_shield_10.14.xcscheme b/stlinkv1_macos_driver/stlink_shield_xcode/stlink_shield.xcodeproj/xcshareddata/xcschemes/stlink_shield_10.14.xcscheme deleted file mode 100644 index 79299d7a5..000000000 --- a/stlinkv1_macos_driver/stlink_shield_xcode/stlink_shield.xcodeproj/xcshareddata/xcschemes/stlink_shield_10.14.xcscheme +++ /dev/null @@ -1,67 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/stlinkv1_macos_driver/stlink_shield_xcode/stlink_shield.xcodeproj/xcshareddata/xcschemes/stlink_shield_10.15.xcscheme b/stlinkv1_macos_driver/stlink_shield_xcode/stlink_shield.xcodeproj/xcshareddata/xcschemes/stlink_shield_10.15.xcscheme deleted file mode 100644 index e72a90366..000000000 --- a/stlinkv1_macos_driver/stlink_shield_xcode/stlink_shield.xcodeproj/xcshareddata/xcschemes/stlink_shield_10.15.xcscheme +++ /dev/null @@ -1,67 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/stlinkv1_macos_driver/stlink_shield_xcode/stlink_shield.xcodeproj/xcuserdata/vm-user.xcuserdatad/xcschemes/xcschememanagement.plist b/stlinkv1_macos_driver/stlink_shield_xcode/stlink_shield.xcodeproj/xcuserdata/vm-user.xcuserdatad/xcschemes/xcschememanagement.plist deleted file mode 100644 index c9d1a75b6..000000000 --- a/stlinkv1_macos_driver/stlink_shield_xcode/stlink_shield.xcodeproj/xcuserdata/vm-user.xcuserdatad/xcschemes/xcschememanagement.plist +++ /dev/null @@ -1,37 +0,0 @@ - - - - - SchemeUserState - - stlink_shield_10.14.xcscheme_^#shared#^_ - - orderHint - 0 - - stlink_shield_10.15.xcscheme_^#shared#^_ - - orderHint - 1 - - - SuppressBuildableAutocreation - - 8F9084E724786F0B009109AD - - primary - - - 8F9084F324786F0F009109AD - - primary - - - 8F9084FF24786F39009109AD - - primary - - - - - From ff8114895a9fc32cae6a9374e58eac6256d68183 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 23 Oct 2022 20:40:43 +0200 Subject: [PATCH 396/503] Corrected sram_size for L496x/L4A6x devices (Closes #1268) --- config/chips/L496x_L4A6x.chip | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/config/chips/L496x_L4A6x.chip b/config/chips/L496x_L4A6x.chip index df1f084ff..6657d5484 100644 --- a/config/chips/L496x_L4A6x.chip +++ b/config/chips/L496x_L4A6x.chip @@ -6,7 +6,7 @@ chip_id 0x461 // STM32_CHIPID_L496x_L4A6x flash_type L4_L4P flash_size_reg 0x1fff75e0 flash_pagesize 0x800 // 2 KB -sram_size 0x40000 // 256 KB +sram_size 0x50000 // 320 KB bootrom_base 0x1fff0000 bootrom_size 0x7000 // 28 KB option_base 0x1fff7800 // STM32_L4_OPTION_BYTES_BASE From f93adb92f2e4ecf05a9361cb723c98693586929d Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Mon, 24 Oct 2022 01:49:03 +0200 Subject: [PATCH 397/503] Fixes for project compilation - Cleanup for CMakeLists.txt - [doc] Added list of cmake path variables - Fixed stlink-gui install path (Closes #1270) (Closes #1271) - Replaced path variable for chips directory --- CMakeLists.txt | 105 +++++++++++++++++++---------- cmake/packaging/cpack_config.cmake | 2 +- doc/man/CMakeLists.txt | 2 +- src/st-flash/flash.c | 2 +- src/st-info/info.c | 2 +- src/st-trace/trace.c | 2 +- src/st-util/gdb-server.c | 2 +- src/stlink-gui/CMakeLists.txt | 10 +-- src/stlink-gui/gui.c | 2 +- tests/CMakeLists.txt | 2 +- 10 files changed, 83 insertions(+), 48 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index 67f76ec08..94721f213 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -13,22 +13,69 @@ set(CMAKE_C_STANDARD 11) set(CMAKE_C_STANDARD_REQUIRED ON) set(CMAKE_C_EXTENSIONS ON) +### +# +# Default cmake directories: +# +# | Target Type | GNUInstallDirs Variable | Built-In Default | +# | --- | --- | --- | +# | RUNTIME | ${CMAKE_INSTALL_BINDIR} | bin | +# | LIBRARY | ${CMAKE_INSTALL_LIBDIR} | lib | +# | ARCHIVE | ${CMAKE_INSTALL_LIBDIR} | lib | +# | PRIVATE_HEADER | ${CMAKE_INSTALL_INCLUDEDIR} | include | +# | PUBLIC_HEADER | ${CMAKE_INSTALL_INCLUDEDIR} | include | +# | FILE_SET (type HEADERS) | ${CMAKE_INSTALL_INCLUDEDIR} | include | +# +# | TYPE Argument | GNUInstallDirs Variable | Built-In Default | +# | --- | --- | --- | +# | BIN | ${CMAKE_INSTALL_BINDIR} | bin | +# | SBIN | ${CMAKE_INSTALL_SBINDIR} | sbin | +# | LIB | ${CMAKE_INSTALL_LIBDIR} | lib | +# | INCLUDE | ${CMAKE_INSTALL_INCLUDEDIR} | include | +# | SYSCONF | ${CMAKE_INSTALL_SYSCONFDIR} | etc | +# | SHAREDSTATE | ${CMAKE_INSTALL_SHARESTATEDIR} | com | +# | LOCALSTATE | ${CMAKE_INSTALL_LOCALSTATEDIR} | var | +# | RUNSTATE | ${CMAKE_INSTALL_RUNSTATEDIR} | /run | +# | DATA | ${CMAKE_INSTALL_DATADIR} | | +# | INFO | ${CMAKE_INSTALL_INFODIR} | /info | +# | LOCALE | ${CMAKE_INSTALL_LOCALEDIR} | /locale | +# | MAN | ${CMAKE_INSTALL_MANDIR} | /man | +# | DOC | ${CMAKE_INSTALL_DOCDIR} | /doc | +# +# ${CMAKE_BINARY_DIR} +# This is the full path to the top level of the current CMake build tree. +# For an in-source build, this would be the same as CMAKE_SOURCE_DIR. +# +# ${CMAKE_SOURCE_DIR} +# This is the full path to the top level of the current CMake source tree. +# For an in-source build, this would be the same as CMAKE_BINARY_DIR. +# +# ${CMAKE_CURRENT_BINARY_DIR} +# The path to the binary directory currently being processed. +# This is the full path to the build directory that is currently being processed by cmake. +# Each directory added by add_subdirectory() will create a binary directory in the build tree, +# and as it is being processed this variable will be set. +# For in-source builds this is the current source directory being processed. +# +# ${CMAKE_CURRENT_SOURCE_DIR} +# The path to the source directory currently being processed. +# This is the full path to the source directory that is currently being processed by cmake. +# +### + ### -# General project settings +# General Project Settings ### project(stlink C) set(PROJECT_DESCRIPTION "Open source version of the STMicroelectronics ST-LINK Tools") -include(GNUInstallDirs) # Define GNU standard installation directories +include(${CMAKE_MODULE_PATH}/get_version.cmake) # Determine project version -## MCU configuration files -set(CMAKE_CHIPS_SUBDIR stlink/chips) -set(CMAKE_CHIPS_DIR ${CMAKE_INSTALL_PREFIX}/${CMAKE_CHIPS_SUBDIR}) -add_definitions( -DETC_STLINK_DIR="${CMAKE_CHIPS_DIR}" ) +include(GNUInstallDirs) # Define GNU standard installation directories -## Determine project version -include(${CMAKE_MODULE_PATH}/get_version.cmake) +# Define install directory /usr/share +set(CMAKE_INSTALL_SHAREDIR /usr/share/) ## Set C build flags if (NOT MSVC) @@ -178,8 +225,6 @@ endif () # Libraries ### -set(STLINK_LIBRARY_PATH ${CMAKE_INSTALL_LIBDIR} CACHE PATH "Main library install directory") - # Set the environment variable LD_LIBRARY_PATH to point to /usr/local/lib (per default). execute_process(COMMAND bash -c "export LD_LIBRARY_PATH=${CMAKE_INSTALL_LIBDIR}") @@ -205,21 +250,15 @@ set_target_properties(${STLINK_LIB_SHARED} PROPERTIES ) # Link shared library -if (APPLE) # ... with Apple macOS libraries - find_library(ObjC objc) - find_library(CoreFoundation CoreFoundation) - find_library(IOKit IOKit) - find_library(Security Security) - target_link_libraries(${STLINK_LIB_SHARED} ${LIBUSB_LIBRARY} ${SSP_LIB} ${ObjC} ${CoreFoundation} ${IOKit} ${Security}) -elseif (WIN32) # ... with Windows libraries +if (WIN32) # ... with Windows libraries target_link_libraries(${STLINK_LIB_SHARED} ${LIBUSB_LIBRARY} ${SSP_LIB} wsock32 ws2_32) else () target_link_libraries(${STLINK_LIB_SHARED} ${LIBUSB_LIBRARY} ${SSP_LIB}) endif () install(TARGETS ${STLINK_LIB_SHARED} - ARCHIVE DESTINATION ${STLINK_LIBRARY_PATH} - LIBRARY DESTINATION ${STLINK_LIBRARY_PATH} + ARCHIVE DESTINATION ${CMAKE_INSTALL_LIBDIR} + LIBRARY DESTINATION ${CMAKE_INSTALL_LIBDIR} RUNTIME DESTINATION ${CMAKE_INSTALL_BINDIR} ) @@ -248,19 +287,13 @@ set_target_properties(${STLINK_LIB_STATIC} PROPERTIES ) # Link static library -if (APPLE) # ... with Apple macOS libraries - find_library(ObjC objc) - find_library(CoreFoundation CoreFoundation) - find_library(IOKit IOKit) - find_library(Security Security) - target_link_libraries(${STLINK_LIB_STATIC} ${LIBUSB_LIBRARY} ${SSP_LIB} ${ObjC} ${CoreFoundation} ${IOKit} ${Security}) -elseif (WIN32) # ... with Windows libraries +if (WIN32) # ... with Windows libraries target_link_libraries(${STLINK_LIB_STATIC} ${LIBUSB_LIBRARY} ${SSP_LIB} wsock32 ws2_32) else () target_link_libraries(${STLINK_LIB_STATIC} ${LIBUSB_LIBRARY} ${SSP_LIB}) endif () -install(TARGETS ${STLINK_LIB_STATIC} ARCHIVE DESTINATION ${STLINK_LIBRARY_PATH}) +install(TARGETS ${STLINK_LIB_STATIC} ARCHIVE DESTINATION ${CMAKE_INSTALL_LIBDIR}) ### @@ -284,7 +317,7 @@ add_executable(st-info ${ST-INFO_SOURCES}) add_executable(st-util ${ST-UTIL_SOURCES}) add_executable(st-trace ${ST-TRACE_SOURCES}) -if (WIN32 OR APPLE) +if (WIN32) target_link_libraries(st-flash ${STLINK_LIB_STATIC} ${SSP_LIB}) target_link_libraries(st-info ${STLINK_LIB_STATIC} ${SSP_LIB}) target_link_libraries(st-util ${STLINK_LIB_STATIC} ${SSP_LIB}) @@ -301,10 +334,6 @@ install(TARGETS st-info DESTINATION ${CMAKE_INSTALL_BINDIR}) install(TARGETS st-util DESTINATION ${CMAKE_INSTALL_BINDIR}) install(TARGETS st-trace DESTINATION ${CMAKE_INSTALL_BINDIR}) -# Install MCU configuration files -file(GLOB CHIP_FILES ${CMAKE_SOURCE_DIR}/config/chips/*.chip) -install(FILES ${CHIP_FILES} DESTINATION ${CMAKE_CHIPS_DIR}) - ### # Device configuration (Linux only) @@ -326,13 +355,19 @@ endif () # Additional build tasks ### -add_subdirectory(src/stlink-gui) # contains subordinate CMakeLists to build GUI -add_subdirectory(tests) # contains subordinate CMakeLists to build test executables -add_subdirectory(cmake/packaging) # contains subordinate CMakeLists to build packages +# MCU configuration files +set(CMAKE_CHIPS_DIR ${CMAKE_INSTALL_SHAREDIR}/${PROJECT_NAME}/chips) +add_definitions( -DSTLINK_CHIPS_DIR="${CMAKE_CHIPS_DIR}" ) +file(GLOB CHIP_FILES ${CMAKE_SOURCE_DIR}/config/chips/*.chip) +install(FILES ${CHIP_FILES} DESTINATION ${CMAKE_CHIPS_DIR}) +# Documentation / manpages option(STLINK_GENERATE_MANPAGES "Generate manpages with pandoc" OFF) add_subdirectory(doc/man) # contains subordinate CMakeLists to generate manpages +add_subdirectory(src/stlink-gui) # contains subordinate CMakeLists to build GUI +add_subdirectory(tests) # contains subordinate CMakeLists to build test executables +add_subdirectory(cmake/packaging) # contains subordinate CMakeLists to build packages ### # Uninstall target diff --git a/cmake/packaging/cpack_config.cmake b/cmake/packaging/cpack_config.cmake index 8766fb2e0..55a859189 100644 --- a/cmake/packaging/cpack_config.cmake +++ b/cmake/packaging/cpack_config.cmake @@ -20,7 +20,7 @@ if (WIN32 AND (NOT EXISTS "/etc/debian_version")) # Wi set(CPACK_PACKAGE_FILE_NAME "${PROJECT_NAME}-${PROJECT_VERSION}-win32") set(CPACK_INSTALL_PREFIX "") -elseif (WIN32) # Windows cross-build on Debian/Ubuntu +elseif (WIN32) # Windows cross-build on Debian/Ubuntu set(CPACK_GENERATOR "ZIP") set(CPACK_PACKAGE_FILE_NAME "${PROJECT_NAME}-${PROJECT_VERSION}-${TOOLCHAIN_PREFIX}") set(CPACK_INSTALL_PREFIX "") diff --git a/doc/man/CMakeLists.txt b/doc/man/CMakeLists.txt index 9b3c50764..1b7d6501f 100644 --- a/doc/man/CMakeLists.txt +++ b/doc/man/CMakeLists.txt @@ -30,7 +30,7 @@ foreach (manpage ${MANPAGES}) endif () if (f AND NOT WIN32) - install(FILES ${f} DESTINATION ${CMAKE_INSTALL_DATAROOTDIR}/man/man1) + install(FILES ${f} DESTINATION ${CMAKE_INSTALL_DATADIR}/man/man1) unset(f) endif () endforeach () diff --git a/src/st-flash/flash.c b/src/st-flash/flash.c index a9952dd34..058501ad6 100644 --- a/src/st-flash/flash.c +++ b/src/st-flash/flash.c @@ -62,7 +62,7 @@ int main(int ac, char** av) { } printf("st-flash %s\n", STLINK_VERSION); - init_chipids (ETC_STLINK_DIR); + init_chipids (STLINK_CHIPS_DIR); sl = stlink_open_usb(o.log_level, o.connect, (char *)o.serial, o.freq); diff --git a/src/st-info/info.c b/src/st-info/info.c index d02653bc5..9963606e3 100644 --- a/src/st-info/info.c +++ b/src/st-info/info.c @@ -68,7 +68,7 @@ static int print_data(int ac, char **av) { return(0); } - init_chipids(ETC_STLINK_DIR); + init_chipids(STLINK_CHIPS_DIR); for (int i=2; i Date: Sun, 13 Nov 2022 17:51:07 -0800 Subject: [PATCH 398/503] Update CMakeLists.txt --- CMakeLists.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index 94721f213..4048928bb 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -74,8 +74,8 @@ include(${CMAKE_MODULE_PATH}/get_version.cmake) # Determine project version include(GNUInstallDirs) # Define GNU standard installation directories -# Define install directory /usr/share -set(CMAKE_INSTALL_SHAREDIR /usr/share/) +# Define install directory /usr/local/share [the new MacOS does not allow changes to /usr/share ] +set(CMAKE_INSTALL_SHAREDIR /usr/local/share/) ## Set C build flags if (NOT MSVC) From 0d96e362696c5b9be0f98ea3187bbfcca12dfd66 Mon Sep 17 00:00:00 2001 From: Wingman Shen Date: Sun, 13 Nov 2022 17:53:59 -0800 Subject: [PATCH 399/503] Update README.md --- README.md | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/README.md b/README.md index b889de389..571db49fd 100644 --- a/README.md +++ b/README.md @@ -84,6 +84,7 @@ We recommend to install `stlink-tools` from the package repository of the used d - RedHat/CentOS 8: Users can install from [EPEL repository](https://src.fedoraproject.org/rpms/stlink/branch/epel8) - FreeBSD: Users can install from [freshports](https://www.freshports.org/devel/stlink) +- MacOS: Users can open a terminal window and then follow the same procedure as for installing on Linux ## Installation from source (advanced users) @@ -103,4 +104,4 @@ Please also refer to our [Contribution Guidelines](CONTRIBUTING.md). *I hope it's not to out of topic, but I've been so frustrated with AVR related things on OpenBSD, the fact that stlink built out of the box without needing to touch anything was so relieving. Literally made my whole weekend better! I take it's thanks to @Crest and also to the stlink-org team (@Nightwalker-87 and @xor-gate it seems) to have made a software that's not unfriendly to the "fringe" OSes. -Thank you <3"* - nbonfils, 11.12.2021 \ No newline at end of file +Thank you <3"* - nbonfils, 11.12.2021 From eb35054ea646ef80b1d57cd3a26bc00583f38d08 Mon Sep 17 00:00:00 2001 From: Angel Iglesias Date: Tue, 22 Nov 2022 10:28:49 +0100 Subject: [PATCH 400/503] config: udev: Add rule for the V3 MINIE programmer --- config/udev/rules.d/49-stlinkv3.rules | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/config/udev/rules.d/49-stlinkv3.rules b/config/udev/rules.d/49-stlinkv3.rules index 5161947a9..98c33eddf 100644 --- a/config/udev/rules.d/49-stlinkv3.rules +++ b/config/udev/rules.d/49-stlinkv3.rules @@ -7,7 +7,12 @@ SUBSYSTEMS=="usb", ATTRS{idVendor}=="0483", ATTRS{idProduct}=="3752", \ SUBSYSTEMS=="usb", ATTRS{idVendor}=="0483", ATTRS{idProduct}=="3753", \ MODE:="0666", \ SYMLINK+="stlinkv3_%n" - + +# STLink V3SET MINIE +SUBSYSTEMS=="usb", ATTRS{idVendor}=="0483", ATTRS{idProduct}=="3754", \ + MODE:="0666", \ + SYMLINK+="stlinkv3_%n" + # STLink V3SET SUBSYSTEMS=="usb", ATTRS{idVendor}=="0483", ATTRS{idProduct}=="374d", \ MODE:="0666", \ From 44ec93d80c191ad22cdecf974d3cc345db654de6 Mon Sep 17 00:00:00 2001 From: Wingman Date: Sat, 3 Dec 2022 05:11:59 -0800 Subject: [PATCH 401/503] add if-clause for macOS --- CMakeLists.txt | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index 4048928bb..124f12f5a 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -74,8 +74,17 @@ include(${CMAKE_MODULE_PATH}/get_version.cmake) # Determine project version include(GNUInstallDirs) # Define GNU standard installation directories -# Define install directory /usr/local/share [the new MacOS does not allow changes to /usr/share ] -set(CMAKE_INSTALL_SHAREDIR /usr/local/share/) +# Define install directory /usr/local/share [not /usr/share on MacOS] +cmake_host_system_information(RESULT OS_NAME QUERY OS_NAME) +message(STATUS "Checking for OS_NAME: ${OS_NAME}") + +if (OS_NAME STREQUAL "macOS") + message(STATUS "set(CMAKE_INSTALL_SHAREDIR /usr/local/share)") + set(CMAKE_INSTALL_SHAREDIR /usr/local/share/) +else () + message(STATUS "set(CMAKE_INSTALL_SHAREDIR /usr/share)") + set(CMAKE_INSTALL_SHAREDIR /usr/share/) +endif () ## Set C build flags if (NOT MSVC) From 33430783b3b18ab88ff89d10d7a2a24dadae2472 Mon Sep 17 00:00:00 2001 From: Marcus Lindemann Date: Sun, 4 Dec 2022 18:11:51 +0100 Subject: [PATCH 402/503] [#1] fFix GUI compilation fail on OpenBSD i386 Explicitely convert from goffset to gsize with prior overflow check. Implicit conversion is forbidden by compiler settings. --- src/stlink-gui/gui.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/src/stlink-gui/gui.c b/src/stlink-gui/gui.c index a58d59247..d7e74c547 100644 --- a/src/stlink-gui/gui.c +++ b/src/stlink-gui/gui.c @@ -301,7 +301,14 @@ static gpointer stlink_gui_populate_filemem_view(gpointer data) { if (gui->file_mem.memory) { g_free(gui->file_mem.memory); } - gui->file_mem.size = g_file_info_get_size(file_info); + goffset file_size = g_file_info_get_size(file_info); + + if (G_MAXSIZE < file_size) { + stlink_gui_set_info_error_message(gui, "File too large."); + goto out_input; + } + + gui->file_mem.size = (gsize) file_info; gui->file_mem.memory = g_malloc(gui->file_mem.size); for (off = 0; off < (gint)gui->file_mem.size; off += MEM_READ_SIZE) { From 014907144840b8a45f3dabd83b6b07b0c0cad72b Mon Sep 17 00:00:00 2001 From: Marcus Lindemann Date: Sun, 4 Dec 2022 18:11:51 +0100 Subject: [PATCH 403/503] Fix GUI compilation fail on OpenBSD i386 Explicitely convert from goffset to gsize with prior overflow check. Implicit conversion is forbidden by compiler settings. --- src/stlink-gui/gui.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/src/stlink-gui/gui.c b/src/stlink-gui/gui.c index a58d59247..d7e74c547 100644 --- a/src/stlink-gui/gui.c +++ b/src/stlink-gui/gui.c @@ -301,7 +301,14 @@ static gpointer stlink_gui_populate_filemem_view(gpointer data) { if (gui->file_mem.memory) { g_free(gui->file_mem.memory); } - gui->file_mem.size = g_file_info_get_size(file_info); + goffset file_size = g_file_info_get_size(file_info); + + if (G_MAXSIZE < file_size) { + stlink_gui_set_info_error_message(gui, "File too large."); + goto out_input; + } + + gui->file_mem.size = (gsize) file_info; gui->file_mem.memory = g_malloc(gui->file_mem.size); for (off = 0; off < (gint)gui->file_mem.size; off += MEM_READ_SIZE) { From d063c1159f0574f143edb42b2a5f05a3f0b20044 Mon Sep 17 00:00:00 2001 From: Marcus Lindemann Date: Sun, 4 Dec 2022 18:11:51 +0100 Subject: [PATCH 404/503] Fix GUI compilation fail on OpenBSD i386 Explicitely convert from goffset to gsize with prior overflow check. Implicit conversion is forbidden by compiler settings. --- src/stlink-gui/gui.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/src/stlink-gui/gui.c b/src/stlink-gui/gui.c index a58d59247..b45f5f126 100644 --- a/src/stlink-gui/gui.c +++ b/src/stlink-gui/gui.c @@ -301,7 +301,14 @@ static gpointer stlink_gui_populate_filemem_view(gpointer data) { if (gui->file_mem.memory) { g_free(gui->file_mem.memory); } - gui->file_mem.size = g_file_info_get_size(file_info); + goffset file_size = g_file_info_get_size(file_info); + + if ((0 > file_size) && (G_MAXSIZE <= file_size)) { + stlink_gui_set_info_error_message(gui, "File too large."); + goto out_input; + } + + gui->file_mem.size = (gsize) file_info; gui->file_mem.memory = g_malloc(gui->file_mem.size); for (off = 0; off < (gint)gui->file_mem.size; off += MEM_READ_SIZE) { From 53e9252cc0c5b348ee7d9cc954c2752168658e34 Mon Sep 17 00:00:00 2001 From: Marcus Lindemann Date: Sun, 4 Dec 2022 18:11:51 +0100 Subject: [PATCH 405/503] Resolve merge conflict for diverging branch. Explicitely convert from goffset to gsize with prior overflow check. Implicit conversion is forbidden by compiler settings. --- src/stlink-gui/gui.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/stlink-gui/gui.c b/src/stlink-gui/gui.c index d7e74c547..b45f5f126 100644 --- a/src/stlink-gui/gui.c +++ b/src/stlink-gui/gui.c @@ -303,7 +303,7 @@ static gpointer stlink_gui_populate_filemem_view(gpointer data) { goffset file_size = g_file_info_get_size(file_info); - if (G_MAXSIZE < file_size) { + if ((0 > file_size) && (G_MAXSIZE <= file_size)) { stlink_gui_set_info_error_message(gui, "File too large."); goto out_input; } From 32fc9f11ef044c27bf48b091e9463c3c9f466271 Mon Sep 17 00:00:00 2001 From: Marcus Lindemann Date: Tue, 6 Dec 2022 21:41:07 +0100 Subject: [PATCH 406/503] Fix resulting compilation error on Ubuntu --- src/stlink-gui/gui.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/stlink-gui/gui.c b/src/stlink-gui/gui.c index b45f5f126..2bf1f9d32 100644 --- a/src/stlink-gui/gui.c +++ b/src/stlink-gui/gui.c @@ -303,7 +303,7 @@ static gpointer stlink_gui_populate_filemem_view(gpointer data) { goffset file_size = g_file_info_get_size(file_info); - if ((0 > file_size) && (G_MAXSIZE <= file_size)) { + if ((0 > file_size) && ((goffset)G_MAXSIZE <= file_size)) { stlink_gui_set_info_error_message(gui, "File too large."); goto out_input; } From a4105f4ce89a110bd3b1fd168e194f8690f43ee6 Mon Sep 17 00:00:00 2001 From: Phil Date: Sun, 18 Dec 2022 16:27:40 +0100 Subject: [PATCH 407/503] Adding device ID for GD32F303VET6 --- doc/devices_boards.md | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/doc/devices_boards.md b/doc/devices_boards.md index 1a5099b72..06f58fe21 100644 --- a/doc/devices_boards.md +++ b/doc/devices_boards.md @@ -89,8 +89,9 @@ Tested non-official ST boards [incl. STLINK programmers]: | Product-Code | Chip-ID | STLINK
Programmer | Boards | | ------------ | ------- | ---------------------- | ---------------------------------- | -| GD32F303VGT6 | 0x430 | [v2] | STM32F303 clone from GigaDevice GD | | GD32F303CGT6 | 0x430 | [v2] | STM32F303 clone from GigaDevice GD | +| GD32F303VET6 | 0x414 | [v2] | STM32F303 clone from GigaDevice GD | +| GD32F303VGT6 | 0x430 | [v2] | STM32F303 clone from GigaDevice GD | ## STM32F4 / ARM Cortex M4F From 194e6e9c6b9f3f1c40bf5c6b724aff8087fb443e Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Wed, 28 Dec 2022 22:21:47 +0100 Subject: [PATCH 408/503] General project clean-up - Removed orphaned old dev-documentation - Rearranged src files belonging to stlink-lib - Revised & sorted option byte source code - Updated devices_boards.md --- CMakeLists.txt | 18 +- doc/dev/app-example/CMakeLists.txt | 22 - doc/dev/app-example/README.md | 2 - doc/dev/app-example/main.c | 28 - doc/dev/developer.txt | 411 --------- doc/dev/pkg-config/CMakeLists.txt | 15 - doc/dev/pkg-config/pkgconfig.pc.cmake | 11 - doc/devices_boards.md | 7 +- inc/stlink.h | 17 - src/st-flash/flash.c | 1 + src/st-util/gdb-server.c | 1 + src/{ => stlink-lib}/calculate.c | 0 src/{ => stlink-lib}/calculate.h | 0 src/{ => stlink-lib}/common.c | 0 src/{ => stlink-lib}/common.h | 0 src/{ => stlink-lib}/common_flash.c | 1 + src/{ => stlink-lib}/common_flash.h | 0 src/stlink-lib/flash_loader.h | 5 +- src/{ => stlink-lib}/flashloader.c | 1 + src/stlink-lib/flashloader.h | 13 + src/{ => stlink-lib}/map_file.c | 0 src/{ => stlink-lib}/map_file.h | 0 src/{ => stlink-lib}/option_bytes.c | 1210 ++++++++++++------------- src/stlink-lib/option_bytes.h | 21 + src/{ => stlink-lib}/read_write.c | 0 25 files changed, 644 insertions(+), 1140 deletions(-) delete mode 100644 doc/dev/app-example/CMakeLists.txt delete mode 100644 doc/dev/app-example/README.md delete mode 100644 doc/dev/app-example/main.c delete mode 100644 doc/dev/developer.txt delete mode 100644 doc/dev/pkg-config/CMakeLists.txt delete mode 100644 doc/dev/pkg-config/pkgconfig.pc.cmake rename src/{ => stlink-lib}/calculate.c (100%) rename src/{ => stlink-lib}/calculate.h (100%) rename src/{ => stlink-lib}/common.c (100%) rename src/{ => stlink-lib}/common.h (100%) rename src/{ => stlink-lib}/common_flash.c (99%) rename src/{ => stlink-lib}/common_flash.h (100%) rename src/{ => stlink-lib}/flashloader.c (99%) create mode 100644 src/stlink-lib/flashloader.h rename src/{ => stlink-lib}/map_file.c (100%) rename src/{ => stlink-lib}/map_file.h (100%) rename src/{ => stlink-lib}/option_bytes.c (73%) create mode 100644 src/stlink-lib/option_bytes.h rename src/{ => stlink-lib}/read_write.c (100%) diff --git a/CMakeLists.txt b/CMakeLists.txt index 124f12f5a..3a22fdedc 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -170,8 +170,8 @@ add_subdirectory(inc) set(STLINK_HEADERS inc/backend.h inc/stlink.h - src/common_flash.h - src/calculate.h + src/stlink-lib/common_flash.h + src/stlink-lib/calculate.h src/stlink-lib/commands.h src/stlink-lib/libusb_settings.h src/stlink-lib/reg.h @@ -185,13 +185,13 @@ set(STLINK_HEADERS ) set(STLINK_SOURCE - src/read_write.c - src/common.c - src/option_bytes.c - src/common_flash.c - src/map_file.c - src/flashloader.c - src/calculate.c + src/stlink-lib/read_write.c + src/stlink-lib/common.c + src/stlink-lib/option_bytes.c + src/stlink-lib/common_flash.c + src/stlink-lib/map_file.c + src/stlink-lib/flashloader.c + src/stlink-lib/calculate.c src/stlink-lib/chipid.c src/stlink-lib/flash_loader.c src/stlink-lib/logging.c diff --git a/doc/dev/app-example/CMakeLists.txt b/doc/dev/app-example/CMakeLists.txt deleted file mode 100644 index 69ba2090e..000000000 --- a/doc/dev/app-example/CMakeLists.txt +++ /dev/null @@ -1,22 +0,0 @@ -# Warning: This example assumes that you are building on a host with pkg-config available (e.g. linux). -# The logic required to build under windows/mingw was intentionally omitted to keep this CMakeLists as small as possible. - -cmake_minimum_required(VERSION 3.4.2) - -project(st-hello) -set(PROJECT_VERSION 0.1) - -set(SRCS main.c) - -include_directories(${STLINK_INCLUDE_DIRS}) - -find_package(PkgConfig) -pkg_check_modules(STLINK REQUIRED stlink) - -set(CMAKE_C_FLAGS " ${STLINK_CFLAGS_OTHER} -Wall -Werror") - -add_executable(${PROJECT_NAME} ${SRCS}) - -target_link_libraries(${PROJECT_NAME} ${STLINK_LIBRARIES}) - -install(TARGETS ${PROJECT_NAME} DESTINATION ${CMAKE_INSTALL_BINDIR}) diff --git a/doc/dev/app-example/README.md b/doc/dev/app-example/README.md deleted file mode 100644 index f3a0bf9bb..000000000 --- a/doc/dev/app-example/README.md +++ /dev/null @@ -1,2 +0,0 @@ -This is a simple standalone application example that uses libstlink. -It can be used as a boilerplate for app development. diff --git a/doc/dev/app-example/main.c b/doc/dev/app-example/main.c deleted file mode 100644 index b8e64b259..000000000 --- a/doc/dev/app-example/main.c +++ /dev/null @@ -1,28 +0,0 @@ -#include -#include -#include - -static stlink_t *stlink_open_first(void) { - stlink_t* sl = NULL; - sl = stlink_v1_open(0, 1); - if (sl == NULL) - sl = stlink_open_usb(0, 1, NULL); - - return sl; -} - - -int main() { - stlink_t* sl = NULL; - sl = stlink_open_first(); - - if (sl == NULL) { - fprintf(stderr, "Failed to open stlink device ;(\n"); - exit(1); - } - - fprintf(stderr, "STlink device opened, that's cool!\n"); - stlink_close(sl); - - return 0; -} diff --git a/doc/dev/developer.txt b/doc/dev/developer.txt deleted file mode 100644 index e3091c003..000000000 --- a/doc/dev/developer.txt +++ /dev/null @@ -1,411 +0,0 @@ -=== Compilation with pkg-config === - -In order to use pkg-config for development purposes, add the following lines to the toplevel CMakeLists.txt file: - -### -# Additional build tasks -### - -## Package configuration (pkg-config) on unix-based systems -if (NOT WIN32 AND NOT CMAKE_CROSSCOMPILING) - add_subdirectory(doc/dev/pkg-config) # external tool pkg-config -endif () - -=== Target Identification === - -The following information is available about the target: -- chip id: 0xE0042000 or 0x40015800, primary information to derive flash and sram architection -- core id: Result from the STLINK_DEBUGREADCOREID call, additionally used for flash/sram architection -- cpu id: 0xE000ED00 (CMSIS System Control Block CPU ID), not used in stlink - - -=== Backend === - -The "backend" implements the interface to the adapter hardware. -There are two backends for two different adapters: "sg" (stlink v1?) and "usb" (stlink v2?). - - - -Include stlink/backend.h - typedef struct _stlink_backend { - void (*close) (stlink_t * sl); - int (*exit_debug_mode) (stlink_t * sl); - int (*enter_swd_mode) (stlink_t * sl); - int (*enter_jtag_mode) (stlink_t * stl); - int (*exit_dfu_mode) (stlink_t * stl); - int (*core_id) (stlink_t * stl); - int (*reset) (stlink_t * stl); - int (*jtag_reset) (stlink_t * stl, int value); - int (*run) (stlink_t * stl); - int (*status) (stlink_t * stl); - int (*version) (stlink_t *sl); - int (*read_debug32) (stlink_t *sl, uint32_t addr, uint32_t *data); - int (*read_mem32) (stlink_t *sl, uint32_t addr, uint16_t len); - int (*write_debug32) (stlink_t *sl, uint32_t addr, uint32_t data); - int (*write_mem32) (stlink_t *sl, uint32_t addr, uint16_t len); - int (*write_mem8) (stlink_t *sl, uint32_t addr, uint16_t len); - int (*read_all_regs) (stlink_t *sl, struct stlink_reg * regp); - int (*read_reg) (stlink_t *sl, int r_idx, struct stlink_reg * regp); - int (*read_all_unsupported_regs) (stlink_t *sl, struct stlink_reg *regp); - int (*read_unsupported_reg) (stlink_t *sl, int r_idx, struct stlink_reg *regp); - int (*write_unsupported_reg) (stlink_t *sl, uint32_t value, int idx, struct stlink_reg *regp); - int (*write_reg) (stlink_t *sl, uint32_t reg, int idx); - int (*step) (stlink_t * stl); - int (*current_mode) (stlink_t * stl); - int (*force_debug) (stlink_t *sl); - int32_t (*target_voltage) (stlink_t *sl); - int (*set_swdclk) (stlink_t * stl, uint16_t divisor); - } stlink_backend_t; - -Descriptions below describe the actions of the usb.h backend: - -void (*close) (stlink_t * sl); -int (*exit_debug_mode) (stlink_t * sl); - __stlink_usb_exit_debug_mode: Send STLINK_DEBUG_EXIT - returns -1 or 0 - -int (*enter_swd_mode) (stlink_t * sl); - _stlink_usb_enter_swd_mode: Send STLINK_DEBUG_ENTER+STLINK_DEBUG_ENTER_SWD - returns -1 or 0 - -int (*enter_jtag_mode) (stlink_t * stl); - -int (*exit_dfu_mode) (stlink_t * stl); - _stlink_usb_exit_dfu_mode: Send STLINK_DFU_EXIT - returns -1 or 0 - -int (*core_id) (stlink_t * stl); - _stlink_usb_core_id: Assign the result from STLINK_DEBUG_READCOREID to stl->core_id - returns -1 or 0 - -int (*reset) (stlink_t * stl); - _stlink_usb_reset: Send STLINK_DEBUG_RESETSYS and reset via AIRCR - AIRCR is part of the CMSIS System Control Block (SCB), which is located in - the System Control Space at 0xE000ED0C - returns -1 or 0 ? - -int (*jtag_reset) (stlink_t * stl, int value); - _stlink_usb_jtag_reset: Send STLINK_JTAG_DRIVE_NRST. - "value" is sent as argument for STLINK_JTAG_DRIVE_NRST and probably contains - the status of the NRST line (0: low, 1: high). Also the value 2 is used in the software. - returns -1 or 0 - -int (*run) (stlink_t * stl); - _stlink_usb_run: Send STLINK_DEBUG_RUNCORE - returns -1 or 0 - -int (*status) (stlink_t * stl); - _stlink_usb_status: Assign the result from STLINK_DEBUG_GETSTATUS to stl->q_len - returns -1 or 0 - -int (*version) (stlink_t *sl); - _stlink_usb_version: Read version with STLINK_GET_VERSION. - Result is stored in sl->q_buf (6 bytes????) - returns -1 or 0 - -int (*read_debug32) (stlink_t *sl, uint32_t addr, uint32_t *data); - _stlink_usb_read_debug32: Send STLINK_JTAG_READDEBUG_32BIT - to read 32 bits from "addr". The result data is stored at "*data". - returns -1 or 0 - -int (*read_mem32) (stlink_t *sl, uint32_t addr, uint16_t len); - _stlink_usb_read_mem32: Use STLINK_DEBUG_READMEM_32BIT - to read "len" bytes from "addr" - Result is returned in sl->q_buf, sl->q_len returns the size of the data (should be - equal to "len"???). - returns -1 or 0 - -int (*write_debug32) (stlink_t *sl, uint32_t addr, uint32_t data); - _stlink_usb_write_debug32: Use STLINK_JTAG_WRITEDEBUG_32BIT - to store "data" at "addr" - returns -1 or 0 - -int (*write_mem32) (stlink_t *sl, uint32_t addr, uint16_t len); - _stlink_usb_write_mem32: Use STLINK_DEBUG_WRITEMEM_32BIT to - send data stored in sl->q_buf to the target at "addr". - "len" is the size data (???? not clear whether this are bytes ) - returns -1 or 0 - -int (*write_mem8) (stlink_t *sl, uint32_t addr, uint16_t len); - _stlink_usb_write_mem8: Use STLINK_DEBUG_WRITEMEM_8BIT to - send data stored in sl->q_buf to the target at "addr". - "len" is the size in bytes (probably). - returns -1 or 0 - -int (*read_all_regs) (stlink_t *sl, struct stlink_reg * regp); - _stlink_usb_read_all_regs: Send STLINK_DEBUG_READALLREGS to read - all register values and store them into *regp; - returns -1 or 0 - -int (*read_reg) (stlink_t *sl, int r_idx, struct stlink_reg * regp); - _stlink_usb_read_reg: Send STLINK_DEBUG_READREG to read specific register "r_idx". - The result is then stored in *regp in the correct register. - Example if "r_idx" is 18, then the result is stored in regp->process_sp - returns -1 or 0 - -int (*read_all_unsupported_regs) (stlink_t *sl, struct stlink_reg *regp); - _stlink_usb_read_all_unsupported_regs: Calls "_stlink_usb_read_unsupported_reg" - (see below) to read all registers. - returns -1 or 0 - -int (*read_unsupported_reg) (stlink_t *sl, int r_idx, struct stlink_reg *regp); - _stlink_usb_read_unsupported_reg Use DCRSR and DCRDR to access some - of the internal registers (primask, basepri, faultmask, control, fpscr). - Also will fill regp->s (???) for some specific "r_idx" values. - WARNING: Some r_idx values may lead to a out of array bound problem in C. - returns -1 or 0 - -int (*write_unsupported_reg) (stlink_t *sl, uint32_t value, int idx, struct stlink_reg *regp); - _stlink_usb_write_unsupported_reg: - Updates one of the following registers: - primask (idx=0x1c), basepri (idx=0x1d), faultmask (idx=0x1e), control (idx=0x1f) - The new value is given as "value" as fn argument. - Corresponding values are refreshed in regp, however the old value for is kept in regp: - If basepri has to be updated (idx=0x1d), then all register values are fetched and - basepri is updated in the core, but not in *regp (BUG???). - returns -1 or 0 - -int (*write_reg) (stlink_t *sl, uint32_t reg, int idx); - _stlink_usb_write_reg: Use STLINK_DEBUG_WRITEREG to update register "idx" - with value "reg". - returns -1 or 0 - -int (*step) (stlink_t * stl); - _stlink_usb_step: Send STLINK_DEBUG_STEPCORE - returns -1 or 0 - -int (*current_mode) (stlink_t * stl); - _stlink_usb_current_mode: Send STLINK_GET_CURRENT_MODE and return - the current mode. - returns -1 or the value for the current mode. - Modes probably are: - STLINK_DEV_DFU_MODE 0x00 - STLINK_DEV_MASS_MODE 0x01 - STLINK_DEV_DEBUG_MODE 0x02 - -int (*force_debug) (stlink_t *sl); - _stlink_usb_force_debug: Sends STLINK_DEBUG_FORCEDEBUG. No other side effects - returns -1 or 0 - -int32_t (*target_voltage) (stlink_t *sl); - _stlink_usb_target_voltage: Send STLINK_GET_TARGET_VOLTAGE - returns -1 or the target voltage. (??? dimension is not clear...) - -int (*set_swdclk) (stlink_t * stl, uint16_t divisor); - _stlink_usb_set_swdclk: Send STLINK_DEBUG_APIV2_SWD_SET_FREQ and "divisor" value - returns -1 or 0 - - -=== Other Functions === - - -Include: stlink.h - - -Prototype: void stlink_close(stlink_t *sl); -Include: inc/stlink.h -Definition: src/common.c -Description: - Calls the backend "close" procedure and frees 'sl' -Backend: "close" -Arguments: - sl: Pointer to the stlink data structure, returned by stlink_v1_open() or stlink_open_usb() -Return: - - -Include: inc/stlink.h -Prototype: int stlink_core_id(stlink_t *sl); -Definition: src/common.c -Description: - Calls the backend "core_id", calls stlink_print_data() on higher verbose levels. - Assigns the core id returned by STLINK_DEBUGREADCOREID to sl->core_id - Only some specific core ids are used: See include/stm32.h - Usage includes the selection of the correct flash algorithm. -Backend: "core_id" -Arguments: - sl: Pointer to the stlink data structure, returned by stlink_v1_open() or stlink_open_usb() -Return: -1 for error. 0 for success. - -Include: inc/stlink.h -Prototype: int stlink_reset(stlink_t *sl); -Definition: src/common.c -Description: - Just calls the backend "reset" procedure (reset via STLINK_DEBUG_RESETSYS - and reset via AIRCR register at 0xE000ED0C) -Backend: "reset" -Arguments: - sl: Pointer to the stlink data structure, returned by stlink_v1_open() or stlink_open_usb() -Return: -1 for error. 0 for success. - -Include: inc/stlink.h -Prototype: int stlink_jtag_reset(stlink_t *sl, int value); -Definition: src/common.c -Description: - Just calls the backend "jtag_reset" procedure -Backend: "jtag_reset" -Arguments: - sl: Pointer to the stlink data structure, returned by stlink_v1_open() or stlink_open_usb() - value: 0: drive low, 1: drive high, 2: pulse -Return: -1 for error. 0 for success. - - -Include: inc/stlink.h -Prototype: int stlink_run(stlink_t *sl, enum run_type type); -Definition: src/common.c -Description: - Just calls the backend "run" procedure. -Backend: "run" -Arguments: - sl: Pointer to the stlink data structure, returned by stlink_v1_open() or stlink_open_usb() - type: RUN_NORMAL - run target, RUN_FLASH_LOADER - run target with masking interrupts -Return: -1 for error. 0 for success. - -Include: inc/stlink.h -Prototype: int stlink_status(stlink_t *sl); -Definition: src/common.c -Description: - Calls the backend "status" procedure and the procedure "stlink_core_stat()" to - store the status in "sl->core_stat". Possible value for "sl->core_stat" are: - STLINK_CORE_RUNNING - STLINK_CORE_HALTED - STLINK_CORE_STAT_UNKNOWN -Backend: "status" -Arguments: - sl: Pointer to the stlink data structure, returned by stlink_v1_open() or stlink_open_usb() -Return: -1 for error. 0 for success. - - -Include: inc/stlink.h -Prototype: int stlink_version(stlink_t *sl); -Definition: src/common.c -Description: - Calls the backend "version" procedure, parses the result and puts the result into sl->version - This version probably refers to the version of the adapter. -Backend: "version" -Arguments: - sl: Pointer to the stlink data structure, returned by stlink_v1_open() or stlink_open_usb() -Return: -1 for error. 0 for success. - - - int stlink_read_debug32(stlink_t *sl, uint32_t addr, uint32_t *data); - int stlink_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len); - int stlink_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data); - int stlink_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len); - int stlink_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len); - int stlink_read_all_regs(stlink_t *sl, struct stlink_reg *regp); - int stlink_read_all_unsupported_regs(stlink_t *sl, struct stlink_reg *regp); - int stlink_read_reg(stlink_t *sl, int r_idx, struct stlink_reg *regp); - int stlink_read_unsupported_reg(stlink_t *sl, int r_idx, struct stlink_reg *regp); - int stlink_write_unsupported_reg(stlink_t *sl, uint32_t value, int r_idx, struct stlink_reg *regp); - int stlink_write_reg(stlink_t *sl, uint32_t reg, int idx); - int stlink_step(stlink_t *sl); - int stlink_current_mode(stlink_t *sl); - int stlink_force_debug(stlink_t *sl); - int stlink_target_voltage(stlink_t *sl); - int stlink_set_swdclk(stlink_t *sl, int freq_khz); - - int stlink_erase_flash_mass(stlink_t* sl); - int stlink_write_flash(stlink_t* sl, stm32_addr_t address, uint8_t* data, uint32_t length, uint8_t eraseonly); - int stlink_parse_ihex(const char* path, uint8_t erased_pattern, uint8_t * * mem, size_t * size, uint32_t * begin); - uint8_t stlink_get_erased_pattern(stlink_t *sl); - int stlink_mwrite_flash(stlink_t *sl, uint8_t* data, uint32_t length, stm32_addr_t addr); - int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr); - int stlink_fwrite_option_bytes(stlink_t *sl, const char* path, stm32_addr_t addr); - int stlink_fwrite_option_bytes_32bit(stlink_t *sl,uint32_t val); - int stlink_mwrite_sram(stlink_t *sl, uint8_t* data, uint32_t length, stm32_addr_t addr); - int stlink_fwrite_sram(stlink_t *sl, const char* path, stm32_addr_t addr); - int stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, uint32_t length); - -Include: inc/stlink.h -Prototype: int stlink_chip_id(stlink_t *sl, uint32_t *chip_id); -Definition: src/common.c -Description: - Tries to read out the chip id via memory read from the device. - Note: sl->chip_id is NOT updated by this procedure. Instead this happens in stlink_load_device_params(): - Do not call this function, but instead call stlink_load_device_params() -Backend: - -Arguments: - sl: Pointer to the stlink data structure, returned by stlink_v1_open() or stlink_open_usb() - chip_id: Pointer. Result is stored via this pointer. -Return: -1 for error. 0 for success. - - -Include: inc/stlink.h -Prototype: int stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid); -Definition: src/common.c -Description: - Reads the CPU id from STLINK_REG_CM3_CPUID (0xE000ED00, first value of - the SCB, system control block) and splits this into - cpuid->implementer_id - cpuid->variant - cpuid->part - cpuid->revision - The result is not used in the tools, but only in the usb test program. -Backend: - -Arguments: - sl: Pointer to the stlink data structure, returned by stlink_v1_open() or stlink_open_usb() - cpuid: Pointer. Result is stored via this pointer. -Return: -1 for error. 0 for success. - - - - - int stlink_erase_flash_page(stlink_t* sl, stm32_addr_t flashaddr); - uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr); - uint16_t read_uint16(const unsigned char *c, const int pt); - void stlink_core_stat(stlink_t *sl); - - -Include: inc/stlink.h -Prototype: void stlink_print_data(stlink_t *sl); -Definition: src/common.c -Description: - If debug logging is enabled: Print the HEX content of the q_buf array. - q_buf will contain the result of the last "backend" command. -Backend: - -Arguments: - sl: Pointer to the stlink data structure, returned by stlink_v1_open() or stlink_open_usb() -Return: - - - - unsigned int is_bigendian(void); - uint32_t read_uint32(const unsigned char *c, const int pt); - void write_uint32(unsigned char* buf, uint32_t ui); - void write_uint16(unsigned char* buf, uint16_t ui); - bool stlink_is_core_halted(stlink_t *sl); - int write_buffer_to_sram(stlink_t *sl, flash_loader_t* fl, const uint8_t* buf, size_t size); - int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size); - int stlink_fread(stlink_t* sl, const char* path, bool is_ihex, stm32_addr_t addr, size_t size); - - -Include: inc/stlink.h -Prototype: int stlink_load_device_params(stlink_t *sl); -Definition: src/common.c -Description: - This is one of the most important procedures. It will get all the device info - and store the results in the "sl" structure. Many other procedures will depend - on this information. - The identification is based on the stlink_chip_id() result and the flash_size register value -Backend: - -Arguments: - sl: Pointer to the stlink data structure, returned by stlink_v1_open() or stlink_open_usb() -Return: -1 for error. 0 for success. - - int stlink_read_option_bytes_f2(stlink_t *sl, uint32_t* option_byte); - int stlink_read_option_bytes_f4(stlink_t *sl, uint32_t* option_byte); - - -Include "flash_loader.h" - -int stlink_flash_loader_init(stlink_t *sl, flash_loader_t* fl); -int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size); -int stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, const uint8_t* buf, size_t size); - - -Inlcude "sg.h" -stlink_t* stlink_v1_open(const int verbose, int reset); - -Include "usb.h" - -stlink_t *stlink_open_usb(enum ugly_loglevel verbose, bool reset, char serial[STLINK_SERIAL_MAX_SIZE]); -size_t stlink_probe_usb(stlink_t **stdevs[]); -void stlink_probe_usb_free(stlink_t **stdevs[], size_t size); diff --git a/doc/dev/pkg-config/CMakeLists.txt b/doc/dev/pkg-config/CMakeLists.txt deleted file mode 100644 index 53870fee4..000000000 --- a/doc/dev/pkg-config/CMakeLists.txt +++ /dev/null @@ -1,15 +0,0 @@ -set(PKG_CONFIG_LIBDIR "\${prefix}/lib/\${deb_host_multiarch}") -set(PKG_CONFIG_INCLUDEDIR "\${prefix}/include/\${deb_host_multiarch}/${PROJECT_NAME}") -set(PKG_CONFIG_LIBS "-L\${libdir} -l:libstlink.so.${PROJECT_VERSION_MAJOR}") -set(PKG_CONFIG_CFLAGS "-I\${includedir}") -set(PKG_CONFIG_REQUIRES "libusb-1.0") - -configure_file( - "${CMAKE_CURRENT_SOURCE_DIR}/pkgconfig.pc.cmake" - "${CMAKE_CURRENT_BINARY_DIR}/${PROJECT_NAME}.pc" - ) - -install( - FILES "${CMAKE_CURRENT_BINARY_DIR}/${PROJECT_NAME}.pc" - DESTINATION ${STLINK_LIBRARY_PATH}/pkgconfig - ) diff --git a/doc/dev/pkg-config/pkgconfig.pc.cmake b/doc/dev/pkg-config/pkgconfig.pc.cmake deleted file mode 100644 index 4f881daec..000000000 --- a/doc/dev/pkg-config/pkgconfig.pc.cmake +++ /dev/null @@ -1,11 +0,0 @@ -prefix=${CMAKE_INSTALL_PREFIX} -deb_host_multiarch=${CMAKE_LIBRARY_PATH} -libdir=${PKG_CONFIG_LIBDIR} -includedir=${PKG_CONFIG_INCLUDEDIR} - -Name: ${PROJECT_NAME} -Description: ${PROJECT_DESCRIPTION} -Version: ${PROJECT_VERSION} -Libs: ${PKG_CONFIG_LIBS} -Cflags: ${PKG_CONFIG_CFLAGS} -Requires: ${PKG_CONFIG_REQUIRES} diff --git a/doc/devices_boards.md b/doc/devices_boards.md index 1a5099b72..feab9ffa9 100644 --- a/doc/devices_boards.md +++ b/doc/devices_boards.md @@ -53,10 +53,9 @@ Tested non-official ST boards [incl. STLINK programmers]: ## STM32F1 Clone / ARM Cortex M3 (Core-ID: 0x2ba01477) [may work, but without support!] -| Product-Code | Chip-ID | STLink
Programmer | Boards | -| ------------- | ------- | ---------------------- | ----------------------------------------------------------------------------------------------- | -| CKS32F103C8Tx | 0x410 | v2 | "STM32"-Bluepill ( _**Fake-Marking !**_ )
STM32F103C8T6 clone from China Key Systems (CKS) | -| CKS32F103C8Tx | 0x410 | v2 | CKS32-Bluepill (Clone)
STM32F103C8T6 clone from China Key Systems (CKS) | +| Product-Code | Chip-ID | STLink
Programmer | Boards | +| ------------- | ------- | ---------------------- | ------------------------------------------------------------------------------------------------------------------------------------ | +| CKS32F103C8Tx | 0x410 | v2 | STM32F103C8T6 clone from China Key Systems (CKS) either as
CKS32-Bluepill or even as "STM32"-Bluepill with _**Fake-Marking !**_ | ## STM32F3 / ARM Cortex M4F diff --git a/inc/stlink.h b/inc/stlink.h index 17601fda8..b9379e03d 100644 --- a/inc/stlink.h +++ b/inc/stlink.h @@ -296,23 +296,6 @@ int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size); int stlink_fread(stlink_t* sl, const char* path, bool is_ihex, stm32_addr_t addr, size_t size); int stlink_load_device_params(stlink_t *sl); -int stlink_read_option_bytes32(stlink_t *sl, uint32_t* option_byte); -int stlink_read_option_bytes_boot_add32(stlink_t *sl, uint32_t* option_byte); -int stlink_read_option_control_register32(stlink_t *sl, uint32_t* option_byte); -int stlink_read_option_control_register1_32(stlink_t *sl, uint32_t* option_byte); - -int stlink_write_option_bytes32(stlink_t *sl, uint32_t option_byte); -int stlink_write_option_bytes_boot_add32(stlink_t *sl, uint32_t option_bytes_boot_add); -int stlink_write_option_control_register32(stlink_t *sl, uint32_t option_control_register); -int stlink_write_option_control_register1_32(stlink_t *sl, uint32_t option_control_register1); - -int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t len); -int stlink_fwrite_option_bytes(stlink_t *sl, const char* path, stm32_addr_t addr); - -int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl); -int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t addr, uint8_t* base, uint32_t len); -int stlink_flashloader_stop(stlink_t *sl, flash_loader_t *fl); - int stlink_target_connect(stlink_t *sl, enum connect_type connect); #include diff --git a/src/st-flash/flash.c b/src/st-flash/flash.c index 058501ad6..0985c75c2 100644 --- a/src/st-flash/flash.c +++ b/src/st-flash/flash.c @@ -11,6 +11,7 @@ #include #include #include "flash.h" +#include "option_bytes.h" static stlink_t *connected_stlink = NULL; diff --git a/src/st-util/gdb-server.c b/src/st-util/gdb-server.c index cef79ddc1..802e23c06 100644 --- a/src/st-util/gdb-server.c +++ b/src/st-util/gdb-server.c @@ -28,6 +28,7 @@ #include #include #include +#include "flashloader.h" #include "gdb-remote.h" #include "gdb-server.h" #include "semihosting.h" diff --git a/src/calculate.c b/src/stlink-lib/calculate.c similarity index 100% rename from src/calculate.c rename to src/stlink-lib/calculate.c diff --git a/src/calculate.h b/src/stlink-lib/calculate.h similarity index 100% rename from src/calculate.h rename to src/stlink-lib/calculate.h diff --git a/src/common.c b/src/stlink-lib/common.c similarity index 100% rename from src/common.c rename to src/stlink-lib/common.c diff --git a/src/common.h b/src/stlink-lib/common.h similarity index 100% rename from src/common.h rename to src/stlink-lib/common.h diff --git a/src/common_flash.c b/src/stlink-lib/common_flash.c similarity index 99% rename from src/common_flash.c rename to src/stlink-lib/common_flash.c index 17352974c..b21929ddf 100644 --- a/src/common_flash.c +++ b/src/stlink-lib/common_flash.c @@ -3,6 +3,7 @@ #include #include #include "calculate.h" +#include "flashloader.h" #include "common_flash.h" #include "map_file.h" #include "common.h" diff --git a/src/common_flash.h b/src/stlink-lib/common_flash.h similarity index 100% rename from src/common_flash.h rename to src/stlink-lib/common_flash.h diff --git a/src/stlink-lib/flash_loader.h b/src/stlink-lib/flash_loader.h index 85b92bef3..368b6ab8b 100644 --- a/src/stlink-lib/flash_loader.h +++ b/src/stlink-lib/flash_loader.h @@ -1,8 +1,7 @@ /* - * File: stlink.h + * File: flash_loader.h * - * This should contain all the common top level stlink interfaces, - * regardless of how the backend does the work.... + * Flash loader */ #ifndef STLINK_FLASH_LOADER_H_ diff --git a/src/flashloader.c b/src/stlink-lib/flashloader.c similarity index 99% rename from src/flashloader.c rename to src/stlink-lib/flashloader.c index b9c26bf4c..abb140fdd 100644 --- a/src/flashloader.c +++ b/src/stlink-lib/flashloader.c @@ -1,6 +1,7 @@ #include #include #include +#include "flashloader.h" #include "common_flash.h" #define L1_WRITE_BLOCK_SIZE 0x80 diff --git a/src/stlink-lib/flashloader.h b/src/stlink-lib/flashloader.h new file mode 100644 index 000000000..ff16d183c --- /dev/null +++ b/src/stlink-lib/flashloader.h @@ -0,0 +1,13 @@ +/* + * File: flashloader.h + * + * Flash loader + */ + +#include +#include + +int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl); +int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t addr, uint8_t* base, uint32_t len); +int stlink_flashloader_stop(stlink_t *sl, flash_loader_t *fl); + diff --git a/src/map_file.c b/src/stlink-lib/map_file.c similarity index 100% rename from src/map_file.c rename to src/stlink-lib/map_file.c diff --git a/src/map_file.h b/src/stlink-lib/map_file.h similarity index 100% rename from src/map_file.h rename to src/stlink-lib/map_file.h diff --git a/src/option_bytes.c b/src/stlink-lib/option_bytes.c similarity index 73% rename from src/option_bytes.c rename to src/stlink-lib/option_bytes.c index c1a418232..44cd3930b 100644 --- a/src/option_bytes.c +++ b/src/stlink-lib/option_bytes.c @@ -1,152 +1,32 @@ #include #include #include +#include "option_bytes.h" #include "common_flash.h" #include "map_file.h" #include "common.h" -/** - * Read option bytes - * @param sl - * @param option_byte value to write - * @return 0 on success, -ve on failure. - */ -int stlink_read_option_control_register_Gx(stlink_t *sl, - uint32_t *option_byte) { - return stlink_read_debug32(sl, STM32Gx_FLASH_OPTR, option_byte); -} - -/** - * Read option bytes - * @param sl - * @param option_byte value to write - * @return 0 on success, -ve on failure. - */ -int stlink_read_option_bytes_Gx(stlink_t *sl, uint32_t *option_byte) { - return stlink_read_option_control_register_Gx(sl, option_byte); -} - -/** - * Read first option bytes - * @param sl - * @param option_byte option value - * @return 0 on success, -ve on failure. - */ -int stlink_read_option_bytes_generic(stlink_t *sl, uint32_t *option_byte) { - DLOG("@@@@ Read option bytes boot address from %#10x\n", sl->option_base); - return stlink_read_debug32(sl, sl->option_base, option_byte); -} - -/** - * Read option bytes - * @param sl - * @param option_byte value to write - * @return 0 on success, -ve on failure. - */ -int stlink_read_option_control_register_f2(stlink_t *sl, - uint32_t *option_byte) { - return stlink_read_debug32(sl, FLASH_F2_OPT_CR, option_byte); -} - -/** - * Read option bytes - * @param sl - * @param option_byte value to write - * @return 0 on success, -ve on failure. - */ -int stlink_read_option_bytes_f2(stlink_t *sl, uint32_t *option_byte) { - return stlink_read_option_control_register_f2(sl, option_byte); -} - -/** - * Read option bytes - * @param sl - * @param option_byte value to read - * @return 0 on success, -ve on failure. - */ -int stlink_read_option_control_register_f4(stlink_t *sl, - uint32_t *option_byte) { - return stlink_read_debug32(sl, FLASH_F4_OPTCR, option_byte); -} - -/** - * Read option bytes - * @param sl - * @param option_byte value to read - * @return 0 on success, -ve on failure. - */ -int stlink_read_option_bytes_f4(stlink_t *sl, uint32_t *option_byte) { - return stlink_read_option_control_register_f4(sl, option_byte); -} /** - * Read option bytes + * Read option control register F0 * @param sl - * @param option_byte value to read + * @param option_byte * @return 0 on success, -ve on failure. - * - * Since multiple bytes can be read, we read and print all but one here - * and then return the last one just like other devices */ -int stlink_read_option_bytes_f7(stlink_t *sl, uint32_t *option_byte) { - int err = -1; - for (uint32_t counter = 0; counter < (sl->option_size / 4 - 1); counter++) { - err = stlink_read_debug32(sl, sl->option_base + counter * sizeof(uint32_t), - option_byte); - if (err == -1) { - return err; - } else { - printf("%08x\n", *option_byte); - } - } - - return stlink_read_debug32( - sl, - sl->option_base + (uint32_t)(sl->option_size / 4 - 1) * sizeof(uint32_t), - option_byte); -} - -/** - * Read option bytes - * @param sl - * @param option_byte option value - * @return 0 on success, -ve on failure. - */ -int stlink_read_option_bytes32(stlink_t *sl, uint32_t *option_byte) { - if (sl->option_base == 0) { - ELOG("Option bytes read is currently not supported for connected chip\n"); - return (-1); - } - - switch (sl->chip_id) { - case STM32_CHIPID_F2: - return stlink_read_option_bytes_f2(sl, option_byte); - case STM32_CHIPID_F4: - case STM32_CHIPID_F446: - return stlink_read_option_bytes_f4(sl, option_byte); - case STM32_CHIPID_F76xxx: - return stlink_read_option_bytes_f7(sl, option_byte); - case STM32_CHIPID_G0_CAT1: - case STM32_CHIPID_G0_CAT2: - case STM32_CHIPID_G4_CAT2: - case STM32_CHIPID_G4_CAT3: - return stlink_read_option_bytes_Gx(sl, option_byte); - default: - return stlink_read_option_bytes_generic(sl, option_byte); - } +int stlink_read_option_control_register_f0(stlink_t *sl, uint32_t *option_byte) { + DLOG("@@@@ Read option control register byte from %#10x\n", FLASH_OBR); + return stlink_read_debug32(sl, FLASH_OBR, option_byte); } - /** - * Write option bytes + * Write option bytes F0 * @param sl - * @param base option bytes to write * @param addr of the memory mapped option bytes - * @param len of options bytes to write + * @param base option bytes + * @param len of option bytes * @return 0 on success, -ve on failure. */ -static int stlink_write_option_bytes_f0( - stlink_t *sl, uint8_t* base, stm32_addr_t addr, uint32_t len) { +static int stlink_write_option_bytes_f0(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t len) { int ret = 0; if (len < 12 || addr != STM32_F0_OPTION_BYTES_BASE) { @@ -196,133 +76,139 @@ static int stlink_write_option_bytes_f0( } /** - * Write option bytes + * Write option control register F0 * @param sl - * @param addr of the memory mapped option bytes - * @param base option bytes to write + * @param option_cr * @return 0 on success, -ve on failure. */ -static int stlink_write_option_bytes_gx(stlink_t *sl, uint8_t *base, - stm32_addr_t addr, uint32_t len) { - /* Write options bytes */ - uint32_t val; +static int stlink_write_option_control_register_f0(stlink_t *sl, uint32_t option_cr) { int ret = 0; - (void)len; - uint32_t data; + uint16_t opt_val[8]; + unsigned protection, optiondata; + uint16_t user_options, user_data, rdp; + unsigned option_offset, user_data_offset; + + ILOG("Asked to write option control register %#10x to %#010x.\n", option_cr, FLASH_OBR); + /* Clear errors */ clear_flash_error(sl); - write_uint32((unsigned char *)&data, *(uint32_t *)(base)); - WLOG("Writing option bytes %#10x to %#10x\n", data, addr); - stlink_write_debug32(sl, STM32Gx_FLASH_OPTR, data); + /* Retrieve current values */ + ret = stlink_read_debug32(sl, FLASH_OBR, &optiondata); + if (ret) { + return ret; + } + ret = stlink_read_debug32(sl, FLASH_WRPR, &protection); + if (ret) { + return ret; + } - // Set Options Start bit - stlink_read_debug32(sl, STM32Gx_FLASH_CR, &val); - val |= (1 << STM32Gx_FLASH_CR_OPTSTRT); - stlink_write_debug32(sl, STM32Gx_FLASH_CR, val); + /* Translate OBR value to flash store structure + * F0: RM0091, Option byte description, pp. 75-78 + * F1: PM0075, Option byte description, pp. 19-22 + * F3: RM0316, Option byte description, pp. 85-87 */ + switch(sl->chip_id) + { + case 0x422: /* STM32F30x */ + case 0x432: /* STM32F37x */ + case 0x438: /* STM32F303x6/8 and STM32F328 */ + case 0x446: /* STM32F303xD/E and STM32F398xE */ + case 0x439: /* STM32F302x6/8 */ + case 0x440: /* STM32F05x */ + case 0x444: /* STM32F03x */ + case 0x445: /* STM32F04x */ + case 0x448: /* STM32F07x */ + case 0x442: /* STM32F09x */ + option_offset = 6; + user_data_offset = 16; + rdp = 0x55AA; + break; + default: + option_offset = 0; + user_data_offset = 10; + rdp = 0x5AA5; + break; + } - wait_flash_busy(sl); + user_options = (option_cr >> option_offset >> 2) & 0xFFFF; + user_data = (option_cr >> user_data_offset) & 0xFFFF; - ret = check_flash_error(sl); +#define VAL_WITH_COMPLEMENT(v) (uint16_t)(((v)&0xFF) | (((~(v))<<8)&0xFF00)) - // Reload options - stlink_read_debug32(sl, STM32Gx_FLASH_CR, &val); - val |= (1 << STM32Gx_FLASH_CR_OBL_LAUNCH); - stlink_write_debug32(sl, STM32Gx_FLASH_CR, val); + opt_val[0] = (option_cr & (1 << 1/*OPT_READOUT*/)) ? 0xFFFF : rdp; + opt_val[1] = VAL_WITH_COMPLEMENT(user_options); + opt_val[2] = VAL_WITH_COMPLEMENT(user_data); + opt_val[3] = VAL_WITH_COMPLEMENT(user_data >> 8); + opt_val[4] = VAL_WITH_COMPLEMENT(protection); + opt_val[5] = VAL_WITH_COMPLEMENT(protection >> 8); + opt_val[6] = VAL_WITH_COMPLEMENT(protection >> 16); + opt_val[7] = VAL_WITH_COMPLEMENT(protection >> 24); - return (ret); +#undef VAL_WITH_COMPLEMENT + + /* Write bytes and check errors */ + ret = stlink_write_option_bytes_f0(sl, STM32_F0_OPTION_BYTES_BASE, (uint8_t*)opt_val, sizeof(opt_val)); + if (ret) + return ret; + + ret = check_flash_error(sl); + if (!ret) { + ILOG("Wrote option bytes %#010x to %#010x!\n", option_cr, + FLASH_OBR); + } + + return ret; } /** - * Write option bytes + * Read option control register F2 * @param sl - * @param addr of the memory mapped option bytes - * @param base option bytes to write + * @param option_byte * @return 0 on success, -ve on failure. */ -static int stlink_write_option_bytes_l0(stlink_t *sl, uint8_t *base, - stm32_addr_t addr, uint32_t len) { - uint32_t flash_base = get_stm32l0_flash_base(sl); - uint32_t val; - uint32_t data; - int ret = 0; - - // Clear errors - clear_flash_error(sl); - - while (len != 0) { - write_uint32((unsigned char *)&data, - *(uint32_t *)(base)); // write options bytes - - WLOG("Writing option bytes %#10x to %#10x\n", data, addr); - stlink_write_debug32(sl, addr, data); - wait_flash_busy(sl); - - if ((ret = check_flash_error(sl))) { - break; - } - - len -= 4; - addr += 4; - base += 4; - } - - // Reload options - stlink_read_debug32(sl, flash_base + FLASH_PECR_OFF, &val); - val |= (1 << STM32L0_FLASH_OBL_LAUNCH); - stlink_write_debug32(sl, flash_base + FLASH_PECR_OFF, val); - - return (ret); +int stlink_read_option_control_register_f2(stlink_t *sl, uint32_t *option_byte) { + return stlink_read_debug32(sl, FLASH_F2_OPT_CR, option_byte); } /** - * Write option bytes + * Read option bytes F2 * @param sl - * @param addr of the memory mapped option bytes - * @param base option bytes to write + * @param option_byte * @return 0 on success, -ve on failure. */ -static int stlink_write_option_bytes_l4(stlink_t *sl, uint8_t *base, - stm32_addr_t addr, uint32_t len) { - - uint32_t val; - int ret = 0; - (void)addr; - (void)len; - - // Clear errors - clear_flash_error(sl); - - // write options bytes - uint32_t data; - write_uint32((unsigned char *)&data, *(uint32_t *)(base)); - WLOG("Writing option bytes 0x%04x\n", data); - stlink_write_debug32(sl, STM32L4_FLASH_OPTR, data); - - // set options start bit - stlink_read_debug32(sl, STM32L4_FLASH_CR, &val); - val |= (1 << STM32L4_FLASH_CR_OPTSTRT); - stlink_write_debug32(sl, STM32L4_FLASH_CR, val); - - wait_flash_busy(sl); - ret = check_flash_error(sl); +int stlink_read_option_bytes_f2(stlink_t *sl, uint32_t *option_byte) { + return stlink_read_option_control_register_f2(sl, option_byte); +} - // apply options bytes immediate - stlink_read_debug32(sl, STM32L4_FLASH_CR, &val); - val |= (1 << STM32L4_FLASH_CR_OBL_LAUNCH); - stlink_write_debug32(sl, STM32L4_FLASH_CR, val); +/** + * Read option control register F4 + * @param sl + * @param option_byte + * @return 0 on success, -ve on failure. + */ +int stlink_read_option_control_register_f4(stlink_t *sl, uint32_t *option_byte) { + return stlink_read_debug32(sl, FLASH_F4_OPTCR, option_byte); +} - return (ret); +/** + * Read option bytes F4 + * @param sl + * @param option_byte + * @return 0 on success, -ve on failure. + */ +int stlink_read_option_bytes_f4(stlink_t *sl, uint32_t *option_byte) { + return stlink_read_option_control_register_f4(sl, option_byte); } /** - * Write option bytes + * Write option bytes F4 * @param sl - * @param option_byte value to write + * @param addr of the memory mapped option bytes + * @param base option bytes + * @param len of option bytes * @return 0 on success, -ve on failure. */ -static int stlink_write_option_bytes_f4(stlink_t *sl, uint8_t *base, - stm32_addr_t addr, uint32_t len) { +static int stlink_write_option_bytes_f4(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint32_t len) { uint32_t option_byte; int ret = 0; (void)addr; @@ -346,13 +232,40 @@ static int stlink_write_option_bytes_f4(stlink_t *sl, uint8_t *base, } /** - * Write option bytes + * Read option bytes F7 * @param sl - * @param option_byte value to write + * @param option_byte * @return 0 on success, -ve on failure. */ -static int stlink_write_option_bytes_f7(stlink_t *sl, uint8_t *base, - stm32_addr_t addr, uint32_t len) { +// Since multiple bytes can be read, we read and print all, but one here +// and then return the last one just like other devices. +int stlink_read_option_bytes_f7(stlink_t *sl, uint32_t *option_byte) { + int err = -1; + for (uint32_t counter = 0; counter < (sl->option_size / 4 - 1); counter++) { + err = stlink_read_debug32(sl, sl->option_base + counter * sizeof(uint32_t), + option_byte); + if (err == -1) { + return err; + } else { + printf("%08x\n", *option_byte); + } + } + + return stlink_read_debug32( + sl, + sl->option_base + (uint32_t)(sl->option_size / 4 - 1) * sizeof(uint32_t), + option_byte); +} + +/** + * Write option bytes F7 + * @param sl + * @param addr of the memory mapped option bytes + * @param base option bytes + * @param len of option bytes + * @return 0 on success, -ve on failure. + */ +static int stlink_write_option_bytes_f7(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint32_t len) { uint32_t option_byte; int ret = 0; @@ -392,25 +305,193 @@ static int stlink_write_option_bytes_f7(stlink_t *sl, uint8_t *base, wait_flash_busy(sl); ret = check_flash_error(sl); - if (!ret) - ILOG("Wrote %d option bytes %#010x to %#010x!\n", len, *(uint32_t *)base, - addr); + if (!ret) + ILOG("Wrote %d option bytes %#010x to %#010x!\n", len, *(uint32_t *)base, + addr); + + /* option bytes are reloaded at reset only, no obl. */ + + return ret; +} + +/** + * Read option control register F7 + * @param sl + * @param option_byte + * @return 0 on success, -ve on failure. + */ +int stlink_read_option_control_register_f7(stlink_t *sl, uint32_t *option_byte) { + DLOG("@@@@ Read option control register byte from %#10x\n", FLASH_F7_OPTCR); + return stlink_read_debug32(sl, FLASH_F7_OPTCR, option_byte); +} + +/** + * Write option control register F7 + * @param sl + * @param option_cr + * @return 0 on success, -ve on failure. + */ +static int stlink_write_option_control_register_f7(stlink_t *sl, uint32_t option_cr) { + int ret = 0; + + // Clear errors + clear_flash_error(sl); + + ILOG("Asked to write option control register 1 %#10x to %#010x.\n", + option_cr, FLASH_F7_OPTCR); + + /* write option byte, ensuring we dont lock opt, and set strt bit */ + stlink_write_debug32(sl, FLASH_F7_OPTCR, + (option_cr & ~(1 << FLASH_F7_OPTCR_LOCK)) | + (1 << FLASH_F7_OPTCR_START)); + + wait_flash_busy(sl); + + ret = check_flash_error(sl); + if (!ret) + ILOG("Wrote option bytes %#010x to %#010x!\n", option_cr, + FLASH_F7_OPTCR); + + return ret; +} + +/** + * Read option control register1 F7 + * @param sl + * @param option_byte + * @return 0 on success, -ve on failure. + */ +int stlink_read_option_control_register1_f7(stlink_t *sl, uint32_t *option_byte) { + DLOG("@@@@ Read option control register 1 byte from %#10x\n", + FLASH_F7_OPTCR1); + return stlink_read_debug32(sl, FLASH_F7_OPTCR1, option_byte); +} + +/** + * Write option control register1 F7 + * @param sl + * @param option_cr1 + * @return 0 on success, -ve on failure. + */ +static int stlink_write_option_control_register1_f7(stlink_t *sl, uint32_t option_cr1) { + int ret = 0; + + // Clear errors + clear_flash_error(sl); + + ILOG("Asked to write option control register 1 %#010x to %#010x.\n", + option_cr1, FLASH_F7_OPTCR1); + + /* write option byte, ensuring we dont lock opt, and set strt bit */ + uint32_t current_control_register_value; + stlink_read_debug32(sl, FLASH_F7_OPTCR, ¤t_control_register_value); + + /* write option byte */ + stlink_write_debug32(sl, FLASH_F7_OPTCR1, option_cr1); + stlink_write_debug32( + sl, FLASH_F7_OPTCR, + (current_control_register_value & ~(1 << FLASH_F7_OPTCR_LOCK)) | + (1 << FLASH_F7_OPTCR_START)); + + wait_flash_busy(sl); + + ret = check_flash_error(sl); + if (!ret) + ILOG("Wrote option bytes %#010x to %#010x!\n", option_cr1, FLASH_F7_OPTCR1); + + return ret; +} + +/** + * Read option bytes boot address F7 + * @param sl + * @param option_byte + * @return 0 on success, -ve on failure. + */ +int stlink_read_option_bytes_boot_add_f7(stlink_t *sl, uint32_t *option_byte) { + DLOG("@@@@ Read option byte boot address\n"); + return stlink_read_option_control_register1_f7(sl, option_byte); +} + +/** + * Write option bytes boot address F7 + * @param sl + * @param option_byte + * @return 0 on success, -ve on failure. + */ +static int +stlink_write_option_bytes_boot_add_f7(stlink_t *sl, uint32_t option_byte_boot_add) { + ILOG("Asked to write option byte boot add %#010x.\n", option_byte_boot_add); + return stlink_write_option_control_register1_f7(sl, option_byte_boot_add); +} + +/** + * Read option control register Gx + * @param sl + * @param option_byte + * @return 0 on success, -ve on failure. + */ +int stlink_read_option_control_register_gx(stlink_t *sl, uint32_t *option_byte) { + return stlink_read_debug32(sl, STM32Gx_FLASH_OPTR, option_byte); +} + +/** + * Read option bytes Gx + * @param sl + * @param option_byte + * @return 0 on success, -ve on failure. + */ +int stlink_read_option_bytes_gx(stlink_t *sl, uint32_t *option_byte) { + return stlink_read_option_control_register_gx(sl, option_byte); +} + +/** + * Write option bytes Gx + * @param sl + * @param addr of the memory mapped option bytes + * @param base option bytes + * @param len of option bytes + * @return 0 on success, -ve on failure. + */ +static int stlink_write_option_bytes_gx(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint32_t len) { + /* Write options bytes */ + uint32_t val; + int ret = 0; + (void)len; + uint32_t data; + + clear_flash_error(sl); + + write_uint32((unsigned char *)&data, *(uint32_t *)(base)); + WLOG("Writing option bytes %#10x to %#10x\n", data, addr); + stlink_write_debug32(sl, STM32Gx_FLASH_OPTR, data); + + // Set Options Start bit + stlink_read_debug32(sl, STM32Gx_FLASH_CR, &val); + val |= (1 << STM32Gx_FLASH_CR_OPTSTRT); + stlink_write_debug32(sl, STM32Gx_FLASH_CR, val); + + wait_flash_busy(sl); + + ret = check_flash_error(sl); - /* option bytes are reloaded at reset only, no obl. */ + // Reload options + stlink_read_debug32(sl, STM32Gx_FLASH_CR, &val); + val |= (1 << STM32Gx_FLASH_CR_OBL_LAUNCH); + stlink_write_debug32(sl, STM32Gx_FLASH_CR, val); - return ret; + return (ret); } /** - * Write STM32H7xx option bytes + * Write option bytes H7 * @param sl - * @param base option bytes to write * @param addr of the memory mapped option bytes - * @param len number of bytes to write (must be multiple of 4) + * @param base option bytes + * @param len of option bytes * @return 0 on success, -ve on failure. */ -static int stlink_write_option_bytes_h7(stlink_t *sl, uint8_t *base, - stm32_addr_t addr, uint32_t len) { +static int stlink_write_option_bytes_h7(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint32_t len) { uint32_t val; uint32_t data; @@ -473,14 +554,96 @@ static int stlink_write_option_bytes_h7(stlink_t *sl, uint8_t *base, } /** - * Write option bytes + * Write option bytes L0 + * @param sl + * @param addr of the memory mapped option bytes + * @param base option bytes + * @param len of option bytes + * @return 0 on success, -ve on failure. + */ +static int stlink_write_option_bytes_l0(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint32_t len) { + uint32_t flash_base = get_stm32l0_flash_base(sl); + uint32_t val; + uint32_t data; + int ret = 0; + + // Clear errors + clear_flash_error(sl); + + while (len != 0) { + write_uint32((unsigned char *)&data, + *(uint32_t *)(base)); // write options bytes + + WLOG("Writing option bytes %#10x to %#10x\n", data, addr); + stlink_write_debug32(sl, addr, data); + wait_flash_busy(sl); + + if ((ret = check_flash_error(sl))) { + break; + } + + len -= 4; + addr += 4; + base += 4; + } + + // Reload options + stlink_read_debug32(sl, flash_base + FLASH_PECR_OFF, &val); + val |= (1 << STM32L0_FLASH_OBL_LAUNCH); + stlink_write_debug32(sl, flash_base + FLASH_PECR_OFF, val); + + return (ret); +} + +/** + * Write option bytes L4 + * @param sl + * @param addr of the memory mapped option bytes + * @param base option bytes + * @param len of option bytes + * @return 0 on success, -ve on failure. + */ +static int stlink_write_option_bytes_l4(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint32_t len) { + + uint32_t val; + int ret = 0; + (void)addr; + (void)len; + + // Clear errors + clear_flash_error(sl); + + // write options bytes + uint32_t data; + write_uint32((unsigned char *)&data, *(uint32_t *)(base)); + WLOG("Writing option bytes 0x%04x\n", data); + stlink_write_debug32(sl, STM32L4_FLASH_OPTR, data); + + // set options start bit + stlink_read_debug32(sl, STM32L4_FLASH_CR, &val); + val |= (1 << STM32L4_FLASH_CR_OPTSTRT); + stlink_write_debug32(sl, STM32L4_FLASH_CR, val); + + wait_flash_busy(sl); + ret = check_flash_error(sl); + + // apply options bytes immediate + stlink_read_debug32(sl, STM32L4_FLASH_CR, &val); + val |= (1 << STM32L4_FLASH_CR_OBL_LAUNCH); + stlink_write_debug32(sl, STM32L4_FLASH_CR, val); + + return (ret); +} + +/** + * Write option bytes WB * @param sl * @param addr of the memory mapped option bytes - * @param base option bytes to write + * @param base option bytes + * @param len of option bytes * @return 0 on success, -ve on failure. */ -static int stlink_write_option_bytes_wb(stlink_t *sl, uint8_t *base, - stm32_addr_t addr, uint32_t len) { +static int stlink_write_option_bytes_wb(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint32_t len) { /* Write options bytes */ uint32_t val; int ret = 0; @@ -490,8 +653,7 @@ static int stlink_write_option_bytes_wb(stlink_t *sl, uint8_t *base, clear_flash_error(sl); while (len != 0) { - write_uint32((unsigned char *)&data, - *(uint32_t *)(base)); // write options bytes + write_uint32((unsigned char *)&data, *(uint32_t *)(base)); // write options bytes WLOG("Writing option bytes %#10x to %#10x\n", data, addr); stlink_write_debug32(sl, addr, data); @@ -523,15 +685,71 @@ static int stlink_write_option_bytes_wb(stlink_t *sl, uint8_t *base, return (ret); } +/** + * Read option control register WB + * @param sl + * @param option_byte + * @return 0 on success, -ve on failure. + */ +int stlink_read_option_control_register_wb(stlink_t *sl, uint32_t *option_byte) { + DLOG("@@@@ Read option control register byte from %#10x\n", STM32WB_FLASH_OPTR); + return stlink_read_debug32(sl, STM32WB_FLASH_OPTR, option_byte); +} + +/** + * Write option control register WB + * @param sl + * @param option_cr + * @return 0 on success, -ve on failure. + */ +static int stlink_write_option_control_register_wb(stlink_t *sl, uint32_t option_cr) { + int ret = 0; + + // Clear errors + clear_flash_error(sl); + + ILOG("Asked to write option control register 1 %#10x to %#010x.\n", + option_cr, STM32WB_FLASH_OPTR); + + /* write option byte, ensuring we dont lock opt, and set strt bit */ + stlink_write_debug32(sl, STM32WB_FLASH_OPTR, option_cr); + + wait_flash_busy(sl); + + // Set Options Start bit + uint32_t val = (1 << STM32WB_FLASH_CR_OPTSTRT); + stlink_write_debug32(sl, STM32WB_FLASH_CR, val); + + wait_flash_busy(sl); + + ret = check_flash_error(sl); + if (!ret) + ILOG("Wrote option bytes %#010x to %#010x!\n", option_cr, STM32WB_FLASH_OPTR); + + return ret; +} + +/** + * Read option bytes generic + * @param sl + * @param option_byte + * @return 0 on success, -ve on failure. + */ +int stlink_read_option_bytes_generic(stlink_t *sl, uint32_t *option_byte) { + DLOG("@@@@ Read option bytes boot address from %#10x\n", sl->option_base); + return stlink_read_debug32(sl, sl->option_base, option_byte); +} + + /** * Write option bytes * @param sl * @param addr of the memory mapped option bytes - * @param base option bytes to write + * @param base option bytes + * @param len of option bytes * @return 0 on success, -ve on failure. */ -int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t *base, - uint32_t len) { +int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint32_t len) { int ret = -1; if (sl->option_base == 0) { @@ -566,29 +784,29 @@ int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t *base, switch (sl->flash_type) { case STM32_FLASH_TYPE_F0_F1_F3: case STM32_FLASH_TYPE_F1_XL: - ret = stlink_write_option_bytes_f0(sl, base, addr, len); + ret = stlink_write_option_bytes_f0(sl, addr, base, len); break; case STM32_FLASH_TYPE_F2_F4: - ret = stlink_write_option_bytes_f4(sl, base, addr, len); + ret = stlink_write_option_bytes_f4(sl, addr, base, len); break; case STM32_FLASH_TYPE_F7: - ret = stlink_write_option_bytes_f7(sl, base, addr, len); + ret = stlink_write_option_bytes_f7(sl, addr, base, len); break; case STM32_FLASH_TYPE_L0_L1: - ret = stlink_write_option_bytes_l0(sl, base, addr, len); + ret = stlink_write_option_bytes_l0(sl, addr, base, len); break; case STM32_FLASH_TYPE_L4_L4P: - ret = stlink_write_option_bytes_l4(sl, base, addr, len); + ret = stlink_write_option_bytes_l4(sl, addr, base, len); break; case STM32_FLASH_TYPE_G0: case STM32_FLASH_TYPE_G4: - ret = stlink_write_option_bytes_gx(sl, base, addr, len); + ret = stlink_write_option_bytes_gx(sl, addr, base, len); break; case STM32_FLASH_TYPE_H7: - ret = stlink_write_option_bytes_h7(sl, base, addr, len); + ret = stlink_write_option_bytes_h7(sl, addr, base, len); break; case STM32_FLASH_TYPE_WB_WL: - ret = stlink_write_option_bytes_wb(sl, base, addr, len); + ret = stlink_write_option_bytes_wb(sl, addr, base, len); break; default: ELOG("Option bytes writing is currently not implemented for connected " @@ -603,216 +821,72 @@ int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t *base, } /* Re-lock flash. */ - lock_flash_option(sl); - lock_flash(sl); - - return ret; -} - - -/** - * Write option bytes - * @param sl - * @param option_byte value to write - * @return 0 on success, -ve on failure. - */ -static int -stlink_write_option_control_register_f0(stlink_t *sl, - uint32_t option_control_register) { - int ret = 0; - uint16_t opt_val[8]; - unsigned protection, optiondata; - uint16_t user_options, user_data, rdp; - unsigned option_offset, user_data_offset; - - ILOG("Asked to write option control register %#10x to %#010x.\n", - option_control_register, FLASH_OBR); - - /* Clear errors */ - clear_flash_error(sl); - - /* Retrieve current values */ - ret = stlink_read_debug32(sl, FLASH_OBR, &optiondata); - if (ret) { - return ret; - } - ret = stlink_read_debug32(sl, FLASH_WRPR, &protection); - if (ret) { - return ret; - } - - /* Translate OBR value to flash store structure - * F0: RM0091, Option byte description, pp. 75-78 - * F1: PM0075, Option byte description, pp. 19-22 - * F3: RM0316, Option byte description, pp. 85-87 */ - switch(sl->chip_id) - { - case 0x422: /* STM32F30x */ - case 0x432: /* STM32F37x */ - case 0x438: /* STM32F303x6/8 and STM32F328 */ - case 0x446: /* STM32F303xD/E and STM32F398xE */ - case 0x439: /* STM32F302x6/8 */ - case 0x440: /* STM32F05x */ - case 0x444: /* STM32F03x */ - case 0x445: /* STM32F04x */ - case 0x448: /* STM32F07x */ - case 0x442: /* STM32F09x */ - option_offset = 6; - user_data_offset = 16; - rdp = 0x55AA; - break; - default: - option_offset = 0; - user_data_offset = 10; - rdp = 0x5AA5; - break; - } - - user_options = (option_control_register >> option_offset >> 2) & 0xFFFF; - user_data = (option_control_register >> user_data_offset) & 0xFFFF; - -#define VAL_WITH_COMPLEMENT(v) (uint16_t)(((v)&0xFF) | (((~(v))<<8)&0xFF00)) - - opt_val[0] = (option_control_register & (1 << 1/*OPT_READOUT*/)) ? 0xFFFF : rdp; - opt_val[1] = VAL_WITH_COMPLEMENT(user_options); - opt_val[2] = VAL_WITH_COMPLEMENT(user_data); - opt_val[3] = VAL_WITH_COMPLEMENT(user_data >> 8); - opt_val[4] = VAL_WITH_COMPLEMENT(protection); - opt_val[5] = VAL_WITH_COMPLEMENT(protection >> 8); - opt_val[6] = VAL_WITH_COMPLEMENT(protection >> 16); - opt_val[7] = VAL_WITH_COMPLEMENT(protection >> 24); - -#undef VAL_WITH_COMPLEMENT - - /* Write bytes and check errors */ - ret = stlink_write_option_bytes_f0(sl, (uint8_t*)opt_val, STM32_F0_OPTION_BYTES_BASE, sizeof(opt_val)); - if (ret) - return ret; - - ret = check_flash_error(sl); - if (!ret) { - ILOG("Wrote option bytes %#010x to %#010x!\n", option_control_register, - FLASH_OBR); - } - - return ret; -} - - -/** - * Write option bytes - * @param sl - * @param option_byte value to write - * @return 0 on success, -ve on failure. - */ -static int -stlink_write_option_control_register1_f7(stlink_t *sl, - uint32_t option_control_register1) { - int ret = 0; - - // Clear errors - clear_flash_error(sl); - - ILOG("Asked to write option control register 1 %#010x to %#010x.\n", - option_control_register1, FLASH_F7_OPTCR1); - - /* write option byte, ensuring we dont lock opt, and set strt bit */ - uint32_t current_control_register_value; - stlink_read_debug32(sl, FLASH_F7_OPTCR, ¤t_control_register_value); - - /* write option byte */ - stlink_write_debug32(sl, FLASH_F7_OPTCR1, option_control_register1); - stlink_write_debug32( - sl, FLASH_F7_OPTCR, - (current_control_register_value & ~(1 << FLASH_F7_OPTCR_LOCK)) | - (1 << FLASH_F7_OPTCR_START)); - - wait_flash_busy(sl); - - ret = check_flash_error(sl); - if (!ret) - ILOG("Wrote option bytes %#010x to %#010x!\n", option_control_register1, - FLASH_F7_OPTCR1); + lock_flash_option(sl); + lock_flash(sl); return ret; } /** - * Write option bytes + * Write the given binary file with option bytes * @param sl - * @param option_byte value to write + * @param path readable file path, should be binary image + * @param addr of the memory mapped option bytes * @return 0 on success, -ve on failure. */ -static int -stlink_write_option_control_register_f7(stlink_t *sl, - uint32_t option_control_register) { - int ret = 0; - - // Clear errors - clear_flash_error(sl); - - ILOG("Asked to write option control register 1 %#10x to %#010x.\n", - option_control_register, FLASH_F7_OPTCR); +int stlink_fwrite_option_bytes(stlink_t *sl, const char *path, stm32_addr_t addr) { + /* Write the file in flash at addr */ + int err; + mapped_file_t mf = MAPPED_FILE_INITIALIZER; - /* write option byte, ensuring we dont lock opt, and set strt bit */ - stlink_write_debug32(sl, FLASH_F7_OPTCR, - (option_control_register & ~(1 << FLASH_F7_OPTCR_LOCK)) | - (1 << FLASH_F7_OPTCR_START)); + if (map_file(&mf, path) == -1) { + ELOG("map_file() == -1\n"); + return (-1); + } - wait_flash_busy(sl); + printf("file %s ", path); + md5_calculate(&mf); + stlink_checksum(&mf); - ret = check_flash_error(sl); - if (!ret) - ILOG("Wrote option bytes %#010x to %#010x!\n", option_control_register, - FLASH_F7_OPTCR); + err = stlink_write_option_bytes(sl, addr, mf.base, (uint32_t)mf.len); + stlink_fwrite_finalize(sl, addr); + unmap_file(&mf); - return ret; + return (err); } /** - * Write option bytes + * Read option control register 32 * @param sl - * @param option_byte value to write + * @param option_byte * @return 0 on success, -ve on failure. */ -static int -stlink_write_option_control_register_wb(stlink_t *sl, - uint32_t option_control_register) { - int ret = 0; - - // Clear errors - clear_flash_error(sl); - - ILOG("Asked to write option control register 1 %#10x to %#010x.\n", - option_control_register, STM32WB_FLASH_OPTR); - - /* write option byte, ensuring we dont lock opt, and set strt bit */ - stlink_write_debug32(sl, STM32WB_FLASH_OPTR, option_control_register); - - wait_flash_busy(sl); - - // Set Options Start bit - uint32_t val = (1 << STM32WB_FLASH_CR_OPTSTRT); - stlink_write_debug32(sl, STM32WB_FLASH_CR, val); - - wait_flash_busy(sl); - - ret = check_flash_error(sl); - if (!ret) - ILOG("Wrote option bytes %#010x to %#010x!\n", option_control_register, - STM32WB_FLASH_OPTR); +int stlink_read_option_control_register32(stlink_t *sl, uint32_t *option_byte) { + if (sl->option_base == 0) { + ELOG("Option bytes read is currently not supported for connected chip\n"); + return -1; + } - return ret; + switch (sl->flash_type) { + case STM32_FLASH_TYPE_F0_F1_F3: + case STM32_FLASH_TYPE_F1_XL: + return stlink_read_option_control_register_f0(sl, option_byte); + case STM32_FLASH_TYPE_F7: + return stlink_read_option_control_register_f7(sl, option_byte); + case STM32_FLASH_TYPE_WB_WL: + return stlink_read_option_control_register_wb(sl, option_byte); + default: + return -1; + } } /** - * Write option bytes + * Write option control register 32 * @param sl - * @param option bytes boot address to write + * @param option_cr * @return 0 on success, -ve on failure. */ -int stlink_write_option_control_register32(stlink_t *sl, - uint32_t option_control_register) { +int stlink_write_option_control_register32(stlink_t *sl, uint32_t option_cr) { int ret = -1; wait_flash_busy(sl); @@ -831,14 +905,14 @@ int stlink_write_option_control_register32(stlink_t *sl, switch (sl->flash_type) { case STM32_FLASH_TYPE_F0_F1_F3: case STM32_FLASH_TYPE_F1_XL: - ret = stlink_write_option_control_register_f0(sl, option_control_register); + ret = stlink_write_option_control_register_f0(sl, option_cr); break; case STM32_FLASH_TYPE_F7: - ret = stlink_write_option_control_register_f7(sl, option_control_register); + ret = stlink_write_option_control_register_f7(sl, option_cr); break; case STM32_FLASH_TYPE_WB_WL: ret = - stlink_write_option_control_register_wb(sl, option_control_register); + stlink_write_option_control_register_wb(sl, option_cr); break; default: ELOG("Option control register writing is currently not implemented for " @@ -849,7 +923,7 @@ int stlink_write_option_control_register32(stlink_t *sl, if (ret) ELOG("Flash option write failed!\n"); else - ILOG("Wrote option control register %#010x!\n", option_control_register); + ILOG("Wrote option control register %#010x!\n", option_cr); /* Re-lock flash. */ lock_flash_option(sl); @@ -859,72 +933,33 @@ int stlink_write_option_control_register32(stlink_t *sl, } /** - * Write option bytes + * Read option control register1 32 * @param sl - * @param option bytes boot address to write + * @param option_byte * @return 0 on success, -ve on failure. */ -int stlink_write_option_control_register1_32( - stlink_t *sl, uint32_t option_control_register1) { - int ret = -1; - - wait_flash_busy(sl); - - if (unlock_flash_if(sl)) { - ELOG("Flash unlock failed! System reset required to be able to unlock it " - "again!\n"); - return -1; - } - - if (unlock_flash_option_if(sl)) { - ELOG("Flash option unlock failed!\n"); +int stlink_read_option_control_register1_32(stlink_t *sl, uint32_t *option_byte) { + if (sl->option_base == 0) { + ELOG("Option bytes read is currently not supported for connected chip\n"); return -1; } switch (sl->flash_type) { case STM32_FLASH_TYPE_F7: - ret = - stlink_write_option_control_register1_f7(sl, option_control_register1); - break; + return stlink_read_option_control_register1_f7(sl, option_byte); default: - ELOG("Option control register 1 writing is currently not implemented for " - "connected chip\n"); - break; + return -1; + // return stlink_read_option_control_register1_generic(sl, option_byte); } - - if (ret) - ELOG("Flash option write failed!\n"); - else - ILOG("Wrote option control register 1 %#010x!\n", option_control_register1); - - lock_flash_option(sl); - lock_flash(sl); - - return (ret); -} - - -/** - * Write option bytes - * @param sl - * @param option_byte value to write - * @return 0 on success, -ve on failure. - */ -static int -stlink_write_option_bytes_boot_add_f7(stlink_t *sl, - uint32_t option_byte_boot_add) { - ILOG("Asked to write option byte boot add %#010x.\n", option_byte_boot_add); - return stlink_write_option_control_register1_f7(sl, option_byte_boot_add); } /** - * Write option bytes + * Write option control register1 32 * @param sl - * @param option bytes boot address to write + * @param option_cr * @return 0 on success, -ve on failure. */ -int stlink_write_option_bytes_boot_add32(stlink_t *sl, - uint32_t option_bytes_boot_add) { +int stlink_write_option_control_register1_32(stlink_t *sl, uint32_t option_cr1) { int ret = -1; wait_flash_busy(sl); @@ -942,10 +977,11 @@ int stlink_write_option_bytes_boot_add32(stlink_t *sl, switch (sl->flash_type) { case STM32_FLASH_TYPE_F7: - ret = stlink_write_option_bytes_boot_add_f7(sl, option_bytes_boot_add); + ret = + stlink_write_option_control_register1_f7(sl, option_cr1); break; default: - ELOG("Option bytes boot address writing is currently not implemented for " + ELOG("Option control register 1 writing is currently not implemented for " "connected chip\n"); break; } @@ -953,108 +989,63 @@ int stlink_write_option_bytes_boot_add32(stlink_t *sl, if (ret) ELOG("Flash option write failed!\n"); else - ILOG("Wrote option bytes boot address %#010x!\n", option_bytes_boot_add); + ILOG("Wrote option control register 1 %#010x!\n", option_cr1); - /* Re-lock flash. */ lock_flash_option(sl); lock_flash(sl); - return ret; -} - -/** - * Write option bytes - * @param sl - * @param option_byte value to write - * @return 0 on success, -ve on failure. - */ -int stlink_write_option_bytes32(stlink_t *sl, uint32_t option_byte) { - WLOG("About to write option byte %#10x to %#10x.\n", option_byte, - sl->option_base); - return stlink_write_option_bytes(sl, sl->option_base, (uint8_t *)&option_byte, - 4); -} - -/** - * Write the given binary file with option bytes - * @param sl - * @param path readable file path, should be binary image - * @param addr of the memory mapped option bytes - * @return 0 on success, -ve on failure. - */ -int stlink_fwrite_option_bytes(stlink_t *sl, const char *path, - stm32_addr_t addr) { - /* Write the file in flash at addr */ - int err; - mapped_file_t mf = MAPPED_FILE_INITIALIZER; - - if (map_file(&mf, path) == -1) { - ELOG("map_file() == -1\n"); - return (-1); - } - - printf("file %s ", path); - md5_calculate(&mf); - stlink_checksum(&mf); - - err = stlink_write_option_bytes(sl, addr, mf.base, (uint32_t)mf.len); - stlink_fwrite_finalize(sl, addr); - unmap_file(&mf); - - return (err); -} - -/** - * Read option bytes - * @param sl - * @param option_byte value to read - * @return 0 on success, -ve on failure. - */ -int stlink_read_option_control_register1_f7(stlink_t *sl, - uint32_t *option_byte) { - DLOG("@@@@ Read option control register 1 byte from %#10x\n", - FLASH_F7_OPTCR1); - return stlink_read_debug32(sl, FLASH_F7_OPTCR1, option_byte); + return (ret); } /** - * Read option bytes + * Read option bytes 32 * @param sl - * @param option_byte option value + * @param option_byte * @return 0 on success, -ve on failure. */ -int stlink_read_option_control_register1_32(stlink_t *sl, - uint32_t *option_byte) { +int stlink_read_option_bytes32(stlink_t *sl, uint32_t *option_byte) { if (sl->option_base == 0) { ELOG("Option bytes read is currently not supported for connected chip\n"); - return -1; + return (-1); } - switch (sl->flash_type) { - case STM32_FLASH_TYPE_F7: - return stlink_read_option_control_register1_f7(sl, option_byte); + switch (sl->chip_id) { + case STM32_CHIPID_F2: + return stlink_read_option_bytes_f2(sl, option_byte); + case STM32_CHIPID_F4: + case STM32_CHIPID_F446: + return stlink_read_option_bytes_f4(sl, option_byte); + case STM32_CHIPID_F76xxx: + return stlink_read_option_bytes_f7(sl, option_byte); + case STM32_CHIPID_G0_CAT1: + return stlink_read_option_bytes_gx(sl, option_byte); + case STM32_CHIPID_G0_CAT2: + return stlink_read_option_bytes_gx(sl, option_byte); + case STM32_CHIPID_G4_CAT2: + return stlink_read_option_bytes_gx(sl, option_byte); + case STM32_CHIPID_G4_CAT3: + return stlink_read_option_bytes_gx(sl, option_byte); default: - return -1; - // return stlink_read_option_control_register1_generic(sl, option_byte); + return stlink_read_option_bytes_generic(sl, option_byte); } } - /** - * Read option bytes + * Write option bytes 32 * @param sl - * @param option_byte value to read + * @param option_byte * @return 0 on success, -ve on failure. */ -int stlink_read_option_bytes_boot_add_f7(stlink_t *sl, uint32_t *option_byte) { - DLOG("@@@@ Read option byte boot address\n"); - return stlink_read_option_control_register1_f7(sl, option_byte); +int stlink_write_option_bytes32(stlink_t *sl, uint32_t option_byte) { + WLOG("About to write option byte %#10x to %#10x.\n", option_byte, + sl->option_base); + return stlink_write_option_bytes(sl, sl->option_base, (uint8_t *)&option_byte, 4); } /** - * Read option bytes + * Read option bytes boot address 32 * @param sl - * @param option_byte option value + * @param option_byte * @return 0 on success, -ve on failure. */ int stlink_read_option_bytes_boot_add32(stlink_t *sl, uint32_t *option_byte) { @@ -1074,62 +1065,45 @@ int stlink_read_option_bytes_boot_add32(stlink_t *sl, uint32_t *option_byte) { } /** - * Read option bytes + * Write option bytes boot address 32 * @param sl - * @param option_byte value to read + * @param option_bytes_boot_add * @return 0 on success, -ve on failure. */ -int stlink_read_option_control_register_f7(stlink_t *sl, - uint32_t *option_byte) { - DLOG("@@@@ Read option control register byte from %#10x\n", FLASH_F7_OPTCR); - return stlink_read_debug32(sl, FLASH_F7_OPTCR, option_byte); -} +int stlink_write_option_bytes_boot_add32(stlink_t *sl, uint32_t option_bytes_boot_add) { + int ret = -1; -/** - * Read option bytes - * @param sl - * @param option_byte value to read - * @return 0 on success, -ve on failure. - */ -int stlink_read_option_control_register_f0(stlink_t *sl, - uint32_t *option_byte) { - DLOG("@@@@ Read option control register byte from %#10x\n", FLASH_OBR); - return stlink_read_debug32(sl, FLASH_OBR, option_byte); -} + wait_flash_busy(sl); -/** - * Read option bytes - * @param sl - * @param option_byte value to read - * @return 0 on success, -ve on failure. - */ -int stlink_read_option_control_register_wb(stlink_t *sl, - uint32_t *option_byte) { - DLOG("@@@@ Read option control register byte from %#10x\n", STM32WB_FLASH_OPTR); - return stlink_read_debug32(sl, STM32WB_FLASH_OPTR, option_byte); -} + if (unlock_flash_if(sl)) { + ELOG("Flash unlock failed! System reset required to be able to unlock it " + "again!\n"); + return -1; + } -/** - * Read option bytes - * @param sl - * @param option_byte option value - * @return 0 on success, -ve on failure. - */ -int stlink_read_option_control_register32(stlink_t *sl, uint32_t *option_byte) { - if (sl->option_base == 0) { - ELOG("Option bytes read is currently not supported for connected chip\n"); + if (unlock_flash_option_if(sl)) { + ELOG("Flash option unlock failed!\n"); return -1; } switch (sl->flash_type) { - case STM32_FLASH_TYPE_F0_F1_F3: - case STM32_FLASH_TYPE_F1_XL: - return stlink_read_option_control_register_f0(sl, option_byte); case STM32_FLASH_TYPE_F7: - return stlink_read_option_control_register_f7(sl, option_byte); - case STM32_FLASH_TYPE_WB_WL: - return stlink_read_option_control_register_wb(sl, option_byte); + ret = stlink_write_option_bytes_boot_add_f7(sl, option_bytes_boot_add); + break; default: - return -1; + ELOG("Option bytes boot address writing is currently not implemented for " + "connected chip\n"); + break; } + + if (ret) + ELOG("Flash option write failed!\n"); + else + ILOG("Wrote option bytes boot address %#010x!\n", option_bytes_boot_add); + + /* Re-lock flash. */ + lock_flash_option(sl); + lock_flash(sl); + + return ret; } diff --git a/src/stlink-lib/option_bytes.h b/src/stlink-lib/option_bytes.h new file mode 100644 index 000000000..b9f88c508 --- /dev/null +++ b/src/stlink-lib/option_bytes.h @@ -0,0 +1,21 @@ +/* + * File: option_bytes.h + * + * Read and write option bytes and option control registers + */ + +#include +#include + +int stlink_read_option_bytes32(stlink_t *sl, uint32_t* option_byte); +int stlink_read_option_bytes_boot_add32(stlink_t *sl, uint32_t* option_byte); +int stlink_read_option_control_register32(stlink_t *sl, uint32_t* option_byte); +int stlink_read_option_control_register1_32(stlink_t *sl, uint32_t* option_byte); + +int stlink_write_option_bytes32(stlink_t *sl, uint32_t option_byte); +int stlink_write_option_bytes_boot_add32(stlink_t *sl, uint32_t option_bytes_boot_add); +int stlink_write_option_control_register32(stlink_t *sl, uint32_t option_cr); +int stlink_write_option_control_register1_32(stlink_t *sl, uint32_t option_cr1); + +int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t len); +int stlink_fwrite_option_bytes(stlink_t *sl, const char* path, stm32_addr_t addr); diff --git a/src/read_write.c b/src/stlink-lib/read_write.c similarity index 100% rename from src/read_write.c rename to src/stlink-lib/read_write.c From aee9a47e3551d3cac9449ef1cceed30ecdcff133 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Fri, 30 Dec 2022 18:01:06 +0100 Subject: [PATCH 409/503] General fixes and improvements - Bugfix: "Failed to parse flash type or unrecognized flash type" (Closes #1240) (Closes #1242) (Closes #1290) (Closes #1291) - Updated README.md on OS-support - Updated version_support.md - Removed remnants of macOS support in CMakeLists.txt - Minor code formatting fixes - Updated CHANGELOG.md --- CHANGELOG.md | 17 +++-- CMakeLists.txt | 10 +-- README.md | 8 +-- doc/version_support.md | 154 +++++++++++++++++++++------------------- src/st-flash/flash.c | 24 ++++--- src/st-trace/trace.c | 3 +- src/stlink-lib/chipid.c | 28 ++++++-- src/stlink-lib/common.c | 2 +- 8 files changed, 134 insertions(+), 112 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index f48840c3f..82656d50b 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -2,7 +2,7 @@ # v1.7.1 -Release date: 2022-xx-xx +Release date: 2023-xx-xx This release drops support for some older operating systems. Check project README for details. @@ -18,7 +18,7 @@ Features: - Added option byte info for STM32F411XX ([#1141](https://github.com/stlink-org/stlink/pull/1141)) - Expanded and revised list of chips ([#1145](https://github.com/stlink-org/stlink/pull/1145), [#1164](https://github.com/stlink-org/stlink/pull/1164)) - [STM32H72X/3X]: Added full access to all device memory ([#1158](https://github.com/stlink-org/stlink/pull/1158), [#1159](https://github.com/stlink-org/stlink/pull/1159)) -- Added support for STM32WLEx ([#1173](https://github.com/stlink-org/stlink/pull/1173)) +- Added support for STM32WLEx ([#1173](https://github.com/stlink-org/stlink/pull/1173), [#1273](https://github.com/stlink-org/stlink/pull/1273)) - Added support for STLINK-V3 devices with no MSD ([#1185](https://github.com/stlink-org/stlink/pull/1185)) - Updated gdb-server.c to allow external memory access on STM32H73xx ([#1196](https://github.com/stlink-org/stlink/pull/1196), [#1197](https://github.com/stlink-org/stlink/pull/1197)) - Erase addr size / section of the flash memory with st-flash ([#1213](https://github.com/stlink-org/stlink/pull/1213)) @@ -26,10 +26,12 @@ Features: - Added parametres option_base, option_size for F401xD_xE ([#1235](https://github.com/stlink-org/stlink/pull/1235)) - Added support for option bytes to F1xx_XLD (GD32F30x) ([#1250](https://github.com/stlink-org/stlink/pull/1250)) - Added option byte address for L4Rx devices ([#1254](https://github.com/stlink-org/stlink/pull/1254)) +- Added udev-rule rule for the STLink v3 MINIE programmer ([#1274](https://github.com/stlink-org/stlink/pull/1274), [#1281](https://github.com/stlink-org/stlink/pull/1281)) Updates & changes: - [refactoring] Moved chip-specific parameters into separate files ([#237](https://github.com/stlink-org/stlink/pull/237), [#1129](https://github.com/stlink-org/stlink/pull/1129)) +- [refactoring] General maintenance for code structure ([#903](https://github.com/stlink-org/stlink/pull/903), [#1090](https://github.com/stlink-org/stlink/pull/1090), [#1199](https://github.com/stlink-org/stlink/pull/1199), [#1212](https://github.com/stlink-org/stlink/pull/1212), [#1216](https://github.com/stlink-org/stlink/pull/1216)) - Added instructions for bug-reports and feature-requests to contribution guidelines ([#906](https://github.com/stlink-org/stlink/pull/906)) - Added travis CI configuration for macOS 10.14 to maintain capability for 32-bit compilation (commit [#f5ada94](https://github.com/stlink-org/stlink/commit/f5ada9474cdb87ff37de0d4eb9e75622b5870646)) - Updated description of chip id 0x0457 to L01x/L02x ([#1143](https://github.com/stlink-org/stlink/pull/1143), [#1144](https://github.com/stlink-org/stlink/pull/1144)) @@ -45,6 +47,7 @@ Updates & changes: - [doc] Linux Install from code Documentation improvement ([#1263](https://github.com/stlink-org/stlink/pull/1263), (commit [#43498de](https://github.com/stlink-org/stlink/commit/43498dedf651260ef34197e512d35e3ad7142401)) Fixes: +- cmake: Install shared libraries in proper directories ([#1098](https://github.com/stlink-org/stlink/pull/1098), [#1138](https://github.com/stlink-org/stlink/pull/1138), [#1154](https://github.com/stlink-org/stlink/pull/1154)) - cmake: Install shared libraries in proper directories ([#1142](https://github.com/stlink-org/stlink/pull/1142)) - Fixed clearance of the H7 dual bank flag ([#1146](https://github.com/stlink-org/stlink/pull/1146), [#1147](https://github.com/stlink-org/stlink/pull/1147)) - Fix for 'libusb_devices were leaked' when no ST-LINK programmer was found ([#1150](https://github.com/stlink-org/stlink/pull/1150)) @@ -66,6 +69,10 @@ Fixes: - Fixed compilation with gcc-12 ([#1257](https://github.com/stlink-org/stlink/pull/1257), [#1267](https://github.com/stlink-org/stlink/pull/1267)) - Fixed flash regs addr for STM32L152RET6 in common_flash.c ([#1265](https://github.com/stlink-org/stlink/pull/1265)) - Fixed flash, dbgmcu and rcc registers for STM32L1 ([#1266](https://github.com/stlink-org/stlink/pull/1266)) +- Fixed compilation with gcc-12 ([#1257](https://github.com/stlink-org/stlink/pull/1257), [#1267](https://github.com/stlink-org/stlink/pull/1267)) +- Fixes for project compilation ([#1270](https://github.com/stlink-org/stlink/pull/1270), [#1271](https://github.com/stlink-org/stlink/pull/1271), [#1283](https://github.com/stlink-org/stlink/pull/1283), [#1286](https://github.com/stlink-org/stlink/pull/1286),commit [#f93adb9](https://github.com/stlink-org/stlink/commit/f93adb92f2e4ecf05a9361cb723c98693586929d)) +- [compilation] Corrected path to stlink/chips subdirectory ([#1276](https://github.com/stlink-org/stlink/pull/1276), [#1279](https://github.com/stlink-org/stlink/pull/1279)) +- [compilation] Fixed GUI compilation failure on OpenBSD i386 ([#1284](https://github.com/stlink-org/stlink/pull/1284)) # v1.7.0 @@ -96,7 +103,7 @@ Updates & changes: - [doc] Updated documentation on target resetting ([#261](https://github.com/stlink-org/stlink/pull/261), [#533](https://github.com/stlink-org/stlink/pull/533), [#1107](https://github.com/stlink-org/stlink/pull/1107)) - [doc] Added note on `(gdb) run` command (commit [#03793d4](https://github.com/stlink-org/stlink/commit/03793d42b6078344a9ef8ad55f1d5d0fc19e486e), [#267](https://github.com/stlink-org/stlink/pull/267)) - [doc] `st-flash --reset` parameter (one solution for #356) ([#642](https://github.com/stlink-org/stlink/pull/642)) -- [refactoring] General maintenance ([#864](https://github.com/stlink-org/stlink/pull/864), [#976](https://github.com/stlink-org/stlink/pull/976), [#978](https://github.com/stlink-org/stlink/pull/978)) +- [refactoring] General maintenance ([#864](https://github.com/stlink-org/stlink/pull/864). [#978](https://github.com/stlink-org/stlink/pull/978)) - Imported debian pkg-settings ([#986](https://github.com/stlink-org/stlink/pull/986)) - Add support for FreeBSD's `libusb` reimplementation ([#992](https://github.com/stlink-org/stlink/pull/992), [#993](https://github.com/stlink-org/stlink/pull/993)) - [doc] Added explanation about STM32F103 fake chips (commit [#a66557a](https://github.com/stlink-org/stlink/commit/a66557a102d48e69feb0a9746e8e42c4baf31fe2), [#1024](https://github.com/stlink-org/stlink/pull/1024)) @@ -117,7 +124,7 @@ Fixes: - doc/man: Fixed installation directory ([#970](https://github.com/stlink-org/stlink/pull/970)) - Fixed installation path for desktop-file and icons ([#972](https://github.com/stlink-org/stlink/pull/972)) - Fix for static linking of `libssp` ([#973](https://github.com/stlink-org/stlink/pull/973), [#974](https://github.com/stlink-org/stlink/pull/974)) -- [regression] Fixed wrong formatting for library install path ([#978](https://github.com/stlink-org/stlink/pull/978), [#1089](https://github.com/stlink-org/stlink/pull/1089)) +- [regression] Fixed wrong formatting for library install path ([#978](https://github.com/stlink-org/stlink/pull/978), [#1089](https://github.com/stlink-org/stlink/pull/1089), [#1277](https://github.com/stlink-org/stlink/pull/1277)) - Fixed installation of header files needed for compiling with `libstlink.so.1.6.1` (commit [#31b1fa1](https://github.com/stlink-org/stlink/commit/31b1fa16201521e2aaf464576f2f169981abede0), [#982](https://github.com/stlink-org/stlink/pull/982)) - Fixed `connect under reset` for `st-flash` and `st-util` ([#983](https://github.com/stlink-org/stlink/pull/983)) - Fix for `mmap() size_t overflow` in `st-flash` ([#988](https://github.com/stlink-org/stlink/pull/988), [#989](https://github.com/stlink-org/stlink/pull/989)) @@ -190,7 +197,7 @@ Updates & changes: - [doc] `st-flash --flash=n[k][m]` command line option to override device model ([#902](https://github.com/stlink-org/stlink/pull/902)) - [refactoring] Improved cmake build process ([#912](https://github.com/stlink-org/stlink/pull/912)) - Set up a `libusb` log level accordingly to verbosity ([#894](https://github.com/stlink-org/stlink/pull/894) - - [compatibility] Updated `libusb` to v1.0.23 ([#895](https://github.com/stlink-org/stlink/pull/895, [#1089](https://github.com/stlink-org/stlink/pull/1089)) + - [compatibility] Updated `libusb` to v1.0.23 ([#895](https://github.com/stlink-org/stlink/pull/895) - Updated compiling doc & version support ([#896](https://github.com/stlink-org/stlink/pull/896), [#897](https://github.com/stlink-org/stlink/pull/897), [#899](https://github.com/stlink-org/stlink/pull/899)) - Version requirements & pkg-maintainer - Fixed install paths in build script diff --git a/CMakeLists.txt b/CMakeLists.txt index 3a22fdedc..f7bbe6f12 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -78,13 +78,9 @@ include(GNUInstallDirs) # Define GNU standard installation directories cmake_host_system_information(RESULT OS_NAME QUERY OS_NAME) message(STATUS "Checking for OS_NAME: ${OS_NAME}") -if (OS_NAME STREQUAL "macOS") - message(STATUS "set(CMAKE_INSTALL_SHAREDIR /usr/local/share)") - set(CMAKE_INSTALL_SHAREDIR /usr/local/share/) -else () - message(STATUS "set(CMAKE_INSTALL_SHAREDIR /usr/share)") - set(CMAKE_INSTALL_SHAREDIR /usr/share/) -endif () +message(STATUS "set(CMAKE_INSTALL_SHAREDIR /usr/share)") +set(CMAKE_INSTALL_SHAREDIR /usr/share/) + ## Set C build flags if (NOT MSVC) diff --git a/README.md b/README.md index 571db49fd..9a36f0fbb 100644 --- a/README.md +++ b/README.md @@ -67,7 +67,7 @@ Please ensure to select the correct version for your system (i686 or x86_64). Th Alternatively one may compile and install from source as described in our [compiling manual](doc/compiling.md#Windows). -**Linux**: +**Linux / Unix**: We recommend to install `stlink-tools` from the package repository of the used distribution: @@ -78,13 +78,7 @@ We recommend to install `stlink-tools` from the package repository of the used d - Arch Linux: [(Link)](https://www.archlinux.org/packages/community/x86_64/stlink) - Alpine Linux: [(Link)](https://pkgs.alpinelinux.org/packages?name=stlink) - Fedora: [(Link)](https://src.fedoraproject.org/rpms/stlink) -- Gentoo Linux: [(Link)](https://packages.gentoo.org/packages/dev-embedded/stlink) - -**Other Operating Systems**: - -- RedHat/CentOS 8: Users can install from [EPEL repository](https://src.fedoraproject.org/rpms/stlink/branch/epel8) - FreeBSD: Users can install from [freshports](https://www.freshports.org/devel/stlink) -- MacOS: Users can open a terminal window and then follow the same procedure as for installing on Linux ## Installation from source (advanced users) diff --git a/doc/version_support.md b/doc/version_support.md index 0f1849697..593c86549 100644 --- a/doc/version_support.md +++ b/doc/version_support.md @@ -8,88 +8,94 @@ On Windows users should ensure that cmake **3.10.2** or any later version is ins Up on compiling c-make will **automatically** download and install the latest compatible version of `libusb`. - Windows 10 -- Windows 8.1 +- Windows 11 ### Linux-/Unix-based: -| Operating System | libusb | cmake | libgtk-dev | Notes | -| ------------------------- | ------------------------------ | ---------- | ----------- | ------------------------ | -| Debian Sid | 1.0.24 | 3.22.1 | 3.24.31 | | -| Debian 11 (Bullseye) | 1.0.24 | 3.18.4 | 3.24.24 | | -| Debian 10 (Buster) | 1.0.**22** | **3.13.4** | 3.24.**5** | | -| | | | | | -| Ubuntu 20.04 LTS (Focal) | 1.0.23 | 3.16.3 | 3.24.**18** | | -| Ubuntu 18.04 LTS (Bionic) | 1.0.**21** | **3.10.2** | 3.**22.30** | End of Support: Apr 2023 | -| | | | | | -| Fedora Rawhide [x64] | 1.0.24 | 3.22.3 | 3.24.31 | | -| Fedora 35 [x64] | 1.0.24 | 3.21.3 | 3.24.30 | | -| Fedora 34 [x64] | 1.0.24 (`libusbx`) | 3.19.7 | 3.24.28 | | -| | | | | | -| openSUSE Tumbleweed [x64] | 1.0.24 | 3.22.1 | 3.24.31 | | -| openSUSE Leap 15.3 [x64] | 1.0.**21** | 3.17.0 | 3.24.20 | End of Support: Dec 2022 | -| | | | | | -| Alpine 3.15 | 1.0.24 | 3.21.3 | 3.24.30 | | -| Alpine 3.14 | 1.0.24 | 3.20.3 | 3.24.28 | | -| Alpine 3.13 | 1.0.24 | 3.18.4 | 3.24.23 | End of Support: Nov 2022 | -| Alpine 3.12 | 1.0.23 | 3.17.2 | 3.24.22 | End of Support: May 2022 | -| | | | | | -| FreeBSD 13.x | 1.0.**16-18** (API 0x01000102) | 3.22.1 | 3.24.31 | | -| FreeBSD 12.x | 1.0.**16-18** (API 0x01000102) | 3.22.1 | 3.24.31 | | -| | | | | | -| NetBSD 9.x | 1.0.24 | 3.21.2 | 3.24.30 | | -| NetBSD 8.x | 1.0.24 | 3.19.7 | 3.24.27 | | -| | | | | | -| CentOS 9 Stream [x64] | 1.0.24 (`libusbx`) | 3.20.3 | 3.24.30 | | -| CentOS 8 Stream [x64] | 1.0.23 (`libusbx`) | 3.20.2 | 3.**22.30** | | -| | | | | | -| ALT Linux Sisyphus | 1.0.24 | 3.22.1 | 3.24.31 | | -| ALT Linux P10 | 1.0.24 | 3.20.5 | 3.24.31 | | -| ALT Linux P9 | 1.0.**22** | 3.16.3 | 3.24.29 | | -| | | | | | -| OpenMandriva Rolling | 1.0.24 | 3.22.1 | 3.24.31 | | -| OpenMandriva Cooker | 1.0.24 | 3.22.1 | 3.24.31 | | -| OpenMandriva Lx 4.2 | 1.0.24 | 3.19.3 | 3.24.24 | | -| | | | | | -| Arch Linux | 1.0.24 | 3.22.1 | - | | -| KaOS [x64] | 1.0.24 | 3.22.1 | 3.24.31 | | -| Mageia Cauldron | 1.0.24 | 3.22.1 | 3.24.31 | | -| PCLinuxOS [x64] | ? | 3.22.1 | 3.24.31 | | -| Solus [x64] | 1.0.24 | 3.22.1 | 3.24.30 | | -| Void Linux | 1.0.24 | 3.22.1 | 3.24.31 | | -| Slackware Current | 1.0.24 | 3.21.4 | 3.24.31 | | -| AlmaLinux 8 | 1.0.23 (`libusbx`) | 3.20.2 | 3.**22.30** | | -| Rocky Linux 8 [x64] | 1.0.23 | 3.20.2 | 3.**22.30** | | -| Mageia 8 | 1.0.24 | 3.19.2 | 3.24.24 | End of Support: Aug 2022 | -| Adélie 1.0 | 1.0.23 | 3.16.4 | 3.24.23 | | +Maintained versions of: +- Debian +- Ubuntu +- Fedora +- openSUSE +- OpenMandriva +- Arch Linux +- FreeBSD +- NetBSD + +Other Linux-/Unix-based Operating Systems: + +| Operating System | libusb | cmake | libgtk-dev | Notes | +| ------------------------ | ------------------------------ | ---------- | ----------- | ------------------------ | +| Debian Sid | 1.0.24 | 3.22.1 | 3.24.31 | | +| Debian 11 (Bullseye) | 1.0.24 | 3.**18.4** | 3.24.24 | | +| Debian 10 (Buster) | 1.0.**22** | 3.**13.4** | 3.24.**5** | | +| | | | | | +| Ubuntu 20.04 LTS (Focal) | 1.0.23 | 3.**16.3** | 3.24.**18** | | +| | | | | | +| Alpine 3.15 | 1.0.24 | 3.21.3 | 3.24.30 | End of Support: Nov 2023 | +| Alpine 3.14 | 1.0.24 | 3.20.3 | 3.24.28 | End of Support: May 2023 | +| | | | | | +| FreeBSD 13.x | 1.0.**16-18** (API 0x01000102) | 3.22.1 | 3.24.31 | | +| FreeBSD 12.x | 1.0.**16-18** (API 0x01000102) | 3.22.1 | 3.24.31 | | +| | | | | | +| NetBSD 9.x | 1.0.24 | 3.21.2 | 3.24.30 | | +| NetBSD 8.x | 1.0.24 | 3.**19.7** | 3.24.27 | | +| | | | | | +| CentOS 9 Stream [x64] | 1.0.24 (`libusbx`) | 3.20.3 | 3.24.30 | | +| CentOS 8 Stream [x64] | 1.0.23 (`libusbx`) | 3.20.2 | 3.**22.30** | | +| | | | | | +| ALT Linux Sisyphus | 1.0.24 | 3.22.1 | 3.24.31 | | +| ALT Linux P10 | 1.0.24 | 3.20.5 | 3.24.31 | | +| ALT Linux P9 | 1.0.**22** | 3.**16.3** | 3.24.29 | | +| | | | | | +| OpenMandriva Rolling | 1.0.24 | 3.22.1 | 3.24.31 | | +| OpenMandriva Cooker | 1.0.24 | 3.22.1 | 3.24.31 | | +| OpenMandriva Lx 4.2 | 1.0.24 | 3.**19.3** | 3.24.24 | | +| | | | | | +| Arch Linux | 1.0.24 | 3.22.1 | - | | +| KaOS [x64] | 1.0.24 | 3.22.1 | 3.24.31 | | +| Mageia Cauldron | 1.0.24 | 3.22.1 | 3.24.31 | | +| PCLinuxOS [x64] | (?) | 3.22.1 | 3.24.31 | | +| Solus [x64] | 1.0.24 | 3.22.1 | 3.24.30 | | +| Void Linux | 1.0.24 | 3.22.1 | 3.24.31 | | +| Slackware Current | 1.0.24 | 3.21.4 | 3.24.31 | | +| AlmaLinux 8 | 1.0.23 (`libusbx`) | 3.20.2 | 3.**22.30** | | +| Rocky Linux 8 [x64] | 1.0.23 | 3.20.2 | 3.**22.30** | | +| Adélie 1.0 | 1.0.23 | 3.**16.4** | 3.24.23 | | ## Unsupported Operating Systems (as of Release v1.7.1) Systems with highlighted versions remain compatible with this toolset. -| Operating System | libusb | cmake | End of
OS-Support | -| ------------------------ | ------------------------------ | ---------- | ---------------------- | -| CentOS 8 [x64] | 1.0.**23** (`libusbx`) | 3.**20.3** | Dec 2021 | -| Ubuntu 21.04 (Hirsute) | 1.0.**24** | 3.**18.4** | Jan 2022 | -| Fedora 33 [x64] | 1.0.**23** (`libusbx`) | 3.**18.3** | Nov 2021 | -| Fedora 32 [x64] | 1.0.**23** (`libusbx`) | 3.**17.0** | May 2021 | -| openSUSE Leap 15.2 [x64] | 1.0.**21** | 3.**17.0** | Dec 2021 | -| Ubuntu 20.10 (Groovy) | 1.0.**23** | 3.**16.3** | Jul 2021 | -| NetBSD 7.x | 1.0.**22** | 3.**16.1** | Jun 2020 | -| Alpine 3.11 | 1.0.**23** | 3.**15.5** | Nov 2021 | -| FreeBSD 11.x | 1.0.**16-18** (API 0x01000102) | 3.**15.5** | Sep 2021 | -| Alpine 3.10 | 1.0.**22** | 3.**14.5** | May 2021 | -| Fedora 31 [x64] | 1.0.**22**(`libusbx`) | 3.**14.5** | Nov 2020 | -| Mageia 7.1 | 1.0.**22** | 3.**14.3** | Jun 2021 | -| Fedora 30 | 1.0.**22**(`libusbx`) | 3.**14.2** | May 2020 | -| Ubuntu 19.10 (Eoan) | 1.0.**23** | 3.**13.4** | Jul 2020 | -| Alpine 3.9 | 1.0.**22** | 3.**13.0** | Jan 2021 | -| openSUSE Leap 15.1 [x64] | 1.0.**21** | 3.**10.2** | Jan 2021 | -| Debian 9 (Stretch) | 1.0.**21** | 3.7.2 | Jun 2022 | -| Slackware 14.2 | 1.0.20 | 3.5.2 | | -| OpenMandriva Lx 3.0x | 1.0.20 | 3.4.2 | | -| CentOS 7 [x64] | 1.0.**21** (`libusbx`) | 2.8.12.2 | Jun 2024 | -| Slackware 14.1 | 1.0.9 | 2.8.12 | | -| Slackware 14.0 | 1.0.9 | 2.8.8 | | +| Operating System | libusb | cmake | End of
OS-Support | +| ------------------------- | ------------------------------ | ---------- | ---------------------- | +| Fedora 35 [x64] | 1.0.**24** | 3.**21.3** | Dec 2022 | +| CentOS 8 [x64] | 1.0.**23** (`libusbx`) | 3.**20.3** | Dec 2021 | +| Fedora 34 [x64] | 1.0.**24** (`libusbx`) | 3.**19.7** | Jun 2022 | +| Mageia 8 | 1.0.**24** | 3.**19.2** | Aug 2022 | +| Alpine 3.13 | 1.0.**24** | 3.**18.4** | Nov 2022 | +| Ubuntu 21.04 (Hirsute) | 1.0.**24** | 3.**18.4** | Jan 2022 | +| Fedora 33 [x64] | 1.0.**23** (`libusbx`) | 3.**18.3** | Nov 2021 | +| Alpine 3.12 | 1.0.**23** | 3.**17.2** | May 2022 | +| openSUSE Leap 15.3 [x64] | 1.0.**21** | 3.**17.0** | Dec 2022 | +| Fedora 32 [x64] | 1.0.**23** (`libusbx`) | 3.**17.0** | May 2021 | +| openSUSE Leap 15.2 [x64] | 1.0.**21** | 3.**17.0** | Dec 2021 | +| Ubuntu 20.10 (Groovy) | 1.0.**23** | 3.**16.3** | Jul 2021 | +| NetBSD 7.x | 1.0.**22** | 3.**16.1** | Jun 2020 | +| Alpine 3.11 | 1.0.**23** | 3.**15.5** | Nov 2021 | +| FreeBSD 11.x | 1.0.**16-18** (API 0x01000102) | 3.**15.5** | Sep 2021 | +| Alpine 3.10 | 1.0.**22** | 3.**14.5** | May 2021 | +| Fedora 31 [x64] | 1.0.**22**(`libusbx`) | 3.**14.5** | Nov 2020 | +| Mageia 7.1 | 1.0.**22** | 3.**14.3** | Jun 2021 | +| Fedora 30 | 1.0.**22**(`libusbx`) | 3.**14.2** | May 2020 | +| Ubuntu 19.10 (Eoan) | 1.0.**23** | 3.**13.4** | Jul 2020 | +| Alpine 3.9 | 1.0.**22** | 3.**13.0** | Jan 2021 | +| Ubuntu 18.04 LTS (Bionic) | 1.0.**21** | 3.**10.2** | **Apr 2023** | +| openSUSE Leap 15.1 [x64] | 1.0.**21** | 3.**10.2** | Jan 2021 | +| Debian 9 (Stretch) | 1.0.21 | 3.7.2 | Jun 2022 | +| Slackware 14.2 | 1.0.20 | 3.5.2 | | +| OpenMandriva Lx 3.0x | 1.0.20 | 3.4.2 | | +| CentOS 7 [x64] | 1.0.21 (`libusbx`) | 2.8.12.2 | Jun 2024 | _All other operating systems which are not listed are unsupported._ diff --git a/src/st-flash/flash.c b/src/st-flash/flash.c index 0985c75c2..4b8e37fef 100644 --- a/src/st-flash/flash.c +++ b/src/st-flash/flash.c @@ -71,6 +71,7 @@ int main(int ac, char** av) { if (sl->flash_type == STM32_FLASH_TYPE_UNKNOWN) { printf("Failed to connect to target\n"); + fprintf(stderr, "Failed to parse flash type or unrecognized flash type\n"); goto on_error; } @@ -98,8 +99,10 @@ int main(int ac, char** av) { goto on_error; } - if (o.cmd == FLASH_CMD_WRITE) { // write + if (o.cmd == FLASH_CMD_WRITE) { size_t size = 0; + + // write if (o.format == FLASH_FORMAT_IHEX) { err = stlink_parse_ihex(o.filename, stlink_get_erased_pattern(sl), &mem, &size, &o.addr); @@ -108,8 +111,7 @@ int main(int ac, char** av) { goto on_error; } } - if ((o.addr >= sl->flash_base) && - (o.addr < sl->flash_base + sl->flash_size)) { + if ((o.addr >= sl->flash_base) && (o.addr < sl->flash_base + sl->flash_size)) { if (o.format == FLASH_FORMAT_IHEX) { err = stlink_mwrite_flash(sl, mem, (uint32_t)size, o.addr); } else { @@ -120,8 +122,7 @@ int main(int ac, char** av) { printf("stlink_fwrite_flash() == -1\n"); goto on_error; } - } else if ((o.addr >= sl->sram_base) && - (o.addr < sl->sram_base + sl->sram_size)) { + } else if ((o.addr >= sl->sram_base) && (o.addr < sl->sram_base + sl->sram_size)) { if (o.format == FLASH_FORMAT_IHEX) { err = stlink_mwrite_sram(sl, mem, (uint32_t)size, o.addr); } else { @@ -132,8 +133,7 @@ int main(int ac, char** av) { printf("stlink_fwrite_sram() == -1\n"); goto on_error; } - } else if ((o.addr >= sl->option_base) && - (o.addr < sl->option_base + sl->option_size)) { + } else if ((o.addr >= sl->option_base) && (o.addr < sl->option_base + sl->option_size)) { err = stlink_fwrite_option_bytes(sl, o.filename, o.addr); if (err == -1) { @@ -170,11 +170,11 @@ int main(int ac, char** av) { goto on_error; } } else if (o.cmd == FLASH_CMD_ERASE) { - if (o.size > 0 && o.addr > 0) + if (o.size > 0 && o.addr > 0) { err = stlink_erase_flash_section(sl, o.addr, o.size, false); - else + } else { err = stlink_erase_flash_mass(sl); - + } if (err == -1) { printf("stlink_erase_flash_mass() == -1\n"); goto on_error; @@ -184,7 +184,9 @@ int main(int ac, char** av) { printf("Failed to reset device\n"); goto on_error; } - } else { // read + } else { + + // read if ((o.area == FLASH_MAIN_MEMORY) || (o.area == FLASH_SYSTEM_MEMORY)) { if ((o.size == 0) && (o.addr >= sl->flash_base) && (o.addr < sl->flash_base + sl->flash_size)) { o.size = sl->flash_size; diff --git a/src/st-trace/trace.c b/src/st-trace/trace.c index 9fcf8e358..83bfeac8c 100644 --- a/src/st-trace/trace.c +++ b/src/st-trace/trace.c @@ -171,8 +171,7 @@ bool parse_options(int argc, char **argv, st_settings_t *settings) { settings->serial_number = NULL; ugly_init(settings->logging_level); - while ((c = getopt_long(argc, argv, "hVv::c:ns:f", long_options, - &option_index)) != -1) { + while ((c = getopt_long(argc, argv, "hVv::c:ns:f", long_options, &option_index)) != -1) { switch (c) { case 'h': settings->show_help = true; diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index e36c150a6..7ff6c77a9 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -67,20 +67,22 @@ void process_chipfile(char *fname) { sscanf(buf, "%s %s", word, value); if (strcmp (word, "dev_type") == 0) { - // ts->dev_type = strdup (value); buf[strlen(buf) - 1] = 0; // chomp newline sscanf(buf, "%*s %n", &nc); ts->dev_type = strdup(buf + nc); } else if (strcmp(word, "ref_manual_id") == 0) { - // ts->ref_manual_id = strdup (value); buf[strlen(buf) - 1] = 0; // chomp newline sscanf(buf, "%*s %n", &nc); ts->ref_manual_id = strdup(buf + nc); } else if (strcmp(word, "chip_id") == 0) { + buf[strlen(buf) - 1] = 0; // chomp newline + sscanf(buf, "%*s %n", &nc); if (sscanf(value, "%i", &ts->chip_id) < 1) { fprintf(stderr, "Failed to parse chip-id\n"); } } else if (strcmp(word, "flash_type") == 0) { + buf[strlen(buf) - 1] = 0; // chomp newline + sscanf(buf, "%*s %n", &nc); if (strcmp(value, "F0_F1_F3") == 0) { ts->flash_type = STM32_FLASH_TYPE_F0_F1_F3; } else if (strcmp(value, "F1_XL") == 0) { @@ -105,37 +107,52 @@ void process_chipfile(char *fname) { ts->flash_type = STM32_FLASH_TYPE_WB_WL; } else { ts->flash_type = STM32_FLASH_TYPE_UNKNOWN; - fprintf(stderr, "Failed to parse flash type or unrecognized flash type\n"); } } else if (strcmp(word, "flash_size_reg") == 0) { + buf[strlen(buf) - 1] = 0; // chomp newline + sscanf(buf, "%*s %n", &nc); if (sscanf(value, "%i", &ts->flash_size_reg) < 1) { fprintf(stderr, "Failed to parse flash size reg\n"); } } else if (strcmp(word, "flash_pagesize") == 0) { + buf[strlen(buf) - 1] = 0; // chomp newline + sscanf(buf, "%*s %n", &nc); if (sscanf(value, "%i", &ts->flash_pagesize) < 1) { fprintf(stderr, "Failed to parse flash page size\n"); } } else if (strcmp(word, "sram_size") == 0) { + buf[strlen(buf) - 1] = 0; // chomp newline + sscanf(buf, "%*s %n", &nc); if (sscanf(value, "%i", &ts->sram_size) < 1) { fprintf(stderr, "Failed to parse SRAM size\n"); } } else if (strcmp(word, "bootrom_base") == 0) { + buf[strlen(buf) - 1] = 0; // chomp newline + sscanf(buf, "%*s %n", &nc); if (sscanf(value, "%i", &ts->bootrom_base) < 1) { fprintf(stderr, "Failed to parse BootROM base\n"); } } else if (strcmp(word, "bootrom_size") == 0) { + buf[strlen(buf) - 1] = 0; // chomp newline + sscanf(buf, "%*s %n", &nc); if (sscanf(value, "%i", &ts->bootrom_size) < 1) { fprintf(stderr, "Failed to parse BootROM size\n"); } } else if (strcmp(word, "option_base") == 0) { + buf[strlen(buf) - 1] = 0; // chomp newline + sscanf(buf, "%*s %n", &nc); if (sscanf(value, "%i", &ts->option_base) < 1) { fprintf(stderr, "Failed to parse option base\n"); } } else if (strcmp(word, "option_size") == 0) { + buf[strlen(buf) - 1] = 0; // chomp newline + sscanf(buf, "%*s %n", &nc); if (sscanf(value, "%i", &ts->option_size) < 1) { fprintf(stderr, "Failed to parse option size\n"); } } else if (strcmp(word, "flags") == 0) { + buf[strlen(buf) - 1] = 0; // chomp newline + sscanf(buf, "%*s %n", &nc); p = strtok (buf, " \t\n"); while ((p = strtok (NULL, " \t\n"))) { @@ -153,8 +170,7 @@ void process_chipfile(char *fname) { sscanf(value, "%x", &ts->flags); } else { - fprintf(stderr, "Unknown keyword in %s: %s\n", - fname, word); + fprintf(stderr, "Unknown keyword in %s: %s\n", fname, word); } } fclose(fp); @@ -164,6 +180,7 @@ void process_chipfile(char *fname) { #if defined(STLINK_HAVE_DIRENT_H) #include + void init_chipids(char *dir_to_scan) { DIR *d; size_t nl; // namelen @@ -198,6 +215,7 @@ void init_chipids(char *dir_to_scan) { #if defined(_WIN32) && !defined(STLINK_HAVE_DIRENT_H) #include #include + void init_chipids(char *dir_to_scan) { HANDLE hFind = INVALID_HANDLE_VALUE; WIN32_FIND_DATAA ffd; diff --git a/src/stlink-lib/common.c b/src/stlink-lib/common.c index d360b5d03..041b55f64 100644 --- a/src/stlink-lib/common.c +++ b/src/stlink-lib/common.c @@ -414,7 +414,7 @@ int stlink_status(stlink_t *sl) { } // 257 int stlink_version(stlink_t *sl) { - DLOG("*** looking up stlink version\n"); + DLOG("*** looking up stlink version ***\n"); if (sl->backend->version(sl)) { return (-1); From dfff59d39f8a3c7cc68e3281b72d237baa109751 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sat, 31 Dec 2022 14:49:39 +0100 Subject: [PATCH 410/503] Added support for STM32L4Q5 (Closes #1224) --- config/chips/L41x_L42x.chip | 2 +- config/chips/L43x_L44x.chip | 2 +- config/chips/L45x_L46x.chip | 2 +- config/chips/L47x_L48x.chip | 2 +- config/chips/L496x_L4A6x.chip | 2 +- config/chips/{L4Px.chip => L4Px_L4Qx.chip} | 10 +++---- config/chips/L4Rx.chip | 2 +- config/chips/L5x5.chip.txt | 15 ---------- inc/stm32.h | 2 +- src/stlink-lib/chipid.c | 2 +- src/stlink-lib/common.c | 2 +- src/stlink-lib/common_flash.c | 32 +++++++++++----------- src/stlink-lib/flashloader.c | 12 ++++---- src/stlink-lib/option_bytes.c | 2 +- 14 files changed, 37 insertions(+), 52 deletions(-) rename config/chips/{L4Px.chip => L4Px_L4Qx.chip} (62%) delete mode 100644 config/chips/L5x5.chip.txt diff --git a/config/chips/L41x_L42x.chip b/config/chips/L41x_L42x.chip index 11e545bb7..18730b4a2 100644 --- a/config/chips/L41x_L42x.chip +++ b/config/chips/L41x_L42x.chip @@ -3,7 +3,7 @@ dev_type STM32L41x_L42x ref_manual_id 0394 chip_id 0x464 // STM32_CHIPID_L41x_L42x -flash_type L4_L4P +flash_type L4 flash_size_reg 0x1fff75e0 flash_pagesize 0x800 // 2 KB sram_size 0xa000 // 40 KB diff --git a/config/chips/L43x_L44x.chip b/config/chips/L43x_L44x.chip index f0a959693..1e4b593ed 100644 --- a/config/chips/L43x_L44x.chip +++ b/config/chips/L43x_L44x.chip @@ -3,7 +3,7 @@ dev_type STM32L41x_L42x ref_manual_id 0392 chip_id 0x435 // STM32_CHIPID_L43x_L44x -flash_type L4_L4P +flash_type L4 flash_size_reg 0x1fff75e0 flash_pagesize 0x800 // 2 KB sram_size 0xc000 // 48 KB diff --git a/config/chips/L45x_L46x.chip b/config/chips/L45x_L46x.chip index 267122f87..cbe948c1f 100644 --- a/config/chips/L45x_L46x.chip +++ b/config/chips/L45x_L46x.chip @@ -3,7 +3,7 @@ dev_type STM32L45x_L46x ref_manual_id 0394 chip_id 0x462 // STM32_CHIPID_L45x_L46x -flash_type L4_L4P +flash_type L4 flash_size_reg 0x1fff75e0 flash_pagesize 0x800 // 2 KB sram_size 0x20000 // 128 KB diff --git a/config/chips/L47x_L48x.chip b/config/chips/L47x_L48x.chip index 421663e58..5475ee77b 100644 --- a/config/chips/L47x_L48x.chip +++ b/config/chips/L47x_L48x.chip @@ -3,7 +3,7 @@ dev_type STM32L47x_L48x ref_manual_id 0351 chip_id 0x415 // STM32_CHIPID_L4 -flash_type L4_L4P +flash_type L4 flash_size_reg 0x1fff75e0 flash_pagesize 0x800 // 2 KB sram_size 0x18000 // 96 KB diff --git a/config/chips/L496x_L4A6x.chip b/config/chips/L496x_L4A6x.chip index 6657d5484..24788c092 100644 --- a/config/chips/L496x_L4A6x.chip +++ b/config/chips/L496x_L4A6x.chip @@ -3,7 +3,7 @@ dev_type STM32L496x_L4A6x ref_manual_id 0351 chip_id 0x461 // STM32_CHIPID_L496x_L4A6x -flash_type L4_L4P +flash_type L4 flash_size_reg 0x1fff75e0 flash_pagesize 0x800 // 2 KB sram_size 0x50000 // 320 KB diff --git a/config/chips/L4Px.chip b/config/chips/L4Px_L4Qx.chip similarity index 62% rename from config/chips/L4Px.chip rename to config/chips/L4Px_L4Qx.chip index 39788eabe..881fd8188 100644 --- a/config/chips/L4Px.chip +++ b/config/chips/L4Px_L4Qx.chip @@ -1,14 +1,14 @@ -# Chip-ID file for STM32L4Px device +# Chip-ID file for STM32L4Px / STM32L4Qx device # -dev_type STM32L4Px +dev_type STM32L4Px_L4Qx ref_manual_id 0432 chip_id 0x471 // STM32_CHIPID_L4PX -flash_type L4_L4P +flash_type L4 flash_size_reg 0x1fff75e0 flash_pagesize 0x1000 // 4 KB sram_size 0xa0000 // 640 KB bootrom_base 0x1fff0000 bootrom_size 0x7000 // 28 KB -option_base 0x0 -option_size 0x0 +option_base 0x1ff00000 +option_size 0x4 // 4 B flags swo diff --git a/config/chips/L4Rx.chip b/config/chips/L4Rx.chip index 428a0c21e..80cd02d55 100644 --- a/config/chips/L4Rx.chip +++ b/config/chips/L4Rx.chip @@ -3,7 +3,7 @@ dev_type STM32L4Rx ref_manual_id 0432 chip_id 0x470 // STM32_CHIPID_L4RX -flash_type L4_L4P +flash_type L4 flash_size_reg 0x1fff75e0 flash_pagesize 0x1000 // 4 KB sram_size 0xa0000 // 640 KB diff --git a/config/chips/L5x5.chip.txt b/config/chips/L5x5.chip.txt deleted file mode 100644 index ce268148b..000000000 --- a/config/chips/L5x5.chip.txt +++ /dev/null @@ -1,15 +0,0 @@ -# Chip-ID file for STM32L5x2 device -# -dev_type STM32L5x2 -ref_manual_id 0438 -chip_id 0x0 // (temporary setting only!) -flash_type 0 // (temporary setting only!) -flash_size_reg 0x0bfa07a0 -flash_pagesize 0x2000 // 8 KB -sram_size 0x40000 // 256 KB -bootrom_base 0x0bf90000 -bootrom_size 0x8000 // 32 KB -option_base 0x0 -option_size 0x0 -flags none - diff --git a/inc/stm32.h b/inc/stm32.h index 2d533eca2..856d6e4bd 100644 --- a/inc/stm32.h +++ b/inc/stm32.h @@ -51,7 +51,7 @@ enum stm32_flash_type { STM32_FLASH_TYPE_G4 = 6, STM32_FLASH_TYPE_H7 = 7, STM32_FLASH_TYPE_L0_L1 = 8, - STM32_FLASH_TYPE_L4_L4P = 9, + STM32_FLASH_TYPE_L4 = 9, STM32_FLASH_TYPE_L5_U5 = 10, STM32_FLASH_TYPE_WB_WL = 11, }; diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index 7ff6c77a9..51a1200ad 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -100,7 +100,7 @@ void process_chipfile(char *fname) { } else if (strcmp(value, "L0_L1") == 0) { ts->flash_type = STM32_FLASH_TYPE_L0_L1; } else if (strcmp(value, "L4_L4P") == 0) { - ts->flash_type = STM32_FLASH_TYPE_L4_L4P; + ts->flash_type = STM32_FLASH_TYPE_L4; } else if (strcmp(value, "L5_U5") == 0) { ts->flash_type = STM32_FLASH_TYPE_L5_U5; } else if (strcmp(value, "WB_WL") == 0) { diff --git a/src/stlink-lib/common.c b/src/stlink-lib/common.c index 041b55f64..34a8ac573 100644 --- a/src/stlink-lib/common.c +++ b/src/stlink-lib/common.c @@ -984,7 +984,7 @@ static void stop_wdg_in_debug(stlink_t *sl) { break; case STM32_FLASH_TYPE_F2_F4: case STM32_FLASH_TYPE_F7: - case STM32_FLASH_TYPE_L4_L4P: + case STM32_FLASH_TYPE_L4: dbgmcu_cr = STM32F4_DBGMCU_APB1FZR1; set = (1 << STM32F4_DBGMCU_APB1FZR1_IWDG_STOP) | (1 << STM32F4_DBGMCU_APB1FZR1_WWDG_STOP); diff --git a/src/stlink-lib/common_flash.c b/src/stlink-lib/common_flash.c index b21929ddf..0ed4734ad 100644 --- a/src/stlink-lib/common_flash.c +++ b/src/stlink-lib/common_flash.c @@ -38,7 +38,7 @@ uint32_t read_flash_cr(stlink_t *sl, unsigned bank) { reg = FLASH_F4_CR; } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { reg = FLASH_F7_CR; - } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { reg = STM32L4_FLASH_CR; } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || sl->flash_type == STM32_FLASH_TYPE_G4) { @@ -79,7 +79,7 @@ void lock_flash(stlink_t *sl) { } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { cr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF; cr_lock_shift = STM32L0_FLASH_PELOCK; - } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { cr_reg = STM32L4_FLASH_CR; cr_lock_shift = STM32L4_FLASH_CR_LOCK; } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || @@ -124,7 +124,7 @@ static inline int write_flash_sr(stlink_t *sl, unsigned bank, uint32_t val) { sr_reg = FLASH_F4_SR; } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { sr_reg = FLASH_F7_SR; - } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { sr_reg = STM32L4_FLASH_SR; } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || sl->flash_type == STM32_FLASH_TYPE_G4) { @@ -163,7 +163,7 @@ void clear_flash_error(stlink_t *sl) { write_flash_sr(sl, BANK_1, STM32L0_FLASH_SR_ERROR_MASK); } break; - case STM32_FLASH_TYPE_L4_L4P: + case STM32_FLASH_TYPE_L4: write_flash_sr(sl, BANK_1, STM32L4_FLASH_SR_ERROR_MASK); break; case STM32_FLASH_TYPE_H7: @@ -192,7 +192,7 @@ uint32_t read_flash_sr(stlink_t *sl, unsigned bank) { sr_reg = FLASH_F4_SR; } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { sr_reg = FLASH_F7_SR; - } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { sr_reg = STM32L4_FLASH_SR; } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || sl->flash_type == STM32_FLASH_TYPE_G4) { @@ -222,7 +222,7 @@ unsigned int is_flash_busy(stlink_t *sl) { sr_busy_shift = FLASH_F4_SR_BSY; } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { sr_busy_shift = FLASH_F7_SR_BSY; - } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { sr_busy_shift = STM32L4_FLASH_SR_BSY; } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || sl->flash_type == STM32_FLASH_TYPE_G4) { @@ -297,7 +297,7 @@ int check_flash_error(stlink_t *sl) { WRPERR = (1 << STM32L0_FLASH_SR_WRPERR); PGAERR = (1 << STM32L0_FLASH_SR_PGAERR); break; - case STM32_FLASH_TYPE_L4_L4P: + case STM32_FLASH_TYPE_L4: res = read_flash_sr(sl, BANK_1) & STM32L4_FLASH_SR_ERROR_MASK; WRPERR = (1 << STM32L4_FLASH_SR_WRPERR); PROGERR = (1 << STM32L4_FLASH_SR_PROGERR); @@ -360,7 +360,7 @@ static inline unsigned int is_flash_locked(stlink_t *sl) { } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { cr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF; cr_lock_shift = STM32L0_FLASH_PELOCK; - } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { cr_reg = STM32L4_FLASH_CR; cr_lock_shift = STM32L4_FLASH_CR_LOCK; } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || @@ -404,7 +404,7 @@ static void unlock_flash(stlink_t *sl) { key_reg = get_stm32l0_flash_base(sl) + FLASH_PEKEYR_OFF; flash_key1 = FLASH_L0_PEKEY1; flash_key2 = FLASH_L0_PEKEY2; - } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { key_reg = STM32L4_FLASH_KEYR; } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || sl->flash_type == STM32_FLASH_TYPE_G4) { @@ -468,7 +468,7 @@ int lock_flash_option(stlink_t *sl) { optcr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF; optlock_shift = STM32L0_FLASH_OPTLOCK; break; - case STM32_FLASH_TYPE_L4_L4P: + case STM32_FLASH_TYPE_L4: optcr_reg = STM32L4_FLASH_CR; optlock_shift = STM32L4_FLASH_CR_OPTLOCK; break; @@ -541,7 +541,7 @@ static bool is_flash_option_locked(stlink_t *sl) { optcr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF; optlock_shift = STM32L0_FLASH_OPTLOCK; break; - case STM32_FLASH_TYPE_L4_L4P: + case STM32_FLASH_TYPE_L4: optcr_reg = STM32L4_FLASH_CR; optlock_shift = STM32L4_FLASH_CR_OPTLOCK; break; @@ -595,7 +595,7 @@ static int unlock_flash_option(stlink_t *sl) { optkey1 = FLASH_L0_OPTKEY1; optkey2 = FLASH_L0_OPTKEY2; break; - case STM32_FLASH_TYPE_L4_L4P: + case STM32_FLASH_TYPE_L4: optkey_reg = STM32L4_FLASH_OPTKEYR; break; case STM32_FLASH_TYPE_G0: @@ -672,7 +672,7 @@ void clear_flash_cr_pg(stlink_t *sl, unsigned bank) { cr_reg = FLASH_F4_CR; } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { cr_reg = FLASH_F7_CR; - } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { cr_reg = STM32L4_FLASH_CR; } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || sl->flash_type == STM32_FLASH_TYPE_G4) { @@ -796,7 +796,7 @@ static void set_flash_cr_strt(stlink_t *sl, unsigned bank) { } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { cr_reg = FLASH_F7_CR; cr_strt = 1 << FLASH_F7_CR_STRT; - } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { cr_reg = STM32L4_FLASH_CR; cr_strt = (1 << STM32L4_FLASH_CR_STRT); } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || @@ -830,7 +830,7 @@ static void set_flash_cr_mer(stlink_t *sl, bool v, unsigned bank) { cr_reg = FLASH_F7_CR; cr_mer = 1 << FLASH_CR_MER; cr_pg = 1 << FLASH_CR_PG; - } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { cr_reg = STM32L4_FLASH_CR; cr_mer = (1 << STM32L4_FLASH_CR_MER1) | (1 << STM32L4_FLASH_CR_MER2); cr_pg = (1 << STM32L4_FLASH_CR_PG); @@ -890,7 +890,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { if (sl->flash_type == STM32_FLASH_TYPE_F2_F4 || sl->flash_type == STM32_FLASH_TYPE_F7 || - sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { + sl->flash_type == STM32_FLASH_TYPE_L4) { // unlock if locked unlock_flash_if(sl); diff --git a/src/stlink-lib/flashloader.c b/src/stlink-lib/flashloader.c index abb140fdd..d9542ebbc 100644 --- a/src/stlink-lib/flashloader.c +++ b/src/stlink-lib/flashloader.c @@ -80,7 +80,7 @@ static void set_flash_cr_pg(stlink_t *sl, unsigned bank) { } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { cr_reg = FLASH_F7_CR; x |= 1 << FLASH_CR_PG; - } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { cr_reg = STM32L4_FLASH_CR; x &= ~STM32L4_FLASH_CR_OPBITS; x |= (1 << STM32L4_FLASH_CR_PG); @@ -123,7 +123,7 @@ static void set_dma_state(stlink_t *sl, flash_loader_t *fl, int bckpRstr) { rcc_dma_mask = STM32G0_RCC_DMAEN; break; case STM32_FLASH_TYPE_G4: - case STM32_FLASH_TYPE_L4_L4P: + case STM32_FLASH_TYPE_L4: rcc = STM32G4_RCC_AHB1ENR; rcc_dma_mask = STM32G4_RCC_DMAEN; break; @@ -170,7 +170,7 @@ int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { if ((sl->flash_type == STM32_FLASH_TYPE_F2_F4) || (sl->flash_type == STM32_FLASH_TYPE_F7) || - (sl->flash_type == STM32_FLASH_TYPE_L4_L4P)) { + (sl->flash_type == STM32_FLASH_TYPE_L4)) { ILOG("Starting Flash write for F2/F4/F7/L4\n"); // Flash loader initialisation @@ -194,7 +194,7 @@ int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { return (-1); } - if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { + if (sl->flash_type == STM32_FLASH_TYPE_L4) { // L4 does not have a byte-write mode if (voltage < 1710) { ELOG("Target voltage (%d mV) too low for flash writes!\n", voltage); @@ -304,7 +304,7 @@ int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, size_t off; if ((sl->flash_type == STM32_FLASH_TYPE_F2_F4) || (sl->flash_type == STM32_FLASH_TYPE_F7) || - (sl->flash_type == STM32_FLASH_TYPE_L4_L4P)) { + (sl->flash_type == STM32_FLASH_TYPE_L4)) { size_t buf_size = (sl->sram_size > 0x8000) ? 0x8000 : 0x4000; for (off = 0; off < len;) { size_t size = len - off > buf_size ? buf_size : len - off; @@ -451,7 +451,7 @@ int stlink_flashloader_stop(stlink_t *sl, flash_loader_t *fl) { (sl->flash_type == STM32_FLASH_TYPE_F1_XL) || (sl->flash_type == STM32_FLASH_TYPE_F2_F4) || (sl->flash_type == STM32_FLASH_TYPE_F7) || - (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) || + (sl->flash_type == STM32_FLASH_TYPE_L4) || (sl->flash_type == STM32_FLASH_TYPE_WB_WL) || (sl->flash_type == STM32_FLASH_TYPE_G0) || (sl->flash_type == STM32_FLASH_TYPE_G4) || diff --git a/src/stlink-lib/option_bytes.c b/src/stlink-lib/option_bytes.c index 44cd3930b..3d332f49d 100644 --- a/src/stlink-lib/option_bytes.c +++ b/src/stlink-lib/option_bytes.c @@ -795,7 +795,7 @@ int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t *base, ui case STM32_FLASH_TYPE_L0_L1: ret = stlink_write_option_bytes_l0(sl, addr, base, len); break; - case STM32_FLASH_TYPE_L4_L4P: + case STM32_FLASH_TYPE_L4: ret = stlink_write_option_bytes_l4(sl, addr, base, len); break; case STM32_FLASH_TYPE_G0: From f025d756b7781cfb15c0aab15e47deddf5c17f7d Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 1 Jan 2023 13:20:02 +0100 Subject: [PATCH 411/503] Minor corrections regarding os support --- .github/ISSUE_TEMPLATE/feature-request.md | 2 +- CMakeLists.txt | 2 +- doc/compiling.md | 2 +- src/stlink-lib/libusb_settings.h | 3 +-- 4 files changed, 4 insertions(+), 5 deletions(-) diff --git a/.github/ISSUE_TEMPLATE/feature-request.md b/.github/ISSUE_TEMPLATE/feature-request.md index d57dbefed..b16cbf92b 100644 --- a/.github/ISSUE_TEMPLATE/feature-request.md +++ b/.github/ISSUE_TEMPLATE/feature-request.md @@ -20,7 +20,7 @@ labels: code/feature-request In order to allow developers to isolate and target your respective issue, please take some time to select the check boxes below and fill out each of the following items appropriate to your specific request. - [ ] Programmer/board type: [enter here] (e.g STLINK /V1, /V2, /V2-onboard, /V2-clone, /V3) -- [ ] Operating system an version: [enter here] (e.g Linux, macOS, Windows) +- [ ] Operating system an version: [enter here] (e.g Linux, Windows) - [ ] **stlink tools version** and/or git commit hash: [enter here] (e.g v1.6.1/git-d0416149) - [ ] stlink commandline tool name: [enter here] (e.g `st-info`, `st-flash`, `st-trace`, `st-util`) - [ ] Target chip (and board, if applicable): [enter here] (e.g STM32F103C8T6 (NUCLEO-F103RB)) diff --git a/CMakeLists.txt b/CMakeLists.txt index f7bbe6f12..b25291992 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -74,7 +74,7 @@ include(${CMAKE_MODULE_PATH}/get_version.cmake) # Determine project version include(GNUInstallDirs) # Define GNU standard installation directories -# Define install directory /usr/local/share [not /usr/share on MacOS] +# Define install directory /usr/local/share cmake_host_system_information(RESULT OS_NAME QUERY OS_NAME) message(STATUS "Checking for OS_NAME: ${OS_NAME}") diff --git a/doc/compiling.md b/doc/compiling.md index 5f6852a93..eec46bb3d 100644 --- a/doc/compiling.md +++ b/doc/compiling.md @@ -1,6 +1,6 @@ # Compiling from sources -## Microsoft Windows (10, 8.1) +## Microsoft Windows (10, 11) ### Common Requirements diff --git a/src/stlink-lib/libusb_settings.h b/src/stlink-lib/libusb_settings.h index 2a595238a..ee690e0b1 100644 --- a/src/stlink-lib/libusb_settings.h +++ b/src/stlink-lib/libusb_settings.h @@ -19,6 +19,7 @@ * v1.0.23 | 0x01000107 * v1.0.24 | 0x01000108 * v1.0.25 | 0x01000109 + * v1.0.26 | 0x01000110 */ #if defined (__FreeBSD__) @@ -35,8 +36,6 @@ #define MINIMAL_API_VERSION 0x01000105 // v1.0.21 #elif defined (__linux__) #define MINIMAL_API_VERSION 0x01000105 // v1.0.21 -#elif defined (__APPLE__) - #define MINIMAL_API_VERSION 0x01000109 // v1.0.25 #elif defined (_WIN32) #define MINIMAL_API_VERSION 0x01000109 // v1.0.25 #endif From b60a03540402bb71a318c6303ad4199ef5c25983 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 1 Jan 2023 13:32:14 +0100 Subject: [PATCH 412/503] Initial support for STM32 L5 & U5 devices (References: #1005 #1096 #1247) --- config/chips/L5x5.chip | 14 + config/chips/{U5x5.chip.txt => U5x5.chip} | 9 +- inc/stm32.h | 8 + inc/stm32flash.h | 39 ++- src/st-flash/flash.c | 1 + src/stlink-lib/common.c | 198 +++++++------- src/stlink-lib/common_flash.c | 300 ++++++++++++++-------- src/stlink-lib/flashloader.c | 29 ++- src/stlink-lib/option_bytes.c | 33 +-- 9 files changed, 392 insertions(+), 239 deletions(-) create mode 100644 config/chips/L5x5.chip rename config/chips/{U5x5.chip.txt => U5x5.chip} (52%) diff --git a/config/chips/L5x5.chip b/config/chips/L5x5.chip new file mode 100644 index 000000000..0f205a62b --- /dev/null +++ b/config/chips/L5x5.chip @@ -0,0 +1,14 @@ +# Chip-ID file for STM32L5x2xx device +# +dev_type STM32L5x2xx +ref_manual_id 0438 +chip_id 0x472 // STM32_CHIPID_L5x2xx +flash_type L5_U5 +flash_size_reg 0x0bfa05e0 +flash_pagesize 0x1000 // 4 KB +sram_size 0x40000 // 256 KB +bootrom_base 0x0bf90000 +bootrom_size 0x8000 // 32 KB +option_base 0x0 +option_size 0x0 +flags dualbank diff --git a/config/chips/U5x5.chip.txt b/config/chips/U5x5.chip similarity index 52% rename from config/chips/U5x5.chip.txt rename to config/chips/U5x5.chip index 177359cc3..be19d04af 100644 --- a/config/chips/U5x5.chip.txt +++ b/config/chips/U5x5.chip @@ -2,14 +2,13 @@ # dev_type STM32U5x5 ref_manual_id 0456 -chip_id 0x0 // (temporary setting only!) -flash_type 0 // (temporary setting only!) +chip_id 0x482 // STM32_CHIPID_U5x5 +flash_type L5_U5 flash_size_reg 0x0bfa07a0 -flash_pagesize 0x2000 // 8 KB +flash_pagesize 0x200000 // 2048 KB sram_size 0xc4800 // 786 KB bootrom_base 0x0bf90000 -bootrom_size 0x8000 // 32 KB +bootrom_size 0x10000 // 64 KB option_base 0x0 option_size 0x0 flags none - diff --git a/inc/stm32.h b/inc/stm32.h index 856d6e4bd..8557c9ce7 100644 --- a/inc/stm32.h +++ b/inc/stm32.h @@ -117,8 +117,10 @@ enum stm32_chipids { STM32_CHIPID_G4_CAT3 = 0x469, STM32_CHIPID_L4Rx = 0x470, /* RM0432, p.2247, found on the STM32L4R9I-DISCO board */ STM32_CHIPID_L4PX = 0x471, /* RM0432, p.2247 */ + STM32_CHIPID_L5x2xx = 0x472, /* RM0438, p.2157 */ STM32_CHIPID_G4_CAT4 = 0x479, STM32_CHIPID_H7Ax = 0x480, /* RM0455, p.2863 */ + STM32_CHIPID_U5x5 = 0x482, /* RM0456, p.2991 */ STM32_CHIPID_H72x = 0x483, /* RM0468, p.3199 */ STM32_CHIPID_WB55 = 0x495, STM32_CHIPID_WLE = 0x497, @@ -196,10 +198,16 @@ enum stm32_chipids { #define STM32L1_RCC_AHBENR 0x4002381C #define STM32L1_RCC_DMAEN 0x30000000 // DMA2EN | DMA1EN +#define STM32L5_RCC_AHB1ENR 0x40021048 // RM0438, p. 91,377 +#define STM32L5_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN // RM0438, p. 378 + #define STM32H7_RCC_AHB1ENR 0x58024538 #define STM32H7_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN #define STM32WB_RCC_AHB1ENR 0x58000048 #define STM32WB_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN +#define STM32L5_PWR_CR1 0x40007000 // RM0438, p. 93,324 +#define STM32L5_PWR_CR1_VOS 8 + #endif // STM32_H diff --git a/inc/stm32flash.h b/inc/stm32flash.h index 5e7ad2e4a..07f824837 100644 --- a/inc/stm32flash.h +++ b/inc/stm32flash.h @@ -72,7 +72,7 @@ #define FLASH_L1_FPRG 10 #define FLASH_L1_PROG 3 -// Flash registers common to STM32G0 and STM32G4 series. +// Flash registers common to STM32G0 and STM32G4 series (RM0440, p. 146) #define STM32Gx_FLASH_REGS_ADDR ((uint32_t)0x40022000) #define STM32Gx_FLASH_ACR (STM32Gx_FLASH_REGS_ADDR + 0x00) #define STM32Gx_FLASH_KEYR (STM32Gx_FLASH_REGS_ADDR + 0x08) @@ -207,6 +207,43 @@ #define STM32L4_FLASH_OPTR_DUALBANK 21 +// Flash registers common to STM32L5 series (RM0438, p. 241) +#define STM32L5_FLASH_REGS_ADDR ((uint32_t)0x40022000) +#define STM32L5_FLASH_ACR (STM32L5_FLASH_REGS_ADDR + 0x00) +#define STM32L5_FLASH_NSKEYR (STM32L5_FLASH_REGS_ADDR + 0x08) +#define STM32L5_FLASH_OPTKEYR (STM32L5_FLASH_REGS_ADDR + 0x10) +#define STM32L5_FLASH_NSSR (STM32L5_FLASH_REGS_ADDR + 0x20) +#define STM32L5_FLASH_NSCR (STM32L5_FLASH_REGS_ADDR + 0x28) +#define STM32L5_FLASH_ECCR (STM32L5_FLASH_REGS_ADDR + 0x30) +#define STM32L5_FLASH_OPTR (STM32L5_FLASH_REGS_ADDR + 0x40) + +// FLASH_NSCR (RM0438, p. 242) +#define STM32L5_FLASH_NSCR_NSPG 0 /* Program */ +#define STM32L5_FLASH_NSCR_NSPER 1 /* Page erase */ +#define STM32L5_FLASH_NSCR_NSMER1 2 /* Bank 1 erase */ +#define STM32L5_FLASH_NSCR_NSPNB 3 /* Page number (7 bits) */ +#define STM32L5_FLASH_NSCR_NSBKER 11 /* Bank select for page erase */ +#define STM32L5_FLASH_NSCR_NSMER2 15 /* Bank 2 erase */ +#define STM32L5_FLASH_NSCR_NSSTRT 16 /* Start command */ +#define STM32L5_FLASH_NSCR_NSOPTSTRT 17 /* Start writing option bytes */ +#define STM32L5_FLASH_NSCR_NSEOPIE 24 +#define STM32L5_FLASH_NSCR_NSERRIE 25 +#define STM32L5_FLASH_NSCR_OBL_LAUNCH 27 /* Option bytes reload */ +#define STM32L5_FLASH_NSCR_OPTLOCK 30 /* Lock option bytes */ +#define STM32L5_FLASH_NSCR_NSLOCK 31 /* Lock control register */ + +// FLASH_NSSR (RM0438, p. 241) +#define STM32L5_FLASH_NSSR_NSEOP 0 /* End of Operation */ +#define STM32L5_FLASH_NSSR_NSOPERR 1 +#define STM32L5_FLASH_NSSR_NSPROGERR 3 +#define STM32L5_FLASH_NSSR_NSWRPERR 4 +#define STM32L5_FLASH_NSSR_NSPGAERR 5 +#define STM32L5_FLASH_NSSR_NSSIZERR 6 +#define STM32L5_FLASH_NSSR_NSPGSERR 7 +#define STM32L5_FLASH_NSSR_OPTWERR 12 +#define STM32L5_FLASH_NSSR_BSY 16 /* Busy */ +#define STM32L5_FLASH_NSSR_ERROR_MASK (0x20fa) + // STM32L0x flash register base and offsets RM0090 - DM00031020.pdf #define STM32L0_FLASH_REGS_ADDR ((uint32_t)0x40022000) diff --git a/src/st-flash/flash.c b/src/st-flash/flash.c index 4b8e37fef..cef0b639f 100644 --- a/src/st-flash/flash.c +++ b/src/st-flash/flash.c @@ -254,6 +254,7 @@ int main(int ac, char** av) { if (o.reset) { stlink_reset(sl, RESET_AUTO); + stlink_run(sl, RUN_NORMAL); } err = 0; // success diff --git a/src/stlink-lib/common.c b/src/stlink-lib/common.c index 34a8ac573..fe5574706 100644 --- a/src/stlink-lib/common.c +++ b/src/stlink-lib/common.c @@ -62,6 +62,7 @@ void stlink_close(stlink_t *sl) { sl->backend->close(sl); free(sl); } + // 250 int stlink_exit_debug_mode(stlink_t *sl) { DLOG("*** stlink_exit_debug_mode ***\n"); @@ -74,11 +75,13 @@ int stlink_exit_debug_mode(stlink_t *sl) { return (sl->backend->exit_debug_mode(sl)); } + //248 int stlink_enter_swd_mode(stlink_t *sl) { DLOG("*** stlink_enter_swd_mode ***\n"); return (sl->backend->enter_swd_mode(sl)); } + // 271 // Force the core into the debug mode -> halted state. int stlink_force_debug(stlink_t *sl) { @@ -91,11 +94,13 @@ int stlink_force_debug(stlink_t *sl) { stop_wdg_in_debug(sl); return (0); } + // 251 int stlink_exit_dfu_mode(stlink_t *sl) { DLOG("*** stlink_exit_dfu_mode ***\n"); return (sl->backend->exit_dfu_mode(sl)); } + // 253 int stlink_core_id(stlink_t *sl) { int ret; @@ -115,6 +120,7 @@ int stlink_core_id(stlink_t *sl) { DLOG("core_id = 0x%08x\n", sl->core_id); return (ret); } + // 287 // stlink_chip_id() is called by stlink_load_device_params() // do not call this procedure directly. @@ -132,7 +138,6 @@ int stlink_chip_id(stlink_t *sl, uint32_t *chip_id) { /* * the chip_id register in the reference manual have * DBGMCU_IDCODE / DBG_IDCODE name - * */ if ((sl->core_id == STM32_CORE_ID_M7F_H7_SWD || sl->core_id == STM32_CORE_ID_M7F_H7_JTAG) && @@ -178,6 +183,7 @@ int stlink_chip_id(stlink_t *sl, uint32_t *chip_id) { return (ret); } + // 288 /** * Cortex M tech ref manual, CPUID register description @@ -201,6 +207,7 @@ int stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid) { cpuid->revision = raw & 0xf; return (0); } + // 303 /** * Reads and decodes the flash parameters, as dynamically as possible @@ -300,6 +307,7 @@ int stlink_load_device_params(stlink_t *sl) { return (0); } + // 254 int stlink_reset(stlink_t *sl, enum reset_type type) { uint32_t dhcsr; @@ -361,6 +369,81 @@ int stlink_reset(stlink_t *sl, enum reset_type type) { return (0); } + +int stlink_soft_reset(stlink_t *sl, int halt_on_reset) { + int ret; + unsigned timeout; + uint32_t dhcsr, dfsr; + + DLOG("*** stlink_soft_reset %s***\n", halt_on_reset ? "(halt) " : ""); + + // halt core and enable debugging (if not already done) + // C_DEBUGEN is required to Halt on reset (DDI0337E, p. 10-6) + stlink_write_debug32(sl, STLINK_REG_DHCSR, + STLINK_REG_DHCSR_DBGKEY | STLINK_REG_DHCSR_C_HALT | + STLINK_REG_DHCSR_C_DEBUGEN); + + // enable Halt on reset by set VC_CORERESET and TRCENA (DDI0337E, p. 10-10) + if (halt_on_reset) { + stlink_write_debug32( + sl, STLINK_REG_CM3_DEMCR, + STLINK_REG_CM3_DEMCR_TRCENA | STLINK_REG_CM3_DEMCR_VC_HARDERR | + STLINK_REG_CM3_DEMCR_VC_BUSERR | STLINK_REG_CM3_DEMCR_VC_CORERESET); + + // clear VCATCH in the DFSR register + stlink_write_debug32(sl, STLINK_REG_DFSR, STLINK_REG_DFSR_VCATCH); + } else { + stlink_write_debug32(sl, STLINK_REG_CM3_DEMCR, + STLINK_REG_CM3_DEMCR_TRCENA | + STLINK_REG_CM3_DEMCR_VC_HARDERR | + STLINK_REG_CM3_DEMCR_VC_BUSERR); + } + + // clear S_RESET_ST in the DHCSR register + stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); + + // soft reset (core reset) by SYSRESETREQ (DDI0337E, p. 8-23) + ret = stlink_write_debug32(sl, STLINK_REG_AIRCR, + STLINK_REG_AIRCR_VECTKEY | + STLINK_REG_AIRCR_SYSRESETREQ); + if (ret) { + ELOG("Soft reset failed: error write to AIRCR\n"); + return (ret); + } + + // waiting for a reset within 500ms + // DDI0337E, p. 10-4, Debug Halting Control and Status Register + timeout = time_ms() + 500; + while (time_ms() < timeout) { + // DDI0337E, p. 10-4, Debug Halting Control and Status Register + dhcsr = STLINK_REG_DHCSR_S_RESET_ST; + stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); + if ((dhcsr & STLINK_REG_DHCSR_S_RESET_ST) == 0) { + if (halt_on_reset) { + // waiting halt by the SYSRESETREQ exception + // DDI0403E, p. C1-699, Debug Fault Status Register + dfsr = 0; + stlink_read_debug32(sl, STLINK_REG_DFSR, &dfsr); + if ((dfsr & STLINK_REG_DFSR_VCATCH) == 0) { + continue; + } + } + timeout = 0; + break; + } + } + + // reset DFSR register. DFSR is power-on reset only (DDI0337H, p. 7-5) + stlink_write_debug32(sl, STLINK_REG_DFSR, STLINK_REG_DFSR_CLEAR); + + if (timeout) { + ELOG("Soft reset failed: timeout\n"); + return (-1); + } + + return (0); +} + // 255 int stlink_run(stlink_t *sl, enum run_type type) { struct stlink_reg rr; @@ -377,11 +460,13 @@ int stlink_run(stlink_t *sl, enum run_type type) { return (sl->backend->run(sl, type)); } + // 273 int stlink_set_swdclk(stlink_t *sl, int freq_khz) { DLOG("*** set_swdclk ***\n"); return (sl->backend->set_swdclk(sl, freq_khz)); } + // 293 // this function is called by stlink_status() // do not call stlink_core_stat() directly, always use stlink_status() @@ -403,6 +488,7 @@ void stlink_core_stat(stlink_t *sl) { DLOG(" core status: unknown\n"); } } + // 256 int stlink_status(stlink_t *sl) { int ret; @@ -412,6 +498,7 @@ int stlink_status(stlink_t *sl) { stlink_core_stat(sl); return (ret); } + // 257 int stlink_version(stlink_t *sl) { DLOG("*** looking up stlink version ***\n"); @@ -435,6 +522,7 @@ int stlink_version(stlink_t *sl) { return (0); } + // 272 int stlink_target_voltage(stlink_t *sl) { int voltage = -1; @@ -454,16 +542,19 @@ int stlink_target_voltage(stlink_t *sl) { return (voltage); } + // 299 bool stlink_is_core_halted(stlink_t *sl) { stlink_status(sl); return (sl->core_stat == TARGET_HALTED); } + // 269 int stlink_step(stlink_t *sl) { DLOG("*** stlink_step ***\n"); return (sl->backend->step(sl)); } + // 270 int stlink_current_mode(stlink_t *sl) { int mode = sl->backend->current_mode(sl); @@ -483,20 +574,24 @@ int stlink_current_mode(stlink_t *sl) { DLOG("stlink mode: unknown!\n"); return (STLINK_DEV_UNKNOWN_MODE); } + // 274 int stlink_trace_enable(stlink_t *sl, uint32_t frequency) { DLOG("*** stlink_trace_enable ***\n"); return (sl->backend->trace_enable(sl, frequency)); } + // 275 int stlink_trace_disable(stlink_t *sl) { DLOG("*** stlink_trace_disable ***\n"); return (sl->backend->trace_disable(sl)); } + // 276 int stlink_trace_read(stlink_t *sl, uint8_t *buf, size_t size) { return (sl->backend->trace_read(sl, buf, size)); } + // 294 void stlink_print_data(stlink_t *sl) { if (sl->q_len <= 0 || sl->verbose < UDEBUG) { @@ -523,9 +618,9 @@ void stlink_print_data(stlink_t *sl) { // DLOG("\n\n"); fprintf(stderr, "\n"); } + // 283 -int stlink_mwrite_sram(stlink_t *sl, uint8_t *data, uint32_t length, - stm32_addr_t addr) { +int stlink_mwrite_sram(stlink_t *sl, uint8_t *data, uint32_t length, stm32_addr_t addr) { // write the file in sram at addr int error = -1; @@ -581,6 +676,7 @@ int stlink_mwrite_sram(stlink_t *sl, uint8_t *data, uint32_t length, on_error: return (error); } + //284 int stlink_fwrite_sram(stlink_t *sl, const char *path, stm32_addr_t addr) { // write the file in sram at addr @@ -655,9 +751,9 @@ int stlink_fwrite_sram(stlink_t *sl, const char *path, stm32_addr_t addr) { unmap_file(&mf); return (error); } + // 302 -int stlink_fread(stlink_t *sl, const char *path, bool is_ihex, - stm32_addr_t addr, size_t size) { +int stlink_fread(stlink_t *sl, const char *path, bool is_ihex, stm32_addr_t addr, size_t size) { // read size bytes from addr to file ILOG("read from address %#010x size %u\n", addr, (unsigned)size); @@ -689,9 +785,9 @@ int stlink_fread(stlink_t *sl, const char *path, bool is_ihex, close(fd); return (error); } + // 300 -int write_buffer_to_sram(stlink_t *sl, flash_loader_t *fl, const uint8_t *buf, - size_t size) { +int write_buffer_to_sram(stlink_t *sl, flash_loader_t *fl, const uint8_t *buf, size_t size) { // write the buffer right after the loader int ret = 0; size_t chunk = size & ~0x3; @@ -709,6 +805,7 @@ int write_buffer_to_sram(stlink_t *sl, flash_loader_t *fl, const uint8_t *buf, return (ret); } + // 291 uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr) { if ((sl->chip_id == STM32_CHIPID_F2) || @@ -749,6 +846,7 @@ uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr) { return ((uint32_t)sl->flash_pgsz); } + // 279 int stlink_parse_ihex(const char *path, uint8_t erased_pattern, uint8_t **mem, size_t *size, uint32_t *begin) { @@ -910,6 +1008,7 @@ int stlink_parse_ihex(const char *path, uint8_t erased_pattern, uint8_t **mem, return (res); } + // 280 uint8_t stlink_get_erased_pattern(stlink_t *sl) { if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { @@ -1024,79 +1123,6 @@ int stlink_jtag_reset(stlink_t *sl, int value) { return (sl->backend->jtag_reset(sl, value)); } -int stlink_soft_reset(stlink_t *sl, int halt_on_reset) { - int ret; - unsigned timeout; - uint32_t dhcsr, dfsr; - - DLOG("*** stlink_soft_reset %s***\n", halt_on_reset ? "(halt) " : ""); - - // halt core and enable debugging (if not already done) - // C_DEBUGEN is required to Halt on reset (DDI0337E, p. 10-6) - stlink_write_debug32(sl, STLINK_REG_DHCSR, - STLINK_REG_DHCSR_DBGKEY | STLINK_REG_DHCSR_C_HALT | - STLINK_REG_DHCSR_C_DEBUGEN); - - // enable Halt on reset by set VC_CORERESET and TRCENA (DDI0337E, p. 10-10) - if (halt_on_reset) { - stlink_write_debug32( - sl, STLINK_REG_CM3_DEMCR, - STLINK_REG_CM3_DEMCR_TRCENA | STLINK_REG_CM3_DEMCR_VC_HARDERR | - STLINK_REG_CM3_DEMCR_VC_BUSERR | STLINK_REG_CM3_DEMCR_VC_CORERESET); - - // clear VCATCH in the DFSR register - stlink_write_debug32(sl, STLINK_REG_DFSR, STLINK_REG_DFSR_VCATCH); - } else { - stlink_write_debug32(sl, STLINK_REG_CM3_DEMCR, - STLINK_REG_CM3_DEMCR_TRCENA | - STLINK_REG_CM3_DEMCR_VC_HARDERR | - STLINK_REG_CM3_DEMCR_VC_BUSERR); - } - - // clear S_RESET_ST in the DHCSR register - stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); - - // soft reset (core reset) by SYSRESETREQ (DDI0337E, p. 8-23) - ret = stlink_write_debug32(sl, STLINK_REG_AIRCR, - STLINK_REG_AIRCR_VECTKEY | - STLINK_REG_AIRCR_SYSRESETREQ); - if (ret) { - ELOG("Soft reset failed: error write to AIRCR\n"); - return (ret); - } - - // waiting for a reset within 500ms - // DDI0337E, p. 10-4, Debug Halting Control and Status Register - timeout = time_ms() + 500; - while (time_ms() < timeout) { - // DDI0337E, p. 10-4, Debug Halting Control and Status Register - dhcsr = STLINK_REG_DHCSR_S_RESET_ST; - stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); - if ((dhcsr & STLINK_REG_DHCSR_S_RESET_ST) == 0) { - if (halt_on_reset) { - // waiting halt by the SYSRESETREQ exception - // DDI0403E, p. C1-699, Debug Fault Status Register - dfsr = 0; - stlink_read_debug32(sl, STLINK_REG_DFSR, &dfsr); - if ((dfsr & STLINK_REG_DFSR_VCATCH) == 0) { - continue; - } - } - timeout = 0; - break; - } - } - - // reset DFSR register. DFSR is power-on reset only (DDI0337H, p. 7-5) - stlink_write_debug32(sl, STLINK_REG_DFSR, STLINK_REG_DFSR_CLEAR); - - if (timeout) { - ELOG("Soft reset failed: timeout\n"); - return (-1); - } - - return (0); -} /** * Decode the version bits, originally from -sg, verified with usb * @param sl stlink context, assumed to contain valid data in the buffer @@ -1283,8 +1309,7 @@ static int stlink_read(stlink_t *sl, stm32_addr_t addr, size_t size, } static bool stlink_fread_worker(void *arg, uint8_t *block, ssize_t len) { - struct stlink_fread_worker_arg *the_arg = - (struct stlink_fread_worker_arg *)arg; + struct stlink_fread_worker_arg *the_arg = (struct stlink_fread_worker_arg *)arg; if (write(the_arg->fd, block, len) != len) { fprintf(stderr, "write() != aligned_size\n"); @@ -1315,8 +1340,7 @@ static uint8_t stlink_parse_hex(const char *hex) { return ((d[0] << 4) | (d[1])); } -static bool -stlink_fread_ihex_newsegment(struct stlink_fread_ihex_worker_arg *the_arg) { +static bool stlink_fread_ihex_newsegment(struct stlink_fread_ihex_worker_arg *the_arg) { uint32_t addr = the_arg->addr; uint8_t sum = 2 + 4 + (uint8_t)((addr & 0xFF000000) >> 24) + (uint8_t)((addr & 0x00FF0000) >> 16); @@ -1330,8 +1354,7 @@ stlink_fread_ihex_newsegment(struct stlink_fread_ihex_worker_arg *the_arg) { return (true); } -static bool -stlink_fread_ihex_writeline(struct stlink_fread_ihex_worker_arg *the_arg) { +static bool stlink_fread_ihex_writeline(struct stlink_fread_ihex_worker_arg *the_arg) { uint8_t count = the_arg->buf_pos; if (count == 0) { @@ -1399,8 +1422,7 @@ static bool stlink_fread_ihex_worker(void *arg, uint8_t *block, ssize_t len) { return (true); } -static bool -stlink_fread_ihex_finalize(struct stlink_fread_ihex_worker_arg *the_arg) { +static bool stlink_fread_ihex_finalize(struct stlink_fread_ihex_worker_arg *the_arg) { if (!stlink_fread_ihex_writeline(the_arg)) { return (false); } diff --git a/src/stlink-lib/common_flash.c b/src/stlink-lib/common_flash.c index 0ed4734ad..5b8075ea7 100644 --- a/src/stlink-lib/common_flash.c +++ b/src/stlink-lib/common_flash.c @@ -38,15 +38,17 @@ uint32_t read_flash_cr(stlink_t *sl, unsigned bank) { reg = FLASH_F4_CR; } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { reg = FLASH_F7_CR; - } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { - reg = STM32L4_FLASH_CR; } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || sl->flash_type == STM32_FLASH_TYPE_G4) { reg = STM32Gx_FLASH_CR; - } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { - reg = STM32WB_FLASH_CR; } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; + } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { + reg = STM32L4_FLASH_CR; + } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5) { + reg = STM32L5_FLASH_NSCR; + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { + reg = STM32WB_FLASH_CR; } else { reg = (bank == BANK_1) ? FLASH_CR : FLASH_CR2; } @@ -60,7 +62,7 @@ uint32_t read_flash_cr(stlink_t *sl, unsigned bank) { } void lock_flash(stlink_t *sl) { - uint32_t cr_lock_shift, cr_reg, n, cr2_reg = 0; + uint32_t cr_lock_shift = 0, cr_reg = 0, n = 0, cr2_reg = 0; uint32_t cr_mask = 0xffffffffu; if (sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) { @@ -76,21 +78,24 @@ void lock_flash(stlink_t *sl) { } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { cr_reg = FLASH_F7_CR; cr_lock_shift = FLASH_F7_CR_LOCK; + } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4) { + cr_reg = STM32Gx_FLASH_CR; + cr_lock_shift = STM32Gx_FLASH_CR_LOCK; + } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { + cr_reg = FLASH_H7_CR1; } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { cr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF; cr_lock_shift = STM32L0_FLASH_PELOCK; } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { cr_reg = STM32L4_FLASH_CR; cr_lock_shift = STM32L4_FLASH_CR_LOCK; - } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || - sl->flash_type == STM32_FLASH_TYPE_G4) { - cr_reg = STM32Gx_FLASH_CR; - cr_lock_shift = STM32Gx_FLASH_CR_LOCK; + } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5) { + cr_reg = STM32L5_FLASH_NSCR; + cr_lock_shift = STM32L5_FLASH_NSCR_NSLOCK; } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { cr_reg = STM32WB_FLASH_CR; cr_lock_shift = STM32WB_FLASH_CR_LOCK; - } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { - cr_reg = FLASH_H7_CR1; if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { cr2_reg = FLASH_H7_CR2; } @@ -118,21 +123,23 @@ static inline int write_flash_sr(stlink_t *sl, unsigned bank, uint32_t val) { if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || (sl->flash_type == STM32_FLASH_TYPE_F1_XL)) { sr_reg = (bank == BANK_1) ? FLASH_SR : FLASH_SR2; - } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { - sr_reg = get_stm32l0_flash_base(sl) + FLASH_SR_OFF; } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { sr_reg = FLASH_F4_SR; } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { sr_reg = FLASH_F7_SR; - } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { - sr_reg = STM32L4_FLASH_SR; } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || sl->flash_type == STM32_FLASH_TYPE_G4) { sr_reg = STM32Gx_FLASH_SR; - } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { - sr_reg = STM32WB_FLASH_SR; } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { sr_reg = (bank == BANK_1) ? FLASH_H7_SR1 : FLASH_H7_SR2; + } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { + sr_reg = get_stm32l0_flash_base(sl) + FLASH_SR_OFF; + } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { + sr_reg = STM32L4_FLASH_SR; + } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5) { + sr_reg = STM32L5_FLASH_NSSR; + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { + sr_reg = STM32WB_FLASH_SR; } else { ELOG("method 'write_flash_sr' is unsupported\n"); return (-1); @@ -156,6 +163,12 @@ void clear_flash_error(stlink_t *sl) { case STM32_FLASH_TYPE_G4: write_flash_sr(sl, BANK_1, STM32Gx_FLASH_SR_ERROR_MASK); break; + case STM32_FLASH_TYPE_H7: + write_flash_sr(sl, BANK_1, FLASH_H7_SR_ERROR_MASK); + if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { + write_flash_sr(sl, BANK_2, FLASH_H7_SR_ERROR_MASK); + } + break; case STM32_FLASH_TYPE_L0_L1: if (get_stm32l0_flash_base(sl) == STM32L_FLASH_REGS_ADDR) { write_flash_sr(sl, BANK_1, STM32L1_FLASH_SR_ERROR_MASK); @@ -166,11 +179,8 @@ void clear_flash_error(stlink_t *sl) { case STM32_FLASH_TYPE_L4: write_flash_sr(sl, BANK_1, STM32L4_FLASH_SR_ERROR_MASK); break; - case STM32_FLASH_TYPE_H7: - write_flash_sr(sl, BANK_1, FLASH_H7_SR_ERROR_MASK); - if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { - write_flash_sr(sl, BANK_2, FLASH_H7_SR_ERROR_MASK); - } + case STM32_FLASH_TYPE_L5_U5: + write_flash_sr(sl, BANK_1, STM32L5_FLASH_NSSR_ERROR_MASK); break; case STM32_FLASH_TYPE_WB_WL: write_flash_sr(sl, BANK_1, STM32WB_FLASH_SR_ERROR_MASK); @@ -186,21 +196,23 @@ uint32_t read_flash_sr(stlink_t *sl, unsigned bank) { if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || (sl->flash_type == STM32_FLASH_TYPE_F1_XL)) { sr_reg = (bank == BANK_1) ? FLASH_SR : FLASH_SR2; - } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { - sr_reg = get_stm32l0_flash_base(sl) + FLASH_SR_OFF; } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { sr_reg = FLASH_F4_SR; } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { sr_reg = FLASH_F7_SR; - } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { - sr_reg = STM32L4_FLASH_SR; } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || sl->flash_type == STM32_FLASH_TYPE_G4) { sr_reg = STM32Gx_FLASH_SR; - } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { - sr_reg = STM32WB_FLASH_SR; } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { sr_reg = (bank == BANK_1) ? FLASH_H7_SR1 : FLASH_H7_SR2; + } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { + sr_reg = get_stm32l0_flash_base(sl) + FLASH_SR_OFF; + } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { + sr_reg = STM32L4_FLASH_SR; + } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5) { + sr_reg = STM32L5_FLASH_NSSR; + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { + sr_reg = STM32WB_FLASH_SR; } else { ELOG("method 'read_flash_sr' is unsupported\n"); return (-1); @@ -222,15 +234,17 @@ unsigned int is_flash_busy(stlink_t *sl) { sr_busy_shift = FLASH_F4_SR_BSY; } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { sr_busy_shift = FLASH_F7_SR_BSY; - } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { - sr_busy_shift = STM32L4_FLASH_SR_BSY; } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || sl->flash_type == STM32_FLASH_TYPE_G4) { sr_busy_shift = STM32Gx_FLASH_SR_BSY; - } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { - sr_busy_shift = STM32WB_FLASH_SR_BSY; } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { sr_busy_shift = FLASH_H7_SR_QW; + } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { + sr_busy_shift = STM32L4_FLASH_SR_BSY; + } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5) { + sr_busy_shift = STM32L5_FLASH_NSSR_BSY; + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { + sr_busy_shift = STM32WB_FLASH_SR_BSY; } else { ELOG("method 'is_flash_busy' is unsupported\n"); return (-1); @@ -286,6 +300,13 @@ int check_flash_error(stlink_t *sl) { PROGERR = (1 << STM32Gx_FLASH_SR_PROGERR); PGAERR = (1 << STM32Gx_FLASH_SR_PGAERR); break; + case STM32_FLASH_TYPE_H7: + res = read_flash_sr(sl, BANK_1) & FLASH_H7_SR_ERROR_MASK; + if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { + res |= read_flash_sr(sl, BANK_2) & FLASH_H7_SR_ERROR_MASK; + } + WRPERR = (1 << FLASH_H7_SR_WRPERR); + break; case STM32_FLASH_TYPE_L0_L1: res = read_flash_sr(sl, BANK_1); if (get_stm32l0_flash_base(sl) == STM32L_FLASH_REGS_ADDR) { @@ -303,12 +324,11 @@ int check_flash_error(stlink_t *sl) { PROGERR = (1 << STM32L4_FLASH_SR_PROGERR); PGAERR = (1 << STM32L4_FLASH_SR_PGAERR); break; - case STM32_FLASH_TYPE_H7: - res = read_flash_sr(sl, BANK_1) & FLASH_H7_SR_ERROR_MASK; - if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { - res |= read_flash_sr(sl, BANK_2) & FLASH_H7_SR_ERROR_MASK; - } - WRPERR = (1 << FLASH_H7_SR_WRPERR); + case STM32_FLASH_TYPE_L5_U5: + res = read_flash_sr(sl, BANK_1) & STM32L5_FLASH_NSSR_ERROR_MASK; + WRPERR = (1 << STM32L5_FLASH_NSSR_NSWRPERR); + PROGERR = (1 << STM32L5_FLASH_NSSR_NSPROGERR); + PGAERR = (1 << STM32L5_FLASH_NSSR_NSPGAERR); break; case STM32_FLASH_TYPE_WB_WL: res = read_flash_sr(sl, BANK_1) & STM32WB_FLASH_SR_ERROR_MASK; @@ -357,22 +377,25 @@ static inline unsigned int is_flash_locked(stlink_t *sl) { } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { cr_reg = FLASH_F7_CR; cr_lock_shift = FLASH_F7_CR_LOCK; + } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4) { + cr_reg = STM32Gx_FLASH_CR; + cr_lock_shift = STM32Gx_FLASH_CR_LOCK; + } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { + cr_reg = FLASH_H7_CR1; + cr_lock_shift = FLASH_H7_CR_LOCK; } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { cr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF; cr_lock_shift = STM32L0_FLASH_PELOCK; } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { cr_reg = STM32L4_FLASH_CR; cr_lock_shift = STM32L4_FLASH_CR_LOCK; - } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || - sl->flash_type == STM32_FLASH_TYPE_G4) { - cr_reg = STM32Gx_FLASH_CR; - cr_lock_shift = STM32Gx_FLASH_CR_LOCK; + } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5) { + cr_reg = STM32L5_FLASH_NSCR; + cr_lock_shift = STM32L5_FLASH_NSCR_NSLOCK; } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { cr_reg = STM32WB_FLASH_CR; cr_lock_shift = STM32WB_FLASH_CR_LOCK; - } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { - cr_reg = FLASH_H7_CR1; - cr_lock_shift = FLASH_H7_CR_LOCK; } else { ELOG("unsupported flash method, abort\n"); return (-1); @@ -400,22 +423,32 @@ static void unlock_flash(stlink_t *sl) { key_reg = FLASH_F4_KEYR; } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { key_reg = FLASH_F7_KEYR; - } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { - key_reg = get_stm32l0_flash_base(sl) + FLASH_PEKEYR_OFF; - flash_key1 = FLASH_L0_PEKEY1; - flash_key2 = FLASH_L0_PEKEY2; - } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { - key_reg = STM32L4_FLASH_KEYR; } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || sl->flash_type == STM32_FLASH_TYPE_G4) { key_reg = STM32Gx_FLASH_KEYR; - } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { - key_reg = STM32WB_FLASH_KEYR; } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { key_reg = FLASH_H7_KEYR1; if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { key2_reg = FLASH_H7_KEYR2; } + } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { + key_reg = get_stm32l0_flash_base(sl) + FLASH_PEKEYR_OFF; + flash_key1 = FLASH_L0_PEKEY1; + flash_key2 = FLASH_L0_PEKEY2; + } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { + key_reg = STM32L4_FLASH_KEYR; + } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5) { + // Set voltage scaling to range 0 to perform flash operations (RM0438 p. 183) + uint32_t mask = (0b11 << STM32L5_PWR_CR1_VOS); + uint32_t val; + stlink_read_debug32(sl, STM32L5_PWR_CR1, &val); + if ((val & mask) > (1 << STM32L5_PWR_CR1_VOS)) { + val &= ~mask; + stlink_write_debug32(sl, STM32L5_PWR_CR1, val); + } + key_reg = STM32L5_FLASH_NSKEYR; + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { + key_reg = STM32WB_FLASH_KEYR; } else { ELOG("unsupported flash method, abort\n"); return; @@ -464,6 +497,17 @@ int lock_flash_option(stlink_t *sl) { optcr_reg = FLASH_F7_OPTCR; optlock_shift = FLASH_F7_OPTCR_LOCK; break; + case STM32_FLASH_TYPE_G0: + case STM32_FLASH_TYPE_G4: + optcr_reg = STM32Gx_FLASH_CR; + optlock_shift = STM32Gx_FLASH_CR_OPTLOCK; + break; + case STM32_FLASH_TYPE_H7: + optcr_reg = FLASH_H7_OPTCR; + optlock_shift = FLASH_H7_OPTCR_OPTLOCK; + if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) + optcr2_reg = FLASH_H7_OPTCR2; + break; case STM32_FLASH_TYPE_L0_L1: optcr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF; optlock_shift = STM32L0_FLASH_OPTLOCK; @@ -472,21 +516,14 @@ int lock_flash_option(stlink_t *sl) { optcr_reg = STM32L4_FLASH_CR; optlock_shift = STM32L4_FLASH_CR_OPTLOCK; break; - case STM32_FLASH_TYPE_G0: - case STM32_FLASH_TYPE_G4: - optcr_reg = STM32Gx_FLASH_CR; - optlock_shift = STM32Gx_FLASH_CR_OPTLOCK; + case STM32_FLASH_TYPE_L5_U5: + optcr_reg = STM32L5_FLASH_NSCR; + optlock_shift = STM32L5_FLASH_NSCR_OPTLOCK; break; case STM32_FLASH_TYPE_WB_WL: optcr_reg = STM32WB_FLASH_CR; optlock_shift = STM32WB_FLASH_CR_OPTLOCK; break; - case STM32_FLASH_TYPE_H7: - optcr_reg = FLASH_H7_OPTCR; - optlock_shift = FLASH_H7_OPTCR_OPTLOCK; - if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) - optcr2_reg = FLASH_H7_OPTCR2; - break; default: ELOG("unsupported flash method, abort\n"); return -1; @@ -537,6 +574,15 @@ static bool is_flash_option_locked(stlink_t *sl) { optcr_reg = FLASH_F7_OPTCR; optlock_shift = FLASH_F7_OPTCR_LOCK; break; + case STM32_FLASH_TYPE_G0: + case STM32_FLASH_TYPE_G4: + optcr_reg = STM32Gx_FLASH_CR; + optlock_shift = STM32Gx_FLASH_CR_OPTLOCK; + break; + case STM32_FLASH_TYPE_H7: + optcr_reg = FLASH_H7_OPTCR; + optlock_shift = FLASH_H7_OPTCR_OPTLOCK; + break; case STM32_FLASH_TYPE_L0_L1: optcr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF; optlock_shift = STM32L0_FLASH_OPTLOCK; @@ -545,19 +591,14 @@ static bool is_flash_option_locked(stlink_t *sl) { optcr_reg = STM32L4_FLASH_CR; optlock_shift = STM32L4_FLASH_CR_OPTLOCK; break; - case STM32_FLASH_TYPE_G0: - case STM32_FLASH_TYPE_G4: - optcr_reg = STM32Gx_FLASH_CR; - optlock_shift = STM32Gx_FLASH_CR_OPTLOCK; + case STM32_FLASH_TYPE_L5_U5: + optcr_reg = STM32L5_FLASH_NSCR; + optlock_shift = STM32L5_FLASH_NSCR_OPTLOCK; break; case STM32_FLASH_TYPE_WB_WL: optcr_reg = STM32WB_FLASH_CR; optlock_shift = STM32WB_FLASH_CR_OPTLOCK; break; - case STM32_FLASH_TYPE_H7: - optcr_reg = FLASH_H7_OPTCR; - optlock_shift = FLASH_H7_OPTCR_OPTLOCK; - break; default: ELOG("unsupported flash method, abort\n"); return -1; @@ -590,6 +631,15 @@ static int unlock_flash_option(stlink_t *sl) { case STM32_FLASH_TYPE_F7: optkey_reg = FLASH_F7_OPT_KEYR; break; + case STM32_FLASH_TYPE_G0: + case STM32_FLASH_TYPE_G4: + optkey_reg = STM32Gx_FLASH_OPTKEYR; + break; + case STM32_FLASH_TYPE_H7: + optkey_reg = FLASH_H7_OPT_KEYR; + if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) + optkey2_reg = FLASH_H7_OPT_KEYR2; + break; case STM32_FLASH_TYPE_L0_L1: optkey_reg = get_stm32l0_flash_base(sl) + FLASH_OPTKEYR_OFF; optkey1 = FLASH_L0_OPTKEY1; @@ -598,18 +648,12 @@ static int unlock_flash_option(stlink_t *sl) { case STM32_FLASH_TYPE_L4: optkey_reg = STM32L4_FLASH_OPTKEYR; break; - case STM32_FLASH_TYPE_G0: - case STM32_FLASH_TYPE_G4: - optkey_reg = STM32Gx_FLASH_OPTKEYR; + case STM32_FLASH_TYPE_L5_U5: + optkey_reg = STM32L5_FLASH_OPTKEYR; break; case STM32_FLASH_TYPE_WB_WL: optkey_reg = STM32WB_FLASH_OPT_KEYR; break; - case STM32_FLASH_TYPE_H7: - optkey_reg = FLASH_H7_OPT_KEYR; - if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) - optkey2_reg = FLASH_H7_OPT_KEYR2; - break; default: ELOG("unsupported flash method, abort\n"); return (-1); @@ -672,16 +716,18 @@ void clear_flash_cr_pg(stlink_t *sl, unsigned bank) { cr_reg = FLASH_F4_CR; } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { cr_reg = FLASH_F7_CR; - } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { - cr_reg = STM32L4_FLASH_CR; } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || sl->flash_type == STM32_FLASH_TYPE_G4) { cr_reg = STM32Gx_FLASH_CR; - } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { - cr_reg = STM32WB_FLASH_CR; } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { cr_reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; bit = FLASH_H7_CR_PG; + } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { + cr_reg = STM32L4_FLASH_CR; + } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5) { + cr_reg = STM32L5_FLASH_NSCR; + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { + cr_reg = STM32WB_FLASH_CR; } else { cr_reg = FLASH_CR; } @@ -744,6 +790,8 @@ static void set_flash_cr_per(stlink_t *sl, unsigned bank) { if (sl->flash_type == STM32_FLASH_TYPE_G0 || sl->flash_type == STM32_FLASH_TYPE_G4) { cr_reg = STM32Gx_FLASH_CR; + } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5) { + cr_reg = STM32L5_FLASH_NSCR; } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { cr_reg = STM32WB_FLASH_CR; } else { @@ -761,6 +809,8 @@ static void clear_flash_cr_per(stlink_t *sl, unsigned bank) { if (sl->flash_type == STM32_FLASH_TYPE_G0 || sl->flash_type == STM32_FLASH_TYPE_G4) { cr_reg = STM32Gx_FLASH_CR; + } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5) { + cr_reg = STM32L5_FLASH_NSCR; } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { cr_reg = STM32WB_FLASH_CR; } else { @@ -796,19 +846,22 @@ static void set_flash_cr_strt(stlink_t *sl, unsigned bank) { } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { cr_reg = FLASH_F7_CR; cr_strt = 1 << FLASH_F7_CR_STRT; - } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { - cr_reg = STM32L4_FLASH_CR; - cr_strt = (1 << STM32L4_FLASH_CR_STRT); } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || sl->flash_type == STM32_FLASH_TYPE_G4) { cr_reg = STM32Gx_FLASH_CR; cr_strt = (1 << STM32Gx_FLASH_CR_STRT); - } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { - cr_reg = STM32WB_FLASH_CR; - cr_strt = (1 << STM32WB_FLASH_CR_STRT); } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { cr_reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; cr_strt = 1 << FLASH_H7_CR_START(sl->chip_id); + } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { + cr_reg = STM32L4_FLASH_CR; + cr_strt = (1 << STM32L4_FLASH_CR_STRT); + } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5) { + cr_reg = STM32L5_FLASH_NSCR; + cr_strt = (1 << STM32L5_FLASH_NSCR_NSSTRT); + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { + cr_reg = STM32WB_FLASH_CR; + cr_strt = (1 << STM32WB_FLASH_CR_STRT); } else { cr_reg = (bank == BANK_1) ? FLASH_CR : FLASH_CR2; cr_strt = (1 << FLASH_CR_STRT); @@ -830,28 +883,30 @@ static void set_flash_cr_mer(stlink_t *sl, bool v, unsigned bank) { cr_reg = FLASH_F7_CR; cr_mer = 1 << FLASH_CR_MER; cr_pg = 1 << FLASH_CR_PG; - } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { - cr_reg = STM32L4_FLASH_CR; - cr_mer = (1 << STM32L4_FLASH_CR_MER1) | (1 << STM32L4_FLASH_CR_MER2); - cr_pg = (1 << STM32L4_FLASH_CR_PG); } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || sl->flash_type == STM32_FLASH_TYPE_G4) { cr_reg = STM32Gx_FLASH_CR; cr_mer = (1 << STM32Gx_FLASH_CR_MER1); - if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { cr_mer |= (1 << STM32Gx_FLASH_CR_MER2); } - - cr_pg = (1 << FLASH_CR_PG); - } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { - cr_reg = STM32WB_FLASH_CR; - cr_mer = (1 << FLASH_CR_MER); cr_pg = (1 << FLASH_CR_PG); } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { cr_reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; cr_mer = (1 << FLASH_H7_CR_BER); cr_pg = (1 << FLASH_H7_CR_PG); + } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { + cr_reg = STM32L4_FLASH_CR; + cr_mer = (1 << STM32L4_FLASH_CR_MER1) | (1 << STM32L4_FLASH_CR_MER2); + cr_pg = (1 << STM32L4_FLASH_CR_PG); + } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5) { + cr_reg = STM32L5_FLASH_NSCR; + cr_mer = (1 << STM32L5_FLASH_NSCR_NSMER1) | (1 << STM32L5_FLASH_NSCR_NSMER2); + cr_pg = (1 << STM32L5_FLASH_NSCR_NSPG); + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { + cr_reg = STM32WB_FLASH_CR; + cr_mer = (1 << FLASH_CR_MER); + cr_pg = (1 << FLASH_CR_PG); } else { cr_reg = (bank == BANK_1) ? FLASH_CR : FLASH_CR2; cr_mer = (1 << FLASH_CR_MER); @@ -993,25 +1048,16 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); val |= (1 << 0) | (1 << 1) | (1 << 2); stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); - } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL || - sl->flash_type == STM32_FLASH_TYPE_G0 || - sl->flash_type == STM32_FLASH_TYPE_G4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4 || + sl->flash_type == STM32_FLASH_TYPE_L5_U5 || + sl->flash_type == STM32_FLASH_TYPE_WB_WL) { uint32_t val; unlock_flash_if(sl); set_flash_cr_per(sl, BANK_1); // set the 'enable Flash erase' bit // set the page to erase - if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { - uint32_t flash_page = - ((flashaddr - STM32_FLASH_BASE) / (uint32_t)(sl->flash_pgsz)); - stlink_read_debug32(sl, STM32WB_FLASH_CR, &val); - - // sec 3.10.5 - PNB[7:0] is offset by 3. - val &= ~(0xFF << 3); // Clear previously set page number (if any) - val |= ((flash_page & 0xFF) << 3); - - stlink_write_debug32(sl, STM32WB_FLASH_CR, val); - } else if (sl->flash_type == STM32_FLASH_TYPE_G0) { + if (sl->flash_type == STM32_FLASH_TYPE_G0) { uint32_t flash_page = ((flashaddr - STM32_FLASH_BASE) / (uint32_t)(sl->flash_pgsz)); stlink_read_debug32(sl, STM32Gx_FLASH_CR, &val); @@ -1027,6 +1073,34 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { val &= ~(0x7F << 3); val |= ((flash_page & 0x7F) << 3) | (1 << FLASH_CR_PER); stlink_write_debug32(sl, STM32Gx_FLASH_CR, val); + } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5) { + uint32_t flash_page; + stlink_read_debug32(sl, STM32L5_FLASH_NSCR, &val); + if (sl->flash_pgsz == 0x800 && (flashaddr - STM32_FLASH_BASE) >= sl->flash_size/2) { + flash_page = (flashaddr - STM32_FLASH_BASE - sl->flash_size/2) / + (uint32_t)(sl->flash_pgsz); + // set bank 2 for erasure + val |= (1 << STM32L5_FLASH_NSCR_NSBKER); + } else { + flash_page = + ((flashaddr - STM32_FLASH_BASE) / (uint32_t)(sl->flash_pgsz)); + // set bank 1 for erasure + val &= ~(1 << STM32L5_FLASH_NSCR_NSBKER); + } + // sec 6.9.9 + val &= ~(0x7F << 3); + val |= ((flash_page & 0x7F) << 3) | (1 << FLASH_CR_PER); + stlink_write_debug32(sl, STM32L5_FLASH_NSCR, val); + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { + uint32_t flash_page = + ((flashaddr - STM32_FLASH_BASE) / (uint32_t)(sl->flash_pgsz)); + stlink_read_debug32(sl, STM32WB_FLASH_CR, &val); + + // sec 3.10.5 - PNB[7:0] is offset by 3. + val &= ~(0xFF << 3); // Clear previously set page number (if any) + val |= ((flash_page & 0xFF) << 3); + + stlink_write_debug32(sl, STM32WB_FLASH_CR, val); } set_flash_cr_strt(sl, BANK_1); // set the 'start operation' bit diff --git a/src/stlink-lib/flashloader.c b/src/stlink-lib/flashloader.c index d9542ebbc..7164983cd 100644 --- a/src/stlink-lib/flashloader.c +++ b/src/stlink-lib/flashloader.c @@ -46,8 +46,7 @@ int stm32l1_write_half_pages(stlink_t *sl, stm32_addr_t addr, uint8_t *base, } if (ret) { - WLOG("l1_stlink_flash_loader_run(%#x) failed! == -1\n", - addr + count * pagesize); + WLOG("l1_stlink_flash_loader_run(%#x) failed! == -1\n", addr + count * pagesize); break; } @@ -84,6 +83,9 @@ static void set_flash_cr_pg(stlink_t *sl, unsigned bank) { cr_reg = STM32L4_FLASH_CR; x &= ~STM32L4_FLASH_CR_OPBITS; x |= (1 << STM32L4_FLASH_CR_PG); + } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5) { + cr_reg = STM32L5_FLASH_NSCR; + x |= (1 << FLASH_CR_PG); } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || sl->flash_type == STM32_FLASH_TYPE_G4) { cr_reg = STM32Gx_FLASH_CR; @@ -136,6 +138,10 @@ static void set_dma_state(stlink_t *sl, flash_loader_t *fl, int bckpRstr) { rcc_dma_mask = STM32L0_RCC_DMAEN; } break; + case STM32_FLASH_TYPE_L5_U5: + rcc = STM32L5_RCC_AHB1ENR; + rcc_dma_mask = STM32L5_RCC_DMAEN; + break; case STM32_FLASH_TYPE_H7: rcc = STM32H7_RCC_AHB1ENR; rcc_dma_mask = STM32H7_RCC_DMAEN; @@ -216,8 +222,9 @@ int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { set_flash_cr_pg(sl, BANK_1); } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL || sl->flash_type == STM32_FLASH_TYPE_G0 || - sl->flash_type == STM32_FLASH_TYPE_G4) { - ILOG("Starting Flash write for WB/G0/G4\n"); + sl->flash_type == STM32_FLASH_TYPE_G4 || + sl->flash_type == STM32_FLASH_TYPE_L5_U5) { + ILOG("Starting Flash write for WB/G0/G4/L5/U5\n"); unlock_flash_if(sl); // unlock flash if necessary set_flash_cr_pg(sl, BANK_1); // set PG 'allow programming' bit @@ -320,14 +327,15 @@ int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, } } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL || sl->flash_type == STM32_FLASH_TYPE_G0 || - sl->flash_type == STM32_FLASH_TYPE_G4) { + sl->flash_type == STM32_FLASH_TYPE_G4 || + sl->flash_type == STM32_FLASH_TYPE_L5_U5) { DLOG("Starting %3u page write\r\n", (unsigned int)(len / sl->flash_pgsz)); for (off = 0; off < len; off += sizeof(uint32_t)) { uint32_t data; if ((off % sl->flash_pgsz) > (sl->flash_pgsz - 5)) { fprintf(stdout, "\r%3u/%3u pages written", - (unsigned int)(off / sl->flash_pgsz), + (unsigned int)(off / sl->flash_pgsz + 1), (unsigned int)(len / sl->flash_pgsz)); fflush(stdout); } @@ -368,7 +376,7 @@ int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, if ((off % sl->flash_pgsz) > (sl->flash_pgsz - 5)) { fprintf(stdout, "\r%3u/%3u pages written", - (unsigned int)(off / sl->flash_pgsz), + (unsigned int)(off / sl->flash_pgsz + 1), (unsigned int)(len / sl->flash_pgsz)); fflush(stdout); } @@ -451,11 +459,12 @@ int stlink_flashloader_stop(stlink_t *sl, flash_loader_t *fl) { (sl->flash_type == STM32_FLASH_TYPE_F1_XL) || (sl->flash_type == STM32_FLASH_TYPE_F2_F4) || (sl->flash_type == STM32_FLASH_TYPE_F7) || - (sl->flash_type == STM32_FLASH_TYPE_L4) || - (sl->flash_type == STM32_FLASH_TYPE_WB_WL) || (sl->flash_type == STM32_FLASH_TYPE_G0) || (sl->flash_type == STM32_FLASH_TYPE_G4) || - (sl->flash_type == STM32_FLASH_TYPE_H7)) { + (sl->flash_type == STM32_FLASH_TYPE_H7) || + (sl->flash_type == STM32_FLASH_TYPE_L4) || + (sl->flash_type == STM32_FLASH_TYPE_L5_U5) || + (sl->flash_type == STM32_FLASH_TYPE_WB_WL)) { clear_flash_cr_pg(sl, BANK_1); if ((sl->flash_type == STM32_FLASH_TYPE_H7 && diff --git a/src/stlink-lib/option_bytes.c b/src/stlink-lib/option_bytes.c index 3d332f49d..2d4898001 100644 --- a/src/stlink-lib/option_bytes.c +++ b/src/stlink-lib/option_bytes.c @@ -510,8 +510,7 @@ static int stlink_write_option_bytes_h7(stlink_t *sl, stm32_addr_t addr, uint8_t case FLASH_H7_REGS_ADDR + 0x3c: // FLASH_WPSN_PRG1 case FLASH_H7_REGS_ADDR + 0x44: // FLASH_BOOT_PRG /* Write to FLASH_xxx_PRG registers */ - write_uint32((unsigned char *)&data, - *(uint32_t *)(base)); // write options bytes + write_uint32((unsigned char *)&data, *(uint32_t *)(base)); // write options bytes WLOG("Writing option bytes %#10x to %#10x\n", data, addr); @@ -534,8 +533,7 @@ static int stlink_write_option_bytes_h7(stlink_t *sl, stm32_addr_t addr, uint8_t /* Check for errors */ if ((val & (1 << FLASH_H7_OPTSR_OPTCHANGEERR)) != 0) { - stlink_write_debug32(sl, FLASH_H7_OPTCCR, - 1 << FLASH_H7_OPTCCR_CLR_OPTCHANGEERR); + stlink_write_debug32(sl, FLASH_H7_OPTCCR, 1 << FLASH_H7_OPTCCR_CLR_OPTCHANGEERR); return -1; } break; @@ -753,8 +751,7 @@ int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t *base, ui int ret = -1; if (sl->option_base == 0) { - ELOG( - "Option bytes writing is currently not supported for connected chip\n"); + ELOG("Option bytes writing is currently not supported for connected chip\n"); return (-1); } @@ -771,8 +768,7 @@ int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t *base, ui wait_flash_busy(sl); if (unlock_flash_if(sl)) { - ELOG("Flash unlock failed! System reset required to be able to unlock it " - "again!\n"); + ELOG("Flash unlock failed! System reset required to be able to unlock it again!\n"); return (-1); } @@ -809,8 +805,7 @@ int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t *base, ui ret = stlink_write_option_bytes_wb(sl, addr, base, len); break; default: - ELOG("Option bytes writing is currently not implemented for connected " - "chip\n"); + ELOG("Option bytes writing is currently not implemented for connected chip\n"); break; } @@ -892,8 +887,7 @@ int stlink_write_option_control_register32(stlink_t *sl, uint32_t option_cr) { wait_flash_busy(sl); if (unlock_flash_if(sl)) { - ELOG("Flash unlock failed! System reset required to be able to unlock it " - "again!\n"); + ELOG("Flash unlock failed! System reset required to be able to unlock it again!\n"); return -1; } @@ -915,8 +909,7 @@ int stlink_write_option_control_register32(stlink_t *sl, uint32_t option_cr) { stlink_write_option_control_register_wb(sl, option_cr); break; default: - ELOG("Option control register writing is currently not implemented for " - "connected chip\n"); + ELOG("Option control register writing is currently not implemented for connected chip\n"); break; } @@ -965,8 +958,7 @@ int stlink_write_option_control_register1_32(stlink_t *sl, uint32_t option_cr1) wait_flash_busy(sl); if (unlock_flash_if(sl)) { - ELOG("Flash unlock failed! System reset required to be able to unlock it " - "again!\n"); + ELOG("Flash unlock failed! System reset required to be able to unlock it again!\n"); return -1; } @@ -1050,8 +1042,7 @@ int stlink_write_option_bytes32(stlink_t *sl, uint32_t option_byte) { */ int stlink_read_option_bytes_boot_add32(stlink_t *sl, uint32_t *option_byte) { if (sl->option_base == 0) { - ELOG("Option bytes boot address read is currently not supported for " - "connected chip\n"); + ELOG("Option bytes boot address read is currently not supported for connected chip\n"); return -1; } @@ -1076,8 +1067,7 @@ int stlink_write_option_bytes_boot_add32(stlink_t *sl, uint32_t option_bytes_boo wait_flash_busy(sl); if (unlock_flash_if(sl)) { - ELOG("Flash unlock failed! System reset required to be able to unlock it " - "again!\n"); + ELOG("Flash unlock failed! System reset required to be able to unlock it again!\n"); return -1; } @@ -1091,8 +1081,7 @@ int stlink_write_option_bytes_boot_add32(stlink_t *sl, uint32_t option_bytes_boo ret = stlink_write_option_bytes_boot_add_f7(sl, option_bytes_boot_add); break; default: - ELOG("Option bytes boot address writing is currently not implemented for " - "connected chip\n"); + ELOG("Option bytes boot address writing is currently not implemented for connected chip\n"); break; } From 893523d74ed83abf26b994cb7e608f87b39bfda0 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 1 Jan 2023 16:27:13 +0100 Subject: [PATCH 413/503] Updated CHANGELOG.md --- CHANGELOG.md | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index 82656d50b..ddd795c37 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -17,7 +17,7 @@ Features: - Added chip-IDs for STM32G0B0/G0B1/G0C1/G050/G051/G061 ([#1140](https://github.com/stlink-org/stlink/pull/1140)) - Added option byte info for STM32F411XX ([#1141](https://github.com/stlink-org/stlink/pull/1141)) - Expanded and revised list of chips ([#1145](https://github.com/stlink-org/stlink/pull/1145), [#1164](https://github.com/stlink-org/stlink/pull/1164)) -- [STM32H72X/3X]: Added full access to all device memory ([#1158](https://github.com/stlink-org/stlink/pull/1158), [#1159](https://github.com/stlink-org/stlink/pull/1159)) +- STM32H72X/3X: Added full access to all device memory ([#1158](https://github.com/stlink-org/stlink/pull/1158), [#1159](https://github.com/stlink-org/stlink/pull/1159)) - Added support for STM32WLEx ([#1173](https://github.com/stlink-org/stlink/pull/1173), [#1273](https://github.com/stlink-org/stlink/pull/1273)) - Added support for STLINK-V3 devices with no MSD ([#1185](https://github.com/stlink-org/stlink/pull/1185)) - Updated gdb-server.c to allow external memory access on STM32H73xx ([#1196](https://github.com/stlink-org/stlink/pull/1196), [#1197](https://github.com/stlink-org/stlink/pull/1197)) @@ -51,7 +51,7 @@ Fixes: - cmake: Install shared libraries in proper directories ([#1142](https://github.com/stlink-org/stlink/pull/1142)) - Fixed clearance of the H7 dual bank flag ([#1146](https://github.com/stlink-org/stlink/pull/1146), [#1147](https://github.com/stlink-org/stlink/pull/1147)) - Fix for 'libusb_devices were leaked' when no ST-LINK programmer was found ([#1150](https://github.com/stlink-org/stlink/pull/1150)) -- Set of fixes and improvements ([#1154](https://github.com/stlink-org/stlink/pull/1154)) +- Set of fixes and improvements ([#1153](https://github.com/stlink-org/stlink/pull/1153), [#1154](https://github.com/stlink-org/stlink/pull/1154)) - Removed limit check for WRITEMEM_32BIT ([#1157](https://github.com/stlink-org/stlink/pull/1157)) - Fixed get_stm32l0_flash_base address for STM32L152RE ([#1161](https://github.com/stlink-org/stlink/pull/1161), [#1162](https://github.com/stlink-org/stlink/pull/1162)) - Fixed segfault if chip was not found in chip config files ([#1138](https://github.com/stlink-org/stlink/pull/1138), [#1163](https://github.com/stlink-org/stlink/pull/1163), [#1165](https://github.com/stlink-org/stlink/pull/1165), [#1166](https://github.com/stlink-org/stlink/pull/1166), [#1170](https://github.com/stlink-org/stlink/pull/1170)) @@ -65,7 +65,7 @@ Fixes: - Fixed compliation for OpenBSD 7.0 ([#1202](https://github.com/stlink-org/stlink/pull/1202)) - Included 'SSIZE_MAX' from 'limits.h' in 'src/common.c' ([#1207](https://github.com/stlink-org/stlink/pull/1207)) - Fix for libusb_kernel_driver_active & error handling for st.st_size () ([#1210](https://github.com/stlink-org/stlink/pull/1210), [#1211](https://github.com/stlink-org/stlink/pull/1211), [#1214](https://github.com/stlink-org/stlink/pull/1214) -- st-trace: Fixed clock issues ([#1251](https://github.com/stlink-org/stlink/pull/1251), [#1252](https://github.com/stlink-org/stlink/pull/1252)) +- st-trace: Fixed clock issues ([#1248](https://github.com/stlink-org/stlink/pull/1248), [#1251](https://github.com/stlink-org/stlink/pull/1251), [#1252](https://github.com/stlink-org/stlink/pull/1252)) - Fixed compilation with gcc-12 ([#1257](https://github.com/stlink-org/stlink/pull/1257), [#1267](https://github.com/stlink-org/stlink/pull/1267)) - Fixed flash regs addr for STM32L152RET6 in common_flash.c ([#1265](https://github.com/stlink-org/stlink/pull/1265)) - Fixed flash, dbgmcu and rcc registers for STM32L1 ([#1266](https://github.com/stlink-org/stlink/pull/1266)) From 54e4bc5251933bbd6206d3548918e52a1b85d66c Mon Sep 17 00:00:00 2001 From: John Hall Date: Sun, 1 Jan 2023 16:01:58 -0800 Subject: [PATCH 414/503] Updating windows signal handling to not terminate the application before cleanup. --- src/st-trace/trace.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/st-trace/trace.c b/src/st-trace/trace.c index 9fcf8e358..e0bf3c88d 100644 --- a/src/st-trace/trace.c +++ b/src/st-trace/trace.c @@ -88,7 +88,7 @@ static void abort_trace() { g_abort_trace = true; } BOOL WINAPI CtrlHandler(DWORD fdwCtrlType) { (void)fdwCtrlType; abort_trace(); - return FALSE; + return TRUE; } #endif From 750a92cdc40ef33d0e3fc7208da9c30496d22aae Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Mon, 2 Jan 2023 11:59:26 +0100 Subject: [PATCH 415/503] Log message improvements for st-flash --- src/st-flash/flash.c | 1 + src/stlink-lib/common.c | 8 +++----- src/stlink-lib/common_flash.c | 2 +- 3 files changed, 5 insertions(+), 6 deletions(-) diff --git a/src/st-flash/flash.c b/src/st-flash/flash.c index cef0b639f..39b31f219 100644 --- a/src/st-flash/flash.c +++ b/src/st-flash/flash.c @@ -179,6 +179,7 @@ int main(int ac, char** av) { printf("stlink_erase_flash_mass() == -1\n"); goto on_error; } + printf("Mass erase completed successfully.\n"); } else if (o.cmd == CMD_RESET) { if (stlink_reset(sl, RESET_AUTO)) { printf("Failed to reset device\n"); diff --git a/src/stlink-lib/common.c b/src/stlink-lib/common.c index fe5574706..cb037fb2f 100644 --- a/src/stlink-lib/common.c +++ b/src/stlink-lib/common.c @@ -342,11 +342,9 @@ int stlink_reset(stlink_t *sl, enum reset_type type) { dhcsr = 0; int res = stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); if ((dhcsr & STLINK_REG_DHCSR_S_RESET_ST) == 0 && !res) { - // reset not done yet - // try reset through AIRCR so that NRST does not need to be connected - - WLOG("NRST is not connected\n"); - DLOG("Using reset through SYSRESETREQ\n"); + // reset not done yet --> try reset through AIRCR so that NRST does not need to be connected + ILOG("NRST is not connected --> using software reset via AIRCR\n"); + DLOG("NRST not connected --> Reset through SYSRESETREQ\n"); return stlink_soft_reset(sl, 0); } diff --git a/src/stlink-lib/common_flash.c b/src/stlink-lib/common_flash.c index 5b8075ea7..e84b307eb 100644 --- a/src/stlink-lib/common_flash.c +++ b/src/stlink-lib/common_flash.c @@ -739,7 +739,7 @@ void clear_flash_cr_pg(stlink_t *sl, unsigned bank) { static void wait_flash_busy_progress(stlink_t *sl) { int i = 0; - fprintf(stdout, "Mass erasing"); + fprintf(stdout, "Mass erasing..."); fflush(stdout); while (is_flash_busy(sl)) { From 2a8a36efba2cf6bae3506f0d92c24ebea46674ba Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Mon, 2 Jan 2023 12:21:18 +0100 Subject: [PATCH 416/503] Updated GitHub Actions C/C++ CI workflow --- .github/workflows/c-cpp.yml | 106 +++++++++++++++++++++++++++++++++--- 1 file changed, 98 insertions(+), 8 deletions(-) diff --git a/.github/workflows/c-cpp.yml b/.github/workflows/c-cpp.yml index 8e798269b..fe07c6e44 100644 --- a/.github/workflows/c-cpp.yml +++ b/.github/workflows/c-cpp.yml @@ -15,7 +15,7 @@ jobs: steps: - uses: actions/checkout@v2 - name: install dependencies - run: sudo apt update && sudo apt-get install gcc-6 libusb-1.0.0-dev libgtk-3-dev rpm + run: sudo apt update && sudo apt-get install gcc-8 libusb-1.0.0-dev libgtk-3-dev rpm - name: make debug run: sudo make clean && make debug - name: make test @@ -35,7 +35,7 @@ jobs: steps: - uses: actions/checkout@v2 - name: install dependencies - run: sudo apt update && sudo apt-get install gcc-6 libusb-1.0.0-dev libgtk-3-dev rpm + run: sudo apt update && sudo apt-get install gcc-8 libusb-1.0.0-dev libgtk-3-dev rpm - name: Set compiler flags run: | CFLAGS="$CFLAGS -m32" @@ -150,7 +150,7 @@ jobs: steps: - uses: actions/checkout@v2 - name: Install dependencies - run: sudo apt update && sudo apt-get install clang-10 libusb-1.0.0-dev libgtk-3-dev rpm + run: sudo apt update && sudo apt-get install clang-12 libusb-1.0.0-dev libgtk-3-dev rpm - name: make debug run: sudo make clean && make debug - name: make test @@ -170,7 +170,97 @@ jobs: steps: - uses: actions/checkout@v2 - name: Install dependencies - run: sudo apt update && sudo apt-get install clang-10 libusb-1.0.0-dev libgtk-3-dev rpm + run: sudo apt update && sudo apt-get install clang-12 libusb-1.0.0-dev libgtk-3-dev rpm + - name: Set compiler flags + run: | + CFLAGS="$CFLAGS -m32" + CXXFLAGS="$CXXFLAGS -m32" + LDFLAGS="$LDFLAGS -m32" + - name: make debug + run: sudo make clean && make debug + - name: make test + run: sudo make clean && make test + - name: make release + run: sudo make clean && make release + - name: sudo make install + run: sudo make clean && sudo make install + - name: sudo make package + run: sudo make package + - name: sudo make uninstall + run: sudo make uninstall && sudo make clean + + job_linux_22_04_64_gcc: + name: ubuntu-22.04 gcc + runs-on: ubuntu-22.04 + steps: + - uses: actions/checkout@v2 + - name: Install dependencies + run: sudo apt update && sudo apt-get install gcc-12 libusb-1.0.0-dev libgtk-4-dev rpm + - name: make debug + run: sudo make clean && make debug + - name: make test + run: sudo make clean && make test + - name: make release + run: sudo make clean && make release + - name: sudo make install + run: sudo make clean && sudo make install + - name: sudo make package + run: sudo make package + - name: sudo make uninstall + run: sudo make uninstall && sudo make clean + + job_linux_22_04_32_gcc: + name: ubuntu-22.04 gcc 32-bit + runs-on: ubuntu-22.04 + steps: + - uses: actions/checkout@v2 + - name: Install dependencies + run: sudo apt update && sudo apt-get install gcc-12 libusb-1.0.0-dev libgtk-4-dev rpm + - name: Set compiler flags + run: | + CFLAGS="$CFLAGS -m32" + CXXFLAGS="$CXXFLAGS -m32" + LDFLAGS="$LDFLAGS -m32" + - name: make debug + run: sudo make clean && make debug + - name: make test + run: sudo make clean && make test + - name: make release + run: sudo make clean && make release + - name: sudo make install + run: sudo make clean && sudo make install + - name: sudo make package + run: sudo make package + - name: sudo make uninstall + run: sudo make uninstall && sudo make clean + + job_linux_22_04_64_clang: + name: ubuntu-22.04 clang + runs-on: ubuntu-22.04 + steps: + - uses: actions/checkout@v2 + - name: Install dependencies + run: sudo apt update && sudo apt-get install clang-14 libusb-1.0.0-dev libgtk-4-dev rpm + - name: make debug + run: sudo make clean && make debug + - name: make test + run: sudo make clean && make test + - name: make release + run: sudo make clean && make release + - name: sudo make install + run: sudo make clean && sudo make install + - name: sudo make package + run: sudo make package + - name: sudo make uninstall + run: sudo make uninstall && sudo make clean + + job_linux_22_04_32_clang: + name: ubuntu-22.04 clang 32-bit + runs-on: ubuntu-22.04 + steps: + - uses: actions/checkout@v2 + - name: Install dependencies + run: sudo apt update && sudo apt-get install clang-14 libusb-1.0.0-dev libgtk-4-dev rpm - name: Set compiler flags run: | CFLAGS="$CFLAGS -m32" @@ -190,13 +280,13 @@ jobs: run: sudo make uninstall && sudo make clean # Linux MinGW cross compliation -# job_linux_20_04_cross: -# name: ubuntu-20.04 mingw64 -# runs-on: ubuntu-20.04 +# job_linux_22_04_cross: +# name: ubuntu-22.04 mingw64 +# runs-on: ubuntu-22.04 # steps: # - uses: actions/checkout@v2 # - name: Install dependencies -# run: sudo apt-get install gcc-10 libusb-1.0.0-dev libgtk-3-dev rpm mingw-w64 +# run: sudo apt-get install gcc-12 libusb-1.0.0-dev libgtk-4-dev rpm mingw-w64 # - name: Building Release for Windows (x86-64) ... # run: sudo mkdir -p build-mingw && cd build-mingw && sudo cmake \ # -DCMAKE_SYSTEM_NAME=Windows \ From 61ff09e5274d46a46ae58bc4ffe44fe90a887ea6 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sat, 14 Jan 2023 12:14:35 +0100 Subject: [PATCH 417/503] [doc] End of support for macOS (Closes #1296) --- README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README.md b/README.md index 571db49fd..661a60764 100644 --- a/README.md +++ b/README.md @@ -84,7 +84,7 @@ We recommend to install `stlink-tools` from the package repository of the used d - RedHat/CentOS 8: Users can install from [EPEL repository](https://src.fedoraproject.org/rpms/stlink/branch/epel8) - FreeBSD: Users can install from [freshports](https://www.freshports.org/devel/stlink) -- MacOS: Users can open a terminal window and then follow the same procedure as for installing on Linux +- MacOS: **Support for macOS will end with v1.7.1.** Please use v1.7.0 (current ***master*** branch) and the related documentation instead. ## Installation from source (advanced users) From 82fb1cc773bd481c93c8b7260e1d64cb020f20b9 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 15 Jan 2023 14:14:25 +0100 Subject: [PATCH 418/503] Updated header files in CMakeLists.txt --- CMakeLists.txt | 30 ++++++++++++++++++------------ 1 file changed, 18 insertions(+), 12 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index b25291992..7d8bce8cf 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -166,35 +166,41 @@ add_subdirectory(inc) set(STLINK_HEADERS inc/backend.h inc/stlink.h - src/stlink-lib/common_flash.h + inc/stm32.h + inc/stm32flash.h src/stlink-lib/calculate.h - src/stlink-lib/commands.h - src/stlink-lib/libusb_settings.h - src/stlink-lib/reg.h src/stlink-lib/chipid.h + src/stlink-lib/commands.h + src/stlink-lib/common_flash.h + src/stlink-lib/common.h src/stlink-lib/flash_loader.h + src/stlink-lib/flashloader.h + src/stlink-lib/helper.h + src/stlink-lib/libusb_settings.h src/stlink-lib/logging.h + src/stlink-lib/map_file.h src/stlink-lib/md5.h + src/stlink-lib/option_bytes.h + src/stlink-lib/reg.h src/stlink-lib/sg.h src/stlink-lib/usb.h - src/stlink-lib/helper.h ) set(STLINK_SOURCE - src/stlink-lib/read_write.c - src/stlink-lib/common.c - src/stlink-lib/option_bytes.c - src/stlink-lib/common_flash.c - src/stlink-lib/map_file.c - src/stlink-lib/flashloader.c src/stlink-lib/calculate.c src/stlink-lib/chipid.c + src/stlink-lib/common_flash.c + src/stlink-lib/common.c src/stlink-lib/flash_loader.c + src/stlink-lib/flashloader.c + src/stlink-lib/helper.c src/stlink-lib/logging.c + src/stlink-lib/map_file.c src/stlink-lib/md5.c + src/stlink-lib/option_bytes.c + src/stlink-lib/read_write.c src/stlink-lib/sg.c src/stlink-lib/usb.c - src/stlink-lib/helper.c ) if (WIN32) From 1bec78c4289ec82f8e43565d610489e8782d5ce6 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 15 Jan 2023 14:20:48 +0100 Subject: [PATCH 419/503] Updated libusb checksum for WIN32 --- cmake/modules/Findlibusb.cmake | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/cmake/modules/Findlibusb.cmake b/cmake/modules/Findlibusb.cmake index 7442c8cc4..fbbda5ba3 100644 --- a/cmake/modules/Findlibusb.cmake +++ b/cmake/modules/Findlibusb.cmake @@ -72,7 +72,7 @@ elseif (WIN32 OR (EXISTS "/etc/debian_version" AND MINGW)) # Windows or MinGW-to message(STATUS "downloading libusb ${LIBUSB_WIN_VERSION}") file(DOWNLOAD https://sourceforge.net/projects/libusb/files/libusb-1.0/libusb-${LIBUSB_WIN_VERSION}/libusb-${LIBUSB_WIN_VERSION}.7z/download - ${LIBUSB_WIN_ARCHIVE_PATH} EXPECTED_MD5 cf3d38d2ff053ef343d10c0b8b0950c2 + ${LIBUSB_WIN_ARCHIVE_PATH} EXPECTED_MD5 aabe177bde869bfad34278335eaf8955 ) endif () From c18293a82e9fa98c34f99f31217959c554197738 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Mon, 13 Feb 2023 23:59:11 +0100 Subject: [PATCH 420/503] Minor fixes - Updated Standards-Version for deb-package - Fix for strcmp(value, "L4") in chipid.c - Minor formatting fixes --- cmake/packaging/deb/control | 2 +- src/stlink-lib/chipid.c | 422 ++++++++++++++++++------------------ 2 files changed, 212 insertions(+), 212 deletions(-) diff --git a/cmake/packaging/deb/control b/cmake/packaging/deb/control index 7c8d13e47..2ed3b6b11 100644 --- a/cmake/packaging/deb/control +++ b/cmake/packaging/deb/control @@ -2,7 +2,7 @@ Source: stlink Priority: optional Maintainer: Nightwalker-87 Build-Depends: cmake (>= 3.10.2), dh-cmake, debhelper (>= 9), libusb-1.0-0-dev (>= 1.0.21), libgtk-3-dev (>= 3.22.30) -Standards-Version: 4.5.0 +Standards-Version: 4.6.2 Rules-Requires-Root: no Section: electronics Homepage: https://github.com/stlink-org/stlink diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index 51a1200ad..075c19c17 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -1,248 +1,248 @@ -#include -#include #include "chipid.h" +#include +#include -#include +#include #include #include -#include #include +#include static struct stlink_chipid_params *devicelist; -void dump_a_chip (struct stlink_chipid_params *dev) { - DLOG("# Device Type: %s\n", dev->dev_type); - DLOG("# Reference Manual: RM%s\n", dev->ref_manual_id); - DLOG("#\n"); - DLOG("chip_id 0x%x\n", dev->chip_id); - DLOG("flash_type %d\n", dev->flash_type); - DLOG("flash_size_reg 0x%x\n", dev->flash_size_reg); - DLOG("flash_pagesize 0x%x\n", dev->flash_pagesize); - DLOG("sram_size 0x%x\n", dev->sram_size); - DLOG("bootrom_base 0x%x\n", dev->bootrom_base); - DLOG("bootrom_size 0x%x\n", dev->bootrom_size); - DLOG("option_base 0x%x\n", dev->option_base); - DLOG("option_size 0x%x\n", dev->option_size); - DLOG("flags %d\n\n", dev->flags); +void dump_a_chip(struct stlink_chipid_params *dev) { + DLOG("# Device Type: %s\n", dev->dev_type); + DLOG("# Reference Manual: RM%s\n", dev->ref_manual_id); + DLOG("#\n"); + DLOG("chip_id 0x%x\n", dev->chip_id); + DLOG("flash_type %d\n", dev->flash_type); + DLOG("flash_size_reg 0x%x\n", dev->flash_size_reg); + DLOG("flash_pagesize 0x%x\n", dev->flash_pagesize); + DLOG("sram_size 0x%x\n", dev->sram_size); + DLOG("bootrom_base 0x%x\n", dev->bootrom_base); + DLOG("bootrom_size 0x%x\n", dev->bootrom_size); + DLOG("option_base 0x%x\n", dev->option_base); + DLOG("option_size 0x%x\n", dev->option_size); + DLOG("flags %d\n\n", dev->flags); } struct stlink_chipid_params *stlink_chipid_get_params(uint32_t chip_id) { - struct stlink_chipid_params *params = NULL; - for (params = devicelist; params != NULL; params = params->next) - if (params->chip_id == chip_id) { - DLOG("detected chip_id parameters\n\n"); - dump_a_chip(params); - break; - } + struct stlink_chipid_params *params = NULL; + for (params = devicelist; params != NULL; params = params->next) + if (params->chip_id == chip_id) { + DLOG("detected chip_id parameters\n\n"); + dump_a_chip(params); + break; + } - return(params); + return (params); } void process_chipfile(char *fname) { - FILE *fp; - char *p, buf[256]; - char word[64], value[64]; - struct stlink_chipid_params *ts; - int nc; - - // fprintf (stderr, "processing chip-id file %s.\n", fname); - fp = fopen(fname, "r"); - - if (!fp) { - perror(fname); - return; - } - - ts = calloc(sizeof(struct stlink_chipid_params), 1); - - while (fgets(buf, sizeof(buf), fp) != NULL) { - - if (strncmp(buf, "#", strlen("#")) == 0) - continue; // ignore comments - - if ((strncmp(buf, "\n", strlen("\n")) == 0) || - (strncmp(buf, " ", strlen(" ")) == 0)) - continue; // ignore empty lines - - sscanf(buf, "%s %s", word, value); - - if (strcmp (word, "dev_type") == 0) { - buf[strlen(buf) - 1] = 0; // chomp newline - sscanf(buf, "%*s %n", &nc); - ts->dev_type = strdup(buf + nc); - } else if (strcmp(word, "ref_manual_id") == 0) { - buf[strlen(buf) - 1] = 0; // chomp newline - sscanf(buf, "%*s %n", &nc); - ts->ref_manual_id = strdup(buf + nc); - } else if (strcmp(word, "chip_id") == 0) { - buf[strlen(buf) - 1] = 0; // chomp newline - sscanf(buf, "%*s %n", &nc); - if (sscanf(value, "%i", &ts->chip_id) < 1) { - fprintf(stderr, "Failed to parse chip-id\n"); - } - } else if (strcmp(word, "flash_type") == 0) { - buf[strlen(buf) - 1] = 0; // chomp newline - sscanf(buf, "%*s %n", &nc); - if (strcmp(value, "F0_F1_F3") == 0) { - ts->flash_type = STM32_FLASH_TYPE_F0_F1_F3; - } else if (strcmp(value, "F1_XL") == 0) { - ts->flash_type = STM32_FLASH_TYPE_F1_XL; - } else if (strcmp(value, "F2_F4") == 0) { - ts->flash_type = STM32_FLASH_TYPE_F2_F4; - } else if (strcmp(value, "F7") == 0) { - ts->flash_type = STM32_FLASH_TYPE_F7; - } else if (strcmp(value, "G0") == 0) { - ts->flash_type = STM32_FLASH_TYPE_G0; - } else if (strcmp(value, "G4") == 0) { - ts->flash_type = STM32_FLASH_TYPE_G4; - } else if (strcmp(value, "H7") == 0) { - ts->flash_type = STM32_FLASH_TYPE_H7; - } else if (strcmp(value, "L0_L1") == 0) { - ts->flash_type = STM32_FLASH_TYPE_L0_L1; - } else if (strcmp(value, "L4_L4P") == 0) { - ts->flash_type = STM32_FLASH_TYPE_L4; - } else if (strcmp(value, "L5_U5") == 0) { - ts->flash_type = STM32_FLASH_TYPE_L5_U5; - } else if (strcmp(value, "WB_WL") == 0) { - ts->flash_type = STM32_FLASH_TYPE_WB_WL; - } else { - ts->flash_type = STM32_FLASH_TYPE_UNKNOWN; - } - } else if (strcmp(word, "flash_size_reg") == 0) { - buf[strlen(buf) - 1] = 0; // chomp newline - sscanf(buf, "%*s %n", &nc); - if (sscanf(value, "%i", &ts->flash_size_reg) < 1) { - fprintf(stderr, "Failed to parse flash size reg\n"); - } - } else if (strcmp(word, "flash_pagesize") == 0) { - buf[strlen(buf) - 1] = 0; // chomp newline - sscanf(buf, "%*s %n", &nc); - if (sscanf(value, "%i", &ts->flash_pagesize) < 1) { - fprintf(stderr, "Failed to parse flash page size\n"); - } - } else if (strcmp(word, "sram_size") == 0) { - buf[strlen(buf) - 1] = 0; // chomp newline - sscanf(buf, "%*s %n", &nc); - if (sscanf(value, "%i", &ts->sram_size) < 1) { - fprintf(stderr, "Failed to parse SRAM size\n"); - } - } else if (strcmp(word, "bootrom_base") == 0) { - buf[strlen(buf) - 1] = 0; // chomp newline - sscanf(buf, "%*s %n", &nc); - if (sscanf(value, "%i", &ts->bootrom_base) < 1) { - fprintf(stderr, "Failed to parse BootROM base\n"); - } - } else if (strcmp(word, "bootrom_size") == 0) { - buf[strlen(buf) - 1] = 0; // chomp newline - sscanf(buf, "%*s %n", &nc); - if (sscanf(value, "%i", &ts->bootrom_size) < 1) { - fprintf(stderr, "Failed to parse BootROM size\n"); - } - } else if (strcmp(word, "option_base") == 0) { - buf[strlen(buf) - 1] = 0; // chomp newline - sscanf(buf, "%*s %n", &nc); - if (sscanf(value, "%i", &ts->option_base) < 1) { - fprintf(stderr, "Failed to parse option base\n"); - } - } else if (strcmp(word, "option_size") == 0) { - buf[strlen(buf) - 1] = 0; // chomp newline - sscanf(buf, "%*s %n", &nc); - if (sscanf(value, "%i", &ts->option_size) < 1) { - fprintf(stderr, "Failed to parse option size\n"); - } - } else if (strcmp(word, "flags") == 0) { - buf[strlen(buf) - 1] = 0; // chomp newline - sscanf(buf, "%*s %n", &nc); - p = strtok (buf, " \t\n"); - - while ((p = strtok (NULL, " \t\n"))) { - if (strcmp(p, "none") == 0) { - // NOP - } else if (strcmp(p, "dualbank") == 0) { - ts->flags |= CHIP_F_HAS_DUAL_BANK; - } else if (strcmp(p, "swo") == 0) { - ts->flags |= CHIP_F_HAS_SWO_TRACING; - } else { - fprintf(stderr, "Unknown flags word in %s: '%s'\n", - fname, p); - } - } - - sscanf(value, "%x", &ts->flags); + FILE *fp; + char *p, buf[256]; + char word[64], value[64]; + struct stlink_chipid_params *ts; + int nc; + + // fprintf (stderr, "processing chip-id file %s.\n", fname); + fp = fopen(fname, "r"); + + if (!fp) { + perror(fname); + return; + } + + ts = calloc(sizeof(struct stlink_chipid_params), 1); + + while (fgets(buf, sizeof(buf), fp) != NULL) { + + if (strncmp(buf, "#", strlen("#")) == 0) + continue; // ignore comments + + if ((strncmp(buf, "\n", strlen("\n")) == 0) || + (strncmp(buf, " ", strlen(" ")) == 0)) + continue; // ignore empty lines + + sscanf(buf, "%s %s", word, value); + + if (strcmp(word, "dev_type") == 0) { + buf[strlen(buf) - 1] = 0; // chomp newline + sscanf(buf, "%*s %n", &nc); + ts->dev_type = strdup(buf + nc); + } else if (strcmp(word, "ref_manual_id") == 0) { + buf[strlen(buf) - 1] = 0; // chomp newline + sscanf(buf, "%*s %n", &nc); + ts->ref_manual_id = strdup(buf + nc); + } else if (strcmp(word, "chip_id") == 0) { + buf[strlen(buf) - 1] = 0; // chomp newline + sscanf(buf, "%*s %n", &nc); + if (sscanf(value, "%i", &ts->chip_id) < 1) { + fprintf(stderr, "Failed to parse chip-id\n"); + } + } else if (strcmp(word, "flash_type") == 0) { + buf[strlen(buf) - 1] = 0; // chomp newline + sscanf(buf, "%*s %n", &nc); + if (strcmp(value, "F0_F1_F3") == 0) { + ts->flash_type = STM32_FLASH_TYPE_F0_F1_F3; + } else if (strcmp(value, "F1_XL") == 0) { + ts->flash_type = STM32_FLASH_TYPE_F1_XL; + } else if (strcmp(value, "F2_F4") == 0) { + ts->flash_type = STM32_FLASH_TYPE_F2_F4; + } else if (strcmp(value, "F7") == 0) { + ts->flash_type = STM32_FLASH_TYPE_F7; + } else if (strcmp(value, "G0") == 0) { + ts->flash_type = STM32_FLASH_TYPE_G0; + } else if (strcmp(value, "G4") == 0) { + ts->flash_type = STM32_FLASH_TYPE_G4; + } else if (strcmp(value, "H7") == 0) { + ts->flash_type = STM32_FLASH_TYPE_H7; + } else if (strcmp(value, "L0_L1") == 0) { + ts->flash_type = STM32_FLASH_TYPE_L0_L1; + } else if (strcmp(value, "L4") == 0) { + ts->flash_type = STM32_FLASH_TYPE_L4; + } else if (strcmp(value, "L5_U5") == 0) { + ts->flash_type = STM32_FLASH_TYPE_L5_U5; + } else if (strcmp(value, "WB_WL") == 0) { + ts->flash_type = STM32_FLASH_TYPE_WB_WL; + } else { + ts->flash_type = STM32_FLASH_TYPE_UNKNOWN; + } + } else if (strcmp(word, "flash_size_reg") == 0) { + buf[strlen(buf) - 1] = 0; // chomp newline + sscanf(buf, "%*s %n", &nc); + if (sscanf(value, "%i", &ts->flash_size_reg) < 1) { + fprintf(stderr, "Failed to parse flash size reg\n"); + } + } else if (strcmp(word, "flash_pagesize") == 0) { + buf[strlen(buf) - 1] = 0; // chomp newline + sscanf(buf, "%*s %n", &nc); + if (sscanf(value, "%i", &ts->flash_pagesize) < 1) { + fprintf(stderr, "Failed to parse flash page size\n"); + } + } else if (strcmp(word, "sram_size") == 0) { + buf[strlen(buf) - 1] = 0; // chomp newline + sscanf(buf, "%*s %n", &nc); + if (sscanf(value, "%i", &ts->sram_size) < 1) { + fprintf(stderr, "Failed to parse SRAM size\n"); + } + } else if (strcmp(word, "bootrom_base") == 0) { + buf[strlen(buf) - 1] = 0; // chomp newline + sscanf(buf, "%*s %n", &nc); + if (sscanf(value, "%i", &ts->bootrom_base) < 1) { + fprintf(stderr, "Failed to parse BootROM base\n"); + } + } else if (strcmp(word, "bootrom_size") == 0) { + buf[strlen(buf) - 1] = 0; // chomp newline + sscanf(buf, "%*s %n", &nc); + if (sscanf(value, "%i", &ts->bootrom_size) < 1) { + fprintf(stderr, "Failed to parse BootROM size\n"); + } + } else if (strcmp(word, "option_base") == 0) { + buf[strlen(buf) - 1] = 0; // chomp newline + sscanf(buf, "%*s %n", &nc); + if (sscanf(value, "%i", &ts->option_base) < 1) { + fprintf(stderr, "Failed to parse option base\n"); + } + } else if (strcmp(word, "option_size") == 0) { + buf[strlen(buf) - 1] = 0; // chomp newline + sscanf(buf, "%*s %n", &nc); + if (sscanf(value, "%i", &ts->option_size) < 1) { + fprintf(stderr, "Failed to parse option size\n"); + } + } else if (strcmp(word, "flags") == 0) { + buf[strlen(buf) - 1] = 0; // chomp newline + sscanf(buf, "%*s %n", &nc); + p = strtok(buf, " \t\n"); + + while ((p = strtok(NULL, " \t\n"))) { + if (strcmp(p, "none") == 0) { + // NOP + } else if (strcmp(p, "dualbank") == 0) { + ts->flags |= CHIP_F_HAS_DUAL_BANK; + } else if (strcmp(p, "swo") == 0) { + ts->flags |= CHIP_F_HAS_SWO_TRACING; } else { - fprintf(stderr, "Unknown keyword in %s: %s\n", fname, word); + fprintf(stderr, "Unknown flags word in %s: '%s'\n", fname, p); } + } + + sscanf(value, "%x", &ts->flags); + } else { + fprintf(stderr, "Unknown keyword in %s: %s\n", fname, word); } - fclose(fp); - ts->next = devicelist; - devicelist = ts; + } + fclose(fp); + ts->next = devicelist; + devicelist = ts; } #if defined(STLINK_HAVE_DIRENT_H) #include void init_chipids(char *dir_to_scan) { - DIR *d; - size_t nl; // namelen - struct dirent *dir; - - if (!dir_to_scan) { - dir_to_scan = "./"; + DIR *d; + size_t nl; // namelen + struct dirent *dir; + + if (!dir_to_scan) { + dir_to_scan = "./"; + } + + devicelist = NULL; + d = opendir(dir_to_scan); + + if (d) { + while ((dir = readdir(d)) != NULL) { + nl = strlen(dir->d_name); + + if (strcmp(dir->d_name + nl - 5, ".chip") == 0) { + char buf[1024]; + sprintf(buf, "%s/%s", dir_to_scan, dir->d_name); + process_chipfile(buf); + } } - devicelist = NULL; - d = opendir(dir_to_scan); - - if (d) { - while ((dir = readdir(d)) != NULL) { - nl = strlen(dir->d_name); - - if (strcmp(dir->d_name + nl - 5, ".chip") == 0) { - char buf[1024]; - sprintf(buf, "%s/%s", dir_to_scan, dir->d_name); - process_chipfile(buf); - } - } - - closedir(d); - } else { - perror (dir_to_scan); - return; - } + closedir(d); + } else { + perror(dir_to_scan); + return; + } } -#endif //STLINK_HAVE_DIRENT_H +#endif // STLINK_HAVE_DIRENT_H #if defined(_WIN32) && !defined(STLINK_HAVE_DIRENT_H) #include #include void init_chipids(char *dir_to_scan) { - HANDLE hFind = INVALID_HANDLE_VALUE; - WIN32_FIND_DATAA ffd; - char filepath[MAX_PATH] = {0}; + HANDLE hFind = INVALID_HANDLE_VALUE; + WIN32_FIND_DATAA ffd; + char filepath[MAX_PATH] = {0}; + StringCchCopyA(filepath, STLINK_ARRAY_SIZE(filepath), dir_to_scan); + + if (FAILED( + StringCchCatA(filepath, STLINK_ARRAY_SIZE(filepath), "\\*.chip"))) { + ELOG("Path to chips's dir too long.\n"); + return; + } + + hFind = FindFirstFileA(filepath, &ffd); + + if (INVALID_HANDLE_VALUE == hFind) { + ELOG("Can't find any chip description file in %s.\n", filepath); + return; + } + + do { + memset(filepath, 0, STLINK_ARRAY_SIZE(filepath)); StringCchCopyA(filepath, STLINK_ARRAY_SIZE(filepath), dir_to_scan); + StringCchCatA(filepath, STLINK_ARRAY_SIZE(filepath), "\\"); + StringCchCatA(filepath, STLINK_ARRAY_SIZE(filepath), ffd.cFileName); + process_chipfile(filepath); + } while (FindNextFileA(hFind, &ffd) != 0); - if (FAILED(StringCchCatA(filepath, STLINK_ARRAY_SIZE(filepath), "\\*.chip"))) { - ELOG("Path to chips's dir too long.\n"); - return; - } - - hFind = FindFirstFileA(filepath, &ffd); - - if (INVALID_HANDLE_VALUE == hFind) { - ELOG("Can't find any chip description file in %s.\n", filepath); - return; - } - - do { - memset(filepath, 0, STLINK_ARRAY_SIZE(filepath)); - StringCchCopyA(filepath, STLINK_ARRAY_SIZE(filepath), dir_to_scan); - StringCchCatA(filepath, STLINK_ARRAY_SIZE(filepath), "\\"); - StringCchCatA(filepath, STLINK_ARRAY_SIZE(filepath), ffd.cFileName); - process_chipfile(filepath); - } while (FindNextFileA(hFind, &ffd) != 0); - - FindClose(hFind); + FindClose(hFind); } -#endif //defined(_WIN32) && !defined(STLINK_HAVE_DIRENT_H) +#endif // defined(_WIN32) && !defined(STLINK_HAVE_DIRENT_H) From 2ff79959f4a8f17c64ca30552e86f35bf89f0fa0 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sat, 18 Mar 2023 21:19:15 +0100 Subject: [PATCH 421/503] Minor fixes & additions - Corrected flash_pagesize for STM32U5 - Updated STM32 core IDs - Added chip-id file for STM32H5 devices --- config/chips/H5xx.chip | 14 ++++++++++ config/chips/U5x5.chip | 2 +- inc/stm32.h | 61 +++++++++++++++++++++-------------------- src/stlink-lib/common.c | 2 +- 4 files changed, 48 insertions(+), 31 deletions(-) create mode 100644 config/chips/H5xx.chip diff --git a/config/chips/H5xx.chip b/config/chips/H5xx.chip new file mode 100644 index 000000000..a1c438999 --- /dev/null +++ b/config/chips/H5xx.chip @@ -0,0 +1,14 @@ +# Chip-ID file for STM32H5xx device +# +dev_type STM32H5xx +ref_manual_id 0481 +chip_id 0x484 // STM32_CHIPID_H5xx +flash_type L5_U5 // ? +flash_size_reg 0x08fff80c +flash_pagesize 0x2000 // 8 KB +sram_size 0xa0000 // 640 KB +bootrom_base 0x0bf80000 +bootrom_size 0x8000 // 32 KB +option_base 0x0 +option_size 0x0 +flags dualbank diff --git a/config/chips/U5x5.chip b/config/chips/U5x5.chip index be19d04af..5f71436ef 100644 --- a/config/chips/U5x5.chip +++ b/config/chips/U5x5.chip @@ -5,7 +5,7 @@ ref_manual_id 0456 chip_id 0x482 // STM32_CHIPID_U5x5 flash_type L5_U5 flash_size_reg 0x0bfa07a0 -flash_pagesize 0x200000 // 2048 KB +flash_pagesize 0x2000 // 8 KB sram_size 0xc4800 // 786 KB bootrom_base 0x0bf90000 bootrom_size 0x10000 // 64 KB diff --git a/inc/stm32.h b/inc/stm32.h index 8557c9ce7..746f4c0f3 100644 --- a/inc/stm32.h +++ b/inc/stm32.h @@ -9,35 +9,37 @@ /* STM32 Cortex-M core ids (CPUTAPID) */ enum stm32_core_id { - STM32_CORE_ID_M0_SWD = 0x0bb11477, // (RM0091 Section 32.5.3) F0 SW-DP - // (RM0444 Section 40.5.3) G0 SW-DP - STM32_CORE_ID_M0P_SWD = 0x0bc11477, // (RM0385 Section 27.5.3) L0 SW-DP - STM32_CORE_ID_M3_r1p1_SWD = 0x1ba01477, // (RM0008 Section 31.8.3) F1 SW-DP - STM32_CORE_ID_M3_r1p1_JTAG = 0x3ba00477, // (RM0008 Section 31.6.3) F1 JTAG - STM32_CORE_ID_M3_r2p0_SWD = 0x2ba01477, // (RM0033 Section 32.8.3) F2 SW-DP - // (RM0038 Section 30.8.3) L1 SW-DP - STM32_CORE_ID_M3_r2p0_JTAG = 0x0ba00477, // (RM0033 Section 32.6.3) F2 JTAG - // (RM0038 Section 30.6.2) L1 JTAG - STM32_CORE_ID_M4_r0p1_SWD = 0x1ba01477, // (RM0316 Section 33.8.3) F3 SW-DP - // (RM0351 Section 48.8.3) L4 SW-DP - // (RM0432 Section 57.8.3) L4+ SW-DP - STM32_CORE_ID_M4_r0p1_JTAG = 0x4ba00477, // (RM0316 Section 33.6.3) F3 JTAG - // (RM0351 Section 48.6.3) L4 JTAG - // (RM0432 Section 57.6.3) L4+ JTAG - STM32_CORE_ID_M4F_r0p1_SWD = 0x2ba01477, // (RM0090 Section 38.8.3) F4 SW-DP - // (RM0090 Section 47.8.3) G4 SW-DP - STM32_CORE_ID_M4F_r0p1_JTAG = 0x4ba00477, // (RM0090 Section 38.6.3) F4 JTAG - // (RM0090 Section 47.6.3) G4 JTAG - STM32_CORE_ID_M7F_SWD = 0x5ba02477, // (RM0385 Section 40.8.3) F7 SW-DP - STM32_CORE_ID_M7F_JTAG = 0x5ba00477, // (RM0385 Section 40.6.3) F7 JTAG - STM32_CORE_ID_M7F_H7_SWD = 0x6ba02477, // (RM0433 Section 60.4.1) H7 SW-DP - STM32_CORE_ID_M7F_H7_JTAG = 0x6ba00477, // (RM0433 Section 60.4.1) H7 JTAG - STM32_CORE_ID_M33_SWD = 0x0be02477, // (RM0438 Section 52.2.10) L5 SW-DP - // (RM0456 Section 65.3.3) U5 SW-DP - STM32_CORE_ID_M33_JTAGD = 0x0be01477, // (RM0438 Section 52.2.10) L5 JTAG-DP - // (RM0456 Section 65.3.3) U5 JTAG-DP - STM32_CORE_ID_M33_JTAG = 0x0ba04477, // (RM0438 Section 52.2.8) L5 JTAG - // (RM0456 Section 56.3.1) U5 JTAG + STM32_CORE_ID_M0_SWD = 0x0bb11477, // (RM0091 Section 32.5.3) F0 SW-DP + // (RM0444 Section 40.5.3) G0 SW-DP + STM32_CORE_ID_M0P_SWD = 0x0bc11477, // (RM0385 Section 27.5.3) L0 SW-DP + STM32_CORE_ID_M3_r1p1_SWD = 0x1ba01477, // (RM0008 Section 31.8.3) F1 SW-DP + STM32_CORE_ID_M3_r1p1_JTAG = 0x3ba00477, // (RM0008 Section 31.6.3) F1 JTAG + STM32_CORE_ID_M3_r2p0_SWD = 0x2ba01477, // (RM0033 Section 32.8.3) F2 SW-DP + // (RM0038 Section 30.8.3) L1 SW-DP + STM32_CORE_ID_M3_r2p0_JTAG = 0x0ba00477, // (RM0033 Section 32.6.3) F2 JTAG + // (RM0038 Section 30.6.2) L1 JTAG + STM32_CORE_ID_M4_r0p1_SWD = 0x1ba01477, // (RM0316 Section 33.8.3) F3 SW-DP + // (RM0351 Section 48.8.3) L4 SW-DP + // (RM0432 Section 57.8.3) L4+ SW-DP + STM32_CORE_ID_M4_r0p1_JTAG = 0x4ba00477, // (RM0316 Section 33.6.3) F3 JTAG + // (RM0351 Section 48.6.3) L4 JTAG + // (RM0432 Section 57.6.3) L4+ JTAG + STM32_CORE_ID_M4F_r0p1_SWD = 0x2ba01477, // (RM0090 Section 38.8.3) F4 SW-DP + // (RM0090 Section 47.8.3) G4 SW-DP + STM32_CORE_ID_M4F_r0p1_JTAG = 0x4ba00477, // (RM0090 Section 38.6.3) F4 JTAG + // (RM0090 Section 47.6.3) G4 JTAG + STM32_CORE_ID_M7F_SWD = 0x5ba02477, // (RM0385 Section 40.8.3) F7 SW-DP + STM32_CORE_ID_M7F_JTAG = 0x5ba00477, // (RM0385 Section 40.6.3) F7 JTAG + STM32_CORE_ID_M7F_M33_SWD = 0x6ba02477, // (RM0481 Section 58.3.3) H5 SW-DP + // (RM0433 Section 60.4.1) H7 SW-DP + STM32_CORE_ID_M7F_M33_JTAG = 0x6ba00477, // (RM0481 Section 58.3.1) H5 JTAG + // (RM0433 Section 60.4.1) H7 SW-DP + STM32_CORE_ID_M33_SWD = 0x0be02477, // (RM0438 Section 52.2.10) L5 SW-DP + // (RM0456 Section 65.3.3) U5 SW-DP + STM32_CORE_ID_M33_JTAGD = 0x0be01477, // (RM0438 Section 52.2.10) L5 JTAG-DP + // (RM0456 Section 65.3.3) U5 JTAG-DP + STM32_CORE_ID_M33_JTAG = 0x0ba04477, // (RM0438 Section 52.2.8) L5 JTAG + // (RM0456 Section 56.3.1) U5 JTAG }; /* STM32 flash types */ @@ -122,6 +124,7 @@ enum stm32_chipids { STM32_CHIPID_H7Ax = 0x480, /* RM0455, p.2863 */ STM32_CHIPID_U5x5 = 0x482, /* RM0456, p.2991 */ STM32_CHIPID_H72x = 0x483, /* RM0468, p.3199 */ + STM32_CHIPID_H5xx = 0x484, /* RM0481, p.3085 */ STM32_CHIPID_WB55 = 0x495, STM32_CHIPID_WLE = 0x497, }; diff --git a/src/stlink-lib/common.c b/src/stlink-lib/common.c index cb037fb2f..65d292235 100644 --- a/src/stlink-lib/common.c +++ b/src/stlink-lib/common.c @@ -140,7 +140,7 @@ int stlink_chip_id(stlink_t *sl, uint32_t *chip_id) { * DBGMCU_IDCODE / DBG_IDCODE name */ - if ((sl->core_id == STM32_CORE_ID_M7F_H7_SWD || sl->core_id == STM32_CORE_ID_M7F_H7_JTAG) && + if ((sl->core_id == STM32_CORE_ID_M7F_M33_SWD || sl->core_id == STM32_CORE_ID_M7F_M33_JTAG) && cpu_id.part == STLINK_REG_CMx_CPUID_PARTNO_CM7) { // STM32H7 chipid in 0x5c001000 (RM0433 pg3189) ret = stlink_read_debug32(sl, 0x5c001000, chip_id); From 186e38a0faac5f546f8b378e625ebe177baf281d Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sat, 18 Mar 2023 21:53:27 +0100 Subject: [PATCH 422/503] Minor fixes & additions - [doc] Update on OS version support - Minor fixes for G0-series from #1293 - [doc] Added core-IDs for WB/WL-series - [doc] Correction for G0/L0-series core-IDs - Set option_size to 128 B for G0-series (#1194) --- config/chips/F401xD_xE.chip | 4 +- config/chips/F446.chip | 2 +- config/chips/G03x_G04x.chip | 2 +- config/chips/G05x_G06x.chip | 6 +-- config/chips/G07x_G08x.chip | 4 +- config/chips/G0Bx_G0Cx.chip | 6 +-- doc/version_support.md | 60 ++++++++++++++--------------- inc/stm32.h | 72 ++++++++++++++++++----------------- src/stlink-lib/common.c | 3 +- src/stlink-lib/option_bytes.c | 9 ++--- 10 files changed, 83 insertions(+), 85 deletions(-) diff --git a/config/chips/F401xD_xE.chip b/config/chips/F401xD_xE.chip index f817175f4..e90f4a78e 100644 --- a/config/chips/F401xD_xE.chip +++ b/config/chips/F401xD_xE.chip @@ -9,6 +9,6 @@ flash_pagesize 0x4000 // 16 KB sram_size 0x18000 // 96 KB bootrom_base 0x1fff0000 bootrom_size 0x7800 // 30 KB -option_base 0x40023C14 -option_size 0x4 +option_base 0x40023C14 // STM32_F4_OPTION_BYTES_BASE +option_size 0x4 // 4 B flags swo diff --git a/config/chips/F446.chip b/config/chips/F446.chip index e4d0bdec2..25f22d9b6 100644 --- a/config/chips/F446.chip +++ b/config/chips/F446.chip @@ -10,5 +10,5 @@ sram_size 0x20000 // 128 KB bootrom_base 0x1fff0000 bootrom_size 0x7800 // 30 KB option_base 0x40023c14 // STM32_F4_OPTION_BYTES_BASE -option_size 0x4 // 4 B +option_size 0x10 // 16 B flags swo diff --git a/config/chips/G03x_G04x.chip b/config/chips/G03x_G04x.chip index a414b52ab..2010940c7 100644 --- a/config/chips/G03x_G04x.chip +++ b/config/chips/G03x_G04x.chip @@ -10,5 +10,5 @@ sram_size 0x2000 // 8 KB bootrom_base 0x1fff0000 bootrom_size 0x2000 // 8 KB option_base 0x1fff7800 // STM32_G0_OPTION_BYTES_BASE -option_size 0x4 // 4 B +option_size 0x80 // 128 B flags none diff --git a/config/chips/G05x_G06x.chip b/config/chips/G05x_G06x.chip index ae074e584..ba556b53a 100644 --- a/config/chips/G05x_G06x.chip +++ b/config/chips/G05x_G06x.chip @@ -1,14 +1,14 @@ # Chip-ID file for STM32G05x / STM32G06x device # dev_type STM32G05x_G06x -ref_manual_id 0444 +ref_manual_id 0444 // also RM454 chip_id 0x456 // STM32_CHIPID_G0_CAT4 flash_type G0 flash_size_reg 0x1fff75e0 flash_pagesize 0x800 // 2 KB -sram_size 0x9000 // 36 KB +sram_size 0x4800 // 18 KB bootrom_base 0x1fff0000 bootrom_size 0x7000 // 28 KB option_base 0x1fff7800 // STM32_G0_OPTION_BYTES_BASE -option_size 0x4 // 4 B +option_size 0x80 // 128 B flags none diff --git a/config/chips/G07x_G08x.chip b/config/chips/G07x_G08x.chip index 82b3992c2..60a6bec7a 100644 --- a/config/chips/G07x_G08x.chip +++ b/config/chips/G07x_G08x.chip @@ -1,7 +1,7 @@ # Chip-ID file for STM32G07x / STM32G08x device # dev_type STM32G07x_G08x -ref_manual_id 0444 +ref_manual_id 0444 // also RM454 chip_id 0x460 // STM32_CHIPID_G0_CAT2 flash_type G0 flash_size_reg 0x1fff75e0 @@ -10,5 +10,5 @@ sram_size 0x9000 // 36 KB bootrom_base 0x1fff0000 bootrom_size 0x7000 // 28 KB option_base 0x1fff7800 // STM32_G0_OPTION_BYTES_BASE -option_size 0x4 // 4 B +option_size 0x80 // 128 B flags none diff --git a/config/chips/G0Bx_G0Cx.chip b/config/chips/G0Bx_G0Cx.chip index f21fd65a0..a9bae1f08 100644 --- a/config/chips/G0Bx_G0Cx.chip +++ b/config/chips/G0Bx_G0Cx.chip @@ -1,14 +1,14 @@ # Chip-ID file for STM32G0Bx / STM32G0Cx device # dev_type STM32G0Bx_G0Cx -ref_manual_id 0444 +ref_manual_id 0444 // also RM454 chip_id 0x467 // STM32_CHIPID_G0_CAT3 flash_type G0 flash_size_reg 0x1fff75e0 flash_pagesize 0x800 // 2 KB -sram_size 0x9000 // 36 KB +sram_size 0x24000 // 144 KB bootrom_base 0x1fff0000 bootrom_size 0x7000 // 28 KB option_base 0x1fff7800 // STM32_G0_OPTION_BYTES_BASE -option_size 0x4 // 4 B +option_size 0x80 // 128 B flags dualbank diff --git a/doc/version_support.md b/doc/version_support.md index 593c86549..e7d8f444b 100644 --- a/doc/version_support.md +++ b/doc/version_support.md @@ -59,43 +59,41 @@ Other Linux-/Unix-based Operating Systems: | Solus [x64] | 1.0.24 | 3.22.1 | 3.24.30 | | | Void Linux | 1.0.24 | 3.22.1 | 3.24.31 | | | Slackware Current | 1.0.24 | 3.21.4 | 3.24.31 | | -| AlmaLinux 8 | 1.0.23 (`libusbx`) | 3.20.2 | 3.**22.30** | | -| Rocky Linux 8 [x64] | 1.0.23 | 3.20.2 | 3.**22.30** | | | Adélie 1.0 | 1.0.23 | 3.**16.4** | 3.24.23 | | ## Unsupported Operating Systems (as of Release v1.7.1) Systems with highlighted versions remain compatible with this toolset. -| Operating System | libusb | cmake | End of
OS-Support | -| ------------------------- | ------------------------------ | ---------- | ---------------------- | -| Fedora 35 [x64] | 1.0.**24** | 3.**21.3** | Dec 2022 | -| CentOS 8 [x64] | 1.0.**23** (`libusbx`) | 3.**20.3** | Dec 2021 | -| Fedora 34 [x64] | 1.0.**24** (`libusbx`) | 3.**19.7** | Jun 2022 | -| Mageia 8 | 1.0.**24** | 3.**19.2** | Aug 2022 | -| Alpine 3.13 | 1.0.**24** | 3.**18.4** | Nov 2022 | -| Ubuntu 21.04 (Hirsute) | 1.0.**24** | 3.**18.4** | Jan 2022 | -| Fedora 33 [x64] | 1.0.**23** (`libusbx`) | 3.**18.3** | Nov 2021 | -| Alpine 3.12 | 1.0.**23** | 3.**17.2** | May 2022 | -| openSUSE Leap 15.3 [x64] | 1.0.**21** | 3.**17.0** | Dec 2022 | -| Fedora 32 [x64] | 1.0.**23** (`libusbx`) | 3.**17.0** | May 2021 | -| openSUSE Leap 15.2 [x64] | 1.0.**21** | 3.**17.0** | Dec 2021 | -| Ubuntu 20.10 (Groovy) | 1.0.**23** | 3.**16.3** | Jul 2021 | -| NetBSD 7.x | 1.0.**22** | 3.**16.1** | Jun 2020 | -| Alpine 3.11 | 1.0.**23** | 3.**15.5** | Nov 2021 | -| FreeBSD 11.x | 1.0.**16-18** (API 0x01000102) | 3.**15.5** | Sep 2021 | -| Alpine 3.10 | 1.0.**22** | 3.**14.5** | May 2021 | -| Fedora 31 [x64] | 1.0.**22**(`libusbx`) | 3.**14.5** | Nov 2020 | -| Mageia 7.1 | 1.0.**22** | 3.**14.3** | Jun 2021 | -| Fedora 30 | 1.0.**22**(`libusbx`) | 3.**14.2** | May 2020 | -| Ubuntu 19.10 (Eoan) | 1.0.**23** | 3.**13.4** | Jul 2020 | -| Alpine 3.9 | 1.0.**22** | 3.**13.0** | Jan 2021 | -| Ubuntu 18.04 LTS (Bionic) | 1.0.**21** | 3.**10.2** | **Apr 2023** | -| openSUSE Leap 15.1 [x64] | 1.0.**21** | 3.**10.2** | Jan 2021 | -| Debian 9 (Stretch) | 1.0.21 | 3.7.2 | Jun 2022 | -| Slackware 14.2 | 1.0.20 | 3.5.2 | | -| OpenMandriva Lx 3.0x | 1.0.20 | 3.4.2 | | -| CentOS 7 [x64] | 1.0.21 (`libusbx`) | 2.8.12.2 | Jun 2024 | +| Operating System | libusb | cmake | End of
OS-Support | +| ---------------------------------------- | ------------------------------ | ---------- | ---------------------- | +| Fedora 35 [x64] | 1.0.**24** | 3.**21.3** | Dec 2022 | +| CentOS / Rocky Linux / AlmaLinux 8 [x64] | 1.0.**23** (`libusbx`) | 3.**20.3** | Dec 2021 | +| Fedora 34 [x64] | 1.0.**24** (`libusbx`) | 3.**19.7** | Jun 2022 | +| Mageia 8 | 1.0.**24** | 3.**19.2** | Aug 2022 | +| Alpine 3.13 | 1.0.**24** | 3.**18.4** | Nov 2022 | +| Ubuntu 21.04 (Hirsute) | 1.0.**24** | 3.**18.4** | Jan 2022 | +| Fedora 33 [x64] | 1.0.**23** (`libusbx`) | 3.**18.3** | Nov 2021 | +| Alpine 3.12 | 1.0.**23** | 3.**17.2** | May 2022 | +| openSUSE Leap 15.3 [x64] | 1.0.**21** | 3.**17.0** | Dec 2022 | +| Fedora 32 [x64] | 1.0.**23** (`libusbx`) | 3.**17.0** | May 2021 | +| openSUSE Leap 15.2 [x64] | 1.0.**21** | 3.**17.0** | Dec 2021 | +| Ubuntu 20.10 (Groovy) | 1.0.**23** | 3.**16.3** | Jul 2021 | +| NetBSD 7.x | 1.0.**22** | 3.**16.1** | Jun 2020 | +| Alpine 3.11 | 1.0.**23** | 3.**15.5** | Nov 2021 | +| FreeBSD 11.x | 1.0.**16-18** (API 0x01000102) | 3.**15.5** | Sep 2021 | +| Alpine 3.10 | 1.0.**22** | 3.**14.5** | May 2021 | +| Fedora 31 [x64] | 1.0.**22**(`libusbx`) | 3.**14.5** | Nov 2020 | +| Mageia 7.1 | 1.0.**22** | 3.**14.3** | Jun 2021 | +| Fedora 30 | 1.0.**22**(`libusbx`) | 3.**14.2** | May 2020 | +| Ubuntu 19.10 (Eoan) | 1.0.**23** | 3.**13.4** | Jul 2020 | +| Alpine 3.9 | 1.0.**22** | 3.**13.0** | Jan 2021 | +| Ubuntu 18.04 LTS (Bionic) | 1.0.**21** | 3.**10.2** | **Apr 2023** | +| openSUSE Leap 15.1 [x64] | 1.0.**21** | 3.**10.2** | Jan 2021 | +| Debian 9 (Stretch) | 1.0.21 | 3.7.2 | Jun 2022 | +| Slackware 14.2 | 1.0.20 | 3.5.2 | | +| OpenMandriva Lx 3.0x | 1.0.20 | 3.4.2 | | +| CentOS / Rocky Linux / AlmaLinux 7 [x64] | 1.0.21 (`libusbx`) | 2.8.12.2 | Jun 2024 | _All other operating systems which are not listed are unsupported._ diff --git a/inc/stm32.h b/inc/stm32.h index 746f4c0f3..92770bd44 100644 --- a/inc/stm32.h +++ b/inc/stm32.h @@ -9,37 +9,41 @@ /* STM32 Cortex-M core ids (CPUTAPID) */ enum stm32_core_id { - STM32_CORE_ID_M0_SWD = 0x0bb11477, // (RM0091 Section 32.5.3) F0 SW-DP - // (RM0444 Section 40.5.3) G0 SW-DP - STM32_CORE_ID_M0P_SWD = 0x0bc11477, // (RM0385 Section 27.5.3) L0 SW-DP - STM32_CORE_ID_M3_r1p1_SWD = 0x1ba01477, // (RM0008 Section 31.8.3) F1 SW-DP - STM32_CORE_ID_M3_r1p1_JTAG = 0x3ba00477, // (RM0008 Section 31.6.3) F1 JTAG - STM32_CORE_ID_M3_r2p0_SWD = 0x2ba01477, // (RM0033 Section 32.8.3) F2 SW-DP - // (RM0038 Section 30.8.3) L1 SW-DP - STM32_CORE_ID_M3_r2p0_JTAG = 0x0ba00477, // (RM0033 Section 32.6.3) F2 JTAG - // (RM0038 Section 30.6.2) L1 JTAG - STM32_CORE_ID_M4_r0p1_SWD = 0x1ba01477, // (RM0316 Section 33.8.3) F3 SW-DP - // (RM0351 Section 48.8.3) L4 SW-DP - // (RM0432 Section 57.8.3) L4+ SW-DP - STM32_CORE_ID_M4_r0p1_JTAG = 0x4ba00477, // (RM0316 Section 33.6.3) F3 JTAG - // (RM0351 Section 48.6.3) L4 JTAG - // (RM0432 Section 57.6.3) L4+ JTAG - STM32_CORE_ID_M4F_r0p1_SWD = 0x2ba01477, // (RM0090 Section 38.8.3) F4 SW-DP - // (RM0090 Section 47.8.3) G4 SW-DP - STM32_CORE_ID_M4F_r0p1_JTAG = 0x4ba00477, // (RM0090 Section 38.6.3) F4 JTAG - // (RM0090 Section 47.6.3) G4 JTAG - STM32_CORE_ID_M7F_SWD = 0x5ba02477, // (RM0385 Section 40.8.3) F7 SW-DP - STM32_CORE_ID_M7F_JTAG = 0x5ba00477, // (RM0385 Section 40.6.3) F7 JTAG - STM32_CORE_ID_M7F_M33_SWD = 0x6ba02477, // (RM0481 Section 58.3.3) H5 SW-DP - // (RM0433 Section 60.4.1) H7 SW-DP - STM32_CORE_ID_M7F_M33_JTAG = 0x6ba00477, // (RM0481 Section 58.3.1) H5 JTAG - // (RM0433 Section 60.4.1) H7 SW-DP - STM32_CORE_ID_M33_SWD = 0x0be02477, // (RM0438 Section 52.2.10) L5 SW-DP - // (RM0456 Section 65.3.3) U5 SW-DP - STM32_CORE_ID_M33_JTAGD = 0x0be01477, // (RM0438 Section 52.2.10) L5 JTAG-DP - // (RM0456 Section 65.3.3) U5 JTAG-DP - STM32_CORE_ID_M33_JTAG = 0x0ba04477, // (RM0438 Section 52.2.8) L5 JTAG - // (RM0456 Section 56.3.1) U5 JTAG + STM32_CORE_ID_M0_SWD = 0x0bb11477, // (RM0091 Section 32.5.3) F0 SW-DP + STM32_CORE_ID_M0P_SWD = 0x0bc11477, // (RM0444 Section 40.5.3) G0 SW-DP + // (RM0377 Section 27.5.3) L0 SW-DP + STM32_CORE_ID_M3_r1p1_SWD = 0x1ba01477, // (RM0008 Section 31.8.3) F1 SW-DP + STM32_CORE_ID_M3_r1p1_JTAG = 0x3ba00477, // (RM0008 Section 31.6.3) F1 JTAG + STM32_CORE_ID_M3_r2p0_SWD = 0x2ba01477, // (RM0033 Section 32.8.3) F2 SW-DP + // (RM0038 Section 30.8.3) L1 SW-DP + STM32_CORE_ID_M3_r2p0_JTAG = 0x0ba00477, // (RM0033 Section 32.6.3) F2 JTAG + // (RM0038 Section 30.6.2) L1 JTAG + STM32_CORE_ID_M4_r0p1_SWD = 0x1ba01477, // (RM0316 Section 33.8.3) F3 SW-DP + // (RM0351 Section 48.8.3) L4 SW-DP + // (RM0432 Section 57.8.3) L4+ SW-DP + STM32_CORE_ID_M4_r0p1_JTAG = 0x4ba00477, // (RM0316 Section 33.6.3) F3 JTAG + // (RM0351 Section 48.6.3) L4 JTAG + // (RM0432 Section 57.6.3) L4+ JTAG + STM32_CORE_ID_M4F_r0p1_SWD = 0x2ba01477, // (RM0090 Section 38.8.3) F4 SW-DP + // (RM0090 Section 47.8.3) G4 SW-DP + STM32_CORE_ID_M4F_r0p1_JTAG = 0x4ba00477, // (RM0090 Section 38.6.3) F4 JTAG + // (RM0090 Section 47.6.3) G4 JTAG + STM32_CORE_ID_M7F_SWD = 0x5ba02477, // (RM0385 Section 40.8.3) F7 SW-DP + // (RM0473 Section 33.4.4) WB SW-DP + // (RM0453 Section 38.4.1) WL SW-DP + STM32_CORE_ID_M7F_JTAG = 0x5ba00477, // (RM0385 Section 40.6.3) F7 JTAG + STM32_CORE_ID_M7F_M33_SWD = 0x6ba02477, // (RM0481 Section 58.3.3) H5 SW-DP + // (RM0433 Section 60.4.1) H7 SW-DP + STM32_CORE_ID_M7F_M33_JTAG = 0x6ba00477, // (RM0481 Section 58.3.1) H5 JTAG + // (RM0433 Section 60.4.1) H7 JTAG + // (RM0473 Section 33.4.1) WB JTAG + // (RM0453 Section 38.3.8) WL JTAG + STM32_CORE_ID_M33_SWD = 0x0be02477, // (RM0438 Section 52.2.10) L5 SW-DP + // (RM0456 Section 65.3.3) U5 SW-DP + STM32_CORE_ID_M33_JTAGD = 0x0be01477, // (RM0438 Section 52.2.10) L5 JTAG-DP + // (RM0456 Section 65.3.3) U5 JTAG-DP + STM32_CORE_ID_M33_JTAG = 0x0ba04477, // (RM0438 Section 52.2.8) L5 JTAG + // (RM0456 Section 56.3.1) U5 JTAG }; /* STM32 flash types */ @@ -108,13 +112,13 @@ enum stm32_chipids { STM32_CHIPID_G0_CAT4 = 0x456, /* G051/G061 */ STM32_CHIPID_L011 = 0x457, STM32_CHIPID_F410 = 0x458, - STM32_CHIPID_G0_CAT2 = 0x460, /* G070/G071/G081 */ + STM32_CHIPID_G0_CAT2 = 0x460, /* G07x/G08x */ STM32_CHIPID_L496x_L4A6x = 0x461, STM32_CHIPID_L45x_L46x = 0x462, STM32_CHIPID_F413 = 0x463, STM32_CHIPID_L41x_L42x = 0x464, - STM32_CHIPID_G0_CAT1 = 0x466, /* G030/G031/G041 */ - STM32_CHIPID_G0_CAT3 = 0x467, /* G0B1/G0C1 */ + STM32_CHIPID_G0_CAT1 = 0x466, /* G03x/G04x */ + STM32_CHIPID_G0_CAT3 = 0x467, /* G0Bx/G0Cx */ STM32_CHIPID_G4_CAT2 = 0x468, /* RM0440, section 46.6.1 "MCU device ID code" */ STM32_CHIPID_G4_CAT3 = 0x469, STM32_CHIPID_L4Rx = 0x470, /* RM0432, p.2247, found on the STM32L4R9I-DISCO board */ diff --git a/src/stlink-lib/common.c b/src/stlink-lib/common.c index 65d292235..ccce342a4 100644 --- a/src/stlink-lib/common.c +++ b/src/stlink-lib/common.c @@ -279,8 +279,7 @@ int stlink_load_device_params(stlink_t *sl) { // medium and low devices have the same chipid. ram size depends on flash // size. STM32F100xx datasheet Doc ID 16455 Table 2 - if (sl->chip_id == STM32_CHIPID_F1_VL_MD_LD && - sl->flash_size < 64 * 1024) { + if (sl->chip_id == STM32_CHIPID_F1_VL_MD_LD && sl->flash_size < 64 * 1024) { sl->sram_size = 0x1000; } diff --git a/src/stlink-lib/option_bytes.c b/src/stlink-lib/option_bytes.c index 2d4898001..32becc5cf 100644 --- a/src/stlink-lib/option_bytes.c +++ b/src/stlink-lib/option_bytes.c @@ -242,8 +242,7 @@ static int stlink_write_option_bytes_f4(stlink_t *sl, stm32_addr_t addr, uint8_t int stlink_read_option_bytes_f7(stlink_t *sl, uint32_t *option_byte) { int err = -1; for (uint32_t counter = 0; counter < (sl->option_size / 4 - 1); counter++) { - err = stlink_read_debug32(sl, sl->option_base + counter * sizeof(uint32_t), - option_byte); + err = stlink_read_debug32(sl, sl->option_base + counter * sizeof(uint32_t), option_byte); if (err == -1) { return err; } else { @@ -272,8 +271,7 @@ static int stlink_write_option_bytes_f7(stlink_t *sl, stm32_addr_t addr, uint8_t // Clear errors clear_flash_error(sl); - ILOG("Asked to write option byte %#10x to %#010x.\n", *(uint32_t *)(base), - addr); + ILOG("Asked to write option byte %#10x to %#010x.\n", *(uint32_t *)(base), addr); write_uint32((unsigned char *)&option_byte, *(uint32_t *)(base)); ILOG("Write %d option bytes %#010x to %#010x!\n", len, option_byte, addr); @@ -306,8 +304,7 @@ static int stlink_write_option_bytes_f7(stlink_t *sl, stm32_addr_t addr, uint8_t ret = check_flash_error(sl); if (!ret) - ILOG("Wrote %d option bytes %#010x to %#010x!\n", len, *(uint32_t *)base, - addr); + ILOG("Wrote %d option bytes %#010x to %#010x!\n", len, *(uint32_t *)base, addr); /* option bytes are reloaded at reset only, no obl. */ From 21633df34ae0bf4a0f9aae3ad5271965160b40f8 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 19 Mar 2023 15:43:37 +0100 Subject: [PATCH 423/503] Minor compilation fixes - Corrected install path for gui executable - Changed directory for chip-id files --- CMakeLists.txt | 4 ++-- src/stlink-gui/CMakeLists.txt | 9 +-------- src/stlink-lib/flashloader.c | 3 +-- 3 files changed, 4 insertions(+), 12 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index 7d8bce8cf..4ce0ee126 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -78,8 +78,8 @@ include(GNUInstallDirs) # Define GNU standard installation directories cmake_host_system_information(RESULT OS_NAME QUERY OS_NAME) message(STATUS "Checking for OS_NAME: ${OS_NAME}") -message(STATUS "set(CMAKE_INSTALL_SHAREDIR /usr/share)") -set(CMAKE_INSTALL_SHAREDIR /usr/share/) +message(STATUS "set(CMAKE_INSTALL_SHAREDIR /usr/local/share)") +set(CMAKE_INSTALL_SHAREDIR /usr/local/share/) ## Set C build flags diff --git a/src/stlink-gui/CMakeLists.txt b/src/stlink-gui/CMakeLists.txt index d2edf0d9f..fb4478bdc 100644 --- a/src/stlink-gui/CMakeLists.txt +++ b/src/stlink-gui/CMakeLists.txt @@ -24,19 +24,12 @@ if (NOT WIN32 AND NOT CMAKE_CROSSCOMPILING) set(GUI_SOURCES gui.c gui.h) - ## stlink-gui-local - add_executable(stlink-gui-local ${GUI_SOURCES}) - file(COPY stlink-gui.ui DESTINATION ${CMAKE_BINARY_DIR}/bin) - set_target_properties(stlink-gui-local PROPERTIES - COMPILE_DEFINITIONS STLINK_UI_DIR="${CMAKE_BINARY_DIR}/bin") - target_link_libraries(stlink-gui-local ${STLINK_LIB_SHARED} ${SSP_LIB} ${GTK3_LDFLAGS}) - ## stlink-gui add_executable(stlink-gui ${GUI_SOURCES}) install(FILES stlink-gui.ui DESTINATION ${CMAKE_INSTALL_SHAREDIR}/${PROJECT_NAME}) set_target_properties(stlink-gui PROPERTIES COMPILE_DEFINITIONS STLINK_UI_DIR="${CMAKE_INSTALL_SHAREDIR}/${PROJECT_NAME}") target_link_libraries(stlink-gui ${STLINK_LIB_SHARED} ${SSP_LIB} ${GTK3_LDFLAGS}) - install(TARGETS stlink-gui DESTINATION ${CMAKE_INSTALL_SHAREDIR}/${PROJECT_NAME}) + install(TARGETS stlink-gui DESTINATION ${CMAKE_BINDIR}) endif () endif () diff --git a/src/stlink-lib/flashloader.c b/src/stlink-lib/flashloader.c index 7164983cd..4adf93a86 100644 --- a/src/stlink-lib/flashloader.c +++ b/src/stlink-lib/flashloader.c @@ -51,8 +51,7 @@ int stm32l1_write_half_pages(stlink_t *sl, stm32_addr_t addr, uint8_t *base, } if (sl->verbose >= 1) { - // show progress; writing procedure is slow and previous errors are - // misleading + // show progress; writing procedure is slow and previous errors are misleading fprintf(stdout, "\r%3u/%u halfpages written", count + 1, num_half_pages); fflush(stdout); } From e93fa5798bfc247faa9ae55e217286f0491d2602 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 19 Mar 2023 18:46:22 +0100 Subject: [PATCH 424/503] Updated CHANGELOG.md --- CHANGELOG.md | 17 +++++++++++------ src/st-flash/flash.c | 7 +++++++ 2 files changed, 18 insertions(+), 6 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index ddd795c37..551a4ba09 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -31,7 +31,7 @@ Features: Updates & changes: - [refactoring] Moved chip-specific parameters into separate files ([#237](https://github.com/stlink-org/stlink/pull/237), [#1129](https://github.com/stlink-org/stlink/pull/1129)) -- [refactoring] General maintenance for code structure ([#903](https://github.com/stlink-org/stlink/pull/903), [#1090](https://github.com/stlink-org/stlink/pull/1090), [#1199](https://github.com/stlink-org/stlink/pull/1199), [#1212](https://github.com/stlink-org/stlink/pull/1212), [#1216](https://github.com/stlink-org/stlink/pull/1216)) +- [refactoring] General maintenance for code structure ([#903](https://github.com/stlink-org/stlink/pull/903), [#1090](https://github.com/stlink-org/stlink/pull/1090), [#1199](https://github.com/stlink-org/stlink/pull/1199), [#1212](https://github.com/stlink-org/stlink/pull/1212), [#1216](https://github.com/stlink-org/stlink/pull/1216), [#1228](https://github.com/stlink-org/stlink/pull/1228)) - Added instructions for bug-reports and feature-requests to contribution guidelines ([#906](https://github.com/stlink-org/stlink/pull/906)) - Added travis CI configuration for macOS 10.14 to maintain capability for 32-bit compilation (commit [#f5ada94](https://github.com/stlink-org/stlink/commit/f5ada9474cdb87ff37de0d4eb9e75622b5870646)) - Updated description of chip id 0x0457 to L01x/L02x ([#1143](https://github.com/stlink-org/stlink/pull/1143), [#1144](https://github.com/stlink-org/stlink/pull/1144)) @@ -44,9 +44,12 @@ Updates & changes: - [refactoring] Sourcefile 'common.c' ([#1218](https://github.com/stlink-org/stlink/pull/1218), [#1220](https://github.com/stlink-org/stlink/pull/1220)) - Set C standard through cmake variables ([#1221](https://github.com/stlink-org/stlink/pull/1221)) - [doc] Added make install to the macOS compiling instructions ([#1259](https://github.com/stlink-org/stlink/pull/1259)) -- [doc] Linux Install from code Documentation improvement ([#1263](https://github.com/stlink-org/stlink/pull/1263), (commit [#43498de](https://github.com/stlink-org/stlink/commit/43498dedf651260ef34197e512d35e3ad7142401)) +- [doc] Linux Install from code Documentation improvement ([#1263](https://github.com/stlink-org/stlink/pull/1263), commit [#43498de](https://github.com/stlink-org/stlink/commit/43498dedf651260ef34197e512d35e3ad7142401)) +- End of support for macOS ([#1269](https://github.com/stlink-org/stlink/pull/1269), [#1296](https://github.com/stlink-org/stlink/pull/1296), commit [#61ff09e](https://github.com/stlink-org/stlink/commit/61ff09e5274d46a46ae58bc4ffe44fe90a887ea6)) +- [doc] Added device ID for GD32F303VET6 ([#1288](https://github.com/stlink-org/stlink/pull/1288)) Fixes: + - cmake: Install shared libraries in proper directories ([#1098](https://github.com/stlink-org/stlink/pull/1098), [#1138](https://github.com/stlink-org/stlink/pull/1138), [#1154](https://github.com/stlink-org/stlink/pull/1154)) - cmake: Install shared libraries in proper directories ([#1142](https://github.com/stlink-org/stlink/pull/1142)) - Fixed clearance of the H7 dual bank flag ([#1146](https://github.com/stlink-org/stlink/pull/1146), [#1147](https://github.com/stlink-org/stlink/pull/1147)) @@ -64,13 +67,15 @@ Fixes: - Define 'SSIZE_MAX' if not defined ([#1183](https://github.com/stlink-org/stlink/pull/1183)) - Fixed compliation for OpenBSD 7.0 ([#1202](https://github.com/stlink-org/stlink/pull/1202)) - Included 'SSIZE_MAX' from 'limits.h' in 'src/common.c' ([#1207](https://github.com/stlink-org/stlink/pull/1207)) -- Fix for libusb_kernel_driver_active & error handling for st.st_size () ([#1210](https://github.com/stlink-org/stlink/pull/1210), [#1211](https://github.com/stlink-org/stlink/pull/1211), [#1214](https://github.com/stlink-org/stlink/pull/1214) +- Fix for libusb_kernel_driver_active & error handling for st.st_size () ([#1210](https://github.com/stlink-org/stlink/pull/1210), [#1211](https://github.com/stlink-org/stlink/pull/1211), [#1214](https://github.com/stlink-org/stlink/pull/1214)) +- General fixes and improvements ([#1240](https://github.com/stlink-org/stlink/pull/1240), [#1242](https://github.com/stlink-org/stlink/pull/1242), [#1290](https://github.com/stlink-org/stlink/pull/1290), [#1291](https://github.com/stlink-org/stlink/pull/1291), [#1295](https://github.com/stlink-org/stlink/pull/1295)) +- Fixes for project compilation ([#1241](https://github.com/stlink-org/stlink/pull/1241), [#1271](https://github.com/stlink-org/stlink/pull/1271), [#1283](https://github.com/stlink-org/stlink/pull/1283), [#1286](https://github.com/stlink-org/stlink/pull/1286),commit [#f93adb9](https://github.com/stlink-org/stlink/commit/f93adb92f2e4ecf05a9361cb723c98693586929d)) - st-trace: Fixed clock issues ([#1248](https://github.com/stlink-org/stlink/pull/1248), [#1251](https://github.com/stlink-org/stlink/pull/1251), [#1252](https://github.com/stlink-org/stlink/pull/1252)) - Fixed compilation with gcc-12 ([#1257](https://github.com/stlink-org/stlink/pull/1257), [#1267](https://github.com/stlink-org/stlink/pull/1267)) - Fixed flash regs addr for STM32L152RET6 in common_flash.c ([#1265](https://github.com/stlink-org/stlink/pull/1265)) - Fixed flash, dbgmcu and rcc registers for STM32L1 ([#1266](https://github.com/stlink-org/stlink/pull/1266)) -- Fixed compilation with gcc-12 ([#1257](https://github.com/stlink-org/stlink/pull/1257), [#1267](https://github.com/stlink-org/stlink/pull/1267)) -- Fixes for project compilation ([#1270](https://github.com/stlink-org/stlink/pull/1270), [#1271](https://github.com/stlink-org/stlink/pull/1271), [#1283](https://github.com/stlink-org/stlink/pull/1283), [#1286](https://github.com/stlink-org/stlink/pull/1286),commit [#f93adb9](https://github.com/stlink-org/stlink/commit/f93adb92f2e4ecf05a9361cb723c98693586929d)) +- Fixed incorrect SRAM size for L496x and L4A6x ([#1268](https://github.com/stlink-org/stlink/pull/1268), commit [#ff81148](https://github.com/stlink-org/stlink/commit/ff8114895a9fc32cae6a9374e58eac6256d68183)) +- Fixed st-trace reconnect on Windows ([#1272](https://github.com/stlink-org/stlink/pull/1272), [#1292](https://github.com/stlink-org/stlink/pull/1292)) - [compilation] Corrected path to stlink/chips subdirectory ([#1276](https://github.com/stlink-org/stlink/pull/1276), [#1279](https://github.com/stlink-org/stlink/pull/1279)) - [compilation] Fixed GUI compilation failure on OpenBSD i386 ([#1284](https://github.com/stlink-org/stlink/pull/1284)) @@ -84,7 +89,7 @@ Features: - Extended set of cmd line arguments for st-info and st-util ([#332](https://github.com/stlink-org/stlink/pull/332), [#990](https://github.com/stlink-org/stlink/pull/990), [#1091](https://github.com/stlink-org/stlink/pull/1091), [#1114](https://github.com/stlink-org/stlink/pull/1114)) - Extended support for STM32H7 & rework of software reset ([#532](https://github.com/stlink-org/stlink/pull/532), [#801](https://github.com/stlink-org/stlink/pull/801), [#868](https://github.com/stlink-org/stlink/pull/868), [#1008](https://github.com/stlink-org/stlink/pull/1008), [#1059](https://github.com/stlink-org/stlink/pull/1059), [#1063](https://github.com/stlink-org/stlink/pull/1063), [#1071](https://github.com/stlink-org/stlink/pull/1071)) -- Added support for STM32H742/743/753 ([#671](https://github.com/stlink-org/stlink/pull/671), [#793](https://github.com/stlink-org/stlink/pull/793), [#823](https://github.com/stlink-org/stlink/pull/823), [#998](https://github.com/stlink-org/stlink/pull/998), [#1052](https://github.com/stlink-org/stlink/pull/1052)) +- Added support for STM32H742/743/753 ([#671](https://github.com/stlink-org/stlink/pull/671), [#793](https://github.com/stlink-org/stlink/pull/793), [#823](https://github.com/stlink-org/stlink/pull/823), [#998](https://github.com/stlink-org/stlink/pull/998), [#1052](https://github.com/stlink-org/stlink/pull/1052), [#1184](https://github.com/stlink-org/stlink/pull/1184)) - Official support for STLINK-V3 programmers (commit [#5e0a502](https://github.com/stlink-org/stlink/commit/5e0a502df812495bfa96fa9116a19f1306152b17), [#820](https://github.com/stlink-org/stlink/pull/820), [#1022](https://github.com/stlink-org/stlink/pull/1022), [#1025](https://github.com/stlink-org/stlink/pull/1025)) - Added preliminary support for STM32L5x2 ([#904](https://github.com/stlink-org/stlink/pull/904), [#999](https://github.com/stlink-org/stlink/pull/999)) - Option bytes on the STM32F767 ZIT6 Nucleo-144 ([#968](https://github.com/stlink-org/stlink/pull/968), [#997](https://github.com/stlink-org/stlink/pull/997)) diff --git a/src/st-flash/flash.c b/src/st-flash/flash.c index 39b31f219..3b25dc214 100644 --- a/src/st-flash/flash.c +++ b/src/st-flash/flash.c @@ -169,7 +169,10 @@ int main(int ac, char** av) { printf("Unknown memory region\n"); goto on_error; } + } else if (o.cmd == FLASH_CMD_ERASE) { + + // erase if (o.size > 0 && o.addr > 0) { err = stlink_erase_flash_section(sl, o.addr, o.size, false); } else { @@ -180,11 +183,15 @@ int main(int ac, char** av) { goto on_error; } printf("Mass erase completed successfully.\n"); + } else if (o.cmd == CMD_RESET) { + + // reset if (stlink_reset(sl, RESET_AUTO)) { printf("Failed to reset device\n"); goto on_error; } + } else { // read From 8af1dcb71e870e3c8f20e28bb123e10808696e55 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Tue, 4 Apr 2023 23:32:51 +0200 Subject: [PATCH 425/503] Minor changes & fixes - Simplified listing of supported devices - Corrected #define STM32L5_PWR_CR1_VOS - Check the return code of stlink_read_debug32 - Fix for flash register reading on L5x2 devices --- doc/devices_boards.md | 207 ---------------------------------- doc/supported devices.md | 59 ++++++++++ inc/stm32.h | 2 +- src/stlink-lib/common.c | 9 ++ src/stlink-lib/common_flash.c | 3 +- 5 files changed, 70 insertions(+), 210 deletions(-) delete mode 100644 doc/devices_boards.md create mode 100644 doc/supported devices.md diff --git a/doc/devices_boards.md b/doc/devices_boards.md deleted file mode 100644 index 13aa0361a..000000000 --- a/doc/devices_boards.md +++ /dev/null @@ -1,207 +0,0 @@ -# MCUs supported by the STlink toolset - -The following devices are supported by the stlink toolset. - -## STM32F0 / ARM Cortex M0 - -| Chip-ID | Product-Code | -| ------- | ------------------- | -| 0x440 | STM32F0**30**x**8** | -| 0x442 | STM32F0**30**x**C** | -| 0x444 | STM32F0**3**xx**4** | -| 0x444 | STM32F0**3**xx**6** | -| 0x445 | STM32F0**4**xxx | -| 0x440 | STM32F0**5**xxx | -| 0x445 | STM32F0**70**x**6** | -| 0x448 | STM32F0**70**x**B** | -| 0x448 | STM32F0**71**xx | -| 0x448 | STM32F0**72**xx | -| 0x442 | STM32F0**9**xxx | - - -## STM32F1 / ARM Cortex M3 - -| Product-Code | Product Line | -| ----------------- | ----------------------- | -| STM32F10**0**yyxx | Value line (V) | -| STM32F10**1**yyxx | Access line (A) | -| STM32F10**2**yyxx | USB Access line (USB-A) | -| STM32F10**3**yyxx | Performance line (P) | -| STM32F10**5**yyxx | Connectivity line (C) | -| STM32F10**7**yyxx | Connectivity line (C) | - -| Chip-ID | Product Line | Code (yy) | V | A | USB-A | P | C | -| ------- | -------------------- | --------- | ---- | ---- | ----- | ---- | -------------- | -| 0x412 | Low-Density | x4 x6 | F100 | F101 | F102 | F103 | | -| 0x410 | Medium Density | x8 xB | | F101 | F102 | F103 | | -| 0x414 | High density | xC xD xE | | F101 | F103 | | | -| 0x418 | STM32F105xx/107xx | x8 xB xC | | | | | F105
F107 | -| 0x420 | Medium density value | x8 xB | F100 | | | | | -| 0x428 | High density Value | xC xD xE | F100 | | | | | -| 0x430 | XL-Density | xF xG | | F101 | | F103 | | - -Tested non-official ST boards [incl. STLINK programmers]: - -- HY-STM32 (STM32F103VETx) [v1, v2] -- DecaWave EVB1000 (STM32F105RCTx) [v1, v2] - -## STM32F2 / ARM Cortex M3 - -| Chip-ID | Product-Code | Product Line | -| ------- | ------------ | ------------- | -| 0x411 | STM32F2yyxx | (all devices) | - -## STM32F1 Clone / ARM Cortex M3 (Core-ID: 0x2ba01477) [may work, but without support!] - -| Product-Code | Chip-ID | STLink
Programmer | Boards | -| ------------- | ------- | ---------------------- | ------------------------------------------------------------------------------------------------------------------------------------ | -| CKS32F103C8Tx | 0x410 | v2 | STM32F103C8T6 clone from China Key Systems (CKS) either as
CKS32-Bluepill or even as "STM32"-Bluepill with _**Fake-Marking !**_ | - -## STM32F3 / ARM Cortex M4F - -| Product-Code | Product Line | -| ----------------- | ------------------------------------------------------------- | -| STM32F3**01**yyxx | Access line (A) | -| STM32F3**02**yyxx | USB & CAN line (USB/CAN) | -| STM32F3**03**yyxx | Performance line (P) | -| STM32F3**34**yy | Digital Power line (DP) | -| STM32F3**73**yy | Precision Measurement line (PM) 64k/16k / 128k/24k / 265k/32k | -| STM32F3**18**yy | General Purpose line (GP) 64k/16k | -| STM32F3**28**yy | General Purpose line (GP) 64k/16k | -| STM32F3**58**yy | General Purpose line (GP) 265k/48k | -| STM32F3**78**yy | Precision Measurement line (PM) 265k/32k | -| STM32F3**98**yy | General Purpose line (GP) 512k/80k | - -| Chip-ID | Product Line | Code (yy) | A | USB/CAN | P | others | -| ------- | ------------ | --------- | ---- | ------- | ---- | -------------- | -| 0x422 | _N/A_ | xB xC | | F302 | F303 | | -| 0x422 | _N/A_ | - | | | | F358 | -| 0x432 | _N/A_ | - | | | | F373
F378 | -| 0x438 | _N/A_ | x4 x6 x8 | | | F303 | | -| 0x438 | _N/A_ | - | | | | F334
F328 | -| 0x439 | _N/A_ | x4 x6 x8 | F301 | F302 | | | -| 0x439 | _N/A_ | - | | | | F318 | -| 0x446 | _N/A_ | xD xE | | F302 | F303 | | -| 0x446 | _N/A_ | - | | | | F398 | - -## STM32F3 Clone / ARM Cortex M4F (Core-ID: 0x2ba01477) [may work, but without support!] - -| Product-Code | Chip-ID | STLINK
Programmer | Boards | -| ------------ | ------- | ---------------------- | ---------------------------------- | -| GD32F303CGT6 | 0x430 | [v2] | STM32F303 clone from GigaDevice GD | -| GD32F303VET6 | 0x414 | [v2] | STM32F303 clone from GigaDevice GD | -| GD32F303VGT6 | 0x430 | [v2] | STM32F303 clone from GigaDevice GD | - -## STM32F4 / ARM Cortex M4F - -| Chip-ID | Product-Code | -| ------- | ------------------- | -| 0x413 | STM32F4**0**xxx | -| 0x413 | STM32F4**1**xxx | -| 0x419 | STM32F4**2**xxx | -| 0x419 | STM32F4**3**xxx | -| 0x423 | STM32F4**01**x**B** | -| 0x423 | STM32F4**01**x**C** | -| 0x433 | STM32F4**01**x**D** | -| 0x433 | STM32F4**01**x**E** | -| 0x458 | STM32F4**10**xx | -| 0x431 | STM32F4**11**xx | -| 0x441 | STM32F4**12**xx | -| 0x421 | STM32F4**46**xx | -| 0x434 | STM32F4**69**xx | -| 0x434 | STM32F4**79**xx | -| 0x463 | STM32F4**13**xx | -| 0x463 | STM32F4**23**xx | - -## STM32F7 / ARM Cortex M7F - -| Chip-ID | Product-Code | -| ------- | --------------- | -| 0x452 | STM32F7**2**xxx | -| 0x452 | STM32F7**3**xxx | -| 0x449 | STM32F7**4**xxx | -| 0x449 | STM32F7**5**xxx | -| 0x451 | STM32F7**6**xxx | -| 0x451 | STM32F7**7**xxx | - -## STM32H7 / ARM Cortex M7F - -| Chip-ID | Product-Code | -| ------- | ------------- | -| 0x450 | STM32H7**4**x | -| 0x450 | STM32H7**5**x | -| 0x480 | STM32H7**A**x | -| 0x480 | STM32H7**B**x | - -## STM32G0 / ARM Cortex M0+ - -| Chip-ID | Product-Code | -| ------- | --------------- | -| 0x466 | STM32G0**3**xxx | -| 0x466 | STM32G0**4**xxx | -| 0x460 | STM32G0**7**xxx | -| 0x460 | STM32G0**8**xxx | - -## STM32G4 / ARM Cortex M4F - -| Chip-ID | Product-Code | -| ------- | --------------- | -| 0x468 | STM32G4**31**xx | -| 0x468 | STM32G4**41**xx | -| 0x469 | STM32G4**7**xxx | -| 0x469 | STM32G4**8**xxx | -| 0x479 | STM32G4**91**xx | - -## STM32L0 / ARM Cortex M0+ - -| Chip-ID | Product-Code | -| ------- | --------------- | -| 0x457 | STM32L0**1**xxx | -| 0x457 | STM32L0**2**xxx | -| 0x425 | STM32L0**31**xx | -| 0x425 | STM32L0**41**xx | -| 0x417 | STM32L0**5**xxx | -| 0x417 | STM32L0**6**xxx | -| 0x447 | STM32L0**7**xxx | -| 0x447 | STM32L0**8**xxx | - -## STM32L1 / ARM Cortex M3 - -| Chip-ID | Product-Code | -| ------- | ---------------- | -| 0x416 | STM32L1xxx**6** | -| 0x416 | STM32L1xxx**8** | -| 0x416 | STM32L1xxx**B** | -| 0x429 | STM32L1xxx**6A** | -| 0x429 | STM32L1xxx**8A** | -| 0x429 | STM32L1xxx**BA** | -| 0x427 | STM32L1xxx**C** | -| 0x436 | STM32L1xxx**D** | -| 0x437 | STM32L1xxx**E** | - -## STM32L4 / ARM Cortex M4F - -| Chip-ID | Product-Code | -| ------- | --------------- | -| 0x464 | STM32L4**12**xx | -| 0x464 | STM32L4**22**xx | -| 0x435 | STM32L4**3**xxx | -| 0x435 | STM32L4**4**xxx | -| 0x462 | STM32L4**5**xxx | -| 0x462 | STM32L4**6**xxx | -| 0x415 | STM32L4**7**xxx | -| 0x415 | STM32L4**8**xxx | -| 0x461 | STM32L4**96**xx | -| 0x461 | STM32L4**A6**xx | -| 0x470 | STM32L4**R**xx | -| 0x470 | STM32L4**S**xx | -| 0x471 | STM32L4**P5**xx | -| 0x471 | STM32L4**Q5**xx | - -## STM32W / ARM Cortex M3 - -| Chip-ID | Product-Code | -| ------- | --------------- | -| 0x495 | STM32WB**50**xx | -| 0x495 | STM32WB**55**xx | -| 0x497 | STM32WLE**5**xx | diff --git a/doc/supported devices.md b/doc/supported devices.md new file mode 100644 index 000000000..2e96dcd39 --- /dev/null +++ b/doc/supported devices.md @@ -0,0 +1,59 @@ +# MCUs supported by the STlink toolset + +A list of devices supported by the stlink toolset can be found in */inc/stm32.h*. +More commonly these are: + +| Product-Family | ARM Cortex Core | Product Line | +| -------------- | --------------- | ---------------------------------------------------------- | +| STM32F0 | M0 | | +| STM32G0 | M0+ | | +| STM32L0 | M0+ | | +| STM32F10**0** | M3 | Value line | +| STM32F10**1** | M3 | Access line | +| STM32F10**2** | M3 | USB Access line | +| STM32F10**3** | M3 | Performance line | +| STM32F10**5** | M3 | Connectivity line | +| STM32F10**7** | M3 | Connectivity line | +| STM32L1 | M3 | | +| STM32F2 | M3 | | +| STM32F3**01** | M4F | Access line | +| STM32F3**02** | M4F | USB & CAN line | +| STM32F3**03** | M4F | Performance line | +| STM32F3**34** | M4F | Digital Power line | +| STM32F3**73** | M4F | Precision Measurement line (64k/16k / 128k/24k / 265k/32k) | +| STM32F3**18** | M4F | General Purpose line (64k/16k) | +| STM32F3**28** | M4F | General Purpose line (64k/16k) | +| STM32F3**58** | M4F | General Purpose line (265k/48k) | +| STM32F3**78** | M4F | Precision Measurement line (265k/32k) | +| STM32F3**98** | M4F | General Purpose line (512k/80k) | +| STM32F4 | M4F | | +| STM32G4 | M4F | | +| STM32L4 | M4F | | +| STM32F7 | M4F | | +| STM32H7 | M4F | | +| STM32WB | M4F | | +| STM32WL | M4 | | + + +# Chinese Clone-Chips [may work, but without support!] + +## STM32F1 Clone / ARM Cortex M3 (Core-ID: 0x2ba01477) (mostly on Bluepill-Boards) + +**(!) Attention:** Some MCUs may come with with _**Fake-STM32-Marking !**_ + +**(!) Attention:** The Core-ID of these MCUs is in conflict with the one of the original STM32F1-devices. + +| Product-Code | Chip-ID | Comment | +| ------------- | ------- | ------------------------------------------------------------------------- | +| CKS32F103C8T6 | 0x410 | STM32F103C8T6 clone from China Key Systems (CKS) | +| CH32F103C8T6 | 0x410 | STM32F103C8T6 clone from Nanjing Qinheng Microelectronics Co., Ltd. (WCH) | + +## STM32F3 Clone / ARM Cortex M4F (Core-ID: 0x2ba01477) + +**(!) Attention:** The Chip-IDs of these MCUs are in conflict with such of original STM32F1-devices. + +| Product-Code | Chip-ID | Comment | +| ------------ | ------- | ------------------------------------ | +| GD32F303VET6 | 0x414 | STM32F303 clone from GigaDevice (GD) | +| GD32F303CGT6 | 0x430 | STM32F303 clone from GigaDevice (GD) | +| GD32F303VGT6 | 0x430 | STM32F303 clone from GigaDevice (GD) | diff --git a/inc/stm32.h b/inc/stm32.h index 92770bd44..d3c4e5512 100644 --- a/inc/stm32.h +++ b/inc/stm32.h @@ -215,6 +215,6 @@ enum stm32_chipids { #define STM32WB_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN #define STM32L5_PWR_CR1 0x40007000 // RM0438, p. 93,324 -#define STM32L5_PWR_CR1_VOS 8 +#define STM32L5_PWR_CR1_VOS 9 #endif // STM32_H diff --git a/src/stlink-lib/common.c b/src/stlink-lib/common.c index ccce342a4..e7c2392c1 100644 --- a/src/stlink-lib/common.c +++ b/src/stlink-lib/common.c @@ -292,6 +292,15 @@ int stlink_load_device_params(stlink_t *sl) { } } + if (sl->chip_id == STM32_CHIPID_L5x2xx) { + uint32_t flash_optr; + stlink_read_debug32(sl, STM32L5_FLASH_OPTR, &flash_optr); + + if (sl->flash_size == 512*1024 && (flash_optr & (1 << 22)) != 0) { + sl->flash_pgsz = 0x800; + } + } + // H7 devices with small flash has one bank if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK && sl->flash_type == STM32_FLASH_TYPE_H7) { diff --git a/src/stlink-lib/common_flash.c b/src/stlink-lib/common_flash.c index e84b307eb..000f9279d 100644 --- a/src/stlink-lib/common_flash.c +++ b/src/stlink-lib/common_flash.c @@ -441,8 +441,7 @@ static void unlock_flash(stlink_t *sl) { // Set voltage scaling to range 0 to perform flash operations (RM0438 p. 183) uint32_t mask = (0b11 << STM32L5_PWR_CR1_VOS); uint32_t val; - stlink_read_debug32(sl, STM32L5_PWR_CR1, &val); - if ((val & mask) > (1 << STM32L5_PWR_CR1_VOS)) { + if (!stlink_read_debug32(sl, STM32L5_PWR_CR1, &val) && (val & mask) > (1 << STM32L5_PWR_CR1_VOS)) { val &= ~mask; stlink_write_debug32(sl, STM32L5_PWR_CR1, val); } From 5946076723d77f4283b7e5483c74d66c12f43c76 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Tue, 4 Apr 2023 23:54:56 +0200 Subject: [PATCH 426/503] General maintenance - Updated pkg-version requirements - Updated version_support.md - Removed Ubuntu 18.04 from GH workflow --- .github/workflows/c-cpp.yml | 90 ------------------------------ cmake/packaging/cpack_config.cmake | 2 +- cmake/packaging/deb/control | 2 +- doc/version_support.md | 12 ++-- 4 files changed, 8 insertions(+), 98 deletions(-) diff --git a/.github/workflows/c-cpp.yml b/.github/workflows/c-cpp.yml index fe07c6e44..72163fdf7 100644 --- a/.github/workflows/c-cpp.yml +++ b/.github/workflows/c-cpp.yml @@ -9,96 +9,6 @@ on: jobs: # Linux - job_linux_18_04_64_gcc: - name: ubuntu-18.04 gcc - runs-on: ubuntu-18.04 - steps: - - uses: actions/checkout@v2 - - name: install dependencies - run: sudo apt update && sudo apt-get install gcc-8 libusb-1.0.0-dev libgtk-3-dev rpm - - name: make debug - run: sudo make clean && make debug - - name: make test - run: sudo make clean && make test - - name: make release - run: sudo make clean && make release - - name: sudo make install - run: sudo make clean && sudo make install - - name: sudo make package - run: sudo make package - - name: sudo make uninstall - run: sudo make uninstall && sudo make clean - - job_linux_18_04_32_gcc: - name: ubuntu-18.04 gcc 32-bit - runs-on: ubuntu-18.04 - steps: - - uses: actions/checkout@v2 - - name: install dependencies - run: sudo apt update && sudo apt-get install gcc-8 libusb-1.0.0-dev libgtk-3-dev rpm - - name: Set compiler flags - run: | - CFLAGS="$CFLAGS -m32" - CXXFLAGS="$CXXFLAGS -m32" - LDFLAGS="$LDFLAGS -m32" - - name: make debug - run: sudo make clean && make debug - - name: make test - run: sudo make clean && make test - - name: make release - run: sudo make clean && make release - - name: sudo make install - run: sudo make clean && sudo make install - - name: sudo make package - run: sudo make package - - name: sudo make uninstall - run: sudo make uninstall && sudo make clean - - job_linux_18_04_64_clang: - name: ubuntu-18.04 clang - runs-on: ubuntu-18.04 - steps: - - uses: actions/checkout@v2 - - name: install dependencies - run: sudo apt update && sudo apt-get install clang-10 libusb-1.0.0-dev libgtk-3-dev rpm - - name: make debug - run: sudo make clean && make debug - - name: make test - run: sudo make clean && make test - - name: make release - run: sudo make clean && make release - - name: sudo make install - run: sudo make clean && sudo make install - - name: sudo make package - run: sudo make package - - name: sudo make uninstall - run: sudo make uninstall && sudo make clean - - job_linux_18_04_32_clang: - name: ubuntu-18.04 clang 32-bit - runs-on: ubuntu-18.04 - steps: - - uses: actions/checkout@v2 - - name: Install dependencies - run: sudo apt update && sudo apt-get install clang-10 libusb-1.0.0-dev libgtk-3-dev rpm - - name: Set compiler flags - run: | - CFLAGS="$CFLAGS -m32" - CXXFLAGS="$CXXFLAGS -m32" - LDFLAGS="$LDFLAGS -m32" - - name: make debug - run: sudo make clean && make debug - - name: make test - run: sudo make clean && make test - - name: make release - run: sudo make clean && make release - - name: sudo make install - run: sudo make clean && sudo make install - - name: sudo make package - run: sudo make package - - name: sudo make uninstall - run: sudo make uninstall && sudo make clean - job_linux_20_04_64_gcc: name: ubuntu-20.04 gcc runs-on: ubuntu-20.04 diff --git a/cmake/packaging/cpack_config.cmake b/cmake/packaging/cpack_config.cmake index 55a859189..57d4803d7 100644 --- a/cmake/packaging/cpack_config.cmake +++ b/cmake/packaging/cpack_config.cmake @@ -48,7 +48,7 @@ elseif (EXISTS "/etc/debian_version" AND NOT EXISTS WIN32) # Package-build is av set(CPACK_DEBIAN_PACKAGE_RELEASE "1") # CPACK_DEBIAN_PACKAGE_ARCHITECTURE --> Default: Output of dpkg --print-architecture - set(CPACK_DEBIAN_PACKAGE_DEPENDS "pkg-config, build-essential, debhelper (>=9), cmake (>= 3.10.2), libusb-1.0-0-dev (>= 1.0.21)") + set(CPACK_DEBIAN_PACKAGE_DEPENDS "pkg-config, build-essential, debhelper (>=9), cmake (>= 3.13.0), libusb-1.0-0-dev (>= 1.0.22)") set(CPACK_DEBIAN_PACKAGE_MAINTAINER "Nightwalker-87 ") # CPACK_DEBIAN_PACKAGE_DESCRIPTION --> Default: CPACK_DEBIAN_PACKAGE_DESCRIPTION (as it is set) # CPACK_DEBIAN_PACKAGE_SECTION --> Default: “devel” diff --git a/cmake/packaging/deb/control b/cmake/packaging/deb/control index 2ed3b6b11..7c2ab8fe7 100644 --- a/cmake/packaging/deb/control +++ b/cmake/packaging/deb/control @@ -1,7 +1,7 @@ Source: stlink Priority: optional Maintainer: Nightwalker-87 -Build-Depends: cmake (>= 3.10.2), dh-cmake, debhelper (>= 9), libusb-1.0-0-dev (>= 1.0.21), libgtk-3-dev (>= 3.22.30) +Build-Depends: cmake (>= 3.13.0), dh-cmake, debhelper (>= 9), libusb-1.0-0-dev (>= 1.0.22), libgtk-3-dev (>= 3.22.30) Standards-Version: 4.6.2 Rules-Requires-Root: no Section: electronics diff --git a/doc/version_support.md b/doc/version_support.md index e7d8f444b..43924e502 100644 --- a/doc/version_support.md +++ b/doc/version_support.md @@ -1,10 +1,10 @@ -_Source:_ [pkgs.org](https://pkgs.org/search) - libusb, cmake, gtk, libgtk) (as of Jan 2022) +_Source:_ [pkgs.org](https://pkgs.org/search) - libusb, cmake, gtk, libgtk (as of Apr 2023) ## Supported Operating Systems ### Microsoft Windows -On Windows users should ensure that cmake **3.10.2** or any later version is installed.
+On Windows users should ensure that cmake **3.13.0** or any later version is installed.
Up on compiling c-make will **automatically** download and install the latest compatible version of `libusb`. - Windows 10 @@ -61,7 +61,7 @@ Other Linux-/Unix-based Operating Systems: | Slackware Current | 1.0.24 | 3.21.4 | 3.24.31 | | | Adélie 1.0 | 1.0.23 | 3.**16.4** | 3.24.23 | | -## Unsupported Operating Systems (as of Release v1.7.1) +## Unsupported Operating Systems (as of Release v1.8.0) Systems with highlighted versions remain compatible with this toolset. @@ -77,7 +77,7 @@ Systems with highlighted versions remain compatible with this toolset. | Alpine 3.12 | 1.0.**23** | 3.**17.2** | May 2022 | | openSUSE Leap 15.3 [x64] | 1.0.**21** | 3.**17.0** | Dec 2022 | | Fedora 32 [x64] | 1.0.**23** (`libusbx`) | 3.**17.0** | May 2021 | -| openSUSE Leap 15.2 [x64] | 1.0.**21** | 3.**17.0** | Dec 2021 | +| openSUSE Leap 15.2 [x64] | 1.0.21 | 3.**17.0** | Dec 2021 | | Ubuntu 20.10 (Groovy) | 1.0.**23** | 3.**16.3** | Jul 2021 | | NetBSD 7.x | 1.0.**22** | 3.**16.1** | Jun 2020 | | Alpine 3.11 | 1.0.**23** | 3.**15.5** | Nov 2021 | @@ -88,8 +88,8 @@ Systems with highlighted versions remain compatible with this toolset. | Fedora 30 | 1.0.**22**(`libusbx`) | 3.**14.2** | May 2020 | | Ubuntu 19.10 (Eoan) | 1.0.**23** | 3.**13.4** | Jul 2020 | | Alpine 3.9 | 1.0.**22** | 3.**13.0** | Jan 2021 | -| Ubuntu 18.04 LTS (Bionic) | 1.0.**21** | 3.**10.2** | **Apr 2023** | -| openSUSE Leap 15.1 [x64] | 1.0.**21** | 3.**10.2** | Jan 2021 | +| Ubuntu 18.04 LTS (Bionic) | 1.0.21 | 3.10.2 | Apr 2023 | +| openSUSE Leap 15.1 [x64] | 1.0.21 | 3.10.2 | Jan 2021 | | Debian 9 (Stretch) | 1.0.21 | 3.7.2 | Jun 2022 | | Slackware 14.2 | 1.0.20 | 3.5.2 | | | OpenMandriva Lx 3.0x | 1.0.20 | 3.4.2 | | From 982408e6ee4504b9eac3e679fc94e2d6c95e02e4 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Wed, 5 Apr 2023 21:33:49 +0200 Subject: [PATCH 427/503] Fixes regarding version support - Updated version_support.md - Updated version requirements for libusb --- config/chips/{L5x5.chip => L5x5xx.chip} | 0 doc/version_support.md | 3 ++- src/stlink-lib/libusb_settings.h | 4 ++-- 3 files changed, 4 insertions(+), 3 deletions(-) rename config/chips/{L5x5.chip => L5x5xx.chip} (100%) diff --git a/config/chips/L5x5.chip b/config/chips/L5x5xx.chip similarity index 100% rename from config/chips/L5x5.chip rename to config/chips/L5x5xx.chip diff --git a/doc/version_support.md b/doc/version_support.md index 43924e502..358e65fb9 100644 --- a/doc/version_support.md +++ b/doc/version_support.md @@ -21,6 +21,7 @@ Maintained versions of: - Arch Linux - FreeBSD - NetBSD +- OpenBSD Other Linux-/Unix-based Operating Systems: @@ -75,7 +76,7 @@ Systems with highlighted versions remain compatible with this toolset. | Ubuntu 21.04 (Hirsute) | 1.0.**24** | 3.**18.4** | Jan 2022 | | Fedora 33 [x64] | 1.0.**23** (`libusbx`) | 3.**18.3** | Nov 2021 | | Alpine 3.12 | 1.0.**23** | 3.**17.2** | May 2022 | -| openSUSE Leap 15.3 [x64] | 1.0.**21** | 3.**17.0** | Dec 2022 | +| openSUSE Leap 15.3 [x64] | 1.0.21 | 3.**17.0** | Dec 2022 | | Fedora 32 [x64] | 1.0.**23** (`libusbx`) | 3.**17.0** | May 2021 | | openSUSE Leap 15.2 [x64] | 1.0.21 | 3.**17.0** | Dec 2021 | | Ubuntu 20.10 (Groovy) | 1.0.**23** | 3.**16.3** | Jul 2021 | diff --git a/src/stlink-lib/libusb_settings.h b/src/stlink-lib/libusb_settings.h index ee690e0b1..3777f720b 100644 --- a/src/stlink-lib/libusb_settings.h +++ b/src/stlink-lib/libusb_settings.h @@ -33,9 +33,9 @@ #if defined (__FreeBSD__) #define MINIMAL_API_VERSION 0x01000102 // v1.0.16 #elif defined (__OpenBSD__) - #define MINIMAL_API_VERSION 0x01000105 // v1.0.21 + #define MINIMAL_API_VERSION 0x01000106 // v1.0.22 #elif defined (__linux__) - #define MINIMAL_API_VERSION 0x01000105 // v1.0.21 + #define MINIMAL_API_VERSION 0x01000106 // v1.0.22 #elif defined (_WIN32) #define MINIMAL_API_VERSION 0x01000109 // v1.0.25 #endif From 1d301a5498433900250fe2a8c0e10dfb7f44d7a4 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Fri, 7 Apr 2023 23:33:28 +0200 Subject: [PATCH 428/503] Fix for option byte read (Closes #1156) --- src/st-flash/flash.c | 38 ++++++++++++++++++++++------------- src/st-util/semihosting.c | 9 +++++---- src/stlink-lib/common.c | 15 ++++++++------ src/stlink-lib/option_bytes.c | 3 --- 4 files changed, 38 insertions(+), 27 deletions(-) diff --git a/src/st-flash/flash.c b/src/st-flash/flash.c index 3b25dc214..d7d17f66f 100644 --- a/src/st-flash/flash.c +++ b/src/st-flash/flash.c @@ -1,17 +1,22 @@ /* Simple wrapper around the stlink_flash_write function */ -// TODO - this should be done as just a simple flag to the st-util command line... - -#include #include #include #include + +#include +#include #include +#include #include #include + +#include +#include +#include + #include "flash.h" -#include "option_bytes.h" static stlink_t *connected_stlink = NULL; @@ -215,20 +220,25 @@ int main(int ac, char** av) { (unsigned)remaining_option_length, sl->option_base); - if (NULL != o.filename) { - if (0 == o.size) { - o.size = sl->option_size; + uint32_t option_byte = 0; + err = stlink_read_option_bytes32(sl, &option_byte); + if (err == -1) { + printf("could not read option bytes (%d)\n", err); + goto on_error; + } else if (NULL != o.filename) { + int fd = open(o.filename, O_RDWR | O_TRUNC | O_CREAT | O_BINARY, 00700); + if (fd == -1) { + fprintf(stderr, "open(%s) == -1\n", o.filename); + goto on_error; } - err = stlink_fread(sl, o.filename, o.format == FLASH_FORMAT_IHEX, sl->option_base, o.size); - } else { - uint32_t option_byte = 0; - err = stlink_read_option_bytes32(sl, &option_byte); + err = (uint32_t)write(fd, &option_byte, 4); if (err == -1) { - printf("could not read option bytes (%d)\n", err); + printf("could not write buffer to file (%d)\n", err); goto on_error; - } else { - printf("%08x\n", option_byte); } + close(fd); + } else { + printf("%08x\n", option_byte); } } else if (o.area == FLASH_OPTION_BYTES_BOOT_ADD) { uint32_t option_byte = 0; diff --git a/src/st-util/semihosting.c b/src/st-util/semihosting.c index 32169c812..f603f6224 100644 --- a/src/st-util/semihosting.c +++ b/src/st-util/semihosting.c @@ -1,11 +1,13 @@ #include +#include #include + +#include #include #include -#include -#include #include + #include #include "semihosting.h" @@ -256,8 +258,7 @@ int do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { return(-1); } - DLOG("Semihosting: write(%d, target_addr:0x%08x, %u)\n", fd, buffer_address, - buffer_len); + DLOG("Semihosting: write(%d, target_addr:0x%08x, %u)\n", fd, buffer_address, buffer_len); *ret = (uint32_t)write(fd, buffer, buffer_len); saved_errno = errno; diff --git a/src/stlink-lib/common.c b/src/stlink-lib/common.c index e7c2392c1..fac97278e 100644 --- a/src/stlink-lib/common.c +++ b/src/stlink-lib/common.c @@ -1,18 +1,21 @@ -#include +#include +#include +#include + #include +#include #include #include #include -#include -#include -#include -#include + #include #include -#include "common_flash.h" #include "calculate.h" +#include "common_flash.h" #include "map_file.h" +#include "md5.h" + #include "common.h" #ifndef O_BINARY diff --git a/src/stlink-lib/option_bytes.c b/src/stlink-lib/option_bytes.c index 32becc5cf..9cbdd097b 100644 --- a/src/stlink-lib/option_bytes.c +++ b/src/stlink-lib/option_bytes.c @@ -1007,11 +1007,8 @@ int stlink_read_option_bytes32(stlink_t *sl, uint32_t *option_byte) { case STM32_CHIPID_F76xxx: return stlink_read_option_bytes_f7(sl, option_byte); case STM32_CHIPID_G0_CAT1: - return stlink_read_option_bytes_gx(sl, option_byte); case STM32_CHIPID_G0_CAT2: - return stlink_read_option_bytes_gx(sl, option_byte); case STM32_CHIPID_G4_CAT2: - return stlink_read_option_bytes_gx(sl, option_byte); case STM32_CHIPID_G4_CAT3: return stlink_read_option_bytes_gx(sl, option_byte); default: From 1745bf5193c4d3186d4f6fde59cc86e9bad6e61b Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sat, 8 Apr 2023 02:16:48 +0200 Subject: [PATCH 429/503] [doc] Human-readable flash_type in chip-id files (Closes #1155) --- src/stlink-lib/chipid.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index 075c19c17..3d122a02e 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -83,6 +83,7 @@ void process_chipfile(char *fname) { } else if (strcmp(word, "flash_type") == 0) { buf[strlen(buf) - 1] = 0; // chomp newline sscanf(buf, "%*s %n", &nc); + // Match human readable flash_type with enum stm32_flash_type { }. if (strcmp(value, "F0_F1_F3") == 0) { ts->flash_type = STM32_FLASH_TYPE_F0_F1_F3; } else if (strcmp(value, "F1_XL") == 0) { From 39f306feaa932729c06a3f546721f3659886f46c Mon Sep 17 00:00:00 2001 From: Nicolas signed-log FORMICHELLA Date: Sat, 15 Apr 2023 08:02:19 +0200 Subject: [PATCH 430/503] Fix broken doc link --- doc/tutorial.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/doc/tutorial.md b/doc/tutorial.md index e694bf8d0..7e87a7bd9 100644 --- a/doc/tutorial.md +++ b/doc/tutorial.md @@ -81,7 +81,7 @@ SUBSYSTEMS=="usb", ATTRS{idVendor}=="0483", ATTRS{idProduct}=="374b", \ and the `idVendor` of `0483` and `idProduct` of `374b` matches the vendor id from the `lsusb` output. -Make sure that you have all 3 files from here: https://github.com/stlink-org/stlink/tree/master/etc/udev/rules.d in your `/etc/udev/rules.d` directory. After copying new files or editing existing files in `/etc/udev/ruled.d` you should run the following: +Make sure that you have all 3 files from [/config/udev/rules.d](https://github.com/stlink-org/stlink/tree/master/config/udev/rules.d) in your `/etc/udev/rules.d` directory. After copying new files or editing existing files in `/etc/udev/ruled.d` you should run the following: ``` sudo udevadm control --reload-rules From 0a5cad7ee8e6950f8816b654b41d6bbaa96f6846 Mon Sep 17 00:00:00 2001 From: Mingjie Shen Date: Sat, 22 Apr 2023 00:03:54 -0400 Subject: [PATCH 431/503] Fix unbounded write of sscanf Format string "%s" that does not control the length of data written may overflow. --- src/stlink-lib/chipid.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index 3d122a02e..44d93fedd 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -64,7 +64,7 @@ void process_chipfile(char *fname) { (strncmp(buf, " ", strlen(" ")) == 0)) continue; // ignore empty lines - sscanf(buf, "%s %s", word, value); + sscanf(buf, "%63s %63s", word, value); if (strcmp(word, "dev_type") == 0) { buf[strlen(buf) - 1] = 0; // chomp newline From 98902c271ef20564e95b73cf8e0ee4a8600a8bd1 Mon Sep 17 00:00:00 2001 From: Mingjie Shen Date: Sat, 22 Apr 2023 00:53:29 -0400 Subject: [PATCH 432/503] Add null check for return value of stlink_chipid_get_params() Pass a null pointer to "%s" is undefined behaviour. --- src/st-trace/trace.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/st-trace/trace.c b/src/st-trace/trace.c index 20e04c080..8c6e3c62b 100644 --- a/src/st-trace/trace.c +++ b/src/st-trace/trace.c @@ -591,7 +591,8 @@ int main(int argc, char **argv) { if (!(stlink->chip_flags & CHIP_F_HAS_SWO_TRACING)) { const struct stlink_chipid_params *params = stlink_chipid_get_params(stlink->chip_id); - ELOG("We do not support SWO output for device '%s'\n", params->dev_type); + ELOG("We do not support SWO output for device '%s'\n", + params ? params->dev_type : ""); if (!settings.force) return APP_RESULT_STLINK_UNSUPPORTED_DEVICE; } From 8f97e62708f5eff3e66669976d17cd0ecbf29125 Mon Sep 17 00:00:00 2001 From: Mingjie Shen Date: Sat, 22 Apr 2023 18:10:31 -0400 Subject: [PATCH 433/503] Check return values of sscanf() Failing to check that a call to 'scanf' actually writes to an output variable can lead to unexpected behavior at reading time. --- src/st-util/gdb-server.c | 6 ++++-- src/stlink-lib/chipid.c | 5 ++++- 2 files changed, 8 insertions(+), 3 deletions(-) diff --git a/src/st-util/gdb-server.c b/src/st-util/gdb-server.c index 802e23c06..d64073cf7 100644 --- a/src/st-util/gdb-server.c +++ b/src/st-util/gdb-server.c @@ -160,8 +160,10 @@ int parse_options(int argc, char** argv, st_state_t *st) { break; case 'p': - sscanf(optarg, "%i", &q); - if (q < 0) { + if (sscanf(optarg, "%i", &q) != 1) { + fprintf(stderr, "Invalid port %s\n", optarg); + exit(EXIT_FAILURE); + } else if (q < 0) { fprintf(stderr, "Can't use a negative port to listen on: %d\n", q); exit(EXIT_FAILURE); } diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index 44d93fedd..347d89e14 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -64,7 +64,10 @@ void process_chipfile(char *fname) { (strncmp(buf, " ", strlen(" ")) == 0)) continue; // ignore empty lines - sscanf(buf, "%63s %63s", word, value); + if (sscanf(buf, "%63s %63s", word, value) != 2) { + fprintf(stderr, "Failed to read keyword or value\n"); + continue; + } if (strcmp(word, "dev_type") == 0) { buf[strlen(buf) - 1] = 0; // chomp newline From 222ff4716520a815f0c3ed7360f93227a080e64a Mon Sep 17 00:00:00 2001 From: Oleksiy Slyshyk Date: Fri, 28 Apr 2023 17:59:47 +0300 Subject: [PATCH 434/503] fix warn in a few *.cmake --- cmake/modules/Findlibusb.cmake | 4 ++-- cmake/modules/get_version.cmake | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/cmake/modules/Findlibusb.cmake b/cmake/modules/Findlibusb.cmake index fbbda5ba3..6f0a21da6 100644 --- a/cmake/modules/Findlibusb.cmake +++ b/cmake/modules/Findlibusb.cmake @@ -60,7 +60,7 @@ elseif (WIN32 OR (EXISTS "/etc/debian_version" AND MINGW)) # Windows or MinGW-to if (WIN32 AND NOT EXISTS "/etc/debian_version") # ... on native Windows systems set(LIBUSB_WIN_ARCHIVE_PATH ${CMAKE_BINARY_DIR}/${LIBUSB_WIN_ARCHIVE}) set(LIBUSB_WIN_OUTPUT_FOLDER ${CMAKE_BINARY_DIR}/3rdparty/libusb-${LIBUSB_WIN_VERSION}) - else (EXISTS "/etc/debian_version" AND MINGW) # ... only for cross-building on Debian + elseif (EXISTS "/etc/debian_version" AND MINGW) # ... only for cross-building on Debian set(LIBUSB_WIN_ARCHIVE_PATH ${CMAKE_SOURCE_DIR}/build-mingw-${ARCH}/${LIBUSB_WIN_ARCHIVE}) set(LIBUSB_WIN_OUTPUT_FOLDER ${CMAKE_SOURCE_DIR}/build-mingw-${ARCH}/3rdparty/libusb-${LIBUSB_WIN_VERSION}) endif () @@ -102,7 +102,7 @@ elseif (WIN32 OR (EXISTS "/etc/debian_version" AND MINGW)) # Windows or MinGW-to NO_CMAKE_FIND_ROOT_PATH ) - else (MSVC) + elseif (MSVC) set(LIBUSB_NAME libusb-1.0.lib) find_library( LIBUSB_LIBRARY NAMES ${LIBUSB_NAME} diff --git a/cmake/modules/get_version.cmake b/cmake/modules/get_version.cmake index 70fbde816..8211d9c84 100644 --- a/cmake/modules/get_version.cmake +++ b/cmake/modules/get_version.cmake @@ -55,7 +55,7 @@ if (GIT_FOUND AND EXISTS "${PROJECT_SOURCE_DIR}/.git") message(STATUS "Rewrite ${PROJECT_SOURCE_DIR}/.version with ${__version_str}!") endif () - else (NOT EXISTS "${PROJECT_SOURCE_DIR}/.version") + elseif (NOT EXISTS "${PROJECT_SOURCE_DIR}/.version") # No local .version file found: Create a new one... file(WRITE "${PROJECT_SOURCE_DIR}/.version" ${__version_str}) From 1775184084f189409d91522e1d14f8d5fb84b61e Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 30 Apr 2023 14:31:50 +0200 Subject: [PATCH 435/503] General Project Update - Updated CHANGELOG.md - Updated README.md - Merged flash loader source files --- CHANGELOG.md | 13 +- CMakeLists.txt | 2 - README.md | 1 - src/st-util/gdb-server.c | 2 +- src/stlink-lib/common_flash.c | 2 +- src/stlink-lib/flash_loader.c | 500 +++++++++++++++++++++++++++++++++- src/stlink-lib/flash_loader.h | 5 + src/stlink-lib/flashloader.c | 496 --------------------------------- src/stlink-lib/flashloader.h | 13 - 9 files changed, 517 insertions(+), 517 deletions(-) delete mode 100644 src/stlink-lib/flashloader.c delete mode 100644 src/stlink-lib/flashloader.h diff --git a/CHANGELOG.md b/CHANGELOG.md index 551a4ba09..c930999cd 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -1,10 +1,11 @@ # stlink Changelog -# v1.7.1 +# v1.8.0 Release date: 2023-xx-xx -This release drops support for some older operating systems. Check project README for details. +This release drops support for macOS and some older operating systems. Check project README for details. +Removed Travis CI integration as it is no longer functional. Updated system requirements: - `cmake` >= 3.10.2 @@ -14,6 +15,7 @@ Updated system requirements: Features: - Support for writing option bytes on STM32F0/F1/F3 ([#346](https://github.com/stlink-org/stlink/pull/346), [#458](https://github.com/stlink-org/stlink/pull/458), [#808](https://github.com/stlink-org/stlink/pull/808), [#1084](https://github.com/stlink-org/stlink/pull/1084), [#1112](https://github.com/stlink-org/stlink/pull/1112)) +- Initial support for STM32 L5 & U5 devices and minor changes ([#1005](https://github.com/stlink-org/stlink/pull/1005), [#1096](https://github.com/stlink-org/stlink/pull/1096), [#1247](https://github.com/stlink-org/stlink/pull/1247), [#1300](https://github.com/stlink-org/stlink/pull/1300), [#1301](https://github.com/stlink-org/stlink/pull/1301)) - Added chip-IDs for STM32G0B0/G0B1/G0C1/G050/G051/G061 ([#1140](https://github.com/stlink-org/stlink/pull/1140)) - Added option byte info for STM32F411XX ([#1141](https://github.com/stlink-org/stlink/pull/1141)) - Expanded and revised list of chips ([#1145](https://github.com/stlink-org/stlink/pull/1145), [#1164](https://github.com/stlink-org/stlink/pull/1164)) @@ -22,6 +24,7 @@ Features: - Added support for STLINK-V3 devices with no MSD ([#1185](https://github.com/stlink-org/stlink/pull/1185)) - Updated gdb-server.c to allow external memory access on STM32H73xx ([#1196](https://github.com/stlink-org/stlink/pull/1196), [#1197](https://github.com/stlink-org/stlink/pull/1197)) - Erase addr size / section of the flash memory with st-flash ([#1213](https://github.com/stlink-org/stlink/pull/1213)) +- Added support for STM32L4Q5 ([#1224](https://github.com/stlink-org/stlink/pull/1224), [#1295](https://github.com/stlink-org/stlink/pull/1295)) - Added writing and reading for STM32WL option bytes ([#1226](https://github.com/stlink-org/stlink/pull/1226), [#1227](https://github.com/stlink-org/stlink/pull/1227)) - Added parametres option_base, option_size for F401xD_xE ([#1235](https://github.com/stlink-org/stlink/pull/1235)) - Added support for option bytes to F1xx_XLD (GD32F30x) ([#1250](https://github.com/stlink-org/stlink/pull/1250)) @@ -35,6 +38,7 @@ Updates & changes: - Added instructions for bug-reports and feature-requests to contribution guidelines ([#906](https://github.com/stlink-org/stlink/pull/906)) - Added travis CI configuration for macOS 10.14 to maintain capability for 32-bit compilation (commit [#f5ada94](https://github.com/stlink-org/stlink/commit/f5ada9474cdb87ff37de0d4eb9e75622b5870646)) - Updated description of chip id 0x0457 to L01x/L02x ([#1143](https://github.com/stlink-org/stlink/pull/1143), [#1144](https://github.com/stlink-org/stlink/pull/1144)) +- [doc] Human-readable flash_type in chip-id files ([#1155](https://github.com/stlink-org/stlink/pull/1155), commit [#1745bf5](https://github.com/stlink-org/stlink/commit/1745bf5193c4d3186d4f6fde59cc86e9bad6e61b)) - Dropped execute bits from source code files ([#1167](https://github.com/stlink-org/stlink/pull/1167)) - Use proper Markdown headers for supported MCUs ([#1168](https://github.com/stlink-org/stlink/pull/1168)) - Removed redundant array ([#1178](https://github.com/stlink-org/stlink/pull/1178)) @@ -58,6 +62,7 @@ Fixes: - Removed limit check for WRITEMEM_32BIT ([#1157](https://github.com/stlink-org/stlink/pull/1157)) - Fixed get_stm32l0_flash_base address for STM32L152RE ([#1161](https://github.com/stlink-org/stlink/pull/1161), [#1162](https://github.com/stlink-org/stlink/pull/1162)) - Fixed segfault if chip was not found in chip config files ([#1138](https://github.com/stlink-org/stlink/pull/1138), [#1163](https://github.com/stlink-org/stlink/pull/1163), [#1165](https://github.com/stlink-org/stlink/pull/1165), [#1166](https://github.com/stlink-org/stlink/pull/1166), [#1170](https://github.com/stlink-org/stlink/pull/1170)) +- Fixed parsing hex numbers in chip config files ([#1156](https://github.com/stlink-org/stlink/pull/1156), commit [#1d301a5](https://github.com/stlink-org/stlink/commit/1d301a5498433900250fe2a8c0e10dfb7f44d7a4)) - Fixed parsing hex numbers in chip config files ([#1169](https://github.com/stlink-org/stlink/pull/1169)) - Corrected flash_pagesize to use hex format ([#1172](https://github.com/stlink-org/stlink/pull/1172)) - Fixed compilation for MSVC ([#1176](https://github.com/stlink-org/stlink/pull/1176)) @@ -65,6 +70,7 @@ Fixes: - st-flash and other utilities search for chip files in the wrong directory ([#1180](https://github.com/stlink-org/stlink/pull/1180), commit [#c8fc656](https://github.com/stlink-org/stlink/commit/c8fc6561fead79ad49c09d82bab864745086792c)) - Fixed broken build on 32 bit systems ([#985](https://github.com/stlink-org/stlink/pull/985), [#1175](https://github.com/stlink-org/stlink/pull/1175), commit [#c8fc656](https://github.com/stlink-org/stlink/commit/c8fc6561fead79ad49c09d82bab864745086792c)) - Define 'SSIZE_MAX' if not defined ([#1183](https://github.com/stlink-org/stlink/pull/1183)) +- STM32G031G8: BOOT_LOCK is not possible to change on option bytes address 0x1FFF7870 ([#1194](https://github.com/stlink-org/stlink/pull/1194)) - Fixed compliation for OpenBSD 7.0 ([#1202](https://github.com/stlink-org/stlink/pull/1202)) - Included 'SSIZE_MAX' from 'limits.h' in 'src/common.c' ([#1207](https://github.com/stlink-org/stlink/pull/1207)) - Fix for libusb_kernel_driver_active & error handling for st.st_size () ([#1210](https://github.com/stlink-org/stlink/pull/1210), [#1211](https://github.com/stlink-org/stlink/pull/1211), [#1214](https://github.com/stlink-org/stlink/pull/1214)) @@ -78,6 +84,9 @@ Fixes: - Fixed st-trace reconnect on Windows ([#1272](https://github.com/stlink-org/stlink/pull/1272), [#1292](https://github.com/stlink-org/stlink/pull/1292)) - [compilation] Corrected path to stlink/chips subdirectory ([#1276](https://github.com/stlink-org/stlink/pull/1276), [#1279](https://github.com/stlink-org/stlink/pull/1279)) - [compilation] Fixed GUI compilation failure on OpenBSD i386 ([#1284](https://github.com/stlink-org/stlink/pull/1284)) +- Fixed unbounded write and check return values of sscanf ([#1306](https://github.com/stlink-org/stlink/pull/1306)) +- Added null check for return value of stlink_chipid_get_params() ([#1307](https://github.com/stlink-org/stlink/pull/1307)) +- Fixed warning in a few *.cmake files ([#1309](https://github.com/stlink-org/stlink/pull/1309)) # v1.7.0 diff --git a/CMakeLists.txt b/CMakeLists.txt index 4ce0ee126..bce4def8f 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -174,7 +174,6 @@ set(STLINK_HEADERS src/stlink-lib/common_flash.h src/stlink-lib/common.h src/stlink-lib/flash_loader.h - src/stlink-lib/flashloader.h src/stlink-lib/helper.h src/stlink-lib/libusb_settings.h src/stlink-lib/logging.h @@ -192,7 +191,6 @@ set(STLINK_SOURCE src/stlink-lib/common_flash.c src/stlink-lib/common.c src/stlink-lib/flash_loader.c - src/stlink-lib/flashloader.c src/stlink-lib/helper.c src/stlink-lib/logging.c src/stlink-lib/map_file.c diff --git a/README.md b/README.md index 3101fb560..0e846b336 100644 --- a/README.md +++ b/README.md @@ -8,7 +8,6 @@ ![GitHub contributors](https://img.shields.io/github/contributors/stlink-org/stlink) [![CodeQL](https://github.com/stlink-org/stlink/actions/workflows/codeql-analysis.yml/badge.svg)](https://github.com/stlink-org/stlink/actions/workflows/codeql-analysis.yml) [![C/C++ CI](https://github.com/stlink-org/stlink/actions/workflows/c-cpp.yml/badge.svg?branch=testing)](https://github.com/stlink-org/stlink/actions/workflows/c-cpp.yml) -[![Linux Status](https://img.shields.io/travis/stlink-org/stlink/master?env=BADGE=linux&label=linux)](https://travis-ci.org/stlink-org/stlink) Recent new features and bugfixes can be found in the [Changelog](CHANGELOG.md) of this software project. diff --git a/src/st-util/gdb-server.c b/src/st-util/gdb-server.c index d64073cf7..99cc0170b 100644 --- a/src/st-util/gdb-server.c +++ b/src/st-util/gdb-server.c @@ -28,7 +28,7 @@ #include #include #include -#include "flashloader.h" +#include "flash_loader.h" #include "gdb-remote.h" #include "gdb-server.h" #include "semihosting.h" diff --git a/src/stlink-lib/common_flash.c b/src/stlink-lib/common_flash.c index 000f9279d..740c93690 100644 --- a/src/stlink-lib/common_flash.c +++ b/src/stlink-lib/common_flash.c @@ -3,7 +3,7 @@ #include #include #include "calculate.h" -#include "flashloader.h" +#include "flash_loader.h" #include "common_flash.h" #include "map_file.h" #include "common.h" diff --git a/src/stlink-lib/flash_loader.c b/src/stlink-lib/flash_loader.c index 94978a51f..852ba6c20 100644 --- a/src/stlink-lib/flash_loader.c +++ b/src/stlink-lib/flash_loader.c @@ -6,6 +6,7 @@ #include #include #include "flash_loader.h" +#include "common_flash.h" #define FLASH_REGS_BANK2_OFS 0x40 #define FLASH_BANK2_START_ADDR 0x08080000 @@ -386,7 +387,7 @@ int stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t targe * The chunk size for loading is not rounded. The flash loader * subtracts the size of the written block (1-8 bytes) from * the remaining size each time. A negative value may mean that - * several bytes garbage has been written due to the unaligned + * several bytes garbage have been written due to the unaligned * firmware size. */ if ((int32_t)rr.r[2] > 0 || (int32_t)rr.r[2] < -7) { @@ -412,3 +413,500 @@ int stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t targe return(-1); } + + +/* ================================================== + * === Content from old source file flashloader.c === + * ================================================== + */ + +#define L1_WRITE_BLOCK_SIZE 0x80 +#define L0_WRITE_BLOCK_SIZE 0x40 + +int stm32l1_write_half_pages(stlink_t *sl, stm32_addr_t addr, uint8_t *base, + uint32_t len, uint32_t pagesize) { + unsigned int count, off; + unsigned int num_half_pages = len / pagesize; + uint32_t val; + uint32_t flash_regs_base = get_stm32l0_flash_base(sl); + flash_loader_t fl; + bool use_loader = true; + int ret = 0; + + // enable half page write + stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); + val |= (1 << FLASH_L1_FPRG); + stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); + val |= (1 << FLASH_L1_PROG); + stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); + + wait_flash_busy(sl); + + for (count = 0; count < num_half_pages; count++) { + if (use_loader) { + ret = stlink_flash_loader_run(sl, &fl, addr + count * pagesize, + base + count * pagesize, pagesize); + if (ret && count == 0) { + /* It seems that stm32lx devices have a problem when it is blank */ + WLOG("Failed to use flash loader, fallback to soft write\n"); + use_loader = false; + } + } + if (!use_loader) { + ret = 0; + for (off = 0; off < pagesize && !ret; off += 64) { + size_t chunk = (pagesize - off > 64) ? 64 : pagesize - off; + memcpy(sl->q_buf, base + count * pagesize + off, chunk); + ret = stlink_write_mem32(sl, addr + count * pagesize + off, (uint16_t)chunk); + } + } + + if (ret) { + WLOG("l1_stlink_flash_loader_run(%#x) failed! == -1\n", addr + count * pagesize); + break; + } + + if (sl->verbose >= 1) { + // show progress; writing procedure is slow and previous errors are misleading + fprintf(stdout, "\r%3u/%u halfpages written", count + 1, num_half_pages); + fflush(stdout); + } + + // wait for sr.busy to be cleared + wait_flash_busy(sl); + } + + // disable half page write + stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); + val &= ~((1 << FLASH_L1_FPRG) | (1 << FLASH_L1_PROG)); + stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); + return (ret); +} + +static void set_flash_cr_pg(stlink_t *sl, unsigned bank) { + uint32_t cr_reg, x; + + x = read_flash_cr(sl, bank); + + if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { + cr_reg = FLASH_F4_CR; + x |= 1 << FLASH_CR_PG; + } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { + cr_reg = FLASH_F7_CR; + x |= 1 << FLASH_CR_PG; + } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { + cr_reg = STM32L4_FLASH_CR; + x &= ~STM32L4_FLASH_CR_OPBITS; + x |= (1 << STM32L4_FLASH_CR_PG); + } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5) { + cr_reg = STM32L5_FLASH_NSCR; + x |= (1 << FLASH_CR_PG); + } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4) { + cr_reg = STM32Gx_FLASH_CR; + x |= (1 << FLASH_CR_PG); + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { + cr_reg = STM32WB_FLASH_CR; + x |= (1 << FLASH_CR_PG); + } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { + cr_reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; + x |= (1 << FLASH_H7_CR_PG); + } else { + cr_reg = (bank == BANK_1) ? FLASH_CR : FLASH_CR2; + x = (1 << FLASH_CR_PG); + } + + stlink_write_debug32(sl, cr_reg, x); +} + +static void set_dma_state(stlink_t *sl, flash_loader_t *fl, int bckpRstr) { + uint32_t rcc, rcc_dma_mask, value; + + rcc = rcc_dma_mask = value = 0; + + switch (sl->flash_type) { + case STM32_FLASH_TYPE_F0_F1_F3: + case STM32_FLASH_TYPE_F1_XL: + rcc = STM32F1_RCC_AHBENR; + rcc_dma_mask = STM32F1_RCC_DMAEN; + break; + case STM32_FLASH_TYPE_F2_F4: + case STM32_FLASH_TYPE_F7: + rcc = STM32F4_RCC_AHB1ENR; + rcc_dma_mask = STM32F4_RCC_DMAEN; + break; + case STM32_FLASH_TYPE_G0: + rcc = STM32G0_RCC_AHBENR; + rcc_dma_mask = STM32G0_RCC_DMAEN; + break; + case STM32_FLASH_TYPE_G4: + case STM32_FLASH_TYPE_L4: + rcc = STM32G4_RCC_AHB1ENR; + rcc_dma_mask = STM32G4_RCC_DMAEN; + break; + case STM32_FLASH_TYPE_L0_L1: + if (get_stm32l0_flash_base(sl) == STM32L_FLASH_REGS_ADDR) { + rcc = STM32L1_RCC_AHBENR; + rcc_dma_mask = STM32L1_RCC_DMAEN; + } else { + rcc = STM32L0_RCC_AHBENR; + rcc_dma_mask = STM32L0_RCC_DMAEN; + } + break; + case STM32_FLASH_TYPE_L5_U5: + rcc = STM32L5_RCC_AHB1ENR; + rcc_dma_mask = STM32L5_RCC_DMAEN; + break; + case STM32_FLASH_TYPE_H7: + rcc = STM32H7_RCC_AHB1ENR; + rcc_dma_mask = STM32H7_RCC_DMAEN; + break; + case STM32_FLASH_TYPE_WB_WL: + rcc = STM32WB_RCC_AHB1ENR; + rcc_dma_mask = STM32WB_RCC_DMAEN; + break; + default: + return; + } + + if (!stlink_read_debug32(sl, rcc, &value)) { + if (bckpRstr) { + value = (value & (~rcc_dma_mask)) | fl->rcc_dma_bkp; + } else { + fl->rcc_dma_bkp = value & rcc_dma_mask; + value &= ~rcc_dma_mask; + } + stlink_write_debug32(sl, rcc, value); + } +} + +int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { + // disable DMA + set_dma_state(sl, fl, 0); + + // wait for ongoing op to finish + wait_flash_busy(sl); + // Clear errors + clear_flash_error(sl); + + if ((sl->flash_type == STM32_FLASH_TYPE_F2_F4) || + (sl->flash_type == STM32_FLASH_TYPE_F7) || + (sl->flash_type == STM32_FLASH_TYPE_L4)) { + ILOG("Starting Flash write for F2/F4/F7/L4\n"); + + // Flash loader initialisation + if (stlink_flash_loader_init(sl, fl) == -1) { + ELOG("stlink_flash_loader_init() == -1\n"); + return (-1); + } + + unlock_flash_if(sl); // first unlock the cr + + int voltage; + if (sl->version.stlink_v == 1) { + WLOG("STLINK V1 cannot read voltage, use default voltage 3.2V\n"); + voltage = 3200; + } else { + voltage = stlink_target_voltage(sl); + } + + if (voltage == -1) { + ELOG("Failed to read Target voltage\n"); + return (-1); + } + + if (sl->flash_type == STM32_FLASH_TYPE_L4) { + // L4 does not have a byte-write mode + if (voltage < 1710) { + ELOG("Target voltage (%d mV) too low for flash writes!\n", voltage); + return (-1); + } + } else { + if (voltage > 2700) { + ILOG("enabling 32-bit flash writes\n"); + write_flash_cr_psiz(sl, 2, BANK_1); + } else { + ILOG("Target voltage (%d mV) too low for 32-bit flash, " + "using 8-bit flash writes\n", + voltage); + write_flash_cr_psiz(sl, 0, BANK_1); + } + } + + // set programming mode + set_flash_cr_pg(sl, BANK_1); + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL || + sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4 || + sl->flash_type == STM32_FLASH_TYPE_L5_U5) { + ILOG("Starting Flash write for WB/G0/G4/L5/U5\n"); + + unlock_flash_if(sl); // unlock flash if necessary + set_flash_cr_pg(sl, BANK_1); // set PG 'allow programming' bit + } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { + ILOG("Starting Flash write for L0\n"); + + uint32_t val; + uint32_t flash_regs_base = get_stm32l0_flash_base(sl); + + // disable pecr protection + stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, + FLASH_L0_PEKEY1); + stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, + FLASH_L0_PEKEY2); + + // check pecr.pelock is cleared + stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); + if (val & (1 << 0)) { + ELOG("pecr.pelock not clear\n"); + return (-1); + } + + // unlock program memory + stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, + FLASH_L0_PRGKEY1); + stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, + FLASH_L0_PRGKEY2); + + // check pecr.prglock is cleared + stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); + if (val & (1 << 1)) { + ELOG("pecr.prglock not clear\n"); + return (-1); + } + + /* Flash loader initialisation */ + if (stlink_flash_loader_init(sl, fl) == -1) { + // L0/L1 have fallback to soft write + WLOG("stlink_flash_loader_init() == -1\n"); + } + } else if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || + (sl->flash_type == STM32_FLASH_TYPE_F1_XL)) { + ILOG("Starting Flash write for VL/F0/F3/F1_XL\n"); + + // flash loader initialisation + if (stlink_flash_loader_init(sl, fl) == -1) { + ELOG("stlink_flash_loader_init() == -1\n"); + return (-1); + } + + // unlock flash + unlock_flash_if(sl); + + // set programming mode + set_flash_cr_pg(sl, BANK_1); + if (sl->flash_type == STM32_FLASH_TYPE_F1_XL) { + set_flash_cr_pg(sl, BANK_2); + } + } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { + ILOG("Starting Flash write for H7\n"); + + unlock_flash_if(sl); // unlock the cr + set_flash_cr_pg(sl, BANK_1); // set programming mode + if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { + set_flash_cr_pg(sl, BANK_2); + } + if (sl->chip_id != STM32_CHIPID_H7Ax) { + // set parallelism + write_flash_cr_psiz(sl, 3 /*64it*/, BANK_1); + if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { + write_flash_cr_psiz(sl, 3 /*64bit*/, BANK_2); + } + } + } else { + ELOG("unknown coreid, not sure how to write: %x\n", sl->core_id); + return (-1); + } + + return (0); +} + +int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, + stm32_addr_t addr, uint8_t *base, uint32_t len) { + size_t off; + if ((sl->flash_type == STM32_FLASH_TYPE_F2_F4) || + (sl->flash_type == STM32_FLASH_TYPE_F7) || + (sl->flash_type == STM32_FLASH_TYPE_L4)) { + size_t buf_size = (sl->sram_size > 0x8000) ? 0x8000 : 0x4000; + for (off = 0; off < len;) { + size_t size = len - off > buf_size ? buf_size : len - off; + if (stlink_flash_loader_run(sl, fl, addr + (uint32_t)off, base + off, + size) == -1) { + ELOG("stlink_flash_loader_run(%#x) failed! == -1\n", + (unsigned)(addr + off)); + check_flash_error(sl); + return (-1); + } + + off += size; + } + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL || + sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4 || + sl->flash_type == STM32_FLASH_TYPE_L5_U5) { + DLOG("Starting %3u page write\r\n", (unsigned int)(len / sl->flash_pgsz)); + for (off = 0; off < len; off += sizeof(uint32_t)) { + uint32_t data; + + if ((off % sl->flash_pgsz) > (sl->flash_pgsz - 5)) { + fprintf(stdout, "\r%3u/%3u pages written", + (unsigned int)(off / sl->flash_pgsz + 1), + (unsigned int)(len / sl->flash_pgsz)); + fflush(stdout); + } + + write_uint32((unsigned char *)&data, *(uint32_t *)(base + off)); + stlink_write_debug32(sl, addr + (uint32_t)off, data); + wait_flash_busy(sl); // wait for 'busy' bit in FLASH_SR to clear + } + fprintf(stdout, "\n"); + + // flash writes happen as 2 words at a time + if ((off / sizeof(uint32_t)) % 2 != 0) { + stlink_write_debug32(sl, addr + (uint32_t)off, + 0); // write a single word of zeros + wait_flash_busy(sl); // wait for 'busy' bit in FLASH_SR to clear + } + } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { + uint32_t val; + uint32_t flash_regs_base = get_stm32l0_flash_base(sl); + uint32_t pagesize = (flash_regs_base==STM32L0_FLASH_REGS_ADDR)? + L0_WRITE_BLOCK_SIZE:L1_WRITE_BLOCK_SIZE; + + DLOG("Starting %3u page write\r\n", (unsigned int)(len / sl->flash_pgsz)); + + off = 0; + + if (len > pagesize) { + if (stm32l1_write_half_pages(sl, addr, base, len, pagesize)) { + return (-1); + } else { + off = (size_t)(len / pagesize) * pagesize; + } + } + + // write remaining word in program memory + for (; off < len; off += sizeof(uint32_t)) { + uint32_t data; + + if ((off % sl->flash_pgsz) > (sl->flash_pgsz - 5)) { + fprintf(stdout, "\r%3u/%3u pages written", + (unsigned int)(off / sl->flash_pgsz + 1), + (unsigned int)(len / sl->flash_pgsz)); + fflush(stdout); + } + + write_uint32((unsigned char *)&data, *(uint32_t *)(base + off)); + stlink_write_debug32(sl, addr + (uint32_t)off, data); + + // wait for sr.busy to be cleared + do { + stlink_read_debug32(sl, flash_regs_base + FLASH_SR_OFF, &val); + } while ((val & (1 << 0)) != 0); + + // TODO: check redo write operation + } + fprintf(stdout, "\n"); + } else if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || + (sl->flash_type == STM32_FLASH_TYPE_F1_XL)) { + int write_block_count = 0; + for (off = 0; off < len; off += sl->flash_pgsz) { + // adjust last write size + size_t size = len - off > sl->flash_pgsz ? sl->flash_pgsz : len - off; + + // unlock and set programming mode + unlock_flash_if(sl); + + DLOG("Finished unlocking flash, running loader!\n"); + + if (stlink_flash_loader_run(sl, fl, addr + (uint32_t)off, base + off, + size) == -1) { + ELOG("stlink_flash_loader_run(%#x) failed! == -1\n", + (unsigned)(addr + off)); + check_flash_error(sl); + return (-1); + } + + lock_flash(sl); + + if (sl->verbose >= 1) { + // show progress; writing procedure is slow and previous errors are + // misleading + fprintf(stdout, "\r%3u/%3u pages written", ++write_block_count, + (unsigned int)((len + sl->flash_pgsz - 1) / sl->flash_pgsz)); + fflush(stdout); + } + } + if (sl->verbose >= 1) { + fprintf(stdout, "\n"); + } + } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { + for (off = 0; off < len;) { + // Program STM32H7x with 64-byte Flash words + size_t chunk = (len - off > 64) ? 64 : len - off; + memcpy(sl->q_buf, base + off, chunk); + stlink_write_mem32(sl, addr + (uint32_t)off, 64); + wait_flash_busy(sl); + + off += chunk; + + if (sl->verbose >= 1) { + // show progress + fprintf(stdout, "\r%u/%u bytes written", (unsigned int)off, + (unsigned int)len); + fflush(stdout); + } + } + if (sl->verbose >= 1) { + fprintf(stdout, "\n"); + } + } else { + return (-1); + } + + return check_flash_error(sl); +} + +int stlink_flashloader_stop(stlink_t *sl, flash_loader_t *fl) { + uint32_t dhcsr; + + if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || + (sl->flash_type == STM32_FLASH_TYPE_F1_XL) || + (sl->flash_type == STM32_FLASH_TYPE_F2_F4) || + (sl->flash_type == STM32_FLASH_TYPE_F7) || + (sl->flash_type == STM32_FLASH_TYPE_G0) || + (sl->flash_type == STM32_FLASH_TYPE_G4) || + (sl->flash_type == STM32_FLASH_TYPE_H7) || + (sl->flash_type == STM32_FLASH_TYPE_L4) || + (sl->flash_type == STM32_FLASH_TYPE_L5_U5) || + (sl->flash_type == STM32_FLASH_TYPE_WB_WL)) { + + clear_flash_cr_pg(sl, BANK_1); + if ((sl->flash_type == STM32_FLASH_TYPE_H7 && + sl->chip_flags & CHIP_F_HAS_DUAL_BANK) || + sl->flash_type == STM32_FLASH_TYPE_F1_XL) { + clear_flash_cr_pg(sl, BANK_2); + } + lock_flash(sl); + } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { + uint32_t val; + uint32_t flash_regs_base = get_stm32l0_flash_base(sl); + + // reset lock bits + stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); + val |= (1 << 0) | (1 << 1) | (1 << 2); + stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); + } + + // enable interrupt + if (!stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr)) { + stlink_write_debug32(sl, STLINK_REG_DHCSR, + STLINK_REG_DHCSR_DBGKEY | STLINK_REG_DHCSR_C_DEBUGEN | + (dhcsr & (~STLINK_REG_DHCSR_C_MASKINTS))); + } + + // restore DMA state + set_dma_state(sl, fl, 1); + + return (0); +} diff --git a/src/stlink-lib/flash_loader.h b/src/stlink-lib/flash_loader.h index 368b6ab8b..0d39a9a48 100644 --- a/src/stlink-lib/flash_loader.h +++ b/src/stlink-lib/flash_loader.h @@ -7,6 +7,7 @@ #ifndef STLINK_FLASH_LOADER_H_ #define STLINK_FLASH_LOADER_H_ +#include #include #include @@ -16,4 +17,8 @@ int stlink_flash_loader_init(stlink_t *sl, flash_loader_t* fl); int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size); int stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, const uint8_t* buf, size_t size); +int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl); +int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t addr, uint8_t* base, uint32_t len); +int stlink_flashloader_stop(stlink_t *sl, flash_loader_t *fl); + #endif // STLINK_FLASH_LOADER_H_ diff --git a/src/stlink-lib/flashloader.c b/src/stlink-lib/flashloader.c deleted file mode 100644 index 4adf93a86..000000000 --- a/src/stlink-lib/flashloader.c +++ /dev/null @@ -1,496 +0,0 @@ -#include -#include -#include -#include "flashloader.h" -#include "common_flash.h" - -#define L1_WRITE_BLOCK_SIZE 0x80 -#define L0_WRITE_BLOCK_SIZE 0x40 - -int stm32l1_write_half_pages(stlink_t *sl, stm32_addr_t addr, uint8_t *base, - uint32_t len, uint32_t pagesize) { - unsigned int count, off; - unsigned int num_half_pages = len / pagesize; - uint32_t val; - uint32_t flash_regs_base = get_stm32l0_flash_base(sl); - flash_loader_t fl; - bool use_loader = true; - int ret = 0; - - // enable half page write - stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); - val |= (1 << FLASH_L1_FPRG); - stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); - val |= (1 << FLASH_L1_PROG); - stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); - - wait_flash_busy(sl); - - for (count = 0; count < num_half_pages; count++) { - if (use_loader) { - ret = stlink_flash_loader_run(sl, &fl, addr + count * pagesize, - base + count * pagesize, pagesize); - if (ret && count == 0) { - /* It seems that stm32lx devices have a problem when it is blank */ - WLOG("Failed to use flash loader, fallback to soft write\n"); - use_loader = false; - } - } - if (!use_loader) { - ret = 0; - for (off = 0; off < pagesize && !ret; off += 64) { - size_t chunk = (pagesize - off > 64) ? 64 : pagesize - off; - memcpy(sl->q_buf, base + count * pagesize + off, chunk); - ret = stlink_write_mem32(sl, addr + count * pagesize + off, (uint16_t)chunk); - } - } - - if (ret) { - WLOG("l1_stlink_flash_loader_run(%#x) failed! == -1\n", addr + count * pagesize); - break; - } - - if (sl->verbose >= 1) { - // show progress; writing procedure is slow and previous errors are misleading - fprintf(stdout, "\r%3u/%u halfpages written", count + 1, num_half_pages); - fflush(stdout); - } - - // wait for sr.busy to be cleared - wait_flash_busy(sl); - } - - // disable half page write - stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); - val &= ~((1 << FLASH_L1_FPRG) | (1 << FLASH_L1_PROG)); - stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); - return (ret); -} - -static void set_flash_cr_pg(stlink_t *sl, unsigned bank) { - uint32_t cr_reg, x; - - x = read_flash_cr(sl, bank); - - if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { - cr_reg = FLASH_F4_CR; - x |= 1 << FLASH_CR_PG; - } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { - cr_reg = FLASH_F7_CR; - x |= 1 << FLASH_CR_PG; - } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { - cr_reg = STM32L4_FLASH_CR; - x &= ~STM32L4_FLASH_CR_OPBITS; - x |= (1 << STM32L4_FLASH_CR_PG); - } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5) { - cr_reg = STM32L5_FLASH_NSCR; - x |= (1 << FLASH_CR_PG); - } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || - sl->flash_type == STM32_FLASH_TYPE_G4) { - cr_reg = STM32Gx_FLASH_CR; - x |= (1 << FLASH_CR_PG); - } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { - cr_reg = STM32WB_FLASH_CR; - x |= (1 << FLASH_CR_PG); - } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { - cr_reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; - x |= (1 << FLASH_H7_CR_PG); - } else { - cr_reg = (bank == BANK_1) ? FLASH_CR : FLASH_CR2; - x = (1 << FLASH_CR_PG); - } - - stlink_write_debug32(sl, cr_reg, x); -} - -static void set_dma_state(stlink_t *sl, flash_loader_t *fl, int bckpRstr) { - uint32_t rcc, rcc_dma_mask, value; - - rcc = rcc_dma_mask = value = 0; - - switch (sl->flash_type) { - case STM32_FLASH_TYPE_F0_F1_F3: - case STM32_FLASH_TYPE_F1_XL: - rcc = STM32F1_RCC_AHBENR; - rcc_dma_mask = STM32F1_RCC_DMAEN; - break; - case STM32_FLASH_TYPE_F2_F4: - case STM32_FLASH_TYPE_F7: - rcc = STM32F4_RCC_AHB1ENR; - rcc_dma_mask = STM32F4_RCC_DMAEN; - break; - case STM32_FLASH_TYPE_G0: - rcc = STM32G0_RCC_AHBENR; - rcc_dma_mask = STM32G0_RCC_DMAEN; - break; - case STM32_FLASH_TYPE_G4: - case STM32_FLASH_TYPE_L4: - rcc = STM32G4_RCC_AHB1ENR; - rcc_dma_mask = STM32G4_RCC_DMAEN; - break; - case STM32_FLASH_TYPE_L0_L1: - if (get_stm32l0_flash_base(sl) == STM32L_FLASH_REGS_ADDR) { - rcc = STM32L1_RCC_AHBENR; - rcc_dma_mask = STM32L1_RCC_DMAEN; - } else { - rcc = STM32L0_RCC_AHBENR; - rcc_dma_mask = STM32L0_RCC_DMAEN; - } - break; - case STM32_FLASH_TYPE_L5_U5: - rcc = STM32L5_RCC_AHB1ENR; - rcc_dma_mask = STM32L5_RCC_DMAEN; - break; - case STM32_FLASH_TYPE_H7: - rcc = STM32H7_RCC_AHB1ENR; - rcc_dma_mask = STM32H7_RCC_DMAEN; - break; - case STM32_FLASH_TYPE_WB_WL: - rcc = STM32WB_RCC_AHB1ENR; - rcc_dma_mask = STM32WB_RCC_DMAEN; - break; - default: - return; - } - - if (!stlink_read_debug32(sl, rcc, &value)) { - if (bckpRstr) { - value = (value & (~rcc_dma_mask)) | fl->rcc_dma_bkp; - } else { - fl->rcc_dma_bkp = value & rcc_dma_mask; - value &= ~rcc_dma_mask; - } - stlink_write_debug32(sl, rcc, value); - } -} - -int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { - // disable DMA - set_dma_state(sl, fl, 0); - - // wait for ongoing op to finish - wait_flash_busy(sl); - // Clear errors - clear_flash_error(sl); - - if ((sl->flash_type == STM32_FLASH_TYPE_F2_F4) || - (sl->flash_type == STM32_FLASH_TYPE_F7) || - (sl->flash_type == STM32_FLASH_TYPE_L4)) { - ILOG("Starting Flash write for F2/F4/F7/L4\n"); - - // Flash loader initialisation - if (stlink_flash_loader_init(sl, fl) == -1) { - ELOG("stlink_flash_loader_init() == -1\n"); - return (-1); - } - - unlock_flash_if(sl); // first unlock the cr - - int voltage; - if (sl->version.stlink_v == 1) { - WLOG("STLINK V1 cannot read voltage, use default voltage 3.2V\n"); - voltage = 3200; - } else { - voltage = stlink_target_voltage(sl); - } - - if (voltage == -1) { - ELOG("Failed to read Target voltage\n"); - return (-1); - } - - if (sl->flash_type == STM32_FLASH_TYPE_L4) { - // L4 does not have a byte-write mode - if (voltage < 1710) { - ELOG("Target voltage (%d mV) too low for flash writes!\n", voltage); - return (-1); - } - } else { - if (voltage > 2700) { - ILOG("enabling 32-bit flash writes\n"); - write_flash_cr_psiz(sl, 2, BANK_1); - } else { - ILOG("Target voltage (%d mV) too low for 32-bit flash, " - "using 8-bit flash writes\n", - voltage); - write_flash_cr_psiz(sl, 0, BANK_1); - } - } - - // set programming mode - set_flash_cr_pg(sl, BANK_1); - } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL || - sl->flash_type == STM32_FLASH_TYPE_G0 || - sl->flash_type == STM32_FLASH_TYPE_G4 || - sl->flash_type == STM32_FLASH_TYPE_L5_U5) { - ILOG("Starting Flash write for WB/G0/G4/L5/U5\n"); - - unlock_flash_if(sl); // unlock flash if necessary - set_flash_cr_pg(sl, BANK_1); // set PG 'allow programming' bit - } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { - ILOG("Starting Flash write for L0\n"); - - uint32_t val; - uint32_t flash_regs_base = get_stm32l0_flash_base(sl); - - // disable pecr protection - stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, - FLASH_L0_PEKEY1); - stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, - FLASH_L0_PEKEY2); - - // check pecr.pelock is cleared - stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); - if (val & (1 << 0)) { - ELOG("pecr.pelock not clear\n"); - return (-1); - } - - // unlock program memory - stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, - FLASH_L0_PRGKEY1); - stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, - FLASH_L0_PRGKEY2); - - // check pecr.prglock is cleared - stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); - if (val & (1 << 1)) { - ELOG("pecr.prglock not clear\n"); - return (-1); - } - - /* Flash loader initialisation */ - if (stlink_flash_loader_init(sl, fl) == -1) { - // L0/L1 have fallback to soft write - WLOG("stlink_flash_loader_init() == -1\n"); - } - } else if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || - (sl->flash_type == STM32_FLASH_TYPE_F1_XL)) { - ILOG("Starting Flash write for VL/F0/F3/F1_XL\n"); - - // flash loader initialisation - if (stlink_flash_loader_init(sl, fl) == -1) { - ELOG("stlink_flash_loader_init() == -1\n"); - return (-1); - } - - // unlock flash - unlock_flash_if(sl); - - // set programming mode - set_flash_cr_pg(sl, BANK_1); - if (sl->flash_type == STM32_FLASH_TYPE_F1_XL) { - set_flash_cr_pg(sl, BANK_2); - } - } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { - ILOG("Starting Flash write for H7\n"); - - unlock_flash_if(sl); // unlock the cr - set_flash_cr_pg(sl, BANK_1); // set programming mode - if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { - set_flash_cr_pg(sl, BANK_2); - } - if (sl->chip_id != STM32_CHIPID_H7Ax) { - // set parallelism - write_flash_cr_psiz(sl, 3 /*64it*/, BANK_1); - if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { - write_flash_cr_psiz(sl, 3 /*64bit*/, BANK_2); - } - } - } else { - ELOG("unknown coreid, not sure how to write: %x\n", sl->core_id); - return (-1); - } - - return (0); -} - -int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, - stm32_addr_t addr, uint8_t *base, uint32_t len) { - size_t off; - if ((sl->flash_type == STM32_FLASH_TYPE_F2_F4) || - (sl->flash_type == STM32_FLASH_TYPE_F7) || - (sl->flash_type == STM32_FLASH_TYPE_L4)) { - size_t buf_size = (sl->sram_size > 0x8000) ? 0x8000 : 0x4000; - for (off = 0; off < len;) { - size_t size = len - off > buf_size ? buf_size : len - off; - if (stlink_flash_loader_run(sl, fl, addr + (uint32_t)off, base + off, - size) == -1) { - ELOG("stlink_flash_loader_run(%#x) failed! == -1\n", - (unsigned)(addr + off)); - check_flash_error(sl); - return (-1); - } - - off += size; - } - } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL || - sl->flash_type == STM32_FLASH_TYPE_G0 || - sl->flash_type == STM32_FLASH_TYPE_G4 || - sl->flash_type == STM32_FLASH_TYPE_L5_U5) { - DLOG("Starting %3u page write\r\n", (unsigned int)(len / sl->flash_pgsz)); - for (off = 0; off < len; off += sizeof(uint32_t)) { - uint32_t data; - - if ((off % sl->flash_pgsz) > (sl->flash_pgsz - 5)) { - fprintf(stdout, "\r%3u/%3u pages written", - (unsigned int)(off / sl->flash_pgsz + 1), - (unsigned int)(len / sl->flash_pgsz)); - fflush(stdout); - } - - write_uint32((unsigned char *)&data, *(uint32_t *)(base + off)); - stlink_write_debug32(sl, addr + (uint32_t)off, data); - wait_flash_busy(sl); // wait for 'busy' bit in FLASH_SR to clear - } - fprintf(stdout, "\n"); - - // flash writes happen as 2 words at a time - if ((off / sizeof(uint32_t)) % 2 != 0) { - stlink_write_debug32(sl, addr + (uint32_t)off, - 0); // write a single word of zeros - wait_flash_busy(sl); // wait for 'busy' bit in FLASH_SR to clear - } - } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { - uint32_t val; - uint32_t flash_regs_base = get_stm32l0_flash_base(sl); - uint32_t pagesize = (flash_regs_base==STM32L0_FLASH_REGS_ADDR)? - L0_WRITE_BLOCK_SIZE:L1_WRITE_BLOCK_SIZE; - - DLOG("Starting %3u page write\r\n", (unsigned int)(len / sl->flash_pgsz)); - - off = 0; - - if (len > pagesize) { - if (stm32l1_write_half_pages(sl, addr, base, len, pagesize)) { - return (-1); - } else { - off = (size_t)(len / pagesize) * pagesize; - } - } - - // write remaining word in program memory - for (; off < len; off += sizeof(uint32_t)) { - uint32_t data; - - if ((off % sl->flash_pgsz) > (sl->flash_pgsz - 5)) { - fprintf(stdout, "\r%3u/%3u pages written", - (unsigned int)(off / sl->flash_pgsz + 1), - (unsigned int)(len / sl->flash_pgsz)); - fflush(stdout); - } - - write_uint32((unsigned char *)&data, *(uint32_t *)(base + off)); - stlink_write_debug32(sl, addr + (uint32_t)off, data); - - // wait for sr.busy to be cleared - do { - stlink_read_debug32(sl, flash_regs_base + FLASH_SR_OFF, &val); - } while ((val & (1 << 0)) != 0); - - // TODO: check redo write operation - } - fprintf(stdout, "\n"); - } else if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || - (sl->flash_type == STM32_FLASH_TYPE_F1_XL)) { - int write_block_count = 0; - for (off = 0; off < len; off += sl->flash_pgsz) { - // adjust last write size - size_t size = len - off > sl->flash_pgsz ? sl->flash_pgsz : len - off; - - // unlock and set programming mode - unlock_flash_if(sl); - - DLOG("Finished unlocking flash, running loader!\n"); - - if (stlink_flash_loader_run(sl, fl, addr + (uint32_t)off, base + off, - size) == -1) { - ELOG("stlink_flash_loader_run(%#x) failed! == -1\n", - (unsigned)(addr + off)); - check_flash_error(sl); - return (-1); - } - - lock_flash(sl); - - if (sl->verbose >= 1) { - // show progress; writing procedure is slow and previous errors are - // misleading - fprintf(stdout, "\r%3u/%3u pages written", ++write_block_count, - (unsigned int)((len + sl->flash_pgsz - 1) / sl->flash_pgsz)); - fflush(stdout); - } - } - if (sl->verbose >= 1) { - fprintf(stdout, "\n"); - } - } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { - for (off = 0; off < len;) { - // Program STM32H7x with 64-byte Flash words - size_t chunk = (len - off > 64) ? 64 : len - off; - memcpy(sl->q_buf, base + off, chunk); - stlink_write_mem32(sl, addr + (uint32_t)off, 64); - wait_flash_busy(sl); - - off += chunk; - - if (sl->verbose >= 1) { - // show progress - fprintf(stdout, "\r%u/%u bytes written", (unsigned int)off, - (unsigned int)len); - fflush(stdout); - } - } - if (sl->verbose >= 1) { - fprintf(stdout, "\n"); - } - } else { - return (-1); - } - - return check_flash_error(sl); -} - -int stlink_flashloader_stop(stlink_t *sl, flash_loader_t *fl) { - uint32_t dhcsr; - - if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || - (sl->flash_type == STM32_FLASH_TYPE_F1_XL) || - (sl->flash_type == STM32_FLASH_TYPE_F2_F4) || - (sl->flash_type == STM32_FLASH_TYPE_F7) || - (sl->flash_type == STM32_FLASH_TYPE_G0) || - (sl->flash_type == STM32_FLASH_TYPE_G4) || - (sl->flash_type == STM32_FLASH_TYPE_H7) || - (sl->flash_type == STM32_FLASH_TYPE_L4) || - (sl->flash_type == STM32_FLASH_TYPE_L5_U5) || - (sl->flash_type == STM32_FLASH_TYPE_WB_WL)) { - - clear_flash_cr_pg(sl, BANK_1); - if ((sl->flash_type == STM32_FLASH_TYPE_H7 && - sl->chip_flags & CHIP_F_HAS_DUAL_BANK) || - sl->flash_type == STM32_FLASH_TYPE_F1_XL) { - clear_flash_cr_pg(sl, BANK_2); - } - lock_flash(sl); - } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { - uint32_t val; - uint32_t flash_regs_base = get_stm32l0_flash_base(sl); - - // reset lock bits - stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); - val |= (1 << 0) | (1 << 1) | (1 << 2); - stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); - } - - // enable interrupt - if (!stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr)) { - stlink_write_debug32(sl, STLINK_REG_DHCSR, - STLINK_REG_DHCSR_DBGKEY | STLINK_REG_DHCSR_C_DEBUGEN | - (dhcsr & (~STLINK_REG_DHCSR_C_MASKINTS))); - } - - // restore DMA state - set_dma_state(sl, fl, 1); - - return (0); -} diff --git a/src/stlink-lib/flashloader.h b/src/stlink-lib/flashloader.h deleted file mode 100644 index ff16d183c..000000000 --- a/src/stlink-lib/flashloader.h +++ /dev/null @@ -1,13 +0,0 @@ -/* - * File: flashloader.h - * - * Flash loader - */ - -#include -#include - -int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl); -int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t addr, uint8_t* base, uint32_t len); -int stlink_flashloader_stop(stlink_t *sl, flash_loader_t *fl); - From ab286988b4135067b7c45d40f8e15e6b2f69d7a0 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 30 Apr 2023 18:52:14 +0200 Subject: [PATCH 436/503] Corrected preprocessor header includes --- inc/backend.h | 6 +++--- inc/stlink.h | 6 +++--- inc/stm32.h | 6 +++--- inc/stm32flash.h | 6 +++--- inc/version.h.in | 6 +++--- src/st-flash/flash.h | 6 +++--- src/st-util/gdb-remote.h | 6 +++--- src/st-util/gdb-server.h | 6 +++--- src/st-util/semihosting.h | 6 +++--- src/stlink-gui/gui.h | 6 +++--- src/stlink-lib/calculate.h | 6 +++--- src/stlink-lib/chipid.h | 6 +++--- src/stlink-lib/commands.h | 6 +++--- src/stlink-lib/common.h | 6 +++--- src/stlink-lib/common_flash.h | 7 ++++--- src/stlink-lib/flash_loader.h | 6 +++--- src/stlink-lib/helper.h | 6 +++--- src/stlink-lib/libusb_settings.h | 6 +++--- src/stlink-lib/logging.h | 6 +++--- src/stlink-lib/map_file.h | 6 +++--- src/stlink-lib/md5.h | 11 +++++++++++ src/stlink-lib/option_bytes.h | 5 +++++ src/stlink-lib/reg.h | 6 +++--- src/stlink-lib/sg.h | 6 +++--- src/stlink-lib/usb.h | 6 +++--- src/win32/getopt/getopt.h | 6 +++--- src/win32/mmap.h | 8 ++++---- src/win32/sys_time.h | 10 ++++++---- src/win32/unistd/unistd.h | 6 +++--- 29 files changed, 102 insertions(+), 83 deletions(-) diff --git a/inc/backend.h b/inc/backend.h index a45dccd82..abbf4bbf0 100644 --- a/inc/backend.h +++ b/inc/backend.h @@ -1,5 +1,5 @@ -#ifndef STLINK_BACKEND_H_ -#define STLINK_BACKEND_H_ +#ifndef BACKEND_H_ +#define BACKEND_H_ typedef struct _stlink_backend { void (*close) (stlink_t * sl); @@ -34,4 +34,4 @@ int (*trace_read) (stlink_t * sl, uint8_t* buf, size_t size); } stlink_backend_t; -#endif // STLINK_BACKEND_H_ +#endif // BACKEND_H_ diff --git a/inc/stlink.h b/inc/stlink.h index b9379e03d..2a192876f 100644 --- a/inc/stlink.h +++ b/inc/stlink.h @@ -6,8 +6,8 @@ * regardless of how the backend does the work.... */ -#ifndef STLINK_H -#define STLINK_H +#ifndef STLINK_H_ +#define STLINK_H_ #include #include @@ -311,4 +311,4 @@ int stlink_target_connect(stlink_t *sl, enum connect_type connect); } #endif -#endif // STLINK_H +#endif // STLINK_H_ diff --git a/inc/stm32.h b/inc/stm32.h index d3c4e5512..abc7f1ded 100644 --- a/inc/stm32.h +++ b/inc/stm32.h @@ -4,8 +4,8 @@ * STM32-specific defines & identification parametres */ -#ifndef STM32_H -#define STM32_H +#ifndef STM32_H_ +#define STM32_H_ /* STM32 Cortex-M core ids (CPUTAPID) */ enum stm32_core_id { @@ -217,4 +217,4 @@ enum stm32_chipids { #define STM32L5_PWR_CR1 0x40007000 // RM0438, p. 93,324 #define STM32L5_PWR_CR1_VOS 9 -#endif // STM32_H +#endif // STM32_H_ diff --git a/inc/stm32flash.h b/inc/stm32flash.h index 07f824837..f5f662cb6 100644 --- a/inc/stm32flash.h +++ b/inc/stm32flash.h @@ -1,5 +1,5 @@ -#ifndef STM32FLASH_H -#define STM32FLASH_H +#ifndef STM32FLASH_H_ +#define STM32FLASH_H_ /* stm32f FPEC flash controller interface, pm0063 manual */ // STM32F05x is identical, based on RM0091 (DM00031936, Doc ID 018940 Rev 2, August 2012) @@ -378,4 +378,4 @@ #define FLASH_H7_OPTSR_CUR (FLASH_H7_REGS_ADDR + 0x1c) #define FLASH_H7_OPTCCR (FLASH_H7_REGS_ADDR + 0x24) -#endif // STM32FLASH_H +#endif // STM32FLASH_H_ diff --git a/inc/version.h.in b/inc/version.h.in index 66159e0e5..b5ccd6e31 100644 --- a/inc/version.h.in +++ b/inc/version.h.in @@ -1,9 +1,9 @@ -#ifndef STLINK_VERSION_H_ -#define STLINK_VERSION_H_ +#ifndef VERSION_H_ +#define VERSION_H_ #define STLINK_VERSION "@PROJECT_VERSION@" #define STLINK_VERSION_MAJOR @PROJECT_VERSION_MAJOR@ #define STLINK_VERSION_MINOR @PROJECT_VERSION_MINOR@ #define STLINK_VERSION_PATCH @PROJECT_VERSION_PATCH@ -#endif // STLINK_VERSION_H_ +#endif // VERSION_H_ diff --git a/src/st-flash/flash.h b/src/st-flash/flash.h index f3d431d65..aab57878f 100644 --- a/src/st-flash/flash.h +++ b/src/st-flash/flash.h @@ -1,5 +1,5 @@ -#ifndef STLINK_TOOLS_FLASH_H_ -#define STLINK_TOOLS_FLASH_H_ +#ifndef FLASH_H_ +#define FLASH_H_ #include @@ -33,4 +33,4 @@ struct flash_opts { int flash_get_opts(struct flash_opts* o, int ac, char** av); -#endif // STLINK_FLASH_H_ +#endif // FLASH_H_ diff --git a/src/st-util/gdb-remote.h b/src/st-util/gdb-remote.h index 6e76746b7..bcf1dbd01 100644 --- a/src/st-util/gdb-remote.h +++ b/src/st-util/gdb-remote.h @@ -1,8 +1,8 @@ -#ifndef _GDB_REMOTE_H_ -#define _GDB_REMOTE_H_ +#ifndef GDB_REMOTE_H_ +#define GDB_REMOTE_H_ int gdb_send_packet(int fd, char* data); int gdb_recv_packet(int fd, char** buffer); int gdb_check_for_interrupt(int fd); -#endif // _GDB_REMOTE_H_ +#endif // GDB_REMOTE_H_ diff --git a/src/st-util/gdb-server.h b/src/st-util/gdb-server.h index b50a7941d..3fbb16dad 100644 --- a/src/st-util/gdb-server.h +++ b/src/st-util/gdb-server.h @@ -1,5 +1,5 @@ -#ifndef _GDB_SERVER_H -#define _GDB_SERVER_H +#ifndef GDB_SERVER_H_ +#define GDB_SERVER_H_ #define STRINGIFY_inner(name) #name #define STRINGIFY(name) STRINGIFY_inner(name) @@ -8,4 +8,4 @@ #define DEBUG_LOGGING_LEVEL 100 #define DEFAULT_GDB_LISTEN_PORT 4242 -#endif // _GDB_SERVER_H +#endif // GDB_SERVER_H_ diff --git a/src/st-util/semihosting.h b/src/st-util/semihosting.h index 8c1ac15f0..2e34b4307 100644 --- a/src/st-util/semihosting.h +++ b/src/st-util/semihosting.h @@ -1,5 +1,5 @@ -#ifndef _SEMIHOSTING_H_ -#define _SEMIHOSTING_H_ +#ifndef SEMIHOSTING_H_ +#define SEMIHOSTING_H_ #include @@ -31,4 +31,4 @@ int do_semihosting(stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret); -#endif // _SEMIHOSTING_H_ +#endif // SEMIHOSTING_H_ diff --git a/src/stlink-gui/gui.h b/src/stlink-gui/gui.h index b3d5dfff8..f29ee5031 100644 --- a/src/stlink-gui/gui.h +++ b/src/stlink-gui/gui.h @@ -1,5 +1,5 @@ -#ifndef __STLINK_GUI_H__ -#define __STLINK_GUI_H__ +#ifndef GUI_H_ +#define GUI_H_ #include @@ -89,4 +89,4 @@ struct _STlinkGUIClass { GType stlink_gui_get_type(void); int export_to_file(const char*filename, const struct mem_t flash_mem); -#endif // __STLINK_GUI_H__ +#endif // GUI_H_ diff --git a/src/stlink-lib/calculate.h b/src/stlink-lib/calculate.h index 64dfb51b2..beb064297 100644 --- a/src/stlink-lib/calculate.h +++ b/src/stlink-lib/calculate.h @@ -4,12 +4,12 @@ * Calculation of sector numbers and pages */ -#ifndef CALCULATE_H -#define CALCULATE_H +#ifndef CALCULATE_H_ +#define CALCULATE_H_ uint32_t calculate_F4_sectornum(uint32_t); uint32_t calculate_F7_sectornum(uint32_t); uint32_t calculate_H7_sectornum(stlink_t *, uint32_t, unsigned); uint32_t calculate_L4_page(stlink_t *, uint32_t); -#endif // CALCULATE_H +#endif // CALCULATE_H_ diff --git a/src/stlink-lib/chipid.h b/src/stlink-lib/chipid.h index 1eae2cc34..b93a3f2d6 100644 --- a/src/stlink-lib/chipid.h +++ b/src/stlink-lib/chipid.h @@ -1,5 +1,5 @@ -#ifndef STLINK_CHIPID_H_ -#define STLINK_CHIPID_H_ +#ifndef CHIPID_H_ +#define CHIPID_H_ #include #include @@ -24,4 +24,4 @@ struct stlink_chipid_params { struct stlink_chipid_params *stlink_chipid_get_params(uint32_t chipid); void init_chipids(char *dir_to_scan); -#endif // STLINK_CHIPID_H_ +#endif // CHIPID_H_ diff --git a/src/stlink-lib/commands.h b/src/stlink-lib/commands.h index 136adf80e..4fa919858 100644 --- a/src/stlink-lib/commands.h +++ b/src/stlink-lib/commands.h @@ -1,5 +1,5 @@ -#ifndef STLINK_COMMANDS_H_ -#define STLINK_COMMANDS_H_ +#ifndef COMMANDS_H_ +#define COMMANDS_H_ enum stlink_commands { STLINK_GET_VERSION = 0xF1, @@ -54,4 +54,4 @@ enum stlink_dfu_commands { STLINK_DFU_EXIT = 0x07 }; -#endif // STLINK_COMMANDS_H_ +#endif // COMMANDS_H_ diff --git a/src/stlink-lib/common.h b/src/stlink-lib/common.h index dd6cf95b2..902493610 100644 --- a/src/stlink-lib/common.h +++ b/src/stlink-lib/common.h @@ -4,12 +4,12 @@ * General helper functions */ -#ifndef COMMON_H -#define COMMON_H +#ifndef COMMON_H_ +#define COMMON_H_ int check_file(stlink_t *, mapped_file_t *, stm32_addr_t); void md5_calculate(mapped_file_t *); void stlink_checksum(mapped_file_t *); void stlink_fwrite_finalize(stlink_t *, stm32_addr_t); -#endif // COMMON_H +#endif // COMMON_H_ diff --git a/src/stlink-lib/common_flash.h b/src/stlink-lib/common_flash.h index 3b6b0404a..269f8196e 100644 --- a/src/stlink-lib/common_flash.h +++ b/src/stlink-lib/common_flash.h @@ -4,8 +4,8 @@ * Flash operations */ -#ifndef COMMON_FLASH_H -#define COMMON_FLASH_H +#ifndef COMMON_FLASH_H_ +#define COMMON_FLASH_H_ void lock_flash(stlink_t *); void clear_flash_error(stlink_t *); @@ -24,4 +24,5 @@ void clear_flash_cr_pg(stlink_t *, unsigned); uint32_t read_flash_cr(stlink_t *, unsigned); uint32_t get_stm32l0_flash_base(stlink_t *); -#endif // STLINK_H + +#endif // COMMON_FLASH_H_ diff --git a/src/stlink-lib/flash_loader.h b/src/stlink-lib/flash_loader.h index 0d39a9a48..781fab74a 100644 --- a/src/stlink-lib/flash_loader.h +++ b/src/stlink-lib/flash_loader.h @@ -4,8 +4,8 @@ * Flash loader */ -#ifndef STLINK_FLASH_LOADER_H_ -#define STLINK_FLASH_LOADER_H_ +#ifndef FLASH_LOADER_H_ +#define FLASH_LOADER_H_ #include #include @@ -21,4 +21,4 @@ int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl); int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t addr, uint8_t* base, uint32_t len); int stlink_flashloader_stop(stlink_t *sl, flash_loader_t *fl); -#endif // STLINK_FLASH_LOADER_H_ +#endif // FLASH_LOADER_H_ diff --git a/src/stlink-lib/helper.h b/src/stlink-lib/helper.h index 96467377a..58023aff2 100644 --- a/src/stlink-lib/helper.h +++ b/src/stlink-lib/helper.h @@ -1,8 +1,8 @@ -#ifndef SYS_HELPER_H -#define SYS_HELPER_H +#ifndef HELPER_H_ +#define HELPER_H_ unsigned time_ms(); int arg_parse_freq(const char *str); -#endif /* SYS_HELPER_H */ +#endif // HELPER_H_ diff --git a/src/stlink-lib/libusb_settings.h b/src/stlink-lib/libusb_settings.h index 3777f720b..639f9e4a4 100644 --- a/src/stlink-lib/libusb_settings.h +++ b/src/stlink-lib/libusb_settings.h @@ -1,5 +1,5 @@ -#ifndef LIBUSB_SETTINGS_H -#define LIBUSB_SETTINGS_H +#ifndef LIBUSB_SETTINGS_H_ +#define LIBUSB_SETTINGS_H_ #include @@ -44,4 +44,4 @@ #error unsupported libusb version #endif -#endif // LIBUSB_SETTINGS_H +#endif // LIBUSB_SETTINGS_H_ diff --git a/src/stlink-lib/logging.h b/src/stlink-lib/logging.h index 7f3994492..7510d573e 100644 --- a/src/stlink-lib/logging.h +++ b/src/stlink-lib/logging.h @@ -2,8 +2,8 @@ * Ugly, low performance, configurable level, logging "framework" */ -#ifndef UGLYLOGGING_H -#define UGLYLOGGING_H +#ifndef LOGGING_H_ +#define LOGGING_H_ #ifdef __cplusplus extern "C" { @@ -45,4 +45,4 @@ int ugly_libusb_log_level(enum ugly_loglevel v); } #endif -#endif // UGLYLOGGING_H +#endif // LOGGING_H_ diff --git a/src/stlink-lib/map_file.h b/src/stlink-lib/map_file.h index f50a201f0..d69f6c3b5 100644 --- a/src/stlink-lib/map_file.h +++ b/src/stlink-lib/map_file.h @@ -4,8 +4,8 @@ * File mapping */ -#ifndef MAP_FILE_H -#define MAP_FILE_H +#ifndef MAP_FILE_H_ +#define MAP_FILE_H_ #ifndef O_BINARY #define O_BINARY 0 @@ -29,4 +29,4 @@ typedef struct mapped_file { int map_file(mapped_file_t *, const char *); void unmap_file(mapped_file_t *); -#endif // MAP_FILE_H +#endif // MAP_FILE_H_ diff --git a/src/stlink-lib/md5.h b/src/stlink-lib/md5.h index a69d7fc6b..7b853a4f6 100644 --- a/src/stlink-lib/md5.h +++ b/src/stlink-lib/md5.h @@ -5,6 +5,15 @@ * This is free and unencumbered software released into the public domain - June 2013 - waterjuice.org */ +/* + * File: md5.h + * + * MD5 hash function + */ + +#ifndef MD5_H_ +#define MD5_H_ + #pragma once #include @@ -61,3 +70,5 @@ void Md5Finalise(Md5Context* Context /* [in out] */, MD5_HASH* Digest /* [in] */ * Calculates the MD5 hash of the buffer. */ void Md5Calculate(void const* Buffer /* [in] */, uint32_t BufferSize /* [in] */, MD5_HASH* Digest /* [in] */); + +#endif // MD5_H_ \ No newline at end of file diff --git a/src/stlink-lib/option_bytes.h b/src/stlink-lib/option_bytes.h index b9f88c508..481a69f0a 100644 --- a/src/stlink-lib/option_bytes.h +++ b/src/stlink-lib/option_bytes.h @@ -4,6 +4,9 @@ * Read and write option bytes and option control registers */ +#ifndef OPTION_BYTES_H_ +#define OPTION_BYTES_H_ + #include #include @@ -19,3 +22,5 @@ int stlink_write_option_control_register1_32(stlink_t *sl, uint32_t option_cr1); int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t len); int stlink_fwrite_option_bytes(stlink_t *sl, const char* path, stm32_addr_t addr); + +#endif // OPTION_BYTES_H_ \ No newline at end of file diff --git a/src/stlink-lib/reg.h b/src/stlink-lib/reg.h index b581a269c..2046f8a6a 100644 --- a/src/stlink-lib/reg.h +++ b/src/stlink-lib/reg.h @@ -1,5 +1,5 @@ -#ifndef STLINK_REG_H_ -#define STLINK_REG_H_ +#ifndef REG_H_ +#define REG_H_ #define STLINK_REG_CM3_CPUID 0xE000ED00 @@ -123,4 +123,4 @@ #define STLINK_REG_CM7_ICIALLU 0xE000EF50 #define STLINK_REG_CM7_CCSIDR 0xE000ED80 -#endif // STLINK_REG_H_ +#endif // REG_H_ diff --git a/src/stlink-lib/sg.h b/src/stlink-lib/sg.h index 212d03b27..e30043fcc 100644 --- a/src/stlink-lib/sg.h +++ b/src/stlink-lib/sg.h @@ -3,8 +3,8 @@ * Author: karl */ -#ifndef STLINK_SG_H -#define STLINK_SG_H +#ifndef SG_H_ +#define SG_H_ #include #include @@ -56,4 +56,4 @@ struct stlink_libsg { stlink_t* stlink_v1_open(const int verbose, int reset); -#endif // STLINK_SG_H +#endif // SG_H_ diff --git a/src/stlink-lib/usb.h b/src/stlink-lib/usb.h index 3f4b71e51..ff6f9088e 100644 --- a/src/stlink-lib/usb.h +++ b/src/stlink-lib/usb.h @@ -3,8 +3,8 @@ * Author: karl */ -#ifndef STLINK_USB_H -#define STLINK_USB_H +#ifndef USB_H_ +#define USB_H_ #include @@ -70,4 +70,4 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, enum connect_type connect, size_t stlink_probe_usb(stlink_t **stdevs[], enum connect_type connect, int freq); void stlink_probe_usb_free(stlink_t **stdevs[], size_t size); -#endif // STLINK_USB_H +#endif // USB_H_ diff --git a/src/win32/getopt/getopt.h b/src/win32/getopt/getopt.h index 3aaf73bed..2a1bd735b 100644 --- a/src/win32/getopt/getopt.h +++ b/src/win32/getopt/getopt.h @@ -1,5 +1,5 @@ -#ifndef INCLUDED_GETOPT_PORT_H -#define INCLUDED_GETOPT_PORT_H +#ifndef GETOPT_H_ +#define GETOPT_H_ #if defined(__cplusplus) extern "C" { @@ -38,4 +38,4 @@ int getopt_long(int argc, } #endif -#endif // INCLUDED_GETOPT_PORT_H +#endif // GETOPT_H_ diff --git a/src/win32/mmap.h b/src/win32/mmap.h index 06079a9bc..ff01f4286 100644 --- a/src/win32/mmap.h +++ b/src/win32/mmap.h @@ -1,5 +1,5 @@ -#ifndef STLINK_MMAP_H -#define STLINK_MMAP_H +#ifndef MMAP_H_ +#define MMAP_H_ #ifdef STLINK_HAVE_SYS_MMAN_H #include @@ -16,6 +16,6 @@ void *mmap(void *addr, size_t len, int prot, int flags, int fd, long long offset); int munmap(void *addr, size_t len); -#endif /* HAVE_SYS_MMAN_H */ +#endif // STLINK_HAVE_SYS_MMAN_H -#endif /* STLINK_MMAP_H */ +#endif // MMAP_H_ diff --git a/src/win32/sys_time.h b/src/win32/sys_time.h index d314509b7..cb767fc31 100644 --- a/src/win32/sys_time.h +++ b/src/win32/sys_time.h @@ -1,8 +1,10 @@ -#ifndef STLINK_TIME_H -#define STLINK_TIME_H +#ifndef SYS_TIME_H_ +#define SYS_TIME_H_ #ifdef STLINK_HAVE_SYS_TIME_H + #include + #else #include @@ -14,6 +16,6 @@ struct timezone { int gettimeofday(struct timeval *tv, struct timezone *tz); -#endif /* STLINK_HAVE_SYS_TIME_H */ +#endif // STLINK_HAVE_SYS_TIME_H -#endif /* STLINK_TIME_H */ +#endif // SYS_TIME_H_ diff --git a/src/win32/unistd/unistd.h b/src/win32/unistd/unistd.h index 389c44664..b8a3db746 100644 --- a/src/win32/unistd/unistd.h +++ b/src/win32/unistd/unistd.h @@ -1,5 +1,5 @@ -#ifndef _UNISTD_H -#define _UNISTD_H 1 +#ifndef UNISTD_H_ +#define UNISTD_H_ /* * This file intended to serve as a drop-in replacement for unistd.h on Windows @@ -72,4 +72,4 @@ typedef unsigned __int64 uint64_t; int usleep(unsigned int waitTime); #endif -#endif // _UNISTD_H +#endif // UNISTD_H_ From 7c2c953ff6051c2adfdd5aa8f312bc98f9cb627c Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 30 Apr 2023 19:21:17 +0200 Subject: [PATCH 437/503] Unified chipid enum naming for L0 series --- config/chips/L0xxx_Cat_1.chip | 2 +- config/chips/L0xxx_Cat_3.chip | 2 +- inc/stm32.h | 4 ++-- src/stlink-lib/common_flash.c | 6 +++--- src/stlink-lib/flash_loader.c | 8 ++++---- 5 files changed, 11 insertions(+), 11 deletions(-) diff --git a/config/chips/L0xxx_Cat_1.chip b/config/chips/L0xxx_Cat_1.chip index 2cce4e23c..2c6bea0eb 100644 --- a/config/chips/L0xxx_Cat_1.chip +++ b/config/chips/L0xxx_Cat_1.chip @@ -2,7 +2,7 @@ # dev_type STM32L0xxx_Cat_1 ref_manual_id 0451 // also RM0377 -chip_id 0x457 // STM32_CHIPID_L011 +chip_id 0x457 // STM32_CHIPID_L0_CAT1 flash_type L0_L1 flash_size_reg 0x1ff8007c flash_pagesize 0x80 // 128 B diff --git a/config/chips/L0xxx_Cat_3.chip b/config/chips/L0xxx_Cat_3.chip index a04dc8376..e6ad3586a 100644 --- a/config/chips/L0xxx_Cat_3.chip +++ b/config/chips/L0xxx_Cat_3.chip @@ -2,7 +2,7 @@ # dev_type STM32L0xxx_Cat_3 ref_manual_id 0451 // also RM0367 & RM0377 -chip_id 0x417 // STM32_CHIPID_L0 +chip_id 0x417 // STM32_CHIPID_L0_CAT3 flash_type L0_L1 flash_size_reg 0x1ff8007c flash_pagesize 0x80 // 128 B diff --git a/inc/stm32.h b/inc/stm32.h index abc7f1ded..ab80ff25e 100644 --- a/inc/stm32.h +++ b/inc/stm32.h @@ -76,7 +76,7 @@ enum stm32_chipids { STM32_CHIPID_F1_HD = 0x414, /* high density */ STM32_CHIPID_L4 = 0x415, STM32_CHIPID_L1_MD = 0x416, /* medium density */ - STM32_CHIPID_L0 = 0x417, + STM32_CHIPID_L0_CAT3 = 0x417, STM32_CHIPID_F1_CONN = 0x418, /* connectivity line */ STM32_CHIPID_F4_HD = 0x419, /* high density */ STM32_CHIPID_F1_VL_MD_LD = 0x420, /* value line medium & low density */ @@ -110,7 +110,7 @@ enum stm32_chipids { STM32_CHIPID_F76xxx = 0x451, STM32_CHIPID_F72xxx = 0x452, /* Nucleo F722ZE board */ STM32_CHIPID_G0_CAT4 = 0x456, /* G051/G061 */ - STM32_CHIPID_L011 = 0x457, + STM32_CHIPID_L0_CAT1 = 0x457, STM32_CHIPID_F410 = 0x458, STM32_CHIPID_G0_CAT2 = 0x460, /* G07x/G08x */ STM32_CHIPID_L496x_L4A6x = 0x461, diff --git a/src/stlink-lib/common_flash.c b/src/stlink-lib/common_flash.c index 740c93690..dbae1c694 100644 --- a/src/stlink-lib/common_flash.c +++ b/src/stlink-lib/common_flash.c @@ -12,10 +12,10 @@ uint32_t get_stm32l0_flash_base(stlink_t *sl) { switch (sl->chip_id) { - case STM32_CHIPID_L0: - case STM32_CHIPID_L0_CAT5: + case STM32_CHIPID_L0_CAT1: case STM32_CHIPID_L0_CAT2: - case STM32_CHIPID_L011: + case STM32_CHIPID_L0_CAT3: + case STM32_CHIPID_L0_CAT5: return (STM32L0_FLASH_REGS_ADDR); case STM32_CHIPID_L1_CAT2: diff --git a/src/stlink-lib/flash_loader.c b/src/stlink-lib/flash_loader.c index 852ba6c20..c46392cbe 100644 --- a/src/stlink-lib/flash_loader.c +++ b/src/stlink-lib/flash_loader.c @@ -238,10 +238,10 @@ int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* sl->chip_id == STM32_CHIPID_L1_MD_PLUS || sl->chip_id == STM32_CHIPID_L1_MD_PLUS_HD || sl->chip_id == STM32_CHIPID_L152_RE || - sl->chip_id == STM32_CHIPID_L011 || - sl->chip_id == STM32_CHIPID_L0 || - sl->chip_id == STM32_CHIPID_L0_CAT5 || - sl->chip_id == STM32_CHIPID_L0_CAT2) { + sl->chip_id == STM32_CHIPID_L0_CAT1 || + sl->chip_id == STM32_CHIPID_L0_CAT2 || + sl->chip_id == STM32_CHIPID_L0_CAT3 || + sl->chip_id == STM32_CHIPID_L0_CAT5) { loader_code = loader_code_stm32lx; loader_size = sizeof(loader_code_stm32lx); } else if (sl->core_id == STM32_CORE_ID_M3_r1p1_SWD || From 823187216afbaccfcfe07da4c3c5739b65820239 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 30 Apr 2023 20:46:37 +0200 Subject: [PATCH 438/503] st-flash: auto-reset after mass erase --- flashloaders/Makefile | 4 ++-- flashloaders/linker.ld | 4 ++-- src/st-flash/flash.c | 6 ++++++ src/stlink-lib/flash_loader.c | 2 +- 4 files changed, 11 insertions(+), 5 deletions(-) diff --git a/flashloaders/Makefile b/flashloaders/Makefile index 8b01d5293..68ce5a881 100644 --- a/flashloaders/Makefile +++ b/flashloaders/Makefile @@ -1,5 +1,5 @@ -# The flash loader code cannot be compiled by the system gcc. This -# makefile use arm-none-eabi-gcc for this purpose +# The flash loader code cannot be compiled by the system gcc. +# This makefile uses arm-none-eabi-gcc for this purpose. CROSS_COMPILE ?= arm-none-eabi- diff --git a/flashloaders/linker.ld b/flashloaders/linker.ld index 7267fe10f..2d8c192ce 100644 --- a/flashloaders/linker.ld +++ b/flashloaders/linker.ld @@ -1,9 +1,9 @@ /* Entry Point */ -ENTRY( copy ) +ENTRY(copy) /* Specify the memory areas */ MEMORY { - RAM ( xrw) : ORIGIN = 0x20000000 , LENGTH = 64K + RAM (xrw) : ORIGIN = 0x20000000 , LENGTH = 64K } diff --git a/src/st-flash/flash.c b/src/st-flash/flash.c index d7d17f66f..bbb52d80c 100644 --- a/src/st-flash/flash.c +++ b/src/st-flash/flash.c @@ -188,6 +188,12 @@ int main(int ac, char** av) { goto on_error; } printf("Mass erase completed successfully.\n"); + + // reset after erase + if (stlink_reset(sl, RESET_AUTO)) { + printf("Failed to reset device\n"); + goto on_error; + } } else if (o.cmd == CMD_RESET) { diff --git a/src/stlink-lib/flash_loader.c b/src/stlink-lib/flash_loader.c index c46392cbe..ebdf0a44e 100644 --- a/src/stlink-lib/flash_loader.c +++ b/src/stlink-lib/flash_loader.c @@ -391,7 +391,7 @@ int stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t targe * firmware size. */ if ((int32_t)rr.r[2] > 0 || (int32_t)rr.r[2] < -7) { - ELOG("Write error\n"); + ELOG("Flash loader write error\n"); goto error; } From 800c8616fbc8115716258b2140b667a643beadc8 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 30 Apr 2023 22:32:59 +0200 Subject: [PATCH 439/503] Unified #define names for STM32 devices --- inc/stm32flash.h | 320 +++++++++++++++++----------------- src/stlink-lib/calculate.c | 4 +- src/stlink-lib/common.c | 8 +- src/stlink-lib/common_flash.c | 278 ++++++++++++++--------------- src/stlink-lib/flash_loader.c | 16 +- src/stlink-lib/option_bytes.c | 58 +++--- 6 files changed, 342 insertions(+), 342 deletions(-) diff --git a/inc/stm32flash.h b/inc/stm32flash.h index f5f662cb6..ccbc0289d 100644 --- a/inc/stm32flash.h +++ b/inc/stm32flash.h @@ -59,206 +59,206 @@ #define FLASH_CR_OPTWRE 9 #define FLASH_CR_OBL_LAUNCH 13 -#define STM32L_FLASH_REGS_ADDR ((uint32_t)0x40023c00) -#define STM32L_FLASH_ACR (STM32L_FLASH_REGS_ADDR + 0x00) -#define STM32L_FLASH_PECR (STM32L_FLASH_REGS_ADDR + 0x04) -#define STM32L_FLASH_PDKEYR (STM32L_FLASH_REGS_ADDR + 0x08) -#define STM32L_FLASH_PEKEYR (STM32L_FLASH_REGS_ADDR + 0x0c) -#define STM32L_FLASH_PRGKEYR (STM32L_FLASH_REGS_ADDR + 0x10) -#define STM32L_FLASH_OPTKEYR (STM32L_FLASH_REGS_ADDR + 0x14) -#define STM32L_FLASH_SR (STM32L_FLASH_REGS_ADDR + 0x18) -#define STM32L_FLASH_OBR (STM32L_FLASH_REGS_ADDR + 0x1c) -#define STM32L_FLASH_WRPR (STM32L_FLASH_REGS_ADDR + 0x20) +#define FLASH_Lx_REGS_ADDR ((uint32_t)0x40023c00) +#define FLASH_Lx_ACR (FLASH_Lx_REGS_ADDR + 0x00) +#define FLASH_Lx_PECR (FLASH_Lx_REGS_ADDR + 0x04) +#define FLASH_Lx_PDKEYR (FLASH_Lx_REGS_ADDR + 0x08) +#define FLASH_Lx_PEKEYR (FLASH_Lx_REGS_ADDR + 0x0c) +#define FLASH_Lx_PRGKEYR (FLASH_Lx_REGS_ADDR + 0x10) +#define FLASH_Lx_OPTKEYR (FLASH_Lx_REGS_ADDR + 0x14) +#define FLASH_Lx_SR (FLASH_Lx_REGS_ADDR + 0x18) +#define FLASH_Lx_OBR (FLASH_Lx_REGS_ADDR + 0x1c) +#define FLASH_Lx_WRPR (FLASH_Lx_REGS_ADDR + 0x20) #define FLASH_L1_FPRG 10 #define FLASH_L1_PROG 3 // Flash registers common to STM32G0 and STM32G4 series (RM0440, p. 146) -#define STM32Gx_FLASH_REGS_ADDR ((uint32_t)0x40022000) -#define STM32Gx_FLASH_ACR (STM32Gx_FLASH_REGS_ADDR + 0x00) -#define STM32Gx_FLASH_KEYR (STM32Gx_FLASH_REGS_ADDR + 0x08) -#define STM32Gx_FLASH_OPTKEYR (STM32Gx_FLASH_REGS_ADDR + 0x0c) -#define STM32Gx_FLASH_SR (STM32Gx_FLASH_REGS_ADDR + 0x10) -#define STM32Gx_FLASH_CR (STM32Gx_FLASH_REGS_ADDR + 0x14) -#define STM32Gx_FLASH_ECCR (STM32Gx_FLASH_REGS_ADDR + 0x18) -#define STM32Gx_FLASH_OPTR (STM32Gx_FLASH_REGS_ADDR + 0x20) +#define FLASH_Gx_REGS_ADDR ((uint32_t)0x40022000) +#define FLASH_Gx_ACR (FLASH_Gx_REGS_ADDR + 0x00) +#define FLASH_Gx_KEYR (FLASH_Gx_REGS_ADDR + 0x08) +#define FLASH_Gx_OPTKEYR (FLASH_Gx_REGS_ADDR + 0x0c) +#define FLASH_Gx_SR (FLASH_Gx_REGS_ADDR + 0x10) +#define FLASH_Gx_CR (FLASH_Gx_REGS_ADDR + 0x14) +#define FLASH_Gx_ECCR (FLASH_Gx_REGS_ADDR + 0x18) +#define FLASH_Gx_OPTR (FLASH_Gx_REGS_ADDR + 0x20) // G0 (RM0444 Table 1, sec 3.7) // Mostly the same as G4 chips, but the notation // varies a bit after the 'OPTR' register. -#define STM32G0_FLASH_REGS_ADDR (STM32Gx_FLASH_REGS_ADDR) -#define STM32G0_FLASH_PCROP1ASR (STM32G0_FLASH_REGS_ADDR + 0x24) -#define STM32G0_FLASH_PCROP1AER (STM32G0_FLASH_REGS_ADDR + 0x28) -#define STM32G0_FLASH_WRP1AR (STM32G0_FLASH_REGS_ADDR + 0x2C) -#define STM32G0_FLASH_WRP1BR (STM32G0_FLASH_REGS_ADDR + 0x30) -#define STM32G0_FLASH_PCROP1BSR (STM32G0_FLASH_REGS_ADDR + 0x34) -#define STM32G0_FLASH_PCROP1BER (STM32G0_FLASH_REGS_ADDR + 0x38) -#define STM32G0_FLASH_SECR (STM32G0_FLASH_REGS_ADDR + 0x80) +#define FLASH_G0_REGS_ADDR (FLASH_Gx_REGS_ADDR) +#define FLASH_G0_PCROP1ASR (FLASH_G0_REGS_ADDR + 0x24) +#define FLASH_G0_PCROP1AER (FLASH_G0_REGS_ADDR + 0x28) +#define FLASH_G0_WRP1AR (FLASH_G0_REGS_ADDR + 0x2C) +#define FLASH_G0_WRP1BR (FLASH_G0_REGS_ADDR + 0x30) +#define FLASH_G0_PCROP1BSR (FLASH_G0_REGS_ADDR + 0x34) +#define FLASH_G0_PCROP1BER (FLASH_G0_REGS_ADDR + 0x38) +#define FLASH_G0_SECR (FLASH_G0_REGS_ADDR + 0x80) // G4 (RM0440 Table 17, sec 3.7.19) // Mostly the same as STM32G0 chips, but there are a few extra // registers because 'cat 3' devices can have two Flash banks. -#define STM32G4_FLASH_REGS_ADDR (STM32Gx_FLASH_REGS_ADDR) -#define STM32G4_FLASH_PDKEYR (STM32G4_FLASH_REGS_ADDR + 0x04) -#define STM32G4_FLASH_PCROP1SR (STM32G4_FLASH_REGS_ADDR + 0x24) -#define STM32G4_FLASH_PCROP1ER (STM32G4_FLASH_REGS_ADDR + 0x28) -#define STM32G4_FLASH_WRP1AR (STM32G4_FLASH_REGS_ADDR + 0x2C) -#define STM32G4_FLASH_WRP1BR (STM32G4_FLASH_REGS_ADDR + 0x30) -#define STM32G4_FLASH_PCROP2SR (STM32G4_FLASH_REGS_ADDR + 0x44) -#define STM32G4_FLASH_PCROP2ER (STM32G4_FLASH_REGS_ADDR + 0x48) -#define STM32G4_FLASH_WRP2AR (STM32G4_FLASH_REGS_ADDR + 0x4C) -#define STM32G4_FLASH_WRP2BR (STM32G4_FLASH_REGS_ADDR + 0x50) -#define STM32G4_FLASH_SEC1R (STM32G4_FLASH_REGS_ADDR + 0x70) -#define STM32G4_FLASH_SEC2R (STM32G4_FLASH_REGS_ADDR + 0x74) +#define FLASH_G4_REGS_ADDR (FLASH_Gx_REGS_ADDR) +#define FLASH_G4_PDKEYR (FLASH_G4_REGS_ADDR + 0x04) +#define FLASH_G4_PCROP1SR (FLASH_G4_REGS_ADDR + 0x24) +#define FLASH_G4_PCROP1ER (FLASH_G4_REGS_ADDR + 0x28) +#define FLASH_G4_WRP1AR (FLASH_G4_REGS_ADDR + 0x2C) +#define FLASH_G4_WRP1BR (FLASH_G4_REGS_ADDR + 0x30) +#define FLASH_G4_PCROP2SR (FLASH_G4_REGS_ADDR + 0x44) +#define FLASH_G4_PCROP2ER (FLASH_G4_REGS_ADDR + 0x48) +#define FLASH_G4_WRP2AR (FLASH_G4_REGS_ADDR + 0x4C) +#define FLASH_G4_WRP2BR (FLASH_G4_REGS_ADDR + 0x50) +#define FLASH_G4_SEC1R (FLASH_G4_REGS_ADDR + 0x70) +#define FLASH_G4_SEC2R (FLASH_G4_REGS_ADDR + 0x74) // G0/G4 FLASH control register -#define STM32Gx_FLASH_CR_PG (0) /* Program */ -#define STM32Gx_FLASH_CR_PER (1) /* Page erase */ -#define STM32Gx_FLASH_CR_MER1 (2) /* Mass erase */ -#define STM32Gx_FLASH_CR_PNB (3) /* Page number */ -#define STM32G0_FLASH_CR_PNG_LEN (5) /* STM32G0: 5 page number bits */ -#define STM32G4_FLASH_CR_PNG_LEN (7) /* STM32G4: 7 page number bits */ -#define STM32Gx_FLASH_CR_MER2 (15) /* Mass erase (2nd bank)*/ -#define STM32Gx_FLASH_CR_STRT (16) /* Start */ -#define STM32Gx_FLASH_CR_OPTSTRT \ +#define FLASH_Gx_CR_PG (0) /* Program */ +#define FLASH_Gx_CR_PER (1) /* Page erase */ +#define FLASH_Gx_CR_MER1 (2) /* Mass erase */ +#define FLASH_Gx_CR_PNB (3) /* Page number */ +#define FLASH_G0_CR_PNG_LEN (5) /* STM32G0: 5 page number bits */ +#define FLASH_G4_CR_PNG_LEN (7) /* STM32G4: 7 page number bits */ +#define FLASH_Gx_CR_MER2 (15) /* Mass erase (2nd bank)*/ +#define FLASH_Gx_CR_STRT (16) /* Start */ +#define FLASH_Gx_CR_OPTSTRT \ (17) /* Start of modification of option bytes */ -#define STM32Gx_FLASH_CR_FSTPG (18) /* Fast programming */ -#define STM32Gx_FLASH_CR_EOPIE (24) /* End of operation interrupt enable */ -#define STM32Gx_FLASH_CR_ERRIE (25) /* Error interrupt enable */ -#define STM32Gx_FLASH_CR_OBL_LAUNCH (27) /* Forces the option byte loading */ -#define STM32Gx_FLASH_CR_OPTLOCK (30) /* Options Lock */ -#define STM32Gx_FLASH_CR_LOCK (31) /* FLASH_CR Lock */ +#define FLASH_Gx_CR_FSTPG (18) /* Fast programming */ +#define FLASH_Gx_CR_EOPIE (24) /* End of operation interrupt enable */ +#define FLASH_Gx_CR_ERRIE (25) /* Error interrupt enable */ +#define FLASH_Gx_CR_OBL_LAUNCH (27) /* Forces the option byte loading */ +#define FLASH_Gx_CR_OPTLOCK (30) /* Options Lock */ +#define FLASH_Gx_CR_LOCK (31) /* FLASH_CR Lock */ // G0/G4 FLASH status register -#define STM32Gx_FLASH_SR_ERROR_MASK (0x3fa) -#define STM32Gx_FLASH_SR_PROGERR (3) -#define STM32Gx_FLASH_SR_WRPERR (4) -#define STM32Gx_FLASH_SR_PGAERR (5) -#define STM32Gx_FLASH_SR_BSY (16) /* FLASH_SR Busy */ -#define STM32Gx_FLASH_SR_EOP (0) /* FLASH_EOP End of Operation */ +#define FLASH_Gx_SR_ERROR_MASK (0x3fa) +#define FLASH_Gx_SR_PROGERR (3) +#define FLASH_Gx_SR_WRPERR (4) +#define FLASH_Gx_SR_PGAERR (5) +#define FLASH_Gx_SR_BSY (16) /* FLASH_SR Busy */ +#define FLASH_Gx_SR_EOP (0) /* FLASH_EOP End of Operation */ // G4 FLASH option register -#define STM32G4_FLASH_OPTR_DBANK (22) /* FLASH_OPTR Dual Bank Mode */ +#define FLASH_G4_OPTR_DBANK (22) /* FLASH_OPTR Dual Bank Mode */ // WB (RM0434) -#define STM32WB_FLASH_REGS_ADDR ((uint32_t)0x58004000) -#define STM32WB_FLASH_ACR (STM32WB_FLASH_REGS_ADDR + 0x00) -#define STM32WB_FLASH_KEYR (STM32WB_FLASH_REGS_ADDR + 0x08) -#define STM32WB_FLASH_OPT_KEYR (STM32WB_FLASH_REGS_ADDR + 0x0C) -#define STM32WB_FLASH_SR (STM32WB_FLASH_REGS_ADDR + 0x10) -#define STM32WB_FLASH_CR (STM32WB_FLASH_REGS_ADDR + 0x14) -#define STM32WB_FLASH_ECCR (STM32WB_FLASH_REGS_ADDR + 0x18) -#define STM32WB_FLASH_OPTR (STM32WB_FLASH_REGS_ADDR + 0x20) -#define STM32WB_FLASH_PCROP1ASR (STM32WB_FLASH_REGS_ADDR + 0x24) -#define STM32WB_FLASH_PCROP1AER (STM32WB_FLASH_REGS_ADDR + 0x28) -#define STM32WB_FLASH_WRP1AR (STM32WB_FLASH_REGS_ADDR + 0x2C) -#define STM32WB_FLASH_WRP1BR (STM32WB_FLASH_REGS_ADDR + 0x30) -#define STM32WB_FLASH_PCROP1BSR (STM32WB_FLASH_REGS_ADDR + 0x34) -#define STM32WB_FLASH_PCROP1BER (STM32WB_FLASH_REGS_ADDR + 0x38) -#define STM32WB_FLASH_IPCCBR (STM32WB_FLASH_REGS_ADDR + 0x3C) -#define STM32WB_FLASH_C2ACR (STM32WB_FLASH_REGS_ADDR + 0x5C) -#define STM32WB_FLASH_C2SR (STM32WB_FLASH_REGS_ADDR + 0x60) -#define STM32WB_FLASH_C2CR (STM32WB_FLASH_REGS_ADDR + 0x64) -#define STM32WB_FLASH_SFR (STM32WB_FLASH_REGS_ADDR + 0x80) -#define STM32WB_FLASH_SRRVR (STM32WB_FLASH_REGS_ADDR + 0x84) +#define FLASH_WB_REGS_ADDR ((uint32_t)0x58004000) +#define FLASH_WB_ACR (FLASH_WB_REGS_ADDR + 0x00) +#define FLASH_WB_KEYR (FLASH_WB_REGS_ADDR + 0x08) +#define FLASH_WB_OPT_KEYR (FLASH_WB_REGS_ADDR + 0x0C) +#define FLASH_WB_SR (FLASH_WB_REGS_ADDR + 0x10) +#define FLASH_WB_CR (FLASH_WB_REGS_ADDR + 0x14) +#define FLASH_WB_ECCR (FLASH_WB_REGS_ADDR + 0x18) +#define FLASH_WB_OPTR (FLASH_WB_REGS_ADDR + 0x20) +#define FLASH_WB_PCROP1ASR (FLASH_WB_REGS_ADDR + 0x24) +#define FLASH_WB_PCROP1AER (FLASH_WB_REGS_ADDR + 0x28) +#define FLASH_WB_WRP1AR (FLASH_WB_REGS_ADDR + 0x2C) +#define FLASH_WB_WRP1BR (FLASH_WB_REGS_ADDR + 0x30) +#define FLASH_WB_PCROP1BSR (FLASH_WB_REGS_ADDR + 0x34) +#define FLASH_WB_PCROP1BER (FLASH_WB_REGS_ADDR + 0x38) +#define FLASH_WB_IPCCBR (FLASH_WB_REGS_ADDR + 0x3C) +#define FLASH_WB_C2ACR (FLASH_WB_REGS_ADDR + 0x5C) +#define FLASH_WB_C2SR (FLASH_WB_REGS_ADDR + 0x60) +#define FLASH_WB_C2CR (FLASH_WB_REGS_ADDR + 0x64) +#define FLASH_WB_SFR (FLASH_WB_REGS_ADDR + 0x80) +#define FLASH_WB_SRRVR (FLASH_WB_REGS_ADDR + 0x84) // WB Flash control register. -#define STM32WB_FLASH_CR_STRT (16) /* Start */ -#define STM32WB_FLASH_CR_OPTSTRT (17) /* Start writing option bytes */ -#define STM32WB_FLASH_CR_OBL_LAUNCH (27) /* Forces the option byte loading */ -#define STM32WB_FLASH_CR_OPTLOCK (30) /* Option Lock */ -#define STM32WB_FLASH_CR_LOCK (31) /* Lock */ +#define FLASH_WB_CR_STRT (16) /* Start */ +#define FLASH_WB_CR_OPTSTRT (17) /* Start writing option bytes */ +#define FLASH_WB_CR_OBL_LAUNCH (27) /* Forces the option byte loading */ +#define FLASH_WB_CR_OPTLOCK (30) /* Option Lock */ +#define FLASH_WB_CR_LOCK (31) /* Lock */ // WB Flash status register. -#define STM32WB_FLASH_SR_ERROR_MASK (0x3f8) /* SR [9:3] */ -#define STM32WB_FLASH_SR_PROGERR (3) /* Programming alignment error */ -#define STM32WB_FLASH_SR_WRPERR (4) /* Write protection error */ -#define STM32WB_FLASH_SR_PGAERR (5) /* Programming error */ -#define STM32WB_FLASH_SR_BSY (16) /* Busy */ +#define FLASH_WB_SR_ERROR_MASK (0x3f8) /* SR [9:3] */ +#define FLASH_WB_SR_PROGERR (3) /* Programming alignment error */ +#define FLASH_WB_SR_WRPERR (4) /* Write protection error */ +#define FLASH_WB_SR_PGAERR (5) /* Programming error */ +#define FLASH_WB_SR_BSY (16) /* Busy */ // 32L4 register base is at FLASH_REGS_ADDR (0x40022000) -#define STM32L4_FLASH_KEYR (FLASH_REGS_ADDR + 0x08) -#define STM32L4_FLASH_OPTKEYR (FLASH_REGS_ADDR + 0x0C) -#define STM32L4_FLASH_SR (FLASH_REGS_ADDR + 0x10) -#define STM32L4_FLASH_CR (FLASH_REGS_ADDR + 0x14) -#define STM32L4_FLASH_OPTR (FLASH_REGS_ADDR + 0x20) - -#define STM32L4_FLASH_SR_ERROR_MASK 0x3f8 /* SR [9:3] */ -#define STM32L4_FLASH_SR_PROGERR 3 -#define STM32L4_FLASH_SR_WRPERR 4 -#define STM32L4_FLASH_SR_PGAERR 5 -#define STM32L4_FLASH_SR_BSY 16 - -#define STM32L4_FLASH_CR_LOCK 31 /* Lock control register */ -#define STM32L4_FLASH_CR_OPTLOCK 30 /* Lock option bytes */ -#define STM32L4_FLASH_CR_PG 0 /* Program */ -#define STM32L4_FLASH_CR_PER 1 /* Page erase */ -#define STM32L4_FLASH_CR_MER1 2 /* Bank 1 erase */ -#define STM32L4_FLASH_CR_MER2 15 /* Bank 2 erase */ -#define STM32L4_FLASH_CR_STRT 16 /* Start command */ -#define STM32L4_FLASH_CR_OPTSTRT 17 /* Start writing option bytes */ -#define STM32L4_FLASH_CR_BKER 11 /* Bank select for page erase */ -#define STM32L4_FLASH_CR_PNB 3 /* Page number (8 bits) */ -#define STM32L4_FLASH_CR_OBL_LAUNCH 27 /* Option bytes reload */ +#define FLASH_L4_KEYR (FLASH_REGS_ADDR + 0x08) +#define FLASH_L4_OPTKEYR (FLASH_REGS_ADDR + 0x0C) +#define FLASH_L4_SR (FLASH_REGS_ADDR + 0x10) +#define FLASH_L4_CR (FLASH_REGS_ADDR + 0x14) +#define FLASH_L4_OPTR (FLASH_REGS_ADDR + 0x20) + +#define FLASH_L4_SR_ERROR_MASK 0x3f8 /* SR [9:3] */ +#define FLASH_L4_SR_PROGERR 3 +#define FLASH_L4_SR_WRPERR 4 +#define FLASH_L4_SR_PGAERR 5 +#define FLASH_L4_SR_BSY 16 + +#define FLASH_L4_CR_LOCK 31 /* Lock control register */ +#define FLASH_L4_CR_OPTLOCK 30 /* Lock option bytes */ +#define FLASH_L4_CR_PG 0 /* Program */ +#define FLASH_L4_CR_PER 1 /* Page erase */ +#define FLASH_L4_CR_MER1 2 /* Bank 1 erase */ +#define FLASH_L4_CR_MER2 15 /* Bank 2 erase */ +#define FLASH_L4_CR_STRT 16 /* Start command */ +#define FLASH_L4_CR_OPTSTRT 17 /* Start writing option bytes */ +#define FLASH_L4_CR_BKER 11 /* Bank select for page erase */ +#define FLASH_L4_CR_PNB 3 /* Page number (8 bits) */ +#define FLASH_L4_CR_OBL_LAUNCH 27 /* Option bytes reload */ // Bits requesting flash operations (useful when we want to clear them) -#define STM32L4_FLASH_CR_OPBITS \ - (uint32_t)((1lu << STM32L4_FLASH_CR_PG) | (1lu << STM32L4_FLASH_CR_PER) | \ - (1lu << STM32L4_FLASH_CR_MER1) | (1lu << STM32L4_FLASH_CR_MER1)) +#define FLASH_L4_CR_OPBITS \ + (uint32_t)((1lu << FLASH_L4_CR_PG) | (1lu << FLASH_L4_CR_PER) | \ + (1lu << FLASH_L4_CR_MER1) | (1lu << FLASH_L4_CR_MER1)) // Page is fully specified by BKER and PNB -#define STM32L4_FLASH_CR_PAGEMASK (uint32_t)(0x1fflu << STM32L4_FLASH_CR_PNB) +#define FLASH_L4_CR_PAGEMASK (uint32_t)(0x1fflu << FLASH_L4_CR_PNB) -#define STM32L4_FLASH_OPTR_DUALBANK 21 +#define FLASH_L4_OPTR_DUALBANK 21 // Flash registers common to STM32L5 series (RM0438, p. 241) -#define STM32L5_FLASH_REGS_ADDR ((uint32_t)0x40022000) -#define STM32L5_FLASH_ACR (STM32L5_FLASH_REGS_ADDR + 0x00) -#define STM32L5_FLASH_NSKEYR (STM32L5_FLASH_REGS_ADDR + 0x08) -#define STM32L5_FLASH_OPTKEYR (STM32L5_FLASH_REGS_ADDR + 0x10) -#define STM32L5_FLASH_NSSR (STM32L5_FLASH_REGS_ADDR + 0x20) -#define STM32L5_FLASH_NSCR (STM32L5_FLASH_REGS_ADDR + 0x28) -#define STM32L5_FLASH_ECCR (STM32L5_FLASH_REGS_ADDR + 0x30) -#define STM32L5_FLASH_OPTR (STM32L5_FLASH_REGS_ADDR + 0x40) +#define FLASH_L5_REGS_ADDR ((uint32_t)0x40022000) +#define FLASH_L5_ACR (FLASH_L5_REGS_ADDR + 0x00) +#define FLASH_L5_NSKEYR (FLASH_L5_REGS_ADDR + 0x08) +#define FLASH_L5_OPTKEYR (FLASH_L5_REGS_ADDR + 0x10) +#define FLASH_L5_NSSR (FLASH_L5_REGS_ADDR + 0x20) +#define FLASH_L5_NSCR (FLASH_L5_REGS_ADDR + 0x28) +#define FLASH_L5_ECCR (FLASH_L5_REGS_ADDR + 0x30) +#define FLASH_L5_OPTR (FLASH_L5_REGS_ADDR + 0x40) // FLASH_NSCR (RM0438, p. 242) -#define STM32L5_FLASH_NSCR_NSPG 0 /* Program */ -#define STM32L5_FLASH_NSCR_NSPER 1 /* Page erase */ -#define STM32L5_FLASH_NSCR_NSMER1 2 /* Bank 1 erase */ -#define STM32L5_FLASH_NSCR_NSPNB 3 /* Page number (7 bits) */ -#define STM32L5_FLASH_NSCR_NSBKER 11 /* Bank select for page erase */ -#define STM32L5_FLASH_NSCR_NSMER2 15 /* Bank 2 erase */ -#define STM32L5_FLASH_NSCR_NSSTRT 16 /* Start command */ -#define STM32L5_FLASH_NSCR_NSOPTSTRT 17 /* Start writing option bytes */ -#define STM32L5_FLASH_NSCR_NSEOPIE 24 -#define STM32L5_FLASH_NSCR_NSERRIE 25 -#define STM32L5_FLASH_NSCR_OBL_LAUNCH 27 /* Option bytes reload */ -#define STM32L5_FLASH_NSCR_OPTLOCK 30 /* Lock option bytes */ -#define STM32L5_FLASH_NSCR_NSLOCK 31 /* Lock control register */ +#define FLASH_L5_NSCR_NSPG 0 /* Program */ +#define FLASH_L5_NSCR_NSPER 1 /* Page erase */ +#define FLASH_L5_NSCR_NSMER1 2 /* Bank 1 erase */ +#define FLASH_L5_NSCR_NSPNB 3 /* Page number (7 bits) */ +#define FLASH_L5_NSCR_NSBKER 11 /* Bank select for page erase */ +#define FLASH_L5_NSCR_NSMER2 15 /* Bank 2 erase */ +#define FLASH_L5_NSCR_NSSTRT 16 /* Start command */ +#define FLASH_L5_NSCR_NSOPTSTRT 17 /* Start writing option bytes */ +#define FLASH_L5_NSCR_NSEOPIE 24 +#define FLASH_L5_NSCR_NSERRIE 25 +#define FLASH_L5_NSCR_OBL_LAUNCH 27 /* Option bytes reload */ +#define FLASH_L5_NSCR_OPTLOCK 30 /* Lock option bytes */ +#define FLASH_L5_NSCR_NSLOCK 31 /* Lock control register */ // FLASH_NSSR (RM0438, p. 241) -#define STM32L5_FLASH_NSSR_NSEOP 0 /* End of Operation */ -#define STM32L5_FLASH_NSSR_NSOPERR 1 -#define STM32L5_FLASH_NSSR_NSPROGERR 3 -#define STM32L5_FLASH_NSSR_NSWRPERR 4 -#define STM32L5_FLASH_NSSR_NSPGAERR 5 -#define STM32L5_FLASH_NSSR_NSSIZERR 6 -#define STM32L5_FLASH_NSSR_NSPGSERR 7 -#define STM32L5_FLASH_NSSR_OPTWERR 12 -#define STM32L5_FLASH_NSSR_BSY 16 /* Busy */ -#define STM32L5_FLASH_NSSR_ERROR_MASK (0x20fa) +#define FLASH_L5_NSSR_NSEOP 0 /* End of Operation */ +#define FLASH_L5_NSSR_NSOPERR 1 +#define FLASH_L5_NSSR_NSPROGERR 3 +#define FLASH_L5_NSSR_NSWRPERR 4 +#define FLASH_L5_NSSR_NSPGAERR 5 +#define FLASH_L5_NSSR_NSSIZERR 6 +#define FLASH_L5_NSSR_NSPGSERR 7 +#define FLASH_L5_NSSR_OPTWERR 12 +#define FLASH_L5_NSSR_BSY 16 /* Busy */ +#define FLASH_L5_NSSR_ERROR_MASK (0x20fa) // STM32L0x flash register base and offsets RM0090 - DM00031020.pdf -#define STM32L0_FLASH_REGS_ADDR ((uint32_t)0x40022000) +#define FLASH_L0_REGS_ADDR ((uint32_t)0x40022000) -#define STM32L0_FLASH_PELOCK (0) -#define STM32L0_FLASH_OPTLOCK (2) -#define STM32L0_FLASH_OBL_LAUNCH (18) +#define FLASH_L0_PELOCK (0) +#define FLASH_L0_OPTLOCK (2) +#define FLASH_L0_OBL_LAUNCH (18) -#define STM32L0_FLASH_SR_ERROR_MASK 0x00013F00 -#define STM32L0_FLASH_SR_WRPERR 8 -#define STM32L0_FLASH_SR_PGAERR 9 -#define STM32L0_FLASH_SR_NOTZEROERR 16 +#define FLASH_L0_SR_ERROR_MASK 0x00013F00 +#define FLASH_L0_SR_WRPERR 8 +#define FLASH_L0_SR_PGAERR 9 +#define FLASH_L0_SR_NOTZEROERR 16 -#define STM32L1_FLASH_SR_ERROR_MASK 0x00003F00 -#define STM32L1_FLASH_SR_WRPERR 8 -#define STM32L1_FLASH_SR_PGAERR 9 +#define FLASH_L1_SR_ERROR_MASK 0x00003F00 +#define FLASH_L1_SR_WRPERR 8 +#define FLASH_L1_SR_PGAERR 9 #define FLASH_ACR_OFF ((uint32_t)0x00) #define FLASH_PECR_OFF ((uint32_t)0x04) diff --git a/src/stlink-lib/calculate.c b/src/stlink-lib/calculate.c index ed3b65873..ddab5ed08 100644 --- a/src/stlink-lib/calculate.c +++ b/src/stlink-lib/calculate.c @@ -51,14 +51,14 @@ uint32_t calculate_H7_sectornum(stlink_t *sl, uint32_t flashaddr, uint32_t calculate_L4_page(stlink_t *sl, uint32_t flashaddr) { uint32_t bker = 0; uint32_t flashopt; - stlink_read_debug32(sl, STM32L4_FLASH_OPTR, &flashopt); + stlink_read_debug32(sl, FLASH_L4_OPTR, &flashopt); flashaddr -= STM32_FLASH_BASE; if (sl->chip_id == STM32_CHIPID_L4 || sl->chip_id == STM32_CHIPID_L496x_L4A6x || sl->chip_id == STM32_CHIPID_L4Rx) { // this chip use dual banked flash - if (flashopt & (uint32_t)(1lu << STM32L4_FLASH_OPTR_DUALBANK)) { + if (flashopt & (uint32_t)(1lu << FLASH_L4_OPTR_DUALBANK)) { uint32_t banksize = (uint32_t)sl->flash_size / 2; if (flashaddr >= banksize) { diff --git a/src/stlink-lib/common.c b/src/stlink-lib/common.c index fac97278e..f2d60ce45 100644 --- a/src/stlink-lib/common.c +++ b/src/stlink-lib/common.c @@ -288,16 +288,16 @@ int stlink_load_device_params(stlink_t *sl) { if (sl->chip_id == STM32_CHIPID_G4_CAT3) { uint32_t flash_optr; - stlink_read_debug32(sl, STM32Gx_FLASH_OPTR, &flash_optr); + stlink_read_debug32(sl, FLASH_Gx_OPTR, &flash_optr); - if (!(flash_optr & (1 << STM32G4_FLASH_OPTR_DBANK))) { + if (!(flash_optr & (1 << FLASH_G4_OPTR_DBANK))) { sl->flash_pgsz <<= 1; } } if (sl->chip_id == STM32_CHIPID_L5x2xx) { uint32_t flash_optr; - stlink_read_debug32(sl, STM32L5_FLASH_OPTR, &flash_optr); + stlink_read_debug32(sl, FLASH_L5_OPTR, &flash_optr); if (sl->flash_size == 512*1024 && (flash_optr & (1 << 22)) != 0) { sl->flash_pgsz = 0x800; @@ -1099,7 +1099,7 @@ static void stop_wdg_in_debug(stlink_t *sl) { break; case STM32_FLASH_TYPE_L0_L1: case STM32_FLASH_TYPE_G0: - if (get_stm32l0_flash_base(sl) == STM32L_FLASH_REGS_ADDR) { + if (get_stm32l0_flash_base(sl) == FLASH_Lx_REGS_ADDR) { dbgmcu_cr = STM32L1_DBGMCU_APB1_FZ; set = (1 << STM32L1_DBGMCU_APB1_FZ_IWDG_STOP) | (1 << STM32L1_DBGMCU_APB1_FZ_WWDG_STOP); diff --git a/src/stlink-lib/common_flash.c b/src/stlink-lib/common_flash.c index dbae1c694..dc33fdfcb 100644 --- a/src/stlink-lib/common_flash.c +++ b/src/stlink-lib/common_flash.c @@ -16,18 +16,18 @@ uint32_t get_stm32l0_flash_base(stlink_t *sl) { case STM32_CHIPID_L0_CAT2: case STM32_CHIPID_L0_CAT3: case STM32_CHIPID_L0_CAT5: - return (STM32L0_FLASH_REGS_ADDR); + return (FLASH_L0_REGS_ADDR); case STM32_CHIPID_L1_CAT2: case STM32_CHIPID_L1_MD: case STM32_CHIPID_L1_MD_PLUS: case STM32_CHIPID_L1_MD_PLUS_HD: case STM32_CHIPID_L152_RE: - return (STM32L_FLASH_REGS_ADDR); + return (FLASH_Lx_REGS_ADDR); default: WLOG("Flash base use default L0 address\n"); - return (STM32L0_FLASH_REGS_ADDR); + return (FLASH_L0_REGS_ADDR); } } @@ -40,15 +40,15 @@ uint32_t read_flash_cr(stlink_t *sl, unsigned bank) { reg = FLASH_F7_CR; } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || sl->flash_type == STM32_FLASH_TYPE_G4) { - reg = STM32Gx_FLASH_CR; + reg = FLASH_Gx_CR; } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { - reg = STM32L4_FLASH_CR; + reg = FLASH_L4_CR; } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5) { - reg = STM32L5_FLASH_NSCR; + reg = FLASH_L5_NSCR; } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { - reg = STM32WB_FLASH_CR; + reg = FLASH_WB_CR; } else { reg = (bank == BANK_1) ? FLASH_CR : FLASH_CR2; } @@ -80,22 +80,22 @@ void lock_flash(stlink_t *sl) { cr_lock_shift = FLASH_F7_CR_LOCK; } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || sl->flash_type == STM32_FLASH_TYPE_G4) { - cr_reg = STM32Gx_FLASH_CR; - cr_lock_shift = STM32Gx_FLASH_CR_LOCK; + cr_reg = FLASH_Gx_CR; + cr_lock_shift = FLASH_Gx_CR_LOCK; } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { cr_reg = FLASH_H7_CR1; } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { cr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF; - cr_lock_shift = STM32L0_FLASH_PELOCK; + cr_lock_shift = FLASH_L0_PELOCK; } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { - cr_reg = STM32L4_FLASH_CR; - cr_lock_shift = STM32L4_FLASH_CR_LOCK; + cr_reg = FLASH_L4_CR; + cr_lock_shift = FLASH_L4_CR_LOCK; } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5) { - cr_reg = STM32L5_FLASH_NSCR; - cr_lock_shift = STM32L5_FLASH_NSCR_NSLOCK; + cr_reg = FLASH_L5_NSCR; + cr_lock_shift = FLASH_L5_NSCR_NSLOCK; } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { - cr_reg = STM32WB_FLASH_CR; - cr_lock_shift = STM32WB_FLASH_CR_LOCK; + cr_reg = FLASH_WB_CR; + cr_lock_shift = FLASH_WB_CR_LOCK; if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { cr2_reg = FLASH_H7_CR2; } @@ -129,17 +129,17 @@ static inline int write_flash_sr(stlink_t *sl, unsigned bank, uint32_t val) { sr_reg = FLASH_F7_SR; } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || sl->flash_type == STM32_FLASH_TYPE_G4) { - sr_reg = STM32Gx_FLASH_SR; + sr_reg = FLASH_Gx_SR; } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { sr_reg = (bank == BANK_1) ? FLASH_H7_SR1 : FLASH_H7_SR2; } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { sr_reg = get_stm32l0_flash_base(sl) + FLASH_SR_OFF; } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { - sr_reg = STM32L4_FLASH_SR; + sr_reg = FLASH_L4_SR; } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5) { - sr_reg = STM32L5_FLASH_NSSR; + sr_reg = FLASH_L5_NSSR; } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { - sr_reg = STM32WB_FLASH_SR; + sr_reg = FLASH_WB_SR; } else { ELOG("method 'write_flash_sr' is unsupported\n"); return (-1); @@ -161,7 +161,7 @@ void clear_flash_error(stlink_t *sl) { break; case STM32_FLASH_TYPE_G0: case STM32_FLASH_TYPE_G4: - write_flash_sr(sl, BANK_1, STM32Gx_FLASH_SR_ERROR_MASK); + write_flash_sr(sl, BANK_1, FLASH_Gx_SR_ERROR_MASK); break; case STM32_FLASH_TYPE_H7: write_flash_sr(sl, BANK_1, FLASH_H7_SR_ERROR_MASK); @@ -170,20 +170,20 @@ void clear_flash_error(stlink_t *sl) { } break; case STM32_FLASH_TYPE_L0_L1: - if (get_stm32l0_flash_base(sl) == STM32L_FLASH_REGS_ADDR) { - write_flash_sr(sl, BANK_1, STM32L1_FLASH_SR_ERROR_MASK); + if (get_stm32l0_flash_base(sl) == FLASH_Lx_REGS_ADDR) { + write_flash_sr(sl, BANK_1, FLASH_L1_SR_ERROR_MASK); } else { - write_flash_sr(sl, BANK_1, STM32L0_FLASH_SR_ERROR_MASK); + write_flash_sr(sl, BANK_1, FLASH_L0_SR_ERROR_MASK); } break; case STM32_FLASH_TYPE_L4: - write_flash_sr(sl, BANK_1, STM32L4_FLASH_SR_ERROR_MASK); + write_flash_sr(sl, BANK_1, FLASH_L4_SR_ERROR_MASK); break; case STM32_FLASH_TYPE_L5_U5: - write_flash_sr(sl, BANK_1, STM32L5_FLASH_NSSR_ERROR_MASK); + write_flash_sr(sl, BANK_1, FLASH_L5_NSSR_ERROR_MASK); break; case STM32_FLASH_TYPE_WB_WL: - write_flash_sr(sl, BANK_1, STM32WB_FLASH_SR_ERROR_MASK); + write_flash_sr(sl, BANK_1, FLASH_WB_SR_ERROR_MASK); break; default: break; @@ -202,17 +202,17 @@ uint32_t read_flash_sr(stlink_t *sl, unsigned bank) { sr_reg = FLASH_F7_SR; } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || sl->flash_type == STM32_FLASH_TYPE_G4) { - sr_reg = STM32Gx_FLASH_SR; + sr_reg = FLASH_Gx_SR; } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { sr_reg = (bank == BANK_1) ? FLASH_H7_SR1 : FLASH_H7_SR2; } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { sr_reg = get_stm32l0_flash_base(sl) + FLASH_SR_OFF; } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { - sr_reg = STM32L4_FLASH_SR; + sr_reg = FLASH_L4_SR; } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5) { - sr_reg = STM32L5_FLASH_NSSR; + sr_reg = FLASH_L5_NSSR; } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { - sr_reg = STM32WB_FLASH_SR; + sr_reg = FLASH_WB_SR; } else { ELOG("method 'read_flash_sr' is unsupported\n"); return (-1); @@ -236,15 +236,15 @@ unsigned int is_flash_busy(stlink_t *sl) { sr_busy_shift = FLASH_F7_SR_BSY; } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || sl->flash_type == STM32_FLASH_TYPE_G4) { - sr_busy_shift = STM32Gx_FLASH_SR_BSY; + sr_busy_shift = FLASH_Gx_SR_BSY; } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { sr_busy_shift = FLASH_H7_SR_QW; } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { - sr_busy_shift = STM32L4_FLASH_SR_BSY; + sr_busy_shift = FLASH_L4_SR_BSY; } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5) { - sr_busy_shift = STM32L5_FLASH_NSSR_BSY; + sr_busy_shift = FLASH_L5_NSSR_BSY; } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { - sr_busy_shift = STM32WB_FLASH_SR_BSY; + sr_busy_shift = FLASH_WB_SR_BSY; } else { ELOG("method 'is_flash_busy' is unsupported\n"); return (-1); @@ -295,10 +295,10 @@ int check_flash_error(stlink_t *sl) { break; case STM32_FLASH_TYPE_G0: case STM32_FLASH_TYPE_G4: - res = read_flash_sr(sl, BANK_1) & STM32Gx_FLASH_SR_ERROR_MASK; - WRPERR = (1 << STM32Gx_FLASH_SR_WRPERR); - PROGERR = (1 << STM32Gx_FLASH_SR_PROGERR); - PGAERR = (1 << STM32Gx_FLASH_SR_PGAERR); + res = read_flash_sr(sl, BANK_1) & FLASH_Gx_SR_ERROR_MASK; + WRPERR = (1 << FLASH_Gx_SR_WRPERR); + PROGERR = (1 << FLASH_Gx_SR_PROGERR); + PGAERR = (1 << FLASH_Gx_SR_PGAERR); break; case STM32_FLASH_TYPE_H7: res = read_flash_sr(sl, BANK_1) & FLASH_H7_SR_ERROR_MASK; @@ -309,32 +309,32 @@ int check_flash_error(stlink_t *sl) { break; case STM32_FLASH_TYPE_L0_L1: res = read_flash_sr(sl, BANK_1); - if (get_stm32l0_flash_base(sl) == STM32L_FLASH_REGS_ADDR) { - res &= STM32L1_FLASH_SR_ERROR_MASK; + if (get_stm32l0_flash_base(sl) == FLASH_Lx_REGS_ADDR) { + res &= FLASH_L1_SR_ERROR_MASK; } else { - res &= STM32L0_FLASH_SR_ERROR_MASK; - PROGERR = (1 << STM32L0_FLASH_SR_NOTZEROERR); + res &= FLASH_L0_SR_ERROR_MASK; + PROGERR = (1 << FLASH_L0_SR_NOTZEROERR); } - WRPERR = (1 << STM32L0_FLASH_SR_WRPERR); - PGAERR = (1 << STM32L0_FLASH_SR_PGAERR); + WRPERR = (1 << FLASH_L0_SR_WRPERR); + PGAERR = (1 << FLASH_L0_SR_PGAERR); break; case STM32_FLASH_TYPE_L4: - res = read_flash_sr(sl, BANK_1) & STM32L4_FLASH_SR_ERROR_MASK; - WRPERR = (1 << STM32L4_FLASH_SR_WRPERR); - PROGERR = (1 << STM32L4_FLASH_SR_PROGERR); - PGAERR = (1 << STM32L4_FLASH_SR_PGAERR); + res = read_flash_sr(sl, BANK_1) & FLASH_L4_SR_ERROR_MASK; + WRPERR = (1 << FLASH_L4_SR_WRPERR); + PROGERR = (1 << FLASH_L4_SR_PROGERR); + PGAERR = (1 << FLASH_L4_SR_PGAERR); break; case STM32_FLASH_TYPE_L5_U5: - res = read_flash_sr(sl, BANK_1) & STM32L5_FLASH_NSSR_ERROR_MASK; - WRPERR = (1 << STM32L5_FLASH_NSSR_NSWRPERR); - PROGERR = (1 << STM32L5_FLASH_NSSR_NSPROGERR); - PGAERR = (1 << STM32L5_FLASH_NSSR_NSPGAERR); + res = read_flash_sr(sl, BANK_1) & FLASH_L5_NSSR_ERROR_MASK; + WRPERR = (1 << FLASH_L5_NSSR_NSWRPERR); + PROGERR = (1 << FLASH_L5_NSSR_NSPROGERR); + PGAERR = (1 << FLASH_L5_NSSR_NSPGAERR); break; case STM32_FLASH_TYPE_WB_WL: - res = read_flash_sr(sl, BANK_1) & STM32WB_FLASH_SR_ERROR_MASK; - WRPERR = (1 << STM32WB_FLASH_SR_WRPERR); - PROGERR = (1 << STM32WB_FLASH_SR_PROGERR); - PGAERR = (1 << STM32WB_FLASH_SR_PGAERR); + res = read_flash_sr(sl, BANK_1) & FLASH_WB_SR_ERROR_MASK; + WRPERR = (1 << FLASH_WB_SR_WRPERR); + PROGERR = (1 << FLASH_WB_SR_PROGERR); + PGAERR = (1 << FLASH_WB_SR_PGAERR); break; default: break; @@ -379,23 +379,23 @@ static inline unsigned int is_flash_locked(stlink_t *sl) { cr_lock_shift = FLASH_F7_CR_LOCK; } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || sl->flash_type == STM32_FLASH_TYPE_G4) { - cr_reg = STM32Gx_FLASH_CR; - cr_lock_shift = STM32Gx_FLASH_CR_LOCK; + cr_reg = FLASH_Gx_CR; + cr_lock_shift = FLASH_Gx_CR_LOCK; } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { cr_reg = FLASH_H7_CR1; cr_lock_shift = FLASH_H7_CR_LOCK; } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { cr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF; - cr_lock_shift = STM32L0_FLASH_PELOCK; + cr_lock_shift = FLASH_L0_PELOCK; } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { - cr_reg = STM32L4_FLASH_CR; - cr_lock_shift = STM32L4_FLASH_CR_LOCK; + cr_reg = FLASH_L4_CR; + cr_lock_shift = FLASH_L4_CR_LOCK; } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5) { - cr_reg = STM32L5_FLASH_NSCR; - cr_lock_shift = STM32L5_FLASH_NSCR_NSLOCK; + cr_reg = FLASH_L5_NSCR; + cr_lock_shift = FLASH_L5_NSCR_NSLOCK; } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { - cr_reg = STM32WB_FLASH_CR; - cr_lock_shift = STM32WB_FLASH_CR_LOCK; + cr_reg = FLASH_WB_CR; + cr_lock_shift = FLASH_WB_CR_LOCK; } else { ELOG("unsupported flash method, abort\n"); return (-1); @@ -425,7 +425,7 @@ static void unlock_flash(stlink_t *sl) { key_reg = FLASH_F7_KEYR; } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || sl->flash_type == STM32_FLASH_TYPE_G4) { - key_reg = STM32Gx_FLASH_KEYR; + key_reg = FLASH_Gx_KEYR; } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { key_reg = FLASH_H7_KEYR1; if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { @@ -436,7 +436,7 @@ static void unlock_flash(stlink_t *sl) { flash_key1 = FLASH_L0_PEKEY1; flash_key2 = FLASH_L0_PEKEY2; } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { - key_reg = STM32L4_FLASH_KEYR; + key_reg = FLASH_L4_KEYR; } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5) { // Set voltage scaling to range 0 to perform flash operations (RM0438 p. 183) uint32_t mask = (0b11 << STM32L5_PWR_CR1_VOS); @@ -445,9 +445,9 @@ static void unlock_flash(stlink_t *sl) { val &= ~mask; stlink_write_debug32(sl, STM32L5_PWR_CR1, val); } - key_reg = STM32L5_FLASH_NSKEYR; + key_reg = FLASH_L5_NSKEYR; } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { - key_reg = STM32WB_FLASH_KEYR; + key_reg = FLASH_WB_KEYR; } else { ELOG("unsupported flash method, abort\n"); return; @@ -498,8 +498,8 @@ int lock_flash_option(stlink_t *sl) { break; case STM32_FLASH_TYPE_G0: case STM32_FLASH_TYPE_G4: - optcr_reg = STM32Gx_FLASH_CR; - optlock_shift = STM32Gx_FLASH_CR_OPTLOCK; + optcr_reg = FLASH_Gx_CR; + optlock_shift = FLASH_Gx_CR_OPTLOCK; break; case STM32_FLASH_TYPE_H7: optcr_reg = FLASH_H7_OPTCR; @@ -509,19 +509,19 @@ int lock_flash_option(stlink_t *sl) { break; case STM32_FLASH_TYPE_L0_L1: optcr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF; - optlock_shift = STM32L0_FLASH_OPTLOCK; + optlock_shift = FLASH_L0_OPTLOCK; break; case STM32_FLASH_TYPE_L4: - optcr_reg = STM32L4_FLASH_CR; - optlock_shift = STM32L4_FLASH_CR_OPTLOCK; + optcr_reg = FLASH_L4_CR; + optlock_shift = FLASH_L4_CR_OPTLOCK; break; case STM32_FLASH_TYPE_L5_U5: - optcr_reg = STM32L5_FLASH_NSCR; - optlock_shift = STM32L5_FLASH_NSCR_OPTLOCK; + optcr_reg = FLASH_L5_NSCR; + optlock_shift = FLASH_L5_NSCR_OPTLOCK; break; case STM32_FLASH_TYPE_WB_WL: - optcr_reg = STM32WB_FLASH_CR; - optlock_shift = STM32WB_FLASH_CR_OPTLOCK; + optcr_reg = FLASH_WB_CR; + optlock_shift = FLASH_WB_CR_OPTLOCK; break; default: ELOG("unsupported flash method, abort\n"); @@ -575,8 +575,8 @@ static bool is_flash_option_locked(stlink_t *sl) { break; case STM32_FLASH_TYPE_G0: case STM32_FLASH_TYPE_G4: - optcr_reg = STM32Gx_FLASH_CR; - optlock_shift = STM32Gx_FLASH_CR_OPTLOCK; + optcr_reg = FLASH_Gx_CR; + optlock_shift = FLASH_Gx_CR_OPTLOCK; break; case STM32_FLASH_TYPE_H7: optcr_reg = FLASH_H7_OPTCR; @@ -584,19 +584,19 @@ static bool is_flash_option_locked(stlink_t *sl) { break; case STM32_FLASH_TYPE_L0_L1: optcr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF; - optlock_shift = STM32L0_FLASH_OPTLOCK; + optlock_shift = FLASH_L0_OPTLOCK; break; case STM32_FLASH_TYPE_L4: - optcr_reg = STM32L4_FLASH_CR; - optlock_shift = STM32L4_FLASH_CR_OPTLOCK; + optcr_reg = FLASH_L4_CR; + optlock_shift = FLASH_L4_CR_OPTLOCK; break; case STM32_FLASH_TYPE_L5_U5: - optcr_reg = STM32L5_FLASH_NSCR; - optlock_shift = STM32L5_FLASH_NSCR_OPTLOCK; + optcr_reg = FLASH_L5_NSCR; + optlock_shift = FLASH_L5_NSCR_OPTLOCK; break; case STM32_FLASH_TYPE_WB_WL: - optcr_reg = STM32WB_FLASH_CR; - optlock_shift = STM32WB_FLASH_CR_OPTLOCK; + optcr_reg = FLASH_WB_CR; + optlock_shift = FLASH_WB_CR_OPTLOCK; break; default: ELOG("unsupported flash method, abort\n"); @@ -632,7 +632,7 @@ static int unlock_flash_option(stlink_t *sl) { break; case STM32_FLASH_TYPE_G0: case STM32_FLASH_TYPE_G4: - optkey_reg = STM32Gx_FLASH_OPTKEYR; + optkey_reg = FLASH_Gx_OPTKEYR; break; case STM32_FLASH_TYPE_H7: optkey_reg = FLASH_H7_OPT_KEYR; @@ -645,13 +645,13 @@ static int unlock_flash_option(stlink_t *sl) { optkey2 = FLASH_L0_OPTKEY2; break; case STM32_FLASH_TYPE_L4: - optkey_reg = STM32L4_FLASH_OPTKEYR; + optkey_reg = FLASH_L4_OPTKEYR; break; case STM32_FLASH_TYPE_L5_U5: - optkey_reg = STM32L5_FLASH_OPTKEYR; + optkey_reg = FLASH_L5_OPTKEYR; break; case STM32_FLASH_TYPE_WB_WL: - optkey_reg = STM32WB_FLASH_OPT_KEYR; + optkey_reg = FLASH_WB_OPT_KEYR; break; default: ELOG("unsupported flash method, abort\n"); @@ -717,16 +717,16 @@ void clear_flash_cr_pg(stlink_t *sl, unsigned bank) { cr_reg = FLASH_F7_CR; } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || sl->flash_type == STM32_FLASH_TYPE_G4) { - cr_reg = STM32Gx_FLASH_CR; + cr_reg = FLASH_Gx_CR; } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { cr_reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; bit = FLASH_H7_CR_PG; } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { - cr_reg = STM32L4_FLASH_CR; + cr_reg = FLASH_L4_CR; } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5) { - cr_reg = STM32L5_FLASH_NSCR; + cr_reg = FLASH_L5_NSCR; } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { - cr_reg = STM32WB_FLASH_CR; + cr_reg = FLASH_WB_CR; } else { cr_reg = FLASH_CR; } @@ -788,11 +788,11 @@ static void set_flash_cr_per(stlink_t *sl, unsigned bank) { if (sl->flash_type == STM32_FLASH_TYPE_G0 || sl->flash_type == STM32_FLASH_TYPE_G4) { - cr_reg = STM32Gx_FLASH_CR; + cr_reg = FLASH_Gx_CR; } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5) { - cr_reg = STM32L5_FLASH_NSCR; + cr_reg = FLASH_L5_NSCR; } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { - cr_reg = STM32WB_FLASH_CR; + cr_reg = FLASH_WB_CR; } else { cr_reg = (bank == BANK_1) ? FLASH_CR : FLASH_CR2; } @@ -807,11 +807,11 @@ static void clear_flash_cr_per(stlink_t *sl, unsigned bank) { if (sl->flash_type == STM32_FLASH_TYPE_G0 || sl->flash_type == STM32_FLASH_TYPE_G4) { - cr_reg = STM32Gx_FLASH_CR; + cr_reg = FLASH_Gx_CR; } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5) { - cr_reg = STM32L5_FLASH_NSCR; + cr_reg = FLASH_L5_NSCR; } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { - cr_reg = STM32WB_FLASH_CR; + cr_reg = FLASH_WB_CR; } else { cr_reg = (bank == BANK_1) ? FLASH_CR : FLASH_CR2; } @@ -821,19 +821,19 @@ static void clear_flash_cr_per(stlink_t *sl, unsigned bank) { } static inline void write_flash_cr_bker_pnb(stlink_t *sl, uint32_t n) { - stlink_write_debug32(sl, STM32L4_FLASH_SR, - 0xFFFFFFFF & ~(1 << STM32L4_FLASH_SR_BSY)); + stlink_write_debug32(sl, FLASH_L4_SR, + 0xFFFFFFFF & ~(1 << FLASH_L4_SR_BSY)); uint32_t x = read_flash_cr(sl, BANK_1); - x &= ~STM32L4_FLASH_CR_OPBITS; - x &= ~STM32L4_FLASH_CR_PAGEMASK; - x &= ~(1 << STM32L4_FLASH_CR_MER1); - x &= ~(1 << STM32L4_FLASH_CR_MER2); - x |= (n << STM32L4_FLASH_CR_PNB); - x |= (uint32_t)(1lu << STM32L4_FLASH_CR_PER); + x &= ~FLASH_L4_CR_OPBITS; + x &= ~FLASH_L4_CR_PAGEMASK; + x &= ~(1 << FLASH_L4_CR_MER1); + x &= ~(1 << FLASH_L4_CR_MER2); + x |= (n << FLASH_L4_CR_PNB); + x |= (uint32_t)(1lu << FLASH_L4_CR_PER); #if DEBUG_FLASH fprintf(stdout, "BKER:PNB:0x%x 0x%x\n", x, n); #endif - stlink_write_debug32(sl, STM32L4_FLASH_CR, x); + stlink_write_debug32(sl, FLASH_L4_CR, x); } static void set_flash_cr_strt(stlink_t *sl, unsigned bank) { @@ -847,20 +847,20 @@ static void set_flash_cr_strt(stlink_t *sl, unsigned bank) { cr_strt = 1 << FLASH_F7_CR_STRT; } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || sl->flash_type == STM32_FLASH_TYPE_G4) { - cr_reg = STM32Gx_FLASH_CR; - cr_strt = (1 << STM32Gx_FLASH_CR_STRT); + cr_reg = FLASH_Gx_CR; + cr_strt = (1 << FLASH_Gx_CR_STRT); } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { cr_reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; cr_strt = 1 << FLASH_H7_CR_START(sl->chip_id); } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { - cr_reg = STM32L4_FLASH_CR; - cr_strt = (1 << STM32L4_FLASH_CR_STRT); + cr_reg = FLASH_L4_CR; + cr_strt = (1 << FLASH_L4_CR_STRT); } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5) { - cr_reg = STM32L5_FLASH_NSCR; - cr_strt = (1 << STM32L5_FLASH_NSCR_NSSTRT); + cr_reg = FLASH_L5_NSCR; + cr_strt = (1 << FLASH_L5_NSCR_NSSTRT); } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { - cr_reg = STM32WB_FLASH_CR; - cr_strt = (1 << STM32WB_FLASH_CR_STRT); + cr_reg = FLASH_WB_CR; + cr_strt = (1 << FLASH_WB_CR_STRT); } else { cr_reg = (bank == BANK_1) ? FLASH_CR : FLASH_CR2; cr_strt = (1 << FLASH_CR_STRT); @@ -884,10 +884,10 @@ static void set_flash_cr_mer(stlink_t *sl, bool v, unsigned bank) { cr_pg = 1 << FLASH_CR_PG; } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || sl->flash_type == STM32_FLASH_TYPE_G4) { - cr_reg = STM32Gx_FLASH_CR; - cr_mer = (1 << STM32Gx_FLASH_CR_MER1); + cr_reg = FLASH_Gx_CR; + cr_mer = (1 << FLASH_Gx_CR_MER1); if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { - cr_mer |= (1 << STM32Gx_FLASH_CR_MER2); + cr_mer |= (1 << FLASH_Gx_CR_MER2); } cr_pg = (1 << FLASH_CR_PG); } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { @@ -895,15 +895,15 @@ static void set_flash_cr_mer(stlink_t *sl, bool v, unsigned bank) { cr_mer = (1 << FLASH_H7_CR_BER); cr_pg = (1 << FLASH_H7_CR_PG); } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { - cr_reg = STM32L4_FLASH_CR; - cr_mer = (1 << STM32L4_FLASH_CR_MER1) | (1 << STM32L4_FLASH_CR_MER2); - cr_pg = (1 << STM32L4_FLASH_CR_PG); + cr_reg = FLASH_L4_CR; + cr_mer = (1 << FLASH_L4_CR_MER1) | (1 << FLASH_L4_CR_MER2); + cr_pg = (1 << FLASH_L4_CR_PG); } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5) { - cr_reg = STM32L5_FLASH_NSCR; - cr_mer = (1 << STM32L5_FLASH_NSCR_NSMER1) | (1 << STM32L5_FLASH_NSCR_NSMER2); - cr_pg = (1 << STM32L5_FLASH_NSCR_NSPG); + cr_reg = FLASH_L5_NSCR; + cr_mer = (1 << FLASH_L5_NSCR_NSMER1) | (1 << FLASH_L5_NSCR_NSMER2); + cr_pg = (1 << FLASH_L5_NSCR_NSPG); } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { - cr_reg = STM32WB_FLASH_CR; + cr_reg = FLASH_WB_CR; cr_mer = (1 << FLASH_CR_MER); cr_pg = (1 << FLASH_CR_PG); } else { @@ -1059,47 +1059,47 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { if (sl->flash_type == STM32_FLASH_TYPE_G0) { uint32_t flash_page = ((flashaddr - STM32_FLASH_BASE) / (uint32_t)(sl->flash_pgsz)); - stlink_read_debug32(sl, STM32Gx_FLASH_CR, &val); + stlink_read_debug32(sl, FLASH_Gx_CR, &val); // sec 3.7.5 - PNB[5:0] is offset by 3. PER is 0x2. val &= ~(0x3F << 3); val |= ((flash_page & 0x3F) << 3) | (1 << FLASH_CR_PER); - stlink_write_debug32(sl, STM32Gx_FLASH_CR, val); + stlink_write_debug32(sl, FLASH_Gx_CR, val); } else if (sl->flash_type == STM32_FLASH_TYPE_G4) { uint32_t flash_page = ((flashaddr - STM32_FLASH_BASE) / (uint32_t)(sl->flash_pgsz)); - stlink_read_debug32(sl, STM32Gx_FLASH_CR, &val); + stlink_read_debug32(sl, FLASH_Gx_CR, &val); // sec 3.7.5 - PNB[6:0] is offset by 3. PER is 0x2. val &= ~(0x7F << 3); val |= ((flash_page & 0x7F) << 3) | (1 << FLASH_CR_PER); - stlink_write_debug32(sl, STM32Gx_FLASH_CR, val); + stlink_write_debug32(sl, FLASH_Gx_CR, val); } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5) { uint32_t flash_page; - stlink_read_debug32(sl, STM32L5_FLASH_NSCR, &val); + stlink_read_debug32(sl, FLASH_L5_NSCR, &val); if (sl->flash_pgsz == 0x800 && (flashaddr - STM32_FLASH_BASE) >= sl->flash_size/2) { flash_page = (flashaddr - STM32_FLASH_BASE - sl->flash_size/2) / (uint32_t)(sl->flash_pgsz); // set bank 2 for erasure - val |= (1 << STM32L5_FLASH_NSCR_NSBKER); + val |= (1 << FLASH_L5_NSCR_NSBKER); } else { flash_page = ((flashaddr - STM32_FLASH_BASE) / (uint32_t)(sl->flash_pgsz)); // set bank 1 for erasure - val &= ~(1 << STM32L5_FLASH_NSCR_NSBKER); + val &= ~(1 << FLASH_L5_NSCR_NSBKER); } // sec 6.9.9 val &= ~(0x7F << 3); val |= ((flash_page & 0x7F) << 3) | (1 << FLASH_CR_PER); - stlink_write_debug32(sl, STM32L5_FLASH_NSCR, val); + stlink_write_debug32(sl, FLASH_L5_NSCR, val); } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { uint32_t flash_page = ((flashaddr - STM32_FLASH_BASE) / (uint32_t)(sl->flash_pgsz)); - stlink_read_debug32(sl, STM32WB_FLASH_CR, &val); + stlink_read_debug32(sl, FLASH_WB_CR, &val); // sec 3.10.5 - PNB[7:0] is offset by 3. val &= ~(0xFF << 3); // Clear previously set page number (if any) val |= ((flash_page & 0xFF) << 3); - stlink_write_debug32(sl, STM32WB_FLASH_CR, val); + stlink_write_debug32(sl, FLASH_WB_CR, val); } set_flash_cr_strt(sl, BANK_1); // set the 'start operation' bit diff --git a/src/stlink-lib/flash_loader.c b/src/stlink-lib/flash_loader.c index ebdf0a44e..f0ce9be42 100644 --- a/src/stlink-lib/flash_loader.c +++ b/src/stlink-lib/flash_loader.c @@ -495,18 +495,18 @@ static void set_flash_cr_pg(stlink_t *sl, unsigned bank) { cr_reg = FLASH_F7_CR; x |= 1 << FLASH_CR_PG; } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { - cr_reg = STM32L4_FLASH_CR; - x &= ~STM32L4_FLASH_CR_OPBITS; - x |= (1 << STM32L4_FLASH_CR_PG); + cr_reg = FLASH_L4_CR; + x &= ~FLASH_L4_CR_OPBITS; + x |= (1 << FLASH_L4_CR_PG); } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5) { - cr_reg = STM32L5_FLASH_NSCR; + cr_reg = FLASH_L5_NSCR; x |= (1 << FLASH_CR_PG); } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || sl->flash_type == STM32_FLASH_TYPE_G4) { - cr_reg = STM32Gx_FLASH_CR; + cr_reg = FLASH_Gx_CR; x |= (1 << FLASH_CR_PG); } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { - cr_reg = STM32WB_FLASH_CR; + cr_reg = FLASH_WB_CR; x |= (1 << FLASH_CR_PG); } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { cr_reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; @@ -545,7 +545,7 @@ static void set_dma_state(stlink_t *sl, flash_loader_t *fl, int bckpRstr) { rcc_dma_mask = STM32G4_RCC_DMAEN; break; case STM32_FLASH_TYPE_L0_L1: - if (get_stm32l0_flash_base(sl) == STM32L_FLASH_REGS_ADDR) { + if (get_stm32l0_flash_base(sl) == FLASH_Lx_REGS_ADDR) { rcc = STM32L1_RCC_AHBENR; rcc_dma_mask = STM32L1_RCC_DMAEN; } else { @@ -770,7 +770,7 @@ int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { uint32_t val; uint32_t flash_regs_base = get_stm32l0_flash_base(sl); - uint32_t pagesize = (flash_regs_base==STM32L0_FLASH_REGS_ADDR)? + uint32_t pagesize = (flash_regs_base == FLASH_L0_REGS_ADDR)? L0_WRITE_BLOCK_SIZE:L1_WRITE_BLOCK_SIZE; DLOG("Starting %3u page write\r\n", (unsigned int)(len / sl->flash_pgsz)); diff --git a/src/stlink-lib/option_bytes.c b/src/stlink-lib/option_bytes.c index 9cbdd097b..f5932a7b9 100644 --- a/src/stlink-lib/option_bytes.c +++ b/src/stlink-lib/option_bytes.c @@ -429,7 +429,7 @@ stlink_write_option_bytes_boot_add_f7(stlink_t *sl, uint32_t option_byte_boot_ad * @return 0 on success, -ve on failure. */ int stlink_read_option_control_register_gx(stlink_t *sl, uint32_t *option_byte) { - return stlink_read_debug32(sl, STM32Gx_FLASH_OPTR, option_byte); + return stlink_read_debug32(sl, FLASH_Gx_OPTR, option_byte); } /** @@ -461,21 +461,21 @@ static int stlink_write_option_bytes_gx(stlink_t *sl, stm32_addr_t addr, uint8_t write_uint32((unsigned char *)&data, *(uint32_t *)(base)); WLOG("Writing option bytes %#10x to %#10x\n", data, addr); - stlink_write_debug32(sl, STM32Gx_FLASH_OPTR, data); + stlink_write_debug32(sl, FLASH_Gx_OPTR, data); // Set Options Start bit - stlink_read_debug32(sl, STM32Gx_FLASH_CR, &val); - val |= (1 << STM32Gx_FLASH_CR_OPTSTRT); - stlink_write_debug32(sl, STM32Gx_FLASH_CR, val); + stlink_read_debug32(sl, FLASH_Gx_CR, &val); + val |= (1 << FLASH_Gx_CR_OPTSTRT); + stlink_write_debug32(sl, FLASH_Gx_CR, val); wait_flash_busy(sl); ret = check_flash_error(sl); // Reload options - stlink_read_debug32(sl, STM32Gx_FLASH_CR, &val); - val |= (1 << STM32Gx_FLASH_CR_OBL_LAUNCH); - stlink_write_debug32(sl, STM32Gx_FLASH_CR, val); + stlink_read_debug32(sl, FLASH_Gx_CR, &val); + val |= (1 << FLASH_Gx_CR_OBL_LAUNCH); + stlink_write_debug32(sl, FLASH_Gx_CR, val); return (ret); } @@ -584,7 +584,7 @@ static int stlink_write_option_bytes_l0(stlink_t *sl, stm32_addr_t addr, uint8_t // Reload options stlink_read_debug32(sl, flash_base + FLASH_PECR_OFF, &val); - val |= (1 << STM32L0_FLASH_OBL_LAUNCH); + val |= (1 << FLASH_L0_OBL_LAUNCH); stlink_write_debug32(sl, flash_base + FLASH_PECR_OFF, val); return (ret); @@ -612,20 +612,20 @@ static int stlink_write_option_bytes_l4(stlink_t *sl, stm32_addr_t addr, uint8_t uint32_t data; write_uint32((unsigned char *)&data, *(uint32_t *)(base)); WLOG("Writing option bytes 0x%04x\n", data); - stlink_write_debug32(sl, STM32L4_FLASH_OPTR, data); + stlink_write_debug32(sl, FLASH_L4_OPTR, data); // set options start bit - stlink_read_debug32(sl, STM32L4_FLASH_CR, &val); - val |= (1 << STM32L4_FLASH_CR_OPTSTRT); - stlink_write_debug32(sl, STM32L4_FLASH_CR, val); + stlink_read_debug32(sl, FLASH_L4_CR, &val); + val |= (1 << FLASH_L4_CR_OPTSTRT); + stlink_write_debug32(sl, FLASH_L4_CR, val); wait_flash_busy(sl); ret = check_flash_error(sl); // apply options bytes immediate - stlink_read_debug32(sl, STM32L4_FLASH_CR, &val); - val |= (1 << STM32L4_FLASH_CR_OBL_LAUNCH); - stlink_write_debug32(sl, STM32L4_FLASH_CR, val); + stlink_read_debug32(sl, FLASH_L4_CR, &val); + val |= (1 << FLASH_L4_CR_OBL_LAUNCH); + stlink_write_debug32(sl, FLASH_L4_CR, val); return (ret); } @@ -664,18 +664,18 @@ static int stlink_write_option_bytes_wb(stlink_t *sl, stm32_addr_t addr, uint8_t } // Set Options Start bit - stlink_read_debug32(sl, STM32WB_FLASH_CR, &val); - val |= (1 << STM32WB_FLASH_CR_OPTSTRT); - stlink_write_debug32(sl, STM32WB_FLASH_CR, val); + stlink_read_debug32(sl, FLASH_WB_CR, &val); + val |= (1 << FLASH_WB_CR_OPTSTRT); + stlink_write_debug32(sl, FLASH_WB_CR, val); wait_flash_busy(sl); ret = check_flash_error(sl); // Reload options - stlink_read_debug32(sl, STM32WB_FLASH_CR, &val); - val |= (1 << STM32WB_FLASH_CR_OBL_LAUNCH); - stlink_write_debug32(sl, STM32WB_FLASH_CR, val); + stlink_read_debug32(sl, FLASH_WB_CR, &val); + val |= (1 << FLASH_WB_CR_OBL_LAUNCH); + stlink_write_debug32(sl, FLASH_WB_CR, val); return (ret); } @@ -687,8 +687,8 @@ static int stlink_write_option_bytes_wb(stlink_t *sl, stm32_addr_t addr, uint8_t * @return 0 on success, -ve on failure. */ int stlink_read_option_control_register_wb(stlink_t *sl, uint32_t *option_byte) { - DLOG("@@@@ Read option control register byte from %#10x\n", STM32WB_FLASH_OPTR); - return stlink_read_debug32(sl, STM32WB_FLASH_OPTR, option_byte); + DLOG("@@@@ Read option control register byte from %#10x\n", FLASH_WB_OPTR); + return stlink_read_debug32(sl, FLASH_WB_OPTR, option_byte); } /** @@ -704,22 +704,22 @@ static int stlink_write_option_control_register_wb(stlink_t *sl, uint32_t option clear_flash_error(sl); ILOG("Asked to write option control register 1 %#10x to %#010x.\n", - option_cr, STM32WB_FLASH_OPTR); + option_cr, FLASH_WB_OPTR); /* write option byte, ensuring we dont lock opt, and set strt bit */ - stlink_write_debug32(sl, STM32WB_FLASH_OPTR, option_cr); + stlink_write_debug32(sl, FLASH_WB_OPTR, option_cr); wait_flash_busy(sl); // Set Options Start bit - uint32_t val = (1 << STM32WB_FLASH_CR_OPTSTRT); - stlink_write_debug32(sl, STM32WB_FLASH_CR, val); + uint32_t val = (1 << FLASH_WB_CR_OPTSTRT); + stlink_write_debug32(sl, FLASH_WB_CR, val); wait_flash_busy(sl); ret = check_flash_error(sl); if (!ret) - ILOG("Wrote option bytes %#010x to %#010x!\n", option_cr, STM32WB_FLASH_OPTR); + ILOG("Wrote option bytes %#010x to %#010x!\n", option_cr, FLASH_WB_OPTR); return ret; } From 5621d541d9b175e0fb6d1354fedd1da5ff5c1902 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Wed, 3 May 2023 13:55:19 +0200 Subject: [PATCH 440/503] Resorted #defines in stm32flash.h --- inc/stm32flash.h | 498 ++++++++++++++++++---------------- src/stlink-lib/common.c | 3 +- src/stlink-lib/common_flash.c | 2 +- src/stlink-lib/flash_loader.c | 4 +- 4 files changed, 269 insertions(+), 238 deletions(-) diff --git a/inc/stm32flash.h b/inc/stm32flash.h index ccbc0289d..12d2f5a7b 100644 --- a/inc/stm32flash.h +++ b/inc/stm32flash.h @@ -1,8 +1,8 @@ #ifndef STM32FLASH_H_ #define STM32FLASH_H_ -/* stm32f FPEC flash controller interface, pm0063 manual */ -// STM32F05x is identical, based on RM0091 (DM00031936, Doc ID 018940 Rev 2, August 2012) +/* STM32Fx FPEC flash controller interface, PM0063 manual */ +// STM32F05x is identical, based on RM0091 (DM00031936, Doc ID 018940 Rev.2, Aug 2012) #define FLASH_REGS_ADDR 0x40022000 #define FLASH_REGS_SIZE 0x28 @@ -15,32 +15,19 @@ #define FLASH_OBR (FLASH_REGS_ADDR + 0x1c) #define FLASH_WRPR (FLASH_REGS_ADDR + 0x20) -// STM32F10x_XL has two flash memory banks with separate registers to control -// the second bank. +// STM32F10x_XL has two flash memory banks +// with separate registers to control the second bank. #define FLASH_KEYR2 (FLASH_REGS_ADDR + 0x44) #define FLASH_SR2 (FLASH_REGS_ADDR + 0x4c) #define FLASH_CR2 (FLASH_REGS_ADDR + 0x50) #define FLASH_AR2 (FLASH_REGS_ADDR + 0x54) -// For STM32F05x, the RDPTR_KEY may be wrong, but as it is not used anywhere... #define FLASH_RDPTR_KEY 0x00a5 #define FLASH_KEY1 0x45670123 #define FLASH_KEY2 0xcdef89ab -#define FLASH_L0_PRGKEY1 0x8c9daebf -#define FLASH_L0_PRGKEY2 0x13141516 - -#define FLASH_L0_PEKEY1 0x89abcdef -#define FLASH_L0_PEKEY2 0x02030405 - -#define FLASH_OPTKEY1 0x08192A3B -#define FLASH_OPTKEY2 0x4C5D6E7F - -#define FLASH_F0_OPTKEY1 0x45670123 -#define FLASH_F0_OPTKEY2 0xCDEF89AB - -#define FLASH_L0_OPTKEY1 0xFBEAD9C8 -#define FLASH_L0_OPTKEY2 0x24252627 +#define FLASH_OPTKEY1 0x08192a3b +#define FLASH_OPTKEY2 0x4c5d6e7f #define FLASH_SR_BSY 0 #define FLASH_SR_PG_ERR 2 @@ -59,20 +46,99 @@ #define FLASH_CR_OPTWRE 9 #define FLASH_CR_OBL_LAUNCH 13 -#define FLASH_Lx_REGS_ADDR ((uint32_t)0x40023c00) -#define FLASH_Lx_ACR (FLASH_Lx_REGS_ADDR + 0x00) -#define FLASH_Lx_PECR (FLASH_Lx_REGS_ADDR + 0x04) -#define FLASH_Lx_PDKEYR (FLASH_Lx_REGS_ADDR + 0x08) -#define FLASH_Lx_PEKEYR (FLASH_Lx_REGS_ADDR + 0x0c) -#define FLASH_Lx_PRGKEYR (FLASH_Lx_REGS_ADDR + 0x10) -#define FLASH_Lx_OPTKEYR (FLASH_Lx_REGS_ADDR + 0x14) -#define FLASH_Lx_SR (FLASH_Lx_REGS_ADDR + 0x18) -#define FLASH_Lx_OBR (FLASH_Lx_REGS_ADDR + 0x1c) -#define FLASH_Lx_WRPR (FLASH_Lx_REGS_ADDR + 0x20) -#define FLASH_L1_FPRG 10 -#define FLASH_L1_PROG 3 +#define FLASH_ACR_OFF ((uint32_t)0x00) +#define FLASH_PECR_OFF ((uint32_t)0x04) +#define FLASH_PDKEYR_OFF ((uint32_t)0x08) +#define FLASH_PEKEYR_OFF ((uint32_t)0x0c) +#define FLASH_PRGKEYR_OFF ((uint32_t)0x10) +#define FLASH_OPTKEYR_OFF ((uint32_t)0x14) +#define FLASH_SR_OFF ((uint32_t)0x18) +#define FLASH_OBR_OFF ((uint32_t)0x1c) +#define FLASH_WRPR_OFF ((uint32_t)0x20) + +// == STM32F0 == +#define FLASH_F0_OPTKEY1 0x45670123 +#define FLASH_F0_OPTKEY2 0xcdef89ab + +// == STM32F2 == +#define FLASH_F2_REGS_ADDR ((uint32_t)0x40023c00) +#define FLASH_F2_KEYR (FLASH_F2_REGS_ADDR + 0x04) +#define FLASH_F2_OPT_KEYR (FLASH_F2_REGS_ADDR + 0x08) +#define FLASH_F2_SR (FLASH_F2_REGS_ADDR + 0x0c) +#define FLASH_F2_CR (FLASH_F2_REGS_ADDR + 0x10) +#define FLASH_F2_OPT_CR (FLASH_F2_REGS_ADDR + 0x14) +#define FLASH_F2_OPT_LOCK_BIT (1u << 0) + +// F2 Flash control register +#define FLASH_F2_CR_STRT 16 +#define FLASH_F2_CR_LOCK 31 +#define FLASH_F2_CR_SER 1 +#define FLASH_F2_CR_SNB 3 +#define FLASH_F2_CR_SNB_MASK 0x78 + +// F2 Flash status register +#define FLASH_F2_SR_BSY 16 + +// == STM32F4 == +// F4 Flash registers +#define FLASH_F4_REGS_ADDR ((uint32_t)0x40023c00) +#define FLASH_F4_KEYR (FLASH_F4_REGS_ADDR + 0x04) +#define FLASH_F4_OPT_KEYR (FLASH_F4_REGS_ADDR + 0x08) +#define FLASH_F4_SR (FLASH_F4_REGS_ADDR + 0x0c) +#define FLASH_F4_CR (FLASH_F4_REGS_ADDR + 0x10) +#define FLASH_F4_OPTCR (FLASH_F4_REGS_ADDR + 0x14) +#define FLASH_F4_OPTCR_LOCK 0 +#define FLASH_F4_OPTCR_START 1 + +// F4 Flash control register +#define FLASH_F4_CR_STRT 16 +#define FLASH_F4_CR_LOCK 31 +#define FLASH_F4_CR_SER 1 +#define FLASH_F4_CR_SNB 3 +#define FLASH_F4_CR_SNB_MASK 0xf8 + +// F4 Flash status register +#define FLASH_F4_SR_ERROR_MASK 0x000000F0 +#define FLASH_F4_SR_PGAERR 5 +#define FLASH_F4_SR_WRPERR 4 +#define FLASH_F4_SR_BSY 16 -// Flash registers common to STM32G0 and STM32G4 series (RM0440, p. 146) +// == STM32F7 == +// F7 Flash registers +#define FLASH_F7_REGS_ADDR ((uint32_t)0x40023c00) +#define FLASH_F7_KEYR (FLASH_F7_REGS_ADDR + 0x04) +#define FLASH_F7_OPT_KEYR (FLASH_F7_REGS_ADDR + 0x08) +#define FLASH_F7_SR (FLASH_F7_REGS_ADDR + 0x0c) +#define FLASH_F7_CR (FLASH_F7_REGS_ADDR + 0x10) +#define FLASH_F7_OPTCR (FLASH_F7_REGS_ADDR + 0x14) +#define FLASH_F7_OPTCR1 (FLASH_F7_REGS_ADDR + 0x18) +#define FLASH_F7_OPTCR_LOCK 0 +#define FLASH_F7_OPTCR_START 1 +#define FLASH_F7_OPTCR1_BOOT_ADD0 0 +#define FLASH_F7_OPTCR1_BOOT_ADD1 16 + +// F7 Flash control register +#define FLASH_F7_CR_STRT 16 +#define FLASH_F7_CR_LOCK 31 +#define FLASH_F7_CR_SER 1 +#define FLASH_F7_CR_SNB 3 +#define FLASH_F7_CR_SNB_MASK 0xf8 + +// F7 Flash status register +#define FLASH_F7_SR_BSY 16 +#define FLASH_F7_SR_ERS_ERR 7 /* Erase Sequence Error */ +#define FLASH_F7_SR_PGP_ERR 6 /* Programming parallelism error */ +#define FLASH_F7_SR_PGA_ERR 5 /* Programming alignment error */ +#define FLASH_F7_SR_WRP_ERR 4 /* Write protection error */ +#define FLASH_F7_SR_OP_ERR 1 /* Operation error */ +#define FLASH_F7_SR_EOP 0 /* End of operation */ +#define FLASH_F7_SR_ERROR_MASK \ + ((1 << FLASH_F7_SR_ERS_ERR) | (1 << FLASH_F7_SR_PGP_ERR) | \ + (1 << FLASH_F7_SR_PGA_ERR) | (1 << FLASH_F7_SR_WRP_ERR) | \ + (1 << FLASH_F7_SR_OP_ERR)) + +// == STM32G0/G4 == +// G0/G4 Flash registers (RM0440, p.146) #define FLASH_Gx_REGS_ADDR ((uint32_t)0x40022000) #define FLASH_Gx_ACR (FLASH_Gx_REGS_ADDR + 0x00) #define FLASH_Gx_KEYR (FLASH_Gx_REGS_ADDR + 0x08) @@ -82,111 +148,171 @@ #define FLASH_Gx_ECCR (FLASH_Gx_REGS_ADDR + 0x18) #define FLASH_Gx_OPTR (FLASH_Gx_REGS_ADDR + 0x20) -// G0 (RM0444 Table 1, sec 3.7) +// G0/G4 Flash control register +#define FLASH_Gx_CR_PG (0) /* Program */ +#define FLASH_Gx_CR_PER (1) /* Page erase */ +#define FLASH_Gx_CR_MER1 (2) /* Mass erase */ +#define FLASH_Gx_CR_PNB (3) /* Page number */ +#define FLASH_G0_CR_PNG_LEN (5) /* STM32G0: 5 page number bits */ +#define FLASH_G4_CR_PNG_LEN (7) /* STM32G4: 7 page number bits */ +#define FLASH_Gx_CR_MER2 (15) /* Mass erase (2nd bank)*/ +#define FLASH_Gx_CR_STRT (16) /* Start */ +#define FLASH_Gx_CR_OPTSTRT (17) /* Start of modification of option bytes */ +#define FLASH_Gx_CR_FSTPG (18) /* Fast programming */ +#define FLASH_Gx_CR_EOPIE (24) /* End of operation interrupt enable */ +#define FLASH_Gx_CR_ERRIE (25) /* Error interrupt enable */ +#define FLASH_Gx_CR_OBL_LAUNCH (27) /* Forces the option byte loading */ +#define FLASH_Gx_CR_OPTLOCK (30) /* Options Lock */ +#define FLASH_Gx_CR_LOCK (31) /* FLASH_CR Lock */ + +// G0/G4 Flash status register +#define FLASH_Gx_SR_ERROR_MASK (0x3fa) +#define FLASH_Gx_SR_PROGERR (3) +#define FLASH_Gx_SR_WRPERR (4) +#define FLASH_Gx_SR_PGAERR (5) +#define FLASH_Gx_SR_BSY (16) /* FLASH_SR Busy */ +#define FLASH_Gx_SR_EOP (0) /* FLASH_EOP End of Operation */ + +// == STM32G0 == (RM0444 Table 1, sec. 3.7) // Mostly the same as G4 chips, but the notation // varies a bit after the 'OPTR' register. #define FLASH_G0_REGS_ADDR (FLASH_Gx_REGS_ADDR) #define FLASH_G0_PCROP1ASR (FLASH_G0_REGS_ADDR + 0x24) #define FLASH_G0_PCROP1AER (FLASH_G0_REGS_ADDR + 0x28) -#define FLASH_G0_WRP1AR (FLASH_G0_REGS_ADDR + 0x2C) +#define FLASH_G0_WRP1AR (FLASH_G0_REGS_ADDR + 0x2c) #define FLASH_G0_WRP1BR (FLASH_G0_REGS_ADDR + 0x30) #define FLASH_G0_PCROP1BSR (FLASH_G0_REGS_ADDR + 0x34) #define FLASH_G0_PCROP1BER (FLASH_G0_REGS_ADDR + 0x38) #define FLASH_G0_SECR (FLASH_G0_REGS_ADDR + 0x80) -// G4 (RM0440 Table 17, sec 3.7.19) -// Mostly the same as STM32G0 chips, but there are a few extra -// registers because 'cat 3' devices can have two Flash banks. +// == STM32G4 == (RM0440 Table 17, sec. 3.7.19) + +#define FLASH_G4_OPTR_DBANK (22) /* FLASH option register FLASH_OPTR Dual-Bank Mode */ + +// There are a few extra registers because 'cat 3' devices can have +// two Flash banks. #define FLASH_G4_REGS_ADDR (FLASH_Gx_REGS_ADDR) #define FLASH_G4_PDKEYR (FLASH_G4_REGS_ADDR + 0x04) #define FLASH_G4_PCROP1SR (FLASH_G4_REGS_ADDR + 0x24) #define FLASH_G4_PCROP1ER (FLASH_G4_REGS_ADDR + 0x28) -#define FLASH_G4_WRP1AR (FLASH_G4_REGS_ADDR + 0x2C) +#define FLASH_G4_WRP1AR (FLASH_G4_REGS_ADDR + 0x2c) #define FLASH_G4_WRP1BR (FLASH_G4_REGS_ADDR + 0x30) #define FLASH_G4_PCROP2SR (FLASH_G4_REGS_ADDR + 0x44) #define FLASH_G4_PCROP2ER (FLASH_G4_REGS_ADDR + 0x48) -#define FLASH_G4_WRP2AR (FLASH_G4_REGS_ADDR + 0x4C) +#define FLASH_G4_WRP2AR (FLASH_G4_REGS_ADDR + 0x4c) #define FLASH_G4_WRP2BR (FLASH_G4_REGS_ADDR + 0x50) #define FLASH_G4_SEC1R (FLASH_G4_REGS_ADDR + 0x70) #define FLASH_G4_SEC2R (FLASH_G4_REGS_ADDR + 0x74) -// G0/G4 FLASH control register -#define FLASH_Gx_CR_PG (0) /* Program */ -#define FLASH_Gx_CR_PER (1) /* Page erase */ -#define FLASH_Gx_CR_MER1 (2) /* Mass erase */ -#define FLASH_Gx_CR_PNB (3) /* Page number */ -#define FLASH_G0_CR_PNG_LEN (5) /* STM32G0: 5 page number bits */ -#define FLASH_G4_CR_PNG_LEN (7) /* STM32G4: 7 page number bits */ -#define FLASH_Gx_CR_MER2 (15) /* Mass erase (2nd bank)*/ -#define FLASH_Gx_CR_STRT (16) /* Start */ -#define FLASH_Gx_CR_OPTSTRT \ - (17) /* Start of modification of option bytes */ -#define FLASH_Gx_CR_FSTPG (18) /* Fast programming */ -#define FLASH_Gx_CR_EOPIE (24) /* End of operation interrupt enable */ -#define FLASH_Gx_CR_ERRIE (25) /* Error interrupt enable */ -#define FLASH_Gx_CR_OBL_LAUNCH (27) /* Forces the option byte loading */ -#define FLASH_Gx_CR_OPTLOCK (30) /* Options Lock */ -#define FLASH_Gx_CR_LOCK (31) /* FLASH_CR Lock */ +// == STM32H7 == +// H7 Flash registers +#define FLASH_H7_REGS_ADDR ((uint32_t)0x52002000) +#define FLASH_H7_KEYR1 (FLASH_H7_REGS_ADDR + 0x04) +#define FLASH_H7_KEYR2 (FLASH_H7_REGS_ADDR + 0x104) +#define FLASH_H7_OPT_KEYR (FLASH_H7_REGS_ADDR + 0x08) +#define FLASH_H7_OPT_KEYR2 (FLASH_H7_REGS_ADDR + 0x108) +#define FLASH_H7_CR1 (FLASH_H7_REGS_ADDR + 0x0c) +#define FLASH_H7_CR2 (FLASH_H7_REGS_ADDR + 0x10c) +#define FLASH_H7_SR1 (FLASH_H7_REGS_ADDR + 0x10) +#define FLASH_H7_SR2 (FLASH_H7_REGS_ADDR + 0x110) +#define FLASH_H7_CCR1 (FLASH_H7_REGS_ADDR + 0x14) +#define FLASH_H7_CCR2 (FLASH_H7_REGS_ADDR + 0x114) +#define FLASH_H7_OPTCR (FLASH_H7_REGS_ADDR + 0x18) +#define FLASH_H7_OPTCR2 (FLASH_H7_REGS_ADDR + 0x118) +#define FLASH_H7_OPTSR_CUR (FLASH_H7_REGS_ADDR + 0x1c) +#define FLASH_H7_OPTCCR (FLASH_H7_REGS_ADDR + 0x24) -// G0/G4 FLASH status register -#define FLASH_Gx_SR_ERROR_MASK (0x3fa) -#define FLASH_Gx_SR_PROGERR (3) -#define FLASH_Gx_SR_WRPERR (4) -#define FLASH_Gx_SR_PGAERR (5) -#define FLASH_Gx_SR_BSY (16) /* FLASH_SR Busy */ -#define FLASH_Gx_SR_EOP (0) /* FLASH_EOP End of Operation */ +#define FLASH_H7_OPTCR_OPTLOCK 0 +#define FLASH_H7_OPTCR_OPTSTART 1 +#define FLASH_H7_OPTCR_MER 4 -// G4 FLASH option register -#define FLASH_G4_OPTR_DBANK (22) /* FLASH_OPTR Dual Bank Mode */ +#define FLASH_H7_OPTSR_OPT_BUSY 0 +#define FLASH_H7_OPTSR_OPTCHANGEERR 30 -// WB (RM0434) -#define FLASH_WB_REGS_ADDR ((uint32_t)0x58004000) -#define FLASH_WB_ACR (FLASH_WB_REGS_ADDR + 0x00) -#define FLASH_WB_KEYR (FLASH_WB_REGS_ADDR + 0x08) -#define FLASH_WB_OPT_KEYR (FLASH_WB_REGS_ADDR + 0x0C) -#define FLASH_WB_SR (FLASH_WB_REGS_ADDR + 0x10) -#define FLASH_WB_CR (FLASH_WB_REGS_ADDR + 0x14) -#define FLASH_WB_ECCR (FLASH_WB_REGS_ADDR + 0x18) -#define FLASH_WB_OPTR (FLASH_WB_REGS_ADDR + 0x20) -#define FLASH_WB_PCROP1ASR (FLASH_WB_REGS_ADDR + 0x24) -#define FLASH_WB_PCROP1AER (FLASH_WB_REGS_ADDR + 0x28) -#define FLASH_WB_WRP1AR (FLASH_WB_REGS_ADDR + 0x2C) -#define FLASH_WB_WRP1BR (FLASH_WB_REGS_ADDR + 0x30) -#define FLASH_WB_PCROP1BSR (FLASH_WB_REGS_ADDR + 0x34) -#define FLASH_WB_PCROP1BER (FLASH_WB_REGS_ADDR + 0x38) -#define FLASH_WB_IPCCBR (FLASH_WB_REGS_ADDR + 0x3C) -#define FLASH_WB_C2ACR (FLASH_WB_REGS_ADDR + 0x5C) -#define FLASH_WB_C2SR (FLASH_WB_REGS_ADDR + 0x60) -#define FLASH_WB_C2CR (FLASH_WB_REGS_ADDR + 0x64) -#define FLASH_WB_SFR (FLASH_WB_REGS_ADDR + 0x80) -#define FLASH_WB_SRRVR (FLASH_WB_REGS_ADDR + 0x84) +#define FLASH_H7_OPTCCR_CLR_OPTCHANGEERR 30 -// WB Flash control register. -#define FLASH_WB_CR_STRT (16) /* Start */ -#define FLASH_WB_CR_OPTSTRT (17) /* Start writing option bytes */ -#define FLASH_WB_CR_OBL_LAUNCH (27) /* Forces the option byte loading */ -#define FLASH_WB_CR_OPTLOCK (30) /* Option Lock */ -#define FLASH_WB_CR_LOCK (31) /* Lock */ -// WB Flash status register. -#define FLASH_WB_SR_ERROR_MASK (0x3f8) /* SR [9:3] */ -#define FLASH_WB_SR_PROGERR (3) /* Programming alignment error */ -#define FLASH_WB_SR_WRPERR (4) /* Write protection error */ -#define FLASH_WB_SR_PGAERR (5) /* Programming error */ -#define FLASH_WB_SR_BSY (16) /* Busy */ +// H7 Flash control register +#define FLASH_H7_CR_LOCK 0 +#define FLASH_H7_CR_PG 1 +#define FLASH_H7_CR_SER 2 +#define FLASH_H7_CR_BER 3 +#define FLASH_H7_CR_PSIZE 4 +#define FLASH_H7_CR_START(chipid) (chipid == STM32_CHIPID_H7Ax ? 5 : 7) +#define FLASH_H7_CR_SNB 8 +#define FLASH_H7_CR_SNB_MASK 0x700 -// 32L4 register base is at FLASH_REGS_ADDR (0x40022000) +// H7 Flash status register +#define FLASH_H7_SR_QW 2 +#define FLASH_H7_SR_WRPERR 17 +#define FLASH_H7_SR_PGSERR 18 +#define FLASH_H7_SR_STRBERR 19 +#define FLASH_H7_SR_ERROR_MASK \ + ((1 << FLASH_H7_SR_PGSERR) | (1 << FLASH_H7_SR_STRBERR) | \ + (1 << FLASH_H7_SR_WRPERR)) + +// == STM32L0/L1/L4/L5 == +// Lx Flash registers +#define FLASH_Lx_REGS_ADDR ((uint32_t)0x40023c00) +#define FLASH_Lx_ACR (FLASH_Lx_REGS_ADDR + 0x00) +#define FLASH_Lx_PECR (FLASH_Lx_REGS_ADDR + 0x04) +#define FLASH_Lx_PDKEYR (FLASH_Lx_REGS_ADDR + 0x08) +#define FLASH_Lx_PEKEYR (FLASH_Lx_REGS_ADDR + 0x0c) +#define FLASH_Lx_PRGKEYR (FLASH_Lx_REGS_ADDR + 0x10) +#define FLASH_Lx_OPTKEYR (FLASH_Lx_REGS_ADDR + 0x14) +#define FLASH_Lx_SR (FLASH_Lx_REGS_ADDR + 0x18) +#define FLASH_Lx_OBR (FLASH_Lx_REGS_ADDR + 0x1c) +#define FLASH_Lx_WRPR (FLASH_Lx_REGS_ADDR + 0x20) + +// == STM32L0 == +// L0 Flash registers +#define FLASH_L0_PEKEY1 0x89abcdef +#define FLASH_L0_PEKEY2 0x02030405 + +#define FLASH_L0_PRGKEY1 0x8c9daebf +#define FLASH_L0_PRGKEY2 0x13141516 + +#define FLASH_L0_OPTKEY1 0xFBEAD9C8 +#define FLASH_L0_OPTKEY2 0x24252627 + +#define FLASH_L0_REGS_ADDR ((uint32_t)0x40022000) + +#define FLASH_L0_PELOCK (0) +#define FLASH_L0_OPTLOCK (2) +#define FLASH_L0_OBL_LAUNCH (18) + +// L0 Flash status register +#define FLASH_L0_SR_ERROR_MASK 0x00013f00 +#define FLASH_L0_SR_WRPERR 8 +#define FLASH_L0_SR_PGAERR 9 +#define FLASH_L0_SR_NOTZEROERR 16 + +// == STM32L1 == +// L1 Flash registers +#define FLASH_L1_FPRG 10 +#define FLASH_L1_PROG 3 + +// L1 Flash status register +#define FLASH_L1_SR_ERROR_MASK 0x00003f00 +#define FLASH_L1_SR_WRPERR 8 +#define FLASH_L1_SR_PGAERR 9 + +// == STM32L4 == +// L4 Flash registers +// L4 register base is at FLASH_REGS_ADDR (0x40022000) #define FLASH_L4_KEYR (FLASH_REGS_ADDR + 0x08) -#define FLASH_L4_OPTKEYR (FLASH_REGS_ADDR + 0x0C) +#define FLASH_L4_OPTKEYR (FLASH_REGS_ADDR + 0x0c) #define FLASH_L4_SR (FLASH_REGS_ADDR + 0x10) #define FLASH_L4_CR (FLASH_REGS_ADDR + 0x14) #define FLASH_L4_OPTR (FLASH_REGS_ADDR + 0x20) +// L4 Flash status register #define FLASH_L4_SR_ERROR_MASK 0x3f8 /* SR [9:3] */ #define FLASH_L4_SR_PROGERR 3 #define FLASH_L4_SR_WRPERR 4 #define FLASH_L4_SR_PGAERR 5 #define FLASH_L4_SR_BSY 16 +// L4 Flash control register #define FLASH_L4_CR_LOCK 31 /* Lock control register */ #define FLASH_L4_CR_OPTLOCK 30 /* Lock option bytes */ #define FLASH_L4_CR_PG 0 /* Program */ @@ -207,7 +333,8 @@ #define FLASH_L4_OPTR_DUALBANK 21 -// Flash registers common to STM32L5 series (RM0438, p. 241) +// == STM32L5 == (RM0438, p.241) +// L5 Flash registers #define FLASH_L5_REGS_ADDR ((uint32_t)0x40022000) #define FLASH_L5_ACR (FLASH_L5_REGS_ADDR + 0x00) #define FLASH_L5_NSKEYR (FLASH_L5_REGS_ADDR + 0x08) @@ -217,7 +344,7 @@ #define FLASH_L5_ECCR (FLASH_L5_REGS_ADDR + 0x30) #define FLASH_L5_OPTR (FLASH_L5_REGS_ADDR + 0x40) -// FLASH_NSCR (RM0438, p. 242) +// FLASH_NSCR control registers (RM0438, p. 242) #define FLASH_L5_NSCR_NSPG 0 /* Program */ #define FLASH_L5_NSCR_NSPER 1 /* Page erase */ #define FLASH_L5_NSCR_NSMER1 2 /* Bank 1 erase */ @@ -232,7 +359,7 @@ #define FLASH_L5_NSCR_OPTLOCK 30 /* Lock option bytes */ #define FLASH_L5_NSCR_NSLOCK 31 /* Lock control register */ -// FLASH_NSSR (RM0438, p. 241) +// FLASH_NSSR status register (RM0438, p. 241) #define FLASH_L5_NSSR_NSEOP 0 /* End of Operation */ #define FLASH_L5_NSSR_NSOPERR 1 #define FLASH_L5_NSSR_NSPROGERR 3 @@ -244,138 +371,41 @@ #define FLASH_L5_NSSR_BSY 16 /* Busy */ #define FLASH_L5_NSSR_ERROR_MASK (0x20fa) -// STM32L0x flash register base and offsets RM0090 - DM00031020.pdf -#define FLASH_L0_REGS_ADDR ((uint32_t)0x40022000) - -#define FLASH_L0_PELOCK (0) -#define FLASH_L0_OPTLOCK (2) -#define FLASH_L0_OBL_LAUNCH (18) - -#define FLASH_L0_SR_ERROR_MASK 0x00013F00 -#define FLASH_L0_SR_WRPERR 8 -#define FLASH_L0_SR_PGAERR 9 -#define FLASH_L0_SR_NOTZEROERR 16 - -#define FLASH_L1_SR_ERROR_MASK 0x00003F00 -#define FLASH_L1_SR_WRPERR 8 -#define FLASH_L1_SR_PGAERR 9 - -#define FLASH_ACR_OFF ((uint32_t)0x00) -#define FLASH_PECR_OFF ((uint32_t)0x04) -#define FLASH_PDKEYR_OFF ((uint32_t)0x08) -#define FLASH_PEKEYR_OFF ((uint32_t)0x0c) -#define FLASH_PRGKEYR_OFF ((uint32_t)0x10) -#define FLASH_OPTKEYR_OFF ((uint32_t)0x14) -#define FLASH_SR_OFF ((uint32_t)0x18) -#define FLASH_OBR_OFF ((uint32_t)0x1c) -#define FLASH_WRPR_OFF ((uint32_t)0x20) - -// STM32F7 -#define FLASH_F7_REGS_ADDR ((uint32_t)0x40023c00) -#define FLASH_F7_KEYR (FLASH_F7_REGS_ADDR + 0x04) -#define FLASH_F7_OPT_KEYR (FLASH_F7_REGS_ADDR + 0x08) -#define FLASH_F7_SR (FLASH_F7_REGS_ADDR + 0x0c) -#define FLASH_F7_CR (FLASH_F7_REGS_ADDR + 0x10) -#define FLASH_F7_OPTCR (FLASH_F7_REGS_ADDR + 0x14) -#define FLASH_F7_OPTCR1 (FLASH_F7_REGS_ADDR + 0x18) -#define FLASH_F7_OPTCR_LOCK 0 -#define FLASH_F7_OPTCR_START 1 -#define FLASH_F7_CR_STRT 16 -#define FLASH_F7_CR_LOCK 31 -#define FLASH_F7_CR_SER 1 -#define FLASH_F7_CR_SNB 3 -#define FLASH_F7_CR_SNB_MASK 0xf8 -#define FLASH_F7_SR_BSY 16 -#define FLASH_F7_SR_ERS_ERR 7 /* Erase Sequence Error */ -#define FLASH_F7_SR_PGP_ERR 6 /* Programming parallelism error */ -#define FLASH_F7_SR_PGA_ERR 5 /* Programming alignment error */ -#define FLASH_F7_SR_WRP_ERR 4 /* Write protection error */ -#define FLASH_F7_SR_OP_ERR 1 /* Operation error */ -#define FLASH_F7_SR_EOP 0 /* End of operation */ -#define FLASH_F7_OPTCR1_BOOT_ADD0 0 -#define FLASH_F7_OPTCR1_BOOT_ADD1 16 - -#define FLASH_F7_SR_ERROR_MASK \ - ((1 << FLASH_F7_SR_ERS_ERR) | (1 << FLASH_F7_SR_PGP_ERR) | \ - (1 << FLASH_F7_SR_PGA_ERR) | (1 << FLASH_F7_SR_WRP_ERR) | \ - (1 << FLASH_F7_SR_OP_ERR)) - -// STM32F4 -#define FLASH_F4_REGS_ADDR ((uint32_t)0x40023c00) -#define FLASH_F4_KEYR (FLASH_F4_REGS_ADDR + 0x04) -#define FLASH_F4_OPT_KEYR (FLASH_F4_REGS_ADDR + 0x08) -#define FLASH_F4_SR (FLASH_F4_REGS_ADDR + 0x0c) -#define FLASH_F4_CR (FLASH_F4_REGS_ADDR + 0x10) -#define FLASH_F4_OPTCR (FLASH_F4_REGS_ADDR + 0x14) -#define FLASH_F4_OPTCR_LOCK 0 -#define FLASH_F4_OPTCR_START 1 -#define FLASH_F4_CR_STRT 16 -#define FLASH_F4_CR_LOCK 31 -#define FLASH_F4_CR_SER 1 -#define FLASH_F4_CR_SNB 3 -#define FLASH_F4_CR_SNB_MASK 0xf8 -#define FLASH_F4_SR_ERROR_MASK 0x000000F0 -#define FLASH_F4_SR_PGAERR 5 -#define FLASH_F4_SR_WRPERR 4 -#define FLASH_F4_SR_BSY 16 - -// STM32F2 -#define FLASH_F2_REGS_ADDR ((uint32_t)0x40023c00) -#define FLASH_F2_KEYR (FLASH_F2_REGS_ADDR + 0x04) -#define FLASH_F2_OPT_KEYR (FLASH_F2_REGS_ADDR + 0x08) -#define FLASH_F2_SR (FLASH_F2_REGS_ADDR + 0x0c) -#define FLASH_F2_CR (FLASH_F2_REGS_ADDR + 0x10) -#define FLASH_F2_OPT_CR (FLASH_F2_REGS_ADDR + 0x14) -#define FLASH_F2_OPT_LOCK_BIT (1u << 0) -#define FLASH_F2_CR_STRT 16 -#define FLASH_F2_CR_LOCK 31 - -#define FLASH_F2_CR_SER 1 -#define FLASH_F2_CR_SNB 3 -#define FLASH_F2_CR_SNB_MASK 0x78 -#define FLASH_F2_SR_BSY 16 - -// STM32H7xx -#define FLASH_H7_CR_LOCK 0 -#define FLASH_H7_CR_PG 1 -#define FLASH_H7_CR_SER 2 -#define FLASH_H7_CR_BER 3 -#define FLASH_H7_CR_PSIZE 4 -#define FLASH_H7_CR_START(chipid) (chipid == STM32_CHIPID_H7Ax ? 5 : 7) -#define FLASH_H7_CR_SNB 8 -#define FLASH_H7_CR_SNB_MASK 0x700 - -#define FLASH_H7_SR_QW 2 -#define FLASH_H7_SR_WRPERR 17 -#define FLASH_H7_SR_PGSERR 18 -#define FLASH_H7_SR_STRBERR 19 -#define FLASH_H7_SR_ERROR_MASK \ - ((1 << FLASH_H7_SR_PGSERR) | (1 << FLASH_H7_SR_STRBERR) | \ - (1 << FLASH_H7_SR_WRPERR)) - -#define FLASH_H7_OPTCR_OPTLOCK 0 -#define FLASH_H7_OPTCR_OPTSTART 1 -#define FLASH_H7_OPTCR_MER 4 - -#define FLASH_H7_OPTSR_OPT_BUSY 0 -#define FLASH_H7_OPTSR_OPTCHANGEERR 30 +// == STM32WB == (RM0434) +// WB Flash registers +#define FLASH_WB_REGS_ADDR ((uint32_t)0x58004000) +#define FLASH_WB_ACR (FLASH_WB_REGS_ADDR + 0x00) +#define FLASH_WB_KEYR (FLASH_WB_REGS_ADDR + 0x08) +#define FLASH_WB_OPT_KEYR (FLASH_WB_REGS_ADDR + 0x0c) +#define FLASH_WB_SR (FLASH_WB_REGS_ADDR + 0x10) +#define FLASH_WB_CR (FLASH_WB_REGS_ADDR + 0x14) +#define FLASH_WB_ECCR (FLASH_WB_REGS_ADDR + 0x18) +#define FLASH_WB_OPTR (FLASH_WB_REGS_ADDR + 0x20) +#define FLASH_WB_PCROP1ASR (FLASH_WB_REGS_ADDR + 0x24) +#define FLASH_WB_PCROP1AER (FLASH_WB_REGS_ADDR + 0x28) +#define FLASH_WB_WRP1AR (FLASH_WB_REGS_ADDR + 0x2c) +#define FLASH_WB_WRP1BR (FLASH_WB_REGS_ADDR + 0x30) +#define FLASH_WB_PCROP1BSR (FLASH_WB_REGS_ADDR + 0x34) +#define FLASH_WB_PCROP1BER (FLASH_WB_REGS_ADDR + 0x38) +#define FLASH_WB_IPCCBR (FLASH_WB_REGS_ADDR + 0x3c) +#define FLASH_WB_C2ACR (FLASH_WB_REGS_ADDR + 0x5c) +#define FLASH_WB_C2SR (FLASH_WB_REGS_ADDR + 0x60) +#define FLASH_WB_C2CR (FLASH_WB_REGS_ADDR + 0x64) +#define FLASH_WB_SFR (FLASH_WB_REGS_ADDR + 0x80) +#define FLASH_WB_SRRVR (FLASH_WB_REGS_ADDR + 0x84) -#define FLASH_H7_OPTCCR_CLR_OPTCHANGEERR 30 +// WB Flash control register +#define FLASH_WB_CR_STRT (16) /* Start */ +#define FLASH_WB_CR_OPTSTRT (17) /* Start writing option bytes */ +#define FLASH_WB_CR_OBL_LAUNCH (27) /* Forces the option byte loading */ +#define FLASH_WB_CR_OPTLOCK (30) /* Option Lock */ +#define FLASH_WB_CR_LOCK (31) /* Lock */ -#define FLASH_H7_REGS_ADDR ((uint32_t)0x52002000) -#define FLASH_H7_KEYR1 (FLASH_H7_REGS_ADDR + 0x04) -#define FLASH_H7_KEYR2 (FLASH_H7_REGS_ADDR + 0x104) -#define FLASH_H7_OPT_KEYR (FLASH_H7_REGS_ADDR + 0x08) -#define FLASH_H7_OPT_KEYR2 (FLASH_H7_REGS_ADDR + 0x108) -#define FLASH_H7_CR1 (FLASH_H7_REGS_ADDR + 0x0c) -#define FLASH_H7_CR2 (FLASH_H7_REGS_ADDR + 0x10c) -#define FLASH_H7_SR1 (FLASH_H7_REGS_ADDR + 0x10) -#define FLASH_H7_SR2 (FLASH_H7_REGS_ADDR + 0x110) -#define FLASH_H7_CCR1 (FLASH_H7_REGS_ADDR + 0x14) -#define FLASH_H7_CCR2 (FLASH_H7_REGS_ADDR + 0x114) -#define FLASH_H7_OPTCR (FLASH_H7_REGS_ADDR + 0x18) -#define FLASH_H7_OPTCR2 (FLASH_H7_REGS_ADDR + 0x118) -#define FLASH_H7_OPTSR_CUR (FLASH_H7_REGS_ADDR + 0x1c) -#define FLASH_H7_OPTCCR (FLASH_H7_REGS_ADDR + 0x24) +// WB Flash status register +#define FLASH_WB_SR_ERROR_MASK (0x3f8) /* SR [9:3] */ +#define FLASH_WB_SR_PROGERR (3) /* Programming alignment error */ +#define FLASH_WB_SR_WRPERR (4) /* Write protection error */ +#define FLASH_WB_SR_PGAERR (5) /* Programming error */ +#define FLASH_WB_SR_BSY (16) /* Busy */ #endif // STM32FLASH_H_ diff --git a/src/stlink-lib/common.c b/src/stlink-lib/common.c index f2d60ce45..8e4b9a716 100644 --- a/src/stlink-lib/common.c +++ b/src/stlink-lib/common.c @@ -348,7 +348,8 @@ int stlink_reset(stlink_t *sl, enum reset_type type) { if (type == RESET_AUTO) { /* Check if the S_RESET_ST bit is set in DHCSR * This means that a reset has occurred - * DDI0337E, p. 10-4, Debug Halting Control and Status Register */ + * DDI0337E, p. 10-4, Debug Halting Control and Status Register + */ dhcsr = 0; int res = stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); diff --git a/src/stlink-lib/common_flash.c b/src/stlink-lib/common_flash.c index dc33fdfcb..a74d88b16 100644 --- a/src/stlink-lib/common_flash.c +++ b/src/stlink-lib/common_flash.c @@ -1154,7 +1154,7 @@ int stlink_erase_flash_section(stlink_t *sl, stm32_addr_t base_addr, size_t size // Check if size is aligned with a page, unless we want to completely erase the last page if ((addr + page_size) > (base_addr + size) && !align_size) { ELOG("Invalid size (not aligned with a page). Page size at address %#x is %#lx\n", addr, page_size); - return -1; + return (-1); } if (stlink_erase_flash_page(sl, addr)) { diff --git a/src/stlink-lib/flash_loader.c b/src/stlink-lib/flash_loader.c index f0ce9be42..231a5d4d6 100644 --- a/src/stlink-lib/flash_loader.c +++ b/src/stlink-lib/flash_loader.c @@ -708,9 +708,9 @@ int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { } if (sl->chip_id != STM32_CHIPID_H7Ax) { // set parallelism - write_flash_cr_psiz(sl, 3 /*64it*/, BANK_1); + write_flash_cr_psiz(sl, 3 /* 64bit */, BANK_1); if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { - write_flash_cr_psiz(sl, 3 /*64bit*/, BANK_2); + write_flash_cr_psiz(sl, 3 /* 64bit */, BANK_2); } } } else { From b1c4de647c9cbea8483e742262a30f1b308e881f Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Wed, 3 May 2023 14:02:26 +0200 Subject: [PATCH 441/503] Naming convention for header includes --- inc/backend.h | 6 +++--- inc/stlink.h | 6 +++--- inc/stm32.h | 6 +++--- inc/stm32flash.h | 6 +++--- inc/version.h.in | 6 +++--- src/st-flash/flash.h | 6 +++--- src/st-util/gdb-remote.h | 6 +++--- src/st-util/gdb-server.h | 6 +++--- src/st-util/semihosting.h | 6 +++--- src/stlink-gui/gui.h | 6 +++--- src/stlink-lib/calculate.h | 6 +++--- src/stlink-lib/chipid.h | 6 +++--- src/stlink-lib/commands.h | 6 +++--- src/stlink-lib/common.h | 6 +++--- src/stlink-lib/common_flash.h | 6 +++--- src/stlink-lib/flash_loader.h | 6 +++--- src/stlink-lib/helper.h | 6 +++--- src/stlink-lib/libusb_settings.h | 6 +++--- src/stlink-lib/logging.h | 6 +++--- src/stlink-lib/map_file.h | 6 +++--- src/stlink-lib/md5.h | 6 +++--- src/stlink-lib/option_bytes.h | 6 +++--- src/stlink-lib/reg.h | 6 +++--- src/stlink-lib/sg.h | 6 +++--- src/stlink-lib/usb.h | 6 +++--- src/win32/getopt/getopt.h | 6 +++--- src/win32/mmap.h | 6 +++--- src/win32/sys_time.h | 6 +++--- src/win32/unistd/unistd.h | 6 +++--- 29 files changed, 87 insertions(+), 87 deletions(-) diff --git a/inc/backend.h b/inc/backend.h index abbf4bbf0..75c569fcf 100644 --- a/inc/backend.h +++ b/inc/backend.h @@ -1,5 +1,5 @@ -#ifndef BACKEND_H_ -#define BACKEND_H_ +#ifndef BACKEND_H +#define BACKEND_H typedef struct _stlink_backend { void (*close) (stlink_t * sl); @@ -34,4 +34,4 @@ int (*trace_read) (stlink_t * sl, uint8_t* buf, size_t size); } stlink_backend_t; -#endif // BACKEND_H_ +#endif // BACKEND_H diff --git a/inc/stlink.h b/inc/stlink.h index 2a192876f..b9379e03d 100644 --- a/inc/stlink.h +++ b/inc/stlink.h @@ -6,8 +6,8 @@ * regardless of how the backend does the work.... */ -#ifndef STLINK_H_ -#define STLINK_H_ +#ifndef STLINK_H +#define STLINK_H #include #include @@ -311,4 +311,4 @@ int stlink_target_connect(stlink_t *sl, enum connect_type connect); } #endif -#endif // STLINK_H_ +#endif // STLINK_H diff --git a/inc/stm32.h b/inc/stm32.h index ab80ff25e..f91269a34 100644 --- a/inc/stm32.h +++ b/inc/stm32.h @@ -4,8 +4,8 @@ * STM32-specific defines & identification parametres */ -#ifndef STM32_H_ -#define STM32_H_ +#ifndef STM32_H +#define STM32_H /* STM32 Cortex-M core ids (CPUTAPID) */ enum stm32_core_id { @@ -217,4 +217,4 @@ enum stm32_chipids { #define STM32L5_PWR_CR1 0x40007000 // RM0438, p. 93,324 #define STM32L5_PWR_CR1_VOS 9 -#endif // STM32_H_ +#endif // STM32_H diff --git a/inc/stm32flash.h b/inc/stm32flash.h index 12d2f5a7b..5cb0ee1df 100644 --- a/inc/stm32flash.h +++ b/inc/stm32flash.h @@ -1,5 +1,5 @@ -#ifndef STM32FLASH_H_ -#define STM32FLASH_H_ +#ifndef STM32FLASH_H +#define STM32FLASH_H /* STM32Fx FPEC flash controller interface, PM0063 manual */ // STM32F05x is identical, based on RM0091 (DM00031936, Doc ID 018940 Rev.2, Aug 2012) @@ -408,4 +408,4 @@ #define FLASH_WB_SR_PGAERR (5) /* Programming error */ #define FLASH_WB_SR_BSY (16) /* Busy */ -#endif // STM32FLASH_H_ +#endif // STM32FLASH_H diff --git a/inc/version.h.in b/inc/version.h.in index b5ccd6e31..39020c0ba 100644 --- a/inc/version.h.in +++ b/inc/version.h.in @@ -1,9 +1,9 @@ -#ifndef VERSION_H_ -#define VERSION_H_ +#ifndef VERSION_H +#define VERSION_H #define STLINK_VERSION "@PROJECT_VERSION@" #define STLINK_VERSION_MAJOR @PROJECT_VERSION_MAJOR@ #define STLINK_VERSION_MINOR @PROJECT_VERSION_MINOR@ #define STLINK_VERSION_PATCH @PROJECT_VERSION_PATCH@ -#endif // VERSION_H_ +#endif // VERSION_H diff --git a/src/st-flash/flash.h b/src/st-flash/flash.h index aab57878f..4aa6033f8 100644 --- a/src/st-flash/flash.h +++ b/src/st-flash/flash.h @@ -1,5 +1,5 @@ -#ifndef FLASH_H_ -#define FLASH_H_ +#ifndef FLASH_H +#define FLASH_H #include @@ -33,4 +33,4 @@ struct flash_opts { int flash_get_opts(struct flash_opts* o, int ac, char** av); -#endif // FLASH_H_ +#endif // FLASH_H diff --git a/src/st-util/gdb-remote.h b/src/st-util/gdb-remote.h index bcf1dbd01..03d6aea10 100644 --- a/src/st-util/gdb-remote.h +++ b/src/st-util/gdb-remote.h @@ -1,8 +1,8 @@ -#ifndef GDB_REMOTE_H_ -#define GDB_REMOTE_H_ +#ifndef GDB_REMOTE_H +#define GDB_REMOTE_H int gdb_send_packet(int fd, char* data); int gdb_recv_packet(int fd, char** buffer); int gdb_check_for_interrupt(int fd); -#endif // GDB_REMOTE_H_ +#endif // GDB_REMOTE_H diff --git a/src/st-util/gdb-server.h b/src/st-util/gdb-server.h index 3fbb16dad..03c37e416 100644 --- a/src/st-util/gdb-server.h +++ b/src/st-util/gdb-server.h @@ -1,5 +1,5 @@ -#ifndef GDB_SERVER_H_ -#define GDB_SERVER_H_ +#ifndef GDB_SERVER_H +#define GDB_SERVER_H #define STRINGIFY_inner(name) #name #define STRINGIFY(name) STRINGIFY_inner(name) @@ -8,4 +8,4 @@ #define DEBUG_LOGGING_LEVEL 100 #define DEFAULT_GDB_LISTEN_PORT 4242 -#endif // GDB_SERVER_H_ +#endif // GDB_SERVER_H diff --git a/src/st-util/semihosting.h b/src/st-util/semihosting.h index 2e34b4307..e7ddfcd97 100644 --- a/src/st-util/semihosting.h +++ b/src/st-util/semihosting.h @@ -1,5 +1,5 @@ -#ifndef SEMIHOSTING_H_ -#define SEMIHOSTING_H_ +#ifndef SEMIHOSTING_H +#define SEMIHOSTING_H #include @@ -31,4 +31,4 @@ int do_semihosting(stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret); -#endif // SEMIHOSTING_H_ +#endif // SEMIHOSTING_H diff --git a/src/stlink-gui/gui.h b/src/stlink-gui/gui.h index f29ee5031..08519ea56 100644 --- a/src/stlink-gui/gui.h +++ b/src/stlink-gui/gui.h @@ -1,5 +1,5 @@ -#ifndef GUI_H_ -#define GUI_H_ +#ifndef GUI_H +#define GUI_H #include @@ -89,4 +89,4 @@ struct _STlinkGUIClass { GType stlink_gui_get_type(void); int export_to_file(const char*filename, const struct mem_t flash_mem); -#endif // GUI_H_ +#endif // GUI_H diff --git a/src/stlink-lib/calculate.h b/src/stlink-lib/calculate.h index beb064297..64dfb51b2 100644 --- a/src/stlink-lib/calculate.h +++ b/src/stlink-lib/calculate.h @@ -4,12 +4,12 @@ * Calculation of sector numbers and pages */ -#ifndef CALCULATE_H_ -#define CALCULATE_H_ +#ifndef CALCULATE_H +#define CALCULATE_H uint32_t calculate_F4_sectornum(uint32_t); uint32_t calculate_F7_sectornum(uint32_t); uint32_t calculate_H7_sectornum(stlink_t *, uint32_t, unsigned); uint32_t calculate_L4_page(stlink_t *, uint32_t); -#endif // CALCULATE_H_ +#endif // CALCULATE_H diff --git a/src/stlink-lib/chipid.h b/src/stlink-lib/chipid.h index b93a3f2d6..d6afc4525 100644 --- a/src/stlink-lib/chipid.h +++ b/src/stlink-lib/chipid.h @@ -1,5 +1,5 @@ -#ifndef CHIPID_H_ -#define CHIPID_H_ +#ifndef CHIPID_H +#define CHIPID_H #include #include @@ -24,4 +24,4 @@ struct stlink_chipid_params { struct stlink_chipid_params *stlink_chipid_get_params(uint32_t chipid); void init_chipids(char *dir_to_scan); -#endif // CHIPID_H_ +#endif // CHIPID_H diff --git a/src/stlink-lib/commands.h b/src/stlink-lib/commands.h index 4fa919858..5f0904971 100644 --- a/src/stlink-lib/commands.h +++ b/src/stlink-lib/commands.h @@ -1,5 +1,5 @@ -#ifndef COMMANDS_H_ -#define COMMANDS_H_ +#ifndef COMMANDS_H +#define COMMANDS_H enum stlink_commands { STLINK_GET_VERSION = 0xF1, @@ -54,4 +54,4 @@ enum stlink_dfu_commands { STLINK_DFU_EXIT = 0x07 }; -#endif // COMMANDS_H_ +#endif // COMMANDS_H diff --git a/src/stlink-lib/common.h b/src/stlink-lib/common.h index 902493610..dd6cf95b2 100644 --- a/src/stlink-lib/common.h +++ b/src/stlink-lib/common.h @@ -4,12 +4,12 @@ * General helper functions */ -#ifndef COMMON_H_ -#define COMMON_H_ +#ifndef COMMON_H +#define COMMON_H int check_file(stlink_t *, mapped_file_t *, stm32_addr_t); void md5_calculate(mapped_file_t *); void stlink_checksum(mapped_file_t *); void stlink_fwrite_finalize(stlink_t *, stm32_addr_t); -#endif // COMMON_H_ +#endif // COMMON_H diff --git a/src/stlink-lib/common_flash.h b/src/stlink-lib/common_flash.h index 269f8196e..aa92b2143 100644 --- a/src/stlink-lib/common_flash.h +++ b/src/stlink-lib/common_flash.h @@ -4,8 +4,8 @@ * Flash operations */ -#ifndef COMMON_FLASH_H_ -#define COMMON_FLASH_H_ +#ifndef COMMON_FLASH_H +#define COMMON_FLASH_H void lock_flash(stlink_t *); void clear_flash_error(stlink_t *); @@ -25,4 +25,4 @@ void clear_flash_cr_pg(stlink_t *, unsigned); uint32_t read_flash_cr(stlink_t *, unsigned); uint32_t get_stm32l0_flash_base(stlink_t *); -#endif // COMMON_FLASH_H_ +#endif // COMMON_FLASH_H diff --git a/src/stlink-lib/flash_loader.h b/src/stlink-lib/flash_loader.h index 781fab74a..51448395f 100644 --- a/src/stlink-lib/flash_loader.h +++ b/src/stlink-lib/flash_loader.h @@ -4,8 +4,8 @@ * Flash loader */ -#ifndef FLASH_LOADER_H_ -#define FLASH_LOADER_H_ +#ifndef FLASH_LOADER_H +#define FLASH_LOADER_H #include #include @@ -21,4 +21,4 @@ int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl); int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t addr, uint8_t* base, uint32_t len); int stlink_flashloader_stop(stlink_t *sl, flash_loader_t *fl); -#endif // FLASH_LOADER_H_ +#endif // FLASH_LOADER_H diff --git a/src/stlink-lib/helper.h b/src/stlink-lib/helper.h index 58023aff2..cf45bbf43 100644 --- a/src/stlink-lib/helper.h +++ b/src/stlink-lib/helper.h @@ -1,8 +1,8 @@ -#ifndef HELPER_H_ -#define HELPER_H_ +#ifndef HELPER_H +#define HELPER_H unsigned time_ms(); int arg_parse_freq(const char *str); -#endif // HELPER_H_ +#endif // HELPER_H diff --git a/src/stlink-lib/libusb_settings.h b/src/stlink-lib/libusb_settings.h index 639f9e4a4..3777f720b 100644 --- a/src/stlink-lib/libusb_settings.h +++ b/src/stlink-lib/libusb_settings.h @@ -1,5 +1,5 @@ -#ifndef LIBUSB_SETTINGS_H_ -#define LIBUSB_SETTINGS_H_ +#ifndef LIBUSB_SETTINGS_H +#define LIBUSB_SETTINGS_H #include @@ -44,4 +44,4 @@ #error unsupported libusb version #endif -#endif // LIBUSB_SETTINGS_H_ +#endif // LIBUSB_SETTINGS_H diff --git a/src/stlink-lib/logging.h b/src/stlink-lib/logging.h index 7510d573e..893a02c24 100644 --- a/src/stlink-lib/logging.h +++ b/src/stlink-lib/logging.h @@ -2,8 +2,8 @@ * Ugly, low performance, configurable level, logging "framework" */ -#ifndef LOGGING_H_ -#define LOGGING_H_ +#ifndef LOGGING_H +#define LOGGING_H #ifdef __cplusplus extern "C" { @@ -45,4 +45,4 @@ int ugly_libusb_log_level(enum ugly_loglevel v); } #endif -#endif // LOGGING_H_ +#endif // LOGGING_H diff --git a/src/stlink-lib/map_file.h b/src/stlink-lib/map_file.h index d69f6c3b5..f50a201f0 100644 --- a/src/stlink-lib/map_file.h +++ b/src/stlink-lib/map_file.h @@ -4,8 +4,8 @@ * File mapping */ -#ifndef MAP_FILE_H_ -#define MAP_FILE_H_ +#ifndef MAP_FILE_H +#define MAP_FILE_H #ifndef O_BINARY #define O_BINARY 0 @@ -29,4 +29,4 @@ typedef struct mapped_file { int map_file(mapped_file_t *, const char *); void unmap_file(mapped_file_t *); -#endif // MAP_FILE_H_ +#endif // MAP_FILE_H diff --git a/src/stlink-lib/md5.h b/src/stlink-lib/md5.h index 7b853a4f6..23c5d971b 100644 --- a/src/stlink-lib/md5.h +++ b/src/stlink-lib/md5.h @@ -11,8 +11,8 @@ * MD5 hash function */ -#ifndef MD5_H_ -#define MD5_H_ +#ifndef MD5_H +#define MD5_H #pragma once @@ -71,4 +71,4 @@ void Md5Finalise(Md5Context* Context /* [in out] */, MD5_HASH* Digest /* [in] */ */ void Md5Calculate(void const* Buffer /* [in] */, uint32_t BufferSize /* [in] */, MD5_HASH* Digest /* [in] */); -#endif // MD5_H_ \ No newline at end of file +#endif // MD5_H \ No newline at end of file diff --git a/src/stlink-lib/option_bytes.h b/src/stlink-lib/option_bytes.h index 481a69f0a..9c81fba8a 100644 --- a/src/stlink-lib/option_bytes.h +++ b/src/stlink-lib/option_bytes.h @@ -4,8 +4,8 @@ * Read and write option bytes and option control registers */ -#ifndef OPTION_BYTES_H_ -#define OPTION_BYTES_H_ +#ifndef OPTION_BYTES_H +#define OPTION_BYTES_H #include #include @@ -23,4 +23,4 @@ int stlink_write_option_control_register1_32(stlink_t *sl, uint32_t option_cr1); int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t len); int stlink_fwrite_option_bytes(stlink_t *sl, const char* path, stm32_addr_t addr); -#endif // OPTION_BYTES_H_ \ No newline at end of file +#endif // OPTION_BYTES_H \ No newline at end of file diff --git a/src/stlink-lib/reg.h b/src/stlink-lib/reg.h index 2046f8a6a..c2976d050 100644 --- a/src/stlink-lib/reg.h +++ b/src/stlink-lib/reg.h @@ -1,5 +1,5 @@ -#ifndef REG_H_ -#define REG_H_ +#ifndef REG_H +#define REG_H #define STLINK_REG_CM3_CPUID 0xE000ED00 @@ -123,4 +123,4 @@ #define STLINK_REG_CM7_ICIALLU 0xE000EF50 #define STLINK_REG_CM7_CCSIDR 0xE000ED80 -#endif // REG_H_ +#endif // REG_H diff --git a/src/stlink-lib/sg.h b/src/stlink-lib/sg.h index e30043fcc..5ba809f59 100644 --- a/src/stlink-lib/sg.h +++ b/src/stlink-lib/sg.h @@ -3,8 +3,8 @@ * Author: karl */ -#ifndef SG_H_ -#define SG_H_ +#ifndef SG_H +#define SG_H #include #include @@ -56,4 +56,4 @@ struct stlink_libsg { stlink_t* stlink_v1_open(const int verbose, int reset); -#endif // SG_H_ +#endif // SG_H diff --git a/src/stlink-lib/usb.h b/src/stlink-lib/usb.h index ff6f9088e..8c98bcaf4 100644 --- a/src/stlink-lib/usb.h +++ b/src/stlink-lib/usb.h @@ -3,8 +3,8 @@ * Author: karl */ -#ifndef USB_H_ -#define USB_H_ +#ifndef USB_H +#define USB_H #include @@ -70,4 +70,4 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, enum connect_type connect, size_t stlink_probe_usb(stlink_t **stdevs[], enum connect_type connect, int freq); void stlink_probe_usb_free(stlink_t **stdevs[], size_t size); -#endif // USB_H_ +#endif // USB_H diff --git a/src/win32/getopt/getopt.h b/src/win32/getopt/getopt.h index 2a1bd735b..b1dd35ef1 100644 --- a/src/win32/getopt/getopt.h +++ b/src/win32/getopt/getopt.h @@ -1,5 +1,5 @@ -#ifndef GETOPT_H_ -#define GETOPT_H_ +#ifndef GETOPT_H +#define GETOPT_H #if defined(__cplusplus) extern "C" { @@ -38,4 +38,4 @@ int getopt_long(int argc, } #endif -#endif // GETOPT_H_ +#endif // GETOPT_H diff --git a/src/win32/mmap.h b/src/win32/mmap.h index ff01f4286..c6390aede 100644 --- a/src/win32/mmap.h +++ b/src/win32/mmap.h @@ -1,5 +1,5 @@ -#ifndef MMAP_H_ -#define MMAP_H_ +#ifndef MMAP_H +#define MMAP_H #ifdef STLINK_HAVE_SYS_MMAN_H #include @@ -18,4 +18,4 @@ int munmap(void *addr, size_t len); #endif // STLINK_HAVE_SYS_MMAN_H -#endif // MMAP_H_ +#endif // MMAP_H diff --git a/src/win32/sys_time.h b/src/win32/sys_time.h index cb767fc31..98ecaddfc 100644 --- a/src/win32/sys_time.h +++ b/src/win32/sys_time.h @@ -1,5 +1,5 @@ -#ifndef SYS_TIME_H_ -#define SYS_TIME_H_ +#ifndef SYS_TIME_H +#define SYS_TIME_H #ifdef STLINK_HAVE_SYS_TIME_H @@ -18,4 +18,4 @@ int gettimeofday(struct timeval *tv, struct timezone *tz); #endif // STLINK_HAVE_SYS_TIME_H -#endif // SYS_TIME_H_ +#endif // SYS_TIME_H diff --git a/src/win32/unistd/unistd.h b/src/win32/unistd/unistd.h index b8a3db746..5f2b5433b 100644 --- a/src/win32/unistd/unistd.h +++ b/src/win32/unistd/unistd.h @@ -1,5 +1,5 @@ -#ifndef UNISTD_H_ -#define UNISTD_H_ +#ifndef UNISTD_H +#define UNISTD_H /* * This file intended to serve as a drop-in replacement for unistd.h on Windows @@ -72,4 +72,4 @@ typedef unsigned __int64 uint64_t; int usleep(unsigned int waitTime); #endif -#endif // UNISTD_H_ +#endif // UNISTD_H From e4b2594b5a0700a43c68fcbe2aa0c91b5a62cec3 Mon Sep 17 00:00:00 2001 From: Andras Gemes Date: Fri, 5 May 2023 15:39:04 +0200 Subject: [PATCH 442/503] Fixed broken links --- README.md | 2 +- doc/tutorial.md | 2 +- doc/version_support.md | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/README.md b/README.md index 0e846b336..b6fca5fe2 100644 --- a/README.md +++ b/README.md @@ -49,7 +49,7 @@ The STlink toolset includes: ## Supported operating systems and hardware combinations -Currently known working MCU targets are listed in [devices_boards.md](doc/devices_boards.md). +Currently known working MCU targets are listed in [supported devices.md](). A list of supported operating can be found in [version_support.md](doc/version_support.md). diff --git a/doc/tutorial.md b/doc/tutorial.md index 7e87a7bd9..53ecabe7d 100644 --- a/doc/tutorial.md +++ b/doc/tutorial.md @@ -104,7 +104,7 @@ In this known example one finds the counterfeited "STM32F103C8T6" MCUs to identi In the following you find some hints on how to identify your chip and track down fraud: - [How to Detect STM32 Fakes](https://www.cnx-software.com/2020/03/22/how-to-detect-stm32-fakes/) -- [Confirmation by STMicroelectronics](https://www.mikrocontroller.net/attachment/442839/couterfeit_STM.png) (Marking: 991KA 93 MYS 807) +- [Confirmation by STMicroelectronics](https://www.mikrocontroller.net/attachment/442839/couterfeit_STM.PNG) (Marking: 991KA 93 MYS 807) - [STM32 Clones: The Good, The Bad And The Ugly](https://hackaday.com/2020/10/22/stm32-clones-the-good-the-bad-and-the-ugly/) However it appears that not all counterfeited parts cause problems during operation, but some are known to not even being able to execute a basic "blinky" example binary. Further there can be problems that may not even show up or affect you directly, but somewhen later in time (or maybe never). diff --git a/doc/version_support.md b/doc/version_support.md index 358e65fb9..022fb5e4d 100644 --- a/doc/version_support.md +++ b/doc/version_support.md @@ -1,4 +1,4 @@ -_Source:_ [pkgs.org](https://pkgs.org/search) - libusb, cmake, gtk, libgtk (as of Apr 2023) +_Source:_ [pkgs.org](https://pkgs.org) - libusb, cmake, gtk, libgtk (as of Apr 2023) ## Supported Operating Systems From 623570e3cc6e8b577c25dd8c23840ad688358f9c Mon Sep 17 00:00:00 2001 From: Andras Gemes Date: Sun, 7 May 2023 12:39:03 +0200 Subject: [PATCH 443/503] Renamed 'supported devices.md' to 'supported_devices.md' --- README.md | 2 +- doc/{supported devices.md => supported_devices.md} | 0 2 files changed, 1 insertion(+), 1 deletion(-) rename doc/{supported devices.md => supported_devices.md} (100%) diff --git a/README.md b/README.md index b6fca5fe2..e103ac301 100644 --- a/README.md +++ b/README.md @@ -49,7 +49,7 @@ The STlink toolset includes: ## Supported operating systems and hardware combinations -Currently known working MCU targets are listed in [supported devices.md](). +Currently known working MCU targets are listed in [supported_devices.md](doc/supported_devices.md). A list of supported operating can be found in [version_support.md](doc/version_support.md). diff --git a/doc/supported devices.md b/doc/supported_devices.md similarity index 100% rename from doc/supported devices.md rename to doc/supported_devices.md From 5e85fd063908f89499180c28fe5e9ba74868b272 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Mon, 8 May 2023 02:05:55 +0200 Subject: [PATCH 444/503] Replace data types with fixed width typedefs (C99) - Unified variable types (Closes #909) short --> int16_t unsigned short --> uint16_t int --> int32_t unsigned int --> uint32_t long --> int32_t unsigned long --> uint32_t long long --> int64_t unsigned long long --> uint64_t - Added missing header includes --- inc/backend.h | 58 ++++---- inc/stlink.h | 108 +++++++-------- inc/stm32.h | 2 + inc/stm32flash.h | 2 + src/st-flash/flash.c | 15 +- src/st-flash/flash.h | 10 +- src/st-flash/flash_opts.c | 15 +- src/st-info/info.c | 17 +-- src/st-trace/trace.c | 15 +- src/st-util/gdb-remote.c | 18 +-- src/st-util/gdb-remote.h | 8 +- src/st-util/gdb-server.c | 251 +++++++++++++++++----------------- src/st-util/semihosting.c | 57 ++++---- src/st-util/semihosting.h | 4 +- src/stlink-gui/gui.c | 8 +- src/stlink-gui/gui.h | 3 +- src/stlink-lib/calculate.c | 4 +- src/stlink-lib/calculate.h | 2 + src/stlink-lib/chipid.c | 11 +- src/stlink-lib/chipid.h | 2 + src/stlink-lib/common.c | 133 +++++++++--------- src/stlink-lib/common.h | 7 +- src/stlink-lib/common_flash.c | 108 ++++++++------- src/stlink-lib/common_flash.h | 10 +- src/stlink-lib/flash_loader.c | 67 ++++----- src/stlink-lib/flash_loader.h | 14 +- src/stlink-lib/helper.c | 13 +- src/stlink-lib/helper.h | 6 +- src/stlink-lib/logging.c | 9 +- src/stlink-lib/logging.h | 8 +- src/stlink-lib/map_file.c | 15 +- src/stlink-lib/map_file.h | 4 +- src/stlink-lib/md5.c | 3 +- src/stlink-lib/option_bytes.c | 116 ++++++++-------- src/stlink-lib/option_bytes.h | 22 +-- src/stlink-lib/read_write.c | 34 ++--- src/stlink-lib/sg.c | 126 ++++++++--------- src/stlink-lib/sg.h | 16 ++- src/stlink-lib/usb.c | 238 ++++++++++++++++---------------- src/stlink-lib/usb.h | 19 +-- src/win32/getopt/getopt.c | 23 ++-- src/win32/getopt/getopt.h | 18 +-- src/win32/mmap.c | 9 +- src/win32/mmap.h | 6 +- src/win32/sys_time.c | 10 +- src/win32/sys_time.h | 8 +- src/win32/unistd/unistd.h | 5 +- src/win32/win32_socket.c | 40 +++--- src/win32/win32_socket.h | 24 ++-- tests/flash.c | 9 +- tests/sg.c | 7 +- tests/usb.c | 7 +- 52 files changed, 908 insertions(+), 836 deletions(-) diff --git a/inc/backend.h b/inc/backend.h index 75c569fcf..a9a7d6e03 100644 --- a/inc/backend.h +++ b/inc/backend.h @@ -1,37 +1,39 @@ #ifndef BACKEND_H #define BACKEND_H +#include + typedef struct _stlink_backend { void (*close) (stlink_t * sl); - int (*exit_debug_mode) (stlink_t * sl); - int (*enter_swd_mode) (stlink_t * sl); - int (*enter_jtag_mode) (stlink_t * stl); - int (*exit_dfu_mode) (stlink_t * stl); - int (*core_id) (stlink_t * stl); - int (*reset) (stlink_t * stl); - int (*jtag_reset) (stlink_t * stl, int value); - int (*run) (stlink_t * stl, enum run_type type); - int (*status) (stlink_t * stl); - int (*version) (stlink_t *sl); - int (*read_debug32) (stlink_t *sl, uint32_t addr, uint32_t *data); - int (*read_mem32) (stlink_t *sl, uint32_t addr, uint16_t len); - int (*write_debug32) (stlink_t *sl, uint32_t addr, uint32_t data); - int (*write_mem32) (stlink_t *sl, uint32_t addr, uint16_t len); - int (*write_mem8) (stlink_t *sl, uint32_t addr, uint16_t len); - int (*read_all_regs) (stlink_t *sl, struct stlink_reg * regp); - int (*read_reg) (stlink_t *sl, int r_idx, struct stlink_reg * regp); - int (*read_all_unsupported_regs) (stlink_t *sl, struct stlink_reg *regp); - int (*read_unsupported_reg) (stlink_t *sl, int r_idx, struct stlink_reg *regp); - int (*write_unsupported_reg) (stlink_t *sl, uint32_t value, int idx, struct stlink_reg *regp); - int (*write_reg) (stlink_t *sl, uint32_t reg, int idx); - int (*step) (stlink_t * stl); - int (*current_mode) (stlink_t * stl); - int (*force_debug) (stlink_t *sl); + int32_t (*exit_debug_mode) (stlink_t * sl); + int32_t (*enter_swd_mode) (stlink_t * sl); + int32_t (*enter_jtag_mode) (stlink_t * stl); + int32_t (*exit_dfu_mode) (stlink_t * stl); + int32_t (*core_id) (stlink_t * stl); + int32_t (*reset) (stlink_t * stl); + int32_t (*jtag_reset) (stlink_t * stl, int32_t value); + int32_t (*run) (stlink_t * stl, enum run_type type); + int32_t (*status) (stlink_t * stl); + int32_t (*version) (stlink_t *sl); + int32_t (*read_debug32) (stlink_t *sl, uint32_t addr, uint32_t *data); + int32_t (*read_mem32) (stlink_t *sl, uint32_t addr, uint16_t len); + int32_t (*write_debug32) (stlink_t *sl, uint32_t addr, uint32_t data); + int32_t (*write_mem32) (stlink_t *sl, uint32_t addr, uint16_t len); + int32_t (*write_mem8) (stlink_t *sl, uint32_t addr, uint16_t len); + int32_t (*read_all_regs) (stlink_t *sl, struct stlink_reg * regp); + int32_t (*read_reg) (stlink_t *sl, int32_t r_idx, struct stlink_reg * regp); + int32_t (*read_all_unsupported_regs) (stlink_t *sl, struct stlink_reg *regp); + int32_t (*read_unsupported_reg) (stlink_t *sl, int32_t r_idx, struct stlink_reg *regp); + int32_t (*write_unsupported_reg) (stlink_t *sl, uint32_t value, int32_t idx, struct stlink_reg *regp); + int32_t (*write_reg) (stlink_t *sl, uint32_t reg, int32_t idx); + int32_t (*step) (stlink_t * stl); + int32_t (*current_mode) (stlink_t * stl); + int32_t (*force_debug) (stlink_t *sl); int32_t (*target_voltage) (stlink_t *sl); - int (*set_swdclk) (stlink_t * stl, int freq_khz); - int (*trace_enable) (stlink_t * sl, uint32_t frequency); - int (*trace_disable) (stlink_t * sl); - int (*trace_read) (stlink_t * sl, uint8_t* buf, size_t size); + int32_t (*set_swdclk) (stlink_t * stl, int32_t freq_khz); + int32_t (*trace_enable) (stlink_t * sl, uint32_t frequency); + int32_t (*trace_disable) (stlink_t * sl); + int32_t (*trace_read) (stlink_t * sl, uint8_t* buf, size_t size); } stlink_backend_t; #endif // BACKEND_H diff --git a/inc/stlink.h b/inc/stlink.h index b9379e03d..ca07a6a89 100644 --- a/inc/stlink.h +++ b/inc/stlink.h @@ -196,17 +196,17 @@ struct _stlink { unsigned char c_buf[C_BUF_LEN]; // data transferred from or to device unsigned char q_buf[Q_BUF_LEN]; - int q_len; + int32_t q_len; // transport layer verboseness: 0 for no debug info, 10 for lots - int verbose; - int opt; + int32_t verbose; + int32_t opt; uint32_t core_id; // set by stlink_core_id(), result from STLINK_DEBUGREADCOREID uint32_t chip_id; // set by stlink_load_device_params(), used to identify flash and sram enum target_state core_stat; // set by stlink_status() char serial[STLINK_SERIAL_BUFFER_SIZE]; - int freq; // set by stlink_open_usb(), values: STLINK_SWDCLK_xxx_DIVISOR + int32_t freq; // set by stlink_open_usb(), values: STLINK_SWDCLK_xxx_DIVISOR enum stm32_flash_type flash_type; // stlink_chipid_params.flash_type, set by stlink_load_device_params(), values: STM32_FLASH_TYPE_xx @@ -236,67 +236,67 @@ struct _stlink { uint32_t max_trace_freq; // set by stlink_open_usb() }; -int stlink_enter_swd_mode(stlink_t *sl); -int stlink_enter_jtag_mode(stlink_t *sl); -int stlink_exit_debug_mode(stlink_t *sl); -int stlink_exit_dfu_mode(stlink_t *sl); +int32_t stlink_enter_swd_mode(stlink_t *sl); +int32_t stlink_enter_jtag_mode(stlink_t *sl); +int32_t stlink_exit_debug_mode(stlink_t *sl); +int32_t stlink_exit_dfu_mode(stlink_t *sl); void stlink_close(stlink_t *sl); -int stlink_core_id(stlink_t *sl); -int stlink_reset(stlink_t *sl, enum reset_type type); -int stlink_run(stlink_t *sl, enum run_type type); -int stlink_status(stlink_t *sl); -int stlink_version(stlink_t *sl); -int stlink_read_debug32(stlink_t *sl, uint32_t addr, uint32_t *data); -int stlink_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len); -int stlink_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data); -int stlink_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len); -int stlink_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len); -int stlink_read_all_regs(stlink_t *sl, struct stlink_reg *regp); -int stlink_read_all_unsupported_regs(stlink_t *sl, struct stlink_reg *regp); -int stlink_read_reg(stlink_t *sl, int r_idx, struct stlink_reg *regp); -int stlink_read_unsupported_reg(stlink_t *sl, int r_idx, struct stlink_reg *regp); -int stlink_write_unsupported_reg(stlink_t *sl, uint32_t value, int r_idx, struct stlink_reg *regp); -int stlink_write_reg(stlink_t *sl, uint32_t reg, int idx); -int stlink_step(stlink_t *sl); -int stlink_current_mode(stlink_t *sl); -int stlink_force_debug(stlink_t *sl); -int stlink_target_voltage(stlink_t *sl); -int stlink_set_swdclk(stlink_t *sl, int freq_khz); -int stlink_trace_enable(stlink_t* sl, uint32_t frequency); -int stlink_trace_disable(stlink_t* sl); -int stlink_trace_read(stlink_t* sl, uint8_t* buf, size_t size); -int stlink_erase_flash_mass(stlink_t* sl); -int stlink_erase_flash_section(stlink_t *sl, stm32_addr_t base_addr, size_t size, bool align_size); -int stlink_write_flash(stlink_t* sl, stm32_addr_t address, uint8_t* data, uint32_t length, uint8_t eraseonly); -int stlink_parse_ihex(const char* path, uint8_t erased_pattern, uint8_t * * mem, size_t * size, uint32_t * begin); +int32_t stlink_core_id(stlink_t *sl); +int32_t stlink_reset(stlink_t *sl, enum reset_type type); +int32_t stlink_run(stlink_t *sl, enum run_type type); +int32_t stlink_status(stlink_t *sl); +int32_t stlink_version(stlink_t *sl); +int32_t stlink_read_debug32(stlink_t *sl, uint32_t addr, uint32_t *data); +int32_t stlink_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len); +int32_t stlink_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data); +int32_t stlink_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len); +int32_t stlink_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len); +int32_t stlink_read_all_regs(stlink_t *sl, struct stlink_reg *regp); +int32_t stlink_read_all_unsupported_regs(stlink_t *sl, struct stlink_reg *regp); +int32_t stlink_read_reg(stlink_t *sl, int32_t r_idx, struct stlink_reg *regp); +int32_t stlink_read_unsupported_reg(stlink_t *sl, int32_t r_idx, struct stlink_reg *regp); +int32_t stlink_write_unsupported_reg(stlink_t *sl, uint32_t value, int32_t r_idx, struct stlink_reg *regp); +int32_t stlink_write_reg(stlink_t *sl, uint32_t reg, int32_t idx); +int32_t stlink_step(stlink_t *sl); +int32_t stlink_current_mode(stlink_t *sl); +int32_t stlink_force_debug(stlink_t *sl); +int32_t stlink_target_voltage(stlink_t *sl); +int32_t stlink_set_swdclk(stlink_t *sl, int32_t freq_khz); +int32_t stlink_trace_enable(stlink_t* sl, uint32_t frequency); +int32_t stlink_trace_disable(stlink_t* sl); +int32_t stlink_trace_read(stlink_t* sl, uint8_t* buf, size_t size); +int32_t stlink_erase_flash_mass(stlink_t* sl); +int32_t stlink_erase_flash_section(stlink_t *sl, stm32_addr_t base_addr, size_t size, bool align_size); +int32_t stlink_write_flash(stlink_t* sl, stm32_addr_t address, uint8_t* data, uint32_t length, uint8_t eraseonly); +int32_t stlink_parse_ihex(const char* path, uint8_t erased_pattern, uint8_t * * mem, size_t * size, uint32_t * begin); uint8_t stlink_get_erased_pattern(stlink_t *sl); -int stlink_mwrite_flash(stlink_t *sl, uint8_t* data, uint32_t length, stm32_addr_t addr); -int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr); -int stlink_mwrite_sram(stlink_t *sl, uint8_t* data, uint32_t length, stm32_addr_t addr); -int stlink_fwrite_sram(stlink_t *sl, const char* path, stm32_addr_t addr); -int stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, uint32_t length); +int32_t stlink_mwrite_flash(stlink_t *sl, uint8_t* data, uint32_t length, stm32_addr_t addr); +int32_t stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr); +int32_t stlink_mwrite_sram(stlink_t *sl, uint8_t* data, uint32_t length, stm32_addr_t addr); +int32_t stlink_fwrite_sram(stlink_t *sl, const char* path, stm32_addr_t addr); +int32_t stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, uint32_t length); -//int stlink_chip_id(stlink_t *sl, uint32_t *chip_id); -int stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid); +//int32_t stlink_chip_id(stlink_t *sl, uint32_t *chip_id); +int32_t stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid); -int stlink_erase_flash_page(stlink_t* sl, stm32_addr_t flashaddr); +int32_t stlink_erase_flash_page(stlink_t* sl, stm32_addr_t flashaddr); uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr); -int stlink_check_address_range_validity(stlink_t *sl, stm32_addr_t addr, size_t size); -int stlink_check_address_alignment(stlink_t *sl, stm32_addr_t addr); -uint16_t read_uint16(const unsigned char *c, const int pt); +int32_t stlink_check_address_range_validity(stlink_t *sl, stm32_addr_t addr, size_t size); +int32_t stlink_check_address_alignment(stlink_t *sl, stm32_addr_t addr); +uint16_t read_uint16(const unsigned char *c, const int32_t pt); //void stlink_core_stat(stlink_t *sl); void stlink_print_data(stlink_t *sl); -unsigned int is_bigendian(void); -uint32_t read_uint32(const unsigned char *c, const int pt); +uint32_t is_bigendian(void); +uint32_t read_uint32(const unsigned char *c, const int32_t pt); void write_uint32(unsigned char* buf, uint32_t ui); void write_uint16(unsigned char* buf, uint16_t ui); bool stlink_is_core_halted(stlink_t *sl); -int write_buffer_to_sram(stlink_t *sl, flash_loader_t* fl, const uint8_t* buf, size_t size); -int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size); -int stlink_fread(stlink_t* sl, const char* path, bool is_ihex, stm32_addr_t addr, size_t size); -int stlink_load_device_params(stlink_t *sl); +int32_t write_buffer_to_sram(stlink_t *sl, flash_loader_t* fl, const uint8_t* buf, size_t size); +int32_t write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size); +int32_t stlink_fread(stlink_t* sl, const char* path, bool is_ihex, stm32_addr_t addr, size_t size); +int32_t stlink_load_device_params(stlink_t *sl); -int stlink_target_connect(stlink_t *sl, enum connect_type connect); +int32_t stlink_target_connect(stlink_t *sl, enum connect_type connect); #include #include diff --git a/inc/stm32.h b/inc/stm32.h index f91269a34..eee1b0433 100644 --- a/inc/stm32.h +++ b/inc/stm32.h @@ -7,6 +7,8 @@ #ifndef STM32_H #define STM32_H +#include + /* STM32 Cortex-M core ids (CPUTAPID) */ enum stm32_core_id { STM32_CORE_ID_M0_SWD = 0x0bb11477, // (RM0091 Section 32.5.3) F0 SW-DP diff --git a/inc/stm32flash.h b/inc/stm32flash.h index 5cb0ee1df..69c6206ee 100644 --- a/inc/stm32flash.h +++ b/inc/stm32flash.h @@ -1,6 +1,8 @@ #ifndef STM32FLASH_H #define STM32FLASH_H +#include + /* STM32Fx FPEC flash controller interface, PM0063 manual */ // STM32F05x is identical, based on RM0091 (DM00031936, Doc ID 018940 Rev.2, Aug 2012) #define FLASH_REGS_ADDR 0x40022000 diff --git a/src/st-flash/flash.c b/src/st-flash/flash.c index bbb52d80c..6b4a10cfc 100644 --- a/src/st-flash/flash.c +++ b/src/st-flash/flash.c @@ -1,6 +1,7 @@ /* Simple wrapper around the stlink_flash_write function */ #include +#include #include #include @@ -20,7 +21,7 @@ static stlink_t *connected_stlink = NULL; -static void cleanup(int signum) { +static void cleanup(int32_t signum) { (void)signum; if (connected_stlink) { // switch back to mass storage mode before closing @@ -52,10 +53,10 @@ static void usage(void) { puts("example write option control register1 byte: ./st-flash --area=optcr1 write 0xXXXXXXXX"); } -int main(int ac, char** av) { +int32_t main(int32_t ac, char** av) { stlink_t* sl = NULL; struct flash_opts o; - int err = -1; + int32_t err = -1; uint8_t * mem = NULL; o.size = 0; @@ -82,7 +83,7 @@ int main(int ac, char** av) { if ( o.flash_size != 0u && o.flash_size != sl->flash_size ) { sl->flash_size = o.flash_size; - printf("Forcing flash size: --flash=0x%08X\n", (unsigned int)sl->flash_size); + printf("Forcing flash size: --flash=0x%08X\n", (uint32_t)sl->flash_size); } sl->verbose = o.log_level; @@ -222,8 +223,8 @@ int main(int ac, char** av) { } else if (o.area == FLASH_OPTION_BYTES) { size_t remaining_option_length = sl->option_size / 4; DLOG("@@@@ Read %u (%#x) option bytes from %#10x\n", - (unsigned)remaining_option_length, - (unsigned)remaining_option_length, + (uint32_t)remaining_option_length, + (uint32_t)remaining_option_length, sl->option_base); uint32_t option_byte = 0; @@ -232,7 +233,7 @@ int main(int ac, char** av) { printf("could not read option bytes (%d)\n", err); goto on_error; } else if (NULL != o.filename) { - int fd = open(o.filename, O_RDWR | O_TRUNC | O_CREAT | O_BINARY, 00700); + int32_t fd = open(o.filename, O_RDWR | O_TRUNC | O_CREAT | O_BINARY, 00700); if (fd == -1) { fprintf(stderr, "open(%s) == -1\n", o.filename); goto on_error; diff --git a/src/st-flash/flash.h b/src/st-flash/flash.h index 4aa6033f8..1a509a660 100644 --- a/src/st-flash/flash.h +++ b/src/st-flash/flash.h @@ -18,19 +18,19 @@ struct flash_opts { const char* filename; stm32_addr_t addr; size_t size; - int reset; - int log_level; + int32_t reset; + int32_t log_level; enum flash_format format; enum flash_area area; uint32_t val; size_t flash_size; // --flash=n[k, M] - int opt; // enable empty tail data drop optimization - int freq; // --freq=n[k, M] frequency of JTAG/SWD + int32_t opt; // enable empty tail data drop optimization + int32_t freq; // --freq=n[k, M] frequency of JTAG/SWD enum connect_type connect; }; #define FLASH_OPTS_INITIALIZER {0, { 0 }, NULL, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} -int flash_get_opts(struct flash_opts* o, int ac, char** av); +int32_t flash_get_opts(struct flash_opts* o, int32_t ac, char** av); #endif // FLASH_H diff --git a/src/st-flash/flash_opts.c b/src/st-flash/flash_opts.c index 984156aa3..e133d52c7 100644 --- a/src/st-flash/flash_opts.c +++ b/src/st-flash/flash_opts.c @@ -1,3 +1,4 @@ +#include #include #include #include @@ -18,7 +19,7 @@ static bool starts_with(const char * str, const char * prefix) { // support decimal, hexadecimal, octal, binary format like 0xff 12 1k 1M, 0b1001 // negative numbers are not supported // return 0 if success else return -1 -static int get_long_integer_from_char_array (const char *const str, uint64_t *read_value) { +static int32_t get_long_integer_from_char_array (const char *const str, uint64_t *read_value) { uint64_t value; char *tail; @@ -50,9 +51,9 @@ static int get_long_integer_from_char_array (const char *const str, uint64_t *re // support decimal, hexadecimal, octal, binary format like 0xff 12 1k 1M, 0b1001 // negative numbers are not supported // return 0 if success else return -1 -static int get_integer_from_char_array (const char *const str, uint32_t *read_value) { +static int32_t get_integer_from_char_array (const char *const str, uint32_t *read_value) { uint64_t value; - int result = get_long_integer_from_char_array (str, &value); + int32_t result = get_long_integer_from_char_array (str, &value); if (result != 0) { return(result); @@ -65,24 +66,24 @@ static int get_integer_from_char_array (const char *const str, uint32_t *read_va } } -static int invalid_args(const char *expected) { +static int32_t invalid_args(const char *expected) { fprintf(stderr, "*** Error: Expected args for this command: %s\n", expected); return(-1); } -static int bad_arg(const char *arg) { +static int32_t bad_arg(const char *arg) { fprintf(stderr, "*** Error: Invalid value for %s\n", arg); return(-1); } -int flash_get_opts(struct flash_opts* o, int ac, char** av) { +int32_t flash_get_opts(struct flash_opts* o, int32_t ac, char** av) { // defaults memset(o, 0, sizeof(*o)); o->log_level = STND_LOG_LEVEL; // options - int result; + int32_t result; while (ac >= 1) { if (strcmp(av[0], "--version") == 0) { diff --git a/src/st-info/info.c b/src/st-info/info.c index 9963606e3..86a1c2d8f 100644 --- a/src/st-info/info.c +++ b/src/st-info/info.c @@ -1,4 +1,5 @@ #include +#include #include #include #include @@ -42,26 +43,26 @@ static void stlink_print_info(stlink_t *sl) { if (params) { printf(" dev-type: %s\n", params->dev_type); } } -static void stlink_probe(enum connect_type connect, int freq) { +static void stlink_probe(enum connect_type connect, int32_t freq) { stlink_t **stdevs; size_t size; size = stlink_probe_usb(&stdevs, connect, freq); - printf("Found %u stlink programmers\n", (unsigned int)size); + printf("Found %u stlink programmers\n", (uint32_t)size); for (size_t n = 0; n < size; n++) { - if (size > 1) printf("%u.\n", (unsigned int)n+1); + if (size > 1) printf("%u.\n", (uint32_t)n+1); stlink_print_info(stdevs[n]); } stlink_probe_usb_free(&stdevs, size); } -static int print_data(int ac, char **av) { +static int32_t print_data(int32_t ac, char **av) { stlink_t* sl = NULL; enum connect_type connect = CONNECT_NORMAL; - int freq = 0; + int32_t freq = 0; if (strcmp(av[1], "--version") == 0) { printf("v%s\n", STLINK_VERSION); @@ -70,7 +71,7 @@ static int print_data(int ac, char **av) { init_chipids(STLINK_CHIPS_DIR); - for (int i=2; i #include #include +#include #include #include #include @@ -41,7 +42,7 @@ typedef struct { bool show_help; bool show_version; - int logging_level; + int32_t logging_level; uint32_t core_frequency; uint32_t trace_frequency; bool reset_board; @@ -144,7 +145,7 @@ static bool parse_frequency(char* text, uint32_t* result) return true; } -bool parse_options(int argc, char **argv, st_settings_t *settings) { +bool parse_options(int32_t argc, char **argv, st_settings_t *settings) { static struct option long_options[] = { {"help", no_argument, NULL, 'h'}, @@ -157,8 +158,8 @@ bool parse_options(int argc, char **argv, st_settings_t *settings) { {"force", no_argument, NULL, 'f'}, {0, 0, 0, 0}, }; - int option_index = 0; - int c; + int32_t option_index = 0; + int32_t c; bool error = false; settings->show_help = false; @@ -421,7 +422,7 @@ static trace_state update_trace(st_trace_t *trace, uint8_t c) { static bool read_trace(stlink_t *stlink, st_trace_t *trace) { uint8_t buffer[STLINK_TRACE_BUF_LEN]; - int length = stlink_trace_read(stlink, buffer, sizeof(buffer)); + int32_t length = stlink_trace_read(stlink, buffer, sizeof(buffer)); if (length < 0) { ELOG("Error reading trace (%d)\n", length); @@ -441,7 +442,7 @@ static bool read_trace(stlink_t *stlink, st_trace_t *trace) { trace->state = TRACE_STATE_UNKNOWN; } - for (int i = 0; i < length; i++) { + for (int32_t i = 0; i < length; i++) { trace->state = update_trace(trace, buffer[i]); } @@ -531,7 +532,7 @@ static void check_for_configuration_error(stlink_t *stlink, st_trace_t *trace, WLOG("****\n"); } -int main(int argc, char **argv) { +int32_t main(int32_t argc, char **argv) { #if defined(_WIN32) SetConsoleCtrlHandler((PHANDLER_ROUTINE)CtrlHandler, TRUE); #else diff --git a/src/st-util/gdb-remote.c b/src/st-util/gdb-remote.c index bdf8afd24..7d0f2c731 100644 --- a/src/st-util/gdb-remote.c +++ b/src/st-util/gdb-remote.c @@ -5,8 +5,8 @@ #include #include -#include #include +#include #if defined(_WIN32) #include @@ -19,9 +19,9 @@ static const char hex[] = "0123456789abcdef"; -int gdb_send_packet(int fd, char* data) { - unsigned int data_length = (unsigned int)strlen(data); - int length = data_length + 4; +int32_t gdb_send_packet(int32_t fd, char* data) { + uint32_t data_length = (uint32_t)strlen(data); + int32_t length = data_length + 4; char* packet = malloc(length); // '$' data (hex) '#' cksum (hex) memset(packet, 0, length); @@ -30,7 +30,7 @@ int gdb_send_packet(int fd, char* data) { uint8_t cksum = 0; - for (unsigned int i = 0; i < data_length; i++) { + for (uint32_t i = 0; i < data_length; i++) { packet[i + 1] = data[i]; cksum += data[i]; } @@ -61,12 +61,12 @@ int gdb_send_packet(int fd, char* data) { #define ALLOC_STEP 1024 -int gdb_recv_packet(int fd, char** buffer) { - unsigned packet_size = ALLOC_STEP + 1, packet_idx = 0; +int32_t gdb_recv_packet(int32_t fd, char** buffer) { + uint32_t packet_size = ALLOC_STEP + 1, packet_idx = 0; uint8_t cksum = 0; char recv_cksum[3] = {0}; char* packet_buffer = malloc(packet_size); - unsigned state; + uint32_t state; if (packet_buffer == NULL) { return(-2); @@ -167,7 +167,7 @@ int gdb_recv_packet(int fd, char** buffer) { * As we use the mode with ACK, in a (very unlikely) situation of a packet lost * because of this skipping, it will be resent anyway. */ -int gdb_check_for_interrupt(int fd) { +int32_t gdb_check_for_interrupt(int32_t fd) { struct pollfd pfd; pfd.fd = fd; pfd.events = POLLIN; diff --git a/src/st-util/gdb-remote.h b/src/st-util/gdb-remote.h index 03d6aea10..ec990455b 100644 --- a/src/st-util/gdb-remote.h +++ b/src/st-util/gdb-remote.h @@ -1,8 +1,10 @@ #ifndef GDB_REMOTE_H #define GDB_REMOTE_H -int gdb_send_packet(int fd, char* data); -int gdb_recv_packet(int fd, char** buffer); -int gdb_check_for_interrupt(int fd); +#include + +int32_t gdb_send_packet(int32_t fd, char* data); +int32_t gdb_recv_packet(int32_t fd, char** buffer); +int32_t gdb_check_for_interrupt(int32_t fd); #endif // GDB_REMOTE_H diff --git a/src/st-util/gdb-server.c b/src/st-util/gdb-server.c index 99cc0170b..557a24f5f 100644 --- a/src/st-util/gdb-server.c +++ b/src/st-util/gdb-server.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include @@ -57,18 +58,18 @@ static const char hex[] = "0123456789abcdef"; typedef struct _st_state_t { // things from command line, bleh - int logging_level; - int listen_port; - int persistent; + int32_t logging_level; + int32_t listen_port; + int32_t persistent; enum connect_type connect_mode; - int freq; + int32_t freq; char serialnumber[STLINK_SERIAL_BUFFER_SIZE]; bool semihosting; const char* current_memory_map; } st_state_t; -int serve(stlink_t *sl, st_state_t *st); +int32_t serve(stlink_t *sl, st_state_t *st); char* make_memory_map(stlink_t *sl); static void init_cache(stlink_t *sl); @@ -81,7 +82,7 @@ static void _cleanup() { } } -static void cleanup(int signum) { +static void cleanup(int32_t signum) { printf("Receive signal %i. Exiting...\n", signum); _cleanup(); exit(1); @@ -90,13 +91,13 @@ static void cleanup(int signum) { #if defined(_WIN32) BOOL WINAPI CtrlHandler(DWORD fdwCtrlType) { - printf("Receive signal %i. Exiting...\r\n", (int)fdwCtrlType); + printf("Receive signal %i. Exiting...\r\n", (int32_t)fdwCtrlType); _cleanup(); return FALSE; } #endif -int parse_options(int argc, char** argv, st_state_t *st) { +int32_t parse_options(int32_t argc, char** argv, st_state_t *st) { static struct option long_options[] = { {"help", no_argument, NULL, 'h'}, {"verbose", optional_argument, NULL, 'v'}, @@ -139,9 +140,9 @@ int parse_options(int argc, char** argv, st_state_t *st) { ; - int option_index = 0; - int c; - int q; + int32_t option_index = 0; + int32_t c; + int32_t q; while ((c = getopt_long(argc, argv, "hv::p:mn", long_options, &option_index)) != -1) switch (c) { @@ -211,7 +212,7 @@ int parse_options(int argc, char** argv, st_state_t *st) { return(0); } -int main(int argc, char** argv) { +int32_t main(int32_t argc, char** argv) { stlink_t *sl = NULL; st_state_t state; memset(&state, 0, sizeof(state)); @@ -564,42 +565,42 @@ char* make_memory_map(stlink_t *sl) { strcpy(map, memory_map_template_F4_DE); } else if (sl->core_id == STM32_CORE_ID_M7F_SWD) { snprintf(map, sz, memory_map_template_F7, - (unsigned int)sl->sram_size); + (uint32_t)sl->sram_size); } else if (sl->chip_id == STM32_CHIPID_H74xxx) { snprintf(map, sz, memory_map_template_H7, - (unsigned int)sl->flash_size, - (unsigned int)sl->flash_pgsz); + (uint32_t)sl->flash_size, + (uint32_t)sl->flash_pgsz); } else if (sl->chip_id == STM32_CHIPID_F4_HD) { strcpy(map, memory_map_template_F4_HD); } else if (sl->chip_id == STM32_CHIPID_F2) { snprintf(map, sz, memory_map_template_F2, - (unsigned int)sl->flash_size, - (unsigned int)sl->sram_size, - (unsigned int)sl->flash_size - 0x20000, - (unsigned int)sl->sys_base, - (unsigned int)sl->sys_size); + (uint32_t)sl->flash_size, + (uint32_t)sl->sram_size, + (uint32_t)sl->flash_size - 0x20000, + (uint32_t)sl->sys_base, + (uint32_t)sl->sys_size); } else if ((sl->chip_id == STM32_CHIPID_L4) || (sl->chip_id == STM32_CHIPID_L43x_L44x) || (sl->chip_id == STM32_CHIPID_L45x_L46x)) { snprintf(map, sz, memory_map_template_L4, - (unsigned int)sl->flash_size, - (unsigned int)sl->flash_size); + (uint32_t)sl->flash_size, + (uint32_t)sl->flash_size); } else if (sl->chip_id == STM32_CHIPID_L496x_L4A6x) { snprintf(map, sz, memory_map_template_L496, - (unsigned int)sl->flash_size, - (unsigned int)sl->flash_size); + (uint32_t)sl->flash_size, + (uint32_t)sl->flash_size); } else if (sl->chip_id == STM32_CHIPID_H72x) { snprintf(map, sz, memory_map_template_H72x3x, - (unsigned int)sl->flash_size, - (unsigned int)sl->flash_pgsz); + (uint32_t)sl->flash_size, + (uint32_t)sl->flash_pgsz); } else { snprintf(map, sz, memory_map_template, - (unsigned int)sl->flash_size, - (unsigned int)sl->sram_size, - (unsigned int)sl->flash_size, - (unsigned int)sl->flash_pgsz, - (unsigned int)sl->sys_base, - (unsigned int)sl->sys_size); + (uint32_t)sl->flash_size, + (uint32_t)sl->sram_size, + (uint32_t)sl->flash_size, + (uint32_t)sl->flash_pgsz, + (uint32_t)sl->sys_base, + (uint32_t)sl->sys_size); } return(map); @@ -627,14 +628,14 @@ static void init_data_watchpoints(stlink_t *sl) { stlink_write_debug32(sl, STLINK_REG_CM3_DEMCR, data); // make sure all watchpoints are cleared - for (int i = 0; i < DATA_WATCH_NUM; i++) { + for (int32_t i = 0; i < DATA_WATCH_NUM; i++) { data_watches[i].fun = WATCHDISABLED; stlink_write_debug32(sl, STLINK_REG_CM3_DWT_FUNn(i), 0); } } -static int add_data_watchpoint(stlink_t *sl, enum watchfun wf, stm32_addr_t addr, unsigned int len) { - int i = 0; +static int32_t add_data_watchpoint(stlink_t *sl, enum watchfun wf, stm32_addr_t addr, uint32_t len) { + int32_t i = 0; uint32_t mask, dummy; // computer mask @@ -678,8 +679,8 @@ static int add_data_watchpoint(stlink_t *sl, enum watchfun wf, stm32_addr_t addr return(-1); } -static int delete_data_watchpoint(stlink_t *sl, stm32_addr_t addr) { - int i; +static int32_t delete_data_watchpoint(stlink_t *sl, stm32_addr_t addr) { + int32_t i; for (i = 0; i < DATA_WATCH_NUM; i++) { if ((data_watches[i].addr == addr) && (data_watches[i].fun != WATCHDISABLED)) { @@ -697,9 +698,9 @@ static int delete_data_watchpoint(stlink_t *sl, stm32_addr_t addr) { return(-1); } -static int code_break_num; -static int code_lit_num; -static int code_break_rev; +static int32_t code_break_num; +static int32_t code_lit_num; +static int32_t code_break_rev; #define CODE_BREAK_NUM_MAX 15 #define CODE_BREAK_LOW 0x01 #define CODE_BREAK_HIGH 0x02 @@ -709,13 +710,13 @@ static int code_break_rev; struct code_hw_breakpoint { stm32_addr_t addr; - int type; + int32_t type; }; static struct code_hw_breakpoint code_breaks[CODE_BREAK_NUM_MAX]; static void init_code_breakpoints(stlink_t *sl) { - unsigned int val; + uint32_t val; memset(sl->q_buf, 0, 4); stlink_write_debug32(sl, STLINK_REG_CM3_FP_CTRL, 0x03 /* KEY | ENABLE */); stlink_read_debug32(sl, STLINK_REG_CM3_FP_CTRL, &val); @@ -732,22 +733,22 @@ static void init_code_breakpoints(stlink_t *sl) { stlink_write_debug32(sl, STLINK_REG_CM7_FP_LAR, STLINK_REG_CM7_FP_LAR_KEY); } - for (int i = 0; i < code_break_num; i++) { + for (int32_t i = 0; i < code_break_num; i++) { code_breaks[i].type = 0; stlink_write_debug32(sl, STLINK_REG_CM3_FP_COMPn(i), 0); } } -static int has_breakpoint(stm32_addr_t addr) { - for (int i = 0; i < code_break_num; i++) +static int32_t has_breakpoint(stm32_addr_t addr) { + for (int32_t i = 0; i < code_break_num; i++) if (code_breaks[i].addr == addr) { return(1); } return(0); } -static int update_code_breakpoint(stlink_t *sl, stm32_addr_t addr, int set) { +static int32_t update_code_breakpoint(stlink_t *sl, stm32_addr_t addr, int32_t set) { uint32_t mask; - int type; + int32_t type; stm32_addr_t fpb_addr; if (addr & 1) { @@ -763,8 +764,8 @@ static int update_code_breakpoint(stlink_t *sl, stm32_addr_t addr, int set) { fpb_addr = addr; } - int id = -1; - for (int i = 0; i < code_break_num; i++) + int32_t id = -1; + for (int32_t i = 0; i < code_break_num; i++) if (fpb_addr == code_breaks[i].addr || (set && code_breaks[i].type == 0)) { id = i; break; @@ -802,7 +803,7 @@ static int update_code_breakpoint(stlink_t *sl, stm32_addr_t addr, int set) { struct flash_block { stm32_addr_t addr; - unsigned length; + uint32_t length; uint8_t* data; struct flash_block* next; @@ -810,7 +811,7 @@ struct flash_block { static struct flash_block* flash_root; -static int flash_add_block(stm32_addr_t addr, unsigned length, stlink_t *sl) { +static int32_t flash_add_block(stm32_addr_t addr, uint32_t length, stlink_t *sl) { if (addr < FLASH_BASE || addr + length > FLASH_BASE + sl->flash_size) { ELOG("flash_add_block: incorrect bounds\n"); @@ -835,8 +836,8 @@ static int flash_add_block(stm32_addr_t addr, unsigned length, stlink_t *sl) { return(0); } -static int flash_populate(stm32_addr_t addr, uint8_t* data, unsigned length) { - unsigned int fit_blocks = 0, fit_length = 0; +static int32_t flash_populate(stm32_addr_t addr, uint8_t* data, uint32_t length) { + uint32_t fit_blocks = 0, fit_length = 0; for (struct flash_block* fb = flash_root; fb; fb = fb->next) { /* @@ -848,13 +849,13 @@ static int flash_populate(stm32_addr_t addr, uint8_t* data, unsigned length) { * a < Y && b > x */ - unsigned X = fb->addr, Y = fb->addr + fb->length; - unsigned a = addr, b = addr + length; + uint32_t X = fb->addr, Y = fb->addr + fb->length; + uint32_t a = addr, b = addr + length; if (a < Y && b > X) { // from start of the block - unsigned start = (a > X ? a : X) - X; - unsigned end = (b > Y ? Y : b) - X; + uint32_t start = (a > X ? a : X) - X; + uint32_t end = (b > Y ? Y : b) - X; memcpy(fb->data + start, data, end - start); @@ -876,9 +877,9 @@ static int flash_populate(stm32_addr_t addr, uint8_t* data, unsigned length) { return(0); } -static int flash_go(stlink_t *sl, st_state_t *st) { - int error = -1; - int ret; +static int32_t flash_go(stlink_t *sl, st_state_t *st) { + int32_t error = -1; + int32_t ret; flash_loader_t fl; stlink_target_connect(sl, st->connect_mode); @@ -904,13 +905,13 @@ static int flash_go(stlink_t *sl, st_state_t *st) { ILOG("flash_do: block %08x -> %04x\n", fb->addr, fb->length); for (stm32_addr_t page = fb->addr; page < fb->addr + fb->length; page += (uint32_t)FLASH_PAGE) { - unsigned length = fb->length - (page - fb->addr); + uint32_t length = fb->length - (page - fb->addr); // update FLASH_PAGE stlink_calculate_pagesize(sl, page); ILOG("flash_do: page %08x\n", page); - unsigned len = (length > FLASH_PAGE) ? (unsigned int)FLASH_PAGE : length; + uint32_t len = (length > FLASH_PAGE) ? (uint32_t)FLASH_PAGE : length; ret = stlink_flashloader_write(sl, &fl, page, fb->data + (page - fb->addr), len); if (ret) { goto error; } } @@ -933,21 +934,21 @@ static int flash_go(stlink_t *sl, st_state_t *st) { } struct cache_level_desc { - unsigned int nsets; - unsigned int nways; - unsigned int log2_nways; - unsigned int width; + uint32_t nsets; + uint32_t nways; + uint32_t log2_nways; + uint32_t width; }; struct cache_desc_t { - unsigned used; + uint32_t used; // minimal line size in bytes - unsigned int dminline; - unsigned int iminline; + uint32_t dminline; + uint32_t iminline; // last level of unification (uniprocessor) - unsigned int louu; + uint32_t louu; struct cache_level_desc icache[7]; struct cache_level_desc dcache[7]; @@ -956,8 +957,8 @@ struct cache_desc_t { static struct cache_desc_t cache_desc; // return the smallest R so that V <= (1 << R); not performance critical -static unsigned ceil_log2(unsigned v) { - unsigned res; +static uint32_t ceil_log2(uint32_t v) { + uint32_t res; for (res = 0; (1U << res) < v; res++); @@ -965,8 +966,8 @@ static unsigned ceil_log2(unsigned v) { } static void read_cache_level_desc(stlink_t *sl, struct cache_level_desc *desc) { - unsigned int ccsidr; - unsigned int log2_nsets; + uint32_t ccsidr; + uint32_t log2_nsets; stlink_read_debug32(sl, STLINK_REG_CM7_CCSIDR, &ccsidr); desc->nsets = ((ccsidr >> 13) & 0x3fff) + 1; @@ -979,10 +980,10 @@ static void read_cache_level_desc(stlink_t *sl, struct cache_level_desc *desc) { } static void init_cache (stlink_t *sl) { - unsigned int clidr; - unsigned int ccr; - unsigned int ctr; - int i; + uint32_t clidr; + uint32_t ccr; + uint32_t ctr; + int32_t i; // Check have cache stlink_read_debug32(sl, STLINK_REG_CM7_CTR, &ctr); @@ -1006,7 +1007,7 @@ static void init_cache (stlink_t *sl) { cache_desc.dminline, cache_desc.iminline); for (i = 0; i < 7; i++) { - unsigned int ct = (clidr >> (3 * i)) & 0x07; + uint32_t ct = (clidr >> (3 * i)) & 0x07; cache_desc.dcache[i].width = 0; cache_desc.icache[i].width = 0; @@ -1024,19 +1025,19 @@ static void init_cache (stlink_t *sl) { } } -static void cache_flush(stlink_t *sl, unsigned ccr) { - int level; +static void cache_flush(stlink_t *sl, uint32_t ccr) { + int32_t level; if (ccr & STLINK_REG_CM7_CCR_DC) { for (level = cache_desc.louu - 1; level >= 0; level--) { struct cache_level_desc *desc = &cache_desc.dcache[level]; - unsigned addr; - unsigned max_addr = 1 << desc->width; - unsigned way_sh = 32 - desc->log2_nways; + uint32_t addr; + uint32_t max_addr = 1 << desc->width; + uint32_t way_sh = 32 - desc->log2_nways; // D-cache clean by set-ways. for (addr = (level << 1); addr < max_addr; addr += cache_desc.dminline) { - unsigned int way; + uint32_t way; for (way = 0; way < desc->nways; way++) { stlink_write_debug32(sl, STLINK_REG_CM7_DCCSW, addr | (way << way_sh)); @@ -1051,9 +1052,9 @@ static void cache_flush(stlink_t *sl, unsigned ccr) { } } -static int cache_modified; +static int32_t cache_modified; -static void cache_change(stm32_addr_t start, unsigned count) { +static void cache_change(stm32_addr_t start, uint32_t count) { if (count == 0) { return; } (void)start; @@ -1061,7 +1062,7 @@ static void cache_change(stm32_addr_t start, unsigned count) { } static void cache_sync(stlink_t *sl) { - unsigned ccr; + uint32_t ccr; if (!cache_desc.used) { return; } @@ -1074,7 +1075,7 @@ static void cache_sync(stlink_t *sl) { static size_t unhexify(const char *in, char *out, size_t out_count) { size_t i; - unsigned int c; + uint32_t c; for (i = 0; i < out_count; i++) { if (sscanf(in + (2 * i), "%02x", &c) != 1) { return(i); } @@ -1085,7 +1086,7 @@ static size_t unhexify(const char *in, char *out, size_t out_count) { return(i); } -int serve(stlink_t *sl, st_state_t *st) { +int32_t serve(stlink_t *sl, st_state_t *st) { SOCKET sock = socket(AF_INET, SOCK_STREAM, 0); if (!IS_SOCK_VALID(sock)) { @@ -1093,7 +1094,7 @@ int serve(stlink_t *sl, st_state_t *st) { return(1); } - unsigned int val = 1; + uint32_t val = 1; setsockopt(sock, SOL_SOCKET, SO_REUSEADDR, (char *)&val, sizeof(val)); struct sockaddr_in serv_addr; @@ -1149,16 +1150,16 @@ int serve(stlink_t *sl, st_state_t *st) { * To allow resetting the chip from GDB it is required to emulate attaching * and detaching to target. */ - unsigned int attached = 1; + uint32_t attached = 1; // if a critical error is detected, break from the loop - int critical_error = 0; - int ret; + int32_t critical_error = 0; + int32_t ret; while (1) { ret = 0; char* packet; - int status = gdb_recv_packet(client, &packet); + int32_t status = gdb_recv_packet(client, &packet); if (status < 0) { ELOG("cannot recv: %d\n", status); @@ -1186,7 +1187,7 @@ int serve(stlink_t *sl, st_state_t *st) { params = separator + 1; } - unsigned queryNameLength = (unsigned int)(separator - &packet[1]); + uint32_t queryNameLength = (uint32_t)(separator - &packet[1]); char* queryName = calloc(queryNameLength + 1, 1); strncpy(queryName, &packet[1], queryNameLength); @@ -1205,8 +1206,8 @@ int serve(stlink_t *sl, st_state_t *st) { __s_addr = strsep(&tok, ","); s_length = tok; - unsigned addr = (unsigned int)strtoul(__s_addr, NULL, 16), - length = (unsigned int)strtoul(s_length, NULL, 16); + uint32_t addr = (uint32_t)strtoul(__s_addr, NULL, 16), + length = (uint32_t)strtoul(s_length, NULL, 16); DLOG("Xfer: type:%s;op:%s;annex:%s;addr:%d;length:%d\n", type, op, annex, addr, length); @@ -1223,7 +1224,7 @@ int serve(stlink_t *sl, st_state_t *st) { } if (data) { - unsigned data_length = (unsigned int)strlen(data); + uint32_t data_length = (uint32_t)strlen(data); if (addr + length > data_length) { length = data_length - addr; } @@ -1366,8 +1367,8 @@ int serve(stlink_t *sl, st_state_t *st) { __s_addr = strsep(&tok, ","); s_length = tok; - unsigned addr = (unsigned int)strtoul(__s_addr, NULL, 16), - length = (unsigned int)strtoul(s_length, NULL, 16); + uint32_t addr = (uint32_t)strtoul(__s_addr, NULL, 16), + length = (uint32_t)strtoul(s_length, NULL, 16); DLOG("FlashErase: addr:%08x,len:%04x\n", addr, length); @@ -1384,15 +1385,15 @@ int serve(stlink_t *sl, st_state_t *st) { __s_addr = strsep(&tok, ":"); data = tok; - unsigned addr = (unsigned int)strtoul(__s_addr, NULL, 16); - unsigned data_length = status - (unsigned int)(data - packet); + uint32_t addr = (uint32_t)strtoul(__s_addr, NULL, 16); + uint32_t data_length = status - (uint32_t)(data - packet); // Length of decoded data cannot be more than encoded, as escapes are removed. // Additional byte is reserved for alignment fix. uint8_t *decoded = calloc(data_length + 1, 1); - unsigned dec_index = 0; + uint32_t dec_index = 0; - for (unsigned int i = 0; i < data_length; i++) { + for (uint32_t i = 0; i < data_length; i++) { if (data[i] == 0x7d) { i++; decoded[dec_index++] = data[i] ^ 0x20; @@ -1457,7 +1458,7 @@ int serve(stlink_t *sl, st_state_t *st) { struct stlink_reg reg; stm32_addr_t pc; stm32_addr_t addr; - int offset = 0; + int32_t offset = 0; uint16_t insn; if (!st->semihosting) { break; } @@ -1547,15 +1548,15 @@ int serve(stlink_t *sl, st_state_t *st) { reply = calloc(8 * 16 + 1, 1); - for (int i = 0; i < 16; i++) { + for (int32_t i = 0; i < 16; i++) { sprintf(&reply[i * 8], "%08x", (uint32_t)htonl(regp.r[i])); } break; case 'p': { - unsigned id = (unsigned int)strtoul(&packet[1], NULL, 16); - unsigned myreg = 0xDEADDEAD; + uint32_t id = (uint32_t)strtoul(&packet[1], NULL, 16); + uint32_t myreg = 0xDEADDEAD; if (id < 16) { ret = stlink_read_reg(sl, id, ®p); @@ -1607,8 +1608,8 @@ int serve(stlink_t *sl, st_state_t *st) { char* s_reg = &packet[1]; char* s_value = strstr(&packet[1], "=") + 1; - unsigned reg = (unsigned int)strtoul(s_reg, NULL, 16); - unsigned value = (unsigned int)strtoul(s_value, NULL, 16); + uint32_t reg = (uint32_t)strtoul(s_reg, NULL, 16); + uint32_t value = (uint32_t)strtoul(s_value, NULL, 16); if (reg < 16) { @@ -1645,7 +1646,7 @@ int serve(stlink_t *sl, st_state_t *st) { case 'G': - for (int i = 0; i < 16; i++) { + for (int32_t i = 0; i < 16; i++) { char str[9] = {0}; strncpy(str, &packet[1 + i * 8], 8); uint32_t reg = (uint32_t)strtoul(str, NULL, 16); @@ -1662,12 +1663,12 @@ int serve(stlink_t *sl, st_state_t *st) { char* s_count = strstr(&packet[1], ",") + 1; stm32_addr_t start = (stm32_addr_t)strtoul(s_start, NULL, 16); - unsigned count = (unsigned int)strtoul(s_count, NULL, 16); + uint32_t count = (uint32_t)strtoul(s_count, NULL, 16); - unsigned adj_start = start % 4; - unsigned count_rnd = (count + adj_start + 4 - 1) / 4 * 4; + uint32_t adj_start = start % 4; + uint32_t count_rnd = (count + adj_start + 4 - 1) / 4 * 4; - if (count_rnd > sl->flash_pgsz) { count_rnd = (unsigned int)sl->flash_pgsz; } + if (count_rnd > sl->flash_pgsz) { count_rnd = (uint32_t)sl->flash_pgsz; } if (count_rnd > 0x1800) { count_rnd = 0x1800; } @@ -1679,7 +1680,7 @@ int serve(stlink_t *sl, st_state_t *st) { reply = calloc(count * 2 + 1, 1); - for (unsigned int i = 0; i < count; i++) { + for (uint32_t i = 0; i < count; i++) { reply[i * 2 + 0] = hex[sl->q_buf[i + adj_start] >> 4]; reply[i * 2 + 1] = hex[sl->q_buf[i + adj_start] & 0xf]; } @@ -1693,15 +1694,15 @@ int serve(stlink_t *sl, st_state_t *st) { char* hexdata = strstr(packet, ":") + 1; stm32_addr_t start = (stm32_addr_t)strtoul(s_start, NULL, 16); - unsigned count = (unsigned int)strtoul(s_count, NULL, 16); - int err = 0; + uint32_t count = (uint32_t)strtoul(s_count, NULL, 16); + int32_t err = 0; if (start % 4) { - unsigned align_count = 4 - start % 4; + uint32_t align_count = 4 - start % 4; if (align_count > count) { align_count = count; } - for (unsigned int i = 0; i < align_count; i++) { + for (uint32_t i = 0; i < align_count; i++) { char hextmp[3] = { hexdata[i * 2], hexdata[i * 2 + 1], 0 }; uint8_t byte = (uint8_t)strtoul(hextmp, NULL, 16); sl->q_buf[i] = byte; @@ -1715,9 +1716,9 @@ int serve(stlink_t *sl, st_state_t *st) { } if (count - count % 4) { - unsigned aligned_count = count - count % 4; + uint32_t aligned_count = count - count % 4; - for (unsigned int i = 0; i < aligned_count; i++) { + for (uint32_t i = 0; i < aligned_count; i++) { char hextmp[3] = { hexdata[i * 2], hexdata[i * 2 + 1], 0 }; uint8_t byte = (uint8_t)strtoul(hextmp, NULL, 16); sl->q_buf[i] = byte; @@ -1731,7 +1732,7 @@ int serve(stlink_t *sl, st_state_t *st) { } if (count) { - for (unsigned int i = 0; i < count; i++) { + for (uint32_t i = 0; i < count; i++) { char hextmp[3] = { hexdata[i * 2], hexdata[i * 2 + 1], 0 }; uint8_t byte = (uint8_t)strtoul(hextmp, NULL, 16); sl->q_buf[i] = byte; @@ -1871,7 +1872,7 @@ int serve(stlink_t *sl, st_state_t *st) { if (reply) { DLOG("send: %s\n", reply); - int result = gdb_send_packet(client, reply); + int32_t result = gdb_send_packet(client, reply); if (result != 0) { ELOG("cannot send: %d\n", result); diff --git a/src/st-util/semihosting.c b/src/st-util/semihosting.c index f603f6224..93a6cf7cc 100644 --- a/src/st-util/semihosting.c +++ b/src/st-util/semihosting.c @@ -1,4 +1,5 @@ #include +#include #include #include @@ -11,9 +12,9 @@ #include #include "semihosting.h" -static int mem_read_u8(stlink_t *sl, uint32_t addr, uint8_t *data) { - int offset = addr % 4; - int len = 4; +static int32_t mem_read_u8(stlink_t *sl, uint32_t addr, uint8_t *data) { + int32_t offset = addr % 4; + int32_t len = 4; if (sl == NULL || data == NULL) { return(-1); } @@ -25,9 +26,9 @@ static int mem_read_u8(stlink_t *sl, uint32_t addr, uint8_t *data) { } #ifdef UNUSED -static int mem_read_u16(stlink_t *sl, uint32_t addr, uint16_t *data) { - int offset = addr % 4; - int len = (offset > 2 ? 8 : 4); +static int32_t mem_read_u16(stlink_t *sl, uint32_t addr, uint16_t *data) { + int32_t offset = addr % 4; + int32_t len = (offset > 2 ? 8 : 4); if (sl == NULL || data == NULL) { return(-1); } @@ -38,9 +39,9 @@ static int mem_read_u16(stlink_t *sl, uint32_t addr, uint16_t *data) { return(0); } -static int mem_read_u32(stlink_t *sl, uint32_t addr, uint32_t *data) { - int offset = addr % 4; - int len = (offset > 0 ? 8 : 4); +static int32_t mem_read_u32(stlink_t *sl, uint32_t addr, uint32_t *data) { + int32_t offset = addr % 4; + int32_t len = (offset > 0 ? 8 : 4); if (sl == NULL || data == NULL) { return(-1); } @@ -52,9 +53,9 @@ static int mem_read_u32(stlink_t *sl, uint32_t addr, uint32_t *data) { } #endif -static int mem_read(stlink_t *sl, uint32_t addr, void *data, uint16_t len) { - int offset = addr % 4; - int read_len = len + offset; +static int32_t mem_read(stlink_t *sl, uint32_t addr, void *data, uint16_t len) { + int32_t offset = addr % 4; + int32_t read_len = len + offset; if (sl == NULL || data == NULL) { return(-1); } @@ -68,7 +69,7 @@ static int mem_read(stlink_t *sl, uint32_t addr, void *data, uint16_t len) { return(0); } -static int mem_write(stlink_t *sl, uint32_t addr, void *data, uint16_t len) { +static int32_t mem_write(stlink_t *sl, uint32_t addr, void *data, uint16_t len) { /* Note: this function can write more than it is asked to! * If addr is not an even 32 bit boundary, or len is not a multiple of 4. * If only 32 bit values can be written to the target, then this function should read @@ -78,8 +79,8 @@ static int mem_write(stlink_t *sl, uint32_t addr, void *data, uint16_t len) { * Just return when the length is zero avoiding unneeded work. */ if (len == 0) { return(0); } - int offset = addr % 4; - int write_len = len + offset; + int32_t offset = addr % 4; + int32_t write_len = len + offset; if (sl == NULL || data == NULL) { return(-1); } @@ -112,7 +113,7 @@ static int mem_write(stlink_t *sl, uint32_t addr, void *data, uint16_t len) { #define O_BINARY 0 #endif -static int open_mode_flags[12] = { +static int32_t open_mode_flags[12] = { O_RDONLY, O_RDONLY | O_BINARY, O_RDWR, @@ -127,9 +128,9 @@ static int open_mode_flags[12] = { O_RDWR | O_CREAT | O_APPEND | O_BINARY }; -static int saved_errno = 0; +static int32_t saved_errno = 0; -int do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { +int32_t do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { if (sl == NULL || ret == NULL) { return(-1); } @@ -200,7 +201,7 @@ int do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { case SEMIHOST_SYS_CLOSE: { uint32_t args[1]; - int fd; + int32_t fd; if (mem_read(sl, r1, args, sizeof(args)) != 0) { DLOG("Semihosting SYS_CLOSE error: cannot read args from target memory\n"); @@ -208,7 +209,7 @@ int do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { return(-1); } - fd = (int)args[0]; + fd = (int32_t)args[0]; DLOG("Semihosting: close(%d)\n", fd); @@ -222,7 +223,7 @@ int do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { { uint32_t args[3]; uint32_t buffer_address; - int fd; + int32_t fd; uint32_t buffer_len; void *buffer; @@ -232,7 +233,7 @@ int do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { return(-1); } - fd = (int)args[0]; + fd = (int32_t)args[0]; buffer_address = args[1]; buffer_len = args[2]; @@ -277,7 +278,7 @@ int do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { { uint32_t args[3]; uint32_t buffer_address; - int fd; + int32_t fd; uint32_t buffer_len; void *buffer; ssize_t read_result; @@ -288,7 +289,7 @@ int do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { return(-1); } - fd = (int)args[0]; + fd = (int32_t)args[0]; buffer_address = args[1]; buffer_len = args[2]; @@ -388,7 +389,7 @@ int do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { case SEMIHOST_SYS_SEEK: { uint32_t args[2]; - int fd; + int32_t fd; off_t offset; if (mem_read(sl, r1, args, sizeof(args)) != 0) { @@ -397,10 +398,10 @@ int do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { return(-1); } - fd = (int)args[0]; + fd = (int32_t)args[0]; offset = (off_t)args[1]; - DLOG("Semihosting: lseek(%d, %d, SEEK_SET)\n", fd, (int)offset); + DLOG("Semihosting: lseek(%d, %d, SEEK_SET)\n", fd, (int32_t)offset); *ret = (uint32_t)lseek(fd, offset, SEEK_SET); saved_errno = errno; @@ -437,7 +438,7 @@ int do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { return(-1); } - for (int i = 0; i < WRITE0_BUFFER_SIZE; i++) { + for (int32_t i = 0; i < WRITE0_BUFFER_SIZE; i++) { if (buf[i] == 0) { return(0); } fprintf(stderr, "%c", buf[i]); diff --git a/src/st-util/semihosting.h b/src/st-util/semihosting.h index e7ddfcd97..fd3990ba2 100644 --- a/src/st-util/semihosting.h +++ b/src/st-util/semihosting.h @@ -1,6 +1,8 @@ #ifndef SEMIHOSTING_H #define SEMIHOSTING_H +#include + #include #define SEMIHOST_SYS_OPEN 0x01 @@ -29,6 +31,6 @@ #define SEMIHOST_SYS_ELAPSED 0x30 #define SEMIHOST_SYS_TICKFREQ 0x31 -int do_semihosting(stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret); +int32_t do_semihosting(stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret); #endif // SEMIHOSTING_H diff --git a/src/stlink-gui/gui.c b/src/stlink-gui/gui.c index 2bf1f9d32..f0426f577 100644 --- a/src/stlink-gui/gui.c +++ b/src/stlink-gui/gui.c @@ -263,7 +263,7 @@ static gpointer stlink_gui_populate_filemem_view(gpointer data) { uint8_t* mem = NULL; size_t size = 0; uint32_t begin = 0; - int res = stlink_parse_ihex(gui->filename, 0, &mem, &size, &begin); + int32_t res = stlink_parse_ihex(gui->filename, 0, &mem, &size, &begin); if (res == 0) { if (gui->file_mem.memory) { @@ -440,7 +440,7 @@ static gchar *dev_format_chip_id(guint32 chip_id) { } static gchar *dev_format_mem_size(gsize flash_size) { - return(g_strdup_printf("%u kB", (unsigned int)(flash_size / 1024))); + return(g_strdup_printf("%u kB", (uint32_t)(flash_size / 1024))); } @@ -640,7 +640,7 @@ static void flash_button_cb(GtkWidget *widget, gpointer data) { } } -int export_to_file(const char*filename, const struct mem_t flash_mem) { +int32_t export_to_file(const char*filename, const struct mem_t flash_mem) { printf("%s\n", filename); FILE * f = fopen(filename, "w"); @@ -885,7 +885,7 @@ static void stlink_gui_build_ui(STlinkGUI *gui) { stlink_gui_set_disconnected(gui); } -int main(int argc, char **argv) { +int32_t main(int32_t argc, char **argv) { STlinkGUI *gui; gtk_init(&argc, &argv); diff --git a/src/stlink-gui/gui.h b/src/stlink-gui/gui.h index 08519ea56..2d7f31913 100644 --- a/src/stlink-gui/gui.h +++ b/src/stlink-gui/gui.h @@ -1,6 +1,7 @@ #ifndef GUI_H #define GUI_H +#include #include #define STLINK_TYPE_GUI (stlink_gui_get_type()) @@ -87,6 +88,6 @@ struct _STlinkGUIClass { }; GType stlink_gui_get_type(void); -int export_to_file(const char*filename, const struct mem_t flash_mem); +int32_t export_to_file(const char*filename, const struct mem_t flash_mem); #endif // GUI_H diff --git a/src/stlink-lib/calculate.c b/src/stlink-lib/calculate.c index ddab5ed08..132875a66 100644 --- a/src/stlink-lib/calculate.c +++ b/src/stlink-lib/calculate.c @@ -1,3 +1,5 @@ +#include + #include #include "calculate.h" #include "common_flash.h" @@ -39,7 +41,7 @@ uint32_t calculate_F7_sectornum(uint32_t flashaddr) { } uint32_t calculate_H7_sectornum(stlink_t *sl, uint32_t flashaddr, - unsigned bank) { + uint32_t bank) { flashaddr &= ~((bank == BANK_1) ? STM32_FLASH_BASE diff --git a/src/stlink-lib/calculate.h b/src/stlink-lib/calculate.h index 64dfb51b2..bdff782ae 100644 --- a/src/stlink-lib/calculate.h +++ b/src/stlink-lib/calculate.h @@ -7,6 +7,8 @@ #ifndef CALCULATE_H #define CALCULATE_H +#include + uint32_t calculate_F4_sectornum(uint32_t); uint32_t calculate_F7_sectornum(uint32_t); uint32_t calculate_H7_sectornum(stlink_t *, uint32_t, unsigned); diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index 347d89e14..7e99a8730 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -1,13 +1,14 @@ -#include "chipid.h" -#include -#include - #include #include #include +#include #include #include +#include "chipid.h" +#include +#include + static struct stlink_chipid_params *devicelist; void dump_a_chip(struct stlink_chipid_params *dev) { @@ -43,7 +44,7 @@ void process_chipfile(char *fname) { char *p, buf[256]; char word[64], value[64]; struct stlink_chipid_params *ts; - int nc; + int32_t nc; // fprintf (stderr, "processing chip-id file %s.\n", fname); fp = fopen(fname, "r"); diff --git a/src/stlink-lib/chipid.h b/src/stlink-lib/chipid.h index d6afc4525..9eaac722d 100644 --- a/src/stlink-lib/chipid.h +++ b/src/stlink-lib/chipid.h @@ -1,6 +1,8 @@ #ifndef CHIPID_H #define CHIPID_H +#include + #include #include diff --git a/src/stlink-lib/common.c b/src/stlink-lib/common.c index 8e4b9a716..cb87f5f36 100644 --- a/src/stlink-lib/common.c +++ b/src/stlink-lib/common.c @@ -1,16 +1,15 @@ +#include #include #include #include - +#include #include #include #include #include -#include #include #include - #include "calculate.h" #include "common_flash.h" #include "map_file.h" @@ -28,7 +27,7 @@ // Private structs and functions defines struct stlink_fread_worker_arg { - int fd; + int32_t fd; }; struct stlink_fread_ihex_worker_arg { @@ -42,12 +41,12 @@ struct stlink_fread_ihex_worker_arg { typedef bool (*save_block_fn)(void *arg, uint8_t *block, ssize_t len); static void stop_wdg_in_debug(stlink_t *); -int stlink_jtag_reset(stlink_t *, int); -int stlink_soft_reset(stlink_t *, int); +int32_t stlink_jtag_reset(stlink_t *, int); +int32_t stlink_soft_reset(stlink_t *, int); void _parse_version(stlink_t *, stlink_version_t *); static uint8_t stlink_parse_hex(const char *); -static int stlink_read(stlink_t *, stm32_addr_t, size_t, save_block_fn, void *); -static bool stlink_fread_ihex_init(struct stlink_fread_ihex_worker_arg *, int, stm32_addr_t); +static int32_t stlink_read(stlink_t *, stm32_addr_t, size_t, save_block_fn, void *); +static bool stlink_fread_ihex_init(struct stlink_fread_ihex_worker_arg *, int32_t, stm32_addr_t); static bool stlink_fread_ihex_worker(void *, uint8_t *, ssize_t); static bool stlink_fread_ihex_finalize(struct stlink_fread_ihex_worker_arg *); static bool stlink_fread_worker(void *, uint8_t *, ssize_t); @@ -67,7 +66,7 @@ void stlink_close(stlink_t *sl) { } // 250 -int stlink_exit_debug_mode(stlink_t *sl) { +int32_t stlink_exit_debug_mode(stlink_t *sl) { DLOG("*** stlink_exit_debug_mode ***\n"); if (sl->flash_type != STM32_FLASH_TYPE_UNKNOWN && @@ -80,16 +79,16 @@ int stlink_exit_debug_mode(stlink_t *sl) { } //248 -int stlink_enter_swd_mode(stlink_t *sl) { +int32_t stlink_enter_swd_mode(stlink_t *sl) { DLOG("*** stlink_enter_swd_mode ***\n"); return (sl->backend->enter_swd_mode(sl)); } // 271 // Force the core into the debug mode -> halted state. -int stlink_force_debug(stlink_t *sl) { +int32_t stlink_force_debug(stlink_t *sl) { DLOG("*** stlink_force_debug_mode ***\n"); - int res = sl->backend->force_debug(sl); + int32_t res = sl->backend->force_debug(sl); if (res) { return (res); } @@ -99,14 +98,14 @@ int stlink_force_debug(stlink_t *sl) { } // 251 -int stlink_exit_dfu_mode(stlink_t *sl) { +int32_t stlink_exit_dfu_mode(stlink_t *sl) { DLOG("*** stlink_exit_dfu_mode ***\n"); return (sl->backend->exit_dfu_mode(sl)); } // 253 -int stlink_core_id(stlink_t *sl) { - int ret; +int32_t stlink_core_id(stlink_t *sl) { + int32_t ret; DLOG("*** stlink_core_id ***\n"); ret = sl->backend->core_id(sl); @@ -127,8 +126,8 @@ int stlink_core_id(stlink_t *sl) { // 287 // stlink_chip_id() is called by stlink_load_device_params() // do not call this procedure directly. -int stlink_chip_id(stlink_t *sl, uint32_t *chip_id) { - int ret; +int32_t stlink_chip_id(stlink_t *sl, uint32_t *chip_id) { + int32_t ret; cortex_m3_cpuid_t cpu_id; // Read the CPU ID to determine where to read the core id @@ -193,7 +192,7 @@ int stlink_chip_id(stlink_t *sl, uint32_t *chip_id) { * @param sl stlink context * @param cpuid pointer to the result object */ -int stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid) { +int32_t stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid) { uint32_t raw; if (stlink_read_debug32(sl, STLINK_REG_CM3_CPUID, &raw)) { @@ -217,7 +216,7 @@ int stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid) { * @param sl * @return 0 for success, or -1 for unsupported core type. */ -int stlink_load_device_params(stlink_t *sl) { +int32_t stlink_load_device_params(stlink_t *sl) { // This seems to normally work so is unnecessary info for a normal user. // Demoted to debug. -- REW DLOG("Loading device parameters....\n"); @@ -312,17 +311,17 @@ int stlink_load_device_params(stlink_t *sl) { } ILOG("%s: %u KiB SRAM, %u KiB flash in at least %u %s pages.\n", - params->dev_type, (unsigned)(sl->sram_size / 1024), (unsigned)(sl->flash_size / 1024), - (sl->flash_pgsz < 1024) ? (unsigned)(sl->flash_pgsz) : (unsigned)(sl->flash_pgsz / 1024), + params->dev_type, (uint32_t)(sl->sram_size / 1024), (uint32_t)(sl->flash_size / 1024), + (sl->flash_pgsz < 1024) ? (uint32_t)(sl->flash_pgsz) : (uint32_t)(sl->flash_pgsz / 1024), (sl->flash_pgsz < 1024) ? "byte" : "KiB"); return (0); } // 254 -int stlink_reset(stlink_t *sl, enum reset_type type) { +int32_t stlink_reset(stlink_t *sl, enum reset_type type) { uint32_t dhcsr; - unsigned timeout; + uint32_t timeout; DLOG("*** stlink_reset ***\n"); @@ -352,7 +351,7 @@ int stlink_reset(stlink_t *sl, enum reset_type type) { */ dhcsr = 0; - int res = stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); + int32_t res = stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); if ((dhcsr & STLINK_REG_DHCSR_S_RESET_ST) == 0 && !res) { // reset not done yet --> try reset through AIRCR so that NRST does not need to be connected ILOG("NRST is not connected --> using software reset via AIRCR\n"); @@ -380,9 +379,9 @@ int stlink_reset(stlink_t *sl, enum reset_type type) { return (0); } -int stlink_soft_reset(stlink_t *sl, int halt_on_reset) { - int ret; - unsigned timeout; +int32_t stlink_soft_reset(stlink_t *sl, int32_t halt_on_reset) { + int32_t ret; + uint32_t timeout; uint32_t dhcsr, dfsr; DLOG("*** stlink_soft_reset %s***\n", halt_on_reset ? "(halt) " : ""); @@ -455,7 +454,7 @@ int stlink_soft_reset(stlink_t *sl, int halt_on_reset) { } // 255 -int stlink_run(stlink_t *sl, enum run_type type) { +int32_t stlink_run(stlink_t *sl, enum run_type type) { struct stlink_reg rr; DLOG("*** stlink_run ***\n"); @@ -472,7 +471,7 @@ int stlink_run(stlink_t *sl, enum run_type type) { } // 273 -int stlink_set_swdclk(stlink_t *sl, int freq_khz) { +int32_t stlink_set_swdclk(stlink_t *sl, int32_t freq_khz) { DLOG("*** set_swdclk ***\n"); return (sl->backend->set_swdclk(sl, freq_khz)); } @@ -500,8 +499,8 @@ void stlink_core_stat(stlink_t *sl) { } // 256 -int stlink_status(stlink_t *sl) { - int ret; +int32_t stlink_status(stlink_t *sl) { + int32_t ret; DLOG("*** stlink_status ***\n"); ret = sl->backend->status(sl); @@ -510,7 +509,7 @@ int stlink_status(stlink_t *sl) { } // 257 -int stlink_version(stlink_t *sl) { +int32_t stlink_version(stlink_t *sl) { DLOG("*** looking up stlink version ***\n"); if (sl->backend->version(sl)) { @@ -534,8 +533,8 @@ int stlink_version(stlink_t *sl) { } // 272 -int stlink_target_voltage(stlink_t *sl) { - int voltage = -1; +int32_t stlink_target_voltage(stlink_t *sl) { + int32_t voltage = -1; DLOG("*** reading target voltage\n"); if (sl->backend->target_voltage != NULL) { @@ -560,14 +559,14 @@ bool stlink_is_core_halted(stlink_t *sl) { } // 269 -int stlink_step(stlink_t *sl) { +int32_t stlink_step(stlink_t *sl) { DLOG("*** stlink_step ***\n"); return (sl->backend->step(sl)); } // 270 -int stlink_current_mode(stlink_t *sl) { - int mode = sl->backend->current_mode(sl); +int32_t stlink_current_mode(stlink_t *sl) { + int32_t mode = sl->backend->current_mode(sl); switch (mode) { case STLINK_DEV_DFU_MODE: @@ -586,19 +585,19 @@ int stlink_current_mode(stlink_t *sl) { } // 274 -int stlink_trace_enable(stlink_t *sl, uint32_t frequency) { +int32_t stlink_trace_enable(stlink_t *sl, uint32_t frequency) { DLOG("*** stlink_trace_enable ***\n"); return (sl->backend->trace_enable(sl, frequency)); } // 275 -int stlink_trace_disable(stlink_t *sl) { +int32_t stlink_trace_disable(stlink_t *sl) { DLOG("*** stlink_trace_disable ***\n"); return (sl->backend->trace_disable(sl)); } // 276 -int stlink_trace_read(stlink_t *sl, uint8_t *buf, size_t size) { +int32_t stlink_trace_read(stlink_t *sl, uint8_t *buf, size_t size) { return (sl->backend->trace_read(sl, buf, size)); } @@ -612,7 +611,7 @@ void stlink_print_data(stlink_t *sl) { DLOG("data_len = %d 0x%x\n", sl->q_len, sl->q_len); } - for (int i = 0; i < sl->q_len; i++) { + for (int32_t i = 0; i < sl->q_len; i++) { if (i % 16 == 0) { /* if (sl->q_data_dir == Q_DATA_OUT) { @@ -622,18 +621,18 @@ void stlink_print_data(stlink_t *sl) { } */ } - // DLOG(" %02x", (unsigned int) sl->q_buf[i]); - fprintf(stderr, " %02x", (unsigned int)sl->q_buf[i]); + // DLOG(" %02x", (uint32_t) sl->q_buf[i]); + fprintf(stderr, " %02x", (uint32_t)sl->q_buf[i]); } // DLOG("\n\n"); fprintf(stderr, "\n"); } // 283 -int stlink_mwrite_sram(stlink_t *sl, uint8_t *data, uint32_t length, stm32_addr_t addr) { +int32_t stlink_mwrite_sram(stlink_t *sl, uint8_t *data, uint32_t length, stm32_addr_t addr) { // write the file in sram at addr - int error = -1; + int32_t error = -1; size_t off; size_t len; @@ -688,10 +687,10 @@ int stlink_mwrite_sram(stlink_t *sl, uint8_t *data, uint32_t length, stm32_addr_ } //284 -int stlink_fwrite_sram(stlink_t *sl, const char *path, stm32_addr_t addr) { +int32_t stlink_fwrite_sram(stlink_t *sl, const char *path, stm32_addr_t addr) { // write the file in sram at addr - int error = -1; + int32_t error = -1; size_t off; size_t len; mapped_file_t mf = MAPPED_FILE_INITIALIZER; @@ -763,12 +762,12 @@ int stlink_fwrite_sram(stlink_t *sl, const char *path, stm32_addr_t addr) { } // 302 -int stlink_fread(stlink_t *sl, const char *path, bool is_ihex, stm32_addr_t addr, size_t size) { +int32_t stlink_fread(stlink_t *sl, const char *path, bool is_ihex, stm32_addr_t addr, size_t size) { // read size bytes from addr to file - ILOG("read from address %#010x size %u\n", addr, (unsigned)size); + ILOG("read from address %#010x size %u\n", addr, (uint32_t)size); - int error; - int fd = open(path, O_RDWR | O_TRUNC | O_CREAT | O_BINARY, 00700); + int32_t error; + int32_t fd = open(path, O_RDWR | O_TRUNC | O_CREAT | O_BINARY, 00700); if (fd == -1) { fprintf(stderr, "open(%s) == -1\n", path); @@ -797,9 +796,9 @@ int stlink_fread(stlink_t *sl, const char *path, bool is_ihex, stm32_addr_t addr } // 300 -int write_buffer_to_sram(stlink_t *sl, flash_loader_t *fl, const uint8_t *buf, size_t size) { +int32_t write_buffer_to_sram(stlink_t *sl, flash_loader_t *fl, const uint8_t *buf, size_t size) { // write the buffer right after the loader - int ret = 0; + int32_t ret = 0; size_t chunk = size & ~0x3; size_t rem = size & 0x3; @@ -858,15 +857,15 @@ uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr) { } // 279 -int stlink_parse_ihex(const char *path, uint8_t erased_pattern, uint8_t **mem, +int32_t stlink_parse_ihex(const char *path, uint8_t erased_pattern, uint8_t **mem, size_t *size, uint32_t *begin) { - int res = 0; + int32_t res = 0; *begin = UINT32_MAX; uint8_t *data = NULL; uint32_t end = 0; bool eof_found = false; - for (int scan = 0; (res == 0) && (scan < 2); ++scan) { + for (int32_t scan = 0; (res == 0) && (scan < 2); ++scan) { // parse file two times - first to find memory range, second - to fill it if (scan == 1) { if (!eof_found) { @@ -885,7 +884,7 @@ int stlink_parse_ihex(const char *path, uint8_t erased_pattern, uint8_t **mem, data = calloc(*size, 1); // use calloc to get NULL if out of memory if (!data) { - ELOG("Cannot allocate %u bytes\n", (unsigned)(*size)); + ELOG("Cannot allocate %u bytes\n", (uint32_t)(*size)); res = -1; break; } @@ -1029,7 +1028,7 @@ uint8_t stlink_get_erased_pattern(stlink_t *sl) { } // 322 -int stlink_target_connect(stlink_t *sl, enum connect_type connect) { +int32_t stlink_target_connect(stlink_t *sl, enum connect_type connect) { if (connect == CONNECT_UNDER_RESET) { stlink_enter_swd_mode(sl); @@ -1045,7 +1044,7 @@ int stlink_target_connect(stlink_t *sl, enum connect_type connect) { stlink_jtag_reset(sl, STLINK_DEBUG_APIV2_DRIVE_NRST_HIGH); // try to halt the core after reset - unsigned timeout = time_ms() + 10; + uint32_t timeout = time_ms() + 10; while (time_ms() < timeout) { sl->backend->force_debug(sl); usleep(100); @@ -1128,7 +1127,7 @@ static void stop_wdg_in_debug(stlink_t *sl) { } } -int stlink_jtag_reset(stlink_t *sl, int value) { +int32_t stlink_jtag_reset(stlink_t *sl, int32_t value) { DLOG("*** stlink_jtag_reset %d ***\n", value); return (sl->backend->jtag_reset(sl, value)); } @@ -1207,7 +1206,7 @@ void stlink_run_at(stlink_t *sl, stm32_addr_t addr) { /* Limit the block size to compare to 0x1800 as anything larger will stall the * STLINK2 Maybe STLINK V1 needs smaller value! */ -int check_file(stlink_t *sl, mapped_file_t *mf, stm32_addr_t addr) { +int32_t check_file(stlink_t *sl, mapped_file_t *mf, stm32_addr_t addr) { size_t off; size_t n_cmp = sl->flash_pgsz; @@ -1249,7 +1248,7 @@ void md5_calculate(mapped_file_t *mf) { Md5Finalise(&md5Context, &md5Hash); printf("md5 checksum: "); - for (int i = 0; i < (int)sizeof(md5Hash); i++) { + for (int32_t i = 0; i < (int32_t)sizeof(md5Hash); i++) { printf("%x", md5Hash.bytes[i]); } @@ -1269,17 +1268,17 @@ void stlink_checksum(mapped_file_t *mp) { } void stlink_fwrite_finalize(stlink_t *sl, stm32_addr_t addr) { - unsigned int val; + uint32_t val; // set PC to the reset routine stlink_read_debug32(sl, addr + 4, &val); stlink_write_reg(sl, val, 15); stlink_run(sl, RUN_NORMAL); } -static int stlink_read(stlink_t *sl, stm32_addr_t addr, size_t size, +static int32_t stlink_read(stlink_t *sl, stm32_addr_t addr, size_t size, save_block_fn fn, void *fn_arg) { - int error = -1; + int32_t error = -1; if (size < 1) { size = sl->flash_size; @@ -1333,7 +1332,7 @@ static bool stlink_fread_worker(void *arg, uint8_t *block, ssize_t len) { static uint8_t stlink_parse_hex(const char *hex) { uint8_t d[2]; - for (int i = 0; i < 2; ++i) { + for (int32_t i = 0; i < 2; ++i) { char c = *(hex + i); if (c >= '0' && c <= '9') { @@ -1406,7 +1405,7 @@ static bool stlink_fread_ihex_writeline(struct stlink_fread_ihex_worker_arg *the } static bool stlink_fread_ihex_init(struct stlink_fread_ihex_worker_arg *the_arg, - int fd, stm32_addr_t addr) { + int32_t fd, stm32_addr_t addr) { the_arg->file = fdopen(fd, "w"); the_arg->addr = addr; the_arg->lba = 0; diff --git a/src/stlink-lib/common.h b/src/stlink-lib/common.h index dd6cf95b2..c60b49199 100644 --- a/src/stlink-lib/common.h +++ b/src/stlink-lib/common.h @@ -7,7 +7,12 @@ #ifndef COMMON_H #define COMMON_H -int check_file(stlink_t *, mapped_file_t *, stm32_addr_t); +#include + +#include "map_file.h" +#include "md5.h" + +int32_t check_file(stlink_t *, mapped_file_t *, stm32_addr_t); void md5_calculate(mapped_file_t *); void stlink_checksum(mapped_file_t *); void stlink_fwrite_finalize(stlink_t *, stm32_addr_t); diff --git a/src/stlink-lib/common_flash.c b/src/stlink-lib/common_flash.c index a74d88b16..e2a394946 100644 --- a/src/stlink-lib/common_flash.c +++ b/src/stlink-lib/common_flash.c @@ -1,7 +1,9 @@ +#include #include -#include #include #include + +#include #include "calculate.h" #include "flash_loader.h" #include "common_flash.h" @@ -31,7 +33,7 @@ uint32_t get_stm32l0_flash_base(stlink_t *sl) { } } -uint32_t read_flash_cr(stlink_t *sl, unsigned bank) { +uint32_t read_flash_cr(stlink_t *sl, uint32_t bank) { uint32_t reg, res; if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { @@ -117,7 +119,7 @@ void lock_flash(stlink_t *sl) { } } -static inline int write_flash_sr(stlink_t *sl, unsigned bank, uint32_t val) { +static inline int32_t write_flash_sr(stlink_t *sl, uint32_t bank, uint32_t val) { uint32_t sr_reg; if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || @@ -190,7 +192,7 @@ void clear_flash_error(stlink_t *sl) { } } -uint32_t read_flash_sr(stlink_t *sl, unsigned bank) { +uint32_t read_flash_sr(stlink_t *sl, uint32_t bank) { uint32_t res, sr_reg; if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || @@ -222,9 +224,9 @@ uint32_t read_flash_sr(stlink_t *sl, unsigned bank) { return (res); } -unsigned int is_flash_busy(stlink_t *sl) { +uint32_t is_flash_busy(stlink_t *sl) { uint32_t sr_busy_shift; - unsigned int res; + uint32_t res; if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || (sl->flash_type == STM32_FLASH_TYPE_F1_XL) || @@ -267,7 +269,7 @@ void wait_flash_busy(stlink_t *sl) { ; } -int check_flash_error(stlink_t *sl) { +int32_t check_flash_error(stlink_t *sl) { uint32_t res = 0; uint32_t WRPERR, PROGERR, PGAERR; @@ -361,7 +363,7 @@ int check_flash_error(stlink_t *sl) { return (0); } -static inline unsigned int is_flash_locked(stlink_t *sl) { +static inline uint32_t is_flash_locked(stlink_t *sl) { /* return non zero for true */ uint32_t cr_lock_shift; uint32_t cr_reg; @@ -463,7 +465,7 @@ static void unlock_flash(stlink_t *sl) { } /* unlock flash if already locked */ -int unlock_flash_if(stlink_t *sl) { +int32_t unlock_flash_if(stlink_t *sl) { if (is_flash_locked(sl)) { unlock_flash(sl); @@ -477,9 +479,9 @@ int unlock_flash_if(stlink_t *sl) { return (0); } -int lock_flash_option(stlink_t *sl) { +int32_t lock_flash_option(stlink_t *sl) { uint32_t optlock_shift, optcr_reg, n, optcr2_reg = 0; - int active_bit_level = 1; + int32_t active_bit_level = 1; switch (sl->flash_type) { case STM32_FLASH_TYPE_F0_F1_F3: @@ -555,7 +557,7 @@ int lock_flash_option(stlink_t *sl) { static bool is_flash_option_locked(stlink_t *sl) { uint32_t optlock_shift, optcr_reg; - int active_bit_level = 1; + int32_t active_bit_level = 1; uint32_t n; switch (sl->flash_type) { @@ -612,7 +614,7 @@ static bool is_flash_option_locked(stlink_t *sl) { return (n & (1u << optlock_shift)); } -static int unlock_flash_option(stlink_t *sl) { +static int32_t unlock_flash_option(stlink_t *sl) { uint32_t optkey_reg, optkey2_reg = 0; uint32_t optkey1 = FLASH_OPTKEY1; uint32_t optkey2 = FLASH_OPTKEY2; @@ -669,7 +671,7 @@ static int unlock_flash_option(stlink_t *sl) { return (0); } -int unlock_flash_option_if(stlink_t *sl) { +int32_t unlock_flash_option_if(stlink_t *sl) { if (is_flash_option_locked(sl)) { if (unlock_flash_option(sl)) { ELOG("Could not unlock flash option!\n"); @@ -687,7 +689,7 @@ int unlock_flash_option_if(stlink_t *sl) { } void write_flash_cr_psiz(stlink_t *sl, uint32_t n, - unsigned bank) { + uint32_t bank) { uint32_t cr_reg, psize_shift; uint32_t x = read_flash_cr(sl, bank); @@ -707,7 +709,7 @@ void write_flash_cr_psiz(stlink_t *sl, uint32_t n, stlink_write_debug32(sl, cr_reg, x); } -void clear_flash_cr_pg(stlink_t *sl, unsigned bank) { +void clear_flash_cr_pg(stlink_t *sl, uint32_t bank) { uint32_t cr_reg, n; uint32_t bit = FLASH_CR_PG; @@ -737,7 +739,7 @@ void clear_flash_cr_pg(stlink_t *sl, unsigned bank) { /* ------------------------------------------------------------------------ */ static void wait_flash_busy_progress(stlink_t *sl) { - int i = 0; + int32_t i = 0; fprintf(stdout, "Mass erasing..."); fflush(stdout); @@ -754,11 +756,11 @@ static void wait_flash_busy_progress(stlink_t *sl) { fprintf(stdout, "\n"); } -static inline void write_flash_ar(stlink_t *sl, uint32_t n, unsigned bank) { +static inline void write_flash_ar(stlink_t *sl, uint32_t n, uint32_t bank) { stlink_write_debug32(sl, (bank == BANK_1) ? FLASH_AR : FLASH_AR2, n); } -static inline void write_flash_cr_snb(stlink_t *sl, uint32_t n, unsigned bank) { +static inline void write_flash_cr_snb(stlink_t *sl, uint32_t n, uint32_t bank) { uint32_t cr_reg, snb_mask, snb_shift, ser_shift; uint32_t x = read_flash_cr(sl, bank); @@ -783,7 +785,7 @@ static inline void write_flash_cr_snb(stlink_t *sl, uint32_t n, unsigned bank) { stlink_write_debug32(sl, cr_reg, x); } -static void set_flash_cr_per(stlink_t *sl, unsigned bank) { +static void set_flash_cr_per(stlink_t *sl, uint32_t bank) { uint32_t cr_reg, val; if (sl->flash_type == STM32_FLASH_TYPE_G0 || @@ -802,7 +804,7 @@ static void set_flash_cr_per(stlink_t *sl, unsigned bank) { stlink_write_debug32(sl, cr_reg, val); } -static void clear_flash_cr_per(stlink_t *sl, unsigned bank) { +static void clear_flash_cr_per(stlink_t *sl, uint32_t bank) { uint32_t cr_reg; if (sl->flash_type == STM32_FLASH_TYPE_G0 || @@ -836,7 +838,7 @@ static inline void write_flash_cr_bker_pnb(stlink_t *sl, uint32_t n) { stlink_write_debug32(sl, FLASH_L4_CR, x); } -static void set_flash_cr_strt(stlink_t *sl, unsigned bank) { +static void set_flash_cr_strt(stlink_t *sl, uint32_t bank) { uint32_t val, cr_reg, cr_strt; if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { @@ -871,7 +873,7 @@ static void set_flash_cr_strt(stlink_t *sl, unsigned bank) { stlink_write_debug32(sl, cr_reg, val); } -static void set_flash_cr_mer(stlink_t *sl, bool v, unsigned bank) { +static void set_flash_cr_mer(stlink_t *sl, bool v, uint32_t bank) { uint32_t val, cr_reg, cr_mer, cr_pg; if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { @@ -936,7 +938,7 @@ static void set_flash_cr_mer(stlink_t *sl, bool v, unsigned bank) { * @param flashaddr an address in the flash page to erase * @return 0 on success -ve on failure */ -int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { +int32_t stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { // wait for ongoing op to finish wait_flash_busy(sl); // clear flash IO errors @@ -1108,7 +1110,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { lock_flash(sl); } else if (sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3 || sl->flash_type == STM32_FLASH_TYPE_F1_XL) { - unsigned bank = (flashaddr < STM32_F1_FLASH_BANK2_BASE) ? BANK_1 : BANK_2; + uint32_t bank = (flashaddr < STM32_F1_FLASH_BANK2_BASE) ? BANK_1 : BANK_2; unlock_flash_if(sl); clear_flash_cr_pg(sl, bank); // clear the pg bit set_flash_cr_per(sl, bank); // set the page erase bit @@ -1119,7 +1121,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { clear_flash_cr_per(sl, bank); // clear the page erase bit lock_flash(sl); } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { - unsigned bank = (flashaddr < STM32_H7_FLASH_BANK2_BASE) ? BANK_1 : BANK_2; + uint32_t bank = (flashaddr < STM32_H7_FLASH_BANK2_BASE) ? BANK_1 : BANK_2; unlock_flash_if(sl); // unlock if locked uint32_t sector = calculate_H7_sectornum( sl, flashaddr, bank); // calculate the actual page from the address @@ -1135,7 +1137,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { return check_flash_error(sl); } -int stlink_erase_flash_section(stlink_t *sl, stm32_addr_t base_addr, size_t size, bool align_size) { +int32_t stlink_erase_flash_section(stlink_t *sl, stm32_addr_t base_addr, size_t size, bool align_size) { // Check the address and size validity if (stlink_check_address_range_validity(sl, base_addr, size) < 0) { return -1; @@ -1149,11 +1151,11 @@ int stlink_erase_flash_section(stlink_t *sl, stm32_addr_t base_addr, size_t size stm32_addr_t addr = base_addr; do { - long unsigned int page_size = stlink_calculate_pagesize(sl, addr); + uint32_t page_size = stlink_calculate_pagesize(sl, addr); // Check if size is aligned with a page, unless we want to completely erase the last page if ((addr + page_size) > (base_addr + size) && !align_size) { - ELOG("Invalid size (not aligned with a page). Page size at address %#x is %#lx\n", addr, page_size); + ELOG("Invalid size (not aligned with a page). Page size at address %#x is %#x\n", addr, page_size); return (-1); } @@ -1162,7 +1164,7 @@ int stlink_erase_flash_section(stlink_t *sl, stm32_addr_t base_addr, size_t size return (-1); } - fprintf(stdout, "-> Flash page at %#x erased (size: %#lx)\n", addr, page_size); + fprintf(stdout, "-> Flash page at %#x erased (size: %#x)\n", addr, page_size); fflush(stdout); // check the next page is within the range to erase @@ -1173,8 +1175,8 @@ int stlink_erase_flash_section(stlink_t *sl, stm32_addr_t base_addr, size_t size return 0; } -int stlink_erase_flash_mass(stlink_t *sl) { - int err = 0; +int32_t stlink_erase_flash_mass(stlink_t *sl) { + int32_t err = 0; // TODO: User MER bit to mass-erase WB series. if (sl->flash_type == STM32_FLASH_TYPE_L0_L1 || @@ -1224,11 +1226,11 @@ int stlink_erase_flash_mass(stlink_t *sl) { return (err); } -int stlink_mwrite_flash(stlink_t *sl, uint8_t *data, uint32_t length, +int32_t stlink_mwrite_flash(stlink_t *sl, uint8_t *data, uint32_t length, stm32_addr_t addr) { /* Write the block in flash at addr */ - int err; - unsigned int num_empty, idx; + int32_t err; + uint32_t num_empty, idx; uint8_t erased_pattern = stlink_get_erased_pattern(sl); /* @@ -1236,7 +1238,7 @@ int stlink_mwrite_flash(stlink_t *sl, uint8_t *data, uint32_t length, * Therfore it is turned off by default. */ if (sl->opt) { - idx = (unsigned int)length; + idx = (uint32_t)length; for (num_empty = 0; num_empty != length; ++num_empty) if (data[--idx] != erased_pattern) { @@ -1273,10 +1275,10 @@ int stlink_mwrite_flash(stlink_t *sl, uint8_t *data, uint32_t length, * @param addr where to start writing * @return 0 on success, -ve on failure. */ -int stlink_fwrite_flash(stlink_t *sl, const char *path, stm32_addr_t addr) { +int32_t stlink_fwrite_flash(stlink_t *sl, const char *path, stm32_addr_t addr) { /* Write the file in flash at addr */ - int err; - unsigned int num_empty, idx; + int32_t err; + uint32_t num_empty, idx; uint8_t erased_pattern = stlink_get_erased_pattern(sl); mapped_file_t mf = MAPPED_FILE_INITIALIZER; @@ -1290,7 +1292,7 @@ int stlink_fwrite_flash(stlink_t *sl, const char *path, stm32_addr_t addr) { stlink_checksum(&mf); if (sl->opt) { - idx = (unsigned int)mf.len; + idx = (uint32_t)mf.len; for (num_empty = 0; num_empty != mf.len; ++num_empty) { if (mf.base[--idx] != erased_pattern) { @@ -1323,10 +1325,10 @@ int stlink_fwrite_flash(stlink_t *sl, const char *path, stm32_addr_t addr) { } -int stlink_fcheck_flash(stlink_t *sl, const char *path, stm32_addr_t addr) { +int32_t stlink_fcheck_flash(stlink_t *sl, const char *path, stm32_addr_t addr) { // check the contents of path are at addr - int res; + int32_t res; mapped_file_t mf = MAPPED_FILE_INITIALIZER; if (map_file(&mf, path) == -1) { @@ -1346,8 +1348,8 @@ int stlink_fcheck_flash(stlink_t *sl, const char *path, stm32_addr_t addr) { * @param length how much * @return 0 for success, -ve for failure */ -int stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, - unsigned length) { +int32_t stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, + uint32_t length) { size_t off; size_t cmp_size = (sl->flash_pgsz > 0x1800) ? 0x1800 : sl->flash_pgsz; ILOG("Starting verification of write complete\n"); @@ -1369,7 +1371,7 @@ int stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, stlink_read_mem32(sl, address + (uint32_t)off, (uint16_t)aligned_size); if (memcmp(sl->q_buf, data + off, cmp_size)) { - ELOG("Verification of flash failed at offset: %u\n", (unsigned int)off); + ELOG("Verification of flash failed at offset: %u\n", (uint32_t)off); return (-1); } } @@ -1379,23 +1381,23 @@ int stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, } // Check if an address and size are within the flash -int stlink_check_address_range_validity(stlink_t *sl, stm32_addr_t addr, size_t size) { - long unsigned int logvar; +int32_t stlink_check_address_range_validity(stlink_t *sl, stm32_addr_t addr, size_t size) { + uint32_t logvar; if (addr < sl->flash_base || addr >= (sl->flash_base + sl->flash_size)) { logvar = sl->flash_base + sl->flash_size - 1; - ELOG("Invalid address, it should be within 0x%08x - 0x%08lx\n", sl->flash_base, logvar); + ELOG("Invalid address, it should be within 0x%08x - 0x%08x\n", sl->flash_base, logvar); return (-1); } if ((addr + size) > (sl->flash_base + sl->flash_size)) { logvar = sl->flash_base + sl->flash_size - addr; - ELOG("The size exceeds the size of the flash (0x%08lx bytes available)\n", logvar); + ELOG("The size exceeds the size of the flash (0x%08x bytes available)\n", logvar); return (-1); } return 0; } // Check if an address is aligned with the beginning of a page -int stlink_check_address_alignment(stlink_t *sl, stm32_addr_t addr) { +int32_t stlink_check_address_alignment(stlink_t *sl, stm32_addr_t addr) { stm32_addr_t page = sl->flash_base; while (page < addr) { @@ -1409,9 +1411,9 @@ int stlink_check_address_alignment(stlink_t *sl, stm32_addr_t addr) { return 0; } -int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t *base, +int32_t stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint32_t len, uint8_t eraseonly) { - int ret; + int32_t ret; flash_loader_t fl; ILOG("Attempting to write %d (%#x) bytes to stm32 address: %u (%#x)\n", len, len, addr, addr); @@ -1428,7 +1430,7 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t *base, ELOG("addr not a multiple of current pagesize (%u bytes), not supported, " "check page start address and compare with flash module organisation " "in related ST reference manual of your device.\n", - (unsigned)(sl->flash_pgsz)); + (uint32_t)(sl->flash_pgsz)); return (-1); } diff --git a/src/stlink-lib/common_flash.h b/src/stlink-lib/common_flash.h index aa92b2143..04e9134b5 100644 --- a/src/stlink-lib/common_flash.h +++ b/src/stlink-lib/common_flash.h @@ -7,13 +7,15 @@ #ifndef COMMON_FLASH_H #define COMMON_FLASH_H +#include + void lock_flash(stlink_t *); void clear_flash_error(stlink_t *); void wait_flash_busy(stlink_t *); -int check_flash_error(stlink_t *); -int unlock_flash_if(stlink_t *); -int lock_flash_option(stlink_t *); -int unlock_flash_option_if(stlink_t *); +int32_t check_flash_error(stlink_t *); +int32_t unlock_flash_if(stlink_t *); +int32_t lock_flash_option(stlink_t *); +int32_t unlock_flash_option_if(stlink_t *); void write_flash_cr_psiz(stlink_t *, uint32_t, unsigned); void clear_flash_cr_pg(stlink_t *, unsigned); diff --git a/src/stlink-lib/flash_loader.c b/src/stlink-lib/flash_loader.c index 231a5d4d6..99a8260f7 100644 --- a/src/stlink-lib/flash_loader.c +++ b/src/stlink-lib/flash_loader.c @@ -1,3 +1,4 @@ +#include #include #include #include @@ -151,7 +152,7 @@ static const uint8_t loader_code_stm32f7_lv[] = { }; -int stlink_flash_loader_init(stlink_t *sl, flash_loader_t *fl) { +int32_t stlink_flash_loader_init(stlink_t *sl, flash_loader_t *fl) { size_t size = 0; uint32_t dfsr, cfsr, hfsr; @@ -199,18 +200,18 @@ int stlink_flash_loader_init(stlink_t *sl, flash_loader_t *fl) { return(0); } -static int loader_v_dependent_assignment(stlink_t *sl, +static int32_t loader_v_dependent_assignment(stlink_t *sl, const uint8_t **loader_code, size_t *loader_size, const uint8_t *high_v_loader, size_t high_v_loader_size, const uint8_t *low_v_loader, size_t low_v_loader_size) { - int retval = 0; + int32_t retval = 0; if ( sl->version.stlink_v == 1) { printf("STLINK V1 cannot read voltage, defaulting to 32-bit writes\n"); *loader_code = high_v_loader; *loader_size = high_v_loader_size; } else { - int voltage = stlink_target_voltage(sl); + int32_t voltage = stlink_target_voltage(sl); if (voltage == -1) { retval = -1; @@ -229,7 +230,7 @@ static int loader_v_dependent_assignment(stlink_t *sl, return(retval); } -int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) { +int32_t stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) { const uint8_t* loader_code; size_t loader_size; @@ -270,7 +271,7 @@ int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* sl->chip_id == STM32_CHIPID_F412 || sl->chip_id == STM32_CHIPID_F413 || sl->chip_id == STM32_CHIPID_F446) { - int retval; + int32_t retval; retval = loader_v_dependent_assignment(sl, &loader_code, &loader_size, loader_code_stm32f4, sizeof(loader_code_stm32f4), @@ -281,7 +282,7 @@ int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* sl->chip_id == STM32_CHIPID_F7 || sl->chip_id == STM32_CHIPID_F76xxx || sl->chip_id == STM32_CHIPID_F72xxx) { - int retval; + int32_t retval; retval = loader_v_dependent_assignment(sl, &loader_code, &loader_size, loader_code_stm32f7, sizeof(loader_code_stm32f7), @@ -310,7 +311,7 @@ int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* } memcpy(sl->q_buf, loader_code, loader_size); - int ret = stlink_write_mem32(sl, sl->sram_base, (uint16_t)loader_size); + int32_t ret = stlink_write_mem32(sl, sl->sram_base, (uint16_t)loader_size); if (ret) { return(ret); } @@ -320,13 +321,13 @@ int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* return(0); // success } -int stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, const uint8_t* buf, size_t size) { +int32_t stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, const uint8_t* buf, size_t size) { struct stlink_reg rr; - unsigned timeout; + uint32_t timeout; uint32_t flash_base = 0; uint32_t dhcsr, dfsr, cfsr, hfsr; - DLOG("Running flash loader, write address:%#x, size: %u\n", target, (unsigned int)size); + DLOG("Running flash loader, write address:%#x, size: %u\n", target, (uint32_t)size); if (write_buffer_to_sram(sl, fl, buf, size) == -1) { ELOG("write_buffer_to_sram() == -1\n"); @@ -423,15 +424,15 @@ int stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t targe #define L1_WRITE_BLOCK_SIZE 0x80 #define L0_WRITE_BLOCK_SIZE 0x40 -int stm32l1_write_half_pages(stlink_t *sl, stm32_addr_t addr, uint8_t *base, +int32_t stm32l1_write_half_pages(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint32_t len, uint32_t pagesize) { - unsigned int count, off; - unsigned int num_half_pages = len / pagesize; + uint32_t count, off; + uint32_t num_half_pages = len / pagesize; uint32_t val; uint32_t flash_regs_base = get_stm32l0_flash_base(sl); flash_loader_t fl; bool use_loader = true; - int ret = 0; + int32_t ret = 0; // enable half page write stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); @@ -483,7 +484,7 @@ int stm32l1_write_half_pages(stlink_t *sl, stm32_addr_t addr, uint8_t *base, return (ret); } -static void set_flash_cr_pg(stlink_t *sl, unsigned bank) { +static void set_flash_cr_pg(stlink_t *sl, uint32_t bank) { uint32_t cr_reg, x; x = read_flash_cr(sl, bank); @@ -519,7 +520,7 @@ static void set_flash_cr_pg(stlink_t *sl, unsigned bank) { stlink_write_debug32(sl, cr_reg, x); } -static void set_dma_state(stlink_t *sl, flash_loader_t *fl, int bckpRstr) { +static void set_dma_state(stlink_t *sl, flash_loader_t *fl, int32_t bckpRstr) { uint32_t rcc, rcc_dma_mask, value; rcc = rcc_dma_mask = value = 0; @@ -580,7 +581,7 @@ static void set_dma_state(stlink_t *sl, flash_loader_t *fl, int bckpRstr) { } } -int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { +int32_t stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { // disable DMA set_dma_state(sl, fl, 0); @@ -602,7 +603,7 @@ int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { unlock_flash_if(sl); // first unlock the cr - int voltage; + int32_t voltage; if (sl->version.stlink_v == 1) { WLOG("STLINK V1 cannot read voltage, use default voltage 3.2V\n"); voltage = 3200; @@ -721,7 +722,7 @@ int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { return (0); } -int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, +int32_t stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t addr, uint8_t *base, uint32_t len) { size_t off; if ((sl->flash_type == STM32_FLASH_TYPE_F2_F4) || @@ -733,7 +734,7 @@ int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, if (stlink_flash_loader_run(sl, fl, addr + (uint32_t)off, base + off, size) == -1) { ELOG("stlink_flash_loader_run(%#x) failed! == -1\n", - (unsigned)(addr + off)); + (uint32_t)(addr + off)); check_flash_error(sl); return (-1); } @@ -744,14 +745,14 @@ int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, sl->flash_type == STM32_FLASH_TYPE_G0 || sl->flash_type == STM32_FLASH_TYPE_G4 || sl->flash_type == STM32_FLASH_TYPE_L5_U5) { - DLOG("Starting %3u page write\r\n", (unsigned int)(len / sl->flash_pgsz)); + DLOG("Starting %3u page write\r\n", (uint32_t)(len / sl->flash_pgsz)); for (off = 0; off < len; off += sizeof(uint32_t)) { uint32_t data; if ((off % sl->flash_pgsz) > (sl->flash_pgsz - 5)) { fprintf(stdout, "\r%3u/%3u pages written", - (unsigned int)(off / sl->flash_pgsz + 1), - (unsigned int)(len / sl->flash_pgsz)); + (uint32_t)(off / sl->flash_pgsz + 1), + (uint32_t)(len / sl->flash_pgsz)); fflush(stdout); } @@ -773,7 +774,7 @@ int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, uint32_t pagesize = (flash_regs_base == FLASH_L0_REGS_ADDR)? L0_WRITE_BLOCK_SIZE:L1_WRITE_BLOCK_SIZE; - DLOG("Starting %3u page write\r\n", (unsigned int)(len / sl->flash_pgsz)); + DLOG("Starting %3u page write\r\n", (uint32_t)(len / sl->flash_pgsz)); off = 0; @@ -791,8 +792,8 @@ int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, if ((off % sl->flash_pgsz) > (sl->flash_pgsz - 5)) { fprintf(stdout, "\r%3u/%3u pages written", - (unsigned int)(off / sl->flash_pgsz + 1), - (unsigned int)(len / sl->flash_pgsz)); + (uint32_t)(off / sl->flash_pgsz + 1), + (uint32_t)(len / sl->flash_pgsz)); fflush(stdout); } @@ -809,7 +810,7 @@ int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, fprintf(stdout, "\n"); } else if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || (sl->flash_type == STM32_FLASH_TYPE_F1_XL)) { - int write_block_count = 0; + int32_t write_block_count = 0; for (off = 0; off < len; off += sl->flash_pgsz) { // adjust last write size size_t size = len - off > sl->flash_pgsz ? sl->flash_pgsz : len - off; @@ -822,7 +823,7 @@ int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, if (stlink_flash_loader_run(sl, fl, addr + (uint32_t)off, base + off, size) == -1) { ELOG("stlink_flash_loader_run(%#x) failed! == -1\n", - (unsigned)(addr + off)); + (uint32_t)(addr + off)); check_flash_error(sl); return (-1); } @@ -833,7 +834,7 @@ int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, // show progress; writing procedure is slow and previous errors are // misleading fprintf(stdout, "\r%3u/%3u pages written", ++write_block_count, - (unsigned int)((len + sl->flash_pgsz - 1) / sl->flash_pgsz)); + (uint32_t)((len + sl->flash_pgsz - 1) / sl->flash_pgsz)); fflush(stdout); } } @@ -852,8 +853,8 @@ int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, if (sl->verbose >= 1) { // show progress - fprintf(stdout, "\r%u/%u bytes written", (unsigned int)off, - (unsigned int)len); + fprintf(stdout, "\r%u/%u bytes written", (uint32_t)off, + (uint32_t)len); fflush(stdout); } } @@ -867,7 +868,7 @@ int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, return check_flash_error(sl); } -int stlink_flashloader_stop(stlink_t *sl, flash_loader_t *fl) { +int32_t stlink_flashloader_stop(stlink_t *sl, flash_loader_t *fl) { uint32_t dhcsr; if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || diff --git a/src/stlink-lib/flash_loader.h b/src/stlink-lib/flash_loader.h index 51448395f..5b7b0945d 100644 --- a/src/stlink-lib/flash_loader.h +++ b/src/stlink-lib/flash_loader.h @@ -7,18 +7,18 @@ #ifndef FLASH_LOADER_H #define FLASH_LOADER_H -#include #include +#include #include #include -int stlink_flash_loader_init(stlink_t *sl, flash_loader_t* fl); -int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size); -int stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, const uint8_t* buf, size_t size); +int32_t stlink_flash_loader_init(stlink_t *sl, flash_loader_t* fl); +int32_t stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size); +int32_t stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, const uint8_t* buf, size_t size); -int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl); -int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t addr, uint8_t* base, uint32_t len); -int stlink_flashloader_stop(stlink_t *sl, flash_loader_t *fl); +int32_t stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl); +int32_t stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t addr, uint8_t* base, uint32_t len); +int32_t stlink_flashloader_stop(stlink_t *sl, flash_loader_t *fl); #endif // FLASH_LOADER_H diff --git a/src/stlink-lib/helper.c b/src/stlink-lib/helper.c index 15e6397bf..a6155925f 100644 --- a/src/stlink-lib/helper.c +++ b/src/stlink-lib/helper.c @@ -1,23 +1,24 @@ -#include - #include +#include #include +#include "helper.h" + #ifdef STLINK_HAVE_SYS_TIME_H #include #else #include #endif -unsigned time_ms() { +uint32_t time_ms() { struct timeval tv; gettimeofday(&tv, NULL); - return (unsigned)(tv.tv_sec * 1000 + tv.tv_usec / 1000); + return (uint32_t)(tv.tv_sec * 1000 + tv.tv_usec / 1000); } -int arg_parse_freq(const char *str) { +int32_t arg_parse_freq(const char *str) { char *tail; - int value = (int)strtol(str, &tail, 10); + int32_t value = (int32_t)strtol(str, &tail, 10); if (tail[0] == 'M' && tail[1] == '\0') { value = value*1000; diff --git a/src/stlink-lib/helper.h b/src/stlink-lib/helper.h index cf45bbf43..dbd760a52 100644 --- a/src/stlink-lib/helper.h +++ b/src/stlink-lib/helper.h @@ -1,8 +1,10 @@ #ifndef HELPER_H #define HELPER_H -unsigned time_ms(); +#include -int arg_parse_freq(const char *str); +uint32_t time_ms(); + +int32_t arg_parse_freq(const char *str); #endif // HELPER_H diff --git a/src/stlink-lib/logging.c b/src/stlink-lib/logging.c index 79924fc20..a64ec4ef2 100644 --- a/src/stlink-lib/logging.c +++ b/src/stlink-lib/logging.c @@ -7,6 +7,7 @@ #include #include +#include #include #include #define __STDC_WANT_LIB_EXT1__ 1 @@ -14,14 +15,14 @@ #include "logging.h" -static int max_level = UDEBUG; +static int32_t max_level = UDEBUG; -int ugly_init(int maximum_threshold) { +int32_t ugly_init(int32_t maximum_threshold) { max_level = maximum_threshold; return (0); } -int ugly_log(int level, const char *tag, const char *format, ...) { +int32_t ugly_log(int32_t level, const char *tag, const char *format, ...) { if (level > max_level) { return (0); } @@ -84,7 +85,7 @@ int ugly_log(int level, const char *tag, const char *format, ...) { * - LIBUSB_LOG_LEVEL_DEBUG (4) : debug and informational messages are * printed to stderr */ -int ugly_libusb_log_level(enum ugly_loglevel v) { +int32_t ugly_libusb_log_level(enum ugly_loglevel v) { #ifdef __FreeBSD__ // FreeBSD includes its own reimplementation of libusb. // Its libusb_set_debug() function expects a lib_debug_level diff --git a/src/stlink-lib/logging.h b/src/stlink-lib/logging.h index 893a02c24..471933096 100644 --- a/src/stlink-lib/logging.h +++ b/src/stlink-lib/logging.h @@ -5,6 +5,8 @@ #ifndef LOGGING_H #define LOGGING_H +#include + #ifdef __cplusplus extern "C" { #endif @@ -22,9 +24,9 @@ enum ugly_loglevel { #define PRINTF_ARRT #endif -int ugly_init(int maximum_threshold); -int ugly_log(int level, const char *tag, const char *format, ...) PRINTF_ARRT; -int ugly_libusb_log_level(enum ugly_loglevel v); +int32_t ugly_init(int32_t maximum_threshold); +int32_t ugly_log(int32_t level, const char *tag, const char *format, ...) PRINTF_ARRT; +int32_t ugly_libusb_log_level(enum ugly_loglevel v); #define UGLY_LOG_FILE (strstr(__FILE__, "/") != NULL ? \ strrchr(__FILE__, '/') + 1 : strstr(__FILE__, "\\") != NULL ? \ diff --git a/src/stlink-lib/map_file.c b/src/stlink-lib/map_file.c index 3bb7555d5..bb83ff7be 100644 --- a/src/stlink-lib/map_file.c +++ b/src/stlink-lib/map_file.c @@ -1,11 +1,12 @@ #include -#include -#include +#include #include -#include -#include +#include +#include +#include "logging.h" #include "map_file.h" +#include "md5.h" #ifndef O_BINARY #define O_BINARY 0 @@ -15,11 +16,11 @@ #define MAX_FILE_SIZE (1<<20) // 1 GB max file size #endif -int map_file(mapped_file_t *mf, const char *path) { - int error = -1; +int32_t map_file(mapped_file_t *mf, const char *path) { + int32_t error = -1; struct stat st; - const int fd = open(path, O_RDONLY | O_BINARY); + const int32_t fd = open(path, O_RDONLY | O_BINARY); if (fd == -1) { fprintf(stderr, "open(%s) == -1\n", path); diff --git a/src/stlink-lib/map_file.h b/src/stlink-lib/map_file.h index f50a201f0..b33ebf5db 100644 --- a/src/stlink-lib/map_file.h +++ b/src/stlink-lib/map_file.h @@ -7,6 +7,8 @@ #ifndef MAP_FILE_H #define MAP_FILE_H +#include + #ifndef O_BINARY #define O_BINARY 0 #endif @@ -26,7 +28,7 @@ typedef struct mapped_file { #define MAPPED_FILE_INITIALIZER \ { NULL, 0 } -int map_file(mapped_file_t *, const char *); +int32_t map_file(mapped_file_t *, const char *); void unmap_file(mapped_file_t *); #endif // MAP_FILE_H diff --git a/src/stlink-lib/md5.c b/src/stlink-lib/md5.c index 4c353bfd6..19ec86b91 100644 --- a/src/stlink-lib/md5.c +++ b/src/stlink-lib/md5.c @@ -5,6 +5,7 @@ * This is free and unencumbered software released into the public domain - June 2013 - waterjuice.org */ +#include #include #include "md5.h" @@ -205,7 +206,7 @@ void Md5Update(Md5Context* Context /* [in out] */, void const* Buffer /* [in] */ } if ( BufferSize >= 64 ) { - Buffer = TransformFunction( Context, Buffer, BufferSize & ~(unsigned long)0x3f ); + Buffer = TransformFunction( Context, Buffer, BufferSize & ~(uint32_t)0x3f ); BufferSize &= 0x3f; } diff --git a/src/stlink-lib/option_bytes.c b/src/stlink-lib/option_bytes.c index f5932a7b9..e2d966b7a 100644 --- a/src/stlink-lib/option_bytes.c +++ b/src/stlink-lib/option_bytes.c @@ -1,10 +1,12 @@ +#include #include #include + #include -#include "option_bytes.h" +#include "common.h" #include "common_flash.h" #include "map_file.h" -#include "common.h" +#include "option_bytes.h" /** @@ -13,7 +15,7 @@ * @param option_byte * @return 0 on success, -ve on failure. */ -int stlink_read_option_control_register_f0(stlink_t *sl, uint32_t *option_byte) { +int32_t stlink_read_option_control_register_f0(stlink_t *sl, uint32_t *option_byte) { DLOG("@@@@ Read option control register byte from %#10x\n", FLASH_OBR); return stlink_read_debug32(sl, FLASH_OBR, option_byte); } @@ -26,8 +28,8 @@ int stlink_read_option_control_register_f0(stlink_t *sl, uint32_t *option_byte) * @param len of option bytes * @return 0 on success, -ve on failure. */ -static int stlink_write_option_bytes_f0(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t len) { - int ret = 0; +static int32_t stlink_write_option_bytes_f0(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t len) { + int32_t ret = 0; if (len < 12 || addr != STM32_F0_OPTION_BYTES_BASE) { WLOG("Only full write of option bytes area is supported\n"); @@ -81,12 +83,12 @@ static int stlink_write_option_bytes_f0(stlink_t *sl, stm32_addr_t addr, uint8_t * @param option_cr * @return 0 on success, -ve on failure. */ -static int stlink_write_option_control_register_f0(stlink_t *sl, uint32_t option_cr) { - int ret = 0; +static int32_t stlink_write_option_control_register_f0(stlink_t *sl, uint32_t option_cr) { + int32_t ret = 0; uint16_t opt_val[8]; - unsigned protection, optiondata; + uint32_t protection, optiondata; uint16_t user_options, user_data, rdp; - unsigned option_offset, user_data_offset; + uint32_t option_offset, user_data_offset; ILOG("Asked to write option control register %#10x to %#010x.\n", option_cr, FLASH_OBR); @@ -166,7 +168,7 @@ static int stlink_write_option_control_register_f0(stlink_t *sl, uint32_t option * @param option_byte * @return 0 on success, -ve on failure. */ -int stlink_read_option_control_register_f2(stlink_t *sl, uint32_t *option_byte) { +int32_t stlink_read_option_control_register_f2(stlink_t *sl, uint32_t *option_byte) { return stlink_read_debug32(sl, FLASH_F2_OPT_CR, option_byte); } @@ -176,7 +178,7 @@ int stlink_read_option_control_register_f2(stlink_t *sl, uint32_t *option_byte) * @param option_byte * @return 0 on success, -ve on failure. */ -int stlink_read_option_bytes_f2(stlink_t *sl, uint32_t *option_byte) { +int32_t stlink_read_option_bytes_f2(stlink_t *sl, uint32_t *option_byte) { return stlink_read_option_control_register_f2(sl, option_byte); } @@ -186,7 +188,7 @@ int stlink_read_option_bytes_f2(stlink_t *sl, uint32_t *option_byte) { * @param option_byte * @return 0 on success, -ve on failure. */ -int stlink_read_option_control_register_f4(stlink_t *sl, uint32_t *option_byte) { +int32_t stlink_read_option_control_register_f4(stlink_t *sl, uint32_t *option_byte) { return stlink_read_debug32(sl, FLASH_F4_OPTCR, option_byte); } @@ -196,7 +198,7 @@ int stlink_read_option_control_register_f4(stlink_t *sl, uint32_t *option_byte) * @param option_byte * @return 0 on success, -ve on failure. */ -int stlink_read_option_bytes_f4(stlink_t *sl, uint32_t *option_byte) { +int32_t stlink_read_option_bytes_f4(stlink_t *sl, uint32_t *option_byte) { return stlink_read_option_control_register_f4(sl, option_byte); } @@ -208,9 +210,9 @@ int stlink_read_option_bytes_f4(stlink_t *sl, uint32_t *option_byte) { * @param len of option bytes * @return 0 on success, -ve on failure. */ -static int stlink_write_option_bytes_f4(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint32_t len) { +static int32_t stlink_write_option_bytes_f4(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint32_t len) { uint32_t option_byte; - int ret = 0; + int32_t ret = 0; (void)addr; (void)len; @@ -237,10 +239,10 @@ static int stlink_write_option_bytes_f4(stlink_t *sl, stm32_addr_t addr, uint8_t * @param option_byte * @return 0 on success, -ve on failure. */ -// Since multiple bytes can be read, we read and print all, but one here +// Since multiple bytes can be read, we read and print32_t all, but one here // and then return the last one just like other devices. -int stlink_read_option_bytes_f7(stlink_t *sl, uint32_t *option_byte) { - int err = -1; +int32_t stlink_read_option_bytes_f7(stlink_t *sl, uint32_t *option_byte) { + int32_t err = -1; for (uint32_t counter = 0; counter < (sl->option_size / 4 - 1); counter++) { err = stlink_read_debug32(sl, sl->option_base + counter * sizeof(uint32_t), option_byte); if (err == -1) { @@ -264,9 +266,9 @@ int stlink_read_option_bytes_f7(stlink_t *sl, uint32_t *option_byte) { * @param len of option bytes * @return 0 on success, -ve on failure. */ -static int stlink_write_option_bytes_f7(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint32_t len) { +static int32_t stlink_write_option_bytes_f7(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint32_t len) { uint32_t option_byte; - int ret = 0; + int32_t ret = 0; // Clear errors clear_flash_error(sl); @@ -317,7 +319,7 @@ static int stlink_write_option_bytes_f7(stlink_t *sl, stm32_addr_t addr, uint8_t * @param option_byte * @return 0 on success, -ve on failure. */ -int stlink_read_option_control_register_f7(stlink_t *sl, uint32_t *option_byte) { +int32_t stlink_read_option_control_register_f7(stlink_t *sl, uint32_t *option_byte) { DLOG("@@@@ Read option control register byte from %#10x\n", FLASH_F7_OPTCR); return stlink_read_debug32(sl, FLASH_F7_OPTCR, option_byte); } @@ -328,8 +330,8 @@ int stlink_read_option_control_register_f7(stlink_t *sl, uint32_t *option_byte) * @param option_cr * @return 0 on success, -ve on failure. */ -static int stlink_write_option_control_register_f7(stlink_t *sl, uint32_t option_cr) { - int ret = 0; +static int32_t stlink_write_option_control_register_f7(stlink_t *sl, uint32_t option_cr) { + int32_t ret = 0; // Clear errors clear_flash_error(sl); @@ -358,7 +360,7 @@ static int stlink_write_option_control_register_f7(stlink_t *sl, uint32_t option * @param option_byte * @return 0 on success, -ve on failure. */ -int stlink_read_option_control_register1_f7(stlink_t *sl, uint32_t *option_byte) { +int32_t stlink_read_option_control_register1_f7(stlink_t *sl, uint32_t *option_byte) { DLOG("@@@@ Read option control register 1 byte from %#10x\n", FLASH_F7_OPTCR1); return stlink_read_debug32(sl, FLASH_F7_OPTCR1, option_byte); @@ -370,8 +372,8 @@ int stlink_read_option_control_register1_f7(stlink_t *sl, uint32_t *option_byte) * @param option_cr1 * @return 0 on success, -ve on failure. */ -static int stlink_write_option_control_register1_f7(stlink_t *sl, uint32_t option_cr1) { - int ret = 0; +static int32_t stlink_write_option_control_register1_f7(stlink_t *sl, uint32_t option_cr1) { + int32_t ret = 0; // Clear errors clear_flash_error(sl); @@ -405,7 +407,7 @@ static int stlink_write_option_control_register1_f7(stlink_t *sl, uint32_t optio * @param option_byte * @return 0 on success, -ve on failure. */ -int stlink_read_option_bytes_boot_add_f7(stlink_t *sl, uint32_t *option_byte) { +int32_t stlink_read_option_bytes_boot_add_f7(stlink_t *sl, uint32_t *option_byte) { DLOG("@@@@ Read option byte boot address\n"); return stlink_read_option_control_register1_f7(sl, option_byte); } @@ -428,7 +430,7 @@ stlink_write_option_bytes_boot_add_f7(stlink_t *sl, uint32_t option_byte_boot_ad * @param option_byte * @return 0 on success, -ve on failure. */ -int stlink_read_option_control_register_gx(stlink_t *sl, uint32_t *option_byte) { +int32_t stlink_read_option_control_register_gx(stlink_t *sl, uint32_t *option_byte) { return stlink_read_debug32(sl, FLASH_Gx_OPTR, option_byte); } @@ -438,7 +440,7 @@ int stlink_read_option_control_register_gx(stlink_t *sl, uint32_t *option_byte) * @param option_byte * @return 0 on success, -ve on failure. */ -int stlink_read_option_bytes_gx(stlink_t *sl, uint32_t *option_byte) { +int32_t stlink_read_option_bytes_gx(stlink_t *sl, uint32_t *option_byte) { return stlink_read_option_control_register_gx(sl, option_byte); } @@ -450,10 +452,10 @@ int stlink_read_option_bytes_gx(stlink_t *sl, uint32_t *option_byte) { * @param len of option bytes * @return 0 on success, -ve on failure. */ -static int stlink_write_option_bytes_gx(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint32_t len) { +static int32_t stlink_write_option_bytes_gx(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint32_t len) { /* Write options bytes */ uint32_t val; - int ret = 0; + int32_t ret = 0; (void)len; uint32_t data; @@ -488,7 +490,7 @@ static int stlink_write_option_bytes_gx(stlink_t *sl, stm32_addr_t addr, uint8_t * @param len of option bytes * @return 0 on success, -ve on failure. */ -static int stlink_write_option_bytes_h7(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint32_t len) { +static int32_t stlink_write_option_bytes_h7(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint32_t len) { uint32_t val; uint32_t data; @@ -556,11 +558,11 @@ static int stlink_write_option_bytes_h7(stlink_t *sl, stm32_addr_t addr, uint8_t * @param len of option bytes * @return 0 on success, -ve on failure. */ -static int stlink_write_option_bytes_l0(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint32_t len) { +static int32_t stlink_write_option_bytes_l0(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint32_t len) { uint32_t flash_base = get_stm32l0_flash_base(sl); uint32_t val; uint32_t data; - int ret = 0; + int32_t ret = 0; // Clear errors clear_flash_error(sl); @@ -598,10 +600,10 @@ static int stlink_write_option_bytes_l0(stlink_t *sl, stm32_addr_t addr, uint8_t * @param len of option bytes * @return 0 on success, -ve on failure. */ -static int stlink_write_option_bytes_l4(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint32_t len) { +static int32_t stlink_write_option_bytes_l4(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint32_t len) { uint32_t val; - int ret = 0; + int32_t ret = 0; (void)addr; (void)len; @@ -638,10 +640,10 @@ static int stlink_write_option_bytes_l4(stlink_t *sl, stm32_addr_t addr, uint8_t * @param len of option bytes * @return 0 on success, -ve on failure. */ -static int stlink_write_option_bytes_wb(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint32_t len) { +static int32_t stlink_write_option_bytes_wb(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint32_t len) { /* Write options bytes */ uint32_t val; - int ret = 0; + int32_t ret = 0; (void)len; uint32_t data; @@ -686,7 +688,7 @@ static int stlink_write_option_bytes_wb(stlink_t *sl, stm32_addr_t addr, uint8_t * @param option_byte * @return 0 on success, -ve on failure. */ -int stlink_read_option_control_register_wb(stlink_t *sl, uint32_t *option_byte) { +int32_t stlink_read_option_control_register_wb(stlink_t *sl, uint32_t *option_byte) { DLOG("@@@@ Read option control register byte from %#10x\n", FLASH_WB_OPTR); return stlink_read_debug32(sl, FLASH_WB_OPTR, option_byte); } @@ -697,8 +699,8 @@ int stlink_read_option_control_register_wb(stlink_t *sl, uint32_t *option_byte) * @param option_cr * @return 0 on success, -ve on failure. */ -static int stlink_write_option_control_register_wb(stlink_t *sl, uint32_t option_cr) { - int ret = 0; +static int32_t stlink_write_option_control_register_wb(stlink_t *sl, uint32_t option_cr) { + int32_t ret = 0; // Clear errors clear_flash_error(sl); @@ -730,7 +732,7 @@ static int stlink_write_option_control_register_wb(stlink_t *sl, uint32_t option * @param option_byte * @return 0 on success, -ve on failure. */ -int stlink_read_option_bytes_generic(stlink_t *sl, uint32_t *option_byte) { +int32_t stlink_read_option_bytes_generic(stlink_t *sl, uint32_t *option_byte) { DLOG("@@@@ Read option bytes boot address from %#10x\n", sl->option_base); return stlink_read_debug32(sl, sl->option_base, option_byte); } @@ -744,8 +746,8 @@ int stlink_read_option_bytes_generic(stlink_t *sl, uint32_t *option_byte) { * @param len of option bytes * @return 0 on success, -ve on failure. */ -int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint32_t len) { - int ret = -1; +int32_t stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint32_t len) { + int32_t ret = -1; if (sl->option_base == 0) { ELOG("Option bytes writing is currently not supported for connected chip\n"); @@ -826,9 +828,9 @@ int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t *base, ui * @param addr of the memory mapped option bytes * @return 0 on success, -ve on failure. */ -int stlink_fwrite_option_bytes(stlink_t *sl, const char *path, stm32_addr_t addr) { +int32_t stlink_fwrite_option_bytes(stlink_t *sl, const char *path, stm32_addr_t addr) { /* Write the file in flash at addr */ - int err; + int32_t err; mapped_file_t mf = MAPPED_FILE_INITIALIZER; if (map_file(&mf, path) == -1) { @@ -853,7 +855,7 @@ int stlink_fwrite_option_bytes(stlink_t *sl, const char *path, stm32_addr_t addr * @param option_byte * @return 0 on success, -ve on failure. */ -int stlink_read_option_control_register32(stlink_t *sl, uint32_t *option_byte) { +int32_t stlink_read_option_control_register32(stlink_t *sl, uint32_t *option_byte) { if (sl->option_base == 0) { ELOG("Option bytes read is currently not supported for connected chip\n"); return -1; @@ -878,8 +880,8 @@ int stlink_read_option_control_register32(stlink_t *sl, uint32_t *option_byte) { * @param option_cr * @return 0 on success, -ve on failure. */ -int stlink_write_option_control_register32(stlink_t *sl, uint32_t option_cr) { - int ret = -1; +int32_t stlink_write_option_control_register32(stlink_t *sl, uint32_t option_cr) { + int32_t ret = -1; wait_flash_busy(sl); @@ -928,7 +930,7 @@ int stlink_write_option_control_register32(stlink_t *sl, uint32_t option_cr) { * @param option_byte * @return 0 on success, -ve on failure. */ -int stlink_read_option_control_register1_32(stlink_t *sl, uint32_t *option_byte) { +int32_t stlink_read_option_control_register1_32(stlink_t *sl, uint32_t *option_byte) { if (sl->option_base == 0) { ELOG("Option bytes read is currently not supported for connected chip\n"); return -1; @@ -949,8 +951,8 @@ int stlink_read_option_control_register1_32(stlink_t *sl, uint32_t *option_byte) * @param option_cr * @return 0 on success, -ve on failure. */ -int stlink_write_option_control_register1_32(stlink_t *sl, uint32_t option_cr1) { - int ret = -1; +int32_t stlink_write_option_control_register1_32(stlink_t *sl, uint32_t option_cr1) { + int32_t ret = -1; wait_flash_busy(sl); @@ -992,7 +994,7 @@ int stlink_write_option_control_register1_32(stlink_t *sl, uint32_t option_cr1) * @param option_byte * @return 0 on success, -ve on failure. */ -int stlink_read_option_bytes32(stlink_t *sl, uint32_t *option_byte) { +int32_t stlink_read_option_bytes32(stlink_t *sl, uint32_t *option_byte) { if (sl->option_base == 0) { ELOG("Option bytes read is currently not supported for connected chip\n"); return (-1); @@ -1022,7 +1024,7 @@ int stlink_read_option_bytes32(stlink_t *sl, uint32_t *option_byte) { * @param option_byte * @return 0 on success, -ve on failure. */ -int stlink_write_option_bytes32(stlink_t *sl, uint32_t option_byte) { +int32_t stlink_write_option_bytes32(stlink_t *sl, uint32_t option_byte) { WLOG("About to write option byte %#10x to %#10x.\n", option_byte, sl->option_base); return stlink_write_option_bytes(sl, sl->option_base, (uint8_t *)&option_byte, 4); @@ -1034,7 +1036,7 @@ int stlink_write_option_bytes32(stlink_t *sl, uint32_t option_byte) { * @param option_byte * @return 0 on success, -ve on failure. */ -int stlink_read_option_bytes_boot_add32(stlink_t *sl, uint32_t *option_byte) { +int32_t stlink_read_option_bytes_boot_add32(stlink_t *sl, uint32_t *option_byte) { if (sl->option_base == 0) { ELOG("Option bytes boot address read is currently not supported for connected chip\n"); return -1; @@ -1055,8 +1057,8 @@ int stlink_read_option_bytes_boot_add32(stlink_t *sl, uint32_t *option_byte) { * @param option_bytes_boot_add * @return 0 on success, -ve on failure. */ -int stlink_write_option_bytes_boot_add32(stlink_t *sl, uint32_t option_bytes_boot_add) { - int ret = -1; +int32_t stlink_write_option_bytes_boot_add32(stlink_t *sl, uint32_t option_bytes_boot_add) { + int32_t ret = -1; wait_flash_busy(sl); diff --git a/src/stlink-lib/option_bytes.h b/src/stlink-lib/option_bytes.h index 9c81fba8a..c0a1c9a6d 100644 --- a/src/stlink-lib/option_bytes.h +++ b/src/stlink-lib/option_bytes.h @@ -7,20 +7,22 @@ #ifndef OPTION_BYTES_H #define OPTION_BYTES_H +#include #include + #include -int stlink_read_option_bytes32(stlink_t *sl, uint32_t* option_byte); -int stlink_read_option_bytes_boot_add32(stlink_t *sl, uint32_t* option_byte); -int stlink_read_option_control_register32(stlink_t *sl, uint32_t* option_byte); -int stlink_read_option_control_register1_32(stlink_t *sl, uint32_t* option_byte); +int32_t stlink_read_option_bytes32(stlink_t *sl, uint32_t* option_byte); +int32_t stlink_read_option_bytes_boot_add32(stlink_t *sl, uint32_t* option_byte); +int32_t stlink_read_option_control_register32(stlink_t *sl, uint32_t* option_byte); +int32_t stlink_read_option_control_register1_32(stlink_t *sl, uint32_t* option_byte); -int stlink_write_option_bytes32(stlink_t *sl, uint32_t option_byte); -int stlink_write_option_bytes_boot_add32(stlink_t *sl, uint32_t option_bytes_boot_add); -int stlink_write_option_control_register32(stlink_t *sl, uint32_t option_cr); -int stlink_write_option_control_register1_32(stlink_t *sl, uint32_t option_cr1); +int32_t stlink_write_option_bytes32(stlink_t *sl, uint32_t option_byte); +int32_t stlink_write_option_bytes_boot_add32(stlink_t *sl, uint32_t option_bytes_boot_add); +int32_t stlink_write_option_control_register32(stlink_t *sl, uint32_t option_cr); +int32_t stlink_write_option_control_register1_32(stlink_t *sl, uint32_t option_cr1); -int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t len); -int stlink_fwrite_option_bytes(stlink_t *sl, const char* path, stm32_addr_t addr); +int32_t stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t len); +int32_t stlink_fwrite_option_bytes(stlink_t *sl, const char* path, stm32_addr_t addr); #endif // OPTION_BYTES_H \ No newline at end of file diff --git a/src/stlink-lib/read_write.c b/src/stlink-lib/read_write.c index efaa5a25f..f9c060bb2 100644 --- a/src/stlink-lib/read_write.c +++ b/src/stlink-lib/read_write.c @@ -1,5 +1,7 @@ +#include #include #include + #include // Endianness @@ -18,17 +20,17 @@ void write_uint16(unsigned char *buf, uint16_t ui) { buf[1] = (uint8_t)(ui >> 8); } -uint32_t read_uint32(const unsigned char *c, const int pt) { +uint32_t read_uint32(const unsigned char *c, const int32_t pt) { return ((uint32_t)c[pt]) | ((uint32_t)c[pt + 1] << 8) | ((uint32_t)c[pt + 2] << 16) | ((uint32_t)c[pt + 3] << 24); } -uint16_t read_uint16(const unsigned char *c, const int pt) { +uint16_t read_uint16(const unsigned char *c, const int32_t pt) { return ((uint16_t)c[pt]) | ((uint16_t)c[pt + 1] << 8); } -int stlink_read_debug32(stlink_t *sl, uint32_t addr, uint32_t *data) { - int ret; +int32_t stlink_read_debug32(stlink_t *sl, uint32_t addr, uint32_t *data) { + int32_t ret; ret = sl->backend->read_debug32(sl, addr, data); if (!ret) @@ -37,12 +39,12 @@ int stlink_read_debug32(stlink_t *sl, uint32_t addr, uint32_t *data) { return (ret); } -int stlink_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data) { +int32_t stlink_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data) { DLOG("*** stlink_write_debug32 %#010x to %#010x\n", data, addr); return sl->backend->write_debug32(sl, addr, data); } -int stlink_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { +int32_t stlink_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { DLOG("*** stlink_write_mem32 %u bytes to %#x\n", len, addr); if (len % 4 != 0) { @@ -53,7 +55,7 @@ int stlink_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { return (sl->backend->write_mem32(sl, addr, len)); } -int stlink_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { +int32_t stlink_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { DLOG("*** stlink_read_mem32 ***\n"); if (len % 4 != 0) { // !!! never ever: fw gives just wrong values @@ -64,27 +66,27 @@ int stlink_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { return (sl->backend->read_mem32(sl, addr, len)); } -int stlink_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len) { +int32_t stlink_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len) { DLOG("*** stlink_write_mem8 ***\n"); return (sl->backend->write_mem8(sl, addr, len)); } -int stlink_read_all_regs(stlink_t *sl, struct stlink_reg *regp) { +int32_t stlink_read_all_regs(stlink_t *sl, struct stlink_reg *regp) { DLOG("*** stlink_read_all_regs ***\n"); return (sl->backend->read_all_regs(sl, regp)); } -int stlink_read_all_unsupported_regs(stlink_t *sl, struct stlink_reg *regp) { +int32_t stlink_read_all_unsupported_regs(stlink_t *sl, struct stlink_reg *regp) { DLOG("*** stlink_read_all_unsupported_regs ***\n"); return (sl->backend->read_all_unsupported_regs(sl, regp)); } -int stlink_write_reg(stlink_t *sl, uint32_t reg, int idx) { +int32_t stlink_write_reg(stlink_t *sl, uint32_t reg, int32_t idx) { DLOG("*** stlink_write_reg\n"); return (sl->backend->write_reg(sl, reg, idx)); } -int stlink_read_reg(stlink_t *sl, int r_idx, struct stlink_reg *regp) { +int32_t stlink_read_reg(stlink_t *sl, int32_t r_idx, struct stlink_reg *regp) { DLOG("*** stlink_read_reg\n"); DLOG(" (%d) ***\n", r_idx); @@ -96,9 +98,9 @@ int stlink_read_reg(stlink_t *sl, int r_idx, struct stlink_reg *regp) { return (sl->backend->read_reg(sl, r_idx, regp)); } -int stlink_read_unsupported_reg(stlink_t *sl, int r_idx, +int32_t stlink_read_unsupported_reg(stlink_t *sl, int32_t r_idx, struct stlink_reg *regp) { - int r_convert; + int32_t r_convert; DLOG("*** stlink_read_unsupported_reg\n"); DLOG(" (%d) ***\n", r_idx); @@ -119,9 +121,9 @@ int stlink_read_unsupported_reg(stlink_t *sl, int r_idx, return (sl->backend->read_unsupported_reg(sl, r_convert, regp)); } -int stlink_write_unsupported_reg(stlink_t *sl, uint32_t val, int r_idx, +int32_t stlink_write_unsupported_reg(stlink_t *sl, uint32_t val, int32_t r_idx, struct stlink_reg *regp) { - int r_convert; + int32_t r_convert; DLOG("*** stlink_write_unsupported_reg\n"); DLOG(" (%d) ***\n", r_idx); diff --git a/src/stlink-lib/sg.c b/src/stlink-lib/sg.c index feab40c13..c0f79c7cf 100644 --- a/src/stlink-lib/sg.c +++ b/src/stlink-lib/sg.c @@ -75,10 +75,12 @@ */ #define __USE_GNU + #include +#include #include -#include #include +#include #include #include @@ -109,12 +111,12 @@ void _stlink_sg_close(stlink_t *sl) { } } -static int get_usb_mass_storage_status(libusb_device_handle *handle, uint8_t endpoint, uint32_t *tag) { +static int32_t get_usb_mass_storage_status(libusb_device_handle *handle, uint8_t endpoint, uint32_t *tag) { unsigned char csw[13]; memset(csw, 0, sizeof(csw)); - int transferred; - int ret; - int try = 0; + int32_t transferred; + int32_t ret; + int32_t try = 0; do { ret = libusb_bulk_transfer(handle, endpoint, (unsigned char *)&csw, sizeof(csw), @@ -150,13 +152,13 @@ static int get_usb_mass_storage_status(libusb_device_handle *handle, uint8_t end return(rstatus); } -static int dump_CDB_command(uint8_t *cdb, uint8_t cdb_len) { +static int32_t dump_CDB_command(uint8_t *cdb, uint8_t cdb_len) { char dbugblah[100]; char *dbugp = dbugblah; dbugp += sprintf(dbugp, "Sending CDB ["); for (uint8_t i = 0; i < cdb_len; i++) { - dbugp += sprintf(dbugp, " %#02x", (unsigned int)cdb[i]); + dbugp += sprintf(dbugp, " %#02x", (uint32_t)cdb[i]); } sprintf(dbugp, "]\n"); @@ -175,7 +177,7 @@ static int dump_CDB_command(uint8_t *cdb, uint8_t cdb_len) { * @param expected_rx_size * @return */ -int send_usb_mass_storage_command(libusb_device_handle *handle, uint8_t endpoint_out, +int32_t send_usb_mass_storage_command(libusb_device_handle *handle, uint8_t endpoint_out, uint8_t *cdb, uint8_t cdb_length, uint8_t lun, uint8_t flags, uint32_t expected_rx_size) { DLOG("Sending usb m-s cmd: cdblen:%d, rxsize=%d\n", cdb_length, expected_rx_size); @@ -185,10 +187,10 @@ int send_usb_mass_storage_command(libusb_device_handle *handle, uint8_t endpoint if (tag == 0) { tag = 1; } - int try = 0; - int ret = 0; - int real_transferred; - int i = 0; + int32_t try = 0; + int32_t ret = 0; + int32_t real_transferred; + int32_t i = 0; uint8_t c_buf[STLINK_SG_SIZE]; // tag is allegedly ignored... TODO - verify @@ -209,7 +211,7 @@ int send_usb_mass_storage_command(libusb_device_handle *handle, uint8_t endpoint assert(cdb_length <= CDB_SL); memcpy(&(c_buf[i]), cdb, cdb_length); - int sending_length = STLINK_SG_SIZE; + int32_t sending_length = STLINK_SG_SIZE; // send.... do { @@ -254,9 +256,9 @@ static void get_sense(libusb_device_handle *handle, uint8_t endpoint_in, uint8_t } unsigned char sense[REQUEST_SENSE_LENGTH]; - int transferred; - int ret; - int try = 0; + int32_t transferred; + int32_t ret; + int32_t try = 0; do { ret = libusb_bulk_transfer(handle, endpoint_in, sense, sizeof(sense), @@ -273,11 +275,11 @@ static void get_sense(libusb_device_handle *handle, uint8_t endpoint_in, uint8_t } if (transferred != sizeof(sense)) { - WLOG("received unexpected amount of sense: %d != %u\n", transferred, (unsigned)sizeof(sense)); + WLOG("received unexpected amount of sense: %d != %u\n", transferred, (uint32_t)sizeof(sense)); } uint32_t received_tag; - int status = get_usb_mass_storage_status(handle, endpoint_in, &received_tag); + int32_t status = get_usb_mass_storage_status(handle, endpoint_in, &received_tag); if (status != 0) { WLOG("receiving sense failed with status: %02x\n", status); @@ -301,11 +303,11 @@ static void get_sense(libusb_device_handle *handle, uint8_t endpoint_in, uint8_t * @param length how much to send * @return number of bytes actually sent, or -1 for failures. */ -int send_usb_data_only(libusb_device_handle *handle, unsigned char endpoint_out, - unsigned char endpoint_in, unsigned char *cbuf, unsigned int length) { - int ret; - int real_transferred; - int try = 0; +int32_t send_usb_data_only(libusb_device_handle *handle, unsigned char endpoint_out, + unsigned char endpoint_in, unsigned char *cbuf, uint32_t length) { + int32_t ret; + int32_t real_transferred; + int32_t try = 0; do { ret = libusb_bulk_transfer(handle, endpoint_out, cbuf, length, @@ -324,7 +326,7 @@ int send_usb_data_only(libusb_device_handle *handle, unsigned char endpoint_out, // now, swallow up the status, so that things behave nicely... uint32_t received_tag; // -ve is for my errors, 0 is good, +ve is libusb sense status bytes - int status = get_usb_mass_storage_status(handle, endpoint_in, &received_tag); + int32_t status = get_usb_mass_storage_status(handle, endpoint_in, &received_tag); if (status < 0) { WLOG("receiving status failed: %d\n", status); @@ -343,7 +345,7 @@ int send_usb_data_only(libusb_device_handle *handle, unsigned char endpoint_out, return(real_transferred); } -int stlink_q(stlink_t *sl) { +int32_t stlink_q(stlink_t *sl) { struct stlink_libsg* sg = sl->backend_data; // uint8_t cdb_len = 6; // FIXME varies!!! uint8_t cdb_len = 10; // FIXME varies!!! @@ -355,10 +357,10 @@ int stlink_q(stlink_t *sl) { // now wait for our response... // length copied from stlink-usb... - int rx_length = sl->q_len; - int try = 0; - int real_transferred; - int ret; + int32_t rx_length = sl->q_len; + int32_t try = 0; + int32_t real_transferred; + int32_t ret; if (rx_length > 0) { do { @@ -382,7 +384,7 @@ int stlink_q(stlink_t *sl) { uint32_t received_tag; // -ve is for my errors, 0 is good, +ve is libusb sense status bytes - int status = get_usb_mass_storage_status(sg->usb_handle, sg->ep_rep, &received_tag); + int32_t status = get_usb_mass_storage_status(sg->usb_handle, sg->ep_rep, &received_tag); if (status < 0) { WLOG("receiving status failed: %d\n", status); @@ -428,7 +430,7 @@ void stlink_stat(stlink_t *stl, char *txt) { } } -int _stlink_sg_version(stlink_t *stl) { +int32_t _stlink_sg_version(stlink_t *stl) { struct stlink_libsg *sl = stl->backend_data; clear_cdb(sl); sl->cdb_cmd_blk[0] = STLINK_GET_VERSION; @@ -440,7 +442,7 @@ int _stlink_sg_version(stlink_t *stl) { // Get stlink mode: // STLINK_DEV_DFU_MODE || STLINK_DEV_MASS_MODE || STLINK_DEV_DEBUG_MODE // usb dfu || usb mass || jtag or swd -int _stlink_sg_current_mode(stlink_t *stl) { +int32_t _stlink_sg_current_mode(stlink_t *stl) { struct stlink_libsg *sl = stl->backend_data; clear_cdb(sl); sl->cdb_cmd_blk[0] = STLINK_GET_CURRENT_MODE; @@ -453,7 +455,7 @@ int _stlink_sg_current_mode(stlink_t *stl) { } // exit the mass mode and enter the swd debug mode. -int _stlink_sg_enter_swd_mode(stlink_t *sl) { +int32_t _stlink_sg_enter_swd_mode(stlink_t *sl) { struct stlink_libsg *sg = sl->backend_data; clear_cdb(sg); sg->cdb_cmd_blk[1] = STLINK_DEBUG_APIV1_ENTER; @@ -464,7 +466,7 @@ int _stlink_sg_enter_swd_mode(stlink_t *sl) { // exit the mass mode and enter the jtag debug mode. // (jtag is disabled in the discovery's stlink firmware) -int _stlink_sg_enter_jtag_mode(stlink_t *sl) { +int32_t _stlink_sg_enter_jtag_mode(stlink_t *sl) { struct stlink_libsg *sg = sl->backend_data; DLOG("\n*** stlink_enter_jtag_mode ***\n"); clear_cdb(sg); @@ -476,7 +478,7 @@ int _stlink_sg_enter_jtag_mode(stlink_t *sl) { // XXX kernel driver performs reset, the device temporally disappears // Suspect this is no longer the case when we have ignore on? RECHECK -int _stlink_sg_exit_dfu_mode(stlink_t *sl) { +int32_t _stlink_sg_exit_dfu_mode(stlink_t *sl) { struct stlink_libsg *sg = sl->backend_data; DLOG("\n*** stlink_exit_dfu_mode ***\n"); clear_cdb(sg); @@ -529,9 +531,9 @@ int _stlink_sg_exit_dfu_mode(stlink_t *sl) { */ } -int _stlink_sg_core_id(stlink_t *sl) { +int32_t _stlink_sg_core_id(stlink_t *sl) { struct stlink_libsg *sg = sl->backend_data; - int ret; + int32_t ret; clear_cdb(sg); sg->cdb_cmd_blk[1] = STLINK_DEBUG_READCOREID; sl->q_len = 4; @@ -545,7 +547,7 @@ int _stlink_sg_core_id(stlink_t *sl) { } // arm-core reset -> halted state. -int _stlink_sg_reset(stlink_t *sl) { +int32_t _stlink_sg_reset(stlink_t *sl) { struct stlink_libsg *sg = sl->backend_data; clear_cdb(sg); sg->cdb_cmd_blk[1] = STLINK_DEBUG_APIV1_RESETSYS; @@ -566,7 +568,7 @@ int _stlink_sg_reset(stlink_t *sl) { } // arm-core reset -> halted state. -int _stlink_sg_jtag_reset(stlink_t *sl, int value) { +int32_t _stlink_sg_jtag_reset(stlink_t *sl, int32_t value) { struct stlink_libsg *sg = sl->backend_data; clear_cdb(sg); sg->cdb_cmd_blk[1] = STLINK_DEBUG_APIV2_DRIVE_NRST; @@ -582,7 +584,7 @@ int _stlink_sg_jtag_reset(stlink_t *sl, int value) { } // arm-core status: halted or running. -int _stlink_sg_status(stlink_t *sl) { +int32_t _stlink_sg_status(stlink_t *sl) { struct stlink_libsg *sg = sl->backend_data; clear_cdb(sg); sg->cdb_cmd_blk[1] = STLINK_DEBUG_GETSTATUS; @@ -592,7 +594,7 @@ int _stlink_sg_status(stlink_t *sl) { } // force the core into the debug mode -> halted state. -int _stlink_sg_force_debug(stlink_t *sl) { +int32_t _stlink_sg_force_debug(stlink_t *sl) { struct stlink_libsg *sg = sl->backend_data; clear_cdb(sg); sg->cdb_cmd_blk[1] = STLINK_DEBUG_FORCEDEBUG; @@ -606,7 +608,7 @@ int _stlink_sg_force_debug(stlink_t *sl) { } // read all arm-core registers. -int _stlink_sg_read_all_regs(stlink_t *sl, struct stlink_reg *regp) { +int32_t _stlink_sg_read_all_regs(stlink_t *sl, struct stlink_reg *regp) { struct stlink_libsg *sg = sl->backend_data; clear_cdb(sg); @@ -622,7 +624,7 @@ int _stlink_sg_read_all_regs(stlink_t *sl, struct stlink_reg *regp) { // 0-3 | 4-7 | ... | 60-63 | 64-67 | 68-71 | 72-75 | 76-79 | 80-83 // r0 | r1 | ... | r15 | xpsr | main_sp | process_sp | rw | rw2 - for (int i = 0; i < 16; i++) { + for (int32_t i = 0; i < 16; i++) { regp->r[i] = read_uint32(sl->q_buf, 4 * i); if (sl->verbose > 1) { DLOG("r%2d = 0x%08x\n", i, regp->r[i]); } @@ -649,7 +651,7 @@ int _stlink_sg_read_all_regs(stlink_t *sl, struct stlink_reg *regp) { // 0 | 1 | ... | 15 | 16 | 17 | 18 | 19 | 20 // r0 | r1 | ... | r15 | xpsr | main_sp | process_sp | rw | rw2 -int _stlink_sg_read_reg(stlink_t *sl, int r_idx, struct stlink_reg *regp) { +int32_t _stlink_sg_read_reg(stlink_t *sl, int32_t r_idx, struct stlink_reg *regp) { struct stlink_libsg *sg = sl->backend_data; clear_cdb(sg); sg->cdb_cmd_blk[1] = STLINK_DEBUG_APIV1_READREG; @@ -694,7 +696,7 @@ int _stlink_sg_read_reg(stlink_t *sl, int r_idx, struct stlink_reg *regp) { // 0 | 1 | ... | 15 | 16 | 17 | 18 | 19 | 20 // r0 | r1 | ... | r15 | xpsr | main_sp | process_sp | rw | rw2 -int _stlink_sg_write_reg(stlink_t *sl, uint32_t reg, int idx) { +int32_t _stlink_sg_write_reg(stlink_t *sl, uint32_t reg, int32_t idx) { struct stlink_libsg *sg = sl->backend_data; clear_cdb(sg); sg->cdb_cmd_blk[1] = STLINK_DEBUG_APIV1_WRITEREG; @@ -730,7 +732,7 @@ void stlink_write_dreg(stlink_t *sl, uint32_t reg, uint32_t addr) { } // force the core exit the debug mode. -int _stlink_sg_run(stlink_t *sl, enum run_type type) { +int32_t _stlink_sg_run(stlink_t *sl, enum run_type type) { struct stlink_libsg *sg = sl->backend_data; (void)(type); //unused clear_cdb(sg); @@ -746,7 +748,7 @@ int _stlink_sg_run(stlink_t *sl, enum run_type type) { } // step the arm-core. -int _stlink_sg_step(stlink_t *sl) { +int32_t _stlink_sg_step(stlink_t *sl) { struct stlink_libsg *sg = sl->backend_data; clear_cdb(sg); sg->cdb_cmd_blk[1] = STLINK_DEBUG_STEPCORE; @@ -761,7 +763,7 @@ int _stlink_sg_step(stlink_t *sl) { // TODO: test and make delegate! // see Cortex-M3 Technical Reference Manual -void stlink_set_hw_bp(stlink_t *sl, int fp_nr, uint32_t addr, int fp) { +void stlink_set_hw_bp(stlink_t *sl, int32_t fp_nr, uint32_t addr, int32_t fp) { DLOG("\n*** stlink_set_hw_bp ***\n"); struct stlink_libsg *sg = sl->backend_data; clear_cdb(sg); @@ -779,7 +781,7 @@ void stlink_set_hw_bp(stlink_t *sl, int fp_nr, uint32_t addr, int fp) { } // TODO: test and make delegate! -void stlink_clr_hw_bp(stlink_t *sl, int fp_nr) { +void stlink_clr_hw_bp(stlink_t *sl, int32_t fp_nr) { struct stlink_libsg *sg = sl->backend_data; DLOG("\n*** stlink_clr_hw_bp ***\n"); clear_cdb(sg); @@ -792,7 +794,7 @@ void stlink_clr_hw_bp(stlink_t *sl, int fp_nr) { } // read a "len" bytes to the sl->q_buf from the memory, max 6kB (6144 bytes) -int _stlink_sg_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { +int32_t _stlink_sg_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { struct stlink_libsg *sg = sl->backend_data; clear_cdb(sg); sg->cdb_cmd_blk[1] = STLINK_DEBUG_READMEM_32BIT; @@ -816,9 +818,9 @@ int _stlink_sg_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { } // write a "len" bytes from the sl->q_buf to the memory, max 64 Bytes. -int _stlink_sg_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len) { +int32_t _stlink_sg_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len) { struct stlink_libsg *sg = sl->backend_data; - int ret; + int32_t ret; clear_cdb(sg); sg->cdb_cmd_blk[1] = STLINK_DEBUG_WRITEMEM_8BIT; @@ -844,9 +846,9 @@ int _stlink_sg_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len) { } // write a "len" bytes from the sl->q_buf to the memory, max Q_BUF_LEN bytes. -int _stlink_sg_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { +int32_t _stlink_sg_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { struct stlink_libsg *sg = sl->backend_data; - int ret; + int32_t ret; clear_cdb(sg); sg->cdb_cmd_blk[1] = STLINK_DEBUG_WRITEMEM_32BIT; @@ -872,7 +874,7 @@ int _stlink_sg_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { } // write one DWORD data to memory -int _stlink_sg_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data) { +int32_t _stlink_sg_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data) { struct stlink_libsg *sg = sl->backend_data; clear_cdb(sg); sg->cdb_cmd_blk[1] = STLINK_DEBUG_APIV2_WRITEDEBUGREG; @@ -884,7 +886,7 @@ int _stlink_sg_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data) { } // read one DWORD data from memory -int _stlink_sg_read_debug32(stlink_t *sl, uint32_t addr, uint32_t *data) { +int32_t _stlink_sg_read_debug32(stlink_t *sl, uint32_t addr, uint32_t *data) { struct stlink_libsg *sg = sl->backend_data; clear_cdb(sg); sg->cdb_cmd_blk[1] = STLINK_DEBUG_APIV2_READDEBUGREG; @@ -899,7 +901,7 @@ int _stlink_sg_read_debug32(stlink_t *sl, uint32_t addr, uint32_t *data) { } // exit the jtag or swd mode and enter the mass mode. -int _stlink_sg_exit_debug_mode(stlink_t *stl) { +int32_t _stlink_sg_exit_debug_mode(stlink_t *stl) { if (stl) { struct stlink_libsg* sl = stl->backend_data; clear_cdb(sl); @@ -950,7 +952,7 @@ static stlink_backend_t _stlink_sg_backend = { NULL, // trace_read }; -static stlink_t* stlink_open(const int verbose) { +static stlink_t* stlink_open(const int32_t verbose) { stlink_t *sl = malloc(sizeof(stlink_t)); struct stlink_libsg *slsg = malloc(sizeof(struct stlink_libsg)); @@ -993,7 +995,7 @@ static stlink_t* stlink_open(const int verbose) { // TODO: Could read the interface config descriptor, and assert lots of the assumptions // assumption: numInterfaces is always 1... if (libusb_kernel_driver_active(slsg->usb_handle, 0) == 1) { - int r = libusb_detach_kernel_driver(slsg->usb_handle, 0); + int32_t r = libusb_detach_kernel_driver(slsg->usb_handle, 0); if (r < 0) { WLOG("libusb_detach_kernel_driver(() error %s\n", strerror(-r)); @@ -1007,7 +1009,7 @@ static stlink_t* stlink_open(const int verbose) { DLOG("Kernel driver was successfully detached\n"); } - int config; + int32_t config; if (libusb_get_configuration(slsg->usb_handle, &config)) { /* this may fail for a previous configured device */ @@ -1062,7 +1064,7 @@ static stlink_t* stlink_open(const int verbose) { } -stlink_t* stlink_v1_open_inner(const int verbose) { +stlink_t* stlink_v1_open_inner(const int32_t verbose) { ugly_init(verbose); stlink_t *sl = stlink_open(verbose); @@ -1105,7 +1107,7 @@ stlink_t* stlink_v1_open_inner(const int verbose) { return(sl); } -stlink_t* stlink_v1_open(const int verbose, int reset) { +stlink_t* stlink_v1_open(const int32_t verbose, int32_t reset) { stlink_t *sl = stlink_v1_open_inner(verbose); if (sl == NULL) { return(NULL); } diff --git a/src/stlink-lib/sg.h b/src/stlink-lib/sg.h index 5ba809f59..d4792c49a 100644 --- a/src/stlink-lib/sg.h +++ b/src/stlink-lib/sg.h @@ -6,8 +6,10 @@ #ifndef SG_H #define SG_H +#include + #include -#include +#include "libusb_settings.h" /* Device access */ #define RDWR 0 @@ -35,15 +37,15 @@ struct stlink_libsg { libusb_context* libusb_ctx; libusb_device_handle *usb_handle; - unsigned ep_rep; - unsigned ep_req; + uint32_t ep_rep; + uint32_t ep_req; - int sg_fd; - int do_scsi_pt_err; + int32_t sg_fd; + int32_t do_scsi_pt_err; unsigned char cdb_cmd_blk[CDB_SL]; - int q_data_dir; // Q_DATA_IN, Q_DATA_OUT + int32_t q_data_dir; // Q_DATA_IN, Q_DATA_OUT // the start of the query data in the device memory space uint32_t q_addr; @@ -54,6 +56,6 @@ struct stlink_libsg { struct stlink_reg reg; }; -stlink_t* stlink_v1_open(const int verbose, int reset); +stlink_t* stlink_v1_open(const int32_t verbose, int32_t reset); #endif // SG_H diff --git a/src/stlink-lib/usb.c b/src/stlink-lib/usb.c index 2e99e82be..d404c2e94 100644 --- a/src/stlink-lib/usb.c +++ b/src/stlink-lib/usb.c @@ -1,8 +1,8 @@ +#include +#include #include #include #include -#include -#include #if !defined(_MSC_VER) #include @@ -17,7 +17,7 @@ #endif #include -#include +#include "helper.h" #include "usb.h" enum SCSI_Generic_Direction {SG_DXFER_TO_DEV = 0, SG_DXFER_FROM_DEV = 0x80}; @@ -26,11 +26,11 @@ static inline uint32_t le_to_h_u32(const uint8_t* buf) { return((uint32_t)((uint32_t)buf[0] | (uint32_t)buf[1] << 8 | (uint32_t)buf[2] << 16 | (uint32_t)buf[3] << 24)); } -static int _stlink_match_speed_map(const uint32_t *map, unsigned int map_size, uint32_t khz) { - unsigned int i; - int speed_index = -1; - int speed_diff = INT_MAX; - int last_valid_speed = -1; +static int32_t _stlink_match_speed_map(const uint32_t *map, uint32_t map_size, uint32_t khz) { + uint32_t i; + int32_t speed_index = -1; + int32_t speed_diff = INT_MAX; + int32_t last_valid_speed = -1; bool match = true; for (i = 0; i < map_size; i++) { @@ -42,7 +42,7 @@ static int _stlink_match_speed_map(const uint32_t *map, unsigned int map_size, u speed_index = i; break; } else { - int current_diff = khz - map[i]; + int32_t current_diff = khz - map[i]; // get abs value for comparison current_diff = (current_diff > 0) ? current_diff : -current_diff; @@ -83,26 +83,26 @@ void _stlink_usb_close(stlink_t* sl) { } } -ssize_t send_recv(struct stlink_libusb* handle, int terminate, +ssize_t send_recv(struct stlink_libusb* handle, int32_t terminate, unsigned char* txbuf, size_t txsize, unsigned char* rxbuf, - size_t rxsize, int check_error, const char *cmd) { + size_t rxsize, int32_t check_error, const char *cmd) { // Note: txbuf and rxbuf can point to the same area - int res, t, retry = 0; + int32_t res, t, retry = 0; while (1) { res = 0; - t = libusb_bulk_transfer(handle->usb_handle, handle->ep_req, txbuf, (int)txsize, &res, 3000); + t = libusb_bulk_transfer(handle->usb_handle, handle->ep_req, txbuf, (int32_t)txsize, &res, 3000); if (t) { ELOG("%s send request failed: %s\n", cmd, libusb_error_name(t)); return(-1); } else if ((size_t)res != txsize) { ELOG("%s send request wrote %u bytes, instead of %u\n", - cmd, (unsigned int)res, (unsigned int)txsize); + cmd, (uint32_t)res, (uint32_t)txsize); } if (rxsize != 0) { - t = libusb_bulk_transfer(handle->usb_handle, handle->ep_rep, rxbuf, (int)rxsize, &res, 3000); + t = libusb_bulk_transfer(handle->usb_handle, handle->ep_rep, rxbuf, (int32_t)rxsize, &res, 3000); if (t) { ELOG("%s read reply failed: %s\n", cmd, libusb_error_name(t)); @@ -116,7 +116,7 @@ ssize_t send_recv(struct stlink_libusb* handle, int terminate, case STLINK_DEBUG_ERR_AP_WAIT: case STLINK_DEBUG_ERR_DP_WAIT: if (check_error == CMD_CHECK_RETRY && retry < 3) { - unsigned int delay_us = (1<backend_data; unsigned char* const cmd = sl->c_buf; - int i = 0; + int32_t i = 0; memset(cmd, 0, sizeof(sl->c_buf)); if (slu->protocoll == 1) { @@ -189,13 +189,13 @@ static int fill_command(stlink_t * sl, enum SCSI_Generic_Direction dir, uint32_t return(i); } -int _stlink_usb_version(stlink_t *sl) { +int32_t _stlink_usb_version(stlink_t *sl) { struct stlink_libusb * const slu = sl->backend_data; unsigned char* const data = sl->q_buf; unsigned char* const cmd = sl->c_buf; ssize_t size; uint32_t rep_len; - int i; + int32_t i; if (sl->version.stlink_v == 3) { // STLINK-V3 version is determined by another command @@ -219,9 +219,9 @@ int32_t _stlink_usb_target_voltage(stlink_t *sl) { unsigned char* const cmd = sl->c_buf; ssize_t size; uint32_t rep_len = 8; - int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); + int32_t i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); uint32_t factor, reading; - int voltage; + int32_t voltage; cmd[i++] = STLINK_GET_TARGET_VOLTAGE; @@ -238,14 +238,14 @@ int32_t _stlink_usb_target_voltage(stlink_t *sl) { return(voltage); } -int _stlink_usb_read_debug32(stlink_t *sl, uint32_t addr, uint32_t *data) { +int32_t _stlink_usb_read_debug32(stlink_t *sl, uint32_t addr, uint32_t *data) { struct stlink_libusb * const slu = sl->backend_data; unsigned char* const rdata = sl->q_buf; unsigned char* const cmd = sl->c_buf; ssize_t size; - const int rep_len = 8; + const int32_t rep_len = 8; - int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); + int32_t i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); cmd[i++] = STLINK_DEBUG_COMMAND; cmd[i++] = STLINK_DEBUG_APIV2_READDEBUGREG; write_uint32(&cmd[i], addr); @@ -260,14 +260,14 @@ int _stlink_usb_read_debug32(stlink_t *sl, uint32_t addr, uint32_t *data) { return(0); } -int _stlink_usb_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data) { +int32_t _stlink_usb_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data) { struct stlink_libusb * const slu = sl->backend_data; unsigned char* const rdata = sl->q_buf; unsigned char* const cmd = sl->c_buf; ssize_t size; - const int rep_len = 2; + const int32_t rep_len = 2; - int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); + int32_t i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); cmd[i++] = STLINK_DEBUG_COMMAND; cmd[i++] = STLINK_DEBUG_APIV2_WRITEDEBUGREG; write_uint32(&cmd[i], addr); @@ -277,13 +277,13 @@ int _stlink_usb_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data) { return(size<0?-1:0); } -int _stlink_usb_get_rw_status(stlink_t *sl) { +int32_t _stlink_usb_get_rw_status(stlink_t *sl) { if (sl->version.jtag_api == STLINK_JTAG_API_V1) { return(0); } unsigned char* const rdata = sl->q_buf; struct stlink_libusb * const slu = sl->backend_data; unsigned char* const cmd = sl->c_buf; - int i; + int32_t i; int16_t ret = 0; i = fill_command(sl, SG_DXFER_FROM_DEV, 12); @@ -300,11 +300,11 @@ int _stlink_usb_get_rw_status(stlink_t *sl) { return(ret<0?-1:0); } -int _stlink_usb_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { +int32_t _stlink_usb_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { struct stlink_libusb * const slu = sl->backend_data; unsigned char* const data = sl->q_buf; unsigned char* const cmd = sl->c_buf; - int i, ret; + int32_t i, ret; i = fill_command(sl, SG_DXFER_TO_DEV, len); cmd[i++] = STLINK_DEBUG_COMMAND; @@ -322,11 +322,11 @@ int _stlink_usb_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { return(_stlink_usb_get_rw_status(sl)); } -int _stlink_usb_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len) { +int32_t _stlink_usb_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len) { struct stlink_libusb * const slu = sl->backend_data; unsigned char* const data = sl->q_buf; unsigned char* const cmd = sl->c_buf; - int i, ret; + int32_t i, ret; if ((sl->version.jtag_api < STLINK_JTAG_API_V3 && len > 64) || (sl->version.jtag_api >= STLINK_JTAG_API_V3 && len > 512)) { @@ -351,13 +351,13 @@ int _stlink_usb_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len) { } -int _stlink_usb_current_mode(stlink_t * sl) { +int32_t _stlink_usb_current_mode(stlink_t * sl) { struct stlink_libusb * const slu = sl->backend_data; unsigned char* const cmd = sl->c_buf; unsigned char* const data = sl->q_buf; ssize_t size; - int rep_len = 2; - int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); + int32_t rep_len = 2; + int32_t i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); cmd[i++] = STLINK_GET_CURRENT_MODE; size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_NO, "GET_CURRENT_MODE"); @@ -369,13 +369,13 @@ int _stlink_usb_current_mode(stlink_t * sl) { return(sl->q_buf[0]); } -int _stlink_usb_core_id(stlink_t * sl) { +int32_t _stlink_usb_core_id(stlink_t * sl) { struct stlink_libusb * const slu = sl->backend_data; unsigned char* const cmd = sl->c_buf; unsigned char* const data = sl->q_buf; ssize_t size; - int offset, rep_len = sl->version.jtag_api == STLINK_JTAG_API_V1 ? 4 : 12; - int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); + int32_t offset, rep_len = sl->version.jtag_api == STLINK_JTAG_API_V1 ? 4 : 12; + int32_t i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); cmd[i++] = STLINK_DEBUG_COMMAND; @@ -398,8 +398,8 @@ int _stlink_usb_core_id(stlink_t * sl) { return(0); } -int _stlink_usb_status_v2(stlink_t *sl) { - int result; +int32_t _stlink_usb_status_v2(stlink_t *sl) { + int32_t result; uint32_t status = 0; result = _stlink_usb_read_debug32(sl, STLINK_REG_DHCSR, &status); @@ -420,15 +420,15 @@ int _stlink_usb_status_v2(stlink_t *sl) { return(result); } -int _stlink_usb_status(stlink_t * sl) { +int32_t _stlink_usb_status(stlink_t * sl) { if (sl->version.jtag_api != STLINK_JTAG_API_V1) { return(_stlink_usb_status_v2(sl)); } struct stlink_libusb * const slu = sl->backend_data; unsigned char* const data = sl->q_buf; unsigned char* const cmd = sl->c_buf; ssize_t size; - int rep_len = 2; - int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); + int32_t rep_len = 2; + int32_t i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); cmd[i++] = STLINK_DEBUG_COMMAND; cmd[i++] = STLINK_DEBUG_GETSTATUS; @@ -449,10 +449,10 @@ int _stlink_usb_status(stlink_t * sl) { return(size<0?-1:0); } -int _stlink_usb_force_debug(stlink_t *sl) { +int32_t _stlink_usb_force_debug(stlink_t *sl) { struct stlink_libusb *slu = sl->backend_data; - int res; + int32_t res; if (sl->version.jtag_api != STLINK_JTAG_API_V1) { res = _stlink_usb_write_debug32(sl, STLINK_REG_DHCSR, STLINK_REG_DHCSR_DBGKEY | STLINK_REG_DHCSR_C_HALT | STLINK_REG_DHCSR_C_DEBUGEN); @@ -462,8 +462,8 @@ int _stlink_usb_force_debug(stlink_t *sl) { unsigned char* const data = sl->q_buf; unsigned char* const cmd = sl->c_buf; ssize_t size; - int rep_len = 2; - int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); + int32_t rep_len = 2; + int32_t i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); cmd[i++] = STLINK_DEBUG_COMMAND; cmd[i++] = STLINK_DEBUG_FORCEDEBUG; @@ -472,13 +472,13 @@ int _stlink_usb_force_debug(stlink_t *sl) { return(size<0?-1:0); } -int _stlink_usb_enter_swd_mode(stlink_t * sl) { +int32_t _stlink_usb_enter_swd_mode(stlink_t * sl) { struct stlink_libusb * const slu = sl->backend_data; unsigned char* const cmd = sl->c_buf; ssize_t size; unsigned char* const data = sl->q_buf; const uint32_t rep_len = sl->version.jtag_api == STLINK_JTAG_API_V1 ? 0 : 2; - int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); + int32_t i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); cmd[i++] = STLINK_DEBUG_COMMAND; // select correct API-Version for entering SWD mode: V1 API (0x20) or V2 API (0x30). @@ -489,11 +489,11 @@ int _stlink_usb_enter_swd_mode(stlink_t * sl) { return(size<0?-1:0); } -int _stlink_usb_exit_dfu_mode(stlink_t* sl) { +int32_t _stlink_usb_exit_dfu_mode(stlink_t* sl) { struct stlink_libusb * const slu = sl->backend_data; unsigned char* const cmd = sl->c_buf; ssize_t size; - int i = fill_command(sl, SG_DXFER_FROM_DEV, 0); + int32_t i = fill_command(sl, SG_DXFER_FROM_DEV, 0); cmd[i++] = STLINK_DFU_COMMAND; cmd[i++] = STLINK_DFU_EXIT; @@ -503,12 +503,12 @@ int _stlink_usb_exit_dfu_mode(stlink_t* sl) { } -int _stlink_usb_reset(stlink_t * sl) { +int32_t _stlink_usb_reset(stlink_t * sl) { struct stlink_libusb * const slu = sl->backend_data; unsigned char* const data = sl->q_buf; unsigned char* const cmd = sl->c_buf; ssize_t size; - int i, rep_len = 2; + int32_t i, rep_len = 2; // send reset command i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); @@ -525,13 +525,13 @@ int _stlink_usb_reset(stlink_t * sl) { return(size<0?-1:0); } -int _stlink_usb_jtag_reset(stlink_t * sl, int value) { +int32_t _stlink_usb_jtag_reset(stlink_t * sl, int32_t value) { struct stlink_libusb * const slu = sl->backend_data; unsigned char* const data = sl->q_buf; unsigned char* const cmd = sl->c_buf; ssize_t size; - int rep_len = 2; - int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); + int32_t rep_len = 2; + int32_t i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); cmd[i++] = STLINK_DEBUG_COMMAND; cmd[i++] = STLINK_DEBUG_APIV2_DRIVE_NRST; @@ -542,7 +542,7 @@ int _stlink_usb_jtag_reset(stlink_t * sl, int value) { } -int _stlink_usb_step(stlink_t* sl) { +int32_t _stlink_usb_step(stlink_t* sl) { struct stlink_libusb * const slu = sl->backend_data; if (sl->version.jtag_api != STLINK_JTAG_API_V1) { @@ -558,8 +558,8 @@ int _stlink_usb_step(stlink_t* sl) { unsigned char* const data = sl->q_buf; unsigned char* const cmd = sl->c_buf; ssize_t size; - int rep_len = 2; - int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); + int32_t rep_len = 2; + int32_t i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); cmd[i++] = STLINK_DEBUG_COMMAND; cmd[i++] = STLINK_DEBUG_STEPCORE; @@ -573,10 +573,10 @@ int _stlink_usb_step(stlink_t* sl) { * @param sl * @param type */ -int _stlink_usb_run(stlink_t* sl, enum run_type type) { +int32_t _stlink_usb_run(stlink_t* sl, enum run_type type) { struct stlink_libusb * const slu = sl->backend_data; - int res; + int32_t res; if (sl->version.jtag_api != STLINK_JTAG_API_V1) { res = _stlink_usb_write_debug32(sl, STLINK_REG_DHCSR, @@ -589,8 +589,8 @@ int _stlink_usb_run(stlink_t* sl, enum run_type type) { unsigned char* const data = sl->q_buf; unsigned char* const cmd = sl->c_buf; ssize_t size; - int rep_len = 2; - int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); + int32_t rep_len = 2; + int32_t i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); cmd[i++] = STLINK_DEBUG_COMMAND; cmd[i++] = STLINK_DEBUG_RUNCORE; @@ -599,20 +599,20 @@ int _stlink_usb_run(stlink_t* sl, enum run_type type) { return(size<0?-1:0); } -int _stlink_usb_set_swdclk(stlink_t* sl, int clk_freq) { +int32_t _stlink_usb_set_swdclk(stlink_t* sl, int32_t clk_freq) { struct stlink_libusb * const slu = sl->backend_data; unsigned char* const data = sl->q_buf; unsigned char* const cmd = sl->c_buf; ssize_t size; - int rep_len = 2; - int i; + int32_t rep_len = 2; + int32_t i; // clock speed only supported by stlink/v2 and for firmware >= 22 if (sl->version.stlink_v == 2 && sl->version.jtag_v >= 22) { uint16_t clk_divisor; if (clk_freq) { const uint32_t map[] = {5, 15, 25, 50, 100, 125, 240, 480, 950, 1200, 1800, 4000}; - int speed_index = _stlink_match_speed_map(map, STLINK_ARRAY_SIZE(map), clk_freq); + int32_t speed_index = _stlink_match_speed_map(map, STLINK_ARRAY_SIZE(map), clk_freq); switch (map[speed_index]) { case 5: clk_divisor = STLINK_SWDCLK_5KHZ_DIVISOR; break; case 15: clk_divisor = STLINK_SWDCLK_15KHZ_DIVISOR; break; @@ -641,7 +641,7 @@ int _stlink_usb_set_swdclk(stlink_t* sl, int clk_freq) { return(size<0?-1:0); } else if (sl->version.stlink_v == 3) { - int speed_index; + int32_t speed_index; uint32_t map[STLINK_V3_MAX_FREQ_NB]; i = fill_command(sl, SG_DXFER_FROM_DEV, 16); @@ -654,7 +654,7 @@ int _stlink_usb_set_swdclk(stlink_t* sl, int clk_freq) { return(-1); } - int speeds_size = data[8]; + int32_t speeds_size = data[8]; if (speeds_size > STLINK_V3_MAX_FREQ_NB) { speeds_size = STLINK_V3_MAX_FREQ_NB; } @@ -688,11 +688,11 @@ int _stlink_usb_set_swdclk(stlink_t* sl, int clk_freq) { return(-1); } -int _stlink_usb_exit_debug_mode(stlink_t *sl) { +int32_t _stlink_usb_exit_debug_mode(stlink_t *sl) { struct stlink_libusb * const slu = sl->backend_data; unsigned char* const cmd = sl->c_buf; ssize_t size; - int i = fill_command(sl, SG_DXFER_FROM_DEV, 0); + int32_t i = fill_command(sl, SG_DXFER_FROM_DEV, 0); cmd[i++] = STLINK_DEBUG_COMMAND; cmd[i++] = STLINK_DEBUG_EXIT; @@ -702,12 +702,12 @@ int _stlink_usb_exit_debug_mode(stlink_t *sl) { return(size<0?-1:0); } -int _stlink_usb_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { +int32_t _stlink_usb_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { struct stlink_libusb * const slu = sl->backend_data; unsigned char* const data = sl->q_buf; unsigned char* const cmd = sl->c_buf; ssize_t size; - int i = fill_command(sl, SG_DXFER_FROM_DEV, len); + int32_t i = fill_command(sl, SG_DXFER_FROM_DEV, len); cmd[i++] = STLINK_DEBUG_COMMAND; cmd[i++] = STLINK_DEBUG_READMEM_32BIT; @@ -719,19 +719,19 @@ int _stlink_usb_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { return(-1); } - sl->q_len = (int)size; + sl->q_len = (int32_t)size; stlink_print_data(sl); return(0); } -int _stlink_usb_read_all_regs(stlink_t *sl, struct stlink_reg *regp) { +int32_t _stlink_usb_read_all_regs(stlink_t *sl, struct stlink_reg *regp) { struct stlink_libusb * const slu = sl->backend_data; unsigned char* const cmd = sl->c_buf; unsigned char* const data = sl->q_buf; ssize_t size; uint32_t rep_len = sl->version.jtag_api == STLINK_JTAG_API_V1 ? 84 : 88; - int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); + int32_t i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); cmd[i++] = STLINK_DEBUG_COMMAND; @@ -749,8 +749,8 @@ int _stlink_usb_read_all_regs(stlink_t *sl, struct stlink_reg *regp) { /* V1: regs data from offset 0 */ /* V2: status at offset 0, regs data from offset 4 */ - int reg_offset = sl->version.jtag_api == STLINK_JTAG_API_V1 ? 0 : 4; - sl->q_len = (int)size; + int32_t reg_offset = sl->version.jtag_api == STLINK_JTAG_API_V1 ? 0 : 4; + sl->q_len = (int32_t)size; stlink_print_data(sl); for (i = 0; i < 16; i++) regp->r[i] = read_uint32(sl->q_buf, reg_offset + i * 4); @@ -772,15 +772,15 @@ int _stlink_usb_read_all_regs(stlink_t *sl, struct stlink_reg *regp) { return(0); } -int _stlink_usb_read_reg(stlink_t *sl, int r_idx, struct stlink_reg *regp) { +int32_t _stlink_usb_read_reg(stlink_t *sl, int32_t r_idx, struct stlink_reg *regp) { struct stlink_libusb * const slu = sl->backend_data; unsigned char* const data = sl->q_buf; unsigned char* const cmd = sl->c_buf; ssize_t size; uint32_t r; uint32_t rep_len = sl->version.jtag_api == STLINK_JTAG_API_V1 ? 4 : 8; - int reg_offset = sl->version.jtag_api == STLINK_JTAG_API_V1 ? 0 : 4; - int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); + int32_t reg_offset = sl->version.jtag_api == STLINK_JTAG_API_V1 ? 0 : 4; + int32_t i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); cmd[i++] = STLINK_DEBUG_COMMAND; @@ -797,7 +797,7 @@ int _stlink_usb_read_reg(stlink_t *sl, int r_idx, struct stlink_reg *regp) { return(-1); } - sl->q_len = (int)size; + sl->q_len = (int32_t)size; stlink_print_data(sl); r = read_uint32(sl->q_buf, reg_offset); DLOG("r_idx (%2d) = 0x%08x\n", r_idx, r); @@ -826,13 +826,13 @@ int _stlink_usb_read_reg(stlink_t *sl, int r_idx, struct stlink_reg *regp) { } /* See section C1.6 of the ARMv7-M Architecture Reference Manual */ -int _stlink_usb_read_unsupported_reg(stlink_t *sl, int r_idx, struct stlink_reg *regp) { +int32_t _stlink_usb_read_unsupported_reg(stlink_t *sl, int32_t r_idx, struct stlink_reg *regp) { uint32_t r; - int ret; + int32_t ret; sl->q_buf[0] = (unsigned char)r_idx; - for (int i = 1; i < 4; i++) sl->q_buf[i] = 0; + for (int32_t i = 1; i < 4; i++) sl->q_buf[i] = 0; ret = _stlink_usb_write_mem32(sl, STLINK_REG_DCRSR, 4); @@ -863,8 +863,8 @@ int _stlink_usb_read_unsupported_reg(stlink_t *sl, int r_idx, struct stlink_reg return(0); } -int _stlink_usb_read_all_unsupported_regs(stlink_t *sl, struct stlink_reg *regp) { - int ret; +int32_t _stlink_usb_read_all_unsupported_regs(stlink_t *sl, struct stlink_reg *regp) { + int32_t ret; ret = _stlink_usb_read_unsupported_reg(sl, 0x14, regp); @@ -874,7 +874,7 @@ int _stlink_usb_read_all_unsupported_regs(stlink_t *sl, struct stlink_reg *regp) if (ret == -1) { return(ret); } - for (int i = 0; i < 32; i++) { + for (int32_t i = 0; i < 32; i++) { ret = _stlink_usb_read_unsupported_reg(sl, 0x40 + i, regp); if (ret == -1) { return(ret); } @@ -884,8 +884,8 @@ int _stlink_usb_read_all_unsupported_regs(stlink_t *sl, struct stlink_reg *regp) } /* See section C1.6 of the ARMv7-M Architecture Reference Manual */ -int _stlink_usb_write_unsupported_reg(stlink_t *sl, uint32_t val, int r_idx, struct stlink_reg *regp) { - int ret; +int32_t _stlink_usb_write_unsupported_reg(stlink_t *sl, uint32_t val, int32_t r_idx, struct stlink_reg *regp) { + int32_t ret; if (r_idx >= 0x1C && r_idx <= 0x1F) { // primask, basepri, faultmask, or control /* These are held in the same register */ @@ -939,13 +939,13 @@ int _stlink_usb_write_unsupported_reg(stlink_t *sl, uint32_t val, int r_idx, str return(_stlink_usb_write_mem32(sl, STLINK_REG_DCRSR, 4)); } -int _stlink_usb_write_reg(stlink_t *sl, uint32_t reg, int idx) { +int32_t _stlink_usb_write_reg(stlink_t *sl, uint32_t reg, int32_t idx) { struct stlink_libusb * const slu = sl->backend_data; unsigned char* const data = sl->q_buf; unsigned char* const cmd = sl->c_buf; ssize_t size; uint32_t rep_len = 2; - int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); + int32_t i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); cmd[i++] = STLINK_DEBUG_COMMAND; @@ -962,14 +962,14 @@ int _stlink_usb_write_reg(stlink_t *sl, uint32_t reg, int idx) { return(size<0?-1:0); } -int _stlink_usb_enable_trace(stlink_t* sl, uint32_t frequency) { +int32_t _stlink_usb_enable_trace(stlink_t* sl, uint32_t frequency) { struct stlink_libusb * const slu = sl->backend_data; unsigned char* const data = sl->q_buf; unsigned char* const cmd = sl->c_buf; ssize_t size; uint32_t rep_len = 2; - int i = fill_command(sl, SG_DXFER_TO_DEV, rep_len); + int32_t i = fill_command(sl, SG_DXFER_TO_DEV, rep_len); cmd[i++] = STLINK_DEBUG_COMMAND; cmd[i++] = STLINK_DEBUG_APIV2_START_TRACE_RX; write_uint16(&cmd[i + 0], 2 * STLINK_TRACE_BUF_LEN); @@ -980,14 +980,14 @@ int _stlink_usb_enable_trace(stlink_t* sl, uint32_t frequency) { return(size<0?-1:0); } -int _stlink_usb_disable_trace(stlink_t* sl) { +int32_t _stlink_usb_disable_trace(stlink_t* sl) { struct stlink_libusb * const slu = sl->backend_data; unsigned char* const data = sl->q_buf; unsigned char* const cmd = sl->c_buf; ssize_t size; uint32_t rep_len = 2; - int i = fill_command(sl, SG_DXFER_TO_DEV, rep_len); + int32_t i = fill_command(sl, SG_DXFER_TO_DEV, rep_len); cmd[i++] = STLINK_DEBUG_COMMAND; cmd[i++] = STLINK_DEBUG_APIV2_STOP_TRACE_RX; @@ -996,12 +996,12 @@ int _stlink_usb_disable_trace(stlink_t* sl) { return(size<0?-1:0); } -int _stlink_usb_read_trace(stlink_t* sl, uint8_t* buf, size_t size) { +int32_t _stlink_usb_read_trace(stlink_t* sl, uint8_t* buf, size_t size) { struct stlink_libusb * const slu = sl->backend_data; unsigned char* const data = sl->q_buf; unsigned char* const cmd = sl->c_buf; uint32_t rep_len = 2; - int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); + int32_t i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); cmd[i++] = STLINK_DEBUG_COMMAND; cmd[i++] = STLINK_DEBUG_APIV2_GET_TRACE_NB; @@ -1010,7 +1010,7 @@ int _stlink_usb_read_trace(stlink_t* sl, uint8_t* buf, size_t size) { if (send_size < 0) { return(-1); } else if (send_size != 2) { - ELOG("STLINK_DEBUG_APIV2_GET_TRACE_NB reply size %d\n", (int)send_size); + ELOG("STLINK_DEBUG_APIV2_GET_TRACE_NB reply size %d\n", (int32_t)send_size); return(-1); } @@ -1022,10 +1022,10 @@ int _stlink_usb_read_trace(stlink_t* sl, uint8_t* buf, size_t size) { } if (trace_count != 0) { - int res = 0; - int t = libusb_bulk_transfer(slu->usb_handle, slu->ep_trace, buf, trace_count, &res, 3000); + int32_t res = 0; + int32_t t = libusb_bulk_transfer(slu->usb_handle, slu->ep_trace, buf, trace_count, &res, 3000); - if (t || res != (int)trace_count) { + if (t || res != (int32_t)trace_count) { ELOG("read_trace read error %d\n", t); return(-1); } @@ -1075,7 +1075,7 @@ size_t stlink_serial(struct libusb_device_handle *handle, struct libusb_device_d serial[0] = '\0'; /* get the LANGID from String Descriptor Zero */ - int ret = libusb_get_string_descriptor(handle, 0, 0, desc_serial, sizeof(desc_serial)); + int32_t ret = libusb_get_string_descriptor(handle, 0, 0, desc_serial, sizeof(desc_serial)); if (ret < 4) return 0; uint32_t langid = desc_serial[2] | (desc_serial[3] << 8); @@ -1094,7 +1094,7 @@ size_t stlink_serial(struct libusb_device_handle *handle, struct libusb_device_d if (ret < 0) return 0; } else if (len == ((STLINK_SERIAL_LENGTH / 2 + 1) * 2)) { /* len == 26 */ /* fix-up the buggy serial */ - for (unsigned int i = 0; i < STLINK_SERIAL_LENGTH; i += 2) + for (uint32_t i = 0; i < STLINK_SERIAL_LENGTH; i += 2) sprintf(serial + i, "%02X", desc_serial[i + 2]); serial[STLINK_SERIAL_LENGTH] = '\0'; } else { @@ -1104,11 +1104,11 @@ size_t stlink_serial(struct libusb_device_handle *handle, struct libusb_device_d return strlen(serial); } -stlink_t *stlink_open_usb(enum ugly_loglevel verbose, enum connect_type connect, char serial[STLINK_SERIAL_BUFFER_SIZE], int freq) { +stlink_t *stlink_open_usb(enum ugly_loglevel verbose, enum connect_type connect, char serial[STLINK_SERIAL_BUFFER_SIZE], int32_t freq) { stlink_t* sl = NULL; struct stlink_libusb* slu = NULL; - int ret = -1; - int config; + int32_t ret = -1; + int32_t config; sl = calloc(1, sizeof(stlink_t)); if (sl == NULL) { goto on_malloc_error; } @@ -1246,7 +1246,7 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, enum connect_type connect, // initialize stlink version (sl->version) stlink_version(sl); - int mode = stlink_current_mode(sl); + int32_t mode = stlink_current_mode(sl); if (mode == STLINK_DEV_DFU_MODE) { DLOG("-- exit_dfu_mode\n"); _stlink_usb_exit_dfu_mode(sl); @@ -1288,17 +1288,17 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, enum connect_type connect, return(NULL); } -static size_t stlink_probe_usb_devs(libusb_device **devs, stlink_t **sldevs[], enum connect_type connect, int freq) { +static size_t stlink_probe_usb_devs(libusb_device **devs, stlink_t **sldevs[], enum connect_type connect, int32_t freq) { stlink_t **_sldevs; libusb_device *dev; - int i = 0; + int32_t i = 0; size_t slcnt = 0; size_t slcur = 0; /* Count STLINKs */ while ((dev = devs[i++]) != NULL) { struct libusb_device_descriptor desc; - int ret = libusb_get_device_descriptor(dev, &desc); + int32_t ret = libusb_get_device_descriptor(dev, &desc); if (ret < 0) { WLOG("failed to get libusb device descriptor (libusb error: %d)\n", ret); @@ -1327,7 +1327,7 @@ static size_t stlink_probe_usb_devs(libusb_device **devs, stlink_t **sldevs[], e while ((dev = devs[i++]) != NULL) { struct libusb_device_descriptor desc; - int ret = libusb_get_device_descriptor(dev, &desc); + int32_t ret = libusb_get_device_descriptor(dev, &desc); if (ret < 0) { WLOG("failed to get libusb device descriptor (libusb error: %d)\n", ret); @@ -1372,12 +1372,12 @@ static size_t stlink_probe_usb_devs(libusb_device **devs, stlink_t **sldevs[], e return(slcur); } -size_t stlink_probe_usb(stlink_t **stdevs[], enum connect_type connect, int freq) { +size_t stlink_probe_usb(stlink_t **stdevs[], enum connect_type connect, int32_t freq) { libusb_device **devs; stlink_t **sldevs; size_t slcnt = 0; - int r; + int32_t r; ssize_t cnt; r = libusb_init(NULL); diff --git a/src/stlink-lib/usb.h b/src/stlink-lib/usb.h index 8c98bcaf4..b5c1835ec 100644 --- a/src/stlink-lib/usb.h +++ b/src/stlink-lib/usb.h @@ -7,9 +7,10 @@ #define USB_H #include +#include #include -#include +#include "libusb_settings.h" #include "logging.h" #define STLINK_USB_VID_ST 0x0483 @@ -49,12 +50,12 @@ struct stlink_libusb { libusb_context* libusb_ctx; libusb_device_handle* usb_handle; - unsigned int ep_req; - unsigned int ep_rep; - unsigned int ep_trace; - int protocoll; - unsigned int sg_transfer_idx; - unsigned int cmd_len; + uint32_t ep_req; + uint32_t ep_rep; + uint32_t ep_trace; + int32_t protocoll; + uint32_t sg_transfer_idx; + uint32_t cmd_len; }; /** @@ -66,8 +67,8 @@ struct stlink_libusb { * @retval !NULL Stlink found and ready to use */ -stlink_t *stlink_open_usb(enum ugly_loglevel verbose, enum connect_type connect, char serial[STLINK_SERIAL_BUFFER_SIZE], int freq); -size_t stlink_probe_usb(stlink_t **stdevs[], enum connect_type connect, int freq); +stlink_t *stlink_open_usb(enum ugly_loglevel verbose, enum connect_type connect, char serial[STLINK_SERIAL_BUFFER_SIZE], int32_t freq); +size_t stlink_probe_usb(stlink_t **stdevs[], enum connect_type connect, int32_t freq); void stlink_probe_usb_free(stlink_t **stdevs[], size_t size); #endif // USB_H diff --git a/src/win32/getopt/getopt.c b/src/win32/getopt/getopt.c index ff0a2fd91..7bc8d2d20 100644 --- a/src/win32/getopt/getopt.c +++ b/src/win32/getopt/getopt.c @@ -1,18 +1,19 @@ #include +#include #include #include "getopt.h" #if !defined(_MSC_VER) -const int no_argument = 0; -const int required_argument = 1; -const int optional_argument = 2; +const int32_t no_argument = 0; +const int32_t required_argument = 1; +const int32_t optional_argument = 2; #endif char* optarg; -int optopt; -int optind = 1; // The variable optind [...] shall be initialized to 1 by the system -int opterr; +int32_t optopt; +int32_t optind = 1; // The variable optind [...] shall be initialized to 1 by the system +int32_t opterr; static char* optcursor = NULL; @@ -24,8 +25,8 @@ static char* optcursor = NULL; * [2] http://www.kernel.org/doc/man-pages/online/pages/man3/getopt.3.html * [3] http://www.freebsd.org/cgi/man.cgi?query=getopt&sektion=3&manpath=FreeBSD+9.0-RELEASE */ -int getopt(int argc, char* const argv[], const char* optstring) { - int optchar = -1; +int32_t getopt(int32_t argc, char* const argv[], const char* optstring) { + int32_t optchar = -1; const char* optdecl = NULL; optarg = NULL; @@ -125,17 +126,17 @@ int getopt(int argc, char* const argv[], const char* optstring) { } /* Implementation based on http://www.kernel.org/doc/man-pages/online/pages/man3/getopt.3.html */ -int getopt_long(int argc, +int32_t getopt_long(int32_t argc, char* const argv[], const char* optstring, const struct option* longopts, int* longindex) { const struct option* o = longopts; const struct option* match = NULL; - int num_matches = 0; + int32_t num_matches = 0; size_t argument_name_length = 0; const char* current_argument = NULL; - int retval = -1; + int32_t retval = -1; optarg = NULL; optopt = 0; diff --git a/src/win32/getopt/getopt.h b/src/win32/getopt/getopt.h index b1dd35ef1..4f21e69dc 100644 --- a/src/win32/getopt/getopt.h +++ b/src/win32/getopt/getopt.h @@ -1,6 +1,8 @@ #ifndef GETOPT_H #define GETOPT_H +#include + #if defined(__cplusplus) extern "C" { #endif @@ -11,24 +13,24 @@ extern "C" { #define required_argument 1 #define optional_argument 2 #else -extern const int no_argument; -extern const int required_argument; -extern const int optional_argument; +extern const int32_t no_argument; +extern const int32_t required_argument; +extern const int32_t optional_argument; #endif extern char* optarg; -extern int optind, opterr, optopt; +extern int32_t optind, opterr, optopt; struct option { const char* name; - int has_arg; + int32_t has_arg; int* flag; - int val; + int32_t val; }; -int getopt(int argc, char* const argv[], const char* optstring); +int32_t getopt(int32_t argc, char* const argv[], const char* optstring); -int getopt_long(int argc, +int32_t getopt_long(int32_t argc, char* const argv[], const char* optstring, const struct option* longopts, diff --git a/src/win32/mmap.c b/src/win32/mmap.c index d702a78f6..ea8a3cb37 100644 --- a/src/win32/mmap.c +++ b/src/win32/mmap.c @@ -1,11 +1,12 @@ -#include -#include +#include #include +#include #include +#include #include "mmap.h" -void *mmap (void *addr, size_t len, int prot, int flags, int fd, long long offset) { +void *mmap (void *addr, size_t len, int32_t prot, int32_t flags, int32_t fd, int64_t offset) { void *buf; ssize_t count; @@ -31,7 +32,7 @@ void *mmap (void *addr, size_t len, int prot, int flags, int fd, long long offse (void)flags; } -int munmap (void *addr, size_t len) { +int32_t munmap (void *addr, size_t len) { free (addr); return(0); (void)len; diff --git a/src/win32/mmap.h b/src/win32/mmap.h index c6390aede..e8bbab0bc 100644 --- a/src/win32/mmap.h +++ b/src/win32/mmap.h @@ -1,6 +1,8 @@ #ifndef MMAP_H #define MMAP_H +#include + #ifdef STLINK_HAVE_SYS_MMAN_H #include #else @@ -13,8 +15,8 @@ #define MAP_ANONYMOUS (1 << 5) #define MAP_FAILED ((void *)-1) -void *mmap(void *addr, size_t len, int prot, int flags, int fd, long long offset); -int munmap(void *addr, size_t len); +void *mmap(void *addr, size_t len, int32_t prot, int32_t flags, int32_t fd, int64_t offset); +int32_t munmap(void *addr, size_t len); #endif // STLINK_HAVE_SYS_MMAN_H diff --git a/src/win32/sys_time.c b/src/win32/sys_time.c index 422731b3f..a09d8df67 100644 --- a/src/win32/sys_time.c +++ b/src/win32/sys_time.c @@ -1,3 +1,5 @@ +#include + #include "sys_time.h" #ifndef STLINK_HAVE_SYS_TIME_H @@ -5,18 +7,18 @@ #include /* Simple gettimeofday implementation without converting Windows time to Linux time */ -int gettimeofday(struct timeval *tv, struct timezone *tz) { +int32_t gettimeofday(struct timeval *tv, struct timezone *tz) { FILETIME ftime; ULARGE_INTEGER ulint; - static int tzflag = 0; + static int32_t tzflag = 0; if(NULL != tv) { GetSystemTimeAsFileTime(&ftime); ulint.LowPart = ftime.dwLowDateTime; ulint.HighPart = ftime.dwHighDateTime; - tv->tv_sec = (long)(ulint.QuadPart / 10000000L); - tv->tv_usec = (long)(ulint.QuadPart % 10000000L); + tv->tv_sec = (int32_t)(ulint.QuadPart / 10000000L); + tv->tv_usec = (int32_t)(ulint.QuadPart % 10000000L); } if(NULL != tz) { diff --git a/src/win32/sys_time.h b/src/win32/sys_time.h index 98ecaddfc..ca6e0a761 100644 --- a/src/win32/sys_time.h +++ b/src/win32/sys_time.h @@ -1,6 +1,8 @@ #ifndef SYS_TIME_H #define SYS_TIME_H +#include + #ifdef STLINK_HAVE_SYS_TIME_H #include @@ -10,11 +12,11 @@ #include struct timezone { - int tz_minuteswest; - int tz_dsttime; + int32_t tz_minuteswest; + int32_t tz_dsttime; }; -int gettimeofday(struct timeval *tv, struct timezone *tz); +int32_t gettimeofday(struct timeval *tv, struct timezone *tz); #endif // STLINK_HAVE_SYS_TIME_H diff --git a/src/win32/unistd/unistd.h b/src/win32/unistd/unistd.h index 5f2b5433b..d61b75b67 100644 --- a/src/win32/unistd/unistd.h +++ b/src/win32/unistd/unistd.h @@ -6,8 +6,9 @@ * Please add functionality as needed. */ -#include +#include #include +#include #if defined(_MSC_VER) #pragma warning(push) @@ -69,7 +70,7 @@ typedef unsigned __int32 uint32_t; typedef unsigned __int64 uint64_t; #ifndef STLINK_HAVE_UNISTD_H -int usleep(unsigned int waitTime); +int32_t usleep(uint32_t waitTime); #endif #endif // UNISTD_H diff --git a/src/win32/win32_socket.c b/src/win32/win32_socket.c index 3f4d28bbd..46b4532a7 100644 --- a/src/win32/win32_socket.c +++ b/src/win32/win32_socket.c @@ -1,5 +1,7 @@ #if defined(_WIN32) +#include + #include "win32_socket.h" #undef socket @@ -11,11 +13,11 @@ #include #include -int win32_poll(struct pollfd *fds, unsigned int nfds, int timo) { +int32_t win32_poll(struct pollfd *fds, uint32_t nfds, int32_t timo) { struct timeval timeout, *toptr; fd_set ifds, ofds, efds, *ip, *op; - unsigned int i; - int rc; + uint32_t i; + int32_t rc; #ifdef _MSC_VER #pragma warning(disable: 4548) @@ -99,7 +101,7 @@ int win32_poll(struct pollfd *fds, unsigned int nfds, int timo) { return(rc); } -static void set_connect_errno(int winsock_err) { +static void set_connect_errno(int32_t winsock_err) { switch (winsock_err) { case WSAEINVAL: case WSAEALREADY: @@ -112,7 +114,7 @@ static void set_connect_errno(int winsock_err) { } } -static void set_socket_errno(int winsock_err) { +static void set_socket_errno(int32_t winsock_err) { switch (winsock_err) { case WSAEWOULDBLOCK: errno = EAGAIN; @@ -128,7 +130,7 @@ static void set_socket_errno(int winsock_err) { * The purpose of this wrapper is to ensure that the global errno symbol is set if an error occurs, * even if we are using winsock. */ -SOCKET win32_socket(int domain, int type, int protocol) { +SOCKET win32_socket(int32_t domain, int32_t type, int32_t protocol) { SOCKET fd = socket(domain, type, protocol); if (fd == INVALID_SOCKET) { set_socket_errno(WSAGetLastError()); } @@ -141,8 +143,8 @@ SOCKET win32_socket(int domain, int type, int protocol) { * The purpose of this wrapper is to ensure that the global errno symbol is set if an error occurs, * even if we are using winsock. */ -int win32_connect(SOCKET fd, struct sockaddr *addr, socklen_t addr_len) { - int rc = connect(fd, addr, addr_len); +int32_t win32_connect(SOCKET fd, struct sockaddr *addr, socklen_t addr_len) { + int32_t rc = connect(fd, addr, addr_len); assert(rc == 0 || rc == SOCKET_ERROR); if (rc == SOCKET_ERROR) { set_connect_errno(WSAGetLastError()); } @@ -169,8 +171,8 @@ SOCKET win32_accept(SOCKET fd, struct sockaddr *addr, socklen_t *addr_len) { * The purpose of this wrapper is to ensure that the global errno symbol is set if an error occurs, * even if we are using winsock. */ -int win32_shutdown(SOCKET fd, int mode) { - int rc = shutdown(fd, mode); +int32_t win32_shutdown(SOCKET fd, int32_t mode) { + int32_t rc = shutdown(fd, mode); assert(rc == 0 || rc == SOCKET_ERROR); if (rc == SOCKET_ERROR) { set_socket_errno(WSAGetLastError()); } @@ -178,24 +180,24 @@ int win32_shutdown(SOCKET fd, int mode) { return(rc); } -int win32_close_socket(SOCKET fd) { - int rc = closesocket(fd); +int32_t win32_close_socket(SOCKET fd) { + int32_t rc = closesocket(fd); if (rc == SOCKET_ERROR) { set_socket_errno(WSAGetLastError()); } return(rc); } -ssize_t win32_write_socket(SOCKET fd, void *buf, int n) { - int rc = send(fd, buf, n, 0); +ssize_t win32_write_socket(SOCKET fd, void *buf, int32_t n) { + int32_t rc = send(fd, buf, n, 0); if (rc == SOCKET_ERROR) { set_socket_errno(WSAGetLastError()); } return(rc); } -ssize_t win32_read_socket(SOCKET fd, void *buf, int n) { - int rc = recv(fd, buf, n, 0); +ssize_t win32_read_socket(SOCKET fd, void *buf, int32_t n) { + int32_t rc = recv(fd, buf, n, 0); if (rc == SOCKET_ERROR) { set_socket_errno(WSAGetLastError()); } @@ -205,7 +207,7 @@ ssize_t win32_read_socket(SOCKET fd, void *buf, int n) { char * win32_strtok_r(char *s, const char *delim, char **lasts) { register char *spanp; - register int c, sc; + register int32_t c, sc; char *tok; @@ -254,7 +256,7 @@ char * win32_strtok_r(char *s, const char *delim, char **lasts) { char *win32_strsep (char **stringp, const char *delim) { register char *s; register const char *spanp; - register int c, sc; + register int32_t c, sc; char *tok; if ((s = *stringp) == NULL) { @@ -284,7 +286,7 @@ char *win32_strsep (char **stringp, const char *delim) { } #ifndef STLINK_HAVE_UNISTD_H -int usleep(unsigned int waitTime) { +int32_t usleep(uint32_t waitTime) { if (waitTime >= 1000) { /* Don't do long busy-waits. * However much it seems like the QPC code would be more accurate, diff --git a/src/win32/win32_socket.h b/src/win32/win32_socket.h index 614046a6f..e7ea398e9 100644 --- a/src/win32/win32_socket.h +++ b/src/win32/win32_socket.h @@ -1,5 +1,7 @@ #if defined(_WIN32) +#include + #define _USE_W32_SOCKETS 1 #if defined(_MSC_VER) @@ -35,8 +37,8 @@ #define POLLNVAL 0x0020 /* Invalid request: fd not open */ struct pollfd { SOCKET fd; /* file descriptor */ - short events; /* requested events */ - short revents; /* returned events */ + int16_t events; /* requested events */ + int16_t revents; /* returned events */ }; #endif #define poll(x, y, z) win32_poll(x, y, z) @@ -54,15 +56,15 @@ struct pollfd { #define read(x, y, z) win32_read_socket(x, y, z) #define write(x, y, z) win32_write_socket(x, y, z) -/* Winsock uses int instead of the usual socklen_t */ -typedef int socklen_t; +/* Winsock uses int32_t instead of the usual socklen_t */ +typedef int32_t socklen_t; -int win32_poll(struct pollfd *, unsigned int, int); -SOCKET win32_socket(int, int, int); -int win32_connect(SOCKET, struct sockaddr*, socklen_t); +int32_t win32_poll(struct pollfd *, uint32_t, int); +SOCKET win32_socket(int32_t, int32_t, int); +int32_t win32_connect(SOCKET, struct sockaddr*, socklen_t); SOCKET win32_accept(SOCKET, struct sockaddr*, socklen_t *); -int win32_shutdown(SOCKET, int); -int win32_close_socket(SOCKET fd); +int32_t win32_shutdown(SOCKET, int); +int32_t win32_close_socket(SOCKET fd); #define strtok_r(x, y, z) win32_strtok_r(x, y, z) #define strsep(x,y) win32_strsep(x,y) @@ -70,7 +72,7 @@ int win32_close_socket(SOCKET fd); char *win32_strtok_r(char *s, const char *delim, char **lasts); char *win32_strsep(char **stringp, const char *delim); -ssize_t win32_read_socket(SOCKET fd, void *buf, int n); -ssize_t win32_write_socket(SOCKET fd, void *buf, int n); +ssize_t win32_read_socket(SOCKET fd, void *buf, int32_t n); +ssize_t win32_write_socket(SOCKET fd, void *buf, int32_t n); #endif // defined(_WIN32) diff --git a/tests/flash.c b/tests/flash.c index 1140566af..f66428dcd 100644 --- a/tests/flash.c +++ b/tests/flash.c @@ -1,3 +1,4 @@ +#include #include #include #include @@ -11,7 +12,7 @@ struct Test { const char * cmd_line; - int res; + int32_t res; struct flash_opts opts; }; @@ -32,7 +33,7 @@ static bool cmp_mem(const uint8_t * s1, const uint8_t * s2, size_t size) { } static bool execute_test(const struct Test * test) { - int ac = 0; + int32_t ac = 0; char* av[32]; /* parse (tokenize) the test command line */ @@ -53,7 +54,7 @@ static bool execute_test(const struct Test * test) { /* Call */ struct flash_opts opts; - int res = flash_get_opts(&opts, ac, av); + int32_t res = flash_get_opts(&opts, ac, av); /* Compare results */ bool ret = (res == test->res); @@ -225,7 +226,7 @@ static struct Test tests[] = { }, }; -int main() { +int32_t main() { bool allOk = true; for (size_t i = 0; i < sizeof(tests) / sizeof(tests[0]); ++i) diff --git a/tests/sg.c b/tests/sg.c index d88fbe760..cd601b6d6 100644 --- a/tests/sg.c +++ b/tests/sg.c @@ -1,3 +1,4 @@ +#include #include #include #include @@ -24,7 +25,7 @@ static void __attribute__((unused)) mark_buf(stlink_t *sl) { } -int main(void) { // main() ripped out of old stlink-hw.c +int32_t main(void) { // main() ripped out of old stlink-hw.c /* Avoid unused parameter warning */ // set scpi lib debug level: 0 for no debug info, 10 for lots fputs( @@ -81,7 +82,7 @@ int main(void) { // main() ripped out of old stlink-hw.c memset(sl->q_buf, 0, sizeof(sl->q_buf)); - for (int i = 0; i < 100; i++) { + for (int32_t i = 0; i < 100; i++) { write_uint32(sl->q_buf, LED_BLUE | LED_GREEN); stlink_write_mem32(sl, GPIOC_ODR, 4); // stlink_read_mem32(sl, 0x4001100c, 4); @@ -184,7 +185,7 @@ int main(void) { // main() ripped out of old stlink-hw.c #if 0 /* check file contents */ fputs("\n+++++++ check flash memory\n\n", stderr); { - const int res = stlink_fcheck_flash(sl, "/tmp/foobar", 0x08000000); + const int32_t res = stlink_fcheck_flash(sl, "/tmp/foobar", 0x08000000); printf("_____ stlink_fcheck_flash() == %d\n", res); } #endif diff --git a/tests/usb.c b/tests/usb.c index 742f5c578..2d928e5f0 100644 --- a/tests/usb.c +++ b/tests/usb.c @@ -1,17 +1,18 @@ +#include #include +#include #include -#include static void usage(void) { puts("test-usb --reset"); puts("test-usb --no-reset"); } -int main(int ac, char** av) { +int32_t main(int32_t ac, char** av) { stlink_t* sl; struct stlink_reg regs; - int reset = 0; + int32_t reset = 0; if (ac == 2) { if (strcmp(av[1], "--reset") == 0) From 92ad99fe35d03adbe411eba5afabbb30c0c734b4 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Wed, 7 Jun 2023 22:01:56 +0200 Subject: [PATCH 445/503] Minor fixes & additions - G49x_G4Ax & WLEx: Added dualbank support - G49x_G4Ax: Added option byte support - Minor formatting improvements - Replaced leftovers for non-fixed length types --- config/chips/G49x_G4Ax.chip | 2 +- config/chips/{WLx5.chip => WLEx.chip} | 2 +- src/stlink-lib/common.c | 11 +- src/stlink-lib/common_flash.c | 3 +- src/stlink-lib/flash_loader.c | 141 +++++++++++++------------- src/stlink-lib/flash_loader.h | 12 ++- src/stlink-lib/option_bytes.c | 1 + src/win32/win32_socket.h | 6 +- 8 files changed, 92 insertions(+), 86 deletions(-) rename config/chips/{WLx5.chip => WLEx.chip} (95%) diff --git a/config/chips/G49x_G4Ax.chip b/config/chips/G49x_G4Ax.chip index 3e8aacf4b..079dc01ae 100644 --- a/config/chips/G49x_G4Ax.chip +++ b/config/chips/G49x_G4Ax.chip @@ -11,4 +11,4 @@ bootrom_base 0x1fff0000 bootrom_size 0x7000 // 28 KB option_base 0x1ffff800 // STM32_G4_OPTION_BYTES_BASE option_size 0x4 // 4 B -flags swo +flags swo dualbank diff --git a/config/chips/WLx5.chip b/config/chips/WLEx.chip similarity index 95% rename from config/chips/WLx5.chip rename to config/chips/WLEx.chip index 8337b0aee..265514211 100644 --- a/config/chips/WLx5.chip +++ b/config/chips/WLEx.chip @@ -11,4 +11,4 @@ bootrom_base 0x1fff0000 bootrom_size 0x7000 // 28 KB option_base 0x1fff7800 option_size 0x10 // 16 B -flags swo +flags swo dualbank diff --git a/src/stlink-lib/common.c b/src/stlink-lib/common.c index cb87f5f36..43d2b9a9e 100644 --- a/src/stlink-lib/common.c +++ b/src/stlink-lib/common.c @@ -41,8 +41,8 @@ struct stlink_fread_ihex_worker_arg { typedef bool (*save_block_fn)(void *arg, uint8_t *block, ssize_t len); static void stop_wdg_in_debug(stlink_t *); -int32_t stlink_jtag_reset(stlink_t *, int); -int32_t stlink_soft_reset(stlink_t *, int); +int32_t stlink_jtag_reset(stlink_t *, int32_t); +int32_t stlink_soft_reset(stlink_t *, int32_t); void _parse_version(stlink_t *, stlink_version_t *); static uint8_t stlink_parse_hex(const char *); static int32_t stlink_read(stlink_t *, stm32_addr_t, size_t, save_block_fn, void *); @@ -253,8 +253,8 @@ int32_t stlink_load_device_params(stlink_t *sl) { flash_size = flash_size & 0xffff; if ((sl->chip_id == STM32_CHIPID_L1_MD || - sl->chip_id == STM32_CHIPID_F1_VL_MD_LD || - sl->chip_id == STM32_CHIPID_L1_MD_PLUS) && + sl->chip_id == STM32_CHIPID_F1_VL_MD_LD || + sl->chip_id == STM32_CHIPID_L1_MD_PLUS) && (flash_size == 0)) { sl->flash_size = 128 * 1024; } else if (sl->chip_id == STM32_CHIPID_L1_CAT2) { @@ -285,7 +285,8 @@ int32_t stlink_load_device_params(stlink_t *sl) { sl->sram_size = 0x1000; } - if (sl->chip_id == STM32_CHIPID_G4_CAT3) { + if (sl->chip_id == STM32_CHIPID_G4_CAT3 || + sl->chip_id == STM32_CHIPID_G4_CAT4) { uint32_t flash_optr; stlink_read_debug32(sl, FLASH_Gx_OPTR, &flash_optr); diff --git a/src/stlink-lib/common_flash.c b/src/stlink-lib/common_flash.c index e2a394946..31ea02c07 100644 --- a/src/stlink-lib/common_flash.c +++ b/src/stlink-lib/common_flash.c @@ -1348,8 +1348,7 @@ int32_t stlink_fcheck_flash(stlink_t *sl, const char *path, stm32_addr_t addr) { * @param length how much * @return 0 for success, -ve for failure */ -int32_t stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, - uint32_t length) { +int32_t stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, uint32_t length) { size_t off; size_t cmp_size = (sl->flash_pgsz > 0x1800) ? 0x1800 : sl->flash_pgsz; ILOG("Starting verification of write complete\n"); diff --git a/src/stlink-lib/flash_loader.c b/src/stlink-lib/flash_loader.c index 99a8260f7..23b2713a8 100644 --- a/src/stlink-lib/flash_loader.c +++ b/src/stlink-lib/flash_loader.c @@ -24,7 +24,7 @@ * flash loaders must be aligned by 4 (it's written by stlink_write_mem32) */ -/* flashloaders/stm32f0.s -- compiled with thumb2 */ +// flashloaders/stm32f0.s -- compiled with thumb2 static const uint8_t loader_code_stm32vl[] = { 0x00, 0xbf, 0x00, 0xbf, 0x09, 0x4f, 0x1f, 0x44, @@ -41,7 +41,7 @@ static const uint8_t loader_code_stm32vl[] = { 0x0c, 0x00, 0x00, 0x00 }; -/* flashloaders/stm32f0.s -- thumb1 only, same sequence as for STM32VL, bank ignored */ +// flashloaders/stm32f0.s -- thumb1 only, same sequence as for STM32VL, bank ignored static const uint8_t loader_code_stm32f0[] = { 0xc0, 0x46, 0xc0, 0x46, 0x08, 0x4f, 0x1f, 0x44, @@ -59,8 +59,8 @@ static const uint8_t loader_code_stm32f0[] = { 0x14, 0x00, 0x00, 0x00 }; +// flashloaders/stm32lx.s static const uint8_t loader_code_stm32lx[] = { - // flashloaders/stm32lx.s 0x04, 0x68, 0x0c, 0x60, 0x00, 0xf1, 0x04, 0x00, 0x01, 0xf1, 0x04, 0x01, @@ -68,8 +68,8 @@ static const uint8_t loader_code_stm32lx[] = { 0x00, 0xbe, 0x00, 0x00 }; +// flashloaders/stm32f4.s static const uint8_t loader_code_stm32f4[] = { - // flashloaders/stm32f4.s 0xdf, 0xf8, 0x24, 0xc0, 0xdf, 0xf8, 0x24, 0xa0, 0xe2, 0x44, 0x04, 0x68, @@ -84,8 +84,8 @@ static const uint8_t loader_code_stm32f4[] = { 0x0e, 0x00, 0x00, 0x00 }; +// flashloaders/stm32f4lv.s static const uint8_t loader_code_stm32f4_lv[] = { - // flashloaders/stm32f4lv.s 0xdf, 0xf8, 0x24, 0xc0, 0xdf, 0xf8, 0x24, 0xa0, 0xe2, 0x44, 0x04, 0x78, @@ -100,8 +100,8 @@ static const uint8_t loader_code_stm32f4_lv[] = { 0x0e, 0x00, 0x00, 0x00 }; +// flashloaders/stm32l4.s static const uint8_t loader_code_stm32l4[] = { - // flashloaders/stm32l4.s 0xdf, 0xf8, 0x28, 0xc0, 0xdf, 0xf8, 0x28, 0xa0, 0xe2, 0x44, 0x05, 0x68, @@ -117,8 +117,8 @@ static const uint8_t loader_code_stm32l4[] = { 0x10, 0x00, 0x00, 0x00 }; +// flashloaders/stm32f7.s static const uint8_t loader_code_stm32f7[] = { - // flashloaders/stm32f7.s 0xdf, 0xf8, 0x28, 0xc0, 0xdf, 0xf8, 0x28, 0xa0, 0xe2, 0x44, 0x04, 0x68, @@ -134,8 +134,8 @@ static const uint8_t loader_code_stm32f7[] = { 0x0e, 0x00, 0x00, 0x00 }; +// flashloaders/stm32f7lv.s static const uint8_t loader_code_stm32f7_lv[] = { - // flashloaders/stm32f7lv.s 0xdf, 0xf8, 0x28, 0xc0, 0xdf, 0xf8, 0x28, 0xa0, 0xe2, 0x44, 0x04, 0x78, @@ -201,9 +201,9 @@ int32_t stlink_flash_loader_init(stlink_t *sl, flash_loader_t *fl) { } static int32_t loader_v_dependent_assignment(stlink_t *sl, - const uint8_t **loader_code, size_t *loader_size, - const uint8_t *high_v_loader, size_t high_v_loader_size, - const uint8_t *low_v_loader, size_t low_v_loader_size) { + const uint8_t **loader_code, size_t *loader_size, + const uint8_t *high_v_loader, size_t high_v_loader_size, + const uint8_t *low_v_loader, size_t low_v_loader_size) { int32_t retval = 0; if ( sl->version.stlink_v == 1) { @@ -338,21 +338,21 @@ int32_t stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t t flash_base = FLASH_REGS_BANK2_OFS; } - /* Setup core */ - stlink_write_reg(sl, fl->buf_addr, 0); // source - stlink_write_reg(sl, target, 1); // target - stlink_write_reg(sl, (uint32_t)size, 2); // count - stlink_write_reg(sl, flash_base, 3); // flash register base - // only used on VL/F1_XL, but harmless for others - stlink_write_reg(sl, fl->loader_addr, 15); // pc register + /* Setup core */ + stlink_write_reg(sl, fl->buf_addr, 0); // source + stlink_write_reg(sl, target, 1); // target + stlink_write_reg(sl, (uint32_t)size, 2); // count + stlink_write_reg(sl, flash_base, 3); // flash register base + // only used on VL/F1_XL, but harmless for others + stlink_write_reg(sl, fl->loader_addr, 15); // pc register - /* Reset IWDG */ - if (fl->iwdg_kr) { - stlink_write_debug32(sl, fl->iwdg_kr, STM32F0_WDG_KR_KEY_RELOAD); - } + /* Reset IWDG */ + if (fl->iwdg_kr) { + stlink_write_debug32(sl, fl->iwdg_kr, STM32F0_WDG_KR_KEY_RELOAD); + } - /* Run loader */ - stlink_run(sl, RUN_FLASH_LOADER); + /* Run loader */ + stlink_run(sl, RUN_FLASH_LOADER); /* * This piece of code used to try to spin for .1 second by waiting doing 10000 rounds of 10 µs. @@ -365,67 +365,63 @@ int32_t stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t t * as what was intended. -- REW. */ - // wait until done (reaches breakpoint) - timeout = time_ms() + 500; - while (time_ms() < timeout) { - usleep(10000); - - if (stlink_is_core_halted(sl)) { - timeout = 0; - break; - } - } + // wait until done (reaches breakpoint) + timeout = time_ms() + 500; + while (time_ms() < timeout) { + usleep(10000); - if (timeout) { - ELOG("Flash loader run error\n"); - goto error; - } + if (stlink_is_core_halted(sl)) { + timeout = 0; + break; + } + } - // check written byte count - stlink_read_reg(sl, 2, &rr); + if (timeout) { + ELOG("Flash loader run error\n"); + goto error; + } - /* - * The chunk size for loading is not rounded. The flash loader - * subtracts the size of the written block (1-8 bytes) from - * the remaining size each time. A negative value may mean that - * several bytes garbage have been written due to the unaligned - * firmware size. - */ - if ((int32_t)rr.r[2] > 0 || (int32_t)rr.r[2] < -7) { - ELOG("Flash loader write error\n"); - goto error; - } + // check written byte count + stlink_read_reg(sl, 2, &rr); + + /* + * The chunk size for loading is not rounded. The flash loader + * subtracts the size of the written block (1-8 bytes) from + * the remaining size each time. A negative value may mean that + * several bytes garbage have been written due to the unaligned + * firmware size. + */ + if ((int32_t)rr.r[2] > 0 || (int32_t)rr.r[2] < -7) { + ELOG("Flash loader write error\n"); + goto error; + } - return(0); + return(0); -error: - dhcsr = dfsr = cfsr = hfsr = 0; - stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); - stlink_read_debug32(sl, STLINK_REG_DFSR, &dfsr); - stlink_read_debug32(sl, STLINK_REG_CFSR, &cfsr); - stlink_read_debug32(sl, STLINK_REG_HFSR, &hfsr); - stlink_read_all_regs(sl, &rr); + error: + dhcsr = dfsr = cfsr = hfsr = 0; + stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); + stlink_read_debug32(sl, STLINK_REG_DFSR, &dfsr); + stlink_read_debug32(sl, STLINK_REG_CFSR, &cfsr); + stlink_read_debug32(sl, STLINK_REG_HFSR, &hfsr); + stlink_read_all_regs(sl, &rr); - WLOG("Loader state: R2 0x%X R15 0x%X\n", rr.r[2], rr.r[15]); - if (dhcsr != 0x3000B || dfsr || cfsr || hfsr) { - WLOG("MCU state: DHCSR 0x%X DFSR 0x%X CFSR 0x%X HFSR 0x%X\n", - dhcsr, dfsr, cfsr, hfsr); - } + WLOG("Loader state: R2 0x%X R15 0x%X\n", rr.r[2], rr.r[15]); + if (dhcsr != 0x3000B || dfsr || cfsr || hfsr) { + WLOG("MCU state: DHCSR 0x%X DFSR 0x%X CFSR 0x%X HFSR 0x%X\n", + dhcsr, dfsr, cfsr, hfsr); + } - return(-1); + return(-1); } -/* ================================================== - * === Content from old source file flashloader.c === - * ================================================== - */ +/* === Content from old source file flashloader.c === */ #define L1_WRITE_BLOCK_SIZE 0x80 #define L0_WRITE_BLOCK_SIZE 0x40 -int32_t stm32l1_write_half_pages(stlink_t *sl, stm32_addr_t addr, uint8_t *base, - uint32_t len, uint32_t pagesize) { +int32_t stm32l1_write_half_pages(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint32_t len, uint32_t pagesize) { uint32_t count, off; uint32_t num_half_pages = len / pagesize; uint32_t val; @@ -722,8 +718,7 @@ int32_t stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { return (0); } -int32_t stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, - stm32_addr_t addr, uint8_t *base, uint32_t len) { +int32_t stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t addr, uint8_t *base, uint32_t len) { size_t off; if ((sl->flash_type == STM32_FLASH_TYPE_F2_F4) || (sl->flash_type == STM32_FLASH_TYPE_F7) || diff --git a/src/stlink-lib/flash_loader.h b/src/stlink-lib/flash_loader.h index 5b7b0945d..46cacba30 100644 --- a/src/stlink-lib/flash_loader.h +++ b/src/stlink-lib/flash_loader.h @@ -14,11 +14,21 @@ #include int32_t stlink_flash_loader_init(stlink_t *sl, flash_loader_t* fl); +static int32_t loader_v_dependent_assignment(stlink_t *sl, + const uint8_t **loader_code, size_t *loader_size, + const uint8_t *high_v_loader, size_t high_v_loader_size, + const uint8_t *low_v_loader, size_t low_v_loader_size); int32_t stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size); int32_t stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, const uint8_t* buf, size_t size); + +/* === Functions from old header file flashloader.h === */ + +int32_t stm32l1_write_half_pages(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint32_t len, uint32_t pagesize); +static void set_flash_cr_pg(stlink_t *sl, uint32_t bank); +static void set_dma_state(stlink_t *sl, flash_loader_t *fl, int32_t bckpRstr); int32_t stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl); -int32_t stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t addr, uint8_t* base, uint32_t len); +int32_t stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t addr, uint8_t *base, uint32_t len); int32_t stlink_flashloader_stop(stlink_t *sl, flash_loader_t *fl); #endif // FLASH_LOADER_H diff --git a/src/stlink-lib/option_bytes.c b/src/stlink-lib/option_bytes.c index e2d966b7a..3300ee15e 100644 --- a/src/stlink-lib/option_bytes.c +++ b/src/stlink-lib/option_bytes.c @@ -1012,6 +1012,7 @@ int32_t stlink_read_option_bytes32(stlink_t *sl, uint32_t *option_byte) { case STM32_CHIPID_G0_CAT2: case STM32_CHIPID_G4_CAT2: case STM32_CHIPID_G4_CAT3: + case STM32_CHIPID_G4_CAT4: return stlink_read_option_bytes_gx(sl, option_byte); default: return stlink_read_option_bytes_generic(sl, option_byte); diff --git a/src/win32/win32_socket.h b/src/win32/win32_socket.h index e7ea398e9..fb622f546 100644 --- a/src/win32/win32_socket.h +++ b/src/win32/win32_socket.h @@ -59,11 +59,11 @@ struct pollfd { /* Winsock uses int32_t instead of the usual socklen_t */ typedef int32_t socklen_t; -int32_t win32_poll(struct pollfd *, uint32_t, int); -SOCKET win32_socket(int32_t, int32_t, int); +int32_t win32_poll(struct pollfd *, uint32_t, int32_t); +SOCKET win32_socket(int32_t, int32_t, int32_t); int32_t win32_connect(SOCKET, struct sockaddr*, socklen_t); SOCKET win32_accept(SOCKET, struct sockaddr*, socklen_t *); -int32_t win32_shutdown(SOCKET, int); +int32_t win32_shutdown(SOCKET, int32_t); int32_t win32_close_socket(SOCKET fd); #define strtok_r(x, y, z) win32_strtok_r(x, y, z) From c8eaebc58eb7b027ab53c16ef4e8ad6fd72a10d7 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Wed, 7 Jun 2023 22:44:59 +0200 Subject: [PATCH 446/503] Improvents for library documentation - Renamed header file reg.h to register.h - Added unified header comments for files - [doc] flash_loader.h: // Static functions --- CMakeLists.txt | 2 +- inc/stlink.h | 6 ++---- src/st-trace/trace.c | 2 +- src/stlink-lib/calculate.c | 6 ++++++ src/stlink-lib/chipid.c | 6 ++++++ src/stlink-lib/chipid.h | 6 ++++++ src/stlink-lib/commands.h | 6 ++++++ src/stlink-lib/common_flash.c | 6 ++++++ src/stlink-lib/flash_loader.c | 6 ++++++ src/stlink-lib/flash_loader.h | 14 +++++++------- src/stlink-lib/helper.c | 6 ++++++ src/stlink-lib/helper.h | 6 ++++++ src/stlink-lib/libusb_settings.h | 6 ++++++ src/stlink-lib/logging.c | 3 +-- src/stlink-lib/map_file.c | 6 ++++++ src/stlink-lib/md5.c | 6 ++++++ src/stlink-lib/option_bytes.c | 6 ++++++ src/stlink-lib/{reg.h => register.h} | 10 ++++++++-- src/stlink-lib/sg.c | 6 ++++++ src/stlink-lib/sg.h | 5 +++-- src/stlink-lib/usb.c | 6 ++++++ src/stlink-lib/usb.h | 5 +++-- 22 files changed, 110 insertions(+), 21 deletions(-) rename src/stlink-lib/{reg.h => register.h} (98%) diff --git a/CMakeLists.txt b/CMakeLists.txt index bce4def8f..4ff18b815 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -180,7 +180,7 @@ set(STLINK_HEADERS src/stlink-lib/map_file.h src/stlink-lib/md5.h src/stlink-lib/option_bytes.h - src/stlink-lib/reg.h + src/stlink-lib/register.h src/stlink-lib/sg.h src/stlink-lib/usb.h ) diff --git a/inc/stlink.h b/inc/stlink.h index ca07a6a89..2ed34a074 100644 --- a/inc/stlink.h +++ b/inc/stlink.h @@ -1,9 +1,7 @@ - /* * File: stlink.h * - * This should contain all the common top level stlink interfaces, - * regardless of how the backend does the work.... + * All common top level stlink interfaces, regardless of how the backend does the work.... */ #ifndef STLINK_H @@ -300,7 +298,7 @@ int32_t stlink_target_connect(stlink_t *sl, enum connect_type connect); #include #include -#include +#include #include #include #include diff --git a/src/st-trace/trace.c b/src/st-trace/trace.c index 8b148f463..ccbd74e16 100644 --- a/src/st-trace/trace.c +++ b/src/st-trace/trace.c @@ -11,7 +11,7 @@ #include #include -#include +#include #include #define DEFAULT_LOGGING_LEVEL 50 diff --git a/src/stlink-lib/calculate.c b/src/stlink-lib/calculate.c index 132875a66..2a708b551 100644 --- a/src/stlink-lib/calculate.c +++ b/src/stlink-lib/calculate.c @@ -1,3 +1,9 @@ +/* + * File: calculate.c + * + * Calculation of sector numbers and pages + */ + #include #include diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index 7e99a8730..65ca2842a 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -1,3 +1,9 @@ +/* + * File: chipid.c + * + * Chip-ID parametres + */ + #include #include #include diff --git a/src/stlink-lib/chipid.h b/src/stlink-lib/chipid.h index 9eaac722d..9955811fa 100644 --- a/src/stlink-lib/chipid.h +++ b/src/stlink-lib/chipid.h @@ -1,3 +1,9 @@ +/* + * File: chipid.h + * + * Chip-ID parametres + */ + #ifndef CHIPID_H #define CHIPID_H diff --git a/src/stlink-lib/commands.h b/src/stlink-lib/commands.h index 5f0904971..64cecce16 100644 --- a/src/stlink-lib/commands.h +++ b/src/stlink-lib/commands.h @@ -1,3 +1,9 @@ +/* + * File: commands.h + * + * stlink commands + */ + #ifndef COMMANDS_H #define COMMANDS_H diff --git a/src/stlink-lib/common_flash.c b/src/stlink-lib/common_flash.c index 31ea02c07..d2063851f 100644 --- a/src/stlink-lib/common_flash.c +++ b/src/stlink-lib/common_flash.c @@ -1,3 +1,9 @@ +/* + * File: common_flash.c + * + * Flash operations + */ + #include #include #include diff --git a/src/stlink-lib/flash_loader.c b/src/stlink-lib/flash_loader.c index 23b2713a8..0f171d223 100644 --- a/src/stlink-lib/flash_loader.c +++ b/src/stlink-lib/flash_loader.c @@ -1,3 +1,9 @@ +/* + * File: flash_loader.c + * + * Flash loaders + */ + #include #include #include diff --git a/src/stlink-lib/flash_loader.h b/src/stlink-lib/flash_loader.h index 46cacba30..8888875a7 100644 --- a/src/stlink-lib/flash_loader.h +++ b/src/stlink-lib/flash_loader.h @@ -1,7 +1,7 @@ /* * File: flash_loader.h * - * Flash loader + * Flash loaders */ #ifndef FLASH_LOADER_H @@ -14,10 +14,10 @@ #include int32_t stlink_flash_loader_init(stlink_t *sl, flash_loader_t* fl); -static int32_t loader_v_dependent_assignment(stlink_t *sl, - const uint8_t **loader_code, size_t *loader_size, - const uint8_t *high_v_loader, size_t high_v_loader_size, - const uint8_t *low_v_loader, size_t low_v_loader_size); +// static int32_t loader_v_dependent_assignment(stlink_t *sl, +// const uint8_t **loader_code, size_t *loader_size, +// const uint8_t *high_v_loader, size_t high_v_loader_size, +// const uint8_t *low_v_loader, size_t low_v_loader_size); int32_t stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size); int32_t stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, const uint8_t* buf, size_t size); @@ -25,8 +25,8 @@ int32_t stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t t /* === Functions from old header file flashloader.h === */ int32_t stm32l1_write_half_pages(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint32_t len, uint32_t pagesize); -static void set_flash_cr_pg(stlink_t *sl, uint32_t bank); -static void set_dma_state(stlink_t *sl, flash_loader_t *fl, int32_t bckpRstr); +// static void set_flash_cr_pg(stlink_t *sl, uint32_t bank); +// static void set_dma_state(stlink_t *sl, flash_loader_t *fl, int32_t bckpRstr); int32_t stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl); int32_t stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t addr, uint8_t *base, uint32_t len); int32_t stlink_flashloader_stop(stlink_t *sl, flash_loader_t *fl); diff --git a/src/stlink-lib/helper.c b/src/stlink-lib/helper.c index a6155925f..d7420691a 100644 --- a/src/stlink-lib/helper.c +++ b/src/stlink-lib/helper.c @@ -1,3 +1,9 @@ +/* + * File: helper.c + * + * General helper functions + */ + #include #include #include diff --git a/src/stlink-lib/helper.h b/src/stlink-lib/helper.h index dbd760a52..43a96368d 100644 --- a/src/stlink-lib/helper.h +++ b/src/stlink-lib/helper.h @@ -1,3 +1,9 @@ +/* + * File: helper.h + * + * General helper functions + */ + #ifndef HELPER_H #define HELPER_H diff --git a/src/stlink-lib/libusb_settings.h b/src/stlink-lib/libusb_settings.h index 3777f720b..b0a51ad31 100644 --- a/src/stlink-lib/libusb_settings.h +++ b/src/stlink-lib/libusb_settings.h @@ -1,3 +1,9 @@ +/* + * File: libusb_settings.h + * + * Settings for libusb library + */ + #ifndef LIBUSB_SETTINGS_H #define LIBUSB_SETTINGS_H diff --git a/src/stlink-lib/logging.c b/src/stlink-lib/logging.c index a64ec4ef2..1463eb925 100644 --- a/src/stlink-lib/logging.c +++ b/src/stlink-lib/logging.c @@ -1,8 +1,7 @@ /* * UglyLogging * - * Slow, yet another wheel reinvented, but enough to make the rest of our code - * pretty enough. + * Slow, yet another wheel reinvented, but enough to make the rest of our code pretty enough. */ #include diff --git a/src/stlink-lib/map_file.c b/src/stlink-lib/map_file.c index bb83ff7be..cfd2d1876 100644 --- a/src/stlink-lib/map_file.c +++ b/src/stlink-lib/map_file.c @@ -1,3 +1,9 @@ +/* + * File: map_file.c + * + * File mapping + */ + #include #include #include diff --git a/src/stlink-lib/md5.c b/src/stlink-lib/md5.c index 19ec86b91..f7af43ac3 100644 --- a/src/stlink-lib/md5.c +++ b/src/stlink-lib/md5.c @@ -5,6 +5,12 @@ * This is free and unencumbered software released into the public domain - June 2013 - waterjuice.org */ +/* + * File: md5.c + * + * MD5 hash function + */ + #include #include diff --git a/src/stlink-lib/option_bytes.c b/src/stlink-lib/option_bytes.c index 3300ee15e..6a12333cd 100644 --- a/src/stlink-lib/option_bytes.c +++ b/src/stlink-lib/option_bytes.c @@ -1,3 +1,9 @@ +/* + * File: option_bytes.c + * + * Read and write option bytes and option control registers + */ + #include #include #include diff --git a/src/stlink-lib/reg.h b/src/stlink-lib/register.h similarity index 98% rename from src/stlink-lib/reg.h rename to src/stlink-lib/register.h index c2976d050..7b63154c8 100644 --- a/src/stlink-lib/reg.h +++ b/src/stlink-lib/register.h @@ -1,5 +1,11 @@ -#ifndef REG_H -#define REG_H +/* + * File: register.h + * + * Common STM32 registers + */ + +#ifndef REGISTER_H +#define REGISTER_H #define STLINK_REG_CM3_CPUID 0xE000ED00 diff --git a/src/stlink-lib/sg.c b/src/stlink-lib/sg.c index c0f79c7cf..7c16a5336 100644 --- a/src/stlink-lib/sg.c +++ b/src/stlink-lib/sg.c @@ -74,6 +74,12 @@ * part to an existing options line for usb-storage). */ +/* + * File: sg.c + * + * + */ + #define __USE_GNU #include diff --git a/src/stlink-lib/sg.h b/src/stlink-lib/sg.h index d4792c49a..ce69f7a09 100644 --- a/src/stlink-lib/sg.h +++ b/src/stlink-lib/sg.h @@ -1,6 +1,7 @@ /* - * File: sg.h - * Author: karl + * File: sg.h + * + * */ #ifndef SG_H diff --git a/src/stlink-lib/usb.c b/src/stlink-lib/usb.c index d404c2e94..e9f45574f 100644 --- a/src/stlink-lib/usb.c +++ b/src/stlink-lib/usb.c @@ -1,3 +1,9 @@ +/* + * File: usb.c + * + * + */ + #include #include #include diff --git a/src/stlink-lib/usb.h b/src/stlink-lib/usb.h index b5c1835ec..55d506c5b 100644 --- a/src/stlink-lib/usb.h +++ b/src/stlink-lib/usb.h @@ -1,6 +1,7 @@ /* - * File: usb.h - * Author: karl + * File: usb.h + * + * */ #ifndef USB_H From dbe13dedae12059fe5ee7b80848d564f82151f0e Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Wed, 7 Jun 2023 23:12:00 +0200 Subject: [PATCH 447/503] [doc] Added header comments for lib modules - common.c/.h - sg.c/.h - usb.c/.h --- src/stlink-lib/common.c | 9 +++++++++ src/stlink-lib/common.h | 5 ++++- src/stlink-lib/sg.c | 2 ++ src/stlink-lib/sg.h | 2 ++ src/stlink-lib/usb.c | 2 +- src/stlink-lib/usb.h | 2 +- 6 files changed, 19 insertions(+), 3 deletions(-) diff --git a/src/stlink-lib/common.c b/src/stlink-lib/common.c index 43d2b9a9e..479aa4943 100644 --- a/src/stlink-lib/common.c +++ b/src/stlink-lib/common.c @@ -1,3 +1,12 @@ +/* == nightwalker-87: TODO: CONTENT AND USE OF THIS SOURCE FILE IS TO BE VERIFIED (07.06.2023) == */ +/* TODO: This file should be split up into new or existing modules. */ + +/* + * File: common.c + * + * + */ + #include #include #include diff --git a/src/stlink-lib/common.h b/src/stlink-lib/common.h index c60b49199..1f7e0804d 100644 --- a/src/stlink-lib/common.h +++ b/src/stlink-lib/common.h @@ -1,7 +1,10 @@ +/* == nightwalker-87: TODO: CONTENT AND USE OF THIS SOURCE FILE IS TO BE VERIFIED (07.06.2023) == */ +/* TODO: This file should be split up into new or existing modules. */ + /* * File: common.h * - * General helper functions + * */ #ifndef COMMON_H diff --git a/src/stlink-lib/sg.c b/src/stlink-lib/sg.c index 7c16a5336..4db8c6164 100644 --- a/src/stlink-lib/sg.c +++ b/src/stlink-lib/sg.c @@ -1,3 +1,5 @@ +/* == nightwalker-87: TODO: CONTENT AND USE OF THIS SOURCE FILE IS TO BE VERIFIED (07.06.2023) == */ + /* * Copyright (c) 2010 "Capt'ns Missing Link" Authors. All rights reserved. * Use of this source code is governed by a BSD-style diff --git a/src/stlink-lib/sg.h b/src/stlink-lib/sg.h index ce69f7a09..1ab433142 100644 --- a/src/stlink-lib/sg.h +++ b/src/stlink-lib/sg.h @@ -1,3 +1,5 @@ +/* == nightwalker-87: TODO: CONTENT AND USE OF THIS HEADER FILE IS TO BE VERIFIED (07.06.2023) == */ + /* * File: sg.h * diff --git a/src/stlink-lib/usb.c b/src/stlink-lib/usb.c index e9f45574f..9dc4a0ebd 100644 --- a/src/stlink-lib/usb.c +++ b/src/stlink-lib/usb.c @@ -1,7 +1,7 @@ /* * File: usb.c * - * + * USB commands & interaction with ST-LINK devices */ #include diff --git a/src/stlink-lib/usb.h b/src/stlink-lib/usb.h index 55d506c5b..83c0c2481 100644 --- a/src/stlink-lib/usb.h +++ b/src/stlink-lib/usb.h @@ -1,7 +1,7 @@ /* * File: usb.h * - * + * USB commands & interaction with ST-LINK devices */ #ifndef USB_H From 67ae7a12d8636795f08f1004bf5cd26f596e1eee Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Fri, 9 Jun 2023 01:16:18 +0200 Subject: [PATCH 448/503] Added comments for testing modules --- README.md | 2 +- tests/flash.c | 2 ++ tests/sg.c | 2 ++ tests/usb.c | 2 ++ 4 files changed, 7 insertions(+), 1 deletion(-) diff --git a/README.md b/README.md index e103ac301..6d188f0df 100644 --- a/README.md +++ b/README.md @@ -78,7 +78,7 @@ We recommend to install `stlink-tools` from the package repository of the used d - Alpine Linux: [(Link)](https://pkgs.alpinelinux.org/packages?name=stlink) - Fedora: [(Link)](https://src.fedoraproject.org/rpms/stlink) - FreeBSD: Users can install from [freshports](https://www.freshports.org/devel/stlink) -- MacOS: **Support for macOS will end with v1.7.1.** Please use v1.7.0 (current ***master*** branch) and the related documentation instead. +- MacOS: **Support for macOS will end with v1.8.0.** Please use v1.7.0 (current ***master*** branch) and the related documentation instead. ## Installation from source (advanced users) diff --git a/tests/flash.c b/tests/flash.c index f66428dcd..a40be0c74 100644 --- a/tests/flash.c +++ b/tests/flash.c @@ -1,3 +1,5 @@ +/* == nightwalker-87: TODO: CONTENT AND USE OF THIS SOURCE FILE IS TO BE VERIFIED (07.06.2023) == */ + #include #include #include diff --git a/tests/sg.c b/tests/sg.c index cd601b6d6..32dcd9a62 100644 --- a/tests/sg.c +++ b/tests/sg.c @@ -1,3 +1,5 @@ +/* == nightwalker-87: TODO: CONTENT AND USE OF THIS SOURCE FILE IS TO BE VERIFIED (07.06.2023) == */ + #include #include #include diff --git a/tests/usb.c b/tests/usb.c index 2d928e5f0..56f0d9c1f 100644 --- a/tests/usb.c +++ b/tests/usb.c @@ -1,3 +1,5 @@ +/* == nightwalker-87: TODO: CONTENT AND USE OF THIS SOURCE FILE IS TO BE VERIFIED (07.06.2023) == */ + #include #include #include From be2e7e3883646eadbda4e2a56bdb21f84c06444d Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Fri, 9 Jun 2023 01:28:22 +0200 Subject: [PATCH 449/503] [refactoring] Clean-up for stlink-lib - Ensure proper function declaration - Moved some functions to related modules - Checked & revised header includes - Renamed "md5" to "lib_md5" - New source file "md5" --- CMakeLists.txt | 3 +- inc/stlink.h | 18 +-- src/st-util/gdb-server.c | 3 +- src/stlink-gui/gui.c | 1 + src/stlink-lib/calculate.c | 1 + src/stlink-lib/chipid.c | 13 +- src/stlink-lib/chipid.h | 3 - src/stlink-lib/common.c | 86 +--------- src/stlink-lib/common.h | 23 --- src/stlink-lib/common_flash.c | 32 ++-- src/stlink-lib/common_flash.h | 43 +++-- src/stlink-lib/flash_loader.c | 9 +- src/stlink-lib/flash_loader.h | 4 - src/stlink-lib/helper.c | 15 +- src/stlink-lib/helper.h | 2 + src/stlink-lib/lib_md5.c | 280 ++++++++++++++++++++++++++++++++ src/stlink-lib/lib_md5.h | 68 ++++++++ src/stlink-lib/logging.c | 12 +- src/stlink-lib/logging.h | 3 + src/stlink-lib/map_file.c | 46 +++++- src/stlink-lib/map_file.h | 1 + src/stlink-lib/md5.c | 293 +++------------------------------- src/stlink-lib/md5.h | 63 +------- src/stlink-lib/option_bytes.c | 8 +- src/stlink-lib/option_bytes.h | 3 - src/stlink-lib/read_write.c | 2 + src/stlink-lib/sg.c | 14 +- src/stlink-lib/sg.h | 3 +- src/stlink-lib/usb.c | 25 +-- src/stlink-lib/usb.h | 2 - 30 files changed, 554 insertions(+), 525 deletions(-) delete mode 100644 src/stlink-lib/common.h create mode 100644 src/stlink-lib/lib_md5.c create mode 100644 src/stlink-lib/lib_md5.h diff --git a/CMakeLists.txt b/CMakeLists.txt index 4ff18b815..2a82ea983 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -172,10 +172,10 @@ set(STLINK_HEADERS src/stlink-lib/chipid.h src/stlink-lib/commands.h src/stlink-lib/common_flash.h - src/stlink-lib/common.h src/stlink-lib/flash_loader.h src/stlink-lib/helper.h src/stlink-lib/libusb_settings.h + src/stlink-lib/lib_md5.h src/stlink-lib/logging.h src/stlink-lib/map_file.h src/stlink-lib/md5.h @@ -194,6 +194,7 @@ set(STLINK_SOURCE src/stlink-lib/helper.c src/stlink-lib/logging.c src/stlink-lib/map_file.c + src/stlink-lib/lib_md5.c src/stlink-lib/md5.c src/stlink-lib/option_bytes.c src/stlink-lib/read_write.c diff --git a/inc/stlink.h b/inc/stlink.h index 2ed34a074..b2516c90c 100644 --- a/inc/stlink.h +++ b/inc/stlink.h @@ -11,8 +11,8 @@ #include #include -#include "stm32.h" -#include "stm32flash.h" +#include +#include #ifdef __cplusplus extern "C" { @@ -263,24 +263,13 @@ int32_t stlink_set_swdclk(stlink_t *sl, int32_t freq_khz); int32_t stlink_trace_enable(stlink_t* sl, uint32_t frequency); int32_t stlink_trace_disable(stlink_t* sl); int32_t stlink_trace_read(stlink_t* sl, uint8_t* buf, size_t size); -int32_t stlink_erase_flash_mass(stlink_t* sl); -int32_t stlink_erase_flash_section(stlink_t *sl, stm32_addr_t base_addr, size_t size, bool align_size); -int32_t stlink_write_flash(stlink_t* sl, stm32_addr_t address, uint8_t* data, uint32_t length, uint8_t eraseonly); int32_t stlink_parse_ihex(const char* path, uint8_t erased_pattern, uint8_t * * mem, size_t * size, uint32_t * begin); uint8_t stlink_get_erased_pattern(stlink_t *sl); -int32_t stlink_mwrite_flash(stlink_t *sl, uint8_t* data, uint32_t length, stm32_addr_t addr); -int32_t stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr); int32_t stlink_mwrite_sram(stlink_t *sl, uint8_t* data, uint32_t length, stm32_addr_t addr); int32_t stlink_fwrite_sram(stlink_t *sl, const char* path, stm32_addr_t addr); -int32_t stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, uint32_t length); - //int32_t stlink_chip_id(stlink_t *sl, uint32_t *chip_id); int32_t stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid); - -int32_t stlink_erase_flash_page(stlink_t* sl, stm32_addr_t flashaddr); uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr); -int32_t stlink_check_address_range_validity(stlink_t *sl, stm32_addr_t addr, size_t size); -int32_t stlink_check_address_alignment(stlink_t *sl, stm32_addr_t addr); uint16_t read_uint16(const unsigned char *c, const int32_t pt); //void stlink_core_stat(stlink_t *sl); void stlink_print_data(stlink_t *sl); @@ -293,7 +282,6 @@ int32_t write_buffer_to_sram(stlink_t *sl, flash_loader_t* fl, const uint8_t* bu int32_t write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size); int32_t stlink_fread(stlink_t* sl, const char* path, bool is_ihex, stm32_addr_t addr, size_t size); int32_t stlink_load_device_params(stlink_t *sl); - int32_t stlink_target_connect(stlink_t *sl, enum connect_type connect); #include @@ -301,8 +289,8 @@ int32_t stlink_target_connect(stlink_t *sl, enum connect_type connect); #include #include #include -#include #include +#include #include #ifdef __cplusplus diff --git a/src/st-util/gdb-server.c b/src/st-util/gdb-server.c index 557a24f5f..431e37eec 100644 --- a/src/st-util/gdb-server.c +++ b/src/st-util/gdb-server.c @@ -29,7 +29,8 @@ #include #include #include -#include "flash_loader.h" +#include +#include #include "gdb-remote.h" #include "gdb-server.h" #include "semihosting.h" diff --git a/src/stlink-gui/gui.c b/src/stlink-gui/gui.c index f0426f577..f1e9382d0 100644 --- a/src/stlink-gui/gui.c +++ b/src/stlink-gui/gui.c @@ -5,6 +5,7 @@ #include #include +#include #include "gui.h" #define MEM_READ_SIZE 1024 diff --git a/src/stlink-lib/calculate.c b/src/stlink-lib/calculate.c index 2a708b551..b13a1c961 100644 --- a/src/stlink-lib/calculate.c +++ b/src/stlink-lib/calculate.c @@ -8,6 +8,7 @@ #include #include "calculate.h" + #include "common_flash.h" uint32_t calculate_F4_sectornum(uint32_t flashaddr) { diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index 65ca2842a..c622abcbb 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -4,16 +4,19 @@ * Chip-ID parametres */ -#include -#include -#include #include +#include #include #include -#include "chipid.h" -#include #include +#include +#include "chipid.h" + +#include "logging.h" + +// #include // TODO: Check use +// #include // TODO: Check use static struct stlink_chipid_params *devicelist; diff --git a/src/stlink-lib/chipid.h b/src/stlink-lib/chipid.h index 9955811fa..d7319f569 100644 --- a/src/stlink-lib/chipid.h +++ b/src/stlink-lib/chipid.h @@ -9,9 +9,6 @@ #include -#include -#include - /* Chipid parametres */ struct stlink_chipid_params { char *dev_type; diff --git a/src/stlink-lib/common.c b/src/stlink-lib/common.c index 479aa4943..d6477281d 100644 --- a/src/stlink-lib/common.c +++ b/src/stlink-lib/common.c @@ -13,18 +13,20 @@ #include #include #include -#include -#include -#include +// #include // TODO: Check use +// #include // TODO: Check use #include -#include + #include "calculate.h" +#include "chipid.h" #include "common_flash.h" +#include "helper.h" +#include "logging.h" #include "map_file.h" #include "md5.h" - -#include "common.h" +#include "register.h" +#include "usb.h" #ifndef O_BINARY #define O_BINARY 0 @@ -1213,78 +1215,6 @@ void stlink_run_at(stlink_t *sl, stm32_addr_t addr) { } } -/* Limit the block size to compare to 0x1800 as anything larger will stall the - * STLINK2 Maybe STLINK V1 needs smaller value! - */ -int32_t check_file(stlink_t *sl, mapped_file_t *mf, stm32_addr_t addr) { - size_t off; - size_t n_cmp = sl->flash_pgsz; - - if (n_cmp > 0x1800) { - n_cmp = 0x1800; - } - - for (off = 0; off < mf->len; off += n_cmp) { - size_t aligned_size; - - size_t cmp_size = n_cmp; // adjust last page size - - if ((off + n_cmp) > mf->len) { - cmp_size = mf->len - off; - } - - aligned_size = cmp_size; - - if (aligned_size & (4 - 1)) { - aligned_size = (cmp_size + 4) & ~(4 - 1); - } - - stlink_read_mem32(sl, addr + (uint32_t)off, (uint16_t)aligned_size); - - if (memcmp(sl->q_buf, mf->base + off, cmp_size)) { - return (-1); - } - } - - return (0); -} - -void md5_calculate(mapped_file_t *mf) { - // calculate md5 checksum of given binary file - Md5Context md5Context; - MD5_HASH md5Hash; - Md5Initialise(&md5Context); - Md5Update(&md5Context, mf->base, (uint32_t)mf->len); - Md5Finalise(&md5Context, &md5Hash); - printf("md5 checksum: "); - - for (int32_t i = 0; i < (int32_t)sizeof(md5Hash); i++) { - printf("%x", md5Hash.bytes[i]); - } - - printf(", "); -} - -void stlink_checksum(mapped_file_t *mp) { - /* checksum that backward compatible with official ST tools */ - uint32_t sum = 0; - uint8_t *mp_byte = (uint8_t *)mp->base; - - for (size_t i = 0; i < mp->len; ++i) { - sum += mp_byte[i]; - } - - printf("stlink checksum: 0x%08x\n", sum); -} - -void stlink_fwrite_finalize(stlink_t *sl, stm32_addr_t addr) { - uint32_t val; - // set PC to the reset routine - stlink_read_debug32(sl, addr + 4, &val); - stlink_write_reg(sl, val, 15); - stlink_run(sl, RUN_NORMAL); -} - static int32_t stlink_read(stlink_t *sl, stm32_addr_t addr, size_t size, save_block_fn fn, void *fn_arg) { diff --git a/src/stlink-lib/common.h b/src/stlink-lib/common.h deleted file mode 100644 index 1f7e0804d..000000000 --- a/src/stlink-lib/common.h +++ /dev/null @@ -1,23 +0,0 @@ -/* == nightwalker-87: TODO: CONTENT AND USE OF THIS SOURCE FILE IS TO BE VERIFIED (07.06.2023) == */ -/* TODO: This file should be split up into new or existing modules. */ - -/* - * File: common.h - * - * - */ - -#ifndef COMMON_H -#define COMMON_H - -#include - -#include "map_file.h" -#include "md5.h" - -int32_t check_file(stlink_t *, mapped_file_t *, stm32_addr_t); -void md5_calculate(mapped_file_t *); -void stlink_checksum(mapped_file_t *); -void stlink_fwrite_finalize(stlink_t *, stm32_addr_t); - -#endif // COMMON_H diff --git a/src/stlink-lib/common_flash.c b/src/stlink-lib/common_flash.c index d2063851f..6ade87311 100644 --- a/src/stlink-lib/common_flash.c +++ b/src/stlink-lib/common_flash.c @@ -5,16 +5,19 @@ */ #include + #include -#include #include +#include #include +#include "common_flash.h" + #include "calculate.h" #include "flash_loader.h" -#include "common_flash.h" +#include "logging.h" #include "map_file.h" -#include "common.h" +#include "md5.h" #define DEBUG_FLASH 0 @@ -742,6 +745,7 @@ void clear_flash_cr_pg(stlink_t *sl, uint32_t bank) { n = read_flash_cr(sl, bank) & ~(1 << bit); stlink_write_debug32(sl, cr_reg, n); } + /* ------------------------------------------------------------------------ */ static void wait_flash_busy_progress(stlink_t *sl) { @@ -1170,7 +1174,7 @@ int32_t stlink_erase_flash_section(stlink_t *sl, stm32_addr_t base_addr, size_t return (-1); } - fprintf(stdout, "-> Flash page at %#x erased (size: %#x)\n", addr, page_size); + fprintf(stdout, "-> Flash page at %#x erased (size: %#x)\r", addr, page_size); fflush(stdout); // check the next page is within the range to erase @@ -1232,8 +1236,7 @@ int32_t stlink_erase_flash_mass(stlink_t *sl) { return (err); } -int32_t stlink_mwrite_flash(stlink_t *sl, uint8_t *data, uint32_t length, - stm32_addr_t addr) { +int32_t stlink_mwrite_flash(stlink_t *sl, uint8_t *data, uint32_t length, stm32_addr_t addr) { /* Write the block in flash at addr */ int32_t err; uint32_t num_empty, idx; @@ -1416,12 +1419,10 @@ int32_t stlink_check_address_alignment(stlink_t *sl, stm32_addr_t addr) { return 0; } -int32_t stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t *base, - uint32_t len, uint8_t eraseonly) { +int32_t stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint32_t len, uint8_t eraseonly) { int32_t ret; flash_loader_t fl; - ILOG("Attempting to write %d (%#x) bytes to stm32 address: %u (%#x)\n", len, - len, addr, addr); + ILOG("Attempting to write %d (%#x) bytes to stm32 address: %u (%#x)\n", len, len, addr, addr); // check addr range is inside the flash stlink_calculate_pagesize(sl, addr); @@ -1438,6 +1439,9 @@ int32_t stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t *base, (uint32_t)(sl->flash_pgsz)); return (-1); } + if ((len % 16 <= 8) & (sl->flash_type == STM32_FLASH_TYPE_L5_U5)) { + len += 8; + } // make sure we've loaded the context with the chip details stlink_core_id(sl); @@ -1464,3 +1468,11 @@ int32_t stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t *base, return (stlink_verify_write_flash(sl, addr, base, len)); } + +void stlink_fwrite_finalize(stlink_t *sl, stm32_addr_t addr) { + uint32_t val; + // set PC to the reset routine + stlink_read_debug32(sl, addr + 4, &val); + stlink_write_reg(sl, val, 15); + stlink_run(sl, RUN_NORMAL); +} diff --git a/src/stlink-lib/common_flash.h b/src/stlink-lib/common_flash.h index 04e9134b5..092bdcbf4 100644 --- a/src/stlink-lib/common_flash.h +++ b/src/stlink-lib/common_flash.h @@ -9,22 +9,45 @@ #include +#define BANK_1 0 +#define BANK_2 1 + +uint32_t get_stm32l0_flash_base(stlink_t *); +uint32_t read_flash_cr(stlink_t *, uint32_t); void lock_flash(stlink_t *); +// static inline int32_t write_flash_sr(stlink_t *sl, uint32_t bank, uint32_t val); void clear_flash_error(stlink_t *); +uint32_t read_flash_sr(stlink_t *sl, uint32_t bank); +uint32_t is_flash_busy(stlink_t *sl); void wait_flash_busy(stlink_t *); int32_t check_flash_error(stlink_t *); +// static inline uint32_t is_flash_locked(stlink_t *sl); +// static void unlock_flash(stlink_t *sl); int32_t unlock_flash_if(stlink_t *); int32_t lock_flash_option(stlink_t *); +// static bool is_flash_option_locked(stlink_t *sl); +// static int32_t unlock_flash_option(stlink_t *sl); int32_t unlock_flash_option_if(stlink_t *); -void write_flash_cr_psiz(stlink_t *, uint32_t, unsigned); -void clear_flash_cr_pg(stlink_t *, unsigned); - -// TODO: move to private defines if possible - -#define BANK_1 0 -#define BANK_2 1 - -uint32_t read_flash_cr(stlink_t *, unsigned); -uint32_t get_stm32l0_flash_base(stlink_t *); +void write_flash_cr_psiz(stlink_t *, uint32_t, uint32_t); +void clear_flash_cr_pg(stlink_t *, uint32_t); +// static void wait_flash_busy_progress(stlink_t *sl); +// static inline void write_flash_ar(stlink_t *sl, uint32_t n, uint32_t bank); +// static inline void write_flash_cr_snb(stlink_t *sl, uint32_t n, uint32_t bank); +// static void set_flash_cr_per(stlink_t *sl, uint32_t bank); +// static void clear_flash_cr_per(stlink_t *sl, uint32_t bank); +// static inline void write_flash_cr_bker_pnb(stlink_t *sl, uint32_t n); +// static void set_flash_cr_strt(stlink_t *sl, uint32_t bank); +// static void set_flash_cr_mer(stlink_t *sl, bool v, uint32_t bank); +int32_t stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr); +int32_t stlink_erase_flash_section(stlink_t *sl, stm32_addr_t base_addr, size_t size, bool align_size); +int32_t stlink_erase_flash_mass(stlink_t *sl); +int32_t stlink_mwrite_flash(stlink_t *sl, uint8_t *data, uint32_t length, stm32_addr_t addr); +int32_t stlink_fwrite_flash(stlink_t *sl, const char *path, stm32_addr_t addr); +int32_t stlink_fcheck_flash(stlink_t *sl, const char *path, stm32_addr_t addr); +int32_t stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, uint32_t length); +int32_t stlink_check_address_range_validity(stlink_t *sl, stm32_addr_t addr, size_t size); +int32_t stlink_check_address_alignment(stlink_t *sl, stm32_addr_t addr); +int32_t stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint32_t len, uint8_t eraseonly); +void stlink_fwrite_finalize(stlink_t *, stm32_addr_t); #endif // COMMON_FLASH_H diff --git a/src/stlink-lib/flash_loader.c b/src/stlink-lib/flash_loader.c index 0f171d223..3472e2a61 100644 --- a/src/stlink-lib/flash_loader.c +++ b/src/stlink-lib/flash_loader.c @@ -11,9 +11,12 @@ #include #include -#include #include "flash_loader.h" + #include "common_flash.h" +#include "helper.h" +#include "logging.h" +#include "register.h" #define FLASH_REGS_BANK2_OFS 0x40 #define FLASH_BANK2_START_ADDR 0x08080000 @@ -757,7 +760,9 @@ int32_t stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t fflush(stdout); } - write_uint32((unsigned char *)&data, *(uint32_t *)(base + off)); + // write_uint32((unsigned char *)&data, *(uint32_t *)(base + off)); + data = 0; + memcpy(&data, base + off, (len - off) < 4 ? (len - off) : 4); stlink_write_debug32(sl, addr + (uint32_t)off, data); wait_flash_busy(sl); // wait for 'busy' bit in FLASH_SR to clear } diff --git a/src/stlink-lib/flash_loader.h b/src/stlink-lib/flash_loader.h index 8888875a7..61a2a0c19 100644 --- a/src/stlink-lib/flash_loader.h +++ b/src/stlink-lib/flash_loader.h @@ -8,10 +8,6 @@ #define FLASH_LOADER_H #include -#include -#include - -#include int32_t stlink_flash_loader_init(stlink_t *sl, flash_loader_t* fl); // static int32_t loader_v_dependent_assignment(stlink_t *sl, diff --git a/src/stlink-lib/helper.c b/src/stlink-lib/helper.c index d7420691a..97d6eb316 100644 --- a/src/stlink-lib/helper.c +++ b/src/stlink-lib/helper.c @@ -1,21 +1,22 @@ +/* == nightwalker-87: TODO: CONTENT AND USE OF THIS SOURCE FILE IS TO BE VERIFIED (07.06.2023) == */ + /* * File: helper.c * * General helper functions */ - -#include -#include -#include - -#include "helper.h" - #ifdef STLINK_HAVE_SYS_TIME_H #include #else #include #endif +#include +#include +#include + +#include "helper.h" + uint32_t time_ms() { struct timeval tv; gettimeofday(&tv, NULL); diff --git a/src/stlink-lib/helper.h b/src/stlink-lib/helper.h index 43a96368d..a42fd480e 100644 --- a/src/stlink-lib/helper.h +++ b/src/stlink-lib/helper.h @@ -1,3 +1,5 @@ +/* == nightwalker-87: TODO: CONTENT AND USE OF THIS SOURCE FILE IS TO BE VERIFIED (07.06.2023) == */ + /* * File: helper.h * diff --git a/src/stlink-lib/lib_md5.c b/src/stlink-lib/lib_md5.c new file mode 100644 index 000000000..42f337ac3 --- /dev/null +++ b/src/stlink-lib/lib_md5.c @@ -0,0 +1,280 @@ +/* + * WjCryptLib_Md5 (https://github.com/WaterJuice/WjCryptLib) + * Implementation of MD5 hash function. Originally written by Alexander Peslyak. + * Modified by WaterJuice retaining Public Domain license. + * This is free and unencumbered software released into the public domain - June 2013 - waterjuice.org + */ + +#include +#include + +#include "lib_md5.h" + +/* INTERNAL FUNCTIONS */ + +/* F, G, H, I + * + * The basic MD5 functions. + * F and G are optimised compared to their RFC 1321 definitions for architectures + * that lack an AND-NOT instruction, just like in Colin Plumb's implementation. + */ +#define F( x, y, z ) ((z) ^ ((x) & ((y) ^ (z)))) +#define G( x, y, z ) ((y) ^ ((z) & ((x) ^ (y)))) +#define H( x, y, z ) ((x) ^ (y) ^ (z)) +#define I( x, y, z ) ((y) ^ ((x) | ~(z))) + +/* STEP: The MD5 transformation for all four rounds. */ +#define STEP( f, a, b, c, d, x, t, s ) \ + (a) += f((b), (c), (d)) + (x) + (t); \ + (a) = (((a) << (s)) | (((a) & 0xffffffff) >> (32 - (s)))); \ + (a) += (b); + +/* TransformFunction + * This processes one or more 64-byte data blocks, but does NOT update the bit counters. + * There are no alignment requirements. + */ +static void* TransformFunction(Md5Context* ctx, void const* data, uintmax_t size) { + uint8_t* ptr; + uint32_t a; + uint32_t b; + uint32_t c; + uint32_t d; + uint32_t saved_a; + uint32_t saved_b; + uint32_t saved_c; + uint32_t saved_d; + + #define GET(n) (ctx->block[(n)]) + #define SET(n) (ctx->block[(n)] = ((uint32_t)ptr[(n) * 4 + 0] << 0) | \ + ((uint32_t)ptr[(n) * 4 + 1] << 8) | \ + ((uint32_t)ptr[(n) * 4 + 2] << 16) | \ + ((uint32_t)ptr[(n) * 4 + 3] << 24)) + + ptr = (uint8_t*)data; + + a = ctx->a; + b = ctx->b; + c = ctx->c; + d = ctx->d; + + do { + saved_a = a; + saved_b = b; + saved_c = c; + saved_d = d; + + // Round 1 + STEP( F, a, b, c, d, SET(0), 0xd76aa478, 7 ) + STEP( F, d, a, b, c, SET(1), 0xe8c7b756, 12 ) + STEP( F, c, d, a, b, SET(2), 0x242070db, 17 ) + STEP( F, b, c, d, a, SET(3), 0xc1bdceee, 22 ) + STEP( F, a, b, c, d, SET(4), 0xf57c0faf, 7 ) + STEP( F, d, a, b, c, SET(5), 0x4787c62a, 12 ) + STEP( F, c, d, a, b, SET(6), 0xa8304613, 17 ) + STEP( F, b, c, d, a, SET(7), 0xfd469501, 22 ) + STEP( F, a, b, c, d, SET(8 ), 0x698098d8, 7 ) + STEP( F, d, a, b, c, SET(9 ), 0x8b44f7af, 12 ) + STEP( F, c, d, a, b, SET(10 ), 0xffff5bb1, 17 ) + STEP( F, b, c, d, a, SET(11 ), 0x895cd7be, 22 ) + STEP( F, a, b, c, d, SET(12 ), 0x6b901122, 7 ) + STEP( F, d, a, b, c, SET(13 ), 0xfd987193, 12 ) + STEP( F, c, d, a, b, SET(14 ), 0xa679438e, 17 ) + STEP( F, b, c, d, a, SET(15 ), 0x49b40821, 22 ) + + // Round 2 + STEP( G, a, b, c, d, GET(1), 0xf61e2562, 5 ) + STEP( G, d, a, b, c, GET(6), 0xc040b340, 9 ) + STEP( G, c, d, a, b, GET(11), 0x265e5a51, 14 ) + STEP( G, b, c, d, a, GET(0), 0xe9b6c7aa, 20 ) + STEP( G, a, b, c, d, GET(5), 0xd62f105d, 5 ) + STEP( G, d, a, b, c, GET(10), 0x02441453, 9 ) + STEP( G, c, d, a, b, GET(15), 0xd8a1e681, 14 ) + STEP( G, b, c, d, a, GET(4), 0xe7d3fbc8, 20 ) + STEP( G, a, b, c, d, GET(9), 0x21e1cde6, 5 ) + STEP( G, d, a, b, c, GET(14), 0xc33707d6, 9 ) + STEP( G, c, d, a, b, GET(3), 0xf4d50d87, 14 ) + STEP( G, b, c, d, a, GET(8), 0x455a14ed, 20 ) + STEP( G, a, b, c, d, GET(13), 0xa9e3e905, 5 ) + STEP( G, d, a, b, c, GET(2), 0xfcefa3f8, 9 ) + STEP( G, c, d, a, b, GET(7), 0x676f02d9, 14 ) + STEP( G, b, c, d, a, GET(12), 0x8d2a4c8a, 20 ) + + // Round 3 + STEP( H, a, b, c, d, GET(5), 0xfffa3942, 4 ) + STEP( H, d, a, b, c, GET(8), 0x8771f681, 11 ) + STEP( H, c, d, a, b, GET(11), 0x6d9d6122, 16 ) + STEP( H, b, c, d, a, GET(14), 0xfde5380c, 23 ) + STEP( H, a, b, c, d, GET(1), 0xa4beea44, 4 ) + STEP( H, d, a, b, c, GET(4), 0x4bdecfa9, 11 ) + STEP( H, c, d, a, b, GET(7), 0xf6bb4b60, 16 ) + STEP( H, b, c, d, a, GET(10), 0xbebfbc70, 23 ) + STEP( H, a, b, c, d, GET(13), 0x289b7ec6, 4 ) + STEP( H, d, a, b, c, GET(0), 0xeaa127fa, 11 ) + STEP( H, c, d, a, b, GET(3), 0xd4ef3085, 16 ) + STEP( H, b, c, d, a, GET(6), 0x04881d05, 23 ) + STEP( H, a, b, c, d, GET(9), 0xd9d4d039, 4 ) + STEP( H, d, a, b, c, GET(12), 0xe6db99e5, 11 ) + STEP( H, c, d, a, b, GET(15), 0x1fa27cf8, 16 ) + STEP( H, b, c, d, a, GET(2), 0xc4ac5665, 23 ) + + // Round 4 + STEP( I, a, b, c, d, GET(0), 0xf4292244, 6 ) + STEP( I, d, a, b, c, GET(7), 0x432aff97, 10 ) + STEP( I, c, d, a, b, GET(14), 0xab9423a7, 15 ) + STEP( I, b, c, d, a, GET(5), 0xfc93a039, 21 ) + STEP( I, a, b, c, d, GET(12), 0x655b59c3, 6 ) + STEP( I, d, a, b, c, GET(3), 0x8f0ccc92, 10 ) + STEP( I, c, d, a, b, GET(10), 0xffeff47d, 15 ) + STEP( I, b, c, d, a, GET(1), 0x85845dd1, 21 ) + STEP( I, a, b, c, d, GET(8), 0x6fa87e4f, 6 ) + STEP( I, d, a, b, c, GET(15), 0xfe2ce6e0, 10 ) + STEP( I, c, d, a, b, GET(6), 0xa3014314, 15 ) + STEP( I, b, c, d, a, GET(13), 0x4e0811a1, 21 ) + STEP( I, a, b, c, d, GET(4), 0xf7537e82, 6 ) + STEP( I, d, a, b, c, GET(11), 0xbd3af235, 10 ) + STEP( I, c, d, a, b, GET(2), 0x2ad7d2bb, 15 ) + STEP( I, b, c, d, a, GET(9), 0xeb86d391, 21 ) + + a += saved_a; + b += saved_b; + c += saved_c; + d += saved_d; + + ptr += 64; + } while ( size -= 64 ); + + ctx->a = a; + ctx->b = b; + ctx->c = c; + ctx->d = d; + + #undef GET + #undef SET + + return(ptr); +} + +/* EXPORTED FUNCTIONS */ + +/* Md5Initialise + * Initialises an MD5 Context. + * Use this to initialise/reset a context. + */ +void Md5Initialise(Md5Context* Context /* [out] */) { + Context->a = 0x67452301; + Context->b = 0xefcdab89; + Context->c = 0x98badcfe; + Context->d = 0x10325476; + + Context->lo = 0; + Context->hi = 0; +} + +/* Md5Update + * Adds data to the MD5 context. + * This will process the data and update the internal state of the context. + * Keep on calling this function until all the data has been added. + * Then call Md5Finalise to calculate the hash. + */ +void Md5Update(Md5Context* Context /* [in out] */, void const* Buffer /* [in] */, uint32_t BufferSize /* [in] */) { + uint32_t saved_lo; + uint32_t used; + uint32_t free; + + saved_lo = Context->lo; + + if ((Context->lo = (saved_lo + BufferSize) & 0x1fffffff) < saved_lo) { + Context->hi++; + } + + Context->hi += (uint32_t)(BufferSize >> 29); + + used = saved_lo & 0x3f; + + if ( used ) { + free = 64 - used; + + if ( BufferSize < free ) { + memcpy( &Context->buffer[used], Buffer, BufferSize ); + return; + } + + memcpy( &Context->buffer[used], Buffer, free ); + Buffer = (uint8_t*)Buffer + free; + BufferSize -= free; + TransformFunction(Context, Context->buffer, 64); + } + + if ( BufferSize >= 64 ) { + Buffer = TransformFunction( Context, Buffer, BufferSize & ~(uint32_t)0x3f ); + BufferSize &= 0x3f; + } + + memcpy( Context->buffer, Buffer, BufferSize ); +} + +/* Md5Finalise + * Performs the final calculation of the hash and returns the digest + * (16 byte buffer containing 128bit hash). + * After calling this, Md5Initialised must be used to reuse the context. + */ +void Md5Finalise(Md5Context* Context /* [in out] */, MD5_HASH* Digest /* [in] */) { + uint32_t used; + uint32_t free; + + used = Context->lo & 0x3f; + + Context->buffer[used++] = 0x80; + + free = 64 - used; + + if (free < 8) { + memset( &Context->buffer[used], 0, free ); + TransformFunction( Context, Context->buffer, 64 ); + used = 0; + free = 64; + } + + memset( &Context->buffer[used], 0, free - 8 ); + + Context->lo <<= 3; + Context->buffer[56] = (uint8_t)(Context->lo); + Context->buffer[57] = (uint8_t)(Context->lo >> 8); + Context->buffer[58] = (uint8_t)(Context->lo >> 16); + Context->buffer[59] = (uint8_t)(Context->lo >> 24); + Context->buffer[60] = (uint8_t)(Context->hi); + Context->buffer[61] = (uint8_t)(Context->hi >> 8); + Context->buffer[62] = (uint8_t)(Context->hi >> 16); + Context->buffer[63] = (uint8_t)(Context->hi >> 24); + + TransformFunction( Context, Context->buffer, 64 ); + + Digest->bytes[0] = (uint8_t)(Context->a); + Digest->bytes[1] = (uint8_t)(Context->a >> 8); + Digest->bytes[2] = (uint8_t)(Context->a >> 16); + Digest->bytes[3] = (uint8_t)(Context->a >> 24); + Digest->bytes[4] = (uint8_t)(Context->b); + Digest->bytes[5] = (uint8_t)(Context->b >> 8); + Digest->bytes[6] = (uint8_t)(Context->b >> 16); + Digest->bytes[7] = (uint8_t)(Context->b >> 24); + Digest->bytes[8] = (uint8_t)(Context->c); + Digest->bytes[9] = (uint8_t)(Context->c >> 8); + Digest->bytes[10] = (uint8_t)(Context->c >> 16); + Digest->bytes[11] = (uint8_t)(Context->c >> 24); + Digest->bytes[12] = (uint8_t)(Context->d); + Digest->bytes[13] = (uint8_t)(Context->d >> 8); + Digest->bytes[14] = (uint8_t)(Context->d >> 16); + Digest->bytes[15] = (uint8_t)(Context->d >> 24); +} + +/* Md5Calculate + * Combines Md5Initialise, Md5Update, and Md5Finalise into one function. + * Calculates the MD5 hash of the buffer. + */ +void Md5Calculate(void const* Buffer /* [in] */, uint32_t BufferSize /* [in] */, MD5_HASH* Digest /* [in] */) { + Md5Context context; + + Md5Initialise( &context ); + Md5Update( &context, Buffer, BufferSize ); + Md5Finalise( &context, Digest ); +} diff --git a/src/stlink-lib/lib_md5.h b/src/stlink-lib/lib_md5.h new file mode 100644 index 000000000..abe1131ae --- /dev/null +++ b/src/stlink-lib/lib_md5.h @@ -0,0 +1,68 @@ +/* + * WjCryptLib_Md5 (https://github.com/WaterJuice/WjCryptLib) + * Implementation of MD5 hash function. Originally written by Alexander Peslyak. + * Modified by WaterJuice retaining Public Domain license. + * This is free and unencumbered software released into the public domain - June 2013 - waterjuice.org + */ + +#ifndef LIB_MD5_H +#define LIB_MD5_H + +#pragma once + +#include +#include + +/* TYPES */ + +/* Md5Context + * This must be initialised using Md5Initialised. + * Do not modify the contents of this structure directly. + */ +typedef struct { + uint32_t lo; + uint32_t hi; + uint32_t a; + uint32_t b; + uint32_t c; + uint32_t d; + uint8_t buffer[64]; + uint32_t block[16]; +} Md5Context; + +#define MD5_HASH_SIZE (128 / 8) + +typedef struct { + uint8_t bytes [MD5_HASH_SIZE]; +} MD5_HASH; + +/* PUBLIC FUNCTIONS */ + +/* Md5Initialise + * Initialises an MD5 Context. + * Use this to initialise/reset a context. + */ +void Md5Initialise(Md5Context* Context /* [out] */); + +/* Md5Update + * Adds data to the MD5 context. + * This will process the data and update the internal state of the context. + * Keep on calling this function until all the data has been added. + * Then call Md5Finalise to calculate the hash. + */ +void Md5Update(Md5Context* Context /* [in out] */, void const* Buffer /* [in] */, uint32_t BufferSize /* [in] */); + +/* Md5Finalise + * Performs the final calculation of the hash and returns the digest + * (16 byte buffer containing 128bit hash). + * After calling this, Md5Initialised must be used to reuse the context. + */ +void Md5Finalise(Md5Context* Context /* [in out] */, MD5_HASH* Digest /* [in] */); + +/* Md5Calculate + * Combines Md5Initialise, Md5Update, and Md5Finalise into one function. + * Calculates the MD5 hash of the buffer. + */ +void Md5Calculate(void const* Buffer /* [in] */, uint32_t BufferSize /* [in] */, MD5_HASH* Digest /* [in] */); + +#endif // LIB_MD5_H \ No newline at end of file diff --git a/src/stlink-lib/logging.c b/src/stlink-lib/logging.c index 1463eb925..92092f3d0 100644 --- a/src/stlink-lib/logging.c +++ b/src/stlink-lib/logging.c @@ -1,15 +1,15 @@ /* - * UglyLogging + * File: logging.c * - * Slow, yet another wheel reinvented, but enough to make the rest of our code pretty enough. + * UglyLogging: Slow, yet another wheel reinvented, but enough to make the rest of our code pretty enough. */ -#include -#include +#define __STDC_WANT_LIB_EXT1__ 1 + #include #include -#include -#define __STDC_WANT_LIB_EXT1__ 1 + +#include #include #include "logging.h" diff --git a/src/stlink-lib/logging.h b/src/stlink-lib/logging.h index 471933096..d07db797d 100644 --- a/src/stlink-lib/logging.h +++ b/src/stlink-lib/logging.h @@ -1,4 +1,7 @@ /* + * File: logging.h + * + * UglyLogging: Slow, yet another wheel reinvented, but enough to make the rest of our code pretty enough. * Ugly, low performance, configurable level, logging "framework" */ diff --git a/src/stlink-lib/map_file.c b/src/stlink-lib/map_file.c index cfd2d1876..5e3d14a5d 100644 --- a/src/stlink-lib/map_file.c +++ b/src/stlink-lib/map_file.c @@ -4,24 +4,62 @@ * File mapping */ -#include #include +#include +#include + +#include #include #include #include -#include "logging.h" #include "map_file.h" -#include "md5.h" #ifndef O_BINARY #define O_BINARY 0 #endif +// 1 GB max file size #ifndef MAX_FILE_SIZE -#define MAX_FILE_SIZE (1<<20) // 1 GB max file size +#define MAX_FILE_SIZE (1<<20) #endif +/* Limit the block size to compare to 0x1800 as anything larger will stall the + * STLINK2 Maybe STLINK V1 needs smaller value! + */ +int32_t check_file(stlink_t *sl, mapped_file_t *mf, stm32_addr_t addr) { + size_t off; + size_t n_cmp = sl->flash_pgsz; + + if (n_cmp > 0x1800) { + n_cmp = 0x1800; + } + + for (off = 0; off < mf->len; off += n_cmp) { + size_t aligned_size; + + size_t cmp_size = n_cmp; // adjust last page size + + if ((off + n_cmp) > mf->len) { + cmp_size = mf->len - off; + } + + aligned_size = cmp_size; + + if (aligned_size & (4 - 1)) { + aligned_size = (cmp_size + 4) & ~(4 - 1); + } + + stlink_read_mem32(sl, addr + (uint32_t)off, (uint16_t)aligned_size); + + if (memcmp(sl->q_buf, mf->base + off, cmp_size)) { + return (-1); + } + } + + return (0); +} + int32_t map_file(mapped_file_t *mf, const char *path) { int32_t error = -1; struct stat st; diff --git a/src/stlink-lib/map_file.h b/src/stlink-lib/map_file.h index b33ebf5db..ddedad93c 100644 --- a/src/stlink-lib/map_file.h +++ b/src/stlink-lib/map_file.h @@ -28,6 +28,7 @@ typedef struct mapped_file { #define MAPPED_FILE_INITIALIZER \ { NULL, 0 } +int32_t check_file(stlink_t *, mapped_file_t *, stm32_addr_t); int32_t map_file(mapped_file_t *, const char *); void unmap_file(mapped_file_t *); diff --git a/src/stlink-lib/md5.c b/src/stlink-lib/md5.c index f7af43ac3..070d9af91 100644 --- a/src/stlink-lib/md5.c +++ b/src/stlink-lib/md5.c @@ -1,10 +1,3 @@ -/* - * WjCryptLib_Md5 (https://github.com/WaterJuice/WjCryptLib) - * Implementation of MD5 hash function. Originally written by Alexander Peslyak. - * Modified by WaterJuice retaining Public Domain license. - * This is free and unencumbered software released into the public domain - June 2013 - waterjuice.org - */ - /* * File: md5.c * @@ -12,275 +5,37 @@ */ #include -#include +#include #include "md5.h" -/* INTERNAL FUNCTIONS */ - -/* F, G, H, I - * - * The basic MD5 functions. - * F and G are optimised compared to their RFC 1321 definitions for architectures - * that lack an AND-NOT instruction, just like in Colin Plumb's implementation. - */ -#define F( x, y, z ) ((z) ^ ((x) & ((y) ^ (z)))) -#define G( x, y, z ) ((y) ^ ((z) & ((x) ^ (y)))) -#define H( x, y, z ) ((x) ^ (y) ^ (z)) -#define I( x, y, z ) ((y) ^ ((x) | ~(z))) - -/* STEP: The MD5 transformation for all four rounds. */ -#define STEP( f, a, b, c, d, x, t, s ) \ - (a) += f((b), (c), (d)) + (x) + (t); \ - (a) = (((a) << (s)) | (((a) & 0xffffffff) >> (32 - (s)))); \ - (a) += (b); - -/* TransformFunction - * This processes one or more 64-byte data blocks, but does NOT update the bit counters. - * There are no alignment requirements. - */ -static void* TransformFunction(Md5Context* ctx, void const* data, uintmax_t size) { - uint8_t* ptr; - uint32_t a; - uint32_t b; - uint32_t c; - uint32_t d; - uint32_t saved_a; - uint32_t saved_b; - uint32_t saved_c; - uint32_t saved_d; - - #define GET(n) (ctx->block[(n)]) - #define SET(n) (ctx->block[(n)] = ((uint32_t)ptr[(n) * 4 + 0] << 0) | \ - ((uint32_t)ptr[(n) * 4 + 1] << 8) | \ - ((uint32_t)ptr[(n) * 4 + 2] << 16) | \ - ((uint32_t)ptr[(n) * 4 + 3] << 24)) - - ptr = (uint8_t*)data; - - a = ctx->a; - b = ctx->b; - c = ctx->c; - d = ctx->d; - - do { - saved_a = a; - saved_b = b; - saved_c = c; - saved_d = d; - - // Round 1 - STEP( F, a, b, c, d, SET(0), 0xd76aa478, 7 ) - STEP( F, d, a, b, c, SET(1), 0xe8c7b756, 12 ) - STEP( F, c, d, a, b, SET(2), 0x242070db, 17 ) - STEP( F, b, c, d, a, SET(3), 0xc1bdceee, 22 ) - STEP( F, a, b, c, d, SET(4), 0xf57c0faf, 7 ) - STEP( F, d, a, b, c, SET(5), 0x4787c62a, 12 ) - STEP( F, c, d, a, b, SET(6), 0xa8304613, 17 ) - STEP( F, b, c, d, a, SET(7), 0xfd469501, 22 ) - STEP( F, a, b, c, d, SET(8 ), 0x698098d8, 7 ) - STEP( F, d, a, b, c, SET(9 ), 0x8b44f7af, 12 ) - STEP( F, c, d, a, b, SET(10 ), 0xffff5bb1, 17 ) - STEP( F, b, c, d, a, SET(11 ), 0x895cd7be, 22 ) - STEP( F, a, b, c, d, SET(12 ), 0x6b901122, 7 ) - STEP( F, d, a, b, c, SET(13 ), 0xfd987193, 12 ) - STEP( F, c, d, a, b, SET(14 ), 0xa679438e, 17 ) - STEP( F, b, c, d, a, SET(15 ), 0x49b40821, 22 ) - - // Round 2 - STEP( G, a, b, c, d, GET(1), 0xf61e2562, 5 ) - STEP( G, d, a, b, c, GET(6), 0xc040b340, 9 ) - STEP( G, c, d, a, b, GET(11), 0x265e5a51, 14 ) - STEP( G, b, c, d, a, GET(0), 0xe9b6c7aa, 20 ) - STEP( G, a, b, c, d, GET(5), 0xd62f105d, 5 ) - STEP( G, d, a, b, c, GET(10), 0x02441453, 9 ) - STEP( G, c, d, a, b, GET(15), 0xd8a1e681, 14 ) - STEP( G, b, c, d, a, GET(4), 0xe7d3fbc8, 20 ) - STEP( G, a, b, c, d, GET(9), 0x21e1cde6, 5 ) - STEP( G, d, a, b, c, GET(14), 0xc33707d6, 9 ) - STEP( G, c, d, a, b, GET(3), 0xf4d50d87, 14 ) - STEP( G, b, c, d, a, GET(8), 0x455a14ed, 20 ) - STEP( G, a, b, c, d, GET(13), 0xa9e3e905, 5 ) - STEP( G, d, a, b, c, GET(2), 0xfcefa3f8, 9 ) - STEP( G, c, d, a, b, GET(7), 0x676f02d9, 14 ) - STEP( G, b, c, d, a, GET(12), 0x8d2a4c8a, 20 ) - - // Round 3 - STEP( H, a, b, c, d, GET(5), 0xfffa3942, 4 ) - STEP( H, d, a, b, c, GET(8), 0x8771f681, 11 ) - STEP( H, c, d, a, b, GET(11), 0x6d9d6122, 16 ) - STEP( H, b, c, d, a, GET(14), 0xfde5380c, 23 ) - STEP( H, a, b, c, d, GET(1), 0xa4beea44, 4 ) - STEP( H, d, a, b, c, GET(4), 0x4bdecfa9, 11 ) - STEP( H, c, d, a, b, GET(7), 0xf6bb4b60, 16 ) - STEP( H, b, c, d, a, GET(10), 0xbebfbc70, 23 ) - STEP( H, a, b, c, d, GET(13), 0x289b7ec6, 4 ) - STEP( H, d, a, b, c, GET(0), 0xeaa127fa, 11 ) - STEP( H, c, d, a, b, GET(3), 0xd4ef3085, 16 ) - STEP( H, b, c, d, a, GET(6), 0x04881d05, 23 ) - STEP( H, a, b, c, d, GET(9), 0xd9d4d039, 4 ) - STEP( H, d, a, b, c, GET(12), 0xe6db99e5, 11 ) - STEP( H, c, d, a, b, GET(15), 0x1fa27cf8, 16 ) - STEP( H, b, c, d, a, GET(2), 0xc4ac5665, 23 ) - - // Round 4 - STEP( I, a, b, c, d, GET(0), 0xf4292244, 6 ) - STEP( I, d, a, b, c, GET(7), 0x432aff97, 10 ) - STEP( I, c, d, a, b, GET(14), 0xab9423a7, 15 ) - STEP( I, b, c, d, a, GET(5), 0xfc93a039, 21 ) - STEP( I, a, b, c, d, GET(12), 0x655b59c3, 6 ) - STEP( I, d, a, b, c, GET(3), 0x8f0ccc92, 10 ) - STEP( I, c, d, a, b, GET(10), 0xffeff47d, 15 ) - STEP( I, b, c, d, a, GET(1), 0x85845dd1, 21 ) - STEP( I, a, b, c, d, GET(8), 0x6fa87e4f, 6 ) - STEP( I, d, a, b, c, GET(15), 0xfe2ce6e0, 10 ) - STEP( I, c, d, a, b, GET(6), 0xa3014314, 15 ) - STEP( I, b, c, d, a, GET(13), 0x4e0811a1, 21 ) - STEP( I, a, b, c, d, GET(4), 0xf7537e82, 6 ) - STEP( I, d, a, b, c, GET(11), 0xbd3af235, 10 ) - STEP( I, c, d, a, b, GET(2), 0x2ad7d2bb, 15 ) - STEP( I, b, c, d, a, GET(9), 0xeb86d391, 21 ) - - a += saved_a; - b += saved_b; - c += saved_c; - d += saved_d; - - ptr += 64; - } while ( size -= 64 ); - - ctx->a = a; - ctx->b = b; - ctx->c = c; - ctx->d = d; - - #undef GET - #undef SET - - return(ptr); -} - -/* EXPORTED FUNCTIONS */ +#include "map_file.h" +#include "lib_md5.h" -/* Md5Initialise - * Initialises an MD5 Context. - * Use this to initialise/reset a context. - */ -void Md5Initialise(Md5Context* Context /* [out] */) { - Context->a = 0x67452301; - Context->b = 0xefcdab89; - Context->c = 0x98badcfe; - Context->d = 0x10325476; - - Context->lo = 0; - Context->hi = 0; -} - -/* Md5Update - * Adds data to the MD5 context. - * This will process the data and update the internal state of the context. - * Keep on calling this function until all the data has been added. - * Then call Md5Finalise to calculate the hash. - */ -void Md5Update(Md5Context* Context /* [in out] */, void const* Buffer /* [in] */, uint32_t BufferSize /* [in] */) { - uint32_t saved_lo; - uint32_t used; - uint32_t free; - - saved_lo = Context->lo; - - if ((Context->lo = (saved_lo + BufferSize) & 0x1fffffff) < saved_lo) { - Context->hi++; - } - - Context->hi += (uint32_t)(BufferSize >> 29); - - used = saved_lo & 0x3f; - - if ( used ) { - free = 64 - used; - - if ( BufferSize < free ) { - memcpy( &Context->buffer[used], Buffer, BufferSize ); - return; - } - - memcpy( &Context->buffer[used], Buffer, free ); - Buffer = (uint8_t*)Buffer + free; - BufferSize -= free; - TransformFunction(Context, Context->buffer, 64); - } +void md5_calculate(mapped_file_t *mf) { + // calculate md5 checksum of given binary file + Md5Context md5Context; + MD5_HASH md5Hash; + Md5Initialise(&md5Context); + Md5Update(&md5Context, mf->base, (uint32_t)mf->len); + Md5Finalise(&md5Context, &md5Hash); + printf("md5 checksum: "); - if ( BufferSize >= 64 ) { - Buffer = TransformFunction( Context, Buffer, BufferSize & ~(uint32_t)0x3f ); - BufferSize &= 0x3f; - } + for (int32_t i = 0; i < (int32_t)sizeof(md5Hash); i++) { + printf("%x", md5Hash.bytes[i]); + } - memcpy( Context->buffer, Buffer, BufferSize ); + printf(", "); } -/* Md5Finalise - * Performs the final calculation of the hash and returns the digest - * (16 byte buffer containing 128bit hash). - * After calling this, Md5Initialised must be used to reuse the context. - */ -void Md5Finalise(Md5Context* Context /* [in out] */, MD5_HASH* Digest /* [in] */) { - uint32_t used; - uint32_t free; - - used = Context->lo & 0x3f; - - Context->buffer[used++] = 0x80; - - free = 64 - used; - - if (free < 8) { - memset( &Context->buffer[used], 0, free ); - TransformFunction( Context, Context->buffer, 64 ); - used = 0; - free = 64; - } - - memset( &Context->buffer[used], 0, free - 8 ); +void stlink_checksum(mapped_file_t *mp) { + /* checksum that backward compatible with official ST tools */ + uint32_t sum = 0; + uint8_t *mp_byte = (uint8_t *)mp->base; - Context->lo <<= 3; - Context->buffer[56] = (uint8_t)(Context->lo); - Context->buffer[57] = (uint8_t)(Context->lo >> 8); - Context->buffer[58] = (uint8_t)(Context->lo >> 16); - Context->buffer[59] = (uint8_t)(Context->lo >> 24); - Context->buffer[60] = (uint8_t)(Context->hi); - Context->buffer[61] = (uint8_t)(Context->hi >> 8); - Context->buffer[62] = (uint8_t)(Context->hi >> 16); - Context->buffer[63] = (uint8_t)(Context->hi >> 24); + for (size_t i = 0; i < mp->len; ++i) { + sum += mp_byte[i]; + } - TransformFunction( Context, Context->buffer, 64 ); - - Digest->bytes[0] = (uint8_t)(Context->a); - Digest->bytes[1] = (uint8_t)(Context->a >> 8); - Digest->bytes[2] = (uint8_t)(Context->a >> 16); - Digest->bytes[3] = (uint8_t)(Context->a >> 24); - Digest->bytes[4] = (uint8_t)(Context->b); - Digest->bytes[5] = (uint8_t)(Context->b >> 8); - Digest->bytes[6] = (uint8_t)(Context->b >> 16); - Digest->bytes[7] = (uint8_t)(Context->b >> 24); - Digest->bytes[8] = (uint8_t)(Context->c); - Digest->bytes[9] = (uint8_t)(Context->c >> 8); - Digest->bytes[10] = (uint8_t)(Context->c >> 16); - Digest->bytes[11] = (uint8_t)(Context->c >> 24); - Digest->bytes[12] = (uint8_t)(Context->d); - Digest->bytes[13] = (uint8_t)(Context->d >> 8); - Digest->bytes[14] = (uint8_t)(Context->d >> 16); - Digest->bytes[15] = (uint8_t)(Context->d >> 24); -} - -/* Md5Calculate - * Combines Md5Initialise, Md5Update, and Md5Finalise into one function. - * Calculates the MD5 hash of the buffer. - */ -void Md5Calculate(void const* Buffer /* [in] */, uint32_t BufferSize /* [in] */, MD5_HASH* Digest /* [in] */) { - Md5Context context; - - Md5Initialise( &context ); - Md5Update( &context, Buffer, BufferSize ); - Md5Finalise( &context, Digest ); -} + printf("stlink checksum: 0x%08x\n", sum); +} \ No newline at end of file diff --git a/src/stlink-lib/md5.h b/src/stlink-lib/md5.h index 23c5d971b..eb36d64cc 100644 --- a/src/stlink-lib/md5.h +++ b/src/stlink-lib/md5.h @@ -1,10 +1,3 @@ -/* - * WjCryptLib_Md5 (https://github.com/WaterJuice/WjCryptLib) - * Implementation of MD5 hash function. Originally written by Alexander Peslyak. - * Modified by WaterJuice retaining Public Domain license. - * This is free and unencumbered software released into the public domain - June 2013 - waterjuice.org - */ - /* * File: md5.h * @@ -14,61 +7,11 @@ #ifndef MD5_H #define MD5_H -#pragma once - #include -#include - -/* TYPES */ - -/* Md5Context - * This must be initialised using Md5Initialised. - * Do not modify the contents of this structure directly. - */ -typedef struct { - uint32_t lo; - uint32_t hi; - uint32_t a; - uint32_t b; - uint32_t c; - uint32_t d; - uint8_t buffer[64]; - uint32_t block[16]; -} Md5Context; - -#define MD5_HASH_SIZE (128 / 8) -typedef struct { - uint8_t bytes [MD5_HASH_SIZE]; -} MD5_HASH; +#include "map_file.h" -/* PUBLIC FUNCTIONS */ - -/* Md5Initialise - * Initialises an MD5 Context. - * Use this to initialise/reset a context. - */ -void Md5Initialise(Md5Context* Context /* [out] */); - -/* Md5Update - * Adds data to the MD5 context. - * This will process the data and update the internal state of the context. - * Keep on calling this function until all the data has been added. - * Then call Md5Finalise to calculate the hash. - */ -void Md5Update(Md5Context* Context /* [in out] */, void const* Buffer /* [in] */, uint32_t BufferSize /* [in] */); - -/* Md5Finalise - * Performs the final calculation of the hash and returns the digest - * (16 byte buffer containing 128bit hash). - * After calling this, Md5Initialised must be used to reuse the context. - */ -void Md5Finalise(Md5Context* Context /* [in out] */, MD5_HASH* Digest /* [in] */); - -/* Md5Calculate - * Combines Md5Initialise, Md5Update, and Md5Finalise into one function. - * Calculates the MD5 hash of the buffer. - */ -void Md5Calculate(void const* Buffer /* [in] */, uint32_t BufferSize /* [in] */, MD5_HASH* Digest /* [in] */); +void md5_calculate(mapped_file_t *); +void stlink_checksum(mapped_file_t *); #endif // MD5_H \ No newline at end of file diff --git a/src/stlink-lib/option_bytes.c b/src/stlink-lib/option_bytes.c index 6a12333cd..624d43a0a 100644 --- a/src/stlink-lib/option_bytes.c +++ b/src/stlink-lib/option_bytes.c @@ -9,11 +9,13 @@ #include #include -#include "common.h" -#include "common_flash.h" -#include "map_file.h" #include "option_bytes.h" +#include "common_flash.h" +#include "flash_loader.h" +#include "logging.h" +#include "map_file.h" +#include "md5.h" /** * Read option control register F0 diff --git a/src/stlink-lib/option_bytes.h b/src/stlink-lib/option_bytes.h index c0a1c9a6d..a58ea3857 100644 --- a/src/stlink-lib/option_bytes.h +++ b/src/stlink-lib/option_bytes.h @@ -8,9 +8,6 @@ #define OPTION_BYTES_H #include -#include - -#include int32_t stlink_read_option_bytes32(stlink_t *sl, uint32_t* option_byte); int32_t stlink_read_option_bytes_boot_add32(stlink_t *sl, uint32_t* option_byte); diff --git a/src/stlink-lib/read_write.c b/src/stlink-lib/read_write.c index f9c060bb2..6ee697d66 100644 --- a/src/stlink-lib/read_write.c +++ b/src/stlink-lib/read_write.c @@ -4,6 +4,8 @@ #include +#include "logging.h" + // Endianness // https://commandcenter.blogspot.com/2012/04/byte-order-fallacy.html // These functions encode and decode little endian uint16 and uint32 values. diff --git a/src/stlink-lib/sg.c b/src/stlink-lib/sg.c index 4db8c6164..860b92b70 100644 --- a/src/stlink-lib/sg.c +++ b/src/stlink-lib/sg.c @@ -1,5 +1,3 @@ -/* == nightwalker-87: TODO: CONTENT AND USE OF THIS SOURCE FILE IS TO BE VERIFIED (07.06.2023) == */ - /* * Copyright (c) 2010 "Capt'ns Missing Link" Authors. All rights reserved. * Use of this source code is governed by a BSD-style @@ -84,17 +82,21 @@ #define __USE_GNU -#include #include #include #include #include -#include +#include +// #include -#include -#include "logging.h" #include "sg.h" +#include "commands.h" +#include "logging.h" +#include "register.h" +#include "usb.h" +// #include + #define STLINK_OK 0x80 #define STLINK_FALSE 0x81 diff --git a/src/stlink-lib/sg.h b/src/stlink-lib/sg.h index 1ab433142..cc3ea725e 100644 --- a/src/stlink-lib/sg.h +++ b/src/stlink-lib/sg.h @@ -1,5 +1,3 @@ -/* == nightwalker-87: TODO: CONTENT AND USE OF THIS HEADER FILE IS TO BE VERIFIED (07.06.2023) == */ - /* * File: sg.h * @@ -12,6 +10,7 @@ #include #include + #include "libusb_settings.h" /* Device access */ diff --git a/src/stlink-lib/usb.c b/src/stlink-lib/usb.c index 9dc4a0ebd..907a32190 100644 --- a/src/stlink-lib/usb.c +++ b/src/stlink-lib/usb.c @@ -4,28 +4,31 @@ * USB commands & interaction with ST-LINK devices */ -#include -#include -#include -#include -#include - #if !defined(_MSC_VER) #include #endif -#include -#include -#include - #if defined(_WIN32) #include #endif +#include +#include +#include +#include + +#include +#include +#include +#include + #include -#include "helper.h" #include "usb.h" +#include "commands.h" +#include "logging.h" +#include "register.h" + enum SCSI_Generic_Direction {SG_DXFER_TO_DEV = 0, SG_DXFER_FROM_DEV = 0x80}; static inline uint32_t le_to_h_u32(const uint8_t* buf) { diff --git a/src/stlink-lib/usb.h b/src/stlink-lib/usb.h index 83c0c2481..b99e46f53 100644 --- a/src/stlink-lib/usb.h +++ b/src/stlink-lib/usb.h @@ -7,10 +7,8 @@ #ifndef USB_H #define USB_H -#include #include -#include #include "libusb_settings.h" #include "logging.h" From fc990648c4a0b91bdea539e699248f59d1157f51 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Fri, 9 Jun 2023 12:55:25 +0200 Subject: [PATCH 450/503] [refactoring] Clean-up for stlink-lib - Ensure proper function declaration - Checked & revised header includes --- src/stlink-lib/calculate.h | 2 -- src/stlink-lib/chipid.c | 1 + src/stlink-lib/chipid.h | 7 +++-- src/stlink-lib/common_flash.h | 2 -- src/stlink-lib/flash_loader.h | 2 -- src/stlink-lib/helper.c | 5 ++-- src/stlink-lib/helper.h | 5 ---- src/stlink-lib/lib_md5.c | 1 + src/stlink-lib/lib_md5.h | 3 -- src/stlink-lib/logging.h | 10 +++---- src/stlink-lib/map_file.h | 6 ++-- src/stlink-lib/md5.c | 1 + src/stlink-lib/md5.h | 2 -- src/stlink-lib/option_bytes.c | 3 +- src/stlink-lib/option_bytes.h | 44 +++++++++++++++++++++------- src/stlink-lib/register.h | 2 +- src/stlink-lib/sg.c | 12 ++++---- src/stlink-lib/sg.h | 42 +++++++++++++++++++++++++++ src/stlink-lib/usb.c | 27 ++++++++++-------- src/stlink-lib/usb.h | 54 +++++++++++++++++++++++++++++------ 20 files changed, 159 insertions(+), 72 deletions(-) diff --git a/src/stlink-lib/calculate.h b/src/stlink-lib/calculate.h index bdff782ae..64dfb51b2 100644 --- a/src/stlink-lib/calculate.h +++ b/src/stlink-lib/calculate.h @@ -7,8 +7,6 @@ #ifndef CALCULATE_H #define CALCULATE_H -#include - uint32_t calculate_F4_sectornum(uint32_t); uint32_t calculate_F7_sectornum(uint32_t); uint32_t calculate_H7_sectornum(stlink_t *, uint32_t, unsigned); diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index c622abcbb..a4abf90d8 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -223,6 +223,7 @@ void init_chipids(char *dir_to_scan) { return; } } + #endif // STLINK_HAVE_DIRENT_H #if defined(_WIN32) && !defined(STLINK_HAVE_DIRENT_H) diff --git a/src/stlink-lib/chipid.h b/src/stlink-lib/chipid.h index d7319f569..a72a40be9 100644 --- a/src/stlink-lib/chipid.h +++ b/src/stlink-lib/chipid.h @@ -7,8 +7,6 @@ #ifndef CHIPID_H #define CHIPID_H -#include - /* Chipid parametres */ struct stlink_chipid_params { char *dev_type; @@ -27,6 +25,9 @@ struct stlink_chipid_params { }; struct stlink_chipid_params *stlink_chipid_get_params(uint32_t chipid); - void init_chipids(char *dir_to_scan); + +void dump_a_chip(struct stlink_chipid_params *dev); +void process_chipfile(char *fname); +void init_chipids(char *dir_to_scan); #endif // CHIPID_H diff --git a/src/stlink-lib/common_flash.h b/src/stlink-lib/common_flash.h index 092bdcbf4..fd1e51b9d 100644 --- a/src/stlink-lib/common_flash.h +++ b/src/stlink-lib/common_flash.h @@ -7,8 +7,6 @@ #ifndef COMMON_FLASH_H #define COMMON_FLASH_H -#include - #define BANK_1 0 #define BANK_2 1 diff --git a/src/stlink-lib/flash_loader.h b/src/stlink-lib/flash_loader.h index 61a2a0c19..06eb53d12 100644 --- a/src/stlink-lib/flash_loader.h +++ b/src/stlink-lib/flash_loader.h @@ -7,8 +7,6 @@ #ifndef FLASH_LOADER_H #define FLASH_LOADER_H -#include - int32_t stlink_flash_loader_init(stlink_t *sl, flash_loader_t* fl); // static int32_t loader_v_dependent_assignment(stlink_t *sl, // const uint8_t **loader_code, size_t *loader_size, diff --git a/src/stlink-lib/helper.c b/src/stlink-lib/helper.c index 97d6eb316..1e756f1de 100644 --- a/src/stlink-lib/helper.c +++ b/src/stlink-lib/helper.c @@ -1,15 +1,14 @@ -/* == nightwalker-87: TODO: CONTENT AND USE OF THIS SOURCE FILE IS TO BE VERIFIED (07.06.2023) == */ - /* * File: helper.c * * General helper functions */ + #ifdef STLINK_HAVE_SYS_TIME_H #include #else #include -#endif +#endif // STLINK_HAVE_SYS_TIME_H #include #include diff --git a/src/stlink-lib/helper.h b/src/stlink-lib/helper.h index a42fd480e..ef374a5b6 100644 --- a/src/stlink-lib/helper.h +++ b/src/stlink-lib/helper.h @@ -1,5 +1,3 @@ -/* == nightwalker-87: TODO: CONTENT AND USE OF THIS SOURCE FILE IS TO BE VERIFIED (07.06.2023) == */ - /* * File: helper.h * @@ -9,10 +7,7 @@ #ifndef HELPER_H #define HELPER_H -#include - uint32_t time_ms(); - int32_t arg_parse_freq(const char *str); #endif // HELPER_H diff --git a/src/stlink-lib/lib_md5.c b/src/stlink-lib/lib_md5.c index 42f337ac3..71703273c 100644 --- a/src/stlink-lib/lib_md5.c +++ b/src/stlink-lib/lib_md5.c @@ -6,6 +6,7 @@ */ #include +#include #include #include "lib_md5.h" diff --git a/src/stlink-lib/lib_md5.h b/src/stlink-lib/lib_md5.h index abe1131ae..7275fd0bd 100644 --- a/src/stlink-lib/lib_md5.h +++ b/src/stlink-lib/lib_md5.h @@ -10,9 +10,6 @@ #pragma once -#include -#include - /* TYPES */ /* Md5Context diff --git a/src/stlink-lib/logging.h b/src/stlink-lib/logging.h index d07db797d..cb49a7af3 100644 --- a/src/stlink-lib/logging.h +++ b/src/stlink-lib/logging.h @@ -8,11 +8,9 @@ #ifndef LOGGING_H #define LOGGING_H -#include - #ifdef __cplusplus extern "C" { -#endif +#endif // __cplusplus enum ugly_loglevel { UDEBUG = 90, @@ -25,7 +23,7 @@ enum ugly_loglevel { #define PRINTF_ARRT __attribute__ ((format (printf, 3, 4))) #else #define PRINTF_ARRT -#endif +#endif // __GNUC__ int32_t ugly_init(int32_t maximum_threshold); int32_t ugly_log(int32_t level, const char *tag, const char *format, ...) PRINTF_ARRT; @@ -48,6 +46,6 @@ int32_t ugly_libusb_log_level(enum ugly_loglevel v); #ifdef __cplusplus } -#endif +#endif // __cplusplus -#endif // LOGGING_H +#endif // LOGGING_H diff --git a/src/stlink-lib/map_file.h b/src/stlink-lib/map_file.h index ddedad93c..ba50e25e9 100644 --- a/src/stlink-lib/map_file.h +++ b/src/stlink-lib/map_file.h @@ -7,17 +7,15 @@ #ifndef MAP_FILE_H #define MAP_FILE_H -#include - #ifndef O_BINARY #define O_BINARY 0 -#endif +#endif // O_BINARY #ifdef STLINK_HAVE_SYS_MMAN_H #include #else #include -#endif +#endif // STLINK_HAVE_SYS_MMAN_H /* Memory mapped file */ typedef struct mapped_file { diff --git a/src/stlink-lib/md5.c b/src/stlink-lib/md5.c index 070d9af91..9481acf0f 100644 --- a/src/stlink-lib/md5.c +++ b/src/stlink-lib/md5.c @@ -5,6 +5,7 @@ */ #include +#include #include #include "md5.h" diff --git a/src/stlink-lib/md5.h b/src/stlink-lib/md5.h index eb36d64cc..f5591e2c3 100644 --- a/src/stlink-lib/md5.h +++ b/src/stlink-lib/md5.h @@ -7,8 +7,6 @@ #ifndef MD5_H #define MD5_H -#include - #include "map_file.h" void md5_calculate(mapped_file_t *); diff --git a/src/stlink-lib/option_bytes.c b/src/stlink-lib/option_bytes.c index 624d43a0a..c84ace348 100644 --- a/src/stlink-lib/option_bytes.c +++ b/src/stlink-lib/option_bytes.c @@ -426,8 +426,7 @@ int32_t stlink_read_option_bytes_boot_add_f7(stlink_t *sl, uint32_t *option_byte * @param option_byte * @return 0 on success, -ve on failure. */ -static int -stlink_write_option_bytes_boot_add_f7(stlink_t *sl, uint32_t option_byte_boot_add) { +static int32_t stlink_write_option_bytes_boot_add_f7(stlink_t *sl, uint32_t option_byte_boot_add) { ILOG("Asked to write option byte boot add %#010x.\n", option_byte_boot_add); return stlink_write_option_control_register1_f7(sl, option_byte_boot_add); } diff --git a/src/stlink-lib/option_bytes.h b/src/stlink-lib/option_bytes.h index a58ea3857..ffeef8a0f 100644 --- a/src/stlink-lib/option_bytes.h +++ b/src/stlink-lib/option_bytes.h @@ -7,19 +7,41 @@ #ifndef OPTION_BYTES_H #define OPTION_BYTES_H -#include - +int32_t stlink_read_option_control_register_f0(stlink_t *sl, uint32_t *option_byte); +// static int32_t stlink_write_option_bytes_f0(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t len); +// static int32_t stlink_write_option_control_register_f0(stlink_t *sl, uint32_t option_cr); +int32_t stlink_read_option_control_register_f2(stlink_t *sl, uint32_t *option_byte); +int32_t stlink_read_option_bytes_f2(stlink_t *sl, uint32_t *option_byte); +int32_t stlink_read_option_control_register_f4(stlink_t *sl, uint32_t *option_byte); +int32_t stlink_read_option_bytes_f4(stlink_t *sl, uint32_t *option_byte); +// static int32_t stlink_write_option_bytes_f4(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint32_t len); +int32_t stlink_read_option_bytes_f7(stlink_t *sl, uint32_t *option_byte); +// static int32_t stlink_write_option_bytes_f7(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint32_t len); +int32_t stlink_read_option_control_register_f7(stlink_t *sl, uint32_t *option_byte); +// static int32_t stlink_write_option_control_register_f7(stlink_t *sl, uint32_t option_cr); +int32_t stlink_read_option_control_register1_f7(stlink_t *sl, uint32_t *option_byte); +// static int32_t stlink_write_option_control_register1_f7(stlink_t *sl, uint32_t option_cr1); +int32_t stlink_read_option_bytes_boot_add_f7(stlink_t *sl, uint32_t *option_byte); +// static int32_t stlink_write_option_bytes_boot_add_f7(stlink_t *sl, uint32_t option_byte_boot_add); +int32_t stlink_read_option_control_register_gx(stlink_t *sl, uint32_t *option_byte); +int32_t stlink_read_option_bytes_gx(stlink_t *sl, uint32_t *option_byte); +// static int32_t stlink_write_option_bytes_gx(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint32_t len); +// static int32_t stlink_write_option_bytes_h7(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint32_t len); +// static int32_t stlink_write_option_bytes_l0(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint32_t len); +// static int32_t stlink_write_option_bytes_l4(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint32_t len); +// static int32_t stlink_write_option_bytes_wb(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint32_t len); +int32_t stlink_read_option_control_register_wb(stlink_t *sl, uint32_t *option_byte); +// static int32_t stlink_write_option_control_register_wb(stlink_t *sl, uint32_t option_cr); +int32_t stlink_read_option_bytes_generic(stlink_t *sl, uint32_t *option_byte); +int32_t stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint32_t len); +int32_t stlink_fwrite_option_bytes(stlink_t *sl, const char *path, stm32_addr_t addr); +int32_t stlink_read_option_control_register32(stlink_t *sl, uint32_t *option_byte); +int32_t stlink_write_option_control_register32(stlink_t *sl, uint32_t option_cr); +int32_t stlink_read_option_control_register1_32(stlink_t *sl, uint32_t *option_byte); +int32_t stlink_write_option_control_register1_32(stlink_t *sl, uint32_t option_cr1); int32_t stlink_read_option_bytes32(stlink_t *sl, uint32_t* option_byte); -int32_t stlink_read_option_bytes_boot_add32(stlink_t *sl, uint32_t* option_byte); -int32_t stlink_read_option_control_register32(stlink_t *sl, uint32_t* option_byte); -int32_t stlink_read_option_control_register1_32(stlink_t *sl, uint32_t* option_byte); - int32_t stlink_write_option_bytes32(stlink_t *sl, uint32_t option_byte); +int32_t stlink_read_option_bytes_boot_add32(stlink_t *sl, uint32_t* option_byte); int32_t stlink_write_option_bytes_boot_add32(stlink_t *sl, uint32_t option_bytes_boot_add); -int32_t stlink_write_option_control_register32(stlink_t *sl, uint32_t option_cr); -int32_t stlink_write_option_control_register1_32(stlink_t *sl, uint32_t option_cr1); - -int32_t stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t len); -int32_t stlink_fwrite_option_bytes(stlink_t *sl, const char* path, stm32_addr_t addr); #endif // OPTION_BYTES_H \ No newline at end of file diff --git a/src/stlink-lib/register.h b/src/stlink-lib/register.h index 7b63154c8..f1e9574cd 100644 --- a/src/stlink-lib/register.h +++ b/src/stlink-lib/register.h @@ -129,4 +129,4 @@ #define STLINK_REG_CM7_ICIALLU 0xE000EF50 #define STLINK_REG_CM7_CCSIDR 0xE000ED80 -#endif // REG_H +#endif // REGISTER_H diff --git a/src/stlink-lib/sg.c b/src/stlink-lib/sg.c index 860b92b70..0aa7a0d68 100644 --- a/src/stlink-lib/sg.c +++ b/src/stlink-lib/sg.c @@ -1,3 +1,5 @@ +/* == nightwalker-87: TODO: CONTENT AND USE OF THIS SOURCE FILE IS TO BE VERIFIED (07.06.2023) == */ + /* * Copyright (c) 2010 "Capt'ns Missing Link" Authors. All rights reserved. * Use of this source code is governed by a BSD-style @@ -87,7 +89,7 @@ #include #include #include -// #include +// #include // TODO: Check use #include "sg.h" @@ -95,7 +97,7 @@ #include "logging.h" #include "register.h" #include "usb.h" -// #include +// #include // TODO: Check use #define STLINK_OK 0x80 #define STLINK_FALSE 0x81 @@ -150,6 +152,7 @@ static int32_t get_usb_mass_storage_status(libusb_device_handle *handle, uint8_t uint32_t rsig = read_uint32(csw, 0); uint32_t rtag = read_uint32(csw, 4); /* uint32_t residue = read_uint32(csw, 8); */ + #define USB_CSW_SIGNATURE 0x53425355 // 'U' 'S' 'B' 'S' (reversed) if (rsig != USB_CSW_SIGNATURE) { @@ -187,9 +190,8 @@ static int32_t dump_CDB_command(uint8_t *cdb, uint8_t cdb_len) { * @param expected_rx_size * @return */ -int32_t send_usb_mass_storage_command(libusb_device_handle *handle, uint8_t endpoint_out, - uint8_t *cdb, uint8_t cdb_length, - uint8_t lun, uint8_t flags, uint32_t expected_rx_size) { +int32_t send_usb_mass_storage_command(libusb_device_handle *handle, uint8_t endpoint_out, uint8_t *cdb, uint8_t cdb_length, + uint8_t lun, uint8_t flags, uint32_t expected_rx_size) { DLOG("Sending usb m-s cmd: cdblen:%d, rxsize=%d\n", cdb_length, expected_rx_size); dump_CDB_command(cdb, cdb_length); diff --git a/src/stlink-lib/sg.h b/src/stlink-lib/sg.h index cc3ea725e..b10d0f6f0 100644 --- a/src/stlink-lib/sg.h +++ b/src/stlink-lib/sg.h @@ -1,3 +1,5 @@ +/* == nightwalker-87: TODO: CONTENT AND USE OF THIS SOURCE FILE IS TO BE VERIFIED (07.06.2023) == */ + /* * File: sg.h * @@ -58,6 +60,46 @@ struct stlink_libsg { struct stlink_reg reg; }; +// static void clear_cdb(struct stlink_libsg *sl); +void _stlink_sg_close(stlink_t *sl); +// static int32_t get_usb_mass_storage_status(libusb_device_handle *handle, uint8_t endpoint, uint32_t *tag); +// static int32_t dump_CDB_command(uint8_t *cdb, uint8_t cdb_len); +int32_t send_usb_mass_storage_command(libusb_device_handle *handle, uint8_t endpoint_out, uint8_t *cdb, uint8_t cdb_length, + uint8_t lun, uint8_t flags, uint32_t expected_rx_size); +// static void get_sense(libusb_device_handle *handle, uint8_t endpoint_in, uint8_t endpoint_out); +int32_t send_usb_data_only(libusb_device_handle *handle, unsigned char endpoint_out, + unsigned char endpoint_in, unsigned char *cbuf, uint32_t length); +int32_t stlink_q(stlink_t *sl); +void stlink_stat(stlink_t *stl, char *txt); +int32_t _stlink_sg_version(stlink_t *stl); +int32_t _stlink_sg_current_mode(stlink_t *stl); +int32_t _stlink_sg_enter_swd_mode(stlink_t *sl); +int32_t _stlink_sg_enter_jtag_mode(stlink_t *sl); +int32_t _stlink_sg_exit_dfu_mode(stlink_t *sl); +int32_t _stlink_sg_core_id(stlink_t *sl); +int32_t _stlink_sg_reset(stlink_t *sl); +int32_t _stlink_sg_jtag_reset(stlink_t *sl, int32_t value); +int32_t _stlink_sg_status(stlink_t *sl); +int32_t _stlink_sg_force_debug(stlink_t *sl); +int32_t _stlink_sg_read_all_regs(stlink_t *sl, struct stlink_reg *regp); +int32_t _stlink_sg_read_reg(stlink_t *sl, int32_t r_idx, struct stlink_reg *regp); +int32_t _stlink_sg_write_reg(stlink_t *sl, uint32_t reg, int32_t idx); +void stlink_write_dreg(stlink_t *sl, uint32_t reg, uint32_t addr); +int32_t _stlink_sg_run(stlink_t *sl, enum run_type type); +int32_t _stlink_sg_step(stlink_t *sl); +void stlink_set_hw_bp(stlink_t *sl, int32_t fp_nr, uint32_t addr, int32_t fp); +void stlink_clr_hw_bp(stlink_t *sl, int32_t fp_nr); +int32_t _stlink_sg_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len); +int32_t _stlink_sg_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len); +int32_t _stlink_sg_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len); +int32_t _stlink_sg_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data); +int32_t _stlink_sg_read_debug32(stlink_t *sl, uint32_t addr, uint32_t *data); +int32_t _stlink_sg_exit_debug_mode(stlink_t *stl); + +// static stlink_backend_t _stlink_sg_backend = { }; + +// static stlink_t* stlink_open(const int32_t verbose); +stlink_t* stlink_v1_open_inner(const int32_t verbose); stlink_t* stlink_v1_open(const int32_t verbose, int32_t reset); #endif // SG_H diff --git a/src/stlink-lib/usb.c b/src/stlink-lib/usb.c index 907a32190..fc1dcbb4e 100644 --- a/src/stlink-lib/usb.c +++ b/src/stlink-lib/usb.c @@ -6,11 +6,11 @@ #if !defined(_MSC_VER) #include -#endif +#endif // _MSC_VER #if defined(_WIN32) #include -#endif +#endif // _WIN32 #include #include @@ -29,8 +29,6 @@ #include "logging.h" #include "register.h" -enum SCSI_Generic_Direction {SG_DXFER_TO_DEV = 0, SG_DXFER_FROM_DEV = 0x80}; - static inline uint32_t le_to_h_u32(const uint8_t* buf) { return((uint32_t)((uint32_t)buf[0] | (uint32_t)buf[1] << 8 | (uint32_t)buf[2] << 16 | (uint32_t)buf[3] << 24)); } @@ -92,9 +90,8 @@ void _stlink_usb_close(stlink_t* sl) { } } -ssize_t send_recv(struct stlink_libusb* handle, int32_t terminate, - unsigned char* txbuf, size_t txsize, unsigned char* rxbuf, - size_t rxsize, int32_t check_error, const char *cmd) { +ssize_t send_recv(struct stlink_libusb* handle, int32_t terminate, unsigned char* txbuf, size_t txsize, + unsigned char* rxbuf, size_t rxsize, int32_t check_error, const char *cmd) { // Note: txbuf and rxbuf can point to the same area int32_t res, t, retry = 0; @@ -170,9 +167,8 @@ ssize_t send_recv(struct stlink_libusb* handle, int32_t terminate, } } -static inline int32_t send_only(struct stlink_libusb* handle, int32_t terminate, - unsigned char* txbuf, size_t txsize, - const char *cmd) { +static inline int32_t send_only(struct stlink_libusb* handle, int32_t terminate, unsigned char* txbuf, + size_t txsize, const char *cmd) { return((int32_t)send_recv(handle, terminate, txbuf, txsize, NULL, 0, CMD_CHECK_NO, cmd)); } @@ -359,7 +355,6 @@ int32_t _stlink_usb_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len) { return(0); } - int32_t _stlink_usb_current_mode(stlink_t * sl) { struct stlink_libusb * const slu = sl->backend_data; unsigned char* const cmd = sl->c_buf; @@ -1113,6 +1108,14 @@ size_t stlink_serial(struct libusb_device_handle *handle, struct libusb_device_d return strlen(serial); } +/** + * Open a stlink + * @param verbose Verbosity loglevel + * @param connect Type of connect to target + * @param serial Serial number to search for, when NULL the first stlink found is opened (binary format) + * @retval NULL Error while opening the stlink + * @retval !NULL Stlink found and ready to use + */ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, enum connect_type connect, char serial[STLINK_SERIAL_BUFFER_SIZE], int32_t freq) { stlink_t* sl = NULL; struct stlink_libusb* slu = NULL; @@ -1208,7 +1211,7 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, enum connect_type connect, goto on_libusb_error; } } -#endif +#endif // NOT _WIN32 if (libusb_get_configuration(slu->usb_handle, &config)) { // this may fail for a previous configured device diff --git a/src/stlink-lib/usb.h b/src/stlink-lib/usb.h index b99e46f53..dd30cc529 100644 --- a/src/stlink-lib/usb.h +++ b/src/stlink-lib/usb.h @@ -46,6 +46,8 @@ #define STLINK_SG_SIZE 31 #define STLINK_CMD_SIZE 16 +enum SCSI_Generic_Direction {SG_DXFER_TO_DEV = 0, SG_DXFER_FROM_DEV = 0x80}; + struct stlink_libusb { libusb_context* libusb_ctx; libusb_device_handle* usb_handle; @@ -57,16 +59,50 @@ struct stlink_libusb { uint32_t cmd_len; }; -/** - * Open a stlink - * @param verbose Verbosity loglevel - * @param connect Type of connect to target - * @param serial Serial number to search for, when NULL the first stlink found is opened (binary format) - * @retval NULL Error while opening the stlink - * @retval !NULL Stlink found and ready to use - */ - +// static inline uint32_t le_to_h_u32(const uint8_t* buf); +// static int32_t _stlink_match_speed_map(const uint32_t *map, uint32_t map_size, uint32_t khz); +void _stlink_usb_close(stlink_t* sl); +ssize_t send_recv(struct stlink_libusb* handle, int32_t terminate, unsigned char* txbuf, size_t txsize, + unsigned char* rxbuf, size_t rxsize, int32_t check_error, const char *cmd); +// static inline int32_t send_only(struct stlink_libusb* handle, int32_t terminate, unsigned char* txbuf, +// size_t txsize, const char *cmd); +// static int32_t fill_command(stlink_t * sl, enum SCSI_Generic_Direction dir, uint32_t len); +int32_t _stlink_usb_version(stlink_t *sl); +int32_t _stlink_usb_target_voltage(stlink_t *sl); +int32_t _stlink_usb_read_debug32(stlink_t *sl, uint32_t addr, uint32_t *data); +int32_t _stlink_usb_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data); +int32_t _stlink_usb_get_rw_status(stlink_t *sl); +int32_t _stlink_usb_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len); +int32_t _stlink_usb_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len); +int32_t _stlink_usb_current_mode(stlink_t * sl); +int32_t _stlink_usb_core_id(stlink_t * sl); +int32_t _stlink_usb_status_v2(stlink_t *sl); +int32_t _stlink_usb_status(stlink_t * sl); +int32_t _stlink_usb_force_debug(stlink_t *sl); +int32_t _stlink_usb_enter_swd_mode(stlink_t * sl); +int32_t _stlink_usb_exit_dfu_mode(stlink_t* sl); +int32_t _stlink_usb_reset(stlink_t * sl); +int32_t _stlink_usb_jtag_reset(stlink_t * sl, int32_t value); +int32_t _stlink_usb_step(stlink_t* sl); +int32_t _stlink_usb_run(stlink_t* sl, enum run_type type); +int32_t _stlink_usb_set_swdclk(stlink_t* sl, int32_t clk_freq); +int32_t _stlink_usb_exit_debug_mode(stlink_t *sl); +int32_t _stlink_usb_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len); +int32_t _stlink_usb_read_all_regs(stlink_t *sl, struct stlink_reg *regp); +int32_t _stlink_usb_read_reg(stlink_t *sl, int32_t r_idx, struct stlink_reg *regp); +int32_t _stlink_usb_read_unsupported_reg(stlink_t *sl, int32_t r_idx, struct stlink_reg *regp); +int32_t _stlink_usb_read_all_unsupported_regs(stlink_t *sl, struct stlink_reg *regp); +int32_t _stlink_usb_write_unsupported_reg(stlink_t *sl, uint32_t val, int32_t r_idx, struct stlink_reg *regp); +int32_t _stlink_usb_write_reg(stlink_t *sl, uint32_t reg, int32_t idx); +int32_t _stlink_usb_enable_trace(stlink_t* sl, uint32_t frequency); +int32_t _stlink_usb_disable_trace(stlink_t* sl); +int32_t _stlink_usb_read_trace(stlink_t* sl, uint8_t* buf, size_t size); + +// static stlink_backend_t _stlink_usb_backend = { }; + +size_t stlink_serial(struct libusb_device_handle *handle, struct libusb_device_descriptor *desc, char *serial); stlink_t *stlink_open_usb(enum ugly_loglevel verbose, enum connect_type connect, char serial[STLINK_SERIAL_BUFFER_SIZE], int32_t freq); +// static size_t stlink_probe_usb_devs(libusb_device **devs, stlink_t **sldevs[], enum connect_type connect, int32_t freq); size_t stlink_probe_usb(stlink_t **stdevs[], enum connect_type connect, int32_t freq); void stlink_probe_usb_free(stlink_t **stdevs[], size_t size); From efc5c3713d3124a1e8c6189a6cab960c700a50b9 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Fri, 9 Jun 2023 14:51:57 +0200 Subject: [PATCH 451/503] Fixed flash-write/verify error (Closes #1303) --- src/stlink-lib/common_flash.c | 3 --- src/stlink-lib/flash_loader.c | 2 +- 2 files changed, 1 insertion(+), 4 deletions(-) diff --git a/src/stlink-lib/common_flash.c b/src/stlink-lib/common_flash.c index 6ade87311..194fa7aab 100644 --- a/src/stlink-lib/common_flash.c +++ b/src/stlink-lib/common_flash.c @@ -1439,9 +1439,6 @@ int32_t stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint3 (uint32_t)(sl->flash_pgsz)); return (-1); } - if ((len % 16 <= 8) & (sl->flash_type == STM32_FLASH_TYPE_L5_U5)) { - len += 8; - } // make sure we've loaded the context with the chip details stlink_core_id(sl); diff --git a/src/stlink-lib/flash_loader.c b/src/stlink-lib/flash_loader.c index 3472e2a61..2bac1ace0 100644 --- a/src/stlink-lib/flash_loader.c +++ b/src/stlink-lib/flash_loader.c @@ -474,7 +474,7 @@ int32_t stm32l1_write_half_pages(stlink_t *sl, stm32_addr_t addr, uint8_t *base, if (sl->verbose >= 1) { // show progress; writing procedure is slow and previous errors are misleading - fprintf(stdout, "\r%3u/%u halfpages written", count + 1, num_half_pages); + fprintf(stdout, "\r%3u/%3u halfpages written", count + 1, num_half_pages); fflush(stdout); } From 755c20c08ea026549439a97be2351540069c7f9e Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sat, 10 Jun 2023 20:07:19 +0200 Subject: [PATCH 452/503] Replace data types with fixed width typedefs (C99) - Unified variable type: size_t --> uint32_t - Removed unnecessary explicit casts - Minor formatting fixes --- inc/backend.h | 2 +- inc/stlink.h | 18 +++--- src/st-flash/flash.c | 14 ++--- src/st-flash/flash.h | 4 +- src/st-flash/flash_opts.c | 12 ++-- src/st-info/info.c | 18 +++--- src/st-util/gdb-server.c | 54 +++++++++--------- src/stlink-gui/gui.c | 2 +- src/stlink-lib/calculate.c | 7 +-- src/stlink-lib/calculate.h | 2 +- src/stlink-lib/chipid.c | 2 +- src/stlink-lib/common.c | 61 ++++++++++---------- src/stlink-lib/common_flash.c | 47 +++++++--------- src/stlink-lib/common_flash.h | 4 +- src/stlink-lib/flash_loader.c | 103 ++++++++++++++-------------------- src/stlink-lib/flash_loader.h | 10 ++-- src/stlink-lib/map_file.c | 12 ++-- src/stlink-lib/map_file.h | 2 +- src/stlink-lib/md5.c | 2 +- src/stlink-lib/option_bytes.h | 2 +- src/stlink-lib/read_write.c | 2 +- src/stlink-lib/sg.c | 2 +- src/stlink-lib/usb.c | 24 ++++---- src/stlink-lib/usb.h | 12 ++-- src/win32/getopt/getopt.c | 2 +- src/win32/mmap.c | 4 +- src/win32/mmap.h | 4 +- tests/flash.c | 4 +- 28 files changed, 200 insertions(+), 232 deletions(-) diff --git a/inc/backend.h b/inc/backend.h index a9a7d6e03..6b9c9c0a8 100644 --- a/inc/backend.h +++ b/inc/backend.h @@ -33,7 +33,7 @@ int32_t (*set_swdclk) (stlink_t * stl, int32_t freq_khz); int32_t (*trace_enable) (stlink_t * sl, uint32_t frequency); int32_t (*trace_disable) (stlink_t * sl); - int32_t (*trace_read) (stlink_t * sl, uint8_t* buf, size_t size); + int32_t (*trace_read) (stlink_t * sl, uint8_t* buf, uint32_t size); } stlink_backend_t; #endif // BACKEND_H diff --git a/inc/stlink.h b/inc/stlink.h index b2516c90c..d5d036725 100644 --- a/inc/stlink.h +++ b/inc/stlink.h @@ -210,22 +210,22 @@ struct _stlink { // stlink_chipid_params.flash_type, set by stlink_load_device_params(), values: STM32_FLASH_TYPE_xx stm32_addr_t flash_base; // STM32_FLASH_BASE, set by stlink_load_device_params() - size_t flash_size; // calculated by stlink_load_device_params() - size_t flash_pgsz; // stlink_chipid_params.flash_pagesize, set by stlink_load_device_params() + uint32_t flash_size; // calculated by stlink_load_device_params() + uint32_t flash_pgsz; // stlink_chipid_params.flash_pagesize, set by stlink_load_device_params() /* sram settings */ stm32_addr_t sram_base; // STM32_SRAM_BASE, set by stlink_load_device_params() - size_t sram_size; // stlink_chipid_params.sram_size, set by stlink_load_device_params() + uint32_t sram_size; // stlink_chipid_params.sram_size, set by stlink_load_device_params() /* option settings */ stm32_addr_t option_base; - size_t option_size; + uint32_t option_size; // bootloader // sys_base and sys_size are not used by the tools, but are only there to download the bootloader code // (see tests/sg.c) stm32_addr_t sys_base; // stlink_chipid_params.bootrom_base, set by stlink_load_device_params() - size_t sys_size; // stlink_chipid_params.bootrom_size, set by stlink_load_device_params() + uint32_t sys_size; // stlink_chipid_params.bootrom_size, set by stlink_load_device_params() struct stlink_version_ version; @@ -262,8 +262,8 @@ int32_t stlink_target_voltage(stlink_t *sl); int32_t stlink_set_swdclk(stlink_t *sl, int32_t freq_khz); int32_t stlink_trace_enable(stlink_t* sl, uint32_t frequency); int32_t stlink_trace_disable(stlink_t* sl); -int32_t stlink_trace_read(stlink_t* sl, uint8_t* buf, size_t size); -int32_t stlink_parse_ihex(const char* path, uint8_t erased_pattern, uint8_t * * mem, size_t * size, uint32_t * begin); +int32_t stlink_trace_read(stlink_t* sl, uint8_t* buf, uint32_t size); +int32_t stlink_parse_ihex(const char* path, uint8_t erased_pattern, uint8_t * * mem, uint32_t * size, uint32_t * begin); uint8_t stlink_get_erased_pattern(stlink_t *sl); int32_t stlink_mwrite_sram(stlink_t *sl, uint8_t* data, uint32_t length, stm32_addr_t addr); int32_t stlink_fwrite_sram(stlink_t *sl, const char* path, stm32_addr_t addr); @@ -278,9 +278,9 @@ uint32_t read_uint32(const unsigned char *c, const int32_t pt); void write_uint32(unsigned char* buf, uint32_t ui); void write_uint16(unsigned char* buf, uint16_t ui); bool stlink_is_core_halted(stlink_t *sl); -int32_t write_buffer_to_sram(stlink_t *sl, flash_loader_t* fl, const uint8_t* buf, size_t size); +int32_t write_buffer_to_sram(stlink_t *sl, flash_loader_t* fl, const uint8_t* buf, uint32_t size); int32_t write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size); -int32_t stlink_fread(stlink_t* sl, const char* path, bool is_ihex, stm32_addr_t addr, size_t size); +int32_t stlink_fread(stlink_t* sl, const char* path, bool is_ihex, stm32_addr_t addr, uint32_t size); int32_t stlink_load_device_params(stlink_t *sl); int32_t stlink_target_connect(stlink_t *sl, enum connect_type connect); diff --git a/src/st-flash/flash.c b/src/st-flash/flash.c index 6b4a10cfc..9a648bd63 100644 --- a/src/st-flash/flash.c +++ b/src/st-flash/flash.c @@ -83,7 +83,7 @@ int32_t main(int32_t ac, char** av) { if ( o.flash_size != 0u && o.flash_size != sl->flash_size ) { sl->flash_size = o.flash_size; - printf("Forcing flash size: --flash=0x%08X\n", (uint32_t)sl->flash_size); + printf("Forcing flash size: --flash=0x%08X\n", sl->flash_size); } sl->verbose = o.log_level; @@ -106,7 +106,7 @@ int32_t main(int32_t ac, char** av) { } if (o.cmd == FLASH_CMD_WRITE) { - size_t size = 0; + uint32_t size = 0; // write if (o.format == FLASH_FORMAT_IHEX) { @@ -119,7 +119,7 @@ int32_t main(int32_t ac, char** av) { } if ((o.addr >= sl->flash_base) && (o.addr < sl->flash_base + sl->flash_size)) { if (o.format == FLASH_FORMAT_IHEX) { - err = stlink_mwrite_flash(sl, mem, (uint32_t)size, o.addr); + err = stlink_mwrite_flash(sl, mem, size, o.addr); } else { err = stlink_fwrite_flash(sl, o.filename, o.addr); } @@ -130,7 +130,7 @@ int32_t main(int32_t ac, char** av) { } } else if ((o.addr >= sl->sram_base) && (o.addr < sl->sram_base + sl->sram_size)) { if (o.format == FLASH_FORMAT_IHEX) { - err = stlink_mwrite_sram(sl, mem, (uint32_t)size, o.addr); + err = stlink_mwrite_sram(sl, mem, size, o.addr); } else { err = stlink_fwrite_sram(sl, o.filename, o.addr); } @@ -221,10 +221,10 @@ int32_t main(int32_t ac, char** av) { goto on_error; } } else if (o.area == FLASH_OPTION_BYTES) { - size_t remaining_option_length = sl->option_size / 4; + uint32_t remaining_option_length = sl->option_size / 4; DLOG("@@@@ Read %u (%#x) option bytes from %#10x\n", - (uint32_t)remaining_option_length, - (uint32_t)remaining_option_length, + remaining_option_length, + remaining_option_length, sl->option_base); uint32_t option_byte = 0; diff --git a/src/st-flash/flash.h b/src/st-flash/flash.h index 1a509a660..84c171158 100644 --- a/src/st-flash/flash.h +++ b/src/st-flash/flash.h @@ -17,13 +17,13 @@ struct flash_opts { uint8_t serial[STLINK_SERIAL_BUFFER_SIZE]; const char* filename; stm32_addr_t addr; - size_t size; + uint32_t size; int32_t reset; int32_t log_level; enum flash_format format; enum flash_area area; uint32_t val; - size_t flash_size; // --flash=n[k, M] + uint32_t flash_size; // --flash=n[k, M] int32_t opt; // enable empty tail data drop optimization int32_t freq; // --freq=n[k, M] frequency of JTAG/SWD enum connect_type connect; diff --git a/src/st-flash/flash_opts.c b/src/st-flash/flash_opts.c index e133d52c7..35763ad50 100644 --- a/src/st-flash/flash_opts.c +++ b/src/st-flash/flash_opts.c @@ -8,7 +8,7 @@ #include "flash.h" static bool starts_with(const char * str, const char * prefix) { - size_t n = strlen(prefix); + uint32_t n = strlen(prefix); if (strlen(str) < n) { return(false); } @@ -61,7 +61,7 @@ static int32_t get_integer_from_char_array (const char *const str, uint32_t *rea fprintf (stderr, "*** Error: Integer greater than UINT32_MAX, cannot convert to int32_t\n"); return(-1); } else { - *read_value = (uint32_t)value; + *read_value = value; return(0); } } @@ -318,7 +318,7 @@ int32_t flash_get_opts(struct flash_opts* o, int32_t ac, char** av) { if (result != 0) { return bad_arg ("val"); } else { - o->val = (uint32_t) val; + o->val = val; } } else if (o->area == FLASH_OPTION_BYTES_BOOT_ADD) { // expect option bytes boot address if (ac != 1) { return invalid_args("option bytes boot_add write "); } @@ -329,7 +329,7 @@ int32_t flash_get_opts(struct flash_opts* o, int32_t ac, char** av) { if (result != 0) { return(bad_arg ("val")); } else { - o->val = (uint32_t)val; + o->val = val; } } else if (o->area == FLASH_OPTCR) { // expect option control register value if (ac != 1) { return invalid_args("option control register write "); } @@ -340,7 +340,7 @@ int32_t flash_get_opts(struct flash_opts* o, int32_t ac, char** av) { if (result != 0) { return bad_arg ("val"); } else { - o->val = (uint32_t) val; + o->val = val; } } else if (o->area == FLASH_OPTCR1) { // expect option control register 1 value if (ac != 1) { return invalid_args("option control register 1 write "); } @@ -350,7 +350,7 @@ int32_t flash_get_opts(struct flash_opts* o, int32_t ac, char** av) { if (result != 0) { return bad_arg ("val"); } else { - o->val = (uint32_t) val; + o->val = val; } } else if (o->format == FLASH_FORMAT_BINARY) { // expect filename and addr if (ac != 2) { return invalid_args("write "); } diff --git a/src/st-info/info.c b/src/st-info/info.c index 86a1c2d8f..b6ec0ccd2 100644 --- a/src/st-info/info.c +++ b/src/st-info/info.c @@ -35,8 +35,8 @@ static void stlink_print_info(stlink_t *sl) { printf(" version: "); stlink_print_version(sl); printf(" serial: %s\n", sl->serial); - printf(" flash: %u (pagesize: %u)\n", (uint32_t)sl->flash_size, (uint32_t)sl->flash_pgsz); - printf(" sram: %u\n", (uint32_t)sl->sram_size); + printf(" flash: %u (pagesize: %u)\n", sl->flash_size, sl->flash_pgsz); + printf(" sram: %u\n", sl->sram_size); printf(" chipid: 0x%.3x\n", sl->chip_id); params = stlink_chipid_get_params(sl->chip_id); @@ -45,14 +45,14 @@ static void stlink_print_info(stlink_t *sl) { static void stlink_probe(enum connect_type connect, int32_t freq) { stlink_t **stdevs; - size_t size; + uint32_t size; size = stlink_probe_usb(&stdevs, connect, freq); - printf("Found %u stlink programmers\n", (uint32_t)size); + printf("Found %u stlink programmers\n", size); - for (size_t n = 0; n < size; n++) { - if (size > 1) printf("%u.\n", (uint32_t)n+1); + for (uint32_t n = 0; n < size; n++) { + if (size > 1) printf("%u.\n", n+1); stlink_print_info(stdevs[n]); } @@ -107,11 +107,11 @@ static int32_t print_data(int32_t ac, char **av) { if (strcmp(av[1], "--serial") == 0) { printf("%s\n", sl->serial); } else if (strcmp(av[1], "--flash") == 0) { - printf("0x%x\n", (uint32_t)sl->flash_size); + printf("0x%x\n", sl->flash_size); } else if (strcmp(av[1], "--pagesize") == 0) { - printf("0x%x\n", (uint32_t)sl->flash_pgsz); + printf("0x%x\n", sl->flash_pgsz); } else if (strcmp(av[1], "--sram") == 0) { - printf("0x%x\n", (uint32_t)sl->sram_size); + printf("0x%x\n", sl->sram_size); } else if (strcmp(av[1], "--chipid") == 0) { printf("0x%.4x\n", sl->chip_id); } else if (strcmp(av[1], "--descr") == 0) { diff --git a/src/st-util/gdb-server.c b/src/st-util/gdb-server.c index 431e37eec..7232f0f69 100644 --- a/src/st-util/gdb-server.c +++ b/src/st-util/gdb-server.c @@ -554,7 +554,7 @@ static const char* const memory_map_template_F4_DE = char* make_memory_map(stlink_t *sl) { // this will be freed in serve() - const size_t sz = 4096; + const uint32_t sz = 4096; char* map = malloc(sz); map[0] = '\0'; @@ -566,42 +566,42 @@ char* make_memory_map(stlink_t *sl) { strcpy(map, memory_map_template_F4_DE); } else if (sl->core_id == STM32_CORE_ID_M7F_SWD) { snprintf(map, sz, memory_map_template_F7, - (uint32_t)sl->sram_size); + sl->sram_size); } else if (sl->chip_id == STM32_CHIPID_H74xxx) { snprintf(map, sz, memory_map_template_H7, - (uint32_t)sl->flash_size, - (uint32_t)sl->flash_pgsz); + sl->flash_size, + sl->flash_pgsz); } else if (sl->chip_id == STM32_CHIPID_F4_HD) { strcpy(map, memory_map_template_F4_HD); } else if (sl->chip_id == STM32_CHIPID_F2) { snprintf(map, sz, memory_map_template_F2, - (uint32_t)sl->flash_size, - (uint32_t)sl->sram_size, - (uint32_t)sl->flash_size - 0x20000, - (uint32_t)sl->sys_base, - (uint32_t)sl->sys_size); + sl->flash_size, + sl->sram_size, + sl->flash_size - 0x20000, + sl->sys_base, + sl->sys_size); } else if ((sl->chip_id == STM32_CHIPID_L4) || (sl->chip_id == STM32_CHIPID_L43x_L44x) || (sl->chip_id == STM32_CHIPID_L45x_L46x)) { snprintf(map, sz, memory_map_template_L4, - (uint32_t)sl->flash_size, - (uint32_t)sl->flash_size); + sl->flash_size, + sl->flash_size); } else if (sl->chip_id == STM32_CHIPID_L496x_L4A6x) { snprintf(map, sz, memory_map_template_L496, - (uint32_t)sl->flash_size, - (uint32_t)sl->flash_size); + sl->flash_size, + sl->flash_size); } else if (sl->chip_id == STM32_CHIPID_H72x) { snprintf(map, sz, memory_map_template_H72x3x, - (uint32_t)sl->flash_size, - (uint32_t)sl->flash_pgsz); + sl->flash_size, + sl->flash_pgsz); } else { snprintf(map, sz, memory_map_template, - (uint32_t)sl->flash_size, - (uint32_t)sl->sram_size, - (uint32_t)sl->flash_size, - (uint32_t)sl->flash_pgsz, - (uint32_t)sl->sys_base, - (uint32_t)sl->sys_size); + sl->flash_size, + sl->sram_size, + sl->flash_size, + sl->flash_pgsz, + sl->sys_base, + sl->sys_size); } return(map); @@ -1074,8 +1074,8 @@ static void cache_sync(stlink_t *sl) { if (ccr & (STLINK_REG_CM7_CCR_IC | STLINK_REG_CM7_CCR_DC)) { cache_flush(sl, ccr); } } -static size_t unhexify(const char *in, char *out, size_t out_count) { - size_t i; +static uint32_t unhexify(const char *in, char *out, uint32_t out_count) { + uint32_t i; uint32_t c; for (i = 0; i < out_count; i++) { @@ -1248,9 +1248,9 @@ int32_t serve(stlink_t *sl, st_state_t *st) { params = separator + 1; } - size_t hex_len = strlen(params); - size_t alloc_size = (hex_len / 2) + 1; - size_t cmd_len; + uint32_t hex_len = strlen(params); + uint32_t alloc_size = (hex_len / 2) + 1; + uint32_t cmd_len; char *cmd = malloc(alloc_size); if (cmd == NULL) { @@ -1669,7 +1669,7 @@ int32_t serve(stlink_t *sl, st_state_t *st) { uint32_t adj_start = start % 4; uint32_t count_rnd = (count + adj_start + 4 - 1) / 4 * 4; - if (count_rnd > sl->flash_pgsz) { count_rnd = (uint32_t)sl->flash_pgsz; } + if (count_rnd > sl->flash_pgsz) { count_rnd = sl->flash_pgsz; } if (count_rnd > 0x1800) { count_rnd = 0x1800; } diff --git a/src/stlink-gui/gui.c b/src/stlink-gui/gui.c index f1e9382d0..af2afcdbf 100644 --- a/src/stlink-gui/gui.c +++ b/src/stlink-gui/gui.c @@ -262,7 +262,7 @@ static gpointer stlink_gui_populate_filemem_view(gpointer data) { */ uint8_t* mem = NULL; - size_t size = 0; + uint32_t size = 0; uint32_t begin = 0; int32_t res = stlink_parse_ihex(gui->filename, 0, &mem, &size, &begin); diff --git a/src/stlink-lib/calculate.c b/src/stlink-lib/calculate.c index b13a1c961..027239694 100644 --- a/src/stlink-lib/calculate.c +++ b/src/stlink-lib/calculate.c @@ -47,8 +47,7 @@ uint32_t calculate_F7_sectornum(uint32_t flashaddr) { } } -uint32_t calculate_H7_sectornum(stlink_t *sl, uint32_t flashaddr, - uint32_t bank) { +uint32_t calculate_H7_sectornum(stlink_t *sl, uint32_t flashaddr, uint32_t bank) { flashaddr &= ~((bank == BANK_1) ? STM32_FLASH_BASE @@ -68,7 +67,7 @@ uint32_t calculate_L4_page(stlink_t *sl, uint32_t flashaddr) { sl->chip_id == STM32_CHIPID_L4Rx) { // this chip use dual banked flash if (flashopt & (uint32_t)(1lu << FLASH_L4_OPTR_DUALBANK)) { - uint32_t banksize = (uint32_t)sl->flash_size / 2; + uint32_t banksize = sl->flash_size / 2; if (flashaddr >= banksize) { flashaddr -= banksize; @@ -79,5 +78,5 @@ uint32_t calculate_L4_page(stlink_t *sl, uint32_t flashaddr) { // For 1MB chips without the dual-bank option set, the page address will // overflow into the BKER bit, which gives us the correct bank:page value. - return (bker | flashaddr / (uint32_t)sl->flash_pgsz); + return (bker | flashaddr / sl->flash_pgsz); } diff --git a/src/stlink-lib/calculate.h b/src/stlink-lib/calculate.h index 64dfb51b2..ca0a39df6 100644 --- a/src/stlink-lib/calculate.h +++ b/src/stlink-lib/calculate.h @@ -9,7 +9,7 @@ uint32_t calculate_F4_sectornum(uint32_t); uint32_t calculate_F7_sectornum(uint32_t); -uint32_t calculate_H7_sectornum(stlink_t *, uint32_t, unsigned); +uint32_t calculate_H7_sectornum(stlink_t *, uint32_t, uint32_t); uint32_t calculate_L4_page(stlink_t *, uint32_t); #endif // CALCULATE_H diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index a4abf90d8..0392f15ff 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -196,7 +196,7 @@ void process_chipfile(char *fname) { void init_chipids(char *dir_to_scan) { DIR *d; - size_t nl; // namelen + uint32_t nl; // namelen struct dirent *dir; if (!dir_to_scan) { diff --git a/src/stlink-lib/common.c b/src/stlink-lib/common.c index d6477281d..70ecdd3a2 100644 --- a/src/stlink-lib/common.c +++ b/src/stlink-lib/common.c @@ -56,7 +56,7 @@ int32_t stlink_jtag_reset(stlink_t *, int32_t); int32_t stlink_soft_reset(stlink_t *, int32_t); void _parse_version(stlink_t *, stlink_version_t *); static uint8_t stlink_parse_hex(const char *); -static int32_t stlink_read(stlink_t *, stm32_addr_t, size_t, save_block_fn, void *); +static int32_t stlink_read(stlink_t *, stm32_addr_t, uint32_t, save_block_fn, void *); static bool stlink_fread_ihex_init(struct stlink_fread_ihex_worker_arg *, int32_t, stm32_addr_t); static bool stlink_fread_ihex_worker(void *, uint8_t *, ssize_t); static bool stlink_fread_ihex_finalize(struct stlink_fread_ihex_worker_arg *); @@ -323,8 +323,8 @@ int32_t stlink_load_device_params(stlink_t *sl) { } ILOG("%s: %u KiB SRAM, %u KiB flash in at least %u %s pages.\n", - params->dev_type, (uint32_t)(sl->sram_size / 1024), (uint32_t)(sl->flash_size / 1024), - (sl->flash_pgsz < 1024) ? (uint32_t)(sl->flash_pgsz) : (uint32_t)(sl->flash_pgsz / 1024), + params->dev_type, (sl->sram_size / 1024), (sl->flash_size / 1024), + (sl->flash_pgsz < 1024) ? sl->flash_pgsz : (sl->flash_pgsz / 1024), (sl->flash_pgsz < 1024) ? "byte" : "KiB"); return (0); @@ -609,7 +609,7 @@ int32_t stlink_trace_disable(stlink_t *sl) { } // 276 -int32_t stlink_trace_read(stlink_t *sl, uint8_t *buf, size_t size) { +int32_t stlink_trace_read(stlink_t *sl, uint8_t *buf, uint32_t size) { return (sl->backend->trace_read(sl, buf, size)); } @@ -645,8 +645,8 @@ int32_t stlink_mwrite_sram(stlink_t *sl, uint8_t *data, uint32_t length, stm32_a // write the file in sram at addr int32_t error = -1; - size_t off; - size_t len; + uint32_t off; + uint32_t len; // check addr range is inside the sram if (addr < sl->sram_base) { @@ -671,7 +671,7 @@ int32_t stlink_mwrite_sram(stlink_t *sl, uint8_t *data, uint32_t length, stm32_a // do the copy by 1kB blocks for (off = 0; off < len; off += 1024) { - size_t size = 1024; + uint32_t size = 1024; if ((off + size) > len) { size = len - off; @@ -683,12 +683,12 @@ int32_t stlink_mwrite_sram(stlink_t *sl, uint8_t *data, uint32_t length, stm32_a size += 2; } // round size if needed - stlink_write_mem32(sl, addr + (uint32_t)off, (uint16_t)size); + stlink_write_mem32(sl, addr + off, (uint16_t)size); } if (length > len) { memcpy(sl->q_buf, data + len, length - len); - stlink_write_mem8(sl, addr + (uint32_t)len, (uint16_t)(length - len)); + stlink_write_mem8(sl, addr + len, (uint16_t)(length - len)); } error = 0; // success @@ -703,8 +703,8 @@ int32_t stlink_fwrite_sram(stlink_t *sl, const char *path, stm32_addr_t addr) { // write the file in sram at addr int32_t error = -1; - size_t off; - size_t len; + uint32_t off; + uint32_t len; mapped_file_t mf = MAPPED_FILE_INITIALIZER; if (map_file(&mf, path) == -1) { @@ -739,7 +739,7 @@ int32_t stlink_fwrite_sram(stlink_t *sl, const char *path, stm32_addr_t addr) { // do the copy by 1kB blocks for (off = 0; off < len; off += 1024) { - size_t size = 1024; + uint32_t size = 1024; if ((off + size) > len) { size = len - off; @@ -751,12 +751,12 @@ int32_t stlink_fwrite_sram(stlink_t *sl, const char *path, stm32_addr_t addr) { size += 2; } // round size if needed - stlink_write_mem32(sl, addr + (uint32_t)off, (uint16_t)size); + stlink_write_mem32(sl, addr + off, (uint16_t)size); } if (mf.len > len) { memcpy(sl->q_buf, mf.base + len, mf.len - len); - stlink_write_mem8(sl, addr + (uint32_t)len, (uint16_t)(mf.len - len)); + stlink_write_mem8(sl, addr + len, (uint16_t)(mf.len - len)); } // check the file has been written @@ -774,9 +774,9 @@ int32_t stlink_fwrite_sram(stlink_t *sl, const char *path, stm32_addr_t addr) { } // 302 -int32_t stlink_fread(stlink_t *sl, const char *path, bool is_ihex, stm32_addr_t addr, size_t size) { +int32_t stlink_fread(stlink_t *sl, const char *path, bool is_ihex, stm32_addr_t addr, uint32_t size) { // read size bytes from addr to file - ILOG("read from address %#010x size %u\n", addr, (uint32_t)size); + ILOG("read from address %#010x size %u\n", addr, size); int32_t error; int32_t fd = open(path, O_RDWR | O_TRUNC | O_CREAT | O_BINARY, 00700); @@ -808,11 +808,11 @@ int32_t stlink_fread(stlink_t *sl, const char *path, bool is_ihex, stm32_addr_t } // 300 -int32_t write_buffer_to_sram(stlink_t *sl, flash_loader_t *fl, const uint8_t *buf, size_t size) { +int32_t write_buffer_to_sram(stlink_t *sl, flash_loader_t *fl, const uint8_t *buf, uint32_t size) { // write the buffer right after the loader int32_t ret = 0; - size_t chunk = size & ~0x3; - size_t rem = size & 0x3; + uint32_t chunk = size & ~0x3; + uint32_t rem = size & 0x3; if (chunk) { memcpy(sl->q_buf, buf, chunk); @@ -821,7 +821,7 @@ int32_t write_buffer_to_sram(stlink_t *sl, flash_loader_t *fl, const uint8_t *bu if (rem && !ret) { memcpy(sl->q_buf, buf + chunk, rem); - ret = stlink_write_mem8(sl, (fl->buf_addr) + (uint32_t)chunk, (uint16_t)rem); + ret = stlink_write_mem8(sl, (fl->buf_addr) + chunk, (uint16_t)rem); } return (ret); @@ -865,12 +865,12 @@ uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr) { } } - return ((uint32_t)sl->flash_pgsz); + return (sl->flash_pgsz); } // 279 int32_t stlink_parse_ihex(const char *path, uint8_t erased_pattern, uint8_t **mem, - size_t *size, uint32_t *begin) { + uint32_t *size, uint32_t *begin) { int32_t res = 0; *begin = UINT32_MAX; uint8_t *data = NULL; @@ -896,7 +896,7 @@ int32_t stlink_parse_ihex(const char *path, uint8_t erased_pattern, uint8_t **me data = calloc(*size, 1); // use calloc to get NULL if out of memory if (!data) { - ELOG("Cannot allocate %u bytes\n", (uint32_t)(*size)); + ELOG("Cannot allocate %u bytes\n", (*size)); res = -1; break; } @@ -926,7 +926,7 @@ int32_t stlink_parse_ihex(const char *path, uint8_t erased_pattern, uint8_t **me break; } - size_t l = strlen(line); + uint32_t l = strlen(line); while (l > 0 && (line[l - 1] == '\n' || line[l - 1] == '\r')) { --l; @@ -942,7 +942,7 @@ int32_t stlink_parse_ihex(const char *path, uint8_t erased_pattern, uint8_t **me uint8_t chksum = 0; // check sum - for (size_t i = 1; i < l; i += 2) { + for (uint32_t i = 1; i < l; i += 2) { chksum += stlink_parse_hex(line + i); } @@ -1215,8 +1215,7 @@ void stlink_run_at(stlink_t *sl, stm32_addr_t addr) { } } -static int32_t stlink_read(stlink_t *sl, stm32_addr_t addr, size_t size, - save_block_fn fn, void *fn_arg) { +static int32_t stlink_read(stlink_t *sl, stm32_addr_t addr, uint32_t size, save_block_fn fn, void *fn_arg) { int32_t error = -1; @@ -1228,10 +1227,10 @@ static int32_t stlink_read(stlink_t *sl, stm32_addr_t addr, size_t size, size = sl->flash_size; } - size_t cmp_size = (sl->flash_pgsz > 0x1800) ? 0x1800 : sl->flash_pgsz; + uint32_t cmp_size = (sl->flash_pgsz > 0x1800) ? 0x1800 : sl->flash_pgsz; - for (size_t off = 0; off < size; off += cmp_size) { - size_t aligned_size; + for (uint32_t off = 0; off < size; off += cmp_size) { + uint32_t aligned_size; // adjust last page size if ((off + cmp_size) > size) { @@ -1244,7 +1243,7 @@ static int32_t stlink_read(stlink_t *sl, stm32_addr_t addr, size_t size, aligned_size = (cmp_size + 4) & ~(4 - 1); } - stlink_read_mem32(sl, addr + (uint32_t)off, (uint16_t)aligned_size); + stlink_read_mem32(sl, addr + off, (uint16_t)aligned_size); if (!fn(fn_arg, sl->q_buf, aligned_size)) { goto on_error; diff --git a/src/stlink-lib/common_flash.c b/src/stlink-lib/common_flash.c index 194fa7aab..70c8a2216 100644 --- a/src/stlink-lib/common_flash.c +++ b/src/stlink-lib/common_flash.c @@ -1027,10 +1027,8 @@ int32_t stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { } // unlock program memory - stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, - FLASH_L0_PRGKEY1); - stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, - FLASH_L0_PRGKEY2); + stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, FLASH_L0_PRGKEY1); + stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, FLASH_L0_PRGKEY2); // check pecr.prglock is cleared stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); @@ -1069,16 +1067,14 @@ int32_t stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { // set the page to erase if (sl->flash_type == STM32_FLASH_TYPE_G0) { - uint32_t flash_page = - ((flashaddr - STM32_FLASH_BASE) / (uint32_t)(sl->flash_pgsz)); + uint32_t flash_page = ((flashaddr - STM32_FLASH_BASE) / sl->flash_pgsz); stlink_read_debug32(sl, FLASH_Gx_CR, &val); // sec 3.7.5 - PNB[5:0] is offset by 3. PER is 0x2. val &= ~(0x3F << 3); val |= ((flash_page & 0x3F) << 3) | (1 << FLASH_CR_PER); stlink_write_debug32(sl, FLASH_Gx_CR, val); } else if (sl->flash_type == STM32_FLASH_TYPE_G4) { - uint32_t flash_page = - ((flashaddr - STM32_FLASH_BASE) / (uint32_t)(sl->flash_pgsz)); + uint32_t flash_page = ((flashaddr - STM32_FLASH_BASE) / sl->flash_pgsz); stlink_read_debug32(sl, FLASH_Gx_CR, &val); // sec 3.7.5 - PNB[6:0] is offset by 3. PER is 0x2. val &= ~(0x7F << 3); @@ -1088,13 +1084,11 @@ int32_t stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { uint32_t flash_page; stlink_read_debug32(sl, FLASH_L5_NSCR, &val); if (sl->flash_pgsz == 0x800 && (flashaddr - STM32_FLASH_BASE) >= sl->flash_size/2) { - flash_page = (flashaddr - STM32_FLASH_BASE - sl->flash_size/2) / - (uint32_t)(sl->flash_pgsz); + flash_page = (flashaddr - STM32_FLASH_BASE - sl->flash_size/2) / sl->flash_pgsz; // set bank 2 for erasure val |= (1 << FLASH_L5_NSCR_NSBKER); } else { - flash_page = - ((flashaddr - STM32_FLASH_BASE) / (uint32_t)(sl->flash_pgsz)); + flash_page = ((flashaddr - STM32_FLASH_BASE) / sl->flash_pgsz); // set bank 1 for erasure val &= ~(1 << FLASH_L5_NSCR_NSBKER); } @@ -1103,8 +1097,7 @@ int32_t stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { val |= ((flash_page & 0x7F) << 3) | (1 << FLASH_CR_PER); stlink_write_debug32(sl, FLASH_L5_NSCR, val); } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { - uint32_t flash_page = - ((flashaddr - STM32_FLASH_BASE) / (uint32_t)(sl->flash_pgsz)); + uint32_t flash_page = ((flashaddr - STM32_FLASH_BASE) / sl->flash_pgsz); stlink_read_debug32(sl, FLASH_WB_CR, &val); // sec 3.10.5 - PNB[7:0] is offset by 3. @@ -1133,8 +1126,7 @@ int32_t stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { uint32_t bank = (flashaddr < STM32_H7_FLASH_BANK2_BASE) ? BANK_1 : BANK_2; unlock_flash_if(sl); // unlock if locked - uint32_t sector = calculate_H7_sectornum( - sl, flashaddr, bank); // calculate the actual page from the address + uint32_t sector = calculate_H7_sectornum(sl, flashaddr, bank); // calculate the actual page from the address write_flash_cr_snb(sl, sector, bank); // select the page to erase set_flash_cr_strt(sl, bank); // start erase operation wait_flash_busy(sl); // wait for completion @@ -1147,7 +1139,7 @@ int32_t stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { return check_flash_error(sl); } -int32_t stlink_erase_flash_section(stlink_t *sl, stm32_addr_t base_addr, size_t size, bool align_size) { +int32_t stlink_erase_flash_section(stlink_t *sl, stm32_addr_t base_addr, uint32_t size, bool align_size) { // Check the address and size validity if (stlink_check_address_range_validity(sl, base_addr, size) < 0) { return -1; @@ -1247,7 +1239,7 @@ int32_t stlink_mwrite_flash(stlink_t *sl, uint8_t *data, uint32_t length, stm32_ * Therfore it is turned off by default. */ if (sl->opt) { - idx = (uint32_t)length; + idx = length; for (num_empty = 0; num_empty != length; ++num_empty) if (data[--idx] != erased_pattern) { @@ -1270,9 +1262,8 @@ int32_t stlink_mwrite_flash(stlink_t *sl, uint8_t *data, uint32_t length, stm32_ * still flash the whole file even if ignoring message is printed. */ err = stlink_write_flash(sl, addr, data, - (num_empty == length) ? (uint32_t)length - : (uint32_t)length - num_empty, - num_empty == length); + (num_empty == length) ? length : length - num_empty, + num_empty == length); stlink_fwrite_finalize(sl, addr); return (err); } @@ -1358,12 +1349,12 @@ int32_t stlink_fcheck_flash(stlink_t *sl, const char *path, stm32_addr_t addr) { * @return 0 for success, -ve for failure */ int32_t stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, uint32_t length) { - size_t off; - size_t cmp_size = (sl->flash_pgsz > 0x1800) ? 0x1800 : sl->flash_pgsz; + uint32_t off; + uint32_t cmp_size = (sl->flash_pgsz > 0x1800) ? 0x1800 : sl->flash_pgsz; ILOG("Starting verification of write complete\n"); for (off = 0; off < length; off += cmp_size) { - size_t aligned_size; + uint32_t aligned_size; // adjust last page size if ((off + cmp_size) > length) { @@ -1376,10 +1367,10 @@ int32_t stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *d aligned_size = (cmp_size + 4) & ~(4 - 1); } - stlink_read_mem32(sl, address + (uint32_t)off, (uint16_t)aligned_size); + stlink_read_mem32(sl, address + off, (uint16_t)aligned_size); if (memcmp(sl->q_buf, data + off, cmp_size)) { - ELOG("Verification of flash failed at offset: %u\n", (uint32_t)off); + ELOG("Verification of flash failed at offset: %u\n", off); return (-1); } } @@ -1389,7 +1380,7 @@ int32_t stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *d } // Check if an address and size are within the flash -int32_t stlink_check_address_range_validity(stlink_t *sl, stm32_addr_t addr, size_t size) { +int32_t stlink_check_address_range_validity(stlink_t *sl, stm32_addr_t addr, uint32_t size) { uint32_t logvar; if (addr < sl->flash_base || addr >= (sl->flash_base + sl->flash_size)) { logvar = sl->flash_base + sl->flash_size - 1; @@ -1436,7 +1427,7 @@ int32_t stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint3 ELOG("addr not a multiple of current pagesize (%u bytes), not supported, " "check page start address and compare with flash module organisation " "in related ST reference manual of your device.\n", - (uint32_t)(sl->flash_pgsz)); + sl->flash_pgsz); return (-1); } diff --git a/src/stlink-lib/common_flash.h b/src/stlink-lib/common_flash.h index fd1e51b9d..9b2b84057 100644 --- a/src/stlink-lib/common_flash.h +++ b/src/stlink-lib/common_flash.h @@ -37,13 +37,13 @@ void clear_flash_cr_pg(stlink_t *, uint32_t); // static void set_flash_cr_strt(stlink_t *sl, uint32_t bank); // static void set_flash_cr_mer(stlink_t *sl, bool v, uint32_t bank); int32_t stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr); -int32_t stlink_erase_flash_section(stlink_t *sl, stm32_addr_t base_addr, size_t size, bool align_size); +int32_t stlink_erase_flash_section(stlink_t *sl, stm32_addr_t base_addr, uint32_t size, bool align_size); int32_t stlink_erase_flash_mass(stlink_t *sl); int32_t stlink_mwrite_flash(stlink_t *sl, uint8_t *data, uint32_t length, stm32_addr_t addr); int32_t stlink_fwrite_flash(stlink_t *sl, const char *path, stm32_addr_t addr); int32_t stlink_fcheck_flash(stlink_t *sl, const char *path, stm32_addr_t addr); int32_t stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, uint32_t length); -int32_t stlink_check_address_range_validity(stlink_t *sl, stm32_addr_t addr, size_t size); +int32_t stlink_check_address_range_validity(stlink_t *sl, stm32_addr_t addr, uint32_t size); int32_t stlink_check_address_alignment(stlink_t *sl, stm32_addr_t addr); int32_t stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint32_t len, uint8_t eraseonly); void stlink_fwrite_finalize(stlink_t *, stm32_addr_t); diff --git a/src/stlink-lib/flash_loader.c b/src/stlink-lib/flash_loader.c index 2bac1ace0..a862bd0e7 100644 --- a/src/stlink-lib/flash_loader.c +++ b/src/stlink-lib/flash_loader.c @@ -162,7 +162,7 @@ static const uint8_t loader_code_stm32f7_lv[] = { int32_t stlink_flash_loader_init(stlink_t *sl, flash_loader_t *fl) { - size_t size = 0; + uint32_t size = 0; uint32_t dfsr, cfsr, hfsr; /* Interrupt masking according to DDI0419C, Table C1-7 firstly force halt */ @@ -172,8 +172,7 @@ int32_t stlink_flash_loader_init(stlink_t *sl, flash_loader_t *fl) { /* and only then disable interrupts */ stlink_write_debug32(sl, STLINK_REG_DHCSR, STLINK_REG_DHCSR_DBGKEY | STLINK_REG_DHCSR_C_DEBUGEN | - STLINK_REG_DHCSR_C_HALT | - STLINK_REG_DHCSR_C_MASKINTS); + STLINK_REG_DHCSR_C_HALT | STLINK_REG_DHCSR_C_MASKINTS); // allocate the loader in SRAM if (stlink_flash_loader_write_to_sram(sl, &fl->loader_addr, &size) == -1) { @@ -182,7 +181,7 @@ int32_t stlink_flash_loader_init(stlink_t *sl, flash_loader_t *fl) { } // allocate a one page buffer in SRAM right after loader - fl->buf_addr = fl->loader_addr + (uint32_t)size; + fl->buf_addr = fl->loader_addr + size; ILOG("Successfully loaded flash loader in sram\n"); // set address of IWDG key register for reset it @@ -210,9 +209,9 @@ int32_t stlink_flash_loader_init(stlink_t *sl, flash_loader_t *fl) { } static int32_t loader_v_dependent_assignment(stlink_t *sl, - const uint8_t **loader_code, size_t *loader_size, - const uint8_t *high_v_loader, size_t high_v_loader_size, - const uint8_t *low_v_loader, size_t low_v_loader_size) { + const uint8_t **loader_code, uint32_t *loader_size, + const uint8_t *high_v_loader, uint32_t high_v_loader_size, + const uint8_t *low_v_loader, uint32_t low_v_loader_size) { int32_t retval = 0; if ( sl->version.stlink_v == 1) { @@ -239,9 +238,9 @@ static int32_t loader_v_dependent_assignment(stlink_t *sl, return(retval); } -int32_t stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) { +int32_t stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, uint32_t* size) { const uint8_t* loader_code; - size_t loader_size; + uint32_t loader_size; if (sl->chip_id == STM32_CHIPID_L1_MD || sl->chip_id == STM32_CHIPID_L1_CAT2 || @@ -330,13 +329,13 @@ int32_t stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size return(0); // success } -int32_t stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, const uint8_t* buf, size_t size) { +int32_t stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, const uint8_t* buf, uint32_t size) { struct stlink_reg rr; uint32_t timeout; uint32_t flash_base = 0; uint32_t dhcsr, dfsr, cfsr, hfsr; - DLOG("Running flash loader, write address:%#x, size: %u\n", target, (uint32_t)size); + DLOG("Running flash loader, write address:%#x, size: %u\n", target, size); if (write_buffer_to_sram(sl, fl, buf, size) == -1) { ELOG("write_buffer_to_sram() == -1\n"); @@ -350,7 +349,7 @@ int32_t stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t t /* Setup core */ stlink_write_reg(sl, fl->buf_addr, 0); // source stlink_write_reg(sl, target, 1); // target - stlink_write_reg(sl, (uint32_t)size, 2); // count + stlink_write_reg(sl, size, 2); // count stlink_write_reg(sl, flash_base, 3); // flash register base // only used on VL/F1_XL, but harmless for others stlink_write_reg(sl, fl->loader_addr, 15); // pc register @@ -417,8 +416,7 @@ int32_t stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t t WLOG("Loader state: R2 0x%X R15 0x%X\n", rr.r[2], rr.r[15]); if (dhcsr != 0x3000B || dfsr || cfsr || hfsr) { - WLOG("MCU state: DHCSR 0x%X DFSR 0x%X CFSR 0x%X HFSR 0x%X\n", - dhcsr, dfsr, cfsr, hfsr); + WLOG("MCU state: DHCSR 0x%X DFSR 0x%X CFSR 0x%X HFSR 0x%X\n", dhcsr, dfsr, cfsr, hfsr); } return(-1); @@ -450,8 +448,7 @@ int32_t stm32l1_write_half_pages(stlink_t *sl, stm32_addr_t addr, uint8_t *base, for (count = 0; count < num_half_pages; count++) { if (use_loader) { - ret = stlink_flash_loader_run(sl, &fl, addr + count * pagesize, - base + count * pagesize, pagesize); + ret = stlink_flash_loader_run(sl, &fl, addr + count * pagesize, base + count * pagesize, pagesize); if (ret && count == 0) { /* It seems that stm32lx devices have a problem when it is blank */ WLOG("Failed to use flash loader, fallback to soft write\n"); @@ -461,7 +458,7 @@ int32_t stm32l1_write_half_pages(stlink_t *sl, stm32_addr_t addr, uint8_t *base, if (!use_loader) { ret = 0; for (off = 0; off < pagesize && !ret; off += 64) { - size_t chunk = (pagesize - off > 64) ? 64 : pagesize - off; + uint32_t chunk = (pagesize - off > 64) ? 64 : pagesize - off; memcpy(sl->q_buf, base + count * pagesize + off, chunk); ret = stlink_write_mem32(sl, addr + count * pagesize + off, (uint16_t)chunk); } @@ -632,9 +629,7 @@ int32_t stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { ILOG("enabling 32-bit flash writes\n"); write_flash_cr_psiz(sl, 2, BANK_1); } else { - ILOG("Target voltage (%d mV) too low for 32-bit flash, " - "using 8-bit flash writes\n", - voltage); + ILOG("Target voltage (%d mV) too low for 32-bit flash, using 8-bit flash writes\n", voltage); write_flash_cr_psiz(sl, 0, BANK_1); } } @@ -656,10 +651,8 @@ int32_t stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { uint32_t flash_regs_base = get_stm32l0_flash_base(sl); // disable pecr protection - stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, - FLASH_L0_PEKEY1); - stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, - FLASH_L0_PEKEY2); + stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, FLASH_L0_PEKEY1); + stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, FLASH_L0_PEKEY2); // check pecr.pelock is cleared stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); @@ -669,10 +662,8 @@ int32_t stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { } // unlock program memory - stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, - FLASH_L0_PRGKEY1); - stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, - FLASH_L0_PRGKEY2); + stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, FLASH_L0_PRGKEY1); + stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, FLASH_L0_PRGKEY2); // check pecr.prglock is cleared stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); @@ -728,17 +719,15 @@ int32_t stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { } int32_t stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t addr, uint8_t *base, uint32_t len) { - size_t off; + uint32_t off; if ((sl->flash_type == STM32_FLASH_TYPE_F2_F4) || (sl->flash_type == STM32_FLASH_TYPE_F7) || (sl->flash_type == STM32_FLASH_TYPE_L4)) { - size_t buf_size = (sl->sram_size > 0x8000) ? 0x8000 : 0x4000; + uint32_t buf_size = (sl->sram_size > 0x8000) ? 0x8000 : 0x4000; for (off = 0; off < len;) { - size_t size = len - off > buf_size ? buf_size : len - off; - if (stlink_flash_loader_run(sl, fl, addr + (uint32_t)off, base + off, - size) == -1) { - ELOG("stlink_flash_loader_run(%#x) failed! == -1\n", - (uint32_t)(addr + off)); + uint32_t size = len - off > buf_size ? buf_size : len - off; + if (stlink_flash_loader_run(sl, fl, addr + off, base + off, size) == -1) { + ELOG("stlink_flash_loader_run(%#x) failed! == -1\n", (addr + off)); check_flash_error(sl); return (-1); } @@ -749,38 +738,34 @@ int32_t stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t sl->flash_type == STM32_FLASH_TYPE_G0 || sl->flash_type == STM32_FLASH_TYPE_G4 || sl->flash_type == STM32_FLASH_TYPE_L5_U5) { - DLOG("Starting %3u page write\r\n", (uint32_t)(len / sl->flash_pgsz)); + DLOG("Starting %3u page write\n", len / sl->flash_pgsz); for (off = 0; off < len; off += sizeof(uint32_t)) { uint32_t data; if ((off % sl->flash_pgsz) > (sl->flash_pgsz - 5)) { - fprintf(stdout, "\r%3u/%3u pages written", - (uint32_t)(off / sl->flash_pgsz + 1), - (uint32_t)(len / sl->flash_pgsz)); + fprintf(stdout, "\r%3u/%3u pages written", (off / sl->flash_pgsz + 1), (len / sl->flash_pgsz)); fflush(stdout); } // write_uint32((unsigned char *)&data, *(uint32_t *)(base + off)); data = 0; memcpy(&data, base + off, (len - off) < 4 ? (len - off) : 4); - stlink_write_debug32(sl, addr + (uint32_t)off, data); + stlink_write_debug32(sl, addr + off, data); wait_flash_busy(sl); // wait for 'busy' bit in FLASH_SR to clear } fprintf(stdout, "\n"); // flash writes happen as 2 words at a time if ((off / sizeof(uint32_t)) % 2 != 0) { - stlink_write_debug32(sl, addr + (uint32_t)off, - 0); // write a single word of zeros - wait_flash_busy(sl); // wait for 'busy' bit in FLASH_SR to clear + stlink_write_debug32(sl, addr + off, 0); // write a single word of zeros + wait_flash_busy(sl); // wait for 'busy' bit in FLASH_SR to clear } } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { uint32_t val; uint32_t flash_regs_base = get_stm32l0_flash_base(sl); - uint32_t pagesize = (flash_regs_base == FLASH_L0_REGS_ADDR)? - L0_WRITE_BLOCK_SIZE:L1_WRITE_BLOCK_SIZE; + uint32_t pagesize = (flash_regs_base == FLASH_L0_REGS_ADDR)? L0_WRITE_BLOCK_SIZE : L1_WRITE_BLOCK_SIZE; - DLOG("Starting %3u page write\r\n", (uint32_t)(len / sl->flash_pgsz)); + DLOG("Starting %3u page write\r\n", len / sl->flash_pgsz); off = 0; @@ -797,14 +782,12 @@ int32_t stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t uint32_t data; if ((off % sl->flash_pgsz) > (sl->flash_pgsz - 5)) { - fprintf(stdout, "\r%3u/%3u pages written", - (uint32_t)(off / sl->flash_pgsz + 1), - (uint32_t)(len / sl->flash_pgsz)); + fprintf(stdout, "\r%3u/%3u pages written", (off / sl->flash_pgsz + 1), (len / sl->flash_pgsz)); fflush(stdout); } write_uint32((unsigned char *)&data, *(uint32_t *)(base + off)); - stlink_write_debug32(sl, addr + (uint32_t)off, data); + stlink_write_debug32(sl, addr + off, data); // wait for sr.busy to be cleared do { @@ -814,22 +797,19 @@ int32_t stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t // TODO: check redo write operation } fprintf(stdout, "\n"); - } else if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || - (sl->flash_type == STM32_FLASH_TYPE_F1_XL)) { + } else if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || (sl->flash_type == STM32_FLASH_TYPE_F1_XL)) { int32_t write_block_count = 0; for (off = 0; off < len; off += sl->flash_pgsz) { // adjust last write size - size_t size = len - off > sl->flash_pgsz ? sl->flash_pgsz : len - off; + uint32_t size = len - off > sl->flash_pgsz ? sl->flash_pgsz : len - off; // unlock and set programming mode unlock_flash_if(sl); DLOG("Finished unlocking flash, running loader!\n"); - if (stlink_flash_loader_run(sl, fl, addr + (uint32_t)off, base + off, - size) == -1) { - ELOG("stlink_flash_loader_run(%#x) failed! == -1\n", - (uint32_t)(addr + off)); + if (stlink_flash_loader_run(sl, fl, addr + off, base + off, size) == -1) { + ELOG("stlink_flash_loader_run(%#x) failed! == -1\n", (addr + off)); check_flash_error(sl); return (-1); } @@ -840,7 +820,7 @@ int32_t stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t // show progress; writing procedure is slow and previous errors are // misleading fprintf(stdout, "\r%3u/%3u pages written", ++write_block_count, - (uint32_t)((len + sl->flash_pgsz - 1) / sl->flash_pgsz)); + (len + sl->flash_pgsz - 1) / sl->flash_pgsz); fflush(stdout); } } @@ -850,17 +830,16 @@ int32_t stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { for (off = 0; off < len;) { // Program STM32H7x with 64-byte Flash words - size_t chunk = (len - off > 64) ? 64 : len - off; + uint32_t chunk = (len - off > 64) ? 64 : len - off; memcpy(sl->q_buf, base + off, chunk); - stlink_write_mem32(sl, addr + (uint32_t)off, 64); + stlink_write_mem32(sl, addr + off, 64); wait_flash_busy(sl); off += chunk; if (sl->verbose >= 1) { // show progress - fprintf(stdout, "\r%u/%u bytes written", (uint32_t)off, - (uint32_t)len); + fprintf(stdout, "\r%u/%u bytes written", off, len); fflush(stdout); } } diff --git a/src/stlink-lib/flash_loader.h b/src/stlink-lib/flash_loader.h index 06eb53d12..33edc7ac6 100644 --- a/src/stlink-lib/flash_loader.h +++ b/src/stlink-lib/flash_loader.h @@ -9,11 +9,11 @@ int32_t stlink_flash_loader_init(stlink_t *sl, flash_loader_t* fl); // static int32_t loader_v_dependent_assignment(stlink_t *sl, -// const uint8_t **loader_code, size_t *loader_size, -// const uint8_t *high_v_loader, size_t high_v_loader_size, -// const uint8_t *low_v_loader, size_t low_v_loader_size); -int32_t stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size); -int32_t stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, const uint8_t* buf, size_t size); +// const uint8_t **loader_code, uint32_t *loader_size, +// const uint8_t *high_v_loader, uint32_t high_v_loader_size, +// const uint8_t *low_v_loader, uint32_t low_v_loader_size); +int32_t stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, uint32_t* size); +int32_t stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, const uint8_t* buf, uint32_t size); /* === Functions from old header file flashloader.h === */ diff --git a/src/stlink-lib/map_file.c b/src/stlink-lib/map_file.c index 5e3d14a5d..e8c4b71a3 100644 --- a/src/stlink-lib/map_file.c +++ b/src/stlink-lib/map_file.c @@ -28,17 +28,17 @@ * STLINK2 Maybe STLINK V1 needs smaller value! */ int32_t check_file(stlink_t *sl, mapped_file_t *mf, stm32_addr_t addr) { - size_t off; - size_t n_cmp = sl->flash_pgsz; + uint32_t off; + uint32_t n_cmp = sl->flash_pgsz; if (n_cmp > 0x1800) { n_cmp = 0x1800; } for (off = 0; off < mf->len; off += n_cmp) { - size_t aligned_size; + uint32_t aligned_size; - size_t cmp_size = n_cmp; // adjust last page size + uint32_t cmp_size = n_cmp; // adjust last page size if ((off + n_cmp) > mf->len) { cmp_size = mf->len - off; @@ -50,7 +50,7 @@ int32_t check_file(stlink_t *sl, mapped_file_t *mf, stm32_addr_t addr) { aligned_size = (cmp_size + 4) & ~(4 - 1); } - stlink_read_mem32(sl, addr + (uint32_t)off, (uint16_t)aligned_size); + stlink_read_mem32(sl, addr + off, (uint16_t)aligned_size); if (memcmp(sl->q_buf, mf->base + off, cmp_size)) { return (-1); @@ -80,7 +80,7 @@ int32_t map_file(mapped_file_t *mf, const char *path) { // on 32 bit systems, check if there is an overflow if (st.st_size > (off_t)MAX_FILE_SIZE /*1 GB*/ ) { // limit file size to 1 GB - fprintf(stderr, "mmap() size_t overflow for file %s\n", path); + fprintf(stderr, "mmap() uint32_t overflow for file %s\n", path); goto on_error; } } diff --git a/src/stlink-lib/map_file.h b/src/stlink-lib/map_file.h index ba50e25e9..f25602d1e 100644 --- a/src/stlink-lib/map_file.h +++ b/src/stlink-lib/map_file.h @@ -20,7 +20,7 @@ /* Memory mapped file */ typedef struct mapped_file { uint8_t *base; - size_t len; + uint32_t len; } mapped_file_t; #define MAPPED_FILE_INITIALIZER \ diff --git a/src/stlink-lib/md5.c b/src/stlink-lib/md5.c index 9481acf0f..a5347de59 100644 --- a/src/stlink-lib/md5.c +++ b/src/stlink-lib/md5.c @@ -34,7 +34,7 @@ void stlink_checksum(mapped_file_t *mp) { uint32_t sum = 0; uint8_t *mp_byte = (uint8_t *)mp->base; - for (size_t i = 0; i < mp->len; ++i) { + for (uint32_t i = 0; i < mp->len; ++i) { sum += mp_byte[i]; } diff --git a/src/stlink-lib/option_bytes.h b/src/stlink-lib/option_bytes.h index ffeef8a0f..7ab3e2952 100644 --- a/src/stlink-lib/option_bytes.h +++ b/src/stlink-lib/option_bytes.h @@ -44,4 +44,4 @@ int32_t stlink_write_option_bytes32(stlink_t *sl, uint32_t option_byte); int32_t stlink_read_option_bytes_boot_add32(stlink_t *sl, uint32_t* option_byte); int32_t stlink_write_option_bytes_boot_add32(stlink_t *sl, uint32_t option_bytes_boot_add); -#endif // OPTION_BYTES_H \ No newline at end of file +#endif // OPTION_BYTES_H diff --git a/src/stlink-lib/read_write.c b/src/stlink-lib/read_write.c index 6ee697d66..9149080af 100644 --- a/src/stlink-lib/read_write.c +++ b/src/stlink-lib/read_write.c @@ -36,7 +36,7 @@ int32_t stlink_read_debug32(stlink_t *sl, uint32_t addr, uint32_t *data) { ret = sl->backend->read_debug32(sl, addr, data); if (!ret) - DLOG("*** stlink_read_debug32 %#010x at %#010x\n", *data, addr); + DLOG("*** stlink_read_debug32 %#010x at %#010x\n", *data, addr); return (ret); } diff --git a/src/stlink-lib/sg.c b/src/stlink-lib/sg.c index 0aa7a0d68..d7f844b51 100644 --- a/src/stlink-lib/sg.c +++ b/src/stlink-lib/sg.c @@ -103,7 +103,7 @@ #define STLINK_FALSE 0x81 static void clear_cdb(struct stlink_libsg *sl) { - for (size_t i = 0; i < sizeof(sl->cdb_cmd_blk); i++) { sl->cdb_cmd_blk[i] = 0; } + for (uint32_t i = 0; i < sizeof(sl->cdb_cmd_blk); i++) { sl->cdb_cmd_blk[i] = 0; } // set default sl->cdb_cmd_blk[0] = STLINK_DEBUG_COMMAND; diff --git a/src/stlink-lib/usb.c b/src/stlink-lib/usb.c index fc1dcbb4e..772fb147f 100644 --- a/src/stlink-lib/usb.c +++ b/src/stlink-lib/usb.c @@ -90,8 +90,8 @@ void _stlink_usb_close(stlink_t* sl) { } } -ssize_t send_recv(struct stlink_libusb* handle, int32_t terminate, unsigned char* txbuf, size_t txsize, - unsigned char* rxbuf, size_t rxsize, int32_t check_error, const char *cmd) { +ssize_t send_recv(struct stlink_libusb* handle, int32_t terminate, unsigned char* txbuf, uint32_t txsize, + unsigned char* rxbuf, uint32_t rxsize, int32_t check_error, const char *cmd) { // Note: txbuf and rxbuf can point to the same area int32_t res, t, retry = 0; @@ -168,7 +168,7 @@ ssize_t send_recv(struct stlink_libusb* handle, int32_t terminate, unsigned char } static inline int32_t send_only(struct stlink_libusb* handle, int32_t terminate, unsigned char* txbuf, - size_t txsize, const char *cmd) { + uint32_t txsize, const char *cmd) { return((int32_t)send_recv(handle, terminate, txbuf, txsize, NULL, 0, CMD_CHECK_NO, cmd)); } @@ -1000,7 +1000,7 @@ int32_t _stlink_usb_disable_trace(stlink_t* sl) { return(size<0?-1:0); } -int32_t _stlink_usb_read_trace(stlink_t* sl, uint8_t* buf, size_t size) { +int32_t _stlink_usb_read_trace(stlink_t* sl, uint8_t* buf, uint32_t size) { struct stlink_libusb * const slu = sl->backend_data; unsigned char* const data = sl->q_buf; unsigned char* const cmd = sl->c_buf; @@ -1160,7 +1160,7 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, enum connect_type connect, if (ret) { continue; } // could not open device - size_t serial_len = stlink_serial(handle, &desc, sl->serial); + uint32_t serial_len = stlink_serial(handle, &desc, sl->serial); libusb_close(handle); @@ -1300,12 +1300,12 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, enum connect_type connect, return(NULL); } -static size_t stlink_probe_usb_devs(libusb_device **devs, stlink_t **sldevs[], enum connect_type connect, int32_t freq) { +static uint32_t stlink_probe_usb_devs(libusb_device **devs, stlink_t **sldevs[], enum connect_type connect, int32_t freq) { stlink_t **_sldevs; libusb_device *dev; int32_t i = 0; - size_t slcnt = 0; - size_t slcur = 0; + uint32_t slcnt = 0; + uint32_t slcur = 0; /* Count STLINKs */ while ((dev = devs[i++]) != NULL) { @@ -1363,7 +1363,7 @@ static size_t stlink_probe_usb_devs(libusb_device **devs, stlink_t **sldevs[], e break; } - size_t serial_len = stlink_serial(handle, &desc, serial); + uint32_t serial_len = stlink_serial(handle, &desc, serial); libusb_close(handle); @@ -1388,7 +1388,7 @@ size_t stlink_probe_usb(stlink_t **stdevs[], enum connect_type connect, int32_t libusb_device **devs; stlink_t **sldevs; - size_t slcnt = 0; + uint32_t slcnt = 0; int32_t r; ssize_t cnt; @@ -1410,10 +1410,10 @@ size_t stlink_probe_usb(stlink_t **stdevs[], enum connect_type connect, int32_t return(slcnt); } -void stlink_probe_usb_free(stlink_t ***stdevs, size_t size) { +void stlink_probe_usb_free(stlink_t ***stdevs, uint32_t size) { if (stdevs == NULL || *stdevs == NULL || size == 0) { return; } - for (size_t n = 0; n < size; n++) { stlink_close((*stdevs)[n]); } + for (uint32_t n = 0; n < size; n++) { stlink_close((*stdevs)[n]); } free(*stdevs); *stdevs = NULL; diff --git a/src/stlink-lib/usb.h b/src/stlink-lib/usb.h index dd30cc529..2ec7490ad 100644 --- a/src/stlink-lib/usb.h +++ b/src/stlink-lib/usb.h @@ -62,10 +62,10 @@ struct stlink_libusb { // static inline uint32_t le_to_h_u32(const uint8_t* buf); // static int32_t _stlink_match_speed_map(const uint32_t *map, uint32_t map_size, uint32_t khz); void _stlink_usb_close(stlink_t* sl); -ssize_t send_recv(struct stlink_libusb* handle, int32_t terminate, unsigned char* txbuf, size_t txsize, - unsigned char* rxbuf, size_t rxsize, int32_t check_error, const char *cmd); +ssize_t send_recv(struct stlink_libusb* handle, int32_t terminate, unsigned char* txbuf, uint32_t txsize, + unsigned char* rxbuf, uint32_t rxsize, int32_t check_error, const char *cmd); // static inline int32_t send_only(struct stlink_libusb* handle, int32_t terminate, unsigned char* txbuf, -// size_t txsize, const char *cmd); +// uint32_t txsize, const char *cmd); // static int32_t fill_command(stlink_t * sl, enum SCSI_Generic_Direction dir, uint32_t len); int32_t _stlink_usb_version(stlink_t *sl); int32_t _stlink_usb_target_voltage(stlink_t *sl); @@ -96,14 +96,14 @@ int32_t _stlink_usb_write_unsupported_reg(stlink_t *sl, uint32_t val, int32_t r_ int32_t _stlink_usb_write_reg(stlink_t *sl, uint32_t reg, int32_t idx); int32_t _stlink_usb_enable_trace(stlink_t* sl, uint32_t frequency); int32_t _stlink_usb_disable_trace(stlink_t* sl); -int32_t _stlink_usb_read_trace(stlink_t* sl, uint8_t* buf, size_t size); +int32_t _stlink_usb_read_trace(stlink_t* sl, uint8_t* buf, uint32_t size); // static stlink_backend_t _stlink_usb_backend = { }; size_t stlink_serial(struct libusb_device_handle *handle, struct libusb_device_descriptor *desc, char *serial); stlink_t *stlink_open_usb(enum ugly_loglevel verbose, enum connect_type connect, char serial[STLINK_SERIAL_BUFFER_SIZE], int32_t freq); -// static size_t stlink_probe_usb_devs(libusb_device **devs, stlink_t **sldevs[], enum connect_type connect, int32_t freq); +// static uint32_t stlink_probe_usb_devs(libusb_device **devs, stlink_t **sldevs[], enum connect_type connect, int32_t freq); size_t stlink_probe_usb(stlink_t **stdevs[], enum connect_type connect, int32_t freq); -void stlink_probe_usb_free(stlink_t **stdevs[], size_t size); +void stlink_probe_usb_free(stlink_t **stdevs[], uint32_t size); #endif // USB_H diff --git a/src/win32/getopt/getopt.c b/src/win32/getopt/getopt.c index 7bc8d2d20..417b0aecf 100644 --- a/src/win32/getopt/getopt.c +++ b/src/win32/getopt/getopt.c @@ -134,7 +134,7 @@ int32_t getopt_long(int32_t argc, const struct option* o = longopts; const struct option* match = NULL; int32_t num_matches = 0; - size_t argument_name_length = 0; + uint32_t argument_name_length = 0; const char* current_argument = NULL; int32_t retval = -1; diff --git a/src/win32/mmap.c b/src/win32/mmap.c index ea8a3cb37..7e76b3344 100644 --- a/src/win32/mmap.c +++ b/src/win32/mmap.c @@ -6,7 +6,7 @@ #include "mmap.h" -void *mmap (void *addr, size_t len, int32_t prot, int32_t flags, int32_t fd, int64_t offset) { +void *mmap (void *addr, uint32_t len, int32_t prot, int32_t flags, int32_t fd, int64_t offset) { void *buf; ssize_t count; @@ -32,7 +32,7 @@ void *mmap (void *addr, size_t len, int32_t prot, int32_t flags, int32_t fd, int (void)flags; } -int32_t munmap (void *addr, size_t len) { +int32_t munmap (void *addr, uint32_t len) { free (addr); return(0); (void)len; diff --git a/src/win32/mmap.h b/src/win32/mmap.h index e8bbab0bc..633816b50 100644 --- a/src/win32/mmap.h +++ b/src/win32/mmap.h @@ -15,8 +15,8 @@ #define MAP_ANONYMOUS (1 << 5) #define MAP_FAILED ((void *)-1) -void *mmap(void *addr, size_t len, int32_t prot, int32_t flags, int32_t fd, int64_t offset); -int32_t munmap(void *addr, size_t len); +void *mmap(void *addr, uint32_t len, int32_t prot, int32_t flags, int32_t fd, int64_t offset); +int32_t munmap(void *addr, uint32_t len); #endif // STLINK_HAVE_SYS_MMAN_H diff --git a/tests/flash.c b/tests/flash.c index a40be0c74..67436ecb1 100644 --- a/tests/flash.c +++ b/tests/flash.c @@ -26,7 +26,7 @@ static bool cmp_strings(const char * s1, const char * s2) { } } -static bool cmp_mem(const uint8_t * s1, const uint8_t * s2, size_t size) { +static bool cmp_mem(const uint8_t * s1, const uint8_t * s2, uint32_t size) { if (s1 == NULL || s2 == NULL) { return (s1 == s2); } else { @@ -231,7 +231,7 @@ static struct Test tests[] = { int32_t main() { bool allOk = true; - for (size_t i = 0; i < sizeof(tests) / sizeof(tests[0]); ++i) + for (uint32_t i = 0; i < sizeof(tests) / sizeof(tests[0]); ++i) if (!execute_test(&tests[i])) allOk = false; From 5d3f3ec7f492b76ce7f1ba4327eeeeeff13c5be8 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sat, 10 Jun 2023 21:37:01 +0200 Subject: [PATCH 453/503] Set flash_type for STM32H5 devices --- config/chips/H5xx.chip | 2 +- config/chips/L5x5xx.chip | 2 +- config/chips/U5x5.chip | 2 +- inc/stm32.h | 2 +- src/stlink-lib/chipid.c | 4 +-- src/stlink-lib/common_flash.c | 52 ++++++++++++++++------------------- src/stlink-lib/flash_loader.c | 12 ++++---- 7 files changed, 36 insertions(+), 40 deletions(-) diff --git a/config/chips/H5xx.chip b/config/chips/H5xx.chip index a1c438999..8484fbc18 100644 --- a/config/chips/H5xx.chip +++ b/config/chips/H5xx.chip @@ -3,7 +3,7 @@ dev_type STM32H5xx ref_manual_id 0481 chip_id 0x484 // STM32_CHIPID_H5xx -flash_type L5_U5 // ? +flash_type L5_U5_H5 flash_size_reg 0x08fff80c flash_pagesize 0x2000 // 8 KB sram_size 0xa0000 // 640 KB diff --git a/config/chips/L5x5xx.chip b/config/chips/L5x5xx.chip index 0f205a62b..eace313d0 100644 --- a/config/chips/L5x5xx.chip +++ b/config/chips/L5x5xx.chip @@ -3,7 +3,7 @@ dev_type STM32L5x2xx ref_manual_id 0438 chip_id 0x472 // STM32_CHIPID_L5x2xx -flash_type L5_U5 +flash_type L5_U5_H5 flash_size_reg 0x0bfa05e0 flash_pagesize 0x1000 // 4 KB sram_size 0x40000 // 256 KB diff --git a/config/chips/U5x5.chip b/config/chips/U5x5.chip index 5f71436ef..82964b1c3 100644 --- a/config/chips/U5x5.chip +++ b/config/chips/U5x5.chip @@ -3,7 +3,7 @@ dev_type STM32U5x5 ref_manual_id 0456 chip_id 0x482 // STM32_CHIPID_U5x5 -flash_type L5_U5 +flash_type L5_U5_H5 flash_size_reg 0x0bfa07a0 flash_pagesize 0x2000 // 8 KB sram_size 0xc4800 // 786 KB diff --git a/inc/stm32.h b/inc/stm32.h index eee1b0433..cf9a8a2ad 100644 --- a/inc/stm32.h +++ b/inc/stm32.h @@ -60,7 +60,7 @@ enum stm32_flash_type { STM32_FLASH_TYPE_H7 = 7, STM32_FLASH_TYPE_L0_L1 = 8, STM32_FLASH_TYPE_L4 = 9, - STM32_FLASH_TYPE_L5_U5 = 10, + STM32_FLASH_TYPE_L5_U5_H5 = 10, STM32_FLASH_TYPE_WB_WL = 11, }; diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index 0392f15ff..06edb26f3 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -115,8 +115,8 @@ void process_chipfile(char *fname) { ts->flash_type = STM32_FLASH_TYPE_L0_L1; } else if (strcmp(value, "L4") == 0) { ts->flash_type = STM32_FLASH_TYPE_L4; - } else if (strcmp(value, "L5_U5") == 0) { - ts->flash_type = STM32_FLASH_TYPE_L5_U5; + } else if (strcmp(value, "L5_U5_H5") == 0) { + ts->flash_type = STM32_FLASH_TYPE_L5_U5_H5; } else if (strcmp(value, "WB_WL") == 0) { ts->flash_type = STM32_FLASH_TYPE_WB_WL; } else { diff --git a/src/stlink-lib/common_flash.c b/src/stlink-lib/common_flash.c index 70c8a2216..f2281ac11 100644 --- a/src/stlink-lib/common_flash.c +++ b/src/stlink-lib/common_flash.c @@ -56,7 +56,7 @@ uint32_t read_flash_cr(stlink_t *sl, uint32_t bank) { reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { reg = FLASH_L4_CR; - } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5_H5) { reg = FLASH_L5_NSCR; } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { reg = FLASH_WB_CR; @@ -101,7 +101,7 @@ void lock_flash(stlink_t *sl) { } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { cr_reg = FLASH_L4_CR; cr_lock_shift = FLASH_L4_CR_LOCK; - } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5_H5) { cr_reg = FLASH_L5_NSCR; cr_lock_shift = FLASH_L5_NSCR_NSLOCK; } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { @@ -147,7 +147,7 @@ static inline int32_t write_flash_sr(stlink_t *sl, uint32_t bank, uint32_t val) sr_reg = get_stm32l0_flash_base(sl) + FLASH_SR_OFF; } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { sr_reg = FLASH_L4_SR; - } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5_H5) { sr_reg = FLASH_L5_NSSR; } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { sr_reg = FLASH_WB_SR; @@ -190,7 +190,7 @@ void clear_flash_error(stlink_t *sl) { case STM32_FLASH_TYPE_L4: write_flash_sr(sl, BANK_1, FLASH_L4_SR_ERROR_MASK); break; - case STM32_FLASH_TYPE_L5_U5: + case STM32_FLASH_TYPE_L5_U5_H5: write_flash_sr(sl, BANK_1, FLASH_L5_NSSR_ERROR_MASK); break; case STM32_FLASH_TYPE_WB_WL: @@ -220,7 +220,7 @@ uint32_t read_flash_sr(stlink_t *sl, uint32_t bank) { sr_reg = get_stm32l0_flash_base(sl) + FLASH_SR_OFF; } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { sr_reg = FLASH_L4_SR; - } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5_H5) { sr_reg = FLASH_L5_NSSR; } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { sr_reg = FLASH_WB_SR; @@ -252,7 +252,7 @@ uint32_t is_flash_busy(stlink_t *sl) { sr_busy_shift = FLASH_H7_SR_QW; } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { sr_busy_shift = FLASH_L4_SR_BSY; - } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5_H5) { sr_busy_shift = FLASH_L5_NSSR_BSY; } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { sr_busy_shift = FLASH_WB_SR_BSY; @@ -335,7 +335,7 @@ int32_t check_flash_error(stlink_t *sl) { PROGERR = (1 << FLASH_L4_SR_PROGERR); PGAERR = (1 << FLASH_L4_SR_PGAERR); break; - case STM32_FLASH_TYPE_L5_U5: + case STM32_FLASH_TYPE_L5_U5_H5: res = read_flash_sr(sl, BANK_1) & FLASH_L5_NSSR_ERROR_MASK; WRPERR = (1 << FLASH_L5_NSSR_NSWRPERR); PROGERR = (1 << FLASH_L5_NSSR_NSPROGERR); @@ -401,7 +401,7 @@ static inline uint32_t is_flash_locked(stlink_t *sl) { } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { cr_reg = FLASH_L4_CR; cr_lock_shift = FLASH_L4_CR_LOCK; - } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5_H5) { cr_reg = FLASH_L5_NSCR; cr_lock_shift = FLASH_L5_NSCR_NSLOCK; } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { @@ -448,7 +448,7 @@ static void unlock_flash(stlink_t *sl) { flash_key2 = FLASH_L0_PEKEY2; } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { key_reg = FLASH_L4_KEYR; - } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5_H5) { // Set voltage scaling to range 0 to perform flash operations (RM0438 p. 183) uint32_t mask = (0b11 << STM32L5_PWR_CR1_VOS); uint32_t val; @@ -526,7 +526,7 @@ int32_t lock_flash_option(stlink_t *sl) { optcr_reg = FLASH_L4_CR; optlock_shift = FLASH_L4_CR_OPTLOCK; break; - case STM32_FLASH_TYPE_L5_U5: + case STM32_FLASH_TYPE_L5_U5_H5: optcr_reg = FLASH_L5_NSCR; optlock_shift = FLASH_L5_NSCR_OPTLOCK; break; @@ -601,7 +601,7 @@ static bool is_flash_option_locked(stlink_t *sl) { optcr_reg = FLASH_L4_CR; optlock_shift = FLASH_L4_CR_OPTLOCK; break; - case STM32_FLASH_TYPE_L5_U5: + case STM32_FLASH_TYPE_L5_U5_H5: optcr_reg = FLASH_L5_NSCR; optlock_shift = FLASH_L5_NSCR_OPTLOCK; break; @@ -658,7 +658,7 @@ static int32_t unlock_flash_option(stlink_t *sl) { case STM32_FLASH_TYPE_L4: optkey_reg = FLASH_L4_OPTKEYR; break; - case STM32_FLASH_TYPE_L5_U5: + case STM32_FLASH_TYPE_L5_U5_H5: optkey_reg = FLASH_L5_OPTKEYR; break; case STM32_FLASH_TYPE_WB_WL: @@ -734,7 +734,7 @@ void clear_flash_cr_pg(stlink_t *sl, uint32_t bank) { bit = FLASH_H7_CR_PG; } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { cr_reg = FLASH_L4_CR; - } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5_H5) { cr_reg = FLASH_L5_NSCR; } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { cr_reg = FLASH_WB_CR; @@ -801,7 +801,7 @@ static void set_flash_cr_per(stlink_t *sl, uint32_t bank) { if (sl->flash_type == STM32_FLASH_TYPE_G0 || sl->flash_type == STM32_FLASH_TYPE_G4) { cr_reg = FLASH_Gx_CR; - } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5_H5) { cr_reg = FLASH_L5_NSCR; } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { cr_reg = FLASH_WB_CR; @@ -820,7 +820,7 @@ static void clear_flash_cr_per(stlink_t *sl, uint32_t bank) { if (sl->flash_type == STM32_FLASH_TYPE_G0 || sl->flash_type == STM32_FLASH_TYPE_G4) { cr_reg = FLASH_Gx_CR; - } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5_H5) { cr_reg = FLASH_L5_NSCR; } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { cr_reg = FLASH_WB_CR; @@ -867,7 +867,7 @@ static void set_flash_cr_strt(stlink_t *sl, uint32_t bank) { } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { cr_reg = FLASH_L4_CR; cr_strt = (1 << FLASH_L4_CR_STRT); - } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5_H5) { cr_reg = FLASH_L5_NSCR; cr_strt = (1 << FLASH_L5_NSCR_NSSTRT); } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { @@ -910,7 +910,7 @@ static void set_flash_cr_mer(stlink_t *sl, bool v, uint32_t bank) { cr_reg = FLASH_L4_CR; cr_mer = (1 << FLASH_L4_CR_MER1) | (1 << FLASH_L4_CR_MER2); cr_pg = (1 << FLASH_L4_CR_PG); - } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5_H5) { cr_reg = FLASH_L5_NSCR; cr_mer = (1 << FLASH_L5_NSCR_NSMER1) | (1 << FLASH_L5_NSCR_NSMER2); cr_pg = (1 << FLASH_L5_NSCR_NSPG); @@ -1059,7 +1059,7 @@ int32_t stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || sl->flash_type == STM32_FLASH_TYPE_G4 || - sl->flash_type == STM32_FLASH_TYPE_L5_U5 || + sl->flash_type == STM32_FLASH_TYPE_L5_U5_H5 || sl->flash_type == STM32_FLASH_TYPE_WB_WL) { uint32_t val; unlock_flash_if(sl); @@ -1080,7 +1080,7 @@ int32_t stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { val &= ~(0x7F << 3); val |= ((flash_page & 0x7F) << 3) | (1 << FLASH_CR_PER); stlink_write_debug32(sl, FLASH_Gx_CR, val); - } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5_H5) { uint32_t flash_page; stlink_read_debug32(sl, FLASH_L5_NSCR, &val); if (sl->flash_pgsz == 0x800 && (flashaddr - STM32_FLASH_BASE) >= sl->flash_size/2) { @@ -1182,7 +1182,7 @@ int32_t stlink_erase_flash_mass(stlink_t *sl) { // TODO: User MER bit to mass-erase WB series. if (sl->flash_type == STM32_FLASH_TYPE_L0_L1 || - sl->flash_type == STM32_FLASH_TYPE_WB_WL) { + sl->flash_type == STM32_FLASH_TYPE_WB_WL) { err = stlink_erase_flash_section(sl, sl->flash_base, sl->flash_size, false); @@ -1191,8 +1191,7 @@ int32_t stlink_erase_flash_mass(stlink_t *sl) { clear_flash_error(sl); unlock_flash_if(sl); - if (sl->flash_type == STM32_FLASH_TYPE_H7 && - sl->chip_id != STM32_CHIPID_H7Ax) { + if (sl->flash_type == STM32_FLASH_TYPE_H7 && sl->chip_id != STM32_CHIPID_H7Ax) { // set parallelism write_flash_cr_psiz(sl, 3 /*64it*/, BANK_1); if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { @@ -1205,8 +1204,7 @@ int32_t stlink_erase_flash_mass(stlink_t *sl) { sl, BANK_1); // start erase operation, reset by hw with busy bit if (sl->flash_type == STM32_FLASH_TYPE_F1_XL || - (sl->flash_type == STM32_FLASH_TYPE_H7 && - sl->chip_flags & CHIP_F_HAS_DUAL_BANK)) { + (sl->flash_type == STM32_FLASH_TYPE_H7 && sl->chip_flags & CHIP_F_HAS_DUAL_BANK)) { set_flash_cr_mer(sl, 1, BANK_2); // set the mass erase bit in bank 2 set_flash_cr_strt(sl, BANK_2); // start erase operation in bank 2 } @@ -1217,8 +1215,7 @@ int32_t stlink_erase_flash_mass(stlink_t *sl) { // reset the mass erase bit set_flash_cr_mer(sl, 0, BANK_1); if (sl->flash_type == STM32_FLASH_TYPE_F1_XL || - (sl->flash_type == STM32_FLASH_TYPE_H7 && - sl->chip_flags & CHIP_F_HAS_DUAL_BANK)) { + (sl->flash_type == STM32_FLASH_TYPE_H7 && sl->chip_flags & CHIP_F_HAS_DUAL_BANK)) { set_flash_cr_mer(sl, 0, BANK_2); } @@ -1316,8 +1313,7 @@ int32_t stlink_fwrite_flash(stlink_t *sl, const char *path, stm32_addr_t addr) { * still flash the whole file even if ignoring message is printed. */ err = stlink_write_flash(sl, addr, mf.base, - (num_empty == mf.len) ? (uint32_t)mf.len - : (uint32_t)mf.len - num_empty, + (num_empty == mf.len) ? (uint32_t)mf.len : (uint32_t)mf.len - num_empty, num_empty == mf.len); stlink_fwrite_finalize(sl, addr); unmap_file(&mf); diff --git a/src/stlink-lib/flash_loader.c b/src/stlink-lib/flash_loader.c index a862bd0e7..0ab8cf6c1 100644 --- a/src/stlink-lib/flash_loader.c +++ b/src/stlink-lib/flash_loader.c @@ -501,7 +501,7 @@ static void set_flash_cr_pg(stlink_t *sl, uint32_t bank) { cr_reg = FLASH_L4_CR; x &= ~FLASH_L4_CR_OPBITS; x |= (1 << FLASH_L4_CR_PG); - } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5_H5) { cr_reg = FLASH_L5_NSCR; x |= (1 << FLASH_CR_PG); } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || @@ -556,7 +556,7 @@ static void set_dma_state(stlink_t *sl, flash_loader_t *fl, int32_t bckpRstr) { rcc_dma_mask = STM32L0_RCC_DMAEN; } break; - case STM32_FLASH_TYPE_L5_U5: + case STM32_FLASH_TYPE_L5_U5_H5: rcc = STM32L5_RCC_AHB1ENR; rcc_dma_mask = STM32L5_RCC_DMAEN; break; @@ -639,8 +639,8 @@ int32_t stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL || sl->flash_type == STM32_FLASH_TYPE_G0 || sl->flash_type == STM32_FLASH_TYPE_G4 || - sl->flash_type == STM32_FLASH_TYPE_L5_U5) { - ILOG("Starting Flash write for WB/G0/G4/L5/U5\n"); + sl->flash_type == STM32_FLASH_TYPE_L5_U5_H5) { + ILOG("Starting Flash write for WB/G0/G4/L5/U5/H5\n"); unlock_flash_if(sl); // unlock flash if necessary set_flash_cr_pg(sl, BANK_1); // set PG 'allow programming' bit @@ -737,7 +737,7 @@ int32_t stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL || sl->flash_type == STM32_FLASH_TYPE_G0 || sl->flash_type == STM32_FLASH_TYPE_G4 || - sl->flash_type == STM32_FLASH_TYPE_L5_U5) { + sl->flash_type == STM32_FLASH_TYPE_L5_U5_H5) { DLOG("Starting %3u page write\n", len / sl->flash_pgsz); for (off = 0; off < len; off += sizeof(uint32_t)) { uint32_t data; @@ -864,7 +864,7 @@ int32_t stlink_flashloader_stop(stlink_t *sl, flash_loader_t *fl) { (sl->flash_type == STM32_FLASH_TYPE_G4) || (sl->flash_type == STM32_FLASH_TYPE_H7) || (sl->flash_type == STM32_FLASH_TYPE_L4) || - (sl->flash_type == STM32_FLASH_TYPE_L5_U5) || + (sl->flash_type == STM32_FLASH_TYPE_L5_U5_H5) || (sl->flash_type == STM32_FLASH_TYPE_WB_WL)) { clear_flash_cr_pg(sl, BANK_1); From 2c337615c945f79fa882ca6714279125e2619d11 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 11 Jun 2023 14:29:23 +0200 Subject: [PATCH 454/503] [refactoring] Clean-up for stlink-flash & -info - Ensure proper function declaration - Checked & revised header includes --- CMakeLists.txt | 3 +++ inc/stlink.h | 9 ++------- src/st-flash/flash.c | 20 ++++++++++++++----- src/st-flash/flash.h | 36 +++++++++------------------------ src/st-flash/flash_opts.c | 15 +++++++++++--- src/st-flash/flash_opts.h | 40 +++++++++++++++++++++++++++++++++++++ src/st-info/info.c | 14 ++++++++++--- src/st-info/info.h | 18 +++++++++++++++++ src/st-trace/trace.c | 5 ++++- src/st-util/gdb-server.c | 14 ++++++++----- src/stlink-gui/gui.c | 5 ++++- src/stlink-lib/chipid.h | 2 +- src/stlink-lib/usb.c | 42 +++++++++++++++++++-------------------- tests/flash.c | 1 + tests/sg.c | 3 +++ tests/usb.c | 3 +++ 16 files changed, 155 insertions(+), 75 deletions(-) create mode 100644 src/st-flash/flash_opts.h create mode 100644 src/st-info/info.h diff --git a/CMakeLists.txt b/CMakeLists.txt index 2a82ea983..511144eae 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -154,6 +154,9 @@ include_directories(${PROJECT_BINARY_DIR}/inc) # contains version.h include_directories(src) include_directories(src/st-flash) +include_directories(src/st-info) +include_directories(src/st-trace) +include_directories(src/st-util) include_directories(src/stlink-lib) ## Set installation directory for header files diff --git a/inc/stlink.h b/inc/stlink.h index d5d036725..ed93b34b7 100644 --- a/inc/stlink.h +++ b/inc/stlink.h @@ -234,6 +234,8 @@ struct _stlink { uint32_t max_trace_freq; // set by stlink_open_usb() }; +/* Functions defined in common.c */ + int32_t stlink_enter_swd_mode(stlink_t *sl); int32_t stlink_enter_jtag_mode(stlink_t *sl); int32_t stlink_exit_debug_mode(stlink_t *sl); @@ -284,14 +286,7 @@ int32_t stlink_fread(stlink_t* sl, const char* path, bool is_ihex, stm32_addr_t int32_t stlink_load_device_params(stlink_t *sl); int32_t stlink_target_connect(stlink_t *sl, enum connect_type connect); -#include -#include -#include -#include -#include #include -#include -#include #ifdef __cplusplus } diff --git a/src/st-flash/flash.c b/src/st-flash/flash.c index 9a648bd63..711d7d2eb 100644 --- a/src/st-flash/flash.c +++ b/src/st-flash/flash.c @@ -1,23 +1,33 @@ -/* Simple wrapper around the stlink_flash_write function */ +/* + * File: flash.c + * + * Tool st-flash - Simple wrapper around the stlink_flash_write function + */ -#include #include +#include #include #include #include #include -#include + +#if defined(_WIN32) +#include +#else #include +#endif // _WIN32 #include #include +#include "flash.h" +#include "flash_opts.h" +#include #include #include #include - -#include "flash.h" +#include static stlink_t *connected_stlink = NULL; diff --git a/src/st-flash/flash.h b/src/st-flash/flash.h index 84c171158..889b2e4c4 100644 --- a/src/st-flash/flash.h +++ b/src/st-flash/flash.h @@ -1,36 +1,18 @@ +/* + * File: flash.h + * + * Tool st-flash + */ + #ifndef FLASH_H #define FLASH_H -#include - -#include - #define DEBUG_LOG_LEVEL 100 #define STND_LOG_LEVEL 50 #define ENABLE_OPT 1 -enum flash_cmd {FLASH_CMD_NONE = 0, FLASH_CMD_WRITE = 1, FLASH_CMD_READ = 2, FLASH_CMD_ERASE = 3, CMD_RESET = 4}; -enum flash_format {FLASH_FORMAT_BINARY = 0, FLASH_FORMAT_IHEX = 1}; -enum flash_area {FLASH_MAIN_MEMORY = 0, FLASH_SYSTEM_MEMORY = 1, FLASH_OTP = 2, FLASH_OPTION_BYTES = 3, FLASH_OPTION_BYTES_BOOT_ADD = 4, FLASH_OPTCR = 5, FLASH_OPTCR1 = 6}; -struct flash_opts { - enum flash_cmd cmd; - uint8_t serial[STLINK_SERIAL_BUFFER_SIZE]; - const char* filename; - stm32_addr_t addr; - uint32_t size; - int32_t reset; - int32_t log_level; - enum flash_format format; - enum flash_area area; - uint32_t val; - uint32_t flash_size; // --flash=n[k, M] - int32_t opt; // enable empty tail data drop optimization - int32_t freq; // --freq=n[k, M] frequency of JTAG/SWD - enum connect_type connect; -}; - -#define FLASH_OPTS_INITIALIZER {0, { 0 }, NULL, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} - -int32_t flash_get_opts(struct flash_opts* o, int32_t ac, char** av); +// static stlink_t *connected_stlink = NULL; +// static void cleanup(int32_t signum); +// static void usage(void); #endif // FLASH_H diff --git a/src/st-flash/flash_opts.c b/src/st-flash/flash_opts.c index 35763ad50..358074793 100644 --- a/src/st-flash/flash_opts.c +++ b/src/st-flash/flash_opts.c @@ -1,12 +1,21 @@ +/* + * File: flash_opts.c + * + * Flash Options + */ + #include -#include #include +#include #include -#include - +#include +#include +#include "flash_opts.h" #include "flash.h" +#include + static bool starts_with(const char * str, const char * prefix) { uint32_t n = strlen(prefix); diff --git a/src/st-flash/flash_opts.h b/src/st-flash/flash_opts.h new file mode 100644 index 000000000..0c0083db6 --- /dev/null +++ b/src/st-flash/flash_opts.h @@ -0,0 +1,40 @@ +/* + * File: flash_opts.h + * + * Flash Options + */ + +#ifndef FLASH_OPTS_H +#define FLASH_OPTS_H + +#define FLASH_OPTS_INITIALIZER {0, { 0 }, NULL, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} + +enum flash_cmd {FLASH_CMD_NONE = 0, FLASH_CMD_WRITE = 1, FLASH_CMD_READ = 2, FLASH_CMD_ERASE = 3, CMD_RESET = 4}; +enum flash_format {FLASH_FORMAT_BINARY = 0, FLASH_FORMAT_IHEX = 1}; +enum flash_area {FLASH_MAIN_MEMORY = 0, FLASH_SYSTEM_MEMORY = 1, FLASH_OTP = 2, FLASH_OPTION_BYTES = 3, FLASH_OPTION_BYTES_BOOT_ADD = 4, FLASH_OPTCR = 5, FLASH_OPTCR1 = 6}; + +struct flash_opts { + enum flash_cmd cmd; + uint8_t serial[STLINK_SERIAL_BUFFER_SIZE]; + const char* filename; + stm32_addr_t addr; + uint32_t size; + int32_t reset; + int32_t log_level; + enum flash_format format; + enum flash_area area; + uint32_t val; + uint32_t flash_size; // --flash=n[k, M] + int32_t opt; // enable empty tail data drop optimization + int32_t freq; // --freq=n[k, M] frequency of JTAG/SWD + enum connect_type connect; +}; + +// static bool starts_with(const char * str, const char * prefix); +// static int32_t get_long_integer_from_char_array (const char *const str, uint64_t *read_value); +// static int32_t get_integer_from_char_array (const char *const str, uint32_t *read_value); +// static int32_t invalid_args(const char *expected); +// static int32_t bad_arg(const char *arg); +int32_t flash_get_opts(struct flash_opts* o, int32_t ac, char** av); + +#endif // FLASH_OPTS_H diff --git a/src/st-info/info.c b/src/st-info/info.c index b6ec0ccd2..664db7b2a 100644 --- a/src/st-info/info.c +++ b/src/st-info/info.c @@ -1,11 +1,19 @@ -#include +/* + * File: stinfo.c + * + * Tool st-info + */ + #include -#include +#include #include -#include #include +#include "info.h" + +#include #include +#include static void usage(void) { puts("st-info --version"); diff --git a/src/st-info/info.h b/src/st-info/info.h new file mode 100644 index 000000000..8e978e678 --- /dev/null +++ b/src/st-info/info.h @@ -0,0 +1,18 @@ +/* + * File: info.h + * + * Tool st-info + */ + +#ifndef INFO_H +#define INFO_H + +// static void usage(void); +// static void stlink_print_version(stlink_t *sl); +// static void stlink_print_info(stlink_t *sl); + +// static void stlink_probe(enum connect_type connect, int32_t freq) { }; +static int32_t print_data(int32_t ac, char **av); +int32_t main(int32_t ac, char** av); + +#endif // INFO_H \ No newline at end of file diff --git a/src/st-trace/trace.c b/src/st-trace/trace.c index ccbd74e16..56170d7c0 100644 --- a/src/st-trace/trace.c +++ b/src/st-trace/trace.c @@ -10,9 +10,12 @@ #include #include +#include + +#include #include #include -#include +#include #define DEFAULT_LOGGING_LEVEL 50 #define DEBUG_LOGGING_LEVEL 100 diff --git a/src/st-util/gdb-server.c b/src/st-util/gdb-server.c index 7232f0f69..9f9d93844 100644 --- a/src/st-util/gdb-server.c +++ b/src/st-util/gdb-server.c @@ -27,14 +27,18 @@ #endif #include -#include -#include -#include -#include -#include "gdb-remote.h" #include "gdb-server.h" +#include "gdb-remote.h" #include "semihosting.h" +#include +#include +#include +#include +#include +#include +#include + #define FLASH_BASE 0x08000000 // Semihosting doesn't have a short option, we define a value to identify it diff --git a/src/stlink-gui/gui.c b/src/stlink-gui/gui.c index af2afcdbf..5853e5ec4 100644 --- a/src/stlink-gui/gui.c +++ b/src/stlink-gui/gui.c @@ -5,9 +5,12 @@ #include #include -#include #include "gui.h" +#include +#include +#include + #define MEM_READ_SIZE 1024 #ifndef G_VALUE_INIT diff --git a/src/stlink-lib/chipid.h b/src/stlink-lib/chipid.h index a72a40be9..6726a7420 100644 --- a/src/stlink-lib/chipid.h +++ b/src/stlink-lib/chipid.h @@ -21,7 +21,7 @@ struct stlink_chipid_params { uint32_t option_base; uint32_t option_size; uint32_t flags; - struct stlink_chipid_params * next; + struct stlink_chipid_params *next; }; struct stlink_chipid_params *stlink_chipid_get_params(uint32_t chipid); diff --git a/src/stlink-lib/usb.c b/src/stlink-lib/usb.c index 772fb147f..c2425b6cd 100644 --- a/src/stlink-lib/usb.c +++ b/src/stlink-lib/usb.c @@ -103,8 +103,7 @@ ssize_t send_recv(struct stlink_libusb* handle, int32_t terminate, unsigned char ELOG("%s send request failed: %s\n", cmd, libusb_error_name(t)); return(-1); } else if ((size_t)res != txsize) { - ELOG("%s send request wrote %u bytes, instead of %u\n", - cmd, (uint32_t)res, (uint32_t)txsize); + ELOG("%s send request wrote %u bytes, instead of %u\n", cmd, (uint32_t)res, (uint32_t)txsize); } if (rxsize != 0) { @@ -215,7 +214,7 @@ int32_t _stlink_usb_version(stlink_t *sl) { size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_REP_LEN, "GET_VERSION"); - return(size<0?-1:0); + return(size < 0 ? -1 : 0); } int32_t _stlink_usb_target_voltage(stlink_t *sl) { @@ -279,7 +278,7 @@ int32_t _stlink_usb_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data) { write_uint32(&cmd[i + 4], data); size = send_recv(slu, 1, cmd, slu->cmd_len, rdata, rep_len, CMD_CHECK_RETRY, "WRITEDEBUGREG"); - return(size<0?-1:0); + return(size < 0 ? -1 : 0); } int32_t _stlink_usb_get_rw_status(stlink_t *sl) { @@ -302,7 +301,7 @@ int32_t _stlink_usb_get_rw_status(stlink_t *sl) { ret = send_recv(slu, 1, cmd, slu->cmd_len, rdata, 2, CMD_CHECK_STATUS, "GETLASTRWSTATUS"); } - return(ret<0?-1:0); + return(ret < 0 ? -1 : 0); } int32_t _stlink_usb_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { @@ -450,7 +449,7 @@ int32_t _stlink_usb_status(stlink_t * sl) { sl->core_stat = TARGET_UNKNOWN; } - return(size<0?-1:0); + return(size < 0 ? -1 : 0); } int32_t _stlink_usb_force_debug(stlink_t *sl) { @@ -473,7 +472,7 @@ int32_t _stlink_usb_force_debug(stlink_t *sl) { cmd[i++] = STLINK_DEBUG_FORCEDEBUG; size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_RETRY, "FORCEDEBUG"); - return(size<0?-1:0); + return(size < 0 ? -1 : 0); } int32_t _stlink_usb_enter_swd_mode(stlink_t * sl) { @@ -490,7 +489,7 @@ int32_t _stlink_usb_enter_swd_mode(stlink_t * sl) { cmd[i++] = STLINK_DEBUG_ENTER_SWD; size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_RETRY, "ENTER_SWD"); - return(size<0?-1:0); + return(size < 0 ? -1 : 0); } int32_t _stlink_usb_exit_dfu_mode(stlink_t* sl) { @@ -503,7 +502,7 @@ int32_t _stlink_usb_exit_dfu_mode(stlink_t* sl) { cmd[i++] = STLINK_DFU_EXIT; size = send_only(slu, 1, cmd, slu->cmd_len, "DFU_EXIT"); - return(size<0?-1:0); + return(size < 0 ? -1 : 0); } @@ -526,7 +525,7 @@ int32_t _stlink_usb_reset(stlink_t * sl) { size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_RETRY, "RESETSYS"); - return(size<0?-1:0); + return(size < 0 ? -1 : 0); } int32_t _stlink_usb_jtag_reset(stlink_t * sl, int32_t value) { @@ -542,7 +541,7 @@ int32_t _stlink_usb_jtag_reset(stlink_t * sl, int32_t value) { cmd[i++] = value; size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_RETRY, "DRIVE_NRST"); - return(size<0?-1:0); + return(size < 0 ? -1 : 0); } @@ -556,7 +555,7 @@ int32_t _stlink_usb_step(stlink_t* sl) { _stlink_usb_write_debug32(sl, STLINK_REG_DHCSR, STLINK_REG_DHCSR_DBGKEY | STLINK_REG_DHCSR_C_STEP | STLINK_REG_DHCSR_C_MASKINTS | STLINK_REG_DHCSR_C_DEBUGEN); return _stlink_usb_write_debug32(sl, STLINK_REG_DHCSR, STLINK_REG_DHCSR_DBGKEY | STLINK_REG_DHCSR_C_HALT | - STLINK_REG_DHCSR_C_DEBUGEN); + STLINK_REG_DHCSR_C_DEBUGEN); } unsigned char* const data = sl->q_buf; @@ -569,7 +568,7 @@ int32_t _stlink_usb_step(stlink_t* sl) { cmd[i++] = STLINK_DEBUG_STEPCORE; size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_RETRY, "STEPCORE"); - return(size<0?-1:0); + return(size < 0 ? -1 : 0); } /** @@ -583,8 +582,7 @@ int32_t _stlink_usb_run(stlink_t* sl, enum run_type type) { int32_t res; if (sl->version.jtag_api != STLINK_JTAG_API_V1) { - res = _stlink_usb_write_debug32(sl, STLINK_REG_DHCSR, - STLINK_REG_DHCSR_DBGKEY | STLINK_REG_DHCSR_C_DEBUGEN | + res = _stlink_usb_write_debug32(sl, STLINK_REG_DHCSR, STLINK_REG_DHCSR_DBGKEY | STLINK_REG_DHCSR_C_DEBUGEN | ((type==RUN_FLASH_LOADER)?STLINK_REG_DHCSR_C_MASKINTS:0)); return(res); } @@ -600,7 +598,7 @@ int32_t _stlink_usb_run(stlink_t* sl, enum run_type type) { cmd[i++] = STLINK_DEBUG_RUNCORE; size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_RETRY, "RUNCORE"); - return(size<0?-1:0); + return(size < 0 ? -1 : 0); } int32_t _stlink_usb_set_swdclk(stlink_t* sl, int32_t clk_freq) { @@ -643,7 +641,7 @@ int32_t _stlink_usb_set_swdclk(stlink_t* sl, int32_t clk_freq) { cmd[i++] = (clk_divisor >> 8) & 0xFF; size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_RETRY, "SWD_SET_FREQ"); - return(size<0?-1:0); + return(size < 0 ? -1 : 0); } else if (sl->version.stlink_v == 3) { int32_t speed_index; uint32_t map[STLINK_V3_MAX_FREQ_NB]; @@ -684,7 +682,7 @@ int32_t _stlink_usb_set_swdclk(stlink_t* sl, int32_t clk_freq) { size = send_recv(slu, 1, cmd, slu->cmd_len, data, 8, CMD_CHECK_STATUS, "SET_COM_FREQ"); - return(size<0?-1:0); + return(size < 0 ? -1 : 0); } else if (clk_freq) { WLOG("ST-Link firmware does not support frequency setup\n"); } @@ -703,7 +701,7 @@ int32_t _stlink_usb_exit_debug_mode(stlink_t *sl) { size = send_only(slu, 1, cmd, slu->cmd_len, "DEBUG_EXIT"); - return(size<0?-1:0); + return(size < 0 ? -1 : 0); } int32_t _stlink_usb_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { @@ -963,7 +961,7 @@ int32_t _stlink_usb_write_reg(stlink_t *sl, uint32_t reg, int32_t idx) { write_uint32(&cmd[i], reg); size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_RETRY, "WRITEREG"); - return(size<0?-1:0); + return(size < 0 ? -1 : 0); } int32_t _stlink_usb_enable_trace(stlink_t* sl, uint32_t frequency) { @@ -981,7 +979,7 @@ int32_t _stlink_usb_enable_trace(stlink_t* sl, uint32_t frequency) { size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_STATUS, "START_TRACE_RX"); - return(size<0?-1:0); + return(size < 0 ? -1 : 0); } int32_t _stlink_usb_disable_trace(stlink_t* sl) { @@ -997,7 +995,7 @@ int32_t _stlink_usb_disable_trace(stlink_t* sl) { size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_STATUS, "STOP_TRACE_RX"); - return(size<0?-1:0); + return(size < 0 ? -1 : 0); } int32_t _stlink_usb_read_trace(stlink_t* sl, uint8_t* buf, uint32_t size) { diff --git a/tests/flash.c b/tests/flash.c index 67436ecb1..f4c838d5d 100644 --- a/tests/flash.c +++ b/tests/flash.c @@ -7,6 +7,7 @@ #include #include +#include #if defined(_MSC_VER) #include diff --git a/tests/sg.c b/tests/sg.c index 32dcd9a62..6881266ab 100644 --- a/tests/sg.c +++ b/tests/sg.c @@ -7,6 +7,9 @@ #include +#include +#include + #if defined(_MSC_VER) #define __attribute__(x) #endif diff --git a/tests/usb.c b/tests/usb.c index 56f0d9c1f..9acd0b02d 100644 --- a/tests/usb.c +++ b/tests/usb.c @@ -6,6 +6,9 @@ #include +#include +#include + static void usage(void) { puts("test-usb --reset"); puts("test-usb --no-reset"); From b72f5b5acf8997a299d9eac4d6cc2dfc5322e144 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Mon, 12 Jun 2023 11:56:21 +0200 Subject: [PATCH 455/503] Fixed compilation on Windows - [doc] Updated installation instructions - Fixed cmd bug in mingw64-build.bat - Fixed cmake building for WIN32 --- CMakeLists.txt | 19 ++++++++++++++++++- doc/compiling.md | 16 +++++++++------- mingw64-build.bat | 5 +++-- 3 files changed, 30 insertions(+), 10 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index 511144eae..7e7d92705 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -74,7 +74,7 @@ include(${CMAKE_MODULE_PATH}/get_version.cmake) # Determine project version include(GNUInstallDirs) # Define GNU standard installation directories -# Define install directory /usr/local/share +# Define install directory for st-link shared files cmake_host_system_information(RESULT OS_NAME QUERY OS_NAME) message(STATUS "Checking for OS_NAME: ${OS_NAME}") @@ -160,7 +160,11 @@ include_directories(src/st-util) include_directories(src/stlink-lib) ## Set installation directory for header files +if (WIN32) +set(STLINK_INCLUDE_PATH ${CMAKE_INSTALL_INCLUDEDIR} CACHE PATH "Main include install directory") +else () set(STLINK_INCLUDE_PATH ${CMAKE_INSTALL_INCLUDEDIR}/${PROJECT_NAME} CACHE PATH "Main include install directory") +endif () ## Subordinate CMakeLists for version config & header installation add_subdirectory(inc) @@ -275,6 +279,15 @@ install(TARGETS ${STLINK_LIB_SHARED} RUNTIME DESTINATION ${CMAKE_INSTALL_BINDIR} ) +# Copy libusb DLL-library to binary output folder +if (WIN32) +file(COPY ${LIBUSB_WIN_OUTPUT_FOLDER}/MinGW64/dll/libusb-1.0.dll + DESTINATION ${CMAKE_INSTALL_BINDIR}) +file(COPY ${LIBUSB_WIN_OUTPUT_FOLDER}/MinGW64/dll/libusb-1.0.dll + DESTINATION ${CMAKE_INSTALL_PREFIX}/${CMAKE_INSTALL_BINDIR}) +endif () + + ### # Static library ### @@ -369,7 +382,11 @@ endif () ### # MCU configuration files +if (WIN32) +set(CMAKE_CHIPS_DIR ${CMAKE_INSTALL_PREFIX}/config/chips) +else () set(CMAKE_CHIPS_DIR ${CMAKE_INSTALL_SHAREDIR}/${PROJECT_NAME}/chips) +endif () add_definitions( -DSTLINK_CHIPS_DIR="${CMAKE_CHIPS_DIR}" ) file(GLOB CHIP_FILES ${CMAKE_SOURCE_DIR}/config/chips/*.chip) install(FILES ${CHIP_FILES} DESTINATION ${CMAKE_CHIPS_DIR}) diff --git a/doc/compiling.md b/doc/compiling.md index eec46bb3d..775d2363e 100644 --- a/doc/compiling.md +++ b/doc/compiling.md @@ -8,7 +8,8 @@ On Windows users should ensure that the following software is installed: - `git` (_optional, but recommended_) - `cmake` -- `MinGW-w64` (7.0.0 or later) with GCC toolchain 8.1.0 +- `7-zip` +- `MinGW-w64` ### Installation @@ -17,13 +18,13 @@ On Windows users should ensure that the following software is installed: Ensure that you add cmake to the $PATH system variable when following the instructions by the setup assistant. 3. Install -- _EITHER_: **MinGW-w64** from (mingw-w64-install.exe)
-- _OR_: **MSVC toolchain** from Visual Studio Build Tools 2019 + - _EITHER_: Download **MinGW-w64** from . Extract content to `C:\mingw-w64\` and add `C:\mingw-w64\bin\` to PATH-Variable.
+ - _OR_: **MSVC toolchain** from Visual Studio Build Tools 2019 4. Create a new destination folder at a place of your choice 5. Open the command-line (cmd.exe) and execute `cd C:\$Path-to-your-destination-folder$\` 6. Fetch the project sourcefiles by running `git clone https://github.com/stlink-org/stlink.git`from the command-line (cmd.exe)
- or download the stlink zip-sourcefolder from the Release page on GitHub + or download and extract the stlink zip-sourcefolder from the Release page on GitHub. #### MSVC toolchain - minimal installation @@ -48,11 +49,12 @@ Visual Studio IDE is not necessary, only Windows SDK & build tools are required #### MinGW-w64 -1. Use the command-line to move to the `scripts` directory within the source-folder: `cd stlink\scripts\` -2. Execute `./mingw64-build.bat` +1. Open command-line with administrator privileges +2. Move to the `stlink` directory +3. Execute `mingw64-build.bat` NOTE:
-Per default the build script (currently) uses `C:\Program Files\mingw-w64\x86_64-8.1.0-release-win32-sjlj-rt_v6-rev0\mingw64\bin`.
+Per default the build script (currently) uses `C:\mingw-w64\x86_64-8.1.0-release-win32-sjlj-rt_v6-rev0\mingw64\bin`.
When installing different toolchains make sure to update the path in the `mingw64-build.bat`.
This can be achieved by opening the .bat file with a common text editor. diff --git a/mingw64-build.bat b/mingw64-build.bat index eeaacddab..b52e529e2 100644 --- a/mingw64-build.bat +++ b/mingw64-build.bat @@ -2,8 +2,9 @@ mkdir build-mingw cd build-mingw -set PATH=C:\Program Files (x86)\CMake\bin;C:\Program Files\CMake\bin;C:\Program Files\mingw-w64\x86_64-8.1.0-win32-sjlj-rt_v6-rev0\mingw64\bin;%PATH% +set PATH=C:\Program Files (x86)\CMake\bin;C:\Program Files\CMake\bin;C:\mingw-w64\x86_64-8.1.0-win32-sjlj-rt_v6-rev0\mingw64\bin;%PATH% cmake -G "MinGW Makefiles" .. mingw32-make -mingw32-make install DESTDIR=install +mingw32-make install mingw32-make package +cd .. From 101d77bf7e6c32c9e9b565301bd6dd9092c033cc Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sat, 24 Jun 2023 23:55:12 +0200 Subject: [PATCH 456/503] Formatting & style fixes. --- CMakeLists.txt | 36 +++---- cmake/modules/Findlibusb.cmake | 18 ++-- cmake/modules/c_flags.cmake | 8 +- cmake/modules/get_version.cmake | 16 +-- cmake/modules/pandocology.cmake | 38 ++++---- cmake/packaging/cpack_config.cmake | 2 +- doc/man/CMakeLists.txt | 6 +- src/st-flash/flash.c | 6 +- src/st-flash/flash_opts.c | 56 +++++------ src/st-info/info.c | 16 +-- src/st-util/gdb-remote.c | 24 ++--- src/st-util/gdb-server.c | 66 ++++++------- src/st-util/semihosting.c | 80 +++++++-------- src/stlink-gui/CMakeLists.txt | 4 +- src/stlink-gui/gui.c | 38 ++++---- src/stlink-lib/flash_loader.c | 30 +++--- src/stlink-lib/lib_md5.c | 2 +- src/stlink-lib/sg.c | 144 +++++++++++++-------------- src/stlink-lib/usb.c | 150 ++++++++++++++--------------- src/win32/getopt/getopt.c | 10 +- src/win32/mmap.c | 12 +-- src/win32/sys_time.c | 4 +- src/win32/win32_socket.c | 28 +++--- tests/flash.c | 4 +- tests/sg.c | 4 +- tests/usb.c | 4 +- 26 files changed, 402 insertions(+), 404 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index 7e7d92705..c0957a034 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -91,7 +91,7 @@ else () set(CMAKE_C_FLAGS_MINSIZEREL_INIT "/MT /O1 /Ob1 /D NDEBUG") set(CMAKE_C_FLAGS_RELEASE_INIT "/MT /O2 /Ob2 /D NDEBUG") set(CMAKE_C_FLAGS_RELWITHDEBINFO_INIT "/MT /Zi /O2 /Ob1 /D NDEBUG") -endif () +endif() ### @@ -111,10 +111,10 @@ if (_stack_chk_fail_exists) set(SSP_LIB -static ssp) else () set(SSP_LIB ssp) - endif () + endif() else () set(SSP_LIB "") -endif () +endif() CHECK_INCLUDE_FILE(sys/mman.h STLINK_HAVE_SYS_MMAN_H) if (STLINK_HAVE_SYS_MMAN_H) @@ -129,17 +129,17 @@ endif() CHECK_INCLUDE_FILE(unistd.h STLINK_HAVE_UNISTD_H) if (STLINK_HAVE_UNISTD_H) add_definitions(-DSTLINK_HAVE_UNISTD_H) -endif () +endif() CHECK_INCLUDE_FILE(dirent.h STLINK_HAVE_DIRENT_H) if (STLINK_HAVE_DIRENT_H) add_definitions(-DSTLINK_HAVE_DIRENT_H) -endif () +endif() if (MSVC) # Use string.h rather than strings.h and disable annoying warnings add_definitions(-DHAVE_STRING_H -D_CRT_SECURE_NO_WARNINGS -D_CRT_NONSTDC_NO_WARNINGS /wd4710) -endif () +endif() ### @@ -164,7 +164,7 @@ if (WIN32) set(STLINK_INCLUDE_PATH ${CMAKE_INSTALL_INCLUDEDIR} CACHE PATH "Main include install directory") else () set(STLINK_INCLUDE_PATH ${CMAKE_INSTALL_INCLUDEDIR}/${PROJECT_NAME} CACHE PATH "Main include install directory") -endif () +endif() ## Subordinate CMakeLists for version config & header installation add_subdirectory(inc) @@ -218,7 +218,7 @@ if (WIN32) # Add drop-in replacement for unistd.h to sources include_directories(src/win32/unistd) set(STLINK_HEADERS "${STLINK_HEADERS};src/win32/unistd/unistd.h") - endif () + endif() if (NOT STLINK_HAVE_SYS_MMAN_H) include_directories(src/win32/mmap) @@ -230,12 +230,12 @@ if (WIN32) set(STLINK_SOURCE "${STLINK_SOURCE};src/win32/sys_time.c") set(STLINK_HEADERS "${STLINK_HEADERS};src/win32/sys_time.h") endif() -endif () +endif() ## Include test execution for test-targets for target Debug if (${CMAKE_BUILD_TYPE} MATCHES "Debug") include(CTest) -endif () +endif() ### @@ -271,7 +271,7 @@ if (WIN32) # ... with Windows libraries target_link_libraries(${STLINK_LIB_SHARED} ${LIBUSB_LIBRARY} ${SSP_LIB} wsock32 ws2_32) else () target_link_libraries(${STLINK_LIB_SHARED} ${LIBUSB_LIBRARY} ${SSP_LIB}) -endif () +endif() install(TARGETS ${STLINK_LIB_SHARED} ARCHIVE DESTINATION ${CMAKE_INSTALL_LIBDIR} @@ -285,7 +285,7 @@ file(COPY ${LIBUSB_WIN_OUTPUT_FOLDER}/MinGW64/dll/libusb-1.0.dll DESTINATION ${CMAKE_INSTALL_BINDIR}) file(COPY ${LIBUSB_WIN_OUTPUT_FOLDER}/MinGW64/dll/libusb-1.0.dll DESTINATION ${CMAKE_INSTALL_PREFIX}/${CMAKE_INSTALL_BINDIR}) -endif () +endif() ### @@ -317,7 +317,7 @@ if (WIN32) # ... with Windows libraries target_link_libraries(${STLINK_LIB_STATIC} ${LIBUSB_LIBRARY} ${SSP_LIB} wsock32 ws2_32) else () target_link_libraries(${STLINK_LIB_STATIC} ${LIBUSB_LIBRARY} ${SSP_LIB}) -endif () +endif() install(TARGETS ${STLINK_LIB_STATIC} ARCHIVE DESTINATION ${CMAKE_INSTALL_LIBDIR}) @@ -336,7 +336,7 @@ if (MSVC) include_directories(src/win32/getopt) set(ST-UTIL_SOURCES "${ST-UTIL_SOURCES};src/win32/getopt/getopt.c") set(ST-TRACE_SOURCES "${ST-TRACE_SOURCES};src/win32/getopt/getopt.c") -endif () +endif() add_executable(st-flash ${ST-FLASH_SOURCES}) add_executable(st-info ${ST-INFO_SOURCES}) @@ -353,7 +353,7 @@ else () target_link_libraries(st-info ${STLINK_LIB_SHARED} ${SSP_LIB}) target_link_libraries(st-util ${STLINK_LIB_SHARED} ${SSP_LIB}) target_link_libraries(st-trace ${STLINK_LIB_SHARED} ${SSP_LIB}) -endif () +endif() install(TARGETS st-flash DESTINATION ${CMAKE_INSTALL_BINDIR}) install(TARGETS st-info DESTINATION ${CMAKE_INSTALL_BINDIR}) @@ -374,7 +374,7 @@ if (CMAKE_SYSTEM_NAME STREQUAL "Linux") set(STLINK_UDEV_RULES_DIR "/lib/udev/rules.d" CACHE PATH "udev rules directory") file(GLOB RULES_FILES ${CMAKE_SOURCE_DIR}/config/udev/rules.d/*.rules) install(FILES ${RULES_FILES} DESTINATION ${STLINK_UDEV_RULES_DIR}) -endif () +endif() ### @@ -386,7 +386,7 @@ if (WIN32) set(CMAKE_CHIPS_DIR ${CMAKE_INSTALL_PREFIX}/config/chips) else () set(CMAKE_CHIPS_DIR ${CMAKE_INSTALL_SHAREDIR}/${PROJECT_NAME}/chips) -endif () +endif() add_definitions( -DSTLINK_CHIPS_DIR="${CMAKE_CHIPS_DIR}" ) file(GLOB CHIP_FILES ${CMAKE_SOURCE_DIR}/config/chips/*.chip) install(FILES ${CHIP_FILES} DESTINATION ${CMAKE_CHIPS_DIR}) @@ -413,4 +413,4 @@ if (NOT TARGET uninstall) uninstall COMMAND ${CMAKE_COMMAND} -P ${CMAKE_CURRENT_BINARY_DIR}/cmake/cmake_uninstall.cmake ) -endif () +endif() diff --git a/cmake/modules/Findlibusb.cmake b/cmake/modules/Findlibusb.cmake index 6f0a21da6..830060486 100644 --- a/cmake/modules/Findlibusb.cmake +++ b/cmake/modules/Findlibusb.cmake @@ -24,7 +24,7 @@ if (CMAKE_SYSTEM_NAME STREQUAL "FreeBSD") # FreeBSD; libusb is mark_as_advanced(LIBUSB_INCLUDE_DIR LIBUSB_LIBRARY) if (NOT LIBUSB_FOUND) message(FATAL_ERROR "Expected libusb library not found on your system! Verify your system integrity.") - endif () + endif() elseif (CMAKE_SYSTEM_NAME STREQUAL "OpenBSD") # OpenBSD; libusb-1.0 is available from ports FIND_PATH( @@ -41,7 +41,7 @@ elseif (CMAKE_SYSTEM_NAME STREQUAL "OpenBSD") # OpenBSD; libusb-1.0 mark_as_advanced(LIBUSB_INCLUDE_DIR LIBUSB_LIBRARY) if (NOT LIBUSB_FOUND) message(FATAL_ERROR "No libusb-1.0 library found on your system! Install libusb-1.0 from ports or packages.") - endif () + endif() elseif (WIN32 OR (EXISTS "/etc/debian_version" AND MINGW)) # Windows or MinGW-toolchain on Debian # MinGW/MSYS/MSVC: 64-bit or 32-bit? @@ -51,7 +51,7 @@ elseif (WIN32 OR (EXISTS "/etc/debian_version" AND MINGW)) # Windows or MinGW-to else () message(STATUS "=== Building for Windows (i686) ===") set(ARCH 32) - endif () + endif() if (WIN32 AND NOT EXISTS "/etc/debian_version") # Skip this for Debian... # Preparations for installing libusb library @@ -63,7 +63,7 @@ elseif (WIN32 OR (EXISTS "/etc/debian_version" AND MINGW)) # Windows or MinGW-to elseif (EXISTS "/etc/debian_version" AND MINGW) # ... only for cross-building on Debian set(LIBUSB_WIN_ARCHIVE_PATH ${CMAKE_SOURCE_DIR}/build-mingw-${ARCH}/${LIBUSB_WIN_ARCHIVE}) set(LIBUSB_WIN_OUTPUT_FOLDER ${CMAKE_SOURCE_DIR}/build-mingw-${ARCH}/3rdparty/libusb-${LIBUSB_WIN_VERSION}) - endif () + endif() # Get libusb package if (EXISTS ${LIBUSB_WIN_ARCHIVE_PATH}) # ... should the package be already there (for whatever reason) @@ -74,7 +74,7 @@ elseif (WIN32 OR (EXISTS "/etc/debian_version" AND MINGW)) # Windows or MinGW-to https://sourceforge.net/projects/libusb/files/libusb-1.0/libusb-${LIBUSB_WIN_VERSION}/libusb-${LIBUSB_WIN_VERSION}.7z/download ${LIBUSB_WIN_ARCHIVE_PATH} EXPECTED_MD5 aabe177bde869bfad34278335eaf8955 ) - endif () + endif() file(MAKE_DIRECTORY ${LIBUSB_WIN_OUTPUT_FOLDER}) @@ -110,9 +110,9 @@ elseif (WIN32 OR (EXISTS "/etc/debian_version" AND MINGW)) # Windows or MinGW-to NO_DEFAULT_PATH NO_CMAKE_FIND_ROOT_PATH ) - endif () + endif() message(STATUS "Missing libusb library has been installed") - endif () + endif() FIND_PACKAGE_HANDLE_STANDARD_ARGS(libusb DEFAULT_MSG LIBUSB_LIBRARY LIBUSB_INCLUDE_DIR) mark_as_advanced(LIBUSB_INCLUDE_DIR LIBUSB_LIBRARY) @@ -132,5 +132,5 @@ else () if (NOT LIBUSB_FOUND) message(FATAL_ERROR "libusb library not found on your system! Install libusb 1.0.x from your package repository.") - endif () -endif () + endif() +endif() diff --git a/cmake/modules/c_flags.cmake b/cmake/modules/c_flags.cmake index 6e22d4ff3..d30f45ec9 100644 --- a/cmake/modules/c_flags.cmake +++ b/cmake/modules/c_flags.cmake @@ -14,7 +14,7 @@ function(add_cflag_if_supported flag) if (C_SUPPORTS${flagclean}) set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} ${flag}" PARENT_SCOPE) - endif () + endif() endfunction() add_cflag_if_supported("-Wall") @@ -38,14 +38,14 @@ add_cflag_if_supported("-Wimplicit-function-declaration") ## if (NOT CMAKE_SYSTEM_NAME STREQUAL "OpenBSD") add_cflag_if_supported("-Wredundant-decls") -endif () +endif() if (NOT (WIN32 OR (EXISTS "/etc/debian_version" AND MINGW))) add_cflag_if_supported("-fPIC") -endif () +endif() if (${CMAKE_BUILD_TYPE} MATCHES "Debug") add_cflag_if_supported("-ggdb") else () add_cflag_if_supported("-Werror") -endif () +endif() diff --git a/cmake/modules/get_version.cmake b/cmake/modules/get_version.cmake index 8211d9c84..07c5793df 100644 --- a/cmake/modules/get_version.cmake +++ b/cmake/modules/get_version.cmake @@ -28,7 +28,7 @@ if (GIT_FOUND AND EXISTS "${PROJECT_SOURCE_DIR}/.git") ) if (res EQUAL 1) set(PROJECT_VERSION "${PROJECT_VERSION}-dirty") - endif () + endif() # Strip a leading v off of the version as proceeding code expects just the version numbering. string(REGEX REPLACE "^v" "" PROJECT_VERSION ${PROJECT_VERSION}) @@ -53,14 +53,14 @@ if (GIT_FOUND AND EXISTS "${PROJECT_SOURCE_DIR}/.git") # ...the version does not match with git-version string if (NOT __version_str STREQUAL __version_file) message(STATUS "Rewrite ${PROJECT_SOURCE_DIR}/.version with ${__version_str}!") - endif () + endif() elseif (NOT EXISTS "${PROJECT_SOURCE_DIR}/.version") # No local .version file found: Create a new one... file(WRITE "${PROJECT_SOURCE_DIR}/.version" ${__version_str}) - endif () + endif() message(STATUS "stlink version: ${PROJECT_VERSION}") message(STATUS "Major ${PROJECT_VERSION_MAJOR} Minor ${PROJECT_VERSION_MINOR} Patch ${PROJECT_VERSION_PATCH}") @@ -68,13 +68,13 @@ if (GIT_FOUND AND EXISTS "${PROJECT_SOURCE_DIR}/.git") else (len EQUAL 3) message(STATUS "Failed to extract version parts from \"${PROJECT_VERSION}\"") set(ERROR_FLAG "1") - endif (len EQUAL 3) + endif(len EQUAL 3) else (GIT_DESCRIBE_RESULT EQUAL 0) message(WARNING "git describe failed: ${GIT_DESCRIBE_ERROR}") set(ERROR_FLAG "1") endif(GIT_DESCRIBE_RESULT EQUAL 0) -endif () +endif() ## # Failure to read version via git @@ -101,9 +101,9 @@ if (NOT GIT_FOUND OR NOT EXISTS "${PROJECT_SOURCE_DIR}/.git" OR ERROR_FLAG EQUAL set(__detect_version 1) else () message(STATUS "Fail to extract version parts from \"${PROJECT_VERSION}\"") - endif () + endif() else (EXISTS ${PROJECT_SOURCE_DIR}/.version) message(STATUS "File \"${PROJECT_SOURCE_DIR}/.version\" does not exist.") message(FATAL_ERROR "Unable to determine project version") - endif () -endif () + endif() +endif() diff --git a/cmake/modules/pandocology.cmake b/cmake/modules/pandocology.cmake index ff9053197..24cd4b9a1 100644 --- a/cmake/modules/pandocology.cmake +++ b/cmake/modules/pandocology.cmake @@ -45,7 +45,7 @@ include(CMakeParseArguments) if (NOT EXISTS ${PANDOC_EXECUTABLE}) find_program(PANDOC_EXECUTABLE pandoc) mark_as_advanced(PANDOC_EXECUTABLE) -endif () +endif() ############################################################################### # Based on code from UseLATEX @@ -133,7 +133,7 @@ This process created the file `CMakeCache.txt' and the directory `CMakeFiles'. Please delete them: $ rm -r CMakeFiles/ CmakeCache.txt ") - ENDif () + endif() endfunction() # This builds a document @@ -171,7 +171,7 @@ function(add_document target_name) if (NOT PANDOC_EXECUTABLE) message(WARNING "Pandoc not found. Install Pandoc (http://johnmacfarlane.net/pandoc/) or set cache variable PANDOC_EXECUTABLE.") return() - endif () + endif() set(options EXPORT_ARCHIVE NO_EXPORT_PRODUCT EXPORT_PDF DIRECT_TEX_TO_PDF VERBOSE) set(oneValueArgs PRODUCT_DIRECTORY) @@ -188,29 +188,29 @@ function(add_document target_name) if (NOT "${target_extension}" STREQUAL ".tex" AND NOT "${target_extension}" STREQUAL ".latex") # if (NOT "${target_extension}" STREQUAL ".tex") MESSAGE(FATAL_ERROR "Target '${target_name}': Cannot use 'EXPORT_PDF' for target of type '${target_extension}': target type must be '.tex' or '.latex'") - endif () - endif () + endif() + endif() if (${ADD_DOCUMENT_DIRECT_TEX_TO_PDF}) list(LENGTH ${ADD_DOCUMENT_SOURCES} SOURCE_LEN) if (SOURCE_LEN GREATER 1) MESSAGE(FATAL_ERROR "Target '${target_name}': Only one source can be specified when using the 'DIRECT_TEX_TO_PDF' option") - endif () + endif() # set(ADD_DOCUMENT_SOURCES, list(GET ${ADD_DOCUMENT_SOURCES} 1)) pandocology_get_file_stemname(source_stemname ${ADD_DOCUMENT_SOURCES}) pandocology_get_file_extension(source_extension ${ADD_DOCUMENT_SOURCES}) if (NOT "${source_extension}" STREQUAL ".tex" AND NOT "${source_extension}" STREQUAL ".latex") MESSAGE(FATAL_ERROR "Target '${target_name}': Cannot use 'DIRECT_TEX_TO_PDF' for source of type '${source_extension}': source type must be '.tex' or '.latex'") - endif () + endif() SET(check_target ${source_stemname}.pdf) IF (NOT ${check_target} STREQUAL ${target_name}) MESSAGE(FATAL_ERROR "Target '${target_name}': Must use target name of '${check_target}' if using 'DIRECT_TEX_TO_PDF'") - endif () - endif () + endif() + endif() ## set up output directory if ("${ADD_DOCUMENT_PRODUCT_DIRECTORY}" STREQUAL "") set(ADD_DOCUMENT_PRODUCT_DIRECTORY "product") - endif () + endif() get_filename_component(product_directory ${CMAKE_BINARY_DIR}/${ADD_DOCUMENT_PRODUCT_DIRECTORY} ABSOLUTE) # get_filename_component(absolute_product_path ${product_directory}/${target_name} ABSOLUTE) @@ -232,7 +232,7 @@ function(add_document target_name) pandocology_add_input_dir(${CMAKE_CURRENT_SOURCE_DIR}/${resource_dir} ${CMAKE_CURRENT_BINARY_DIR} build_resources) if (${ADD_DOCUMENT_EXPORT_ARCHIVE}) pandocology_add_input_dir(${CMAKE_CURRENT_SOURCE_DIR}/${resource_dir} ${product_directory} exported_resources) - endif () + endif() endforeach() ## primary command @@ -255,7 +255,7 @@ function(add_document target_name) # we produce the target in the source directory, in case other build targets require it as a source COMMAND latexmk -gg -halt-on-error -interaction=nonstopmode -file-line-error -pdf ${build_sources} 2>/dev/null >/dev/null || (grep --no-messages -A8 ".*:[0-9]*:.*" ${target_stemname}.log && false) ) - endif () + endif() add_to_make_clean(${CMAKE_CURRENT_BINARY_DIR}/${target_name}) else() add_custom_command( @@ -267,7 +267,7 @@ function(add_document target_name) COMMAND ${PANDOC_EXECUTABLE} ${build_sources} ${ADD_DOCUMENT_PANDOC_DIRECTIVES} -o ${target_name} ) add_to_make_clean(${CMAKE_CURRENT_BINARY_DIR}/${target_name}) - endif () + endif() ## figure out what all is going to be produced by this build set, and set ## those as dependencies of the primary target @@ -275,14 +275,14 @@ function(add_document target_name) set(primary_target_dependencies ${primary_target_dependencies} ${CMAKE_CURRENT_BINARY_DIR}/${target_name}) if (NOT ${ADD_DOCUMENT_NO_EXPORT_PRODUCT}) set(primary_target_dependencies ${primary_target_dependencies} ${product_directory}/${target_name}) - endif () + endif() if (${ADD_DOCUMENT_EXPORT_PDF}) set(primary_target_dependencies ${primary_target_dependencies} ${CMAKE_CURRENT_BINARY_DIR}/${target_stemname}.pdf) set(primary_target_dependencies ${primary_target_dependencies} ${product_directory}/${target_stemname}.pdf) - endif () + endif() if (${ADD_DOCUMENT_EXPORT_ARCHIVE}) set(primary_target_dependencies ${primary_target_dependencies} ${product_directory}/${target_stemname}.tbz) - endif () + endif() ## primary target # # target cannot have same (absolute name) as dependencies: @@ -326,7 +326,7 @@ function(add_document target_name) ) add_to_make_clean(${CMAKE_CURRENT_BINARY_DIR}/${target_stemname}.pdf) add_to_make_clean(${product_directory}/${target_stemname}.pdf) - endif () + endif() ## copy products if (NOT ${ADD_DOCUMENT_NO_EXPORT_PRODUCT}) @@ -336,7 +336,7 @@ function(add_document target_name) COMMAND ${CMAKE_COMMAND} -E copy ${target_name} ${product_directory} ) add_to_make_clean(${product_directory}/${target_name}) - endif () + endif() ## copy resources if (${ADD_DOCUMENT_EXPORT_ARCHIVE}) @@ -359,7 +359,7 @@ function(add_document target_name) # ALL # DEPENDS ${product_directory}/${target_stemname}.tbz # ) - endif () + endif() endfunction(add_document) diff --git a/cmake/packaging/cpack_config.cmake b/cmake/packaging/cpack_config.cmake index 57d4803d7..17de607ef 100644 --- a/cmake/packaging/cpack_config.cmake +++ b/cmake/packaging/cpack_config.cmake @@ -101,7 +101,7 @@ elseif (EXISTS "/etc/debian_version" AND NOT EXISTS WIN32) # Package-build is av else () # No package configuration on other platforms ... -endif () +endif() ### diff --git a/doc/man/CMakeLists.txt b/doc/man/CMakeLists.txt index 1b7d6501f..f225c85b7 100644 --- a/doc/man/CMakeLists.txt +++ b/doc/man/CMakeLists.txt @@ -17,7 +17,7 @@ if (${STLINK_GENERATE_MANPAGES}) endforeach () else () message(STATUS "Manpage generation disabled") -endif () +endif() # Install from output folder or this folder foreach (manpage ${MANPAGES}) @@ -27,10 +27,10 @@ foreach (manpage ${MANPAGES}) set(f "${CMAKE_CURRENT_SOURCE_DIR}/${manpage}.1") else() message(AUTHOR_WARNING "Manpage ${manpage} not generated") - endif () + endif() if (f AND NOT WIN32) install(FILES ${f} DESTINATION ${CMAKE_INSTALL_DATADIR}/man/man1) unset(f) - endif () + endif() endforeach () diff --git a/src/st-flash/flash.c b/src/st-flash/flash.c index 711d7d2eb..ba6d1f4bb 100644 --- a/src/st-flash/flash.c +++ b/src/st-flash/flash.c @@ -75,7 +75,7 @@ int32_t main(int32_t ac, char** av) { if (flash_get_opts(&o, ac - 1, av + 1) == -1) { printf("invalid command line\n"); usage(); - return(-1); + return (-1); } printf("st-flash %s\n", STLINK_VERSION); @@ -83,7 +83,7 @@ int32_t main(int32_t ac, char** av) { sl = stlink_open_usb(o.log_level, o.connect, (char *)o.serial, o.freq); - if (sl == NULL) { return(-1); } + if (sl == NULL) { return (-1); } if (sl->flash_type == STM32_FLASH_TYPE_UNKNOWN) { printf("Failed to connect to target\n"); @@ -299,5 +299,5 @@ int32_t main(int32_t ac, char** av) { stlink_close(sl); free(mem); - return(err); + return (err); } diff --git a/src/st-flash/flash_opts.c b/src/st-flash/flash_opts.c index 358074793..300203a3f 100644 --- a/src/st-flash/flash_opts.c +++ b/src/st-flash/flash_opts.c @@ -19,7 +19,7 @@ static bool starts_with(const char * str, const char * prefix) { uint32_t n = strlen(prefix); - if (strlen(str) < n) { return(false); } + if (strlen(str) < n) { return (false); } return (0 == strncmp(str, prefix, n)); } @@ -49,11 +49,11 @@ static int32_t get_long_integer_from_char_array (const char *const str, uint64_t } else if (tail[0] == '\0') { /* value not changed */ } else { - return(-1); + return (-1); } *read_value = value; - return(0); + return (0); } // support positive integer from 0 to UINT32_MAX @@ -65,24 +65,24 @@ static int32_t get_integer_from_char_array (const char *const str, uint32_t *rea int32_t result = get_long_integer_from_char_array (str, &value); if (result != 0) { - return(result); + return (result); } else if (value > UINT32_MAX) { fprintf (stderr, "*** Error: Integer greater than UINT32_MAX, cannot convert to int32_t\n"); - return(-1); + return (-1); } else { *read_value = value; - return(0); + return (0); } } static int32_t invalid_args(const char *expected) { fprintf(stderr, "*** Error: Expected args for this command: %s\n", expected); - return(-1); + return (-1); } static int32_t bad_arg(const char *arg) { fprintf(stderr, "*** Error: Invalid value for %s\n", arg); - return(-1); + return (-1); } int32_t flash_get_opts(struct flash_opts* o, int32_t ac, char** av) { @@ -111,7 +111,7 @@ int32_t flash_get_opts(struct flash_opts* o, int32_t ac, char** av) { ac--; av++; - if (ac < 1) { return(-1); } + if (ac < 1) { return (-1); } serial = av[0]; } else { @@ -127,7 +127,7 @@ int32_t flash_get_opts(struct flash_opts* o, int32_t ac, char** av) { ac--; av++; - if (ac < 1) { return(-1); } + if (ac < 1) { return (-1); } area = av[0]; } else { @@ -149,7 +149,7 @@ int32_t flash_get_opts(struct flash_opts* o, int32_t ac, char** av) { } else if (strcmp(area, "optcr1") == 0) { o->area = FLASH_OPTCR1; } else { - return(-1); + return (-1); } } else if (strcmp(av[0], "--freq") == 0) { @@ -157,17 +157,17 @@ int32_t flash_get_opts(struct flash_opts* o, int32_t ac, char** av) { av++; if (ac < 1) { - return(-1); + return (-1); } o->freq = arg_parse_freq(av[0]); if (o->freq < 0) { - return(-1); + return (-1); } } else if (starts_with(av[0], "--freq=")) { o->freq = arg_parse_freq(av[0] + strlen("--freq=")); if (o->freq < 0) { - return(-1); + return (-1); } } else if (strcmp(av[0], "--format") == 0 || starts_with(av[0], "--format=")) { const char * format; @@ -176,7 +176,7 @@ int32_t flash_get_opts(struct flash_opts* o, int32_t ac, char** av) { ac--; av++; - if (ac < 1) { return(-1); } + if (ac < 1) { return (-1); } format = av[0]; } else { @@ -188,7 +188,7 @@ int32_t flash_get_opts(struct flash_opts* o, int32_t ac, char** av) { } else if (strcmp(format, "ihex") == 0) { o->format = FLASH_FORMAT_IHEX; } else { - return(bad_arg("format")); + return (bad_arg("format")); } } else if ( starts_with(av[0], "--flash=")) { const char *arg = av[0] + strlen("--flash="); @@ -197,7 +197,7 @@ int32_t flash_get_opts(struct flash_opts* o, int32_t ac, char** av) { result = get_integer_from_char_array(arg, &flash_size); if (result != 0) { - return(bad_arg ("--flash")); + return (bad_arg ("--flash")); } else { o->flash_size = (size_t)flash_size; } @@ -217,18 +217,18 @@ int32_t flash_get_opts(struct flash_opts* o, int32_t ac, char** av) { // command and (optional) device name while (ac >= 1) { if (strcmp(av[0], "erase") == 0) { - if (o->cmd != FLASH_CMD_NONE) { return(-1); } + if (o->cmd != FLASH_CMD_NONE) { return (-1); } o->cmd = FLASH_CMD_ERASE; } else if (strcmp(av[0], "read") == 0) { - if (o->cmd != FLASH_CMD_NONE) { return(-1); } + if (o->cmd != FLASH_CMD_NONE) { return (-1); } o->cmd = FLASH_CMD_READ; } else if (strcmp(av[0], "write") == 0) { - if (o->cmd != FLASH_CMD_NONE) { return(-1); } + if (o->cmd != FLASH_CMD_NONE) { return (-1); } o->cmd = FLASH_CMD_WRITE; } else if (strcmp(av[0], "reset") == 0) { - if (o->cmd != FLASH_CMD_NONE) { return(-1); } + if (o->cmd != FLASH_CMD_NONE) { return (-1); } o->cmd = CMD_RESET; } else { @@ -241,10 +241,10 @@ int32_t flash_get_opts(struct flash_opts* o, int32_t ac, char** av) { switch (o->cmd) { case FLASH_CMD_NONE: // no command found - return(-1); + return (-1); case FLASH_CMD_ERASE: // no more arguments expected - if (ac != 0 && ac != 2) { return(-1); } + if (ac != 0 && ac != 2) { return (-1); } if (ac == 2) { uint32_t address; result = get_integer_from_char_array(av[0], &address); @@ -336,7 +336,7 @@ int32_t flash_get_opts(struct flash_opts* o, int32_t ac, char** av) { result = get_integer_from_char_array(av[0], &val); if (result != 0) { - return(bad_arg ("val")); + return (bad_arg ("val")); } else { o->val = val; } @@ -369,16 +369,16 @@ int32_t flash_get_opts(struct flash_opts* o, int32_t ac, char** av) { result = get_integer_from_char_array(av[1], &addr); if (result != 0) { - return(bad_arg ("addr")); + return (bad_arg ("addr")); } else { o->addr = (stm32_addr_t)addr; } } else if (o->format == FLASH_FORMAT_IHEX) { // expect filename - if (ac != 1) { return(invalid_args("write ")); } + if (ac != 1) { return (invalid_args("write ")); } o->filename = av[0]; } else { - return(-1); // should have been caught during format parsing + return (-1); // should have been caught during format parsing } break; @@ -386,5 +386,5 @@ int32_t flash_get_opts(struct flash_opts* o, int32_t ac, char** av) { default: break; } - return(0); + return (0); } diff --git a/src/st-info/info.c b/src/st-info/info.c index 664db7b2a..ffdf521cc 100644 --- a/src/st-info/info.c +++ b/src/st-info/info.c @@ -74,7 +74,7 @@ static int32_t print_data(int32_t ac, char **av) { if (strcmp(av[1], "--version") == 0) { printf("v%s\n", STLINK_VERSION); - return(0); + return (0); } init_chipids(STLINK_CHIPS_DIR); @@ -99,18 +99,18 @@ static int32_t print_data(int32_t ac, char **av) { printf("Incorrect argument: %s\n\n", av[i]); usage(); - return(-1); + return (-1); } // probe needs all devices unclaimed if (strcmp(av[1], "--probe") == 0) { stlink_probe(connect, freq); - return(0); + return (0); } // open first st-link device sl = stlink_open_usb(0, connect, NULL, freq); - if (sl == NULL) { return(-1); } + if (sl == NULL) { return (-1); } if (strcmp(av[1], "--serial") == 0) { printf("%s\n", sl->serial); @@ -124,7 +124,7 @@ static int32_t print_data(int32_t ac, char **av) { printf("0x%.4x\n", sl->chip_id); } else if (strcmp(av[1], "--descr") == 0) { const struct stlink_chipid_params *params = stlink_chipid_get_params(sl->chip_id); - if (params == NULL) { return(-1); } + if (params == NULL) { return (-1); } printf("%s\n", params->dev_type); } @@ -134,7 +134,7 @@ static int32_t print_data(int32_t ac, char **av) { stlink_close(sl); } - return(0); + return (0); } int32_t main(int32_t ac, char** av) { @@ -142,10 +142,10 @@ int32_t main(int32_t ac, char** av) { if (ac < 2) { usage(); - return(-1); + return (-1); } err = print_data(ac, av); - return(err); + return (err); } diff --git a/src/st-util/gdb-remote.c b/src/st-util/gdb-remote.c index 7d0f2c731..25ca4da5b 100644 --- a/src/st-util/gdb-remote.c +++ b/src/st-util/gdb-remote.c @@ -42,19 +42,19 @@ int32_t gdb_send_packet(int32_t fd, char* data) { while (1) { if (write(fd, packet, length) != length) { free(packet); - return(-2); + return (-2); } char ack; if (read(fd, &ack, 1) != 1) { free(packet); - return(-2); + return (-2); } if (ack == '+') { free(packet); - return(0); + return (0); } } } @@ -69,7 +69,7 @@ int32_t gdb_recv_packet(int32_t fd, char** buffer) { uint32_t state; if (packet_buffer == NULL) { - return(-2); + return (-2); } start: @@ -88,7 +88,7 @@ int32_t gdb_recv_packet(int32_t fd, char** buffer) { while (state != 4) { if (read(fd, &c, 1) != 1) { free(packet_buffer); - return(-2); + return (-2); } switch (state) { @@ -117,7 +117,7 @@ int32_t gdb_recv_packet(int32_t fd, char** buffer) { packet_buffer = p; } else { free(packet_buffer); - return(-2); + return (-2); } } } @@ -143,7 +143,7 @@ int32_t gdb_recv_packet(int32_t fd, char** buffer) { if (write(fd, &nack, 1) != 1) { free(packet_buffer); - return(-2); + return (-2); } goto start; @@ -152,14 +152,14 @@ int32_t gdb_recv_packet(int32_t fd, char** buffer) { if (write(fd, &ack, 1) != 1) { free(packet_buffer); - return(-2); + return (-2); } } packet_buffer[packet_idx] = 0; *buffer = packet_buffer; - return(packet_idx); + return (packet_idx); } /* @@ -176,13 +176,13 @@ int32_t gdb_check_for_interrupt(int32_t fd) { char c; if (read(fd, &c, 1) != 1) { - return(-2); + return (-2); } if (c == '\x03') { - return(1); // ^C + return (1); // ^C } } - return(0); + return (0); } diff --git a/src/st-util/gdb-server.c b/src/st-util/gdb-server.c index 9f9d93844..8a187fb24 100644 --- a/src/st-util/gdb-server.c +++ b/src/st-util/gdb-server.c @@ -214,7 +214,7 @@ int32_t parse_options(int32_t argc, char** argv, st_state_t *st) { printf("\n"); } - return(0); + return (0); } int32_t main(int32_t argc, char** argv) { @@ -233,11 +233,11 @@ int32_t main(int32_t argc, char** argv) { init_chipids (STLINK_CHIPS_DIR); sl = stlink_open_usb(state.logging_level, state.connect_mode, state.serialnumber, state.freq); - if (sl == NULL) { return(1); } + if (sl == NULL) { return (1); } if (sl->chip_id == STM32_CHIPID_UNKNOWN) { ELOG("Unsupported Target (Chip ID is %#010x, Core ID is %#010x).\n", sl->chip_id, sl->core_id); - return(1); + return (1); } sl->verbose = 0; @@ -275,7 +275,7 @@ int32_t main(int32_t argc, char** argv) { stlink_exit_debug_mode(sl); stlink_close(sl); - return(0); + return (0); } static const char* const target_description = @@ -608,7 +608,7 @@ char* make_memory_map(stlink_t *sl) { sl->sys_size); } - return(map); + return (map); } #define DATA_WATCH_NUM 4 @@ -676,12 +676,12 @@ static int32_t add_data_watchpoint(stlink_t *sl, enum watchfun wf, stm32_addr_t // just to make sure the matched bit is clear ! stlink_read_debug32(sl, STLINK_REG_CM3_DWT_FUNn(i), &dummy); - return(0); + return (0); } } DLOG("failure: add watchpoints addr %x wf %u len %u\n", addr, wf, len); - return(-1); + return (-1); } static int32_t delete_data_watchpoint(stlink_t *sl, stm32_addr_t addr) { @@ -694,13 +694,13 @@ static int32_t delete_data_watchpoint(stlink_t *sl, stm32_addr_t addr) { data_watches[i].fun = WATCHDISABLED; stlink_write_debug32(sl, STLINK_REG_CM3_DWT_FUNn(i), 0); - return(0); + return (0); } } DLOG("failure: delete watchpoint addr %x\n", addr); - return(-1); + return (-1); } static int32_t code_break_num; @@ -746,9 +746,9 @@ static void init_code_breakpoints(stlink_t *sl) { static int32_t has_breakpoint(stm32_addr_t addr) { for (int32_t i = 0; i < code_break_num; i++) - if (code_breaks[i].addr == addr) { return(1); } + if (code_breaks[i].addr == addr) { return (1); } - return(0); + return (0); } static int32_t update_code_breakpoint(stlink_t *sl, stm32_addr_t addr, int32_t set) { @@ -758,7 +758,7 @@ static int32_t update_code_breakpoint(stlink_t *sl, stm32_addr_t addr, int32_t s if (addr & 1) { ELOG("update_code_breakpoint: unaligned address %08x\n", addr); - return(-1); + return (-1); } if (code_break_rev == CODE_BREAK_REV_V1) { @@ -778,9 +778,9 @@ static int32_t update_code_breakpoint(stlink_t *sl, stm32_addr_t addr, int32_t s if (id == -1) { if (set) - return(-1); // free slot not found + return (-1); // free slot not found else - return(0); // breakpoint is already removed + return (0); // breakpoint is already removed } struct code_hw_breakpoint* bp = &code_breaks[id]; @@ -802,7 +802,7 @@ static int32_t update_code_breakpoint(stlink_t *sl, stm32_addr_t addr, int32_t s stlink_write_debug32(sl, STLINK_REG_CM3_FP_COMPn(id), mask); } - return(0); + return (0); } @@ -820,14 +820,14 @@ static int32_t flash_add_block(stm32_addr_t addr, uint32_t length, stlink_t *sl) if (addr < FLASH_BASE || addr + length > FLASH_BASE + sl->flash_size) { ELOG("flash_add_block: incorrect bounds\n"); - return(-1); + return (-1); } stlink_calculate_pagesize(sl, addr); if (addr % FLASH_PAGE != 0 || length % FLASH_PAGE != 0) { ELOG("flash_add_block: unaligned block\n"); - return(-1); + return (-1); } struct flash_block* new = malloc(sizeof(struct flash_block)); @@ -838,7 +838,7 @@ static int32_t flash_add_block(stm32_addr_t addr, uint32_t length, stlink_t *sl) memset(new->data, stlink_get_erased_pattern(sl), length); flash_root = new; - return(0); + return (0); } static int32_t flash_populate(stm32_addr_t addr, uint8_t* data, uint32_t length) { @@ -871,7 +871,7 @@ static int32_t flash_populate(stm32_addr_t addr, uint8_t* data, uint32_t length) if (fit_blocks == 0) { ELOG("Unfit data block %08x -> %04x\n", addr, length); - return(-1); + return (-1); } if (fit_length != length) { @@ -879,7 +879,7 @@ static int32_t flash_populate(stm32_addr_t addr, uint8_t* data, uint32_t length) WLOG("(this is not an error, just a GDB glitch)\n"); } - return(0); + return (0); } static int32_t flash_go(stlink_t *sl, st_state_t *st) { @@ -935,7 +935,7 @@ static int32_t flash_go(stlink_t *sl, st_state_t *st) { } flash_root = NULL; - return(error); + return (error); } struct cache_level_desc { @@ -967,7 +967,7 @@ static uint32_t ceil_log2(uint32_t v) { for (res = 0; (1U << res) < v; res++); - return(res); + return (res); } static void read_cache_level_desc(stlink_t *sl, struct cache_level_desc *desc) { @@ -1083,12 +1083,12 @@ static uint32_t unhexify(const char *in, char *out, uint32_t out_count) { uint32_t c; for (i = 0; i < out_count; i++) { - if (sscanf(in + (2 * i), "%02x", &c) != 1) { return(i); } + if (sscanf(in + (2 * i), "%02x", &c) != 1) { return (i); } out[i] = (char)c; } - return(i); + return (i); } int32_t serve(stlink_t *sl, st_state_t *st) { @@ -1096,7 +1096,7 @@ int32_t serve(stlink_t *sl, st_state_t *st) { if (!IS_SOCK_VALID(sock)) { perror("socket"); - return(1); + return (1); } uint32_t val = 1; @@ -1111,13 +1111,13 @@ int32_t serve(stlink_t *sl, st_state_t *st) { if (bind(sock, (struct sockaddr *)&serv_addr, sizeof(serv_addr)) < 0) { perror("bind"); close_socket(sock); - return(1); + return (1); } if (listen(sock, 5) < 0) { perror("listen"); close_socket(sock); - return(1); + return (1); } ILOG("Listening at *:%d...\n", st->listen_port); @@ -1128,7 +1128,7 @@ int32_t serve(stlink_t *sl, st_state_t *st) { if (!IS_SOCK_VALID(client)) { perror("accept"); close_socket(sock); - return(1); + return (1); } close_socket(sock); @@ -1169,7 +1169,7 @@ int32_t serve(stlink_t *sl, st_state_t *st) { if (status < 0) { ELOG("cannot recv: %d\n", status); close_socket(client); - return(1); + return (1); } DLOG("recv: %s\n", packet); @@ -1447,7 +1447,7 @@ int32_t serve(stlink_t *sl, st_state_t *st) { if (status < 0) { ELOG("cannot check for int: %d\n", status); close_socket(client); - return(1); + return (1); } if (status == 1) { @@ -1884,7 +1884,7 @@ int32_t serve(stlink_t *sl, st_state_t *st) { free(reply); free(packet); close_socket(client); - return(1); + return (1); } free(reply); @@ -1892,12 +1892,12 @@ int32_t serve(stlink_t *sl, st_state_t *st) { if (critical_error) { close_socket(client); - return(1); + return (1); } free(packet); } close_socket(client); - return(0); + return (0); } diff --git a/src/st-util/semihosting.c b/src/st-util/semihosting.c index 93a6cf7cc..a200a7408 100644 --- a/src/st-util/semihosting.c +++ b/src/st-util/semihosting.c @@ -16,13 +16,13 @@ static int32_t mem_read_u8(stlink_t *sl, uint32_t addr, uint8_t *data) { int32_t offset = addr % 4; int32_t len = 4; - if (sl == NULL || data == NULL) { return(-1); } + if (sl == NULL || data == NULL) { return (-1); } // read address and length must be aligned - if (stlink_read_mem32(sl, addr - offset, len) != 0) { return(-1); } + if (stlink_read_mem32(sl, addr - offset, len) != 0) { return (-1); } *data = sl->q_buf[offset]; - return(0); + return (0); } #ifdef UNUSED @@ -30,26 +30,26 @@ static int32_t mem_read_u16(stlink_t *sl, uint32_t addr, uint16_t *data) { int32_t offset = addr % 4; int32_t len = (offset > 2 ? 8 : 4); - if (sl == NULL || data == NULL) { return(-1); } + if (sl == NULL || data == NULL) { return (-1); } // read address and length must be aligned - if (stlink_read_mem32(sl, addr - offset, len) != 0) { return(-1); } + if (stlink_read_mem32(sl, addr - offset, len) != 0) { return (-1); } memcpy(data, &sl->q_buf[offset], sizeof(*data)); - return(0); + return (0); } static int32_t mem_read_u32(stlink_t *sl, uint32_t addr, uint32_t *data) { int32_t offset = addr % 4; int32_t len = (offset > 0 ? 8 : 4); - if (sl == NULL || data == NULL) { return(-1); } + if (sl == NULL || data == NULL) { return (-1); } // read address and length must be aligned - if (stlink_read_mem32(sl, addr - offset, len) != 0) { return(-1); } + if (stlink_read_mem32(sl, addr - offset, len) != 0) { return (-1); } memcpy(data, &sl->q_buf[offset], sizeof(*data)); - return(0); + return (0); } #endif @@ -57,16 +57,16 @@ static int32_t mem_read(stlink_t *sl, uint32_t addr, void *data, uint16_t len) { int32_t offset = addr % 4; int32_t read_len = len + offset; - if (sl == NULL || data == NULL) { return(-1); } + if (sl == NULL || data == NULL) { return (-1); } // align read size if ((read_len % 4) != 0) { read_len += 4 - (read_len % 4); } // address and length must be aligned - if (stlink_read_mem32(sl, addr - offset, read_len) != 0) { return(-1); } + if (stlink_read_mem32(sl, addr - offset, read_len) != 0) { return (-1); } memcpy(data, &sl->q_buf[offset], len); - return(0); + return (0); } static int32_t mem_write(stlink_t *sl, uint32_t addr, void *data, uint16_t len) { @@ -77,12 +77,12 @@ static int32_t mem_write(stlink_t *sl, uint32_t addr, void *data, uint16_t len) * the requested bytes. (perhaps reading the whole area is faster??). * If 16 and 8 bit writes are available, then they could be used instead. * Just return when the length is zero avoiding unneeded work. */ - if (len == 0) { return(0); } + if (len == 0) { return (0); } int32_t offset = addr % 4; int32_t write_len = len + offset; - if (sl == NULL || data == NULL) { return(-1); } + if (sl == NULL || data == NULL) { return (-1); } // align read size if ((write_len % 4) != 0) { write_len += 4 - (write_len % 4); } @@ -90,9 +90,9 @@ static int32_t mem_write(stlink_t *sl, uint32_t addr, void *data, uint16_t len) memcpy(&sl->q_buf[offset], data, len); // address and length must be aligned - if (stlink_write_mem32(sl, addr - offset, write_len) != 0) { return(-1); } + if (stlink_write_mem32(sl, addr - offset, write_len) != 0) { return (-1); } - return(0); + return (0); } /* For the SYS_WRITE0 call, we don't know the size of the null-terminated buffer @@ -132,7 +132,7 @@ static int32_t saved_errno = 0; int32_t do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { - if (sl == NULL || ret == NULL) { return(-1); } + if (sl == NULL || ret == NULL) { return (-1); } DLOG("Do semihosting R0=0x%08x R1=0x%08x\n", r0, r1); @@ -148,7 +148,7 @@ int32_t do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { if (mem_read(sl, r1, args, sizeof(args)) != 0) { DLOG("Semihosting SYS_OPEN error: cannot read args from target memory\n"); *ret = -1; - return(-1); + return (-1); } name_address = args[0]; @@ -159,7 +159,7 @@ int32_t do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { /* Invalid mode */ DLOG("Semihosting SYS_OPEN error: invalid mode %d\n", mode); *ret = -1; - return(-1); + return (-1); } /* Add the trailing zero that is not counted in the length argument (see @@ -170,7 +170,7 @@ int32_t do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { if (name_len > MAX_BUFFER_SIZE) { DLOG("Semihosting SYS_OPEN error: name buffer size is too big %d\n", name_len); *ret = -1; - return(-1); + return (-1); } name = malloc(name_len); @@ -178,14 +178,14 @@ int32_t do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { if (name == NULL) { DLOG("Semihosting SYS_OPEN error: cannot allocate name buffer\n"); *ret = -1; - return(-1); + return (-1); } if (mem_read(sl, name_address, name, name_len) != 0) { free(name); *ret = -1; DLOG("Semihosting SYS_OPEN error: cannot read name from target memory\n"); - return(-1); + return (-1); } DLOG("Semihosting: open('%s', (SH open mode)%d, 0644)\n", name, mode); @@ -206,7 +206,7 @@ int32_t do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { if (mem_read(sl, r1, args, sizeof(args)) != 0) { DLOG("Semihosting SYS_CLOSE error: cannot read args from target memory\n"); *ret = -1; - return(-1); + return (-1); } fd = (int32_t)args[0]; @@ -230,7 +230,7 @@ int32_t do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { if (mem_read(sl, r1, args, sizeof(args)) != 0) { DLOG("Semihosting SYS_WRITE error: cannot read args from target memory\n"); *ret = -1; - return(-1); + return (-1); } fd = (int32_t)args[0]; @@ -241,7 +241,7 @@ int32_t do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { DLOG("Semihosting SYS_WRITE error: buffer size is too big %d\n", buffer_len); *ret = buffer_len; - return(-1); + return (-1); } buffer = malloc(buffer_len); @@ -249,14 +249,14 @@ int32_t do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { if (buffer == NULL) { DLOG("Semihosting SYS_WRITE error: cannot allocate buffer\n"); *ret = buffer_len; - return(-1); + return (-1); } if (mem_read(sl, buffer_address, buffer, buffer_len) != 0) { DLOG("Semihosting SYS_WRITE error: cannot read buffer from target memory\n"); free(buffer); *ret = buffer_len; - return(-1); + return (-1); } DLOG("Semihosting: write(%d, target_addr:0x%08x, %u)\n", fd, buffer_address, buffer_len); @@ -286,7 +286,7 @@ int32_t do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { if (mem_read(sl, r1, args, sizeof(args)) != 0) { DLOG("Semihosting SYS_READ error: cannot read args from target memory\n"); *ret = -1; - return(-1); + return (-1); } fd = (int32_t)args[0]; @@ -296,7 +296,7 @@ int32_t do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { if (buffer_len > MAX_BUFFER_SIZE) { DLOG("Semihosting SYS_READ error: buffer size is too big %d\n", buffer_len); *ret = buffer_len; - return(-1); + return (-1); } buffer = malloc(buffer_len); @@ -304,7 +304,7 @@ int32_t do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { if (buffer == NULL) { DLOG("Semihosting SYS_READ error: cannot allocatebuffer\n"); *ret = buffer_len; - return(-1); + return (-1); } DLOG("Semihosting: read(%d, target_addr:0x%08x, %u)\n", fd, buffer_address, @@ -320,7 +320,7 @@ int32_t do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { DLOG("Semihosting SYS_READ error: cannot write buffer to target memory\n"); free(buffer); *ret = buffer_len; - return(-1); + return (-1); } else { *ret = buffer_len - (uint32_t)read_result; } @@ -346,7 +346,7 @@ int32_t do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { if (mem_read(sl, r1, args, sizeof(args)) != 0) { DLOG("Semihosting SYS_REMOVE error: cannot read args from target memory\n"); *ret = -1; - return(-1); + return (-1); } name_address = args[0]; @@ -361,7 +361,7 @@ int32_t do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { DLOG("Semihosting SYS_REMOVE error: name buffer size is too big %d\n", name_len); *ret = -1; - return(-1); + return (-1); } name = malloc(name_len); @@ -369,14 +369,14 @@ int32_t do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { if (name == NULL) { DLOG("Semihosting SYS_REMOVE error: cannot allocate name buffer\n"); *ret = -1; - return(-1); + return (-1); } if (mem_read(sl, name_address, name, name_len) != 0) { free(name); *ret = -1; DLOG("Semihosting SYS_REMOVE error: cannot read name from target memory\n"); - return(-1); + return (-1); } DLOG("Semihosting: unlink('%s')\n", name); @@ -395,7 +395,7 @@ int32_t do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { if (mem_read(sl, r1, args, sizeof(args)) != 0) { DLOG("Semihosting SYS_SEEK error: cannot read args from target memory\n"); *ret = -1; - return(-1); + return (-1); } fd = (int32_t)args[0]; @@ -435,11 +435,11 @@ int32_t do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { while (true) { if (mem_read(sl, r1, buf, WRITE0_BUFFER_SIZE) != 0) { DLOG("Semihosting WRITE0: cannot read target memory at 0x%08x\n", r1); - return(-1); + return (-1); } for (int32_t i = 0; i < WRITE0_BUFFER_SIZE; i++) { - if (buf[i] == 0) { return(0); } + if (buf[i] == 0) { return (0); } fprintf(stderr, "%c", buf[i]); } @@ -451,7 +451,7 @@ int32_t do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { } default: fprintf(stderr, "semihosting: unsupported call %#x\n", r0); - return(-1); + return (-1); } - return(0); + return (0); } diff --git a/src/stlink-gui/CMakeLists.txt b/src/stlink-gui/CMakeLists.txt index fb4478bdc..bbfcc20a3 100644 --- a/src/stlink-gui/CMakeLists.txt +++ b/src/stlink-gui/CMakeLists.txt @@ -31,5 +31,5 @@ if (NOT WIN32 AND NOT CMAKE_CROSSCOMPILING) COMPILE_DEFINITIONS STLINK_UI_DIR="${CMAKE_INSTALL_SHAREDIR}/${PROJECT_NAME}") target_link_libraries(stlink-gui ${STLINK_LIB_SHARED} ${SSP_LIB} ${GTK3_LDFLAGS}) install(TARGETS stlink-gui DESTINATION ${CMAKE_BINDIR}) - endif () -endif () + endif() +endif() diff --git a/src/stlink-gui/gui.c b/src/stlink-gui/gui.c index 5853e5ec4..4b312c8a1 100644 --- a/src/stlink-gui/gui.c +++ b/src/stlink-gui/gui.c @@ -63,7 +63,7 @@ static gboolean set_info_error_message_idle(STlinkGUI *gui) { gui->error_message = NULL; } - return(FALSE); + return (FALSE); } static void stlink_gui_set_info_error_message(STlinkGUI *gui, const gchar *message) { @@ -156,15 +156,15 @@ static guint32 hexstr_to_guint32(const gchar *str, GError **err) { if ((errno == ERANGE && val == UINT_MAX) || (errno != 0 && val == 0)) { g_set_error(err, g_quark_from_string("hextou32"), 1, "Invalid hexstring"); - return(UINT32_MAX); + return (UINT32_MAX); } if (end_ptr == str) { g_set_error(err, g_quark_from_string("hextou32"), 2, "Invalid hexstring"); - return(UINT32_MAX); + return (UINT32_MAX); } - return(val); + return (val); } static void stlink_gui_update_mem_view(STlinkGUI *gui, struct mem_t *mem, GtkTreeView *view) { @@ -182,7 +182,7 @@ static void stlink_gui_update_mem_view(STlinkGUI *gui, struct mem_t *mem, GtkTre static gboolean stlink_gui_update_devmem_view(STlinkGUI *gui) { stlink_gui_update_mem_view(gui, &gui->flash_mem, gui->devmem_treeview); - return(FALSE); + return (FALSE); } static gpointer stlink_gui_populate_devmem_view(gpointer data) { @@ -220,7 +220,7 @@ static gpointer stlink_gui_populate_devmem_view(gpointer data) { stlink_gui_set_info_error_message(gui, "Failed to read memory"); g_free(gui->flash_mem.memory); gui->flash_mem.memory = NULL; - return(NULL); + return (NULL); } memcpy(gui->flash_mem.memory + off, gui->sl->q_buf, n_read); @@ -228,7 +228,7 @@ static gpointer stlink_gui_populate_devmem_view(gpointer data) { } g_idle_add((GSourceFunc)stlink_gui_update_devmem_view, gui); - return(NULL); + return (NULL); } static gboolean stlink_gui_update_filemem_view(STlinkGUI *gui) { @@ -240,7 +240,7 @@ static gboolean stlink_gui_update_filemem_view(STlinkGUI *gui) { g_free(basename); stlink_gui_update_mem_view(gui, &gui->file_mem, gui->filemem_treeview); - return(FALSE); + return (FALSE); } static gpointer stlink_gui_populate_filemem_view(gpointer data) { @@ -338,7 +338,7 @@ out: g_object_unref(file); } g_idle_add((GSourceFunc)stlink_gui_update_filemem_view, gui); - return(NULL); + return (NULL); } static void mem_jmp(GtkTreeView *view, @@ -438,13 +438,13 @@ static gchar *dev_format_chip_id(guint32 chip_id) { params = stlink_chipid_get_params(chip_id); - if (!params) { return(g_strdup_printf("0x%x", chip_id)); } + if (!params) { return (g_strdup_printf("0x%x", chip_id)); } - return(g_strdup(params->dev_type)); + return (g_strdup(params->dev_type)); } static gchar *dev_format_mem_size(gsize flash_size) { - return(g_strdup_printf("%u kB", (uint32_t)(flash_size / 1024))); + return (g_strdup_printf("%u kB", (uint32_t)(flash_size / 1024))); } @@ -585,7 +585,7 @@ static gboolean stlink_gui_write_flash_update(STlinkGUI *gui) { stlink_gui_set_sensitivity(gui, TRUE); gui->progress.activity_mode = FALSE; gtk_widget_hide(GTK_WIDGET(gui->progress.bar)); - return(FALSE); + return (FALSE); } static gpointer stlink_gui_write_flash(gpointer data) { @@ -601,7 +601,7 @@ static gpointer stlink_gui_write_flash(gpointer data) { } g_idle_add((GSourceFunc)stlink_gui_write_flash_update, gui); - return(NULL); + return (NULL); } static void flash_button_cb(GtkWidget *widget, gpointer data) { @@ -648,13 +648,13 @@ int32_t export_to_file(const char*filename, const struct mem_t flash_mem) { printf("%s\n", filename); FILE * f = fopen(filename, "w"); - if (f == NULL) { return(-1); } + if (f == NULL) { return (-1); } for (gsize i = 0; i < flash_mem.size; i++) - if (fputc(flash_mem.memory[i], f) == EOF) { return(-1); } + if (fputc(flash_mem.memory[i], f) == EOF) { return (-1); } fclose(f); - return(0); + return (0); } static void export_button_cb(GtkWidget *widget, gpointer data) { @@ -697,7 +697,7 @@ static gboolean progress_pulse_timeout(STlinkGUI *gui) { gtk_progress_bar_set_fraction(gui->progress.bar, gui->progress.fraction); } - return(TRUE); + return (TRUE); } static void notebook_switch_page_cb(GtkNotebook *notebook, @@ -901,5 +901,5 @@ int32_t main(int32_t argc, char **argv) { stlink_gui_init_dnd(gui); gtk_main(); - return(0); + return (0); } diff --git a/src/stlink-lib/flash_loader.c b/src/stlink-lib/flash_loader.c index 0ab8cf6c1..0f12c3131 100644 --- a/src/stlink-lib/flash_loader.c +++ b/src/stlink-lib/flash_loader.c @@ -177,7 +177,7 @@ int32_t stlink_flash_loader_init(stlink_t *sl, flash_loader_t *fl) { // allocate the loader in SRAM if (stlink_flash_loader_write_to_sram(sl, &fl->loader_addr, &size) == -1) { WLOG("Failed to write flash loader to sram!\n"); - return(-1); + return (-1); } // allocate a one page buffer in SRAM right after loader @@ -205,7 +205,7 @@ int32_t stlink_flash_loader_init(stlink_t *sl, flash_loader_t *fl) { stlink_write_debug32(sl, STLINK_REG_HFSR, hfsr); } - return(0); + return (0); } static int32_t loader_v_dependent_assignment(stlink_t *sl, @@ -235,7 +235,7 @@ static int32_t loader_v_dependent_assignment(stlink_t *sl, } } - return(retval); + return (retval); } int32_t stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, uint32_t* size) { @@ -285,7 +285,7 @@ int32_t stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, uint loader_code_stm32f4, sizeof(loader_code_stm32f4), loader_code_stm32f4_lv, sizeof(loader_code_stm32f4_lv)); - if (retval == -1) { return(retval); } + if (retval == -1) { return (retval); } } else if (sl->core_id == STM32_CORE_ID_M7F_SWD || sl->chip_id == STM32_CHIPID_F7 || sl->chip_id == STM32_CHIPID_F76xxx || @@ -296,7 +296,7 @@ int32_t stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, uint loader_code_stm32f7, sizeof(loader_code_stm32f7), loader_code_stm32f7_lv, sizeof(loader_code_stm32f7_lv)); - if (retval == -1) { return(retval); } + if (retval == -1) { return (retval); } } else if (sl->chip_id == STM32_CHIPID_F0 || sl->chip_id == STM32_CHIPID_F04 || sl->chip_id == STM32_CHIPID_F0_CAN || @@ -315,18 +315,18 @@ int32_t stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, uint } else { ELOG("unknown coreid, not sure what flash loader to use, aborting! coreid: %x, chipid: %x\n", sl->core_id, sl->chip_id); - return(-1); + return (-1); } memcpy(sl->q_buf, loader_code, loader_size); int32_t ret = stlink_write_mem32(sl, sl->sram_base, (uint16_t)loader_size); - if (ret) { return(ret); } + if (ret) { return (ret); } *addr = sl->sram_base; *size = loader_size; - return(0); // success + return (0); // success } int32_t stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, const uint8_t* buf, uint32_t size) { @@ -339,7 +339,7 @@ int32_t stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t t if (write_buffer_to_sram(sl, fl, buf, size) == -1) { ELOG("write_buffer_to_sram() == -1\n"); - return(-1); + return (-1); } if ((sl->flash_type == STM32_FLASH_TYPE_F1_XL) && (target >= FLASH_BANK2_START_ADDR)) { @@ -404,7 +404,7 @@ int32_t stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t t goto error; } - return(0); + return (0); error: dhcsr = dfsr = cfsr = hfsr = 0; @@ -419,7 +419,7 @@ int32_t stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t t WLOG("MCU state: DHCSR 0x%X DFSR 0x%X CFSR 0x%X HFSR 0x%X\n", dhcsr, dfsr, cfsr, hfsr); } - return(-1); + return (-1); } @@ -868,8 +868,7 @@ int32_t stlink_flashloader_stop(stlink_t *sl, flash_loader_t *fl) { (sl->flash_type == STM32_FLASH_TYPE_WB_WL)) { clear_flash_cr_pg(sl, BANK_1); - if ((sl->flash_type == STM32_FLASH_TYPE_H7 && - sl->chip_flags & CHIP_F_HAS_DUAL_BANK) || + if ((sl->flash_type == STM32_FLASH_TYPE_H7 && sl->chip_flags & CHIP_F_HAS_DUAL_BANK) || sl->flash_type == STM32_FLASH_TYPE_F1_XL) { clear_flash_cr_pg(sl, BANK_2); } @@ -886,9 +885,8 @@ int32_t stlink_flashloader_stop(stlink_t *sl, flash_loader_t *fl) { // enable interrupt if (!stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr)) { - stlink_write_debug32(sl, STLINK_REG_DHCSR, - STLINK_REG_DHCSR_DBGKEY | STLINK_REG_DHCSR_C_DEBUGEN | - (dhcsr & (~STLINK_REG_DHCSR_C_MASKINTS))); + stlink_write_debug32(sl, STLINK_REG_DHCSR, STLINK_REG_DHCSR_DBGKEY | STLINK_REG_DHCSR_C_DEBUGEN | + (dhcsr & (~STLINK_REG_DHCSR_C_MASKINTS))); } // restore DMA state diff --git a/src/stlink-lib/lib_md5.c b/src/stlink-lib/lib_md5.c index 71703273c..62e77252e 100644 --- a/src/stlink-lib/lib_md5.c +++ b/src/stlink-lib/lib_md5.c @@ -152,7 +152,7 @@ static void* TransformFunction(Md5Context* ctx, void const* data, uintmax_t size #undef GET #undef SET - return(ptr); + return (ptr); } /* EXPORTED FUNCTIONS */ diff --git a/src/stlink-lib/sg.c b/src/stlink-lib/sg.c index d7f844b51..b744389ba 100644 --- a/src/stlink-lib/sg.c +++ b/src/stlink-lib/sg.c @@ -141,12 +141,12 @@ static int32_t get_usb_mass_storage_status(libusb_device_handle *handle, uint8_t if (ret != LIBUSB_SUCCESS) { WLOG("%s: receiving failed: %d\n", __func__, ret); - return(-1); + return (-1); } if (transferred != sizeof(csw)) { WLOG("%s: received unexpected amount: %d\n", __func__, transferred); - return(-1); + return (-1); } uint32_t rsig = read_uint32(csw, 0); @@ -157,12 +157,12 @@ static int32_t get_usb_mass_storage_status(libusb_device_handle *handle, uint8_t if (rsig != USB_CSW_SIGNATURE) { WLOG("status signature was invalid: %#x\n", rsig); - return(-1); + return (-1); } *tag = rtag; uint8_t rstatus = csw[12]; - return(rstatus); + return (rstatus); } static int32_t dump_CDB_command(uint8_t *cdb, uint8_t cdb_len) { @@ -176,7 +176,7 @@ static int32_t dump_CDB_command(uint8_t *cdb, uint8_t cdb_len) { sprintf(dbugp, "]\n"); DLOG("%s",dbugblah); - return(0); + return (0); } /** @@ -239,10 +239,10 @@ int32_t send_usb_mass_storage_command(libusb_device_handle *handle, uint8_t endp if (ret != LIBUSB_SUCCESS) { WLOG("sending failed: %d\n", ret); - return(-1); + return (-1); } - return(this_tag); + return (this_tag); } /** @@ -332,7 +332,7 @@ int32_t send_usb_data_only(libusb_device_handle *handle, unsigned char endpoint_ if (ret != LIBUSB_SUCCESS) { WLOG("sending failed: %d\n", ret); - return(-1); + return (-1); } // now, swallow up the status, so that things behave nicely... @@ -342,7 +342,7 @@ int32_t send_usb_data_only(libusb_device_handle *handle, unsigned char endpoint_ if (status < 0) { WLOG("receiving status failed: %d\n", status); - return(-1); + return (-1); } if (status != 0) { @@ -351,10 +351,10 @@ int32_t send_usb_data_only(libusb_device_handle *handle, unsigned char endpoint_ if (status == 1) { get_sense(handle, endpoint_in, endpoint_out); - return(-1); + return (-1); } - return(real_transferred); + return (real_transferred); } int32_t stlink_q(stlink_t *sl) { @@ -386,7 +386,7 @@ int32_t stlink_q(stlink_t *sl) { if (ret != LIBUSB_SUCCESS) { WLOG("Receiving failed: %d\n", ret); - return(-1); + return (-1); } if (real_transferred != rx_length) { @@ -400,7 +400,7 @@ int32_t stlink_q(stlink_t *sl) { if (status < 0) { WLOG("receiving status failed: %d\n", status); - return(-1); + return (-1); } if (status != 0) { @@ -409,7 +409,7 @@ int32_t stlink_q(stlink_t *sl) { if (status == 1) { get_sense(sg->usb_handle, sg->ep_rep, sg->ep_req); - return(-1); + return (-1); } if (received_tag != tag) { @@ -418,10 +418,10 @@ int32_t stlink_q(stlink_t *sl) { } if (rx_length > 0 && real_transferred != rx_length) { - return(-1); + return (-1); } - return(0); + return (0); } // TODO: thinking, cleanup @@ -448,7 +448,7 @@ int32_t _stlink_sg_version(stlink_t *stl) { sl->cdb_cmd_blk[0] = STLINK_GET_VERSION; stl->q_len = 6; sl->q_addr = 0; - return(stlink_q(stl)); + return (stlink_q(stl)); } // Get stlink mode: @@ -461,9 +461,9 @@ int32_t _stlink_sg_current_mode(stlink_t *stl) { stl->q_len = 2; sl->q_addr = 0; - if (stlink_q(stl)) { return(-1); } + if (stlink_q(stl)) { return (-1); } - return(stl->q_buf[0]); + return (stl->q_buf[0]); } // exit the mass mode and enter the swd debug mode. @@ -473,7 +473,7 @@ int32_t _stlink_sg_enter_swd_mode(stlink_t *sl) { sg->cdb_cmd_blk[1] = STLINK_DEBUG_APIV1_ENTER; sg->cdb_cmd_blk[2] = STLINK_DEBUG_ENTER_SWD; sl->q_len = 0; // >0 -> aboard - return(stlink_q(sl)); + return (stlink_q(sl)); } // exit the mass mode and enter the jtag debug mode. @@ -485,7 +485,7 @@ int32_t _stlink_sg_enter_jtag_mode(stlink_t *sl) { sg->cdb_cmd_blk[1] = STLINK_DEBUG_APIV1_ENTER; sg->cdb_cmd_blk[2] = STLINK_DEBUG_ENTER_JTAG_RESET; sl->q_len = 0; - return(stlink_q(sl)); + return (stlink_q(sl)); } // XXX kernel driver performs reset, the device temporally disappears @@ -497,7 +497,7 @@ int32_t _stlink_sg_exit_dfu_mode(stlink_t *sl) { sg->cdb_cmd_blk[0] = STLINK_DFU_COMMAND; sg->cdb_cmd_blk[1] = STLINK_DFU_EXIT; sl->q_len = 0; // ?? - return(stlink_q(sl)); + return (stlink_q(sl)); /* [135121.844564] sd 19:0:0:0: [sdb] Unhandled error code [135121.844569] sd 19:0:0:0: [sdb] Result: hostbyte=DID_ERROR driverbyte=DRIVER_OK @@ -552,10 +552,10 @@ int32_t _stlink_sg_core_id(stlink_t *sl) { sg->q_addr = 0; ret = stlink_q(sl); - if (ret) { return(ret); } + if (ret) { return (ret); } sl->core_id = read_uint32(sl->q_buf, 0); - return(0); + return (0); } // arm-core reset -> halted state. @@ -566,17 +566,17 @@ int32_t _stlink_sg_reset(stlink_t *sl) { sl->q_len = 2; sg->q_addr = 0; - if (stlink_q(sl)) { return(-1); } + if (stlink_q(sl)) { return (-1); } // Reset through AIRCR so NRST does not need to be connected if (stlink_write_debug32(sl, STLINK_REG_AIRCR, STLINK_REG_AIRCR_VECTKEY | \ STLINK_REG_AIRCR_SYSRESETREQ)) { - return(-1); + return (-1); } stlink_stat(sl, "core reset"); - return(0); + return (0); } // arm-core reset -> halted state. @@ -588,11 +588,11 @@ int32_t _stlink_sg_jtag_reset(stlink_t *sl, int32_t value) { sl->q_len = 3; sg->q_addr = 2; - if (stlink_q(sl)) { return(-1); } + if (stlink_q(sl)) { return (-1); } stlink_stat(sl, "core reset"); - return(0); + return (0); } // arm-core status: halted or running. @@ -602,7 +602,7 @@ int32_t _stlink_sg_status(stlink_t *sl) { sg->cdb_cmd_blk[1] = STLINK_DEBUG_GETSTATUS; sl->q_len = 2; sg->q_addr = 0; - return(stlink_q(sl)); + return (stlink_q(sl)); } // force the core into the debug mode -> halted state. @@ -613,10 +613,10 @@ int32_t _stlink_sg_force_debug(stlink_t *sl) { sl->q_len = 2; sg->q_addr = 0; - if (stlink_q(sl)) { return(-1); } + if (stlink_q(sl)) { return (-1); } stlink_stat(sl, "force debug"); - return(0); + return (0); } // read all arm-core registers. @@ -628,7 +628,7 @@ int32_t _stlink_sg_read_all_regs(stlink_t *sl, struct stlink_reg *regp) { sl->q_len = 84; sg->q_addr = 0; - if (stlink_q(sl)) { return(-1); } + if (stlink_q(sl)) { return (-1); } stlink_print_data(sl); @@ -648,7 +648,7 @@ int32_t _stlink_sg_read_all_regs(stlink_t *sl, struct stlink_reg *regp) { regp->rw = read_uint32(sl->q_buf, 76); regp->rw2 = read_uint32(sl->q_buf, 80); - if (sl->verbose < 2) { return(0); } + if (sl->verbose < 2) { return (0); } DLOG("xpsr = 0x%08x\n", regp->xpsr); DLOG("main_sp = 0x%08x\n", regp->main_sp); @@ -656,7 +656,7 @@ int32_t _stlink_sg_read_all_regs(stlink_t *sl, struct stlink_reg *regp) { DLOG("rw = 0x%08x\n", regp->rw); DLOG("rw2 = 0x%08x\n", regp->rw2); - return(0); + return (0); } // read an arm-core register, the index must be in the range 0..20. @@ -671,7 +671,7 @@ int32_t _stlink_sg_read_reg(stlink_t *sl, int32_t r_idx, struct stlink_reg *regp sl->q_len = 4; sg->q_addr = 0; - if (stlink_q(sl)) { return(-1); } + if (stlink_q(sl)) { return (-1); } // 0 | 1 | ... | 15 | 16 | 17 | 18 | 19 | 20 // 0-3 | 4-7 | ... | 60-63 | 64-67 | 68-71 | 72-75 | 76-79 | 80-83 @@ -701,7 +701,7 @@ int32_t _stlink_sg_read_reg(stlink_t *sl, int32_t r_idx, struct stlink_reg *regp regp->r[r_idx] = r; } - return(0); + return (0); } // write an arm-core register. Index: @@ -719,10 +719,10 @@ int32_t _stlink_sg_write_reg(stlink_t *sl, uint32_t reg, int32_t idx) { sl->q_len = 2; sg->q_addr = 0; - if (stlink_q(sl)) { return(-1); } + if (stlink_q(sl)) { return (-1); } stlink_stat(sl, "write reg"); - return(0); + return (0); } // write a register of the debug module of the core. @@ -752,11 +752,11 @@ int32_t _stlink_sg_run(stlink_t *sl, enum run_type type) { sl->q_len = 2; sg->q_addr = 0; - if (stlink_q(sl)) { return(-1); } + if (stlink_q(sl)) { return (-1); } stlink_stat(sl, "run core"); - return(0); + return (0); } // step the arm-core. @@ -767,10 +767,10 @@ int32_t _stlink_sg_step(stlink_t *sl) { sl->q_len = 2; sg->q_addr = 0; - if (stlink_q(sl)) { return(-1); } + if (stlink_q(sl)) { return (-1); } stlink_stat(sl, "step core"); - return(0); + return (0); } // TODO: test and make delegate! @@ -823,10 +823,10 @@ int32_t _stlink_sg_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { sl->q_len = len; sg->q_addr = addr; - if (stlink_q(sl)) { return(-1); } + if (stlink_q(sl)) { return (-1); } stlink_print_data(sl); - return(0); + return (0); } // write a "len" bytes from the sl->q_buf to the memory, max 64 Bytes. @@ -845,16 +845,16 @@ int32_t _stlink_sg_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len) { ret = send_usb_mass_storage_command(sg->usb_handle, sg->ep_req, sg->cdb_cmd_blk, CDB_SL, 0, 0, 0); - if (ret == -1) { return(ret); } + if (ret == -1) { return (ret); } // This sends the data... ret = send_usb_data_only(sg->usb_handle, sg->ep_req, sg->ep_rep, sl->q_buf, len); - if (ret == -1) { return(ret); } + if (ret == -1) { return (ret); } stlink_print_data(sl); - return(0); + return (0); } // write a "len" bytes from the sl->q_buf to the memory, max Q_BUF_LEN bytes. @@ -873,16 +873,16 @@ int32_t _stlink_sg_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { ret = send_usb_mass_storage_command(sg->usb_handle, sg->ep_req, sg->cdb_cmd_blk, CDB_SL, 0, 0, 0); - if (ret == -1) { return(ret); } + if (ret == -1) { return (ret); } // This sends the data... ret = send_usb_data_only(sg->usb_handle, sg->ep_req, sg->ep_rep, sl->q_buf, len); - if (ret == -1) { return(ret); } + if (ret == -1) { return (ret); } stlink_print_data(sl); - return(0); + return (0); } // write one DWORD data to memory @@ -894,7 +894,7 @@ int32_t _stlink_sg_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data) { write_uint32(sg->cdb_cmd_blk + 2, addr); write_uint32(sg->cdb_cmd_blk + 6, data); sl->q_len = 2; - return(stlink_q(sl)); + return (stlink_q(sl)); } // read one DWORD data from memory @@ -906,10 +906,10 @@ int32_t _stlink_sg_read_debug32(stlink_t *sl, uint32_t addr, uint32_t *data) { write_uint32(sg->cdb_cmd_blk + 2, addr); sl->q_len = 8; - if (stlink_q(sl)) { return(-1); } + if (stlink_q(sl)) { return (-1); } *data = read_uint32(sl->q_buf, 4); - return(0); + return (0); } // exit the jtag or swd mode and enter the mass mode. @@ -919,10 +919,10 @@ int32_t _stlink_sg_exit_debug_mode(stlink_t *stl) { clear_cdb(sl); sl->cdb_cmd_blk[1] = STLINK_DEBUG_EXIT; stl->q_len = 0; // >0 -> aboard - return(stlink_q(stl)); + return (stlink_q(stl)); } - return(0); + return (0); } // 1) open a sg device, switch the stlink from dfu to mass mode @@ -975,7 +975,7 @@ static stlink_t* stlink_open(const int32_t verbose) { if (slsg != NULL) { free(slsg); } - return(NULL); + return (NULL); } memset(sl, 0, sizeof(stlink_t)); @@ -984,7 +984,7 @@ static stlink_t* stlink_open(const int32_t verbose) { WLOG("failed to init libusb context, wrong version of libraries?\n"); free(sl); free(slsg); - return(NULL); + return (NULL); } #if LIBUSB_API_VERSION < 0x01000106 @@ -1001,7 +1001,7 @@ static stlink_t* stlink_open(const int32_t verbose) { libusb_exit(slsg->libusb_ctx); free(sl); free(slsg); - return(NULL); + return (NULL); } // TODO: Could read the interface config descriptor, and assert lots of the assumptions @@ -1015,7 +1015,7 @@ static stlink_t* stlink_open(const int32_t verbose) { libusb_exit(slsg->libusb_ctx); free(sl); free(slsg); - return(NULL); + return (NULL); } DLOG("Kernel driver was successfully detached\n"); @@ -1030,7 +1030,7 @@ static stlink_t* stlink_open(const int32_t verbose) { libusb_exit(slsg->libusb_ctx); free(sl); free(slsg); - return(NULL); + return (NULL); } @@ -1046,7 +1046,7 @@ static stlink_t* stlink_open(const int32_t verbose) { libusb_exit(slsg->libusb_ctx); free(sl); free(slsg); - return(NULL); + return (NULL); } } @@ -1056,7 +1056,7 @@ static stlink_t* stlink_open(const int32_t verbose) { libusb_exit(slsg->libusb_ctx); free(sl); free(slsg); - return(NULL); + return (NULL); } // assumption: endpoint config is fixed mang. really. @@ -1072,7 +1072,7 @@ static stlink_t* stlink_open(const int32_t verbose) { sl->core_stat = TARGET_UNKNOWN; slsg->q_addr = 0; - return(sl); + return (sl); } @@ -1082,24 +1082,24 @@ stlink_t* stlink_v1_open_inner(const int32_t verbose) { if (sl == NULL) { ELOG("Could not open stlink device\n"); - return(NULL); + return (NULL); } stlink_version(sl); if ((sl->version.st_vid != STLINK_USB_VID_ST) || (sl->version.stlink_pid != STLINK_USB_PID_STLINK)) { ELOG("WTF? successfully opened, but unable to read version details. BROKEN!\n"); - return(NULL); + return (NULL); } DLOG("Reading current mode...\n"); switch (stlink_current_mode(sl)) { case STLINK_DEV_MASS_MODE: - return(sl); + return (sl); case STLINK_DEV_DEBUG_MODE: // TODO go to mass? - return(sl); + return (sl); default: ILOG("Current mode unusable, trying to get back to a useful state...\n"); break; @@ -1113,16 +1113,16 @@ stlink_t* stlink_v1_open_inner(const int32_t verbose) { if ((sl->version.st_vid != STLINK_USB_VID_ST) || (sl->version.stlink_pid != STLINK_USB_PID_STLINK)) { ELOG("WTF? successfully opened, but unable to read version details. BROKEN!\n"); - return(NULL); + return (NULL); } - return(sl); + return (sl); } stlink_t* stlink_v1_open(const int32_t verbose, int32_t reset) { stlink_t *sl = stlink_v1_open_inner(verbose); - if (sl == NULL) { return(NULL); } + if (sl == NULL) { return (NULL); } // by now, it _must_ be fully open and in a useful mode.... stlink_enter_swd_mode(sl); @@ -1132,5 +1132,5 @@ stlink_t* stlink_v1_open(const int32_t verbose, int32_t reset) { stlink_load_device_params(sl); ILOG("Successfully opened a stlink v1 debugger\n"); - return(sl); + return (sl); } diff --git a/src/stlink-lib/usb.c b/src/stlink-lib/usb.c index c2425b6cd..0934fe368 100644 --- a/src/stlink-lib/usb.c +++ b/src/stlink-lib/usb.c @@ -30,7 +30,7 @@ #include "register.h" static inline uint32_t le_to_h_u32(const uint8_t* buf) { - return((uint32_t)((uint32_t)buf[0] | (uint32_t)buf[1] << 8 | (uint32_t)buf[2] << 16 | (uint32_t)buf[3] << 24)); + return ((uint32_t)((uint32_t)buf[0] | (uint32_t)buf[1] << 8 | (uint32_t)buf[2] << 16 | (uint32_t)buf[3] << 24)); } static int32_t _stlink_match_speed_map(const uint32_t *map, uint32_t map_size, uint32_t khz) { @@ -73,7 +73,7 @@ static int32_t _stlink_match_speed_map(const uint32_t *map, uint32_t map_size, u ILOG("Unable to match requested speed %d kHz, using %d kHz\n", khz, map[speed_index]); } - return(speed_index); + return (speed_index); } void _stlink_usb_close(stlink_t* sl) { @@ -101,7 +101,7 @@ ssize_t send_recv(struct stlink_libusb* handle, int32_t terminate, unsigned char if (t) { ELOG("%s send request failed: %s\n", cmd, libusb_error_name(t)); - return(-1); + return (-1); } else if ((size_t)res != txsize) { ELOG("%s send request wrote %u bytes, instead of %u\n", cmd, (uint32_t)res, (uint32_t)txsize); } @@ -111,7 +111,7 @@ ssize_t send_recv(struct stlink_libusb* handle, int32_t terminate, unsigned char if (t) { ELOG("%s read reply failed: %s\n", cmd, libusb_error_name(t)); - return(-1); + return (-1); } /* Checking the command execution status stored in the first byte of the response */ @@ -139,7 +139,7 @@ ssize_t send_recv(struct stlink_libusb* handle, int32_t terminate, unsigned char default: DLOG("%s error (0x%02X)\n", cmd, rxbuf[0]); break; } - return(-1); + return (-1); } if (check_error == CMD_CHECK_REP_LEN && res != (int32_t)rxsize) { @@ -155,20 +155,20 @@ ssize_t send_recv(struct stlink_libusb* handle, int32_t terminate, unsigned char if (t) { ELOG("%s read storage failed: %s\n", cmd, libusb_error_name(t)); - return(-1); + return (-1); } // The STLink doesn't seem to evaluate the sequence number. handle->sg_transfer_idx++; } - return(res); + return (res); } } static inline int32_t send_only(struct stlink_libusb* handle, int32_t terminate, unsigned char* txbuf, uint32_t txsize, const char *cmd) { - return((int32_t)send_recv(handle, terminate, txbuf, txsize, NULL, 0, CMD_CHECK_NO, cmd)); + return ((int32_t)send_recv(handle, terminate, txbuf, txsize, NULL, 0, CMD_CHECK_NO, cmd)); } @@ -190,7 +190,7 @@ static int32_t fill_command(stlink_t * sl, enum SCSI_Generic_Direction dir, uint cmd[i++] = 0; // logical unit cmd[i++] = 0xa; // command length } - return(i); + return (i); } int32_t _stlink_usb_version(stlink_t *sl) { @@ -214,7 +214,7 @@ int32_t _stlink_usb_version(stlink_t *sl) { size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_REP_LEN, "GET_VERSION"); - return(size < 0 ? -1 : 0); + return (size < 0 ? -1 : 0); } int32_t _stlink_usb_target_voltage(stlink_t *sl) { @@ -232,14 +232,14 @@ int32_t _stlink_usb_target_voltage(stlink_t *sl) { size = send_recv(slu, 1, cmd, slu->cmd_len, rdata, rep_len, CMD_CHECK_REP_LEN, "GET_TARGET_VOLTAGE"); if (size < 0) { - return(-1); + return (-1); } factor = (rdata[3] << 24) | (rdata[2] << 16) | (rdata[1] << 8) | (rdata[0] << 0); reading = (rdata[7] << 24) | (rdata[6] << 16) | (rdata[5] << 8) | (rdata[4] << 0); voltage = 2400 * reading / factor; - return(voltage); + return (voltage); } int32_t _stlink_usb_read_debug32(stlink_t *sl, uint32_t addr, uint32_t *data) { @@ -256,12 +256,12 @@ int32_t _stlink_usb_read_debug32(stlink_t *sl, uint32_t addr, uint32_t *data) { size = send_recv(slu, 1, cmd, slu->cmd_len, rdata, rep_len, CMD_CHECK_RETRY, "READDEBUGREG"); if (size < 0) { - return(-1); + return (-1); } *data = read_uint32(rdata, 4); - return(0); + return (0); } int32_t _stlink_usb_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data) { @@ -278,11 +278,11 @@ int32_t _stlink_usb_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data) { write_uint32(&cmd[i + 4], data); size = send_recv(slu, 1, cmd, slu->cmd_len, rdata, rep_len, CMD_CHECK_RETRY, "WRITEDEBUGREG"); - return(size < 0 ? -1 : 0); + return (size < 0 ? -1 : 0); } int32_t _stlink_usb_get_rw_status(stlink_t *sl) { - if (sl->version.jtag_api == STLINK_JTAG_API_V1) { return(0); } + if (sl->version.jtag_api == STLINK_JTAG_API_V1) { return (0); } unsigned char* const rdata = sl->q_buf; struct stlink_libusb * const slu = sl->backend_data; @@ -301,7 +301,7 @@ int32_t _stlink_usb_get_rw_status(stlink_t *sl) { ret = send_recv(slu, 1, cmd, slu->cmd_len, rdata, 2, CMD_CHECK_STATUS, "GETLASTRWSTATUS"); } - return(ret < 0 ? -1 : 0); + return (ret < 0 ? -1 : 0); } int32_t _stlink_usb_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { @@ -317,13 +317,13 @@ int32_t _stlink_usb_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { write_uint16(&cmd[i + 4], len); ret = send_only(slu, 0, cmd, slu->cmd_len, "WRITEMEM_32BIT"); - if (ret == -1) { return(ret); } + if (ret == -1) { return (ret); } ret = send_only(slu, 1, data, len, "WRITEMEM_32BIT"); - if (ret == -1) { return(ret); } + if (ret == -1) { return (ret); } - return(_stlink_usb_get_rw_status(sl)); + return (_stlink_usb_get_rw_status(sl)); } int32_t _stlink_usb_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len) { @@ -345,13 +345,13 @@ int32_t _stlink_usb_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len) { write_uint16(&cmd[i + 4], len); ret = send_only(slu, 0, cmd, slu->cmd_len, "WRITEMEM_8BIT"); - if (ret == -1) { return(ret); } + if (ret == -1) { return (ret); } ret = send_only(slu, 1, data, len, "WRITEMEM_8BIT"); - if (ret == -1) { return(ret); } + if (ret == -1) { return (ret); } - return(0); + return (0); } int32_t _stlink_usb_current_mode(stlink_t * sl) { @@ -366,10 +366,10 @@ int32_t _stlink_usb_current_mode(stlink_t * sl) { size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_NO, "GET_CURRENT_MODE"); if (size < 0) { - return(-1); + return (-1); } - return(sl->q_buf[0]); + return (sl->q_buf[0]); } int32_t _stlink_usb_core_id(stlink_t * sl) { @@ -393,12 +393,12 @@ int32_t _stlink_usb_core_id(stlink_t * sl) { size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_STATUS, "READ_IDCODES"); if (size < 0) { - return(-1); + return (-1); } sl->core_id = read_uint32(data, offset); - return(0); + return (0); } int32_t _stlink_usb_status_v2(stlink_t *sl) { @@ -420,11 +420,11 @@ int32_t _stlink_usb_status_v2(stlink_t *sl) { } } - return(result); + return (result); } int32_t _stlink_usb_status(stlink_t * sl) { - if (sl->version.jtag_api != STLINK_JTAG_API_V1) { return(_stlink_usb_status_v2(sl)); } + if (sl->version.jtag_api != STLINK_JTAG_API_V1) { return (_stlink_usb_status_v2(sl)); } struct stlink_libusb * const slu = sl->backend_data; unsigned char* const data = sl->q_buf; @@ -449,7 +449,7 @@ int32_t _stlink_usb_status(stlink_t * sl) { sl->core_stat = TARGET_UNKNOWN; } - return(size < 0 ? -1 : 0); + return (size < 0 ? -1 : 0); } int32_t _stlink_usb_force_debug(stlink_t *sl) { @@ -459,7 +459,7 @@ int32_t _stlink_usb_force_debug(stlink_t *sl) { if (sl->version.jtag_api != STLINK_JTAG_API_V1) { res = _stlink_usb_write_debug32(sl, STLINK_REG_DHCSR, STLINK_REG_DHCSR_DBGKEY | STLINK_REG_DHCSR_C_HALT | STLINK_REG_DHCSR_C_DEBUGEN); - return(res); + return (res); } unsigned char* const data = sl->q_buf; @@ -472,7 +472,7 @@ int32_t _stlink_usb_force_debug(stlink_t *sl) { cmd[i++] = STLINK_DEBUG_FORCEDEBUG; size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_RETRY, "FORCEDEBUG"); - return(size < 0 ? -1 : 0); + return (size < 0 ? -1 : 0); } int32_t _stlink_usb_enter_swd_mode(stlink_t * sl) { @@ -489,7 +489,7 @@ int32_t _stlink_usb_enter_swd_mode(stlink_t * sl) { cmd[i++] = STLINK_DEBUG_ENTER_SWD; size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_RETRY, "ENTER_SWD"); - return(size < 0 ? -1 : 0); + return (size < 0 ? -1 : 0); } int32_t _stlink_usb_exit_dfu_mode(stlink_t* sl) { @@ -502,7 +502,7 @@ int32_t _stlink_usb_exit_dfu_mode(stlink_t* sl) { cmd[i++] = STLINK_DFU_EXIT; size = send_only(slu, 1, cmd, slu->cmd_len, "DFU_EXIT"); - return(size < 0 ? -1 : 0); + return (size < 0 ? -1 : 0); } @@ -525,7 +525,7 @@ int32_t _stlink_usb_reset(stlink_t * sl) { size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_RETRY, "RESETSYS"); - return(size < 0 ? -1 : 0); + return (size < 0 ? -1 : 0); } int32_t _stlink_usb_jtag_reset(stlink_t * sl, int32_t value) { @@ -541,7 +541,7 @@ int32_t _stlink_usb_jtag_reset(stlink_t * sl, int32_t value) { cmd[i++] = value; size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_RETRY, "DRIVE_NRST"); - return(size < 0 ? -1 : 0); + return (size < 0 ? -1 : 0); } @@ -568,7 +568,7 @@ int32_t _stlink_usb_step(stlink_t* sl) { cmd[i++] = STLINK_DEBUG_STEPCORE; size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_RETRY, "STEPCORE"); - return(size < 0 ? -1 : 0); + return (size < 0 ? -1 : 0); } /** @@ -584,7 +584,7 @@ int32_t _stlink_usb_run(stlink_t* sl, enum run_type type) { if (sl->version.jtag_api != STLINK_JTAG_API_V1) { res = _stlink_usb_write_debug32(sl, STLINK_REG_DHCSR, STLINK_REG_DHCSR_DBGKEY | STLINK_REG_DHCSR_C_DEBUGEN | ((type==RUN_FLASH_LOADER)?STLINK_REG_DHCSR_C_MASKINTS:0)); - return(res); + return (res); } @@ -598,7 +598,7 @@ int32_t _stlink_usb_run(stlink_t* sl, enum run_type type) { cmd[i++] = STLINK_DEBUG_RUNCORE; size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_RETRY, "RUNCORE"); - return(size < 0 ? -1 : 0); + return (size < 0 ? -1 : 0); } int32_t _stlink_usb_set_swdclk(stlink_t* sl, int32_t clk_freq) { @@ -641,7 +641,7 @@ int32_t _stlink_usb_set_swdclk(stlink_t* sl, int32_t clk_freq) { cmd[i++] = (clk_divisor >> 8) & 0xFF; size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_RETRY, "SWD_SET_FREQ"); - return(size < 0 ? -1 : 0); + return (size < 0 ? -1 : 0); } else if (sl->version.stlink_v == 3) { int32_t speed_index; uint32_t map[STLINK_V3_MAX_FREQ_NB]; @@ -653,7 +653,7 @@ int32_t _stlink_usb_set_swdclk(stlink_t* sl, int32_t clk_freq) { size = send_recv(slu, 1, cmd, slu->cmd_len, data, 52, CMD_CHECK_STATUS, "GET_COM_FREQ"); if (size < 0) { - return(-1); + return (-1); } int32_t speeds_size = data[8]; @@ -682,12 +682,12 @@ int32_t _stlink_usb_set_swdclk(stlink_t* sl, int32_t clk_freq) { size = send_recv(slu, 1, cmd, slu->cmd_len, data, 8, CMD_CHECK_STATUS, "SET_COM_FREQ"); - return(size < 0 ? -1 : 0); + return (size < 0 ? -1 : 0); } else if (clk_freq) { WLOG("ST-Link firmware does not support frequency setup\n"); } - return(-1); + return (-1); } int32_t _stlink_usb_exit_debug_mode(stlink_t *sl) { @@ -701,7 +701,7 @@ int32_t _stlink_usb_exit_debug_mode(stlink_t *sl) { size = send_only(slu, 1, cmd, slu->cmd_len, "DEBUG_EXIT"); - return(size < 0 ? -1 : 0); + return (size < 0 ? -1 : 0); } int32_t _stlink_usb_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { @@ -718,13 +718,13 @@ int32_t _stlink_usb_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { size = send_recv(slu, 1, cmd, slu->cmd_len, data, len, CMD_CHECK_NO, "READMEM_32BIT"); if (size < 0) { - return(-1); + return (-1); } sl->q_len = (int32_t)size; stlink_print_data(sl); - return(0); + return (0); } int32_t _stlink_usb_read_all_regs(stlink_t *sl, struct stlink_reg *regp) { @@ -746,7 +746,7 @@ int32_t _stlink_usb_read_all_regs(stlink_t *sl, struct stlink_reg *regp) { size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_STATUS, "READALLREGS"); if (size < 0) { - return(-1); + return (-1); } /* V1: regs data from offset 0 */ @@ -763,7 +763,7 @@ int32_t _stlink_usb_read_all_regs(stlink_t *sl, struct stlink_reg *regp) { regp->rw = read_uint32(sl->q_buf, reg_offset + 76); regp->rw2 = read_uint32(sl->q_buf, reg_offset + 80); - if (sl->verbose < 2) { return(0); } + if (sl->verbose < 2) { return (0); } DLOG("xpsr = 0x%08x\n", regp->xpsr); DLOG("main_sp = 0x%08x\n", regp->main_sp); @@ -771,7 +771,7 @@ int32_t _stlink_usb_read_all_regs(stlink_t *sl, struct stlink_reg *regp) { DLOG("rw = 0x%08x\n", regp->rw); DLOG("rw2 = 0x%08x\n", regp->rw2); - return(0); + return (0); } int32_t _stlink_usb_read_reg(stlink_t *sl, int32_t r_idx, struct stlink_reg *regp) { @@ -796,7 +796,7 @@ int32_t _stlink_usb_read_reg(stlink_t *sl, int32_t r_idx, struct stlink_reg *reg size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_RETRY, "READREG"); if (size < 0) { - return(-1); + return (-1); } sl->q_len = (int32_t)size; @@ -824,7 +824,7 @@ int32_t _stlink_usb_read_reg(stlink_t *sl, int32_t r_idx, struct stlink_reg *reg regp->r[r_idx] = r; } - return(0); + return (0); } /* See section C1.6 of the ARMv7-M Architecture Reference Manual */ @@ -838,11 +838,11 @@ int32_t _stlink_usb_read_unsupported_reg(stlink_t *sl, int32_t r_idx, struct stl ret = _stlink_usb_write_mem32(sl, STLINK_REG_DCRSR, 4); - if (ret == -1) { return(ret); } + if (ret == -1) { return (ret); } ret = _stlink_usb_read_mem32(sl, STLINK_REG_DCRDR, 4); - if (ret == -1) { return(ret); } + if (ret == -1) { return (ret); } r = read_uint32(sl->q_buf, 0); DLOG("r_idx (%2d) = 0x%08x\n", r_idx, r); @@ -862,7 +862,7 @@ int32_t _stlink_usb_read_unsupported_reg(stlink_t *sl, int32_t r_idx, struct stl break; } - return(0); + return (0); } int32_t _stlink_usb_read_all_unsupported_regs(stlink_t *sl, struct stlink_reg *regp) { @@ -870,19 +870,19 @@ int32_t _stlink_usb_read_all_unsupported_regs(stlink_t *sl, struct stlink_reg *r ret = _stlink_usb_read_unsupported_reg(sl, 0x14, regp); - if (ret == -1) { return(ret); } + if (ret == -1) { return (ret); } ret = _stlink_usb_read_unsupported_reg(sl, 0x21, regp); - if (ret == -1) { return(ret); } + if (ret == -1) { return (ret); } for (int32_t i = 0; i < 32; i++) { ret = _stlink_usb_read_unsupported_reg(sl, 0x40 + i, regp); - if (ret == -1) { return(ret); } + if (ret == -1) { return (ret); } } - return(0); + return (0); } /* See section C1.6 of the ARMv7-M Architecture Reference Manual */ @@ -893,7 +893,7 @@ int32_t _stlink_usb_write_unsupported_reg(stlink_t *sl, uint32_t val, int32_t r_ /* These are held in the same register */ ret = _stlink_usb_read_unsupported_reg(sl, 0x14, regp); - if (ret == -1) { return(ret); } + if (ret == -1) { return (ret); } val = (uint8_t)(val >> 24); @@ -931,14 +931,14 @@ int32_t _stlink_usb_write_unsupported_reg(stlink_t *sl, uint32_t val, int32_t r_ ret = _stlink_usb_write_mem32(sl, STLINK_REG_DCRDR, 4); - if (ret == -1) { return(ret); } + if (ret == -1) { return (ret); } sl->q_buf[0] = (unsigned char)r_idx; sl->q_buf[1] = 0; sl->q_buf[2] = 0x01; sl->q_buf[3] = 0; - return(_stlink_usb_write_mem32(sl, STLINK_REG_DCRSR, 4)); + return (_stlink_usb_write_mem32(sl, STLINK_REG_DCRSR, 4)); } int32_t _stlink_usb_write_reg(stlink_t *sl, uint32_t reg, int32_t idx) { @@ -961,7 +961,7 @@ int32_t _stlink_usb_write_reg(stlink_t *sl, uint32_t reg, int32_t idx) { write_uint32(&cmd[i], reg); size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_RETRY, "WRITEREG"); - return(size < 0 ? -1 : 0); + return (size < 0 ? -1 : 0); } int32_t _stlink_usb_enable_trace(stlink_t* sl, uint32_t frequency) { @@ -979,7 +979,7 @@ int32_t _stlink_usb_enable_trace(stlink_t* sl, uint32_t frequency) { size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_STATUS, "START_TRACE_RX"); - return(size < 0 ? -1 : 0); + return (size < 0 ? -1 : 0); } int32_t _stlink_usb_disable_trace(stlink_t* sl) { @@ -995,7 +995,7 @@ int32_t _stlink_usb_disable_trace(stlink_t* sl) { size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_STATUS, "STOP_TRACE_RX"); - return(size < 0 ? -1 : 0); + return (size < 0 ? -1 : 0); } int32_t _stlink_usb_read_trace(stlink_t* sl, uint8_t* buf, uint32_t size) { @@ -1010,10 +1010,10 @@ int32_t _stlink_usb_read_trace(stlink_t* sl, uint8_t* buf, uint32_t size) { ssize_t send_size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_NO, "GET_TRACE_NB"); if (send_size < 0) { - return(-1); + return (-1); } else if (send_size != 2) { ELOG("STLINK_DEBUG_APIV2_GET_TRACE_NB reply size %d\n", (int32_t)send_size); - return(-1); + return (-1); } uint16_t trace_count = read_uint16(sl->q_buf, 0); @@ -1029,7 +1029,7 @@ int32_t _stlink_usb_read_trace(stlink_t* sl, uint8_t* buf, uint32_t size) { if (t || res != (int32_t)trace_count) { ELOG("read_trace read error %d\n", t); - return(-1); + return (-1); } } @@ -1282,11 +1282,11 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, enum connect_type connect, _stlink_usb_set_swdclk(sl, freq); stlink_target_connect(sl, connect); - return(sl); + return (sl); on_libusb_error: stlink_close(sl); - return(NULL); + return (NULL); on_error: if (slu->libusb_ctx) { libusb_exit(slu->libusb_ctx); } @@ -1295,7 +1295,7 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, enum connect_type connect, if (sl != NULL) { free(sl); } if (slu != NULL) { free(slu); } - return(NULL); + return (NULL); } static uint32_t stlink_probe_usb_devs(libusb_device **devs, stlink_t **sldevs[], enum connect_type connect, int32_t freq) { @@ -1329,7 +1329,7 @@ static uint32_t stlink_probe_usb_devs(libusb_device **devs, stlink_t **sldevs[], if (!_sldevs) { *sldevs = NULL; - return(0); + return (0); } /* Open STLINKS and attach them to list */ @@ -1379,7 +1379,7 @@ static uint32_t stlink_probe_usb_devs(libusb_device **devs, stlink_t **sldevs[], *sldevs = _sldevs; - return(slcur); + return (slcur); } size_t stlink_probe_usb(stlink_t **stdevs[], enum connect_type connect, int32_t freq) { @@ -1392,11 +1392,11 @@ size_t stlink_probe_usb(stlink_t **stdevs[], enum connect_type connect, int32_t r = libusb_init(NULL); - if (r < 0) { return(0); } + if (r < 0) { return (0); } cnt = libusb_get_device_list(NULL, &devs); - if (cnt < 0) { return(0); } + if (cnt < 0) { return (0); } slcnt = stlink_probe_usb_devs(devs, &sldevs, connect, freq); libusb_free_device_list(devs, 1); @@ -1405,7 +1405,7 @@ size_t stlink_probe_usb(stlink_t **stdevs[], enum connect_type connect, int32_t *stdevs = sldevs; - return(slcnt); + return (slcnt); } void stlink_probe_usb_free(stlink_t ***stdevs, uint32_t size) { diff --git a/src/win32/getopt/getopt.c b/src/win32/getopt/getopt.c index 417b0aecf..3347da34d 100644 --- a/src/win32/getopt/getopt.c +++ b/src/win32/getopt/getopt.c @@ -118,11 +118,11 @@ int32_t getopt(int32_t argc, char* const argv[], const char* optstring) { if (optcursor == NULL || *++optcursor == '\0') { ++optind; } - return(optchar); + return (optchar); no_more_optchars: optcursor = NULL; - return(-1); + return (-1); } /* Implementation based on http://www.kernel.org/doc/man-pages/online/pages/man3/getopt.3.html */ @@ -141,10 +141,10 @@ int32_t getopt_long(int32_t argc, optarg = NULL; optopt = 0; - if (optind >= argc) { return(-1); } + if (optind >= argc) { return (-1); } if (strlen(argv[optind]) < 3 || strncmp(argv[optind], "--", 2) != 0) { - return(getopt(argc, argv, optstring)); + return (getopt(argc, argv, optstring)); } // it's an option; starts with -- and is longer than two chars @@ -198,5 +198,5 @@ int32_t getopt_long(int32_t argc, } ++optind; - return(retval); + return (retval); } diff --git a/src/win32/mmap.c b/src/win32/mmap.c index 7e76b3344..8bddb5094 100644 --- a/src/win32/mmap.c +++ b/src/win32/mmap.c @@ -10,30 +10,30 @@ void *mmap (void *addr, uint32_t len, int32_t prot, int32_t flags, int32_t fd, i void *buf; ssize_t count; - if ( addr || fd == -1 || (prot & PROT_WRITE)) { return(MAP_FAILED); } + if ( addr || fd == -1 || (prot & PROT_WRITE)) { return (MAP_FAILED); } buf = malloc(len); - if ( NULL == buf ) { return(MAP_FAILED); } + if ( NULL == buf ) { return (MAP_FAILED); } if (lseek(fd, offset, SEEK_SET) != offset) { free(buf); - return(MAP_FAILED); + return (MAP_FAILED); } count = read(fd, buf, len); if (count != (ssize_t)len) { free (buf); - return(MAP_FAILED); + return (MAP_FAILED); } - return(buf); + return (buf); (void)flags; } int32_t munmap (void *addr, uint32_t len) { free (addr); - return(0); + return (0); (void)len; } diff --git a/src/win32/sys_time.c b/src/win32/sys_time.c index a09d8df67..f1ebd63b9 100644 --- a/src/win32/sys_time.c +++ b/src/win32/sys_time.c @@ -12,7 +12,7 @@ int32_t gettimeofday(struct timeval *tv, struct timezone *tz) { ULARGE_INTEGER ulint; static int32_t tzflag = 0; - if(NULL != tv) { + if (NULL != tv) { GetSystemTimeAsFileTime(&ftime); ulint.LowPart = ftime.dwLowDateTime; ulint.HighPart = ftime.dwHighDateTime; @@ -21,7 +21,7 @@ int32_t gettimeofday(struct timeval *tv, struct timezone *tz) { tv->tv_usec = (int32_t)(ulint.QuadPart % 10000000L); } - if(NULL != tz) { + if (NULL != tz) { if (!tzflag) { _tzset(); tzflag++; diff --git a/src/win32/win32_socket.c b/src/win32/win32_socket.c index 46b4532a7..d3038882b 100644 --- a/src/win32/win32_socket.c +++ b/src/win32/win32_socket.c @@ -68,7 +68,7 @@ int32_t win32_poll(struct pollfd *fds, uint32_t nfds, int32_t timo) { printf("Exiting select rc=%d\n", rc); #endif - if (rc <= 0) { return(rc); } + if (rc <= 0) { return (rc); } if (rc > 0) { for ( i = 0; i < nfds; ++i) { @@ -98,7 +98,7 @@ int32_t win32_poll(struct pollfd *fds, uint32_t nfds, int32_t timo) { } } - return(rc); + return (rc); } static void set_connect_errno(int32_t winsock_err) { @@ -135,7 +135,7 @@ SOCKET win32_socket(int32_t domain, int32_t type, int32_t protocol) { if (fd == INVALID_SOCKET) { set_socket_errno(WSAGetLastError()); } - return(fd); + return (fd); } /* @@ -149,7 +149,7 @@ int32_t win32_connect(SOCKET fd, struct sockaddr *addr, socklen_t addr_len) { if (rc == SOCKET_ERROR) { set_connect_errno(WSAGetLastError()); } - return(rc); + return (rc); } /* A wrapper around the accept() function. @@ -164,7 +164,7 @@ SOCKET win32_accept(SOCKET fd, struct sockaddr *addr, socklen_t *addr_len) { newfd = (SOCKET)-1; } - return(newfd); + return (newfd); } /* A wrapper around the shutdown() function. @@ -177,7 +177,7 @@ int32_t win32_shutdown(SOCKET fd, int32_t mode) { if (rc == SOCKET_ERROR) { set_socket_errno(WSAGetLastError()); } - return(rc); + return (rc); } int32_t win32_close_socket(SOCKET fd) { @@ -185,7 +185,7 @@ int32_t win32_close_socket(SOCKET fd) { if (rc == SOCKET_ERROR) { set_socket_errno(WSAGetLastError()); } - return(rc); + return (rc); } ssize_t win32_write_socket(SOCKET fd, void *buf, int32_t n) { @@ -193,7 +193,7 @@ ssize_t win32_write_socket(SOCKET fd, void *buf, int32_t n) { if (rc == SOCKET_ERROR) { set_socket_errno(WSAGetLastError()); } - return(rc); + return (rc); } ssize_t win32_read_socket(SOCKET fd, void *buf, int32_t n) { @@ -201,7 +201,7 @@ ssize_t win32_read_socket(SOCKET fd, void *buf, int32_t n) { if (rc == SOCKET_ERROR) { set_socket_errno(WSAGetLastError()); } - return(rc); + return (rc); } @@ -244,7 +244,7 @@ char * win32_strtok_r(char *s, const char *delim, char **lasts) { } *lasts = s; - return(tok); + return (tok); } } while (sc != 0); @@ -260,7 +260,7 @@ char *win32_strsep (char **stringp, const char *delim) { char *tok; if ((s = *stringp) == NULL) { - return(NULL); + return (NULL); } for (tok = s; ;) { @@ -276,7 +276,7 @@ char *win32_strsep (char **stringp, const char *delim) { } *stringp = s; - return(tok); + return (tok); } } while (sc != 0); @@ -301,7 +301,7 @@ int32_t usleep(uint32_t waitTime) { WaitForSingleObject(timer, INFINITE); CloseHandle(timer); - return(0); + return (0); } LARGE_INTEGER perf_cnt, start, now; @@ -313,7 +313,7 @@ int32_t usleep(uint32_t waitTime) { QueryPerformanceCounter((LARGE_INTEGER*)&now); } while ((now.QuadPart - start.QuadPart) / (float)perf_cnt.QuadPart * 1000 * 1000 < waitTime); - return(0); + return (0); } #endif diff --git a/tests/flash.c b/tests/flash.c index f4c838d5d..4d9ac5185 100644 --- a/tests/flash.c +++ b/tests/flash.c @@ -49,7 +49,7 @@ static bool execute_test(const struct Test * test) { strcpy(cmd_line, test->cmd_line); for (char * tok = strtok(cmd_line, " "); tok; tok = strtok(NULL, " ")) { - if ((size_t)ac >= sizeof(av) / sizeof(av[0])) return(false); + if ((size_t)ac >= sizeof(av) / sizeof(av[0])) return (false); av[ac] = tok; ++ac; @@ -75,7 +75,7 @@ static bool execute_test(const struct Test * test) { } printf("[%s] (%d) %s\n", ret ? "OK" : "ERROR", res, test->cmd_line); - return(ret); + return (ret); } static struct Test tests[] = { diff --git a/tests/sg.c b/tests/sg.c index 6881266ab..67d804b23 100644 --- a/tests/sg.c +++ b/tests/sg.c @@ -44,7 +44,7 @@ int32_t main(void) { // main() ripped out of old stlink-hw.c stlink_t *sl = stlink_v1_open(99, 1); - if (sl == NULL) return(0); + if (sl == NULL) return (0); // we are in mass mode, go to swd stlink_enter_swd_mode(sl); @@ -212,5 +212,5 @@ int32_t main(void) { // main() ripped out of old stlink-hw.c // fflush(stderr); // fflush(stdout); - return(EXIT_SUCCESS); + return (EXIT_SUCCESS); } diff --git a/tests/usb.c b/tests/usb.c index 9acd0b02d..5dbb1d83c 100644 --- a/tests/usb.c +++ b/tests/usb.c @@ -29,7 +29,7 @@ int32_t main(int32_t ac, char** av) { if (reset == 0) { usage(); - return(0); + return (0); } sl = stlink_open_usb(10, reset, NULL, 0); @@ -125,5 +125,5 @@ int32_t main(int32_t ac, char** av) { stlink_close(sl); } - return(0); + return (0); } From 041517bd4a8caf7dbf17b0c7d8004272cbaefa43 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 25 Jun 2023 15:31:13 +0200 Subject: [PATCH 457/503] Fixed flashing on STM32G0/G4 dual bank devices (Closes #1310) --- src/stlink-lib/common_flash.c | 25 +++++++++++-------------- 1 file changed, 11 insertions(+), 14 deletions(-) diff --git a/src/stlink-lib/common_flash.c b/src/stlink-lib/common_flash.c index f2281ac11..885be9c74 100644 --- a/src/stlink-lib/common_flash.c +++ b/src/stlink-lib/common_flash.c @@ -307,6 +307,9 @@ int32_t check_flash_error(stlink_t *sl) { case STM32_FLASH_TYPE_G0: case STM32_FLASH_TYPE_G4: res = read_flash_sr(sl, BANK_1) & FLASH_Gx_SR_ERROR_MASK; + if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { + res |= read_flash_sr(sl, BANK_2) & FLASH_Gx_SR_ERROR_MASK; + } WRPERR = (1 << FLASH_Gx_SR_WRPERR); PROGERR = (1 << FLASH_Gx_SR_PROGERR); PGAERR = (1 << FLASH_Gx_SR_PGAERR); @@ -1013,10 +1016,8 @@ int32_t stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { if ((val & (1 << 0)) || (val & (1 << 1))) { // disable pecr protection - stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, - FLASH_L0_PEKEY1); - stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, - FLASH_L0_PEKEY2); + stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, FLASH_L0_PEKEY1); + stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, FLASH_L0_PEKEY2); // check pecr.pelock is cleared stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); @@ -1118,8 +1119,7 @@ int32_t stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { clear_flash_cr_pg(sl, bank); // clear the pg bit set_flash_cr_per(sl, bank); // set the page erase bit write_flash_ar(sl, flashaddr, bank); // select the page to erase - set_flash_cr_strt(sl, - bank); // start erase operation, reset by hw with busy bit + set_flash_cr_strt(sl, bank); // start erase operation, reset by hw with busy bit wait_flash_busy(sl); clear_flash_cr_per(sl, bank); // clear the page erase bit lock_flash(sl); @@ -1180,7 +1180,7 @@ int32_t stlink_erase_flash_section(stlink_t *sl, stm32_addr_t base_addr, uint32_ int32_t stlink_erase_flash_mass(stlink_t *sl) { int32_t err = 0; - // TODO: User MER bit to mass-erase WB series. + // TODO: Use MER bit to mass-erase WB series. if (sl->flash_type == STM32_FLASH_TYPE_L0_L1 || sl->flash_type == STM32_FLASH_TYPE_WB_WL) { @@ -1193,15 +1193,14 @@ int32_t stlink_erase_flash_mass(stlink_t *sl) { if (sl->flash_type == STM32_FLASH_TYPE_H7 && sl->chip_id != STM32_CHIPID_H7Ax) { // set parallelism - write_flash_cr_psiz(sl, 3 /*64it*/, BANK_1); + write_flash_cr_psiz(sl, 3 /*64bit*/, BANK_1); if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { write_flash_cr_psiz(sl, 3 /*64bit*/, BANK_2); } } set_flash_cr_mer(sl, 1, BANK_1); // set the mass erase bit - set_flash_cr_strt( - sl, BANK_1); // start erase operation, reset by hw with busy bit + set_flash_cr_strt(sl, BANK_1); // start erase operation, reset by hw with busy bit if (sl->flash_type == STM32_FLASH_TYPE_F1_XL || (sl->flash_type == STM32_FLASH_TYPE_H7 && sl->chip_flags & CHIP_F_HAS_DUAL_BANK)) { @@ -1246,8 +1245,7 @@ int32_t stlink_mwrite_flash(stlink_t *sl, uint8_t *data, uint32_t length, stm32_ num_empty -= (num_empty & 3); // Round down to words if (num_empty != 0) { - ILOG("Ignoring %d bytes of 0x%02x at end of file\n", num_empty, - erased_pattern); + ILOG("Ignoring %d bytes of 0x%02x at end of file\n", num_empty, erased_pattern); } } else { num_empty = 0; @@ -1300,8 +1298,7 @@ int32_t stlink_fwrite_flash(stlink_t *sl, const char *path, stm32_addr_t addr) { num_empty -= (num_empty & 3); // round down to words if (num_empty != 0) { - ILOG("Ignoring %d bytes of 0x%02x at end of file\n", num_empty, - erased_pattern); + ILOG("Ignoring %d bytes of 0x%02x at end of file\n", num_empty, erased_pattern); } } else { num_empty = 0; From 8fad9be9d0b055069b3f4fcdc3dc17014a6ce9cb Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 25 Jun 2023 15:45:33 +0200 Subject: [PATCH 458/503] [refactoring] Clean-up for stlink-lib - Moved declarations for read/write functions to read_write.h . - Checked & revised header includes - Changed some datatypes for write_buffer_to_sram() to avoid explicit casting. --- SECURITY.md | 2 +- inc/stlink.h | 24 +++---------- src/st-trace/trace.c | 1 + src/st-util/gdb-server.c | 1 + src/st-util/semihosting.c | 3 +- src/stlink-gui/gui.c | 1 + src/stlink-lib/calculate.c | 1 + src/stlink-lib/common.c | 11 +++--- src/stlink-lib/common_flash.c | 1 + src/stlink-lib/flash_loader.c | 1 + src/stlink-lib/map_file.c | 2 ++ src/stlink-lib/option_bytes.c | 1 + src/stlink-lib/read_write.c | 67 +++++++++++++++++++---------------- src/stlink-lib/read_write.h | 27 ++++++++++++++ src/stlink-lib/sg.c | 1 + src/stlink-lib/usb.c | 1 + tests/sg.c | 1 + tests/usb.c | 1 + 18 files changed, 90 insertions(+), 57 deletions(-) create mode 100644 src/stlink-lib/read_write.h diff --git a/SECURITY.md b/SECURITY.md index 9ace47066..054641822 100644 --- a/SECURITY.md +++ b/SECURITY.md @@ -7,7 +7,7 @@ The following versions of the stlink toolset are currently being supported.
#include +#include #include #include diff --git a/src/st-util/gdb-server.c b/src/st-util/gdb-server.c index 8a187fb24..d001395e9 100644 --- a/src/st-util/gdb-server.c +++ b/src/st-util/gdb-server.c @@ -36,6 +36,7 @@ #include #include #include +#include #include #include diff --git a/src/st-util/semihosting.c b/src/st-util/semihosting.c index a200a7408..8e9828ce8 100644 --- a/src/st-util/semihosting.c +++ b/src/st-util/semihosting.c @@ -8,9 +8,10 @@ #include #include +#include "semihosting.h" #include -#include "semihosting.h" +#include static int32_t mem_read_u8(stlink_t *sl, uint32_t addr, uint8_t *data) { int32_t offset = addr % 4; diff --git a/src/stlink-gui/gui.c b/src/stlink-gui/gui.c index 4b312c8a1..e3eec34b8 100644 --- a/src/stlink-gui/gui.c +++ b/src/stlink-gui/gui.c @@ -9,6 +9,7 @@ #include #include +#include #include #define MEM_READ_SIZE 1024 diff --git a/src/stlink-lib/calculate.c b/src/stlink-lib/calculate.c index 027239694..a7344e0b0 100644 --- a/src/stlink-lib/calculate.c +++ b/src/stlink-lib/calculate.c @@ -10,6 +10,7 @@ #include "calculate.h" #include "common_flash.h" +#include "read_write.h" uint32_t calculate_F4_sectornum(uint32_t flashaddr) { uint32_t offset = 0; diff --git a/src/stlink-lib/common.c b/src/stlink-lib/common.c index 70ecdd3a2..dbfcc8b9e 100644 --- a/src/stlink-lib/common.c +++ b/src/stlink-lib/common.c @@ -25,6 +25,7 @@ #include "logging.h" #include "map_file.h" #include "md5.h" +#include "read_write.h" #include "register.h" #include "usb.h" @@ -808,20 +809,20 @@ int32_t stlink_fread(stlink_t *sl, const char *path, bool is_ihex, stm32_addr_t } // 300 -int32_t write_buffer_to_sram(stlink_t *sl, flash_loader_t *fl, const uint8_t *buf, uint32_t size) { +int32_t write_buffer_to_sram(stlink_t *sl, flash_loader_t *fl, const uint8_t *buf, uint16_t size) { // write the buffer right after the loader int32_t ret = 0; - uint32_t chunk = size & ~0x3; - uint32_t rem = size & 0x3; + uint16_t chunk = size & ~0x3; + uint16_t rem = size & 0x3; if (chunk) { memcpy(sl->q_buf, buf, chunk); - ret = stlink_write_mem32(sl, fl->buf_addr, (uint16_t)chunk); + ret = stlink_write_mem32(sl, fl->buf_addr, chunk); } if (rem && !ret) { memcpy(sl->q_buf, buf + chunk, rem); - ret = stlink_write_mem8(sl, (fl->buf_addr) + chunk, (uint16_t)rem); + ret = stlink_write_mem8(sl, (fl->buf_addr) + chunk, rem); } return (ret); diff --git a/src/stlink-lib/common_flash.c b/src/stlink-lib/common_flash.c index 885be9c74..3038b53e7 100644 --- a/src/stlink-lib/common_flash.c +++ b/src/stlink-lib/common_flash.c @@ -18,6 +18,7 @@ #include "logging.h" #include "map_file.h" #include "md5.h" +#include "read_write.h" #define DEBUG_FLASH 0 diff --git a/src/stlink-lib/flash_loader.c b/src/stlink-lib/flash_loader.c index 0f12c3131..e1e9e9995 100644 --- a/src/stlink-lib/flash_loader.c +++ b/src/stlink-lib/flash_loader.c @@ -16,6 +16,7 @@ #include "common_flash.h" #include "helper.h" #include "logging.h" +#include "read_write.h" #include "register.h" #define FLASH_REGS_BANK2_OFS 0x40 diff --git a/src/stlink-lib/map_file.c b/src/stlink-lib/map_file.c index e8c4b71a3..118c80d34 100644 --- a/src/stlink-lib/map_file.c +++ b/src/stlink-lib/map_file.c @@ -15,6 +15,8 @@ #include #include "map_file.h" +#include "read_write.h" + #ifndef O_BINARY #define O_BINARY 0 #endif diff --git a/src/stlink-lib/option_bytes.c b/src/stlink-lib/option_bytes.c index c84ace348..ee03dced9 100644 --- a/src/stlink-lib/option_bytes.c +++ b/src/stlink-lib/option_bytes.c @@ -16,6 +16,7 @@ #include "logging.h" #include "map_file.h" #include "md5.h" +#include "read_write.h" /** * Read option control register F0 diff --git a/src/stlink-lib/read_write.c b/src/stlink-lib/read_write.c index 9149080af..4e43d8aa5 100644 --- a/src/stlink-lib/read_write.c +++ b/src/stlink-lib/read_write.c @@ -1,8 +1,15 @@ +/* + * File: read_write.c + * + * Read and write operations + */ + #include #include #include #include +#include "read_write.h" #include "logging.h" @@ -10,11 +17,8 @@ // https://commandcenter.blogspot.com/2012/04/byte-order-fallacy.html // These functions encode and decode little endian uint16 and uint32 values. -void write_uint32(unsigned char *buf, uint32_t ui) { - buf[0] = ui; - buf[1] = ui >> 8; - buf[2] = ui >> 16; - buf[3] = ui >> 24; +uint16_t read_uint16(const unsigned char *c, const int32_t pt) { + return ((uint16_t)c[pt]) | ((uint16_t)c[pt + 1] << 8); } void write_uint16(unsigned char *buf, uint16_t ui) { @@ -27,8 +31,11 @@ uint32_t read_uint32(const unsigned char *c, const int32_t pt) { ((uint32_t)c[pt + 2] << 16) | ((uint32_t)c[pt + 3] << 24); } -uint16_t read_uint16(const unsigned char *c, const int32_t pt) { - return ((uint16_t)c[pt]) | ((uint16_t)c[pt + 1] << 8); +void write_uint32(unsigned char *buf, uint32_t ui) { + buf[0] = ui; + buf[1] = ui >> 8; + buf[2] = ui >> 16; + buf[3] = ui >> 24; } int32_t stlink_read_debug32(stlink_t *sl, uint32_t addr, uint32_t *data) { @@ -46,26 +53,26 @@ int32_t stlink_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data) { return sl->backend->write_debug32(sl, addr, data); } -int32_t stlink_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { - DLOG("*** stlink_write_mem32 %u bytes to %#x\n", len, addr); +int32_t stlink_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { + DLOG("*** stlink_read_mem32 ***\n"); - if (len % 4 != 0) { + if (len % 4 != 0) { // !!! never ever: fw gives just wrong values ELOG("Data length doesn't have a 32 bit alignment: +%d byte.\n", len % 4); return (-1); } - return (sl->backend->write_mem32(sl, addr, len)); + return (sl->backend->read_mem32(sl, addr, len)); } -int32_t stlink_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { - DLOG("*** stlink_read_mem32 ***\n"); +int32_t stlink_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { + DLOG("*** stlink_write_mem32 %u bytes to %#x\n", len, addr); - if (len % 4 != 0) { // !!! never ever: fw gives just wrong values + if (len % 4 != 0) { ELOG("Data length doesn't have a 32 bit alignment: +%d byte.\n", len % 4); return (-1); } - return (sl->backend->read_mem32(sl, addr, len)); + return (sl->backend->write_mem32(sl, addr, len)); } int32_t stlink_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len) { @@ -73,21 +80,6 @@ int32_t stlink_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len) { return (sl->backend->write_mem8(sl, addr, len)); } -int32_t stlink_read_all_regs(stlink_t *sl, struct stlink_reg *regp) { - DLOG("*** stlink_read_all_regs ***\n"); - return (sl->backend->read_all_regs(sl, regp)); -} - -int32_t stlink_read_all_unsupported_regs(stlink_t *sl, struct stlink_reg *regp) { - DLOG("*** stlink_read_all_unsupported_regs ***\n"); - return (sl->backend->read_all_unsupported_regs(sl, regp)); -} - -int32_t stlink_write_reg(stlink_t *sl, uint32_t reg, int32_t idx) { - DLOG("*** stlink_write_reg\n"); - return (sl->backend->write_reg(sl, reg, idx)); -} - int32_t stlink_read_reg(stlink_t *sl, int32_t r_idx, struct stlink_reg *regp) { DLOG("*** stlink_read_reg\n"); DLOG(" (%d) ***\n", r_idx); @@ -100,6 +92,11 @@ int32_t stlink_read_reg(stlink_t *sl, int32_t r_idx, struct stlink_reg *regp) { return (sl->backend->read_reg(sl, r_idx, regp)); } +int32_t stlink_write_reg(stlink_t *sl, uint32_t reg, int32_t idx) { + DLOG("*** stlink_write_reg\n"); + return (sl->backend->write_reg(sl, reg, idx)); +} + int32_t stlink_read_unsupported_reg(stlink_t *sl, int32_t r_idx, struct stlink_reg *regp) { int32_t r_convert; @@ -145,3 +142,13 @@ int32_t stlink_write_unsupported_reg(stlink_t *sl, uint32_t val, int32_t r_idx, return (sl->backend->write_unsupported_reg(sl, val, r_convert, regp)); } + +int32_t stlink_read_all_regs(stlink_t *sl, struct stlink_reg *regp) { + DLOG("*** stlink_read_all_regs ***\n"); + return (sl->backend->read_all_regs(sl, regp)); +} + +int32_t stlink_read_all_unsupported_regs(stlink_t *sl, struct stlink_reg *regp) { + DLOG("*** stlink_read_all_unsupported_regs ***\n"); + return (sl->backend->read_all_unsupported_regs(sl, regp)); +} diff --git a/src/stlink-lib/read_write.h b/src/stlink-lib/read_write.h new file mode 100644 index 000000000..b9ca082c8 --- /dev/null +++ b/src/stlink-lib/read_write.h @@ -0,0 +1,27 @@ +/* + * File: read_write.h + * + * Read and write operations + */ + +#ifndef READ_WRITE_H +#define READ_WRITE_H + +uint16_t read_uint16(const unsigned char *c, const int32_t pt); +void write_uint16(unsigned char *buf, uint16_t ui); +uint32_t read_uint32(const unsigned char *c, const int32_t pt); +void write_uint32(unsigned char *buf, uint32_t ui); + +int32_t stlink_read_debug32(stlink_t *sl, uint32_t addr, uint32_t *data); +int32_t stlink_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data); +int32_t stlink_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len); +int32_t stlink_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len); +int32_t stlink_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len); +int32_t stlink_read_reg(stlink_t *sl, int32_t r_idx, struct stlink_reg *regp); +int32_t stlink_write_reg(stlink_t *sl, uint32_t reg, int32_t idx); +int32_t stlink_read_unsupported_reg(stlink_t *sl, int32_t r_idx, struct stlink_reg *regp); +int32_t stlink_write_unsupported_reg(stlink_t *sl, uint32_t value, int32_t r_idx, struct stlink_reg *regp); +int32_t stlink_read_all_regs(stlink_t *sl, struct stlink_reg *regp); +int32_t stlink_read_all_unsupported_regs(stlink_t *sl, struct stlink_reg *regp); + +#endif // READ_WRITE_H diff --git a/src/stlink-lib/sg.c b/src/stlink-lib/sg.c index b744389ba..d9bd8ab6a 100644 --- a/src/stlink-lib/sg.c +++ b/src/stlink-lib/sg.c @@ -95,6 +95,7 @@ #include "commands.h" #include "logging.h" +#include "read_write.h" #include "register.h" #include "usb.h" // #include // TODO: Check use diff --git a/src/stlink-lib/usb.c b/src/stlink-lib/usb.c index 0934fe368..30134e161 100644 --- a/src/stlink-lib/usb.c +++ b/src/stlink-lib/usb.c @@ -27,6 +27,7 @@ #include "commands.h" #include "logging.h" +#include "read_write.h" #include "register.h" static inline uint32_t le_to_h_u32(const uint8_t* buf) { diff --git a/tests/sg.c b/tests/sg.c index 67d804b23..1284bb15b 100644 --- a/tests/sg.c +++ b/tests/sg.c @@ -8,6 +8,7 @@ #include #include +#include #include #if defined(_MSC_VER) diff --git a/tests/usb.c b/tests/usb.c index 5dbb1d83c..f8b60c306 100644 --- a/tests/usb.c +++ b/tests/usb.c @@ -6,6 +6,7 @@ #include +#include #include #include From 2f27e8ec98db7dcba9437aae3c6e33e90ca3b674 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Tue, 27 Jun 2023 08:24:09 +0200 Subject: [PATCH 459/503] Fixed chip recovery after reset (Closes #1260) --- src/st-flash/flash.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/src/st-flash/flash.c b/src/st-flash/flash.c index ba6d1f4bb..0577ee179 100644 --- a/src/st-flash/flash.c +++ b/src/st-flash/flash.c @@ -287,10 +287,9 @@ int32_t main(int32_t ac, char** av) { } } - if (o.reset) { - stlink_reset(sl, RESET_AUTO); - stlink_run(sl, RUN_NORMAL); - } + if (o.reset) stlink_reset(sl, RESET_AUTO); + + stlink_run(sl, RUN_NORMAL); err = 0; // success From 457d971a40e8882765baaea1fa4015489825b09f Mon Sep 17 00:00:00 2001 From: Meo Date: Mon, 3 Jul 2023 09:59:26 +0800 Subject: [PATCH 460/503] Update README.md --- README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README.md b/README.md index 6d188f0df..80d39a28a 100644 --- a/README.md +++ b/README.md @@ -74,7 +74,7 @@ We recommend to install `stlink-tools` from the package repository of the used d - Debian Linux: [(Link)](https://github.com/stlink-org/stlink/releases) - Ubuntu Linux: [(Link)](https://github.com/stlink-org/stlink/releases) -- Arch Linux: [(Link)](https://www.archlinux.org/packages/community/x86_64/stlink) +- Arch Linux: [(Link)](https://archlinux.org/packages/extra/x86_64/stlink/) - Alpine Linux: [(Link)](https://pkgs.alpinelinux.org/packages?name=stlink) - Fedora: [(Link)](https://src.fedoraproject.org/rpms/stlink) - FreeBSD: Users can install from [freshports](https://www.freshports.org/devel/stlink) From 682ec389b720f164c42aafe1b0d7614abc29a12f Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 9 Jul 2023 00:38:49 +0200 Subject: [PATCH 461/503] [doc] Corrected compiling manual (Closes #1317) --- doc/compiling.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/doc/compiling.md b/doc/compiling.md index 775d2363e..45cf38aa1 100644 --- a/doc/compiling.md +++ b/doc/compiling.md @@ -125,7 +125,7 @@ or execute (Debian-based systems only): `apt-get install gcc build-essential cma 4. Run `make install` to full install the package with complete system integration. This might require sudo permissions. 5. Run `make debug` to create the _Debug_ target (_optional_)
The debug target is only necessary in order to modify the sources and to run under a debugger. -6. Run `make package`to build a Debian Package. The generated packages can be found in the subdirectory `./build/dist`. +6. Run `make package`to build a Debian Package. The generated packages can be found in the subdirectory `./build/Release/dist`. As an option you may also install to an individual user-defined folder e.g `$HOME` with `make install DESTDIR=$HOME`. From 4b69bdd3e95f7077991d198550aaa76405e54ce4 Mon Sep 17 00:00:00 2001 From: Martin Mares Date: Tue, 15 Aug 2023 10:44:18 +0200 Subject: [PATCH 462/503] CMake: Avoid hard-wired /usr/local/share Instead of defining own CMAKE_INSTALL_SHAREDIR, use existing CMAKE_INSTALL_FULL_DATADIR. This way, CMAKE_INSTALL_PREFIX is respected. --- CMakeLists.txt | 5 +---- src/stlink-gui/CMakeLists.txt | 8 ++++---- 2 files changed, 5 insertions(+), 8 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index 7e7d92705..31825945f 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -78,9 +78,6 @@ include(GNUInstallDirs) # Define GNU standard installation directories cmake_host_system_information(RESULT OS_NAME QUERY OS_NAME) message(STATUS "Checking for OS_NAME: ${OS_NAME}") -message(STATUS "set(CMAKE_INSTALL_SHAREDIR /usr/local/share)") -set(CMAKE_INSTALL_SHAREDIR /usr/local/share/) - ## Set C build flags if (NOT MSVC) @@ -385,7 +382,7 @@ endif () if (WIN32) set(CMAKE_CHIPS_DIR ${CMAKE_INSTALL_PREFIX}/config/chips) else () -set(CMAKE_CHIPS_DIR ${CMAKE_INSTALL_SHAREDIR}/${PROJECT_NAME}/chips) +set(CMAKE_CHIPS_DIR ${CMAKE_INSTALL_FULL_DATADIR}/${PROJECT_NAME}/chips) endif () add_definitions( -DSTLINK_CHIPS_DIR="${CMAKE_CHIPS_DIR}" ) file(GLOB CHIP_FILES ${CMAKE_SOURCE_DIR}/config/chips/*.chip) diff --git a/src/stlink-gui/CMakeLists.txt b/src/stlink-gui/CMakeLists.txt index fb4478bdc..f9b6c3fb9 100644 --- a/src/stlink-gui/CMakeLists.txt +++ b/src/stlink-gui/CMakeLists.txt @@ -16,19 +16,19 @@ if (NOT WIN32 AND NOT CMAKE_CROSSCOMPILING) # Install desktop application entry install(FILES stlink-gui.desktop - DESTINATION ${CMAKE_INSTALL_SHAREDIR}/applications) + DESTINATION ${CMAKE_INSTALL_FULL_DATADIR}/applications) # Install icons install(FILES icons/stlink-gui.svg - DESTINATION ${CMAKE_INSTALL_SHAREDIR}/icons/hicolor/scalable/apps) + DESTINATION ${CMAKE_INSTALL_FULL_DATADIR}/icons/hicolor/scalable/apps) set(GUI_SOURCES gui.c gui.h) ## stlink-gui add_executable(stlink-gui ${GUI_SOURCES}) - install(FILES stlink-gui.ui DESTINATION ${CMAKE_INSTALL_SHAREDIR}/${PROJECT_NAME}) + install(FILES stlink-gui.ui DESTINATION ${CMAKE_INSTALL_FULL_DATADIR}/${PROJECT_NAME}) set_target_properties(stlink-gui PROPERTIES - COMPILE_DEFINITIONS STLINK_UI_DIR="${CMAKE_INSTALL_SHAREDIR}/${PROJECT_NAME}") + COMPILE_DEFINITIONS STLINK_UI_DIR="${CMAKE_INSTALL_FULL_DATADIR}/${PROJECT_NAME}") target_link_libraries(stlink-gui ${STLINK_LIB_SHARED} ${SSP_LIB} ${GTK3_LDFLAGS}) install(TARGETS stlink-gui DESTINATION ${CMAKE_BINDIR}) endif () From 270efb3535a968ec639dfe5d20bb69462ab71fd6 Mon Sep 17 00:00:00 2001 From: ArmoredPony Date: Wed, 16 Aug 2023 18:05:37 +0400 Subject: [PATCH 463/503] fixed unknown option -u --- src/st-util/gdb-server.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/st-util/gdb-server.c b/src/st-util/gdb-server.c index 9f9d93844..629eb4c6f 100644 --- a/src/st-util/gdb-server.c +++ b/src/st-util/gdb-server.c @@ -149,7 +149,7 @@ int32_t parse_options(int32_t argc, char** argv, st_state_t *st) { int32_t c; int32_t q; - while ((c = getopt_long(argc, argv, "hv::p:mn", long_options, &option_index)) != -1) + while ((c = getopt_long(argc, argv, "hv::p:mnu", long_options, &option_index)) != -1) switch (c) { case 0: break; From 2e6cf7d806cf8ec0a88c88119e5d69bf4f67e564 Mon Sep 17 00:00:00 2001 From: andrew Date: Sun, 27 Aug 2023 01:45:57 -0700 Subject: [PATCH 464/503] Fix use of uninitialized flash_loader_t in stm32l1_write_half_pages stm32l1_write_half_pages uses a local flash_loader_t that is never initialized. This results in stlink_flash_loader_run using uninitialized values for fl->buf_addr and fl->loader_addr when copying the buffer and initializing the source register and PC before running the core to execute the flashloader. Pass the flash_loader_t from stlink_flashloader_write through to stm32l1_write_half_pages and use that one instead of an uninitialized local structure. --- src/stlink-lib/flash_loader.c | 7 +++---- src/stlink-lib/flash_loader.h | 2 +- 2 files changed, 4 insertions(+), 5 deletions(-) diff --git a/src/stlink-lib/flash_loader.c b/src/stlink-lib/flash_loader.c index 0ab8cf6c1..94a0dc41f 100644 --- a/src/stlink-lib/flash_loader.c +++ b/src/stlink-lib/flash_loader.c @@ -428,12 +428,11 @@ int32_t stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t t #define L1_WRITE_BLOCK_SIZE 0x80 #define L0_WRITE_BLOCK_SIZE 0x40 -int32_t stm32l1_write_half_pages(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint32_t len, uint32_t pagesize) { +int32_t stm32l1_write_half_pages(stlink_t *sl, flash_loader_t *fl, stm32_addr_t addr, uint8_t *base, uint32_t len, uint32_t pagesize) { uint32_t count, off; uint32_t num_half_pages = len / pagesize; uint32_t val; uint32_t flash_regs_base = get_stm32l0_flash_base(sl); - flash_loader_t fl; bool use_loader = true; int32_t ret = 0; @@ -448,7 +447,7 @@ int32_t stm32l1_write_half_pages(stlink_t *sl, stm32_addr_t addr, uint8_t *base, for (count = 0; count < num_half_pages; count++) { if (use_loader) { - ret = stlink_flash_loader_run(sl, &fl, addr + count * pagesize, base + count * pagesize, pagesize); + ret = stlink_flash_loader_run(sl, fl, addr + count * pagesize, base + count * pagesize, pagesize); if (ret && count == 0) { /* It seems that stm32lx devices have a problem when it is blank */ WLOG("Failed to use flash loader, fallback to soft write\n"); @@ -770,7 +769,7 @@ int32_t stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t off = 0; if (len > pagesize) { - if (stm32l1_write_half_pages(sl, addr, base, len, pagesize)) { + if (stm32l1_write_half_pages(sl, fl, addr, base, len, pagesize)) { return (-1); } else { off = (size_t)(len / pagesize) * pagesize; diff --git a/src/stlink-lib/flash_loader.h b/src/stlink-lib/flash_loader.h index 33edc7ac6..6ac2e4f80 100644 --- a/src/stlink-lib/flash_loader.h +++ b/src/stlink-lib/flash_loader.h @@ -18,7 +18,7 @@ int32_t stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t t /* === Functions from old header file flashloader.h === */ -int32_t stm32l1_write_half_pages(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint32_t len, uint32_t pagesize); +int32_t stm32l1_write_half_pages(stlink_t *sl, flash_loader_t *fl, stm32_addr_t addr, uint8_t *base, uint32_t len, uint32_t pagesize); // static void set_flash_cr_pg(stlink_t *sl, uint32_t bank); // static void set_dma_state(stlink_t *sl, flash_loader_t *fl, int32_t bckpRstr); int32_t stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl); From 1861b8dc9f7e70f4034bddabfe3b1e112dcd483f Mon Sep 17 00:00:00 2001 From: andrew Date: Sun, 27 Aug 2023 11:01:45 -0700 Subject: [PATCH 465/503] Fix stm32lx flash loader on STM32L0 STM32L0 chips use loader_code_stm32lx, but this flash loader is built for armv7-m and uses instructions that are unsupported on STM32L0 (which have Cortex M0+ cores implementing armv6-m). In particular, loader_code_stm32lx uses variants of add-immediate that do not update the condition flags ( `add r0, r0, #4` ). These are 32bit instructions in armv7-m and are not available in armv6-m. Enable loader_code_stm32lx to run on both armv6-m and armv7-m by building for armv6-m, which requires changing the `add` instructions to `adds` instructions that do update condition flags (which is ok because the subs updates the condition flags again before the branch). --- flashloaders/Makefile | 5 +++++ flashloaders/stm32lx.s | 4 ++-- src/stlink-lib/flash_loader.c | 8 ++++---- 3 files changed, 11 insertions(+), 6 deletions(-) diff --git a/flashloaders/Makefile b/flashloaders/Makefile index 68ce5a881..73080c644 100644 --- a/flashloaders/Makefile +++ b/flashloaders/Makefile @@ -30,6 +30,11 @@ stm32f0.o: stm32f0.s stm32vl.o: stm32f0.s $(CC) stm32f0.s $(CFLAGS_ARMV7_M) -o stm32vl.o +# separate rule for STM32Lx. +# Built for ARMv6-M target to be compatible with both Cortex M0 and Cortex M3. +stm32lx.o: stm32lx.s + $(CC) stm32lx.s $(CFLAGS_ARMV6_M) -o stm32lx.o + # generic rule for all other ARMv7-M %.o: %.s $(CC) $< $(CFLAGS_ARMV7_M) -o $@ diff --git a/flashloaders/stm32lx.s b/flashloaders/stm32lx.s index 69acdea7b..263f1f829 100644 --- a/flashloaders/stm32lx.s +++ b/flashloaders/stm32lx.s @@ -17,8 +17,8 @@ loop: str r4, [r1] # increment address - add r0, r0, #4 - add r1, r1, #4 + adds r0, r0, #4 + adds r1, r1, #4 # loop if count > 0 subs r2, r2, #4 diff --git a/src/stlink-lib/flash_loader.c b/src/stlink-lib/flash_loader.c index 94a0dc41f..040a7ab09 100644 --- a/src/stlink-lib/flash_loader.c +++ b/src/stlink-lib/flash_loader.c @@ -68,12 +68,12 @@ static const uint8_t loader_code_stm32f0[] = { 0x14, 0x00, 0x00, 0x00 }; -// flashloaders/stm32lx.s +// flashloaders/stm32lx.s -- compiled for armv6-m for compatibility with both +// armv6-m cores (STM32L0) and armv7-m cores (STM32L1) static const uint8_t loader_code_stm32lx[] = { 0x04, 0x68, 0x0c, 0x60, - 0x00, 0xf1, 0x04, 0x00, - 0x01, 0xf1, 0x04, 0x01, - 0x04, 0x3a, 0xf7, 0xdc, + 0x04, 0x30, 0x04, 0x31, + 0x04, 0x3a, 0xf9, 0xdc, 0x00, 0xbe, 0x00, 0x00 }; From 7475ec7f30edcff72b7c38cc221b29aaefe93220 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sat, 2 Sep 2023 17:18:09 +0200 Subject: [PATCH 466/503] General Project Update - Updated CHANGELOG.md - Updated README.md - Minor fixes & updates in documentation. --- CHANGELOG.md | 9 ++- README.md | 7 ++- SECURITY.md | 2 +- doc/compiling.md | 2 + flashloaders/cleanroom.md | 125 ++------------------------------------ 5 files changed, 22 insertions(+), 123 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index c930999cd..9b6cccdf9 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -37,6 +37,7 @@ Updates & changes: - [refactoring] General maintenance for code structure ([#903](https://github.com/stlink-org/stlink/pull/903), [#1090](https://github.com/stlink-org/stlink/pull/1090), [#1199](https://github.com/stlink-org/stlink/pull/1199), [#1212](https://github.com/stlink-org/stlink/pull/1212), [#1216](https://github.com/stlink-org/stlink/pull/1216), [#1228](https://github.com/stlink-org/stlink/pull/1228)) - Added instructions for bug-reports and feature-requests to contribution guidelines ([#906](https://github.com/stlink-org/stlink/pull/906)) - Added travis CI configuration for macOS 10.14 to maintain capability for 32-bit compilation (commit [#f5ada94](https://github.com/stlink-org/stlink/commit/f5ada9474cdb87ff37de0d4eb9e75622b5870646)) +- [refactoring] Clean code with unified variable type ([#909](https://github.com/stlink-org/stlink/pull/909), commit [#5e85fd0](https://github.com/stlink-org/stlink/commit/5e85fd063908f89499180c28fe5e9ba74868b272)) - Updated description of chip id 0x0457 to L01x/L02x ([#1143](https://github.com/stlink-org/stlink/pull/1143), [#1144](https://github.com/stlink-org/stlink/pull/1144)) - [doc] Human-readable flash_type in chip-id files ([#1155](https://github.com/stlink-org/stlink/pull/1155), commit [#1745bf5](https://github.com/stlink-org/stlink/commit/1745bf5193c4d3186d4f6fde59cc86e9bad6e61b)) - Dropped execute bits from source code files ([#1167](https://github.com/stlink-org/stlink/pull/1167)) @@ -51,9 +52,13 @@ Updates & changes: - [doc] Linux Install from code Documentation improvement ([#1263](https://github.com/stlink-org/stlink/pull/1263), commit [#43498de](https://github.com/stlink-org/stlink/commit/43498dedf651260ef34197e512d35e3ad7142401)) - End of support for macOS ([#1269](https://github.com/stlink-org/stlink/pull/1269), [#1296](https://github.com/stlink-org/stlink/pull/1296), commit [#61ff09e](https://github.com/stlink-org/stlink/commit/61ff09e5274d46a46ae58bc4ffe44fe90a887ea6)) - [doc] Added device ID for GD32F303VET6 ([#1288](https://github.com/stlink-org/stlink/pull/1288)) +- [doc] Fixed broken links ([#1312](https://github.com/stlink-org/stlink/pull/1312)) +- [doc] Updated package source link for Arch Linux ([#1318](https://github.com/stlink-org/stlink/pull/1318)) +- CMake: Avoid hard-wired /usr/local/share ([#1325](https://github.com/stlink-org/stlink/pull/1325)) Fixes: +- Fixed some flashing issues on STM32L0 ([#681](https://github.com/stlink-org/stlink/pull/681), [#1203](https://github.com/stlink-org/stlink/pull/1203), [#1225](https://github.com/stlink-org/stlink/pull/1225), [#1253](https://github.com/stlink-org/stlink/pull/1253), [#1289](https://github.com/stlink-org/stlink/pull/1289), [#1330](https://github.com/stlink-org/stlink/pull/1330)) - cmake: Install shared libraries in proper directories ([#1098](https://github.com/stlink-org/stlink/pull/1098), [#1138](https://github.com/stlink-org/stlink/pull/1138), [#1154](https://github.com/stlink-org/stlink/pull/1154)) - cmake: Install shared libraries in proper directories ([#1142](https://github.com/stlink-org/stlink/pull/1142)) - Fixed clearance of the H7 dual bank flag ([#1146](https://github.com/stlink-org/stlink/pull/1146), [#1147](https://github.com/stlink-org/stlink/pull/1147)) @@ -84,9 +89,11 @@ Fixes: - Fixed st-trace reconnect on Windows ([#1272](https://github.com/stlink-org/stlink/pull/1272), [#1292](https://github.com/stlink-org/stlink/pull/1292)) - [compilation] Corrected path to stlink/chips subdirectory ([#1276](https://github.com/stlink-org/stlink/pull/1276), [#1279](https://github.com/stlink-org/stlink/pull/1279)) - [compilation] Fixed GUI compilation failure on OpenBSD i386 ([#1284](https://github.com/stlink-org/stlink/pull/1284)) +- [STM32U5x5]: Last bytes are not written (flashed) when len()%16 <= 8 ([#1303](https://github.com/stlink-org/stlink/pull/1303), [#1315](https://github.com/stlink-org/stlink/pull/1315)) - Fixed unbounded write and check return values of sscanf ([#1306](https://github.com/stlink-org/stlink/pull/1306)) - Added null check for return value of stlink_chipid_get_params() ([#1307](https://github.com/stlink-org/stlink/pull/1307)) - Fixed warning in a few *.cmake files ([#1309](https://github.com/stlink-org/stlink/pull/1309)) +- Notification "unknown option -- u" in tool st-util ([#1326](https://github.com/stlink-org/stlink/pull/1326), [#1327](https://github.com/stlink-org/stlink/pull/1327)) # v1.7.0 @@ -98,7 +105,7 @@ Features: - Extended set of cmd line arguments for st-info and st-util ([#332](https://github.com/stlink-org/stlink/pull/332), [#990](https://github.com/stlink-org/stlink/pull/990), [#1091](https://github.com/stlink-org/stlink/pull/1091), [#1114](https://github.com/stlink-org/stlink/pull/1114)) - Extended support for STM32H7 & rework of software reset ([#532](https://github.com/stlink-org/stlink/pull/532), [#801](https://github.com/stlink-org/stlink/pull/801), [#868](https://github.com/stlink-org/stlink/pull/868), [#1008](https://github.com/stlink-org/stlink/pull/1008), [#1059](https://github.com/stlink-org/stlink/pull/1059), [#1063](https://github.com/stlink-org/stlink/pull/1063), [#1071](https://github.com/stlink-org/stlink/pull/1071)) -- Added support for STM32H742/743/753 ([#671](https://github.com/stlink-org/stlink/pull/671), [#793](https://github.com/stlink-org/stlink/pull/793), [#823](https://github.com/stlink-org/stlink/pull/823), [#998](https://github.com/stlink-org/stlink/pull/998), [#1052](https://github.com/stlink-org/stlink/pull/1052), [#1184](https://github.com/stlink-org/stlink/pull/1184)) +- Added support for STM32H742/743/753 ([#671](https://github.com/stlink-org/stlink/pull/671), [#793](https://github.com/stlink-org/stlink/pull/793), [#823](https://github.com/stlink-org/stlink/pull/823), [#998](https://github.com/stlink-org/stlink/pull/998), [#1052](https://github.com/stlink-org/stlink/pull/1052), [#1184](https://github.com/stlink-org/stlink/pull/1184), [#1324](https://github.com/stlink-org/stlink/pull/1324)) - Official support for STLINK-V3 programmers (commit [#5e0a502](https://github.com/stlink-org/stlink/commit/5e0a502df812495bfa96fa9116a19f1306152b17), [#820](https://github.com/stlink-org/stlink/pull/820), [#1022](https://github.com/stlink-org/stlink/pull/1022), [#1025](https://github.com/stlink-org/stlink/pull/1025)) - Added preliminary support for STM32L5x2 ([#904](https://github.com/stlink-org/stlink/pull/904), [#999](https://github.com/stlink-org/stlink/pull/999)) - Option bytes on the STM32F767 ZIT6 Nucleo-144 ([#968](https://github.com/stlink-org/stlink/pull/968), [#997](https://github.com/stlink-org/stlink/pull/997)) diff --git a/README.md b/README.md index 6d188f0df..05f87658d 100644 --- a/README.md +++ b/README.md @@ -78,7 +78,12 @@ We recommend to install `stlink-tools` from the package repository of the used d - Alpine Linux: [(Link)](https://pkgs.alpinelinux.org/packages?name=stlink) - Fedora: [(Link)](https://src.fedoraproject.org/rpms/stlink) - FreeBSD: Users can install from [freshports](https://www.freshports.org/devel/stlink) -- MacOS: **Support for macOS will end with v1.8.0.** Please use v1.7.0 (current ***master*** branch) and the related documentation instead. + +**macOS**: + +**Support for macOS will be dropped with v1.8.0.** + +Please use v1.7.0 instead, **but note that this version is no longer maintained and supported!** ## Installation from source (advanced users) diff --git a/SECURITY.md b/SECURITY.md index 054641822..13432b927 100644 --- a/SECURITY.md +++ b/SECURITY.md @@ -7,7 +7,7 @@ The following versions of the stlink toolset are currently being supported.
Date: Mon, 4 Sep 2023 16:21:55 +0200 Subject: [PATCH 467/503] Prefix all CDB bytes with 0x, including zeros --- src/stlink-lib/sg.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/stlink-lib/sg.c b/src/stlink-lib/sg.c index d7f844b51..c0e43547b 100644 --- a/src/stlink-lib/sg.c +++ b/src/stlink-lib/sg.c @@ -171,7 +171,7 @@ static int32_t dump_CDB_command(uint8_t *cdb, uint8_t cdb_len) { dbugp += sprintf(dbugp, "Sending CDB ["); for (uint8_t i = 0; i < cdb_len; i++) { - dbugp += sprintf(dbugp, " %#02x", (uint32_t)cdb[i]); + dbugp += sprintf(dbugp, " 0x%02x", (uint32_t)cdb[i]); } sprintf(dbugp, "]\n"); From a0c02161085401ecfce3dfcfd9c7ee63931a6b05 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Thu, 14 Sep 2023 11:35:35 +0200 Subject: [PATCH 468/503] Updated behaviour on Reset Fixes an issue where early breakpoints did not trigger. (Closes #1198) (Closes #1246) (Closes #1319) --- src/st-util/gdb-server.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/st-util/gdb-server.c b/src/st-util/gdb-server.c index a0bc3f0a1..71f24fb60 100644 --- a/src/st-util/gdb-server.c +++ b/src/st-util/gdb-server.c @@ -1318,7 +1318,7 @@ int32_t serve(stlink_t *sl, st_state_t *st) { reply = strdup("E00"); } - ret = stlink_reset(sl, RESET_AUTO); + ret = stlink_reset(sl, RESET_SOFT_AND_HALT); if (ret) { DLOG("Rcmd: reset failed with reset\n"); reply = strdup("E00"); @@ -1835,7 +1835,7 @@ int32_t serve(stlink_t *sl, st_state_t *st) { case 'R': { // reset the core. - ret = stlink_reset(sl, RESET_AUTO); + ret = stlink_reset(sl, RESET_SOFT_AND_HALT); if (ret) { DLOG("R packet : stlink_reset failed\n"); } init_code_breakpoints(sl); From df7c7d21728f9804225c04912b45e34578b0d9ca Mon Sep 17 00:00:00 2001 From: Brian Date: Wed, 11 Oct 2023 19:55:50 -0400 Subject: [PATCH 469/503] Add CodeQL Workflow for Code Security Analysis Add CodeQL Workflow for Code Security Analysis This pull request introduces a CodeQL workflow to enhance the security analysis of our repository. CodeQL is a powerful static analysis tool that helps identify and mitigate security vulnerabilities in our codebase. By integrating this workflow into our GitHub Actions, we can proactively identify and address potential issues before they become security threats. We added a new CodeQL workflow file (.github/workflows/codeql.yml) that - Runs on every push and pull request to the main branch. - Excludes queries with a high false positive rate or low-severity findings. - Does not display results for third-party code, focusing only on our own codebase. Testing: To validate the functionality of this workflow, we have run several test scans on the codebase and reviewed the results. The workflow successfully compiles the project, identifies issues, and provides actionable insights while reducing noise by excluding certain queries and third-party code. Deployment: Once this pull request is merged, the CodeQL workflow will be active and automatically run on every push and pull request to the main branch. To view the results of these code scans, please follow these steps: 1. Under the repository name, click on the Security tab. 2. In the left sidebar, click Code scanning alerts. Additional Information: - You can further customize the workflow to adapt to your specific needs by modifying the workflow file. - For more information on CodeQL and how to interpret its results, refer to the GitHub documentation and the CodeQL documentation. Signed-off-by: Brian --- .github/workflows/codeql-buildscript.sh | 6 ++ .github/workflows/codeql.yml | 123 ++++++++++++++++++++++++ 2 files changed, 129 insertions(+) create mode 100644 .github/workflows/codeql-buildscript.sh create mode 100644 .github/workflows/codeql.yml diff --git a/.github/workflows/codeql-buildscript.sh b/.github/workflows/codeql-buildscript.sh new file mode 100644 index 000000000..d626d4283 --- /dev/null +++ b/.github/workflows/codeql-buildscript.sh @@ -0,0 +1,6 @@ +#!/usr/bin/env bash + +sudo apt-get -y update +sudo apt-get -y install libusb-1.0 libusb-1.0-0-dev libgtk-3-dev +make clean +make release -j$(nproc) diff --git a/.github/workflows/codeql.yml b/.github/workflows/codeql.yml new file mode 100644 index 000000000..eaa9599bd --- /dev/null +++ b/.github/workflows/codeql.yml @@ -0,0 +1,123 @@ +# For most projects, this workflow file will not need changing; you simply need +# to commit it to your repository. +# +# You may wish to alter this file to override the set of languages analyzed, +# or to provide custom queries or build logic. +# +# ******** NOTE ******** +# We have attempted to detect the languages in your repository. Please check +# the `language` matrix defined below to confirm you have the correct set of +# supported CodeQL languages. +# +name: "CodeQL" + +on: + push: + branches: [ "main", "master" ] + pull_request: + # The branches below must be a subset of the branches above + branches: [ "main", "master" ] + schedule: + - cron: '28 21 * * 0' + +jobs: + analyze: + name: Analyze + # Runner size impacts CodeQL analysis time. To learn more, please see: + # - https://gh.io/recommended-hardware-resources-for-running-codeql + # - https://gh.io/supported-runners-and-hardware-resources + # - https://gh.io/using-larger-runners + # Consider using larger runners for possible analysis time improvements. + runs-on: ${{ (matrix.language == 'swift' && 'macos-latest') || 'ubuntu-20.04' }} + timeout-minutes: ${{ (matrix.language == 'swift' && 120) || 360 }} + permissions: + actions: read + contents: read + security-events: write + + strategy: + fail-fast: false + matrix: + language: [ 'cpp' ] + # CodeQL supports [ 'cpp', 'csharp', 'go', 'java', 'javascript', 'python', 'ruby', 'swift' ] + # Use only 'java' to analyze code written in Java, Kotlin or both + # Use only 'javascript' to analyze code written in JavaScript, TypeScript or both + # Learn more about CodeQL language support at https://aka.ms/codeql-docs/language-support + + steps: + - name: Checkout repository + uses: actions/checkout@v3 + with: + submodules: recursive + + # Initializes the CodeQL tools for scanning. + - name: Initialize CodeQL + uses: github/codeql-action/init@v2 + with: + languages: ${{ matrix.language }} + # If you wish to specify custom queries, you can do so here or in a config file. + # By default, queries listed here will override any specified in a config file. + # Prefix the list here with "+" to use these queries and those in the config file. + + # For more details on CodeQL's query packs, refer to: https://docs.github.com/en/code-security/code-scanning/automatically-scanning-your-code-for-vulnerabilities-and-errors/configuring-code-scanning#using-queries-in-ql-packs + # queries: security-extended,security-and-quality + queries: security-and-quality + + + # Autobuild attempts to build any compiled languages (C/C++, C#, Go, Java, or Swift). + # If this step fails, then you should remove it and run the build manually (see below) + #- name: Autobuild + # uses: github/codeql-action/autobuild@v2 + + # ℹ️ Command-line programs to run using the OS shell. + # 📚 See https://docs.github.com/en/actions/using-workflows/workflow-syntax-for-github-actions#jobsjob_idstepsrun + + # If the Autobuild fails above, remove it and uncomment the following three lines. + # modify them (or add more) to build your code if your project, please refer to the EXAMPLE below for guidance. + + - run: | + ./.github/workflows/codeql-buildscript.sh + + - name: Perform CodeQL Analysis + uses: github/codeql-action/analyze@v2 + with: + category: "/language:${{matrix.language}}" + upload: false + id: step1 + + # Filter out rules with low severity or high false positve rate + # Also filter out warnings in third-party code + - name: Filter out unwanted errors and warnings + uses: advanced-security/filter-sarif@v1 + with: + patterns: | + -**:cpp/path-injection + -**:cpp/world-writable-file-creation + -**:cpp/poorly-documented-function + -**:cpp/potentially-dangerous-function + -**:cpp/use-of-goto + -**:cpp/integer-multiplication-cast-to-long + -**:cpp/comparison-with-wider-type + -**:cpp/leap-year/* + -**:cpp/ambiguously-signed-bit-field + -**:cpp/suspicious-pointer-scaling + -**:cpp/suspicious-pointer-scaling-void + -**:cpp/unsigned-comparison-zero + -**/third*party/** + -**/3rd*party/** + -**/external/** + input: ${{ steps.step1.outputs.sarif-output }}/cpp.sarif + output: ${{ steps.step1.outputs.sarif-output }}/cpp.sarif + + - name: Upload SARIF + uses: github/codeql-action/upload-sarif@v2 + with: + sarif_file: ${{ steps.step1.outputs.sarif-output }} + category: "/language:${{matrix.language}}" + + - name: Archive CodeQL results + uses: actions/upload-artifact@v3 + with: + name: codeql-results + path: ${{ steps.step1.outputs.sarif-output }} + retention-days: 5 \ No newline at end of file From 3387ca5b425072b06c95831665ab9c9a63caf811 Mon Sep 17 00:00:00 2001 From: Daniele Cattaneo Date: Sat, 14 Oct 2023 17:48:17 +0200 Subject: [PATCH 470/503] Do not crash when the STLink chip returns a voltage factor of zero. --- src/stlink-lib/usb.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/src/stlink-lib/usb.c b/src/stlink-lib/usb.c index 30134e161..d3a57c33f 100644 --- a/src/stlink-lib/usb.c +++ b/src/stlink-lib/usb.c @@ -238,7 +238,13 @@ int32_t _stlink_usb_target_voltage(stlink_t *sl) { factor = (rdata[3] << 24) | (rdata[2] << 16) | (rdata[1] << 8) | (rdata[0] << 0); reading = (rdata[7] << 24) | (rdata[6] << 16) | (rdata[5] << 8) | (rdata[4] << 0); - voltage = 2400 * reading / factor; + DLOG("target voltage factor=%08x reading=%08x\n", factor, reading); + if (factor != 0 && reading != 0) { + voltage = 2400 * reading / factor; + } else { + DLOG("voltage reading failed at device side, bad STLink chip?\n"); + voltage = 0; + } return (voltage); } From ed8fa62d098ad52bafc78507146899b5738f01d8 Mon Sep 17 00:00:00 2001 From: Brian Date: Wed, 18 Oct 2023 16:49:46 -0400 Subject: [PATCH 471/503] Add CodeQL Workflow for Code Security Analysis Add CodeQL Workflow for Code Security Analysis This pull request introduces a CodeQL workflow to enhance the security analysis of our repository. CodeQL is a powerful static analysis tool that helps identify and mitigate security vulnerabilities in our codebase. By integrating this workflow into our GitHub Actions, we can proactively identify and address potential issues before they become security threats. We added a new CodeQL workflow file (.github/workflows/codeql.yml) that - Runs on every pull request (functionality to run on every push to main branches is included as a comment for convenience). - Runs daily. - Excludes queries with a high false positive rate or low-severity findings. - Does not display results for git submodules, focusing only on our own codebase. Testing: To validate the functionality of this workflow, we have run several test scans on the codebase and reviewed the results. The workflow successfully compiles the project, identifies issues, and provides actionable insights while reducing noise by excluding certain queries and third-party code. Deployment: Once this pull request is merged, the CodeQL workflow will be active and automatically run on every push and pull request to the main branch. To view the results of these code scans, please follow these steps: 1. Under the repository name, click on the Security tab. 2. In the left sidebar, click Code scanning alerts. Additional Information: - You can further customize the workflow to adapt to your specific needs by modifying the workflow file. - For more information on CodeQL and how to interpret its results, refer to the GitHub documentation and the CodeQL documentation (https://codeql.github.com/ and https://codeql.github.com/docs/). Signed-off-by: Brian --- .github/workflows/codeql.yml | 23 +++++++++++++---------- 1 file changed, 13 insertions(+), 10 deletions(-) diff --git a/.github/workflows/codeql.yml b/.github/workflows/codeql.yml index eaa9599bd..3ef873fc8 100644 --- a/.github/workflows/codeql.yml +++ b/.github/workflows/codeql.yml @@ -14,11 +14,10 @@ name: "CodeQL" on: push: branches: [ "main", "master" ] - pull_request: - # The branches below must be a subset of the branches above - branches: [ "main", "master" ] schedule: - - cron: '28 21 * * 0' + - cron: '0 0 * * *' + pull_request: + branches: '*' jobs: analyze: @@ -103,21 +102,25 @@ jobs: -**:cpp/suspicious-pointer-scaling -**:cpp/suspicious-pointer-scaling-void -**:cpp/unsigned-comparison-zero - -**/third*party/** - -**/3rd*party/** - -**/external/** + -**/cmake*/Modules/** input: ${{ steps.step1.outputs.sarif-output }}/cpp.sarif output: ${{ steps.step1.outputs.sarif-output }}/cpp.sarif - - name: Upload SARIF + - name: Upload CodeQL results to code scanning uses: github/codeql-action/upload-sarif@v2 with: sarif_file: ${{ steps.step1.outputs.sarif-output }} category: "/language:${{matrix.language}}" - - name: Archive CodeQL results + - name: Upload CodeQL results as an artifact + if: success() || failure() uses: actions/upload-artifact@v3 with: name: codeql-results path: ${{ steps.step1.outputs.sarif-output }} - retention-days: 5 \ No newline at end of file + retention-days: 5 + + - name: Fail if an error is found + run: | + ./.github/workflows/fail_on_error.py \ + ${{ steps.step1.outputs.sarif-output }}/cpp.sarif From b9a0a49a5423706433796605fb1511882603f635 Mon Sep 17 00:00:00 2001 From: Brian Date: Fri, 20 Oct 2023 01:02:15 -0400 Subject: [PATCH 472/503] Add CodeQL Workflow for Code Security Analysis Add CodeQL Workflow for Code Security Analysis This pull request introduces a CodeQL workflow to enhance the security analysis of our repository. CodeQL is a powerful static analysis tool that helps identify and mitigate security vulnerabilities in our codebase. By integrating this workflow into our GitHub Actions, we can proactively identify and address potential issues before they become security threats. We added a new CodeQL workflow file (.github/workflows/codeql.yml) that - Runs on every pull request (functionality to run on every push to main branches is included as a comment for convenience). - Runs daily. - Excludes queries with a high false positive rate or low-severity findings. - Does not display results for git submodules, focusing only on our own codebase. Testing: To validate the functionality of this workflow, we have run several test scans on the codebase and reviewed the results. The workflow successfully compiles the project, identifies issues, and provides actionable insights while reducing noise by excluding certain queries and third-party code. Deployment: Once this pull request is merged, the CodeQL workflow will be active and automatically run on every push and pull request to the main branch. To view the results of these code scans, please follow these steps: 1. Under the repository name, click on the Security tab. 2. In the left sidebar, click Code scanning alerts. Additional Information: - You can further customize the workflow to adapt to your specific needs by modifying the workflow file. - For more information on CodeQL and how to interpret its results, refer to the GitHub documentation and the CodeQL documentation (https://codeql.github.com/ and https://codeql.github.com/docs/). Signed-off-by: Brian --- .github/workflows/fail_on_error.py | 34 ++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) create mode 100755 .github/workflows/fail_on_error.py diff --git a/.github/workflows/fail_on_error.py b/.github/workflows/fail_on_error.py new file mode 100755 index 000000000..29791742b --- /dev/null +++ b/.github/workflows/fail_on_error.py @@ -0,0 +1,34 @@ +#!/usr/bin/env python3 + +import json +import sys + +# Return whether SARIF file contains error-level results +def codeql_sarif_contain_error(filename): + with open(filename, 'r') as f: + s = json.load(f) + + for run in s.get('runs', []): + rules_metadata = run['tool']['driver']['rules'] + if not rules_metadata: + rules_metadata = run['tool']['extensions'][0]['rules'] + + for res in run.get('results', []): + if 'ruleIndex' in res: + rule_index = res['ruleIndex'] + elif 'rule' in res and 'index' in res['rule']: + rule_index = res['rule']['index'] + else: + continue + try: + rule_level = rules_metadata[rule_index]['defaultConfiguration']['level'] + except IndexError as e: + print(e, rule_index, len(rules_metadata)) + else: + if rule_level == 'error': + return True + return False + +if __name__ == "__main__": + if codeql_sarif_contain_error(sys.argv[1]): + sys.exit(1) From abf354a1558215fe9909c5d2c4947dd9aa35eb6c Mon Sep 17 00:00:00 2001 From: Brian Date: Sun, 29 Oct 2023 15:28:16 -0400 Subject: [PATCH 473/503] Add CodeQL Workflow for Code Security Analysis Add CodeQL Workflow for Code Security Analysis This pull request introduces a CodeQL workflow to enhance the security analysis of our repository. CodeQL is a powerful static analysis tool that helps identify and mitigate security vulnerabilities in our codebase. By integrating this workflow into our GitHub Actions, we can proactively identify and address potential issues before they become security threats. We added a new CodeQL workflow file (.github/workflows/codeql.yml) that - Runs on every pull request (functionality to run on every push to main branches is included as a comment for convenience). - Runs daily. - Excludes queries with a high false positive rate or low-severity findings. - Does not display results for git submodules, focusing only on our own codebase. Testing: To validate the functionality of this workflow, we have run several test scans on the codebase and reviewed the results. The workflow successfully compiles the project, identifies issues, and provides actionable insights while reducing noise by excluding certain queries and third-party code. Deployment: Once this pull request is merged, the CodeQL workflow will be active and automatically run on every push and pull request to the main branch. To view the results of these code scans, please follow these steps: 1. Under the repository name, click on the Security tab. 2. In the left sidebar, click Code scanning alerts. Additional Information: - You can further customize the workflow to adapt to your specific needs by modifying the workflow file. - For more information on CodeQL and how to interpret its results, refer to the GitHub documentation and the CodeQL documentation (https://codeql.github.com/ and https://codeql.github.com/docs/). Signed-off-by: Brian --- .github/workflows/codeql.yml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/.github/workflows/codeql.yml b/.github/workflows/codeql.yml index 3ef873fc8..816492278 100644 --- a/.github/workflows/codeql.yml +++ b/.github/workflows/codeql.yml @@ -12,8 +12,8 @@ name: "CodeQL" on: - push: - branches: [ "main", "master" ] + # push: + # branches: [ "main", "master" ] schedule: - cron: '0 0 * * *' pull_request: From 2d21188cdce20cfdcf9126044a2368a6ccc8dfc0 Mon Sep 17 00:00:00 2001 From: Mirko Date: Wed, 8 Nov 2023 14:51:19 +0000 Subject: [PATCH 474/503] first commit --- config/chips/L45x_L46x.chip | 2 ++ config/chips/L496x_L4A6x.chip | 2 ++ src/st-flash/flash.c | 24 +++++++++++++++ src/st-flash/flash_opts.c | 18 +++++------- src/stlink-lib/chipid.c | 16 ++++++++-- src/stlink-lib/chipid.h | 2 ++ src/stlink-lib/common.c | 3 ++ src/stlink-lib/common_flash.c | 55 ++++++++++++++++++++++++++++++++++- src/stlink-lib/common_flash.h | 2 ++ 9 files changed, 111 insertions(+), 13 deletions(-) diff --git a/config/chips/L45x_L46x.chip b/config/chips/L45x_L46x.chip index cbe948c1f..1c8fc2e1f 100644 --- a/config/chips/L45x_L46x.chip +++ b/config/chips/L45x_L46x.chip @@ -12,3 +12,5 @@ bootrom_size 0x7000 // 28 KB option_base 0x0 option_size 0x0 flags swo +otp_base 0x1fff7000 +otp_size 0x400 // 1 KB \ No newline at end of file diff --git a/config/chips/L496x_L4A6x.chip b/config/chips/L496x_L4A6x.chip index 24788c092..8a4a93b1c 100644 --- a/config/chips/L496x_L4A6x.chip +++ b/config/chips/L496x_L4A6x.chip @@ -12,3 +12,5 @@ bootrom_size 0x7000 // 28 KB option_base 0x1fff7800 // STM32_L4_OPTION_BYTES_BASE option_size 0x4 // 4 B flags swo +otp_base 0x1fff7000 +otp_size 0x400 // 1 KB \ No newline at end of file diff --git a/src/st-flash/flash.c b/src/st-flash/flash.c index 0577ee179..6553298c3 100644 --- a/src/st-flash/flash.c +++ b/src/st-flash/flash.c @@ -61,6 +61,7 @@ static void usage(void) { puts("example write option control register1 byte: ./st-flash --area=optcr write 0xXXXXXXXX"); puts("example read option control register1 byte: ./st-flash --area=optcr1 read"); puts("example write option control register1 byte: ./st-flash --area=optcr1 write 0xXXXXXXXX"); + puts("example read OTP area: ./st-flash --area=otp read [path]"); } int32_t main(int32_t ac, char** av) { @@ -180,6 +181,18 @@ int32_t main(int32_t ac, char** av) { DLOG("@@@@ Write %d (%0#10x) to option bytes boot address\n", o.val, o.val); err = stlink_write_option_bytes_boot_add32(sl, o.val); + } else if (o.area == FLASH_OTP) { + if(sl->otp_base == 0) { + err = -1; + printf("OTP Write Not implimented\n"); + goto on_error; + } + err = stlink_fwrite_flash(sl, o.filename, o.addr); + + if (err == -1) { + printf("stlink_fwrite_flash() == -1\n"); + goto on_error; + } } else { err = -1; printf("Unknown memory region\n"); @@ -284,6 +297,17 @@ int32_t main(int32_t ac, char** av) { } else { printf("%08x\n",option_byte); } + } else if (o.area == FLASH_OTP) { + if(sl->otp_base == 0) { + err = -1; + printf("OTP Read not implimented\n"); + goto on_error; + } + err = stlink_fread(sl, o.filename, 0, sl->otp_base, sl->otp_size); + if (err == -1) { + printf("could not read OTP area (%d)\n", err); + goto on_error; + } } } diff --git a/src/st-flash/flash_opts.c b/src/st-flash/flash_opts.c index 300203a3f..cf80407d1 100644 --- a/src/st-flash/flash_opts.c +++ b/src/st-flash/flash_opts.c @@ -86,7 +86,6 @@ static int32_t bad_arg(const char *arg) { } int32_t flash_get_opts(struct flash_opts* o, int32_t ac, char** av) { - // defaults memset(o, 0, sizeof(*o)); o->log_level = STND_LOG_LEVEL; @@ -270,13 +269,13 @@ int32_t flash_get_opts(struct flash_opts* o, int32_t ac, char** av) { if (ac != 3) { return invalid_args("read "); } o->filename = av[0]; - uint32_t address; - result = get_integer_from_char_array(av[1], &address); - if (result != 0) { - return bad_arg ("addr"); - } else { - o->addr = (stm32_addr_t) address; - } + uint32_t address; + result = get_integer_from_char_array(av[1], &address); + if (result != 0) { + return bad_arg ("addr"); + } else { + o->addr = (stm32_addr_t) address; + } uint32_t size; result = get_integer_from_char_array(av[2], &size); @@ -288,8 +287,7 @@ int32_t flash_get_opts(struct flash_opts* o, int32_t ac, char** av) { break; } else if (o->area == FLASH_OTP) { - return bad_arg("TODO: otp not implemented yet"); - if (ac > 1) { return invalid_args("otp read: [path]"); } + if (ac > 1 || ac ==0 ) { return invalid_args("otp read: [path]"); } if (ac > 0) { o->filename = av[0]; } break; } else if (o->area == FLASH_OPTION_BYTES) { diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index 06edb26f3..1b6fc13f7 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -34,6 +34,7 @@ void dump_a_chip(struct stlink_chipid_params *dev) { DLOG("option_base 0x%x\n", dev->option_base); DLOG("option_size 0x%x\n", dev->option_size); DLOG("flags %d\n\n", dev->flags); + DLOG("otp_base %d\n\n", dev->otp_base); } struct stlink_chipid_params *stlink_chipid_get_params(uint32_t chip_id) { @@ -57,7 +58,6 @@ void process_chipfile(char *fname) { // fprintf (stderr, "processing chip-id file %s.\n", fname); fp = fopen(fname, "r"); - if (!fp) { perror(fname); return; @@ -180,8 +180,19 @@ void process_chipfile(char *fname) { fprintf(stderr, "Unknown flags word in %s: '%s'\n", fname, p); } } - sscanf(value, "%x", &ts->flags); + } else if (strcmp(word, "otp_base") == 0) { + buf[strlen(buf) - 1] = 0; // chomp newline + sscanf(buf, "%*s %n", &nc); + if (sscanf(value, "%i", &ts->otp_base) < 1) { + fprintf(stderr, "Failed to parse option size\n"); + } + } else if (strcmp(word, "otp_size") == 0) { + buf[strlen(buf) - 1] = 0; // chomp newline + sscanf(buf, "%*s %n", &nc); + if (sscanf(value, "%i", &ts->otp_size) < 1) { + fprintf(stderr, "Failed to parse option size\n"); + } } else { fprintf(stderr, "Unknown keyword in %s: %s\n", fname, word); } @@ -191,6 +202,7 @@ void process_chipfile(char *fname) { devicelist = ts; } + #if defined(STLINK_HAVE_DIRENT_H) #include diff --git a/src/stlink-lib/chipid.h b/src/stlink-lib/chipid.h index 6726a7420..cf97e6609 100644 --- a/src/stlink-lib/chipid.h +++ b/src/stlink-lib/chipid.h @@ -21,6 +21,8 @@ struct stlink_chipid_params { uint32_t option_base; uint32_t option_size; uint32_t flags; + uint32_t otp_base; + uint32_t otp_size; struct stlink_chipid_params *next; }; diff --git a/src/stlink-lib/common.c b/src/stlink-lib/common.c index dbfcc8b9e..c470f9095 100644 --- a/src/stlink-lib/common.c +++ b/src/stlink-lib/common.c @@ -290,6 +290,9 @@ int32_t stlink_load_device_params(stlink_t *sl) { sl->option_base = params->option_base; sl->option_size = params->option_size; sl->chip_flags = params->flags; + sl->otp_base = params->otp_base; + sl->otp_size = params->otp_size; + // medium and low devices have the same chipid. ram size depends on flash // size. STM32F100xx datasheet Doc ID 16455 Table 2 diff --git a/src/stlink-lib/common_flash.c b/src/stlink-lib/common_flash.c index 3038b53e7..60d8f42fb 100644 --- a/src/stlink-lib/common_flash.c +++ b/src/stlink-lib/common_flash.c @@ -1310,9 +1310,17 @@ int32_t stlink_fwrite_flash(stlink_t *sl, const char *path, stm32_addr_t addr) { * If the file is identified to be all-empty and four-bytes aligned, * still flash the whole file even if ignoring message is printed. */ - err = stlink_write_flash(sl, addr, mf.base, + + /* In case the address is within the OTP area we use a different flash method */ + if(addr >= sl->otp_base && addr <= sl->otp_base + sl->otp_size) { + err = stlink_write_otp(sl, addr, mf.base, + (num_empty == mf.len) ? (uint32_t)mf.len : (uint32_t)mf.len - num_empty); + } else { + err = stlink_write_flash(sl, addr, mf.base, (num_empty == mf.len) ? (uint32_t)mf.len : (uint32_t)mf.len - num_empty, num_empty == mf.len); + } + stlink_fwrite_finalize(sl, addr); unmap_file(&mf); return (err); @@ -1389,6 +1397,22 @@ int32_t stlink_check_address_range_validity(stlink_t *sl, stm32_addr_t addr, uin return 0; } +// Check if an address and size are within the flash (otp area) +int32_t stlink_check_address_range_validity_otp(stlink_t *sl, stm32_addr_t addr, uint32_t size) { + uint32_t logvar; + if (addr < sl->otp_base || addr >= (sl->otp_base + sl->otp_size)) { + logvar = sl->otp_base + sl->otp_size - 1; + ELOG("Invalid address, it should be within 0x%08x - 0x%08x\n", sl->otp_base, logvar); + return (-1); + } + if ((addr + size) > (sl->otp_base + sl->otp_size)) { + logvar = sl->otp_base + sl->otp_size - addr; + ELOG("The size exceeds the size of the OTP Area (0x%08x bytes available)\n", logvar); + return (-1); + } + return 0; +} + // Check if an address is aligned with the beginning of a page int32_t stlink_check_address_alignment(stlink_t *sl, stm32_addr_t addr) { stm32_addr_t page = sl->flash_base; @@ -1408,6 +1432,9 @@ int32_t stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint3 int32_t ret; flash_loader_t fl; ILOG("Attempting to write %d (%#x) bytes to stm32 address: %u (%#x)\n", len, len, addr, addr); + + (void)eraseonly; + // check addr range is inside the flash stlink_calculate_pagesize(sl, addr); @@ -1437,7 +1464,33 @@ int32_t stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint3 if (eraseonly) { return (0); } + + ret = stlink_flashloader_start(sl, &fl); + if (ret) + return ret; + ret = stlink_flashloader_write(sl, &fl, addr, base, len); + if (ret) + return ret; + ret = stlink_flashloader_stop(sl, &fl); + if (ret) + return ret; + + return (stlink_verify_write_flash(sl, addr, base, len)); +} + +int32_t stlink_write_otp(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint32_t len) { + int32_t ret; + flash_loader_t fl; + ILOG("Attempting to write %d (%#x) bytes to stm32 address: %u (%#x)\n", len, len, addr, addr); + + // Check the address and size validity + if (stlink_check_address_range_validity_otp(sl, addr, len) < 0) { + return (-1); + } + // make sure we've loaded the context with the chip details + stlink_core_id(sl); + ret = stlink_flashloader_start(sl, &fl); if (ret) return ret; diff --git a/src/stlink-lib/common_flash.h b/src/stlink-lib/common_flash.h index 9b2b84057..238f0403e 100644 --- a/src/stlink-lib/common_flash.h +++ b/src/stlink-lib/common_flash.h @@ -44,8 +44,10 @@ int32_t stlink_fwrite_flash(stlink_t *sl, const char *path, stm32_addr_t addr); int32_t stlink_fcheck_flash(stlink_t *sl, const char *path, stm32_addr_t addr); int32_t stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, uint32_t length); int32_t stlink_check_address_range_validity(stlink_t *sl, stm32_addr_t addr, uint32_t size); +int32_t stlink_check_address_range_validity_otp(stlink_t *sl, stm32_addr_t addr, uint32_t size); int32_t stlink_check_address_alignment(stlink_t *sl, stm32_addr_t addr); int32_t stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint32_t len, uint8_t eraseonly); +int32_t stlink_write_otp(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint32_t len); void stlink_fwrite_finalize(stlink_t *, stm32_addr_t); #endif // COMMON_FLASH_H From b1d99a2fc22af6935f714525641a01483c076b3c Mon Sep 17 00:00:00 2001 From: Mirko Date: Wed, 8 Nov 2023 15:04:10 +0000 Subject: [PATCH 475/503] cleaning ident --- config/chips/L45x_L46x.chip | 2 +- config/chips/L496x_L4A6x.chip | 2 +- src/st-flash/flash.c | 4 ++-- src/st-flash/flash_opts.c | 15 ++++++++------- src/stlink-lib/chipid.c | 2 +- src/stlink-lib/common.c | 1 - 6 files changed, 13 insertions(+), 13 deletions(-) diff --git a/config/chips/L45x_L46x.chip b/config/chips/L45x_L46x.chip index 1c8fc2e1f..c32030be9 100644 --- a/config/chips/L45x_L46x.chip +++ b/config/chips/L45x_L46x.chip @@ -13,4 +13,4 @@ option_base 0x0 option_size 0x0 flags swo otp_base 0x1fff7000 -otp_size 0x400 // 1 KB \ No newline at end of file +otp_size 0x400 // 1 KB diff --git a/config/chips/L496x_L4A6x.chip b/config/chips/L496x_L4A6x.chip index 8a4a93b1c..65fa3dcbc 100644 --- a/config/chips/L496x_L4A6x.chip +++ b/config/chips/L496x_L4A6x.chip @@ -13,4 +13,4 @@ option_base 0x1fff7800 // STM32_L4_OPTION_BYTES_BASE option_size 0x4 // 4 B flags swo otp_base 0x1fff7000 -otp_size 0x400 // 1 KB \ No newline at end of file +otp_size 0x400 // 1 KB diff --git a/src/st-flash/flash.c b/src/st-flash/flash.c index 6553298c3..c2cd77a47 100644 --- a/src/st-flash/flash.c +++ b/src/st-flash/flash.c @@ -184,7 +184,7 @@ int32_t main(int32_t ac, char** av) { } else if (o.area == FLASH_OTP) { if(sl->otp_base == 0) { err = -1; - printf("OTP Write Not implimented\n"); + printf("OTP Write NOT implemented\n"); goto on_error; } err = stlink_fwrite_flash(sl, o.filename, o.addr); @@ -300,7 +300,7 @@ int32_t main(int32_t ac, char** av) { } else if (o.area == FLASH_OTP) { if(sl->otp_base == 0) { err = -1; - printf("OTP Read not implimented\n"); + printf("OTP Read NOT implemented\n"); goto on_error; } err = stlink_fread(sl, o.filename, 0, sl->otp_base, sl->otp_size); diff --git a/src/st-flash/flash_opts.c b/src/st-flash/flash_opts.c index cf80407d1..8f88f6ea7 100644 --- a/src/st-flash/flash_opts.c +++ b/src/st-flash/flash_opts.c @@ -86,6 +86,7 @@ static int32_t bad_arg(const char *arg) { } int32_t flash_get_opts(struct flash_opts* o, int32_t ac, char** av) { + // defaults memset(o, 0, sizeof(*o)); o->log_level = STND_LOG_LEVEL; @@ -269,13 +270,13 @@ int32_t flash_get_opts(struct flash_opts* o, int32_t ac, char** av) { if (ac != 3) { return invalid_args("read "); } o->filename = av[0]; - uint32_t address; - result = get_integer_from_char_array(av[1], &address); - if (result != 0) { - return bad_arg ("addr"); - } else { - o->addr = (stm32_addr_t) address; - } + uint32_t address; + result = get_integer_from_char_array(av[1], &address); + if (result != 0) { + return bad_arg ("addr"); + } else { + o->addr = (stm32_addr_t) address; + } uint32_t size; result = get_integer_from_char_array(av[2], &size); diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index 1b6fc13f7..77cbfb15d 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -58,6 +58,7 @@ void process_chipfile(char *fname) { // fprintf (stderr, "processing chip-id file %s.\n", fname); fp = fopen(fname, "r"); + if (!fp) { perror(fname); return; @@ -202,7 +203,6 @@ void process_chipfile(char *fname) { devicelist = ts; } - #if defined(STLINK_HAVE_DIRENT_H) #include diff --git a/src/stlink-lib/common.c b/src/stlink-lib/common.c index c470f9095..337fe6efa 100644 --- a/src/stlink-lib/common.c +++ b/src/stlink-lib/common.c @@ -293,7 +293,6 @@ int32_t stlink_load_device_params(stlink_t *sl) { sl->otp_base = params->otp_base; sl->otp_size = params->otp_size; - // medium and low devices have the same chipid. ram size depends on flash // size. STM32F100xx datasheet Doc ID 16455 Table 2 if (sl->chip_id == STM32_CHIPID_F1_VL_MD_LD && sl->flash_size < 64 * 1024) { From 3cb15d7da2deb69a38940d1fa82570771252951b Mon Sep 17 00:00:00 2001 From: Mirko Date: Wed, 8 Nov 2023 15:14:19 +0000 Subject: [PATCH 476/503] final --- src/st-flash/flash.c | 1 + src/st-flash/flash_opts.c | 2 +- src/stlink-lib/chipid.c | 2 ++ src/stlink-lib/common_flash.c | 3 --- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/st-flash/flash.c b/src/st-flash/flash.c index c2cd77a47..0b7c0cfca 100644 --- a/src/st-flash/flash.c +++ b/src/st-flash/flash.c @@ -62,6 +62,7 @@ static void usage(void) { puts("example read option control register1 byte: ./st-flash --area=optcr1 read"); puts("example write option control register1 byte: ./st-flash --area=optcr1 write 0xXXXXXXXX"); puts("example read OTP area: ./st-flash --area=otp read [path]"); + puts("example write OTP area: ./st-flash --area=otp write [path] 0xXXXXXXXX"); } int32_t main(int32_t ac, char** av) { diff --git a/src/st-flash/flash_opts.c b/src/st-flash/flash_opts.c index 8f88f6ea7..e2d4154fe 100644 --- a/src/st-flash/flash_opts.c +++ b/src/st-flash/flash_opts.c @@ -86,7 +86,7 @@ static int32_t bad_arg(const char *arg) { } int32_t flash_get_opts(struct flash_opts* o, int32_t ac, char** av) { - + // defaults memset(o, 0, sizeof(*o)); o->log_level = STND_LOG_LEVEL; diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index 77cbfb15d..ceeed3114 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -35,6 +35,7 @@ void dump_a_chip(struct stlink_chipid_params *dev) { DLOG("option_size 0x%x\n", dev->option_size); DLOG("flags %d\n\n", dev->flags); DLOG("otp_base %d\n\n", dev->otp_base); + DLOG("otp_size %d\n\n", dev->otp_size); } struct stlink_chipid_params *stlink_chipid_get_params(uint32_t chip_id) { @@ -181,6 +182,7 @@ void process_chipfile(char *fname) { fprintf(stderr, "Unknown flags word in %s: '%s'\n", fname, p); } } + sscanf(value, "%x", &ts->flags); } else if (strcmp(word, "otp_base") == 0) { buf[strlen(buf) - 1] = 0; // chomp newline diff --git a/src/stlink-lib/common_flash.c b/src/stlink-lib/common_flash.c index 60d8f42fb..5005a632f 100644 --- a/src/stlink-lib/common_flash.c +++ b/src/stlink-lib/common_flash.c @@ -1320,7 +1320,6 @@ int32_t stlink_fwrite_flash(stlink_t *sl, const char *path, stm32_addr_t addr) { (num_empty == mf.len) ? (uint32_t)mf.len : (uint32_t)mf.len - num_empty, num_empty == mf.len); } - stlink_fwrite_finalize(sl, addr); unmap_file(&mf); return (err); @@ -1433,8 +1432,6 @@ int32_t stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint3 flash_loader_t fl; ILOG("Attempting to write %d (%#x) bytes to stm32 address: %u (%#x)\n", len, len, addr, addr); - (void)eraseonly; - // check addr range is inside the flash stlink_calculate_pagesize(sl, addr); From e122764f214fb9821b173a63f7ae18690611dc0a Mon Sep 17 00:00:00 2001 From: Mirko Date: Wed, 8 Nov 2023 22:58:05 +0000 Subject: [PATCH 477/503] forgot to include this --- inc/stlink.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/inc/stlink.h b/inc/stlink.h index dec608e97..557a9eeaa 100644 --- a/inc/stlink.h +++ b/inc/stlink.h @@ -232,6 +232,9 @@ struct _stlink { uint32_t chip_flags; // stlink_chipid_params.flags, set by stlink_load_device_params(), values: CHIP_F_xxx uint32_t max_trace_freq; // set by stlink_open_usb() + + uint32_t otp_base; + uint32_t otp_size; }; /* Functions defined in common.c */ From 99a2be4d287198ea8072e0db1865fc1757255b7b Mon Sep 17 00:00:00 2001 From: rcubee Date: Sat, 11 Nov 2023 17:27:05 +0100 Subject: [PATCH 478/503] initial commit --- c0.patch | 618 ++++++++++++++++++++++++++++++++++ doc/supported_devices.md | 1 + inc/stm32.h | 30 +- inc/stm32flash.h | 24 ++ src/stlink-lib/chipid.c | 4 +- src/stlink-lib/common_flash.c | 98 ++++-- src/stlink-lib/flash_loader.c | 31 +- src/stlink-lib/option_bytes.c | 107 +++++- 8 files changed, 870 insertions(+), 43 deletions(-) create mode 100644 c0.patch diff --git a/c0.patch b/c0.patch new file mode 100644 index 000000000..5b59834d6 --- /dev/null +++ b/c0.patch @@ -0,0 +1,618 @@ +diff --git a/doc/supported_devices.md b/doc/supported_devices.md +index 2e96dcd..103c7fb 100644 +--- a/doc/supported_devices.md ++++ b/doc/supported_devices.md +@@ -6,6 +6,7 @@ More commonly these are: + | Product-Family | ARM Cortex Core | Product Line | + | -------------- | --------------- | ---------------------------------------------------------- | + | STM32F0 | M0 | | ++| STM32C0 | M0+ | | + | STM32G0 | M0+ | | + | STM32L0 | M0+ | | + | STM32F10**0** | M3 | Value line | +diff --git a/inc/stm32.h b/inc/stm32.h +index cf9a8a2..017ea0a 100644 +--- a/inc/stm32.h ++++ b/inc/stm32.h +@@ -51,17 +51,18 @@ enum stm32_core_id { + /* STM32 flash types */ + enum stm32_flash_type { + STM32_FLASH_TYPE_UNKNOWN = 0, +- STM32_FLASH_TYPE_F0_F1_F3 = 1, +- STM32_FLASH_TYPE_F1_XL = 2, +- STM32_FLASH_TYPE_F2_F4 = 3, +- STM32_FLASH_TYPE_F7 = 4, +- STM32_FLASH_TYPE_G0 = 5, +- STM32_FLASH_TYPE_G4 = 6, +- STM32_FLASH_TYPE_H7 = 7, +- STM32_FLASH_TYPE_L0_L1 = 8, +- STM32_FLASH_TYPE_L4 = 9, +- STM32_FLASH_TYPE_L5_U5_H5 = 10, +- STM32_FLASH_TYPE_WB_WL = 11, ++ STM32_FLASH_TYPE_C0 = 1, ++ STM32_FLASH_TYPE_F0_F1_F3 = 2, ++ STM32_FLASH_TYPE_F1_XL = 3, ++ STM32_FLASH_TYPE_F2_F4 = 4, ++ STM32_FLASH_TYPE_F7 = 5, ++ STM32_FLASH_TYPE_G0 = 6, ++ STM32_FLASH_TYPE_G4 = 7, ++ STM32_FLASH_TYPE_H7 = 8, ++ STM32_FLASH_TYPE_L0_L1 = 9, ++ STM32_FLASH_TYPE_L4 = 10, ++ STM32_FLASH_TYPE_L5_U5_H5 = 11, ++ STM32_FLASH_TYPE_WB_WL = 12, + }; + + /* STM32 chip-ids */ +@@ -102,6 +103,7 @@ enum stm32_chipids { + STM32_CHIPID_F0 = 0x440, + STM32_CHIPID_F412 = 0x441, + STM32_CHIPID_F09x = 0x442, ++ STM32_CHIPID_C011xx = 0x443, /* RM0490 (revision 3), section 26.10.1 "DBG device ID code register (DBG_IDCODE)" */ + STM32_CHIPID_F0xx_SMALL = 0x444, + STM32_CHIPID_F04 = 0x445, + STM32_CHIPID_F303_HD = 0x446, /* high density */ +@@ -111,6 +113,7 @@ enum stm32_chipids { + STM32_CHIPID_H74xxx = 0x450, /* RM0433, p.3189 */ + STM32_CHIPID_F76xxx = 0x451, + STM32_CHIPID_F72xxx = 0x452, /* Nucleo F722ZE board */ ++ STM32_CHIPID_C031xx = 0x453, /* RM0490 (revision 3), section 26.10.1 "DBG device ID code register (DBG_IDCODE)" */ + STM32_CHIPID_G0_CAT4 = 0x456, /* G051/G061 */ + STM32_CHIPID_L0_CAT1 = 0x457, + STM32_CHIPID_F410 = 0x458, +@@ -136,6 +139,8 @@ enum stm32_chipids { + }; + + /* Constant STM32 option bytes base memory address */ ++#define STM32_C0_OPTION_BYTES_BASE ((uint32_t)0x1fff7800) ++ + #define STM32_F4_OPTION_BYTES_BASE ((uint32_t)0x40023c14) + + #define STM32_H7_OPTION_BYTES_BASE ((uint32_t)0x5200201c) +@@ -189,6 +194,9 @@ enum stm32_chipids { + #define STM32WB_DBGMCU_APB1FZR1_WWDG_STOP 11 + #define STM32WB_DBGMCU_APB1FZR1_IWDG_STOP 12 + ++#define STM32C0_RCC_AHBENR 0x40021038 // RM0490 (revision 3), section 5.4.25 "RCC register map" ++#define STM32C0_RCC_DMAEN 0x00000001 // DMAEN // RM0490 (revision 3), section 5.4.25 "RCC register map" ++ + #define STM32F1_RCC_AHBENR 0x40021014 + #define STM32F1_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN + +diff --git a/inc/stm32flash.h b/inc/stm32flash.h +index 69c6206..b5e47e0 100644 +--- a/inc/stm32flash.h ++++ b/inc/stm32flash.h +@@ -58,6 +58,30 @@ + #define FLASH_OBR_OFF ((uint32_t)0x1c) + #define FLASH_WRPR_OFF ((uint32_t)0x20) + ++// == STM32C0 == (RM0490) ++// C0 Flash registers ++#define FLASH_C0_REGS_ADDR ((uint32_t)0x40022000) ++#define FLASH_C0_KEYR (FLASH_C0_REGS_ADDR + 0x08) ++#define FLASH_C0_OPT_KEYR (FLASH_C0_REGS_ADDR + 0x0C) ++#define FLASH_C0_SR (FLASH_C0_REGS_ADDR + 0x10) ++#define FLASH_C0_CR (FLASH_C0_REGS_ADDR + 0x14) ++#define FLASH_C0_OPTR (FLASH_C0_REGS_ADDR + 0x20) ++ ++// C0 Flash control register ++#define FLASH_C0_CR_PNB 3 ++#define FLASH_C0_CR_STRT 16 ++#define FLASH_C0_CR_OPTSTRT 17 ++#define FLASH_C0_CR_OBL_LAUNCH 27 ++#define FLASH_C0_CR_OPTLOCK 30 ++#define FLASH_C0_CR_LOCK 31 ++ ++// C0 Flash status register ++#define FLASH_C0_SR_ERROR_MASK 0xC3F8 // [15:14], [9:3] ++#define FLASH_C0_SR_PROGERR 3 ++#define FLASH_C0_SR_WRPERR 4 ++#define FLASH_C0_SR_PGAERR 5 ++#define FLASH_C0_SR_BSY 16 ++ + // == STM32F0 == + #define FLASH_F0_OPTKEY1 0x45670123 + #define FLASH_F0_OPTKEY2 0xcdef89ab +diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c +index 06edb26..86f01f4 100644 +--- a/src/stlink-lib/chipid.c ++++ b/src/stlink-lib/chipid.c +@@ -97,7 +97,9 @@ void process_chipfile(char *fname) { + buf[strlen(buf) - 1] = 0; // chomp newline + sscanf(buf, "%*s %n", &nc); + // Match human readable flash_type with enum stm32_flash_type { }. +- if (strcmp(value, "F0_F1_F3") == 0) { ++ if(strcmp(value, "C0") == 0) { ++ ts->flash_type = STM32_FLASH_TYPE_C0; ++ } else if (strcmp(value, "F0_F1_F3") == 0) { + ts->flash_type = STM32_FLASH_TYPE_F0_F1_F3; + } else if (strcmp(value, "F1_XL") == 0) { + ts->flash_type = STM32_FLASH_TYPE_F1_XL; +diff --git a/src/stlink-lib/common_flash.c b/src/stlink-lib/common_flash.c +index 3038b53..491cf46 100644 +--- a/src/stlink-lib/common_flash.c ++++ b/src/stlink-lib/common_flash.c +@@ -46,7 +46,9 @@ uint32_t get_stm32l0_flash_base(stlink_t *sl) { + uint32_t read_flash_cr(stlink_t *sl, uint32_t bank) { + uint32_t reg, res; + +- if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { ++ if (sl->flash_type == STM32_FLASH_TYPE_C0) { ++ reg = FLASH_C0_CR; ++ } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { + reg = FLASH_F4_CR; + } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { + reg = FLASH_F7_CR; +@@ -77,7 +79,10 @@ void lock_flash(stlink_t *sl) { + uint32_t cr_lock_shift = 0, cr_reg = 0, n = 0, cr2_reg = 0; + uint32_t cr_mask = 0xffffffffu; + +- if (sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) { ++ if (sl->flash_type == STM32_FLASH_TYPE_C0) { ++ cr_reg = FLASH_C0_CR; ++ cr_lock_shift = FLASH_C0_CR_LOCK; ++ } else if (sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) { + cr_reg = FLASH_CR; + cr_lock_shift = FLASH_CR_LOCK; + } else if (sl->flash_type == STM32_FLASH_TYPE_F1_XL) { +@@ -132,8 +137,10 @@ void lock_flash(stlink_t *sl) { + static inline int32_t write_flash_sr(stlink_t *sl, uint32_t bank, uint32_t val) { + uint32_t sr_reg; + +- if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || +- (sl->flash_type == STM32_FLASH_TYPE_F1_XL)) { ++ if (sl->flash_type == STM32_FLASH_TYPE_C0) { ++ sr_reg = FLASH_C0_SR; ++ } else if (sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3 || ++ sl->flash_type == STM32_FLASH_TYPE_F1_XL) { + sr_reg = (bank == BANK_1) ? FLASH_SR : FLASH_SR2; + } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { + sr_reg = FLASH_F4_SR; +@@ -162,6 +169,9 @@ static inline int32_t write_flash_sr(stlink_t *sl, uint32_t bank, uint32_t val) + + void clear_flash_error(stlink_t *sl) { + switch (sl->flash_type) { ++ case STM32_FLASH_TYPE_C0: ++ write_flash_sr(sl, BANK_1, FLASH_C0_SR_ERROR_MASK); ++ break; + case STM32_FLASH_TYPE_F0_F1_F3: + write_flash_sr(sl, BANK_1, FLASH_SR_ERROR_MASK); + break; +@@ -205,8 +215,10 @@ void clear_flash_error(stlink_t *sl) { + uint32_t read_flash_sr(stlink_t *sl, uint32_t bank) { + uint32_t res, sr_reg; + +- if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || +- (sl->flash_type == STM32_FLASH_TYPE_F1_XL)) { ++ if (sl->flash_type == STM32_FLASH_TYPE_C0) { ++ sr_reg = FLASH_C0_SR; ++ } else if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || ++ (sl->flash_type == STM32_FLASH_TYPE_F1_XL)) { + sr_reg = (bank == BANK_1) ? FLASH_SR : FLASH_SR2; + } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { + sr_reg = FLASH_F4_SR; +@@ -238,9 +250,11 @@ uint32_t is_flash_busy(stlink_t *sl) { + uint32_t sr_busy_shift; + uint32_t res; + +- if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || +- (sl->flash_type == STM32_FLASH_TYPE_F1_XL) || +- (sl->flash_type == STM32_FLASH_TYPE_L0_L1)) { ++ if (sl->flash_type == STM32_FLASH_TYPE_C0) { ++ sr_busy_shift = FLASH_C0_SR_BSY; ++ } else if (sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3 || ++ sl->flash_type == STM32_FLASH_TYPE_F1_XL || ++ sl->flash_type == STM32_FLASH_TYPE_L0_L1) { + sr_busy_shift = FLASH_SR_BSY; + } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { + sr_busy_shift = FLASH_F4_SR_BSY; +@@ -286,6 +300,12 @@ int32_t check_flash_error(stlink_t *sl) { + WRPERR = PROGERR = PGAERR = 0; + + switch (sl->flash_type) { ++ case STM32_FLASH_TYPE_C0: ++ res = read_flash_sr(sl, BANK_1) & FLASH_C0_SR_ERROR_MASK; ++ WRPERR = (1 << FLASH_C0_SR_WRPERR); ++ PROGERR = (1 << FLASH_C0_SR_PROGERR); ++ PGAERR = (1 << FLASH_C0_SR_PGAERR); ++ break; + case STM32_FLASH_TYPE_F0_F1_F3: + case STM32_FLASH_TYPE_F1_XL: + res = read_flash_sr(sl, BANK_1) & FLASH_SR_ERROR_MASK; +@@ -382,8 +402,11 @@ static inline uint32_t is_flash_locked(stlink_t *sl) { + uint32_t cr_reg; + uint32_t n; + +- if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || +- (sl->flash_type == STM32_FLASH_TYPE_F1_XL)) { ++ if (sl->flash_type == STM32_FLASH_TYPE_C0) { ++ cr_reg = FLASH_C0_CR; ++ cr_lock_shift = FLASH_C0_CR_LOCK; ++ } else if (sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3 || ++ sl->flash_type == STM32_FLASH_TYPE_F1_XL) { + cr_reg = FLASH_CR; + cr_lock_shift = FLASH_CR_LOCK; + } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { +@@ -429,7 +452,9 @@ static void unlock_flash(stlink_t *sl) { + * definitive lock of the FPEC block until next reset. + */ + +- if (sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) { ++ if (sl->flash_type == STM32_FLASH_TYPE_C0) { ++ key_reg = FLASH_C0_KEYR; ++ } else if (sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) { + key_reg = FLASH_KEYR; + } else if (sl->flash_type == STM32_FLASH_TYPE_F1_XL) { + key_reg = FLASH_KEYR; +@@ -497,6 +522,10 @@ int32_t lock_flash_option(stlink_t *sl) { + int32_t active_bit_level = 1; + + switch (sl->flash_type) { ++ case STM32_FLASH_TYPE_C0: ++ optcr_reg = FLASH_C0_CR; ++ optlock_shift = FLASH_C0_CR_OPTLOCK; ++ break; + case STM32_FLASH_TYPE_F0_F1_F3: + case STM32_FLASH_TYPE_F1_XL: + optcr_reg = FLASH_CR; +@@ -574,6 +603,10 @@ static bool is_flash_option_locked(stlink_t *sl) { + uint32_t n; + + switch (sl->flash_type) { ++ case STM32_FLASH_TYPE_C0: ++ optcr_reg = FLASH_C0_CR; ++ optlock_shift = FLASH_C0_CR_OPTLOCK; ++ break; + case STM32_FLASH_TYPE_F0_F1_F3: + case STM32_FLASH_TYPE_F1_XL: + optcr_reg = FLASH_CR; +@@ -633,6 +666,9 @@ static int32_t unlock_flash_option(stlink_t *sl) { + uint32_t optkey2 = FLASH_OPTKEY2; + + switch (sl->flash_type) { ++ case STM32_FLASH_TYPE_C0: ++ optkey_reg = FLASH_C0_OPT_KEYR; ++ break; + case STM32_FLASH_TYPE_F0_F1_F3: + case STM32_FLASH_TYPE_F1_XL: + optkey_reg = FLASH_OPTKEYR; +@@ -726,7 +762,9 @@ void clear_flash_cr_pg(stlink_t *sl, uint32_t bank) { + uint32_t cr_reg, n; + uint32_t bit = FLASH_CR_PG; + +- if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { ++ if (sl->flash_type == STM32_FLASH_TYPE_C0) { ++ cr_reg = FLASH_C0_CR; ++ } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { + cr_reg = FLASH_F4_CR; + } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { + cr_reg = FLASH_F7_CR; +@@ -802,8 +840,10 @@ static inline void write_flash_cr_snb(stlink_t *sl, uint32_t n, uint32_t bank) { + static void set_flash_cr_per(stlink_t *sl, uint32_t bank) { + uint32_t cr_reg, val; + +- if (sl->flash_type == STM32_FLASH_TYPE_G0 || +- sl->flash_type == STM32_FLASH_TYPE_G4) { ++ if (sl->flash_type == STM32_FLASH_TYPE_C0) { ++ cr_reg = FLASH_C0_CR; ++ } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || ++ sl->flash_type == STM32_FLASH_TYPE_G4) { + cr_reg = FLASH_Gx_CR; + } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5_H5) { + cr_reg = FLASH_L5_NSCR; +@@ -821,8 +861,10 @@ static void set_flash_cr_per(stlink_t *sl, uint32_t bank) { + static void clear_flash_cr_per(stlink_t *sl, uint32_t bank) { + uint32_t cr_reg; + +- if (sl->flash_type == STM32_FLASH_TYPE_G0 || +- sl->flash_type == STM32_FLASH_TYPE_G4) { ++ if (sl->flash_type == STM32_FLASH_TYPE_C0) { ++ cr_reg = FLASH_C0_CR; ++ } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || ++ sl->flash_type == STM32_FLASH_TYPE_G4) { + cr_reg = FLASH_Gx_CR; + } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5_H5) { + cr_reg = FLASH_L5_NSCR; +@@ -855,7 +897,10 @@ static inline void write_flash_cr_bker_pnb(stlink_t *sl, uint32_t n) { + static void set_flash_cr_strt(stlink_t *sl, uint32_t bank) { + uint32_t val, cr_reg, cr_strt; + +- if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { ++ if (sl->flash_type == STM32_FLASH_TYPE_C0) { ++ cr_reg = FLASH_C0_CR; ++ cr_strt = 1 << FLASH_C0_CR_STRT; ++ } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { + cr_reg = FLASH_F4_CR; + cr_strt = 1 << FLASH_F4_CR_STRT; + } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { +@@ -890,7 +935,11 @@ static void set_flash_cr_strt(stlink_t *sl, uint32_t bank) { + static void set_flash_cr_mer(stlink_t *sl, bool v, uint32_t bank) { + uint32_t val, cr_reg, cr_mer, cr_pg; + +- if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { ++ if (sl->flash_type == STM32_FLASH_TYPE_C0) { ++ cr_reg = FLASH_C0_CR; ++ cr_mer = 1 << FLASH_CR_MER; ++ cr_pg = 1 << FLASH_CR_PG; ++ } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { + cr_reg = FLASH_F4_CR; + cr_mer = 1 << FLASH_CR_MER; + cr_pg = 1 << FLASH_CR_PG; +@@ -1062,7 +1111,8 @@ int32_t stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { + } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4 || + sl->flash_type == STM32_FLASH_TYPE_L5_U5_H5 || +- sl->flash_type == STM32_FLASH_TYPE_WB_WL) { ++ sl->flash_type == STM32_FLASH_TYPE_WB_WL || ++ sl->flash_type == STM32_FLASH_TYPE_C0) { + uint32_t val; + unlock_flash_if(sl); + set_flash_cr_per(sl, BANK_1); // set the 'enable Flash erase' bit +@@ -1107,6 +1157,14 @@ int32_t stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { + val |= ((flash_page & 0xFF) << 3); + + stlink_write_debug32(sl, FLASH_WB_CR, val); ++ } else if (sl->flash_type == STM32_FLASH_TYPE_C0) { ++ uint32_t flash_page = ((flashaddr - STM32_FLASH_BASE) / sl->flash_pgsz); ++ stlink_read_debug32(sl, FLASH_C0_CR, &val); ++ ++ val &= ~(0xF << FLASH_C0_CR_PNB); ++ val |= ((flash_page & 0xF) << FLASH_C0_CR_PNB); ++ ++ stlink_write_debug32(sl, FLASH_C0_CR, val); + } + + set_flash_cr_strt(sl, BANK_1); // set the 'start operation' bit +diff --git a/src/stlink-lib/flash_loader.c b/src/stlink-lib/flash_loader.c +index ea1f6d9..0d01dfd 100644 +--- a/src/stlink-lib/flash_loader.c ++++ b/src/stlink-lib/flash_loader.c +@@ -491,12 +491,15 @@ static void set_flash_cr_pg(stlink_t *sl, uint32_t bank) { + + x = read_flash_cr(sl, bank); + +- if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { ++ if (sl->flash_type == STM32_FLASH_TYPE_C0) { ++ cr_reg = FLASH_C0_CR; ++ x |= (1 << FLASH_CR_PG); ++ } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { + cr_reg = FLASH_F4_CR; +- x |= 1 << FLASH_CR_PG; ++ x |= (1 << FLASH_CR_PG); + } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { + cr_reg = FLASH_F7_CR; +- x |= 1 << FLASH_CR_PG; ++ x |= (1 << FLASH_CR_PG); + } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { + cr_reg = FLASH_L4_CR; + x &= ~FLASH_L4_CR_OPBITS; +@@ -528,6 +531,10 @@ static void set_dma_state(stlink_t *sl, flash_loader_t *fl, int32_t bckpRstr) { + rcc = rcc_dma_mask = value = 0; + + switch (sl->flash_type) { ++ case STM32_FLASH_TYPE_C0: ++ rcc = STM32C0_RCC_AHBENR; ++ rcc_dma_mask = STM32C0_RCC_DMAEN; ++ break; + case STM32_FLASH_TYPE_F0_F1_F3: + case STM32_FLASH_TYPE_F1_XL: + rcc = STM32F1_RCC_AHBENR; +@@ -639,8 +646,9 @@ int32_t stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL || + sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4 || +- sl->flash_type == STM32_FLASH_TYPE_L5_U5_H5) { +- ILOG("Starting Flash write for WB/G0/G4/L5/U5/H5\n"); ++ sl->flash_type == STM32_FLASH_TYPE_L5_U5_H5 || ++ sl->flash_type == STM32_FLASH_TYPE_C0) { ++ ILOG("Starting Flash write for WB/G0/G4/L5/U5/H5/C0\n"); + + unlock_flash_if(sl); // unlock flash if necessary + set_flash_cr_pg(sl, BANK_1); // set PG 'allow programming' bit +@@ -720,6 +728,7 @@ int32_t stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { + + int32_t stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t addr, uint8_t *base, uint32_t len) { + uint32_t off; ++ + if ((sl->flash_type == STM32_FLASH_TYPE_F2_F4) || + (sl->flash_type == STM32_FLASH_TYPE_F7) || + (sl->flash_type == STM32_FLASH_TYPE_L4)) { +@@ -737,13 +746,14 @@ int32_t stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL || + sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4 || +- sl->flash_type == STM32_FLASH_TYPE_L5_U5_H5) { ++ sl->flash_type == STM32_FLASH_TYPE_L5_U5_H5 || ++ sl->flash_type == STM32_FLASH_TYPE_C0) { + DLOG("Starting %3u page write\n", len / sl->flash_pgsz); + for (off = 0; off < len; off += sizeof(uint32_t)) { + uint32_t data; + + if ((off % sl->flash_pgsz) > (sl->flash_pgsz - 5)) { +- fprintf(stdout, "\r%3u/%3u pages written", (off / sl->flash_pgsz + 1), (len / sl->flash_pgsz)); ++ fprintf(stdout, "\r%3u/%-3u pages written", (off / sl->flash_pgsz + 1), (len / sl->flash_pgsz)); + fflush(stdout); + } + +@@ -782,7 +792,7 @@ int32_t stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t + uint32_t data; + + if ((off % sl->flash_pgsz) > (sl->flash_pgsz - 5)) { +- fprintf(stdout, "\r%3u/%3u pages written", (off / sl->flash_pgsz + 1), (len / sl->flash_pgsz)); ++ fprintf(stdout, "\r%3u/%-3u pages written", (off / sl->flash_pgsz + 1), (len / sl->flash_pgsz)); + fflush(stdout); + } + +@@ -819,7 +829,7 @@ int32_t stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t + if (sl->verbose >= 1) { + // show progress; writing procedure is slow and previous errors are + // misleading +- fprintf(stdout, "\r%3u/%3u pages written", ++write_block_count, ++ fprintf(stdout, "\r%3u/%-3u pages written", ++write_block_count, + (len + sl->flash_pgsz - 1) / sl->flash_pgsz); + fflush(stdout); + } +@@ -856,7 +866,8 @@ int32_t stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t + int32_t stlink_flashloader_stop(stlink_t *sl, flash_loader_t *fl) { + uint32_t dhcsr; + +- if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || ++ if ((sl->flash_type == STM32_FLASH_TYPE_C0) || ++ (sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || + (sl->flash_type == STM32_FLASH_TYPE_F1_XL) || + (sl->flash_type == STM32_FLASH_TYPE_F2_F4) || + (sl->flash_type == STM32_FLASH_TYPE_F7) || +diff --git a/src/stlink-lib/option_bytes.c b/src/stlink-lib/option_bytes.c +index ee03dce..2ee45c9 100644 +--- a/src/stlink-lib/option_bytes.c ++++ b/src/stlink-lib/option_bytes.c +@@ -18,6 +18,101 @@ + #include "md5.h" + #include "read_write.h" + ++/** ++ * Read option control register C0 ++ * @param sl ++ * @param option_byte ++ * @return 0 on success, -ve on failure. ++ */ ++static int32_t stlink_read_option_control_register_c0(stlink_t *sl, uint32_t *option_byte) { ++ return stlink_read_debug32(sl, FLASH_C0_OPTR, option_byte); ++} ++ ++/** ++ * Read option bytes C0 ++ * @param sl ++ * @param option_byte ++ * @return 0 on success, -ve on failure. ++ */ ++static int32_t stlink_read_option_bytes_c0(stlink_t *sl, uint32_t *option_byte) { ++ return stlink_read_option_control_register_c0(sl, option_byte); ++} ++ ++/** ++ * Write option control register C0 ++ * @param sl ++ * @param option_cr ++ * @return 0 on success, -ve on failure. ++ */ ++static int32_t stlink_write_option_control_register_c0(stlink_t *sl, uint32_t option_cr) { ++ int32_t ret = 0; ++ ++ clear_flash_error(sl); ++ ++ if ((ret = stlink_write_debug32(sl, FLASH_C0_OPTR, option_cr))) ++ return ret; ++ ++ wait_flash_busy(sl); ++ ++ uint32_t cr_reg = (1 << FLASH_C0_CR_OPTSTRT); ++ if ((ret = stlink_write_debug32(sl, FLASH_C0_CR, cr_reg))) ++ return ret; ++ ++ wait_flash_busy(sl); ++ ++ if ((ret = check_flash_error(sl))) ++ return ret; ++ ++ // trigger the load of option bytes into option registers ++ cr_reg = (1 << FLASH_C0_CR_OBL_LAUNCH); ++ stlink_write_debug32(sl, FLASH_C0_CR, cr_reg); ++ ++ return ret; ++} ++ ++/** ++ * Write option bytes C0 ++ * @param sl ++ * @param addr of the memory mapped option bytes ++ * @param base option bytes ++ * @param len of option bytes ++ * @return 0 on success, -ve on failure. ++ */ ++static int32_t stlink_write_option_bytes_c0(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint32_t len) { ++#if 0 ++ uint32_t val; ++ int32_t ret = 0; ++ (void)len; ++ uint32_t data; ++ ++ clear_flash_error(sl); ++ ++ write_uint32((unsigned char *)&data, *(uint32_t *)(base)); ++ WLOG("Writing option bytes %#10x to %#10x\n", data, addr); ++ stlink_write_debug32(sl, FLASH_C0_OPTR, data); ++ ++ stlink_read_debug32(sl, FLASH_C0_CR, &val); ++ val |= (1 << FLASH_C0_CR_OPTSTRT); ++ stlink_write_debug32(sl, FLASH_C0_CR, val); ++ ++ wait_flash_busy(sl); ++ ++ ret = check_flash_error(sl); ++ ++ // trigger the load of option bytes into option registers ++ stlink_read_debug32(sl, FLASH_C0_CR, &val); ++ val |= (1 << FLASH_C0_CR_OBL_LAUNCH); ++ stlink_write_debug32(sl, FLASH_C0_CR, val); ++ ++ return (ret); ++#else ++ (void)addr; ++ (void)len; ++ ++ return stlink_write_option_control_register_c0(sl, *(uint32_t*)base); ++#endif ++} ++ + /** + * Read option control register F0 + * @param sl +@@ -745,7 +840,6 @@ int32_t stlink_read_option_bytes_generic(stlink_t *sl, uint32_t *option_byte) { + return stlink_read_debug32(sl, sl->option_base, option_byte); + } + +- + /** + * Write option bytes + * @param sl +@@ -785,6 +879,9 @@ int32_t stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t *base + } + + switch (sl->flash_type) { ++ case STM32_FLASH_TYPE_C0: ++ ret = stlink_write_option_bytes_c0(sl, addr, base, len); ++ break; + case STM32_FLASH_TYPE_F0_F1_F3: + case STM32_FLASH_TYPE_F1_XL: + ret = stlink_write_option_bytes_f0(sl, addr, base, len); +@@ -870,6 +967,8 @@ int32_t stlink_read_option_control_register32(stlink_t *sl, uint32_t *option_byt + } + + switch (sl->flash_type) { ++ case STM32_FLASH_TYPE_C0: ++ return stlink_read_option_control_register_c0(sl, option_byte); + case STM32_FLASH_TYPE_F0_F1_F3: + case STM32_FLASH_TYPE_F1_XL: + return stlink_read_option_control_register_f0(sl, option_byte); +@@ -904,6 +1003,9 @@ int32_t stlink_write_option_control_register32(stlink_t *sl, uint32_t option_cr) + } + + switch (sl->flash_type) { ++ case STM32_FLASH_TYPE_C0: ++ ret = stlink_write_option_control_register_c0(sl, option_cr); ++ break; + case STM32_FLASH_TYPE_F0_F1_F3: + case STM32_FLASH_TYPE_F1_XL: + ret = stlink_write_option_control_register_f0(sl, option_cr); +@@ -1009,6 +1111,9 @@ int32_t stlink_read_option_bytes32(stlink_t *sl, uint32_t *option_byte) { + } + + switch (sl->chip_id) { ++ case STM32_CHIPID_C011xx: ++ case STM32_CHIPID_C031xx: ++ return stlink_read_option_bytes_c0(sl, option_byte); + case STM32_CHIPID_F2: + return stlink_read_option_bytes_f2(sl, option_byte); + case STM32_CHIPID_F4: diff --git a/doc/supported_devices.md b/doc/supported_devices.md index 2e96dcd39..103c7fb5f 100644 --- a/doc/supported_devices.md +++ b/doc/supported_devices.md @@ -6,6 +6,7 @@ More commonly these are: | Product-Family | ARM Cortex Core | Product Line | | -------------- | --------------- | ---------------------------------------------------------- | | STM32F0 | M0 | | +| STM32C0 | M0+ | | | STM32G0 | M0+ | | | STM32L0 | M0+ | | | STM32F10**0** | M3 | Value line | diff --git a/inc/stm32.h b/inc/stm32.h index cf9a8a2ad..017ea0af6 100644 --- a/inc/stm32.h +++ b/inc/stm32.h @@ -51,17 +51,18 @@ enum stm32_core_id { /* STM32 flash types */ enum stm32_flash_type { STM32_FLASH_TYPE_UNKNOWN = 0, - STM32_FLASH_TYPE_F0_F1_F3 = 1, - STM32_FLASH_TYPE_F1_XL = 2, - STM32_FLASH_TYPE_F2_F4 = 3, - STM32_FLASH_TYPE_F7 = 4, - STM32_FLASH_TYPE_G0 = 5, - STM32_FLASH_TYPE_G4 = 6, - STM32_FLASH_TYPE_H7 = 7, - STM32_FLASH_TYPE_L0_L1 = 8, - STM32_FLASH_TYPE_L4 = 9, - STM32_FLASH_TYPE_L5_U5_H5 = 10, - STM32_FLASH_TYPE_WB_WL = 11, + STM32_FLASH_TYPE_C0 = 1, + STM32_FLASH_TYPE_F0_F1_F3 = 2, + STM32_FLASH_TYPE_F1_XL = 3, + STM32_FLASH_TYPE_F2_F4 = 4, + STM32_FLASH_TYPE_F7 = 5, + STM32_FLASH_TYPE_G0 = 6, + STM32_FLASH_TYPE_G4 = 7, + STM32_FLASH_TYPE_H7 = 8, + STM32_FLASH_TYPE_L0_L1 = 9, + STM32_FLASH_TYPE_L4 = 10, + STM32_FLASH_TYPE_L5_U5_H5 = 11, + STM32_FLASH_TYPE_WB_WL = 12, }; /* STM32 chip-ids */ @@ -102,6 +103,7 @@ enum stm32_chipids { STM32_CHIPID_F0 = 0x440, STM32_CHIPID_F412 = 0x441, STM32_CHIPID_F09x = 0x442, + STM32_CHIPID_C011xx = 0x443, /* RM0490 (revision 3), section 26.10.1 "DBG device ID code register (DBG_IDCODE)" */ STM32_CHIPID_F0xx_SMALL = 0x444, STM32_CHIPID_F04 = 0x445, STM32_CHIPID_F303_HD = 0x446, /* high density */ @@ -111,6 +113,7 @@ enum stm32_chipids { STM32_CHIPID_H74xxx = 0x450, /* RM0433, p.3189 */ STM32_CHIPID_F76xxx = 0x451, STM32_CHIPID_F72xxx = 0x452, /* Nucleo F722ZE board */ + STM32_CHIPID_C031xx = 0x453, /* RM0490 (revision 3), section 26.10.1 "DBG device ID code register (DBG_IDCODE)" */ STM32_CHIPID_G0_CAT4 = 0x456, /* G051/G061 */ STM32_CHIPID_L0_CAT1 = 0x457, STM32_CHIPID_F410 = 0x458, @@ -136,6 +139,8 @@ enum stm32_chipids { }; /* Constant STM32 option bytes base memory address */ +#define STM32_C0_OPTION_BYTES_BASE ((uint32_t)0x1fff7800) + #define STM32_F4_OPTION_BYTES_BASE ((uint32_t)0x40023c14) #define STM32_H7_OPTION_BYTES_BASE ((uint32_t)0x5200201c) @@ -189,6 +194,9 @@ enum stm32_chipids { #define STM32WB_DBGMCU_APB1FZR1_WWDG_STOP 11 #define STM32WB_DBGMCU_APB1FZR1_IWDG_STOP 12 +#define STM32C0_RCC_AHBENR 0x40021038 // RM0490 (revision 3), section 5.4.25 "RCC register map" +#define STM32C0_RCC_DMAEN 0x00000001 // DMAEN // RM0490 (revision 3), section 5.4.25 "RCC register map" + #define STM32F1_RCC_AHBENR 0x40021014 #define STM32F1_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN diff --git a/inc/stm32flash.h b/inc/stm32flash.h index 69c6206ee..b5e47e0d3 100644 --- a/inc/stm32flash.h +++ b/inc/stm32flash.h @@ -58,6 +58,30 @@ #define FLASH_OBR_OFF ((uint32_t)0x1c) #define FLASH_WRPR_OFF ((uint32_t)0x20) +// == STM32C0 == (RM0490) +// C0 Flash registers +#define FLASH_C0_REGS_ADDR ((uint32_t)0x40022000) +#define FLASH_C0_KEYR (FLASH_C0_REGS_ADDR + 0x08) +#define FLASH_C0_OPT_KEYR (FLASH_C0_REGS_ADDR + 0x0C) +#define FLASH_C0_SR (FLASH_C0_REGS_ADDR + 0x10) +#define FLASH_C0_CR (FLASH_C0_REGS_ADDR + 0x14) +#define FLASH_C0_OPTR (FLASH_C0_REGS_ADDR + 0x20) + +// C0 Flash control register +#define FLASH_C0_CR_PNB 3 +#define FLASH_C0_CR_STRT 16 +#define FLASH_C0_CR_OPTSTRT 17 +#define FLASH_C0_CR_OBL_LAUNCH 27 +#define FLASH_C0_CR_OPTLOCK 30 +#define FLASH_C0_CR_LOCK 31 + +// C0 Flash status register +#define FLASH_C0_SR_ERROR_MASK 0xC3F8 // [15:14], [9:3] +#define FLASH_C0_SR_PROGERR 3 +#define FLASH_C0_SR_WRPERR 4 +#define FLASH_C0_SR_PGAERR 5 +#define FLASH_C0_SR_BSY 16 + // == STM32F0 == #define FLASH_F0_OPTKEY1 0x45670123 #define FLASH_F0_OPTKEY2 0xcdef89ab diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index 06edb26f3..86f01f4df 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -97,7 +97,9 @@ void process_chipfile(char *fname) { buf[strlen(buf) - 1] = 0; // chomp newline sscanf(buf, "%*s %n", &nc); // Match human readable flash_type with enum stm32_flash_type { }. - if (strcmp(value, "F0_F1_F3") == 0) { + if(strcmp(value, "C0") == 0) { + ts->flash_type = STM32_FLASH_TYPE_C0; + } else if (strcmp(value, "F0_F1_F3") == 0) { ts->flash_type = STM32_FLASH_TYPE_F0_F1_F3; } else if (strcmp(value, "F1_XL") == 0) { ts->flash_type = STM32_FLASH_TYPE_F1_XL; diff --git a/src/stlink-lib/common_flash.c b/src/stlink-lib/common_flash.c index 3038b53e7..491cf462d 100644 --- a/src/stlink-lib/common_flash.c +++ b/src/stlink-lib/common_flash.c @@ -46,7 +46,9 @@ uint32_t get_stm32l0_flash_base(stlink_t *sl) { uint32_t read_flash_cr(stlink_t *sl, uint32_t bank) { uint32_t reg, res; - if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { + if (sl->flash_type == STM32_FLASH_TYPE_C0) { + reg = FLASH_C0_CR; + } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { reg = FLASH_F4_CR; } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { reg = FLASH_F7_CR; @@ -77,7 +79,10 @@ void lock_flash(stlink_t *sl) { uint32_t cr_lock_shift = 0, cr_reg = 0, n = 0, cr2_reg = 0; uint32_t cr_mask = 0xffffffffu; - if (sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) { + if (sl->flash_type == STM32_FLASH_TYPE_C0) { + cr_reg = FLASH_C0_CR; + cr_lock_shift = FLASH_C0_CR_LOCK; + } else if (sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) { cr_reg = FLASH_CR; cr_lock_shift = FLASH_CR_LOCK; } else if (sl->flash_type == STM32_FLASH_TYPE_F1_XL) { @@ -132,8 +137,10 @@ void lock_flash(stlink_t *sl) { static inline int32_t write_flash_sr(stlink_t *sl, uint32_t bank, uint32_t val) { uint32_t sr_reg; - if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || - (sl->flash_type == STM32_FLASH_TYPE_F1_XL)) { + if (sl->flash_type == STM32_FLASH_TYPE_C0) { + sr_reg = FLASH_C0_SR; + } else if (sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3 || + sl->flash_type == STM32_FLASH_TYPE_F1_XL) { sr_reg = (bank == BANK_1) ? FLASH_SR : FLASH_SR2; } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { sr_reg = FLASH_F4_SR; @@ -162,6 +169,9 @@ static inline int32_t write_flash_sr(stlink_t *sl, uint32_t bank, uint32_t val) void clear_flash_error(stlink_t *sl) { switch (sl->flash_type) { + case STM32_FLASH_TYPE_C0: + write_flash_sr(sl, BANK_1, FLASH_C0_SR_ERROR_MASK); + break; case STM32_FLASH_TYPE_F0_F1_F3: write_flash_sr(sl, BANK_1, FLASH_SR_ERROR_MASK); break; @@ -205,8 +215,10 @@ void clear_flash_error(stlink_t *sl) { uint32_t read_flash_sr(stlink_t *sl, uint32_t bank) { uint32_t res, sr_reg; - if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || - (sl->flash_type == STM32_FLASH_TYPE_F1_XL)) { + if (sl->flash_type == STM32_FLASH_TYPE_C0) { + sr_reg = FLASH_C0_SR; + } else if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || + (sl->flash_type == STM32_FLASH_TYPE_F1_XL)) { sr_reg = (bank == BANK_1) ? FLASH_SR : FLASH_SR2; } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { sr_reg = FLASH_F4_SR; @@ -238,9 +250,11 @@ uint32_t is_flash_busy(stlink_t *sl) { uint32_t sr_busy_shift; uint32_t res; - if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || - (sl->flash_type == STM32_FLASH_TYPE_F1_XL) || - (sl->flash_type == STM32_FLASH_TYPE_L0_L1)) { + if (sl->flash_type == STM32_FLASH_TYPE_C0) { + sr_busy_shift = FLASH_C0_SR_BSY; + } else if (sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3 || + sl->flash_type == STM32_FLASH_TYPE_F1_XL || + sl->flash_type == STM32_FLASH_TYPE_L0_L1) { sr_busy_shift = FLASH_SR_BSY; } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { sr_busy_shift = FLASH_F4_SR_BSY; @@ -286,6 +300,12 @@ int32_t check_flash_error(stlink_t *sl) { WRPERR = PROGERR = PGAERR = 0; switch (sl->flash_type) { + case STM32_FLASH_TYPE_C0: + res = read_flash_sr(sl, BANK_1) & FLASH_C0_SR_ERROR_MASK; + WRPERR = (1 << FLASH_C0_SR_WRPERR); + PROGERR = (1 << FLASH_C0_SR_PROGERR); + PGAERR = (1 << FLASH_C0_SR_PGAERR); + break; case STM32_FLASH_TYPE_F0_F1_F3: case STM32_FLASH_TYPE_F1_XL: res = read_flash_sr(sl, BANK_1) & FLASH_SR_ERROR_MASK; @@ -382,8 +402,11 @@ static inline uint32_t is_flash_locked(stlink_t *sl) { uint32_t cr_reg; uint32_t n; - if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || - (sl->flash_type == STM32_FLASH_TYPE_F1_XL)) { + if (sl->flash_type == STM32_FLASH_TYPE_C0) { + cr_reg = FLASH_C0_CR; + cr_lock_shift = FLASH_C0_CR_LOCK; + } else if (sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3 || + sl->flash_type == STM32_FLASH_TYPE_F1_XL) { cr_reg = FLASH_CR; cr_lock_shift = FLASH_CR_LOCK; } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { @@ -429,7 +452,9 @@ static void unlock_flash(stlink_t *sl) { * definitive lock of the FPEC block until next reset. */ - if (sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) { + if (sl->flash_type == STM32_FLASH_TYPE_C0) { + key_reg = FLASH_C0_KEYR; + } else if (sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) { key_reg = FLASH_KEYR; } else if (sl->flash_type == STM32_FLASH_TYPE_F1_XL) { key_reg = FLASH_KEYR; @@ -497,6 +522,10 @@ int32_t lock_flash_option(stlink_t *sl) { int32_t active_bit_level = 1; switch (sl->flash_type) { + case STM32_FLASH_TYPE_C0: + optcr_reg = FLASH_C0_CR; + optlock_shift = FLASH_C0_CR_OPTLOCK; + break; case STM32_FLASH_TYPE_F0_F1_F3: case STM32_FLASH_TYPE_F1_XL: optcr_reg = FLASH_CR; @@ -574,6 +603,10 @@ static bool is_flash_option_locked(stlink_t *sl) { uint32_t n; switch (sl->flash_type) { + case STM32_FLASH_TYPE_C0: + optcr_reg = FLASH_C0_CR; + optlock_shift = FLASH_C0_CR_OPTLOCK; + break; case STM32_FLASH_TYPE_F0_F1_F3: case STM32_FLASH_TYPE_F1_XL: optcr_reg = FLASH_CR; @@ -633,6 +666,9 @@ static int32_t unlock_flash_option(stlink_t *sl) { uint32_t optkey2 = FLASH_OPTKEY2; switch (sl->flash_type) { + case STM32_FLASH_TYPE_C0: + optkey_reg = FLASH_C0_OPT_KEYR; + break; case STM32_FLASH_TYPE_F0_F1_F3: case STM32_FLASH_TYPE_F1_XL: optkey_reg = FLASH_OPTKEYR; @@ -726,7 +762,9 @@ void clear_flash_cr_pg(stlink_t *sl, uint32_t bank) { uint32_t cr_reg, n; uint32_t bit = FLASH_CR_PG; - if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { + if (sl->flash_type == STM32_FLASH_TYPE_C0) { + cr_reg = FLASH_C0_CR; + } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { cr_reg = FLASH_F4_CR; } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { cr_reg = FLASH_F7_CR; @@ -802,8 +840,10 @@ static inline void write_flash_cr_snb(stlink_t *sl, uint32_t n, uint32_t bank) { static void set_flash_cr_per(stlink_t *sl, uint32_t bank) { uint32_t cr_reg, val; - if (sl->flash_type == STM32_FLASH_TYPE_G0 || - sl->flash_type == STM32_FLASH_TYPE_G4) { + if (sl->flash_type == STM32_FLASH_TYPE_C0) { + cr_reg = FLASH_C0_CR; + } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4) { cr_reg = FLASH_Gx_CR; } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5_H5) { cr_reg = FLASH_L5_NSCR; @@ -821,8 +861,10 @@ static void set_flash_cr_per(stlink_t *sl, uint32_t bank) { static void clear_flash_cr_per(stlink_t *sl, uint32_t bank) { uint32_t cr_reg; - if (sl->flash_type == STM32_FLASH_TYPE_G0 || - sl->flash_type == STM32_FLASH_TYPE_G4) { + if (sl->flash_type == STM32_FLASH_TYPE_C0) { + cr_reg = FLASH_C0_CR; + } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4) { cr_reg = FLASH_Gx_CR; } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5_H5) { cr_reg = FLASH_L5_NSCR; @@ -855,7 +897,10 @@ static inline void write_flash_cr_bker_pnb(stlink_t *sl, uint32_t n) { static void set_flash_cr_strt(stlink_t *sl, uint32_t bank) { uint32_t val, cr_reg, cr_strt; - if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { + if (sl->flash_type == STM32_FLASH_TYPE_C0) { + cr_reg = FLASH_C0_CR; + cr_strt = 1 << FLASH_C0_CR_STRT; + } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { cr_reg = FLASH_F4_CR; cr_strt = 1 << FLASH_F4_CR_STRT; } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { @@ -890,7 +935,11 @@ static void set_flash_cr_strt(stlink_t *sl, uint32_t bank) { static void set_flash_cr_mer(stlink_t *sl, bool v, uint32_t bank) { uint32_t val, cr_reg, cr_mer, cr_pg; - if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { + if (sl->flash_type == STM32_FLASH_TYPE_C0) { + cr_reg = FLASH_C0_CR; + cr_mer = 1 << FLASH_CR_MER; + cr_pg = 1 << FLASH_CR_PG; + } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { cr_reg = FLASH_F4_CR; cr_mer = 1 << FLASH_CR_MER; cr_pg = 1 << FLASH_CR_PG; @@ -1062,7 +1111,8 @@ int32_t stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || sl->flash_type == STM32_FLASH_TYPE_G4 || sl->flash_type == STM32_FLASH_TYPE_L5_U5_H5 || - sl->flash_type == STM32_FLASH_TYPE_WB_WL) { + sl->flash_type == STM32_FLASH_TYPE_WB_WL || + sl->flash_type == STM32_FLASH_TYPE_C0) { uint32_t val; unlock_flash_if(sl); set_flash_cr_per(sl, BANK_1); // set the 'enable Flash erase' bit @@ -1107,6 +1157,14 @@ int32_t stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { val |= ((flash_page & 0xFF) << 3); stlink_write_debug32(sl, FLASH_WB_CR, val); + } else if (sl->flash_type == STM32_FLASH_TYPE_C0) { + uint32_t flash_page = ((flashaddr - STM32_FLASH_BASE) / sl->flash_pgsz); + stlink_read_debug32(sl, FLASH_C0_CR, &val); + + val &= ~(0xF << FLASH_C0_CR_PNB); + val |= ((flash_page & 0xF) << FLASH_C0_CR_PNB); + + stlink_write_debug32(sl, FLASH_C0_CR, val); } set_flash_cr_strt(sl, BANK_1); // set the 'start operation' bit diff --git a/src/stlink-lib/flash_loader.c b/src/stlink-lib/flash_loader.c index ea1f6d97a..0d01dfd61 100644 --- a/src/stlink-lib/flash_loader.c +++ b/src/stlink-lib/flash_loader.c @@ -491,12 +491,15 @@ static void set_flash_cr_pg(stlink_t *sl, uint32_t bank) { x = read_flash_cr(sl, bank); - if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { + if (sl->flash_type == STM32_FLASH_TYPE_C0) { + cr_reg = FLASH_C0_CR; + x |= (1 << FLASH_CR_PG); + } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { cr_reg = FLASH_F4_CR; - x |= 1 << FLASH_CR_PG; + x |= (1 << FLASH_CR_PG); } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { cr_reg = FLASH_F7_CR; - x |= 1 << FLASH_CR_PG; + x |= (1 << FLASH_CR_PG); } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { cr_reg = FLASH_L4_CR; x &= ~FLASH_L4_CR_OPBITS; @@ -528,6 +531,10 @@ static void set_dma_state(stlink_t *sl, flash_loader_t *fl, int32_t bckpRstr) { rcc = rcc_dma_mask = value = 0; switch (sl->flash_type) { + case STM32_FLASH_TYPE_C0: + rcc = STM32C0_RCC_AHBENR; + rcc_dma_mask = STM32C0_RCC_DMAEN; + break; case STM32_FLASH_TYPE_F0_F1_F3: case STM32_FLASH_TYPE_F1_XL: rcc = STM32F1_RCC_AHBENR; @@ -639,8 +646,9 @@ int32_t stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL || sl->flash_type == STM32_FLASH_TYPE_G0 || sl->flash_type == STM32_FLASH_TYPE_G4 || - sl->flash_type == STM32_FLASH_TYPE_L5_U5_H5) { - ILOG("Starting Flash write for WB/G0/G4/L5/U5/H5\n"); + sl->flash_type == STM32_FLASH_TYPE_L5_U5_H5 || + sl->flash_type == STM32_FLASH_TYPE_C0) { + ILOG("Starting Flash write for WB/G0/G4/L5/U5/H5/C0\n"); unlock_flash_if(sl); // unlock flash if necessary set_flash_cr_pg(sl, BANK_1); // set PG 'allow programming' bit @@ -720,6 +728,7 @@ int32_t stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { int32_t stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t addr, uint8_t *base, uint32_t len) { uint32_t off; + if ((sl->flash_type == STM32_FLASH_TYPE_F2_F4) || (sl->flash_type == STM32_FLASH_TYPE_F7) || (sl->flash_type == STM32_FLASH_TYPE_L4)) { @@ -737,13 +746,14 @@ int32_t stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL || sl->flash_type == STM32_FLASH_TYPE_G0 || sl->flash_type == STM32_FLASH_TYPE_G4 || - sl->flash_type == STM32_FLASH_TYPE_L5_U5_H5) { + sl->flash_type == STM32_FLASH_TYPE_L5_U5_H5 || + sl->flash_type == STM32_FLASH_TYPE_C0) { DLOG("Starting %3u page write\n", len / sl->flash_pgsz); for (off = 0; off < len; off += sizeof(uint32_t)) { uint32_t data; if ((off % sl->flash_pgsz) > (sl->flash_pgsz - 5)) { - fprintf(stdout, "\r%3u/%3u pages written", (off / sl->flash_pgsz + 1), (len / sl->flash_pgsz)); + fprintf(stdout, "\r%3u/%-3u pages written", (off / sl->flash_pgsz + 1), (len / sl->flash_pgsz)); fflush(stdout); } @@ -782,7 +792,7 @@ int32_t stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t uint32_t data; if ((off % sl->flash_pgsz) > (sl->flash_pgsz - 5)) { - fprintf(stdout, "\r%3u/%3u pages written", (off / sl->flash_pgsz + 1), (len / sl->flash_pgsz)); + fprintf(stdout, "\r%3u/%-3u pages written", (off / sl->flash_pgsz + 1), (len / sl->flash_pgsz)); fflush(stdout); } @@ -819,7 +829,7 @@ int32_t stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t if (sl->verbose >= 1) { // show progress; writing procedure is slow and previous errors are // misleading - fprintf(stdout, "\r%3u/%3u pages written", ++write_block_count, + fprintf(stdout, "\r%3u/%-3u pages written", ++write_block_count, (len + sl->flash_pgsz - 1) / sl->flash_pgsz); fflush(stdout); } @@ -856,7 +866,8 @@ int32_t stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t int32_t stlink_flashloader_stop(stlink_t *sl, flash_loader_t *fl) { uint32_t dhcsr; - if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || + if ((sl->flash_type == STM32_FLASH_TYPE_C0) || + (sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || (sl->flash_type == STM32_FLASH_TYPE_F1_XL) || (sl->flash_type == STM32_FLASH_TYPE_F2_F4) || (sl->flash_type == STM32_FLASH_TYPE_F7) || diff --git a/src/stlink-lib/option_bytes.c b/src/stlink-lib/option_bytes.c index ee03dced9..2ee45c901 100644 --- a/src/stlink-lib/option_bytes.c +++ b/src/stlink-lib/option_bytes.c @@ -18,6 +18,101 @@ #include "md5.h" #include "read_write.h" +/** + * Read option control register C0 + * @param sl + * @param option_byte + * @return 0 on success, -ve on failure. + */ +static int32_t stlink_read_option_control_register_c0(stlink_t *sl, uint32_t *option_byte) { + return stlink_read_debug32(sl, FLASH_C0_OPTR, option_byte); +} + +/** + * Read option bytes C0 + * @param sl + * @param option_byte + * @return 0 on success, -ve on failure. + */ +static int32_t stlink_read_option_bytes_c0(stlink_t *sl, uint32_t *option_byte) { + return stlink_read_option_control_register_c0(sl, option_byte); +} + +/** + * Write option control register C0 + * @param sl + * @param option_cr + * @return 0 on success, -ve on failure. + */ +static int32_t stlink_write_option_control_register_c0(stlink_t *sl, uint32_t option_cr) { + int32_t ret = 0; + + clear_flash_error(sl); + + if ((ret = stlink_write_debug32(sl, FLASH_C0_OPTR, option_cr))) + return ret; + + wait_flash_busy(sl); + + uint32_t cr_reg = (1 << FLASH_C0_CR_OPTSTRT); + if ((ret = stlink_write_debug32(sl, FLASH_C0_CR, cr_reg))) + return ret; + + wait_flash_busy(sl); + + if ((ret = check_flash_error(sl))) + return ret; + + // trigger the load of option bytes into option registers + cr_reg = (1 << FLASH_C0_CR_OBL_LAUNCH); + stlink_write_debug32(sl, FLASH_C0_CR, cr_reg); + + return ret; +} + +/** + * Write option bytes C0 + * @param sl + * @param addr of the memory mapped option bytes + * @param base option bytes + * @param len of option bytes + * @return 0 on success, -ve on failure. + */ +static int32_t stlink_write_option_bytes_c0(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint32_t len) { +#if 0 + uint32_t val; + int32_t ret = 0; + (void)len; + uint32_t data; + + clear_flash_error(sl); + + write_uint32((unsigned char *)&data, *(uint32_t *)(base)); + WLOG("Writing option bytes %#10x to %#10x\n", data, addr); + stlink_write_debug32(sl, FLASH_C0_OPTR, data); + + stlink_read_debug32(sl, FLASH_C0_CR, &val); + val |= (1 << FLASH_C0_CR_OPTSTRT); + stlink_write_debug32(sl, FLASH_C0_CR, val); + + wait_flash_busy(sl); + + ret = check_flash_error(sl); + + // trigger the load of option bytes into option registers + stlink_read_debug32(sl, FLASH_C0_CR, &val); + val |= (1 << FLASH_C0_CR_OBL_LAUNCH); + stlink_write_debug32(sl, FLASH_C0_CR, val); + + return (ret); +#else + (void)addr; + (void)len; + + return stlink_write_option_control_register_c0(sl, *(uint32_t*)base); +#endif +} + /** * Read option control register F0 * @param sl @@ -745,7 +840,6 @@ int32_t stlink_read_option_bytes_generic(stlink_t *sl, uint32_t *option_byte) { return stlink_read_debug32(sl, sl->option_base, option_byte); } - /** * Write option bytes * @param sl @@ -785,6 +879,9 @@ int32_t stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t *base } switch (sl->flash_type) { + case STM32_FLASH_TYPE_C0: + ret = stlink_write_option_bytes_c0(sl, addr, base, len); + break; case STM32_FLASH_TYPE_F0_F1_F3: case STM32_FLASH_TYPE_F1_XL: ret = stlink_write_option_bytes_f0(sl, addr, base, len); @@ -870,6 +967,8 @@ int32_t stlink_read_option_control_register32(stlink_t *sl, uint32_t *option_byt } switch (sl->flash_type) { + case STM32_FLASH_TYPE_C0: + return stlink_read_option_control_register_c0(sl, option_byte); case STM32_FLASH_TYPE_F0_F1_F3: case STM32_FLASH_TYPE_F1_XL: return stlink_read_option_control_register_f0(sl, option_byte); @@ -904,6 +1003,9 @@ int32_t stlink_write_option_control_register32(stlink_t *sl, uint32_t option_cr) } switch (sl->flash_type) { + case STM32_FLASH_TYPE_C0: + ret = stlink_write_option_control_register_c0(sl, option_cr); + break; case STM32_FLASH_TYPE_F0_F1_F3: case STM32_FLASH_TYPE_F1_XL: ret = stlink_write_option_control_register_f0(sl, option_cr); @@ -1009,6 +1111,9 @@ int32_t stlink_read_option_bytes32(stlink_t *sl, uint32_t *option_byte) { } switch (sl->chip_id) { + case STM32_CHIPID_C011xx: + case STM32_CHIPID_C031xx: + return stlink_read_option_bytes_c0(sl, option_byte); case STM32_CHIPID_F2: return stlink_read_option_bytes_f2(sl, option_byte); case STM32_CHIPID_F4: From eb083ae7539eccd3532156a829b3a8008736485b Mon Sep 17 00:00:00 2001 From: rcubee Date: Sat, 11 Nov 2023 17:40:28 +0100 Subject: [PATCH 479/503] removed redundant lines --- src/stlink-lib/option_bytes.c | 28 ---------------------------- 1 file changed, 28 deletions(-) diff --git a/src/stlink-lib/option_bytes.c b/src/stlink-lib/option_bytes.c index 2ee45c901..d49c346ef 100644 --- a/src/stlink-lib/option_bytes.c +++ b/src/stlink-lib/option_bytes.c @@ -79,38 +79,10 @@ static int32_t stlink_write_option_control_register_c0(stlink_t *sl, uint32_t op * @return 0 on success, -ve on failure. */ static int32_t stlink_write_option_bytes_c0(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint32_t len) { -#if 0 - uint32_t val; - int32_t ret = 0; - (void)len; - uint32_t data; - - clear_flash_error(sl); - - write_uint32((unsigned char *)&data, *(uint32_t *)(base)); - WLOG("Writing option bytes %#10x to %#10x\n", data, addr); - stlink_write_debug32(sl, FLASH_C0_OPTR, data); - - stlink_read_debug32(sl, FLASH_C0_CR, &val); - val |= (1 << FLASH_C0_CR_OPTSTRT); - stlink_write_debug32(sl, FLASH_C0_CR, val); - - wait_flash_busy(sl); - - ret = check_flash_error(sl); - - // trigger the load of option bytes into option registers - stlink_read_debug32(sl, FLASH_C0_CR, &val); - val |= (1 << FLASH_C0_CR_OBL_LAUNCH); - stlink_write_debug32(sl, FLASH_C0_CR, val); - - return (ret); -#else (void)addr; (void)len; return stlink_write_option_control_register_c0(sl, *(uint32_t*)base); -#endif } /** From 4a7b8cdb2678e64fccedf4f49508c4f5ce80868e Mon Sep 17 00:00:00 2001 From: rcubee Date: Sat, 11 Nov 2023 18:19:04 +0100 Subject: [PATCH 480/503] removed the patch file itself --- c0.patch | 618 ------------------------------------------------------- 1 file changed, 618 deletions(-) delete mode 100644 c0.patch diff --git a/c0.patch b/c0.patch deleted file mode 100644 index 5b59834d6..000000000 --- a/c0.patch +++ /dev/null @@ -1,618 +0,0 @@ -diff --git a/doc/supported_devices.md b/doc/supported_devices.md -index 2e96dcd..103c7fb 100644 ---- a/doc/supported_devices.md -+++ b/doc/supported_devices.md -@@ -6,6 +6,7 @@ More commonly these are: - | Product-Family | ARM Cortex Core | Product Line | - | -------------- | --------------- | ---------------------------------------------------------- | - | STM32F0 | M0 | | -+| STM32C0 | M0+ | | - | STM32G0 | M0+ | | - | STM32L0 | M0+ | | - | STM32F10**0** | M3 | Value line | -diff --git a/inc/stm32.h b/inc/stm32.h -index cf9a8a2..017ea0a 100644 ---- a/inc/stm32.h -+++ b/inc/stm32.h -@@ -51,17 +51,18 @@ enum stm32_core_id { - /* STM32 flash types */ - enum stm32_flash_type { - STM32_FLASH_TYPE_UNKNOWN = 0, -- STM32_FLASH_TYPE_F0_F1_F3 = 1, -- STM32_FLASH_TYPE_F1_XL = 2, -- STM32_FLASH_TYPE_F2_F4 = 3, -- STM32_FLASH_TYPE_F7 = 4, -- STM32_FLASH_TYPE_G0 = 5, -- STM32_FLASH_TYPE_G4 = 6, -- STM32_FLASH_TYPE_H7 = 7, -- STM32_FLASH_TYPE_L0_L1 = 8, -- STM32_FLASH_TYPE_L4 = 9, -- STM32_FLASH_TYPE_L5_U5_H5 = 10, -- STM32_FLASH_TYPE_WB_WL = 11, -+ STM32_FLASH_TYPE_C0 = 1, -+ STM32_FLASH_TYPE_F0_F1_F3 = 2, -+ STM32_FLASH_TYPE_F1_XL = 3, -+ STM32_FLASH_TYPE_F2_F4 = 4, -+ STM32_FLASH_TYPE_F7 = 5, -+ STM32_FLASH_TYPE_G0 = 6, -+ STM32_FLASH_TYPE_G4 = 7, -+ STM32_FLASH_TYPE_H7 = 8, -+ STM32_FLASH_TYPE_L0_L1 = 9, -+ STM32_FLASH_TYPE_L4 = 10, -+ STM32_FLASH_TYPE_L5_U5_H5 = 11, -+ STM32_FLASH_TYPE_WB_WL = 12, - }; - - /* STM32 chip-ids */ -@@ -102,6 +103,7 @@ enum stm32_chipids { - STM32_CHIPID_F0 = 0x440, - STM32_CHIPID_F412 = 0x441, - STM32_CHIPID_F09x = 0x442, -+ STM32_CHIPID_C011xx = 0x443, /* RM0490 (revision 3), section 26.10.1 "DBG device ID code register (DBG_IDCODE)" */ - STM32_CHIPID_F0xx_SMALL = 0x444, - STM32_CHIPID_F04 = 0x445, - STM32_CHIPID_F303_HD = 0x446, /* high density */ -@@ -111,6 +113,7 @@ enum stm32_chipids { - STM32_CHIPID_H74xxx = 0x450, /* RM0433, p.3189 */ - STM32_CHIPID_F76xxx = 0x451, - STM32_CHIPID_F72xxx = 0x452, /* Nucleo F722ZE board */ -+ STM32_CHIPID_C031xx = 0x453, /* RM0490 (revision 3), section 26.10.1 "DBG device ID code register (DBG_IDCODE)" */ - STM32_CHIPID_G0_CAT4 = 0x456, /* G051/G061 */ - STM32_CHIPID_L0_CAT1 = 0x457, - STM32_CHIPID_F410 = 0x458, -@@ -136,6 +139,8 @@ enum stm32_chipids { - }; - - /* Constant STM32 option bytes base memory address */ -+#define STM32_C0_OPTION_BYTES_BASE ((uint32_t)0x1fff7800) -+ - #define STM32_F4_OPTION_BYTES_BASE ((uint32_t)0x40023c14) - - #define STM32_H7_OPTION_BYTES_BASE ((uint32_t)0x5200201c) -@@ -189,6 +194,9 @@ enum stm32_chipids { - #define STM32WB_DBGMCU_APB1FZR1_WWDG_STOP 11 - #define STM32WB_DBGMCU_APB1FZR1_IWDG_STOP 12 - -+#define STM32C0_RCC_AHBENR 0x40021038 // RM0490 (revision 3), section 5.4.25 "RCC register map" -+#define STM32C0_RCC_DMAEN 0x00000001 // DMAEN // RM0490 (revision 3), section 5.4.25 "RCC register map" -+ - #define STM32F1_RCC_AHBENR 0x40021014 - #define STM32F1_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN - -diff --git a/inc/stm32flash.h b/inc/stm32flash.h -index 69c6206..b5e47e0 100644 ---- a/inc/stm32flash.h -+++ b/inc/stm32flash.h -@@ -58,6 +58,30 @@ - #define FLASH_OBR_OFF ((uint32_t)0x1c) - #define FLASH_WRPR_OFF ((uint32_t)0x20) - -+// == STM32C0 == (RM0490) -+// C0 Flash registers -+#define FLASH_C0_REGS_ADDR ((uint32_t)0x40022000) -+#define FLASH_C0_KEYR (FLASH_C0_REGS_ADDR + 0x08) -+#define FLASH_C0_OPT_KEYR (FLASH_C0_REGS_ADDR + 0x0C) -+#define FLASH_C0_SR (FLASH_C0_REGS_ADDR + 0x10) -+#define FLASH_C0_CR (FLASH_C0_REGS_ADDR + 0x14) -+#define FLASH_C0_OPTR (FLASH_C0_REGS_ADDR + 0x20) -+ -+// C0 Flash control register -+#define FLASH_C0_CR_PNB 3 -+#define FLASH_C0_CR_STRT 16 -+#define FLASH_C0_CR_OPTSTRT 17 -+#define FLASH_C0_CR_OBL_LAUNCH 27 -+#define FLASH_C0_CR_OPTLOCK 30 -+#define FLASH_C0_CR_LOCK 31 -+ -+// C0 Flash status register -+#define FLASH_C0_SR_ERROR_MASK 0xC3F8 // [15:14], [9:3] -+#define FLASH_C0_SR_PROGERR 3 -+#define FLASH_C0_SR_WRPERR 4 -+#define FLASH_C0_SR_PGAERR 5 -+#define FLASH_C0_SR_BSY 16 -+ - // == STM32F0 == - #define FLASH_F0_OPTKEY1 0x45670123 - #define FLASH_F0_OPTKEY2 0xcdef89ab -diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c -index 06edb26..86f01f4 100644 ---- a/src/stlink-lib/chipid.c -+++ b/src/stlink-lib/chipid.c -@@ -97,7 +97,9 @@ void process_chipfile(char *fname) { - buf[strlen(buf) - 1] = 0; // chomp newline - sscanf(buf, "%*s %n", &nc); - // Match human readable flash_type with enum stm32_flash_type { }. -- if (strcmp(value, "F0_F1_F3") == 0) { -+ if(strcmp(value, "C0") == 0) { -+ ts->flash_type = STM32_FLASH_TYPE_C0; -+ } else if (strcmp(value, "F0_F1_F3") == 0) { - ts->flash_type = STM32_FLASH_TYPE_F0_F1_F3; - } else if (strcmp(value, "F1_XL") == 0) { - ts->flash_type = STM32_FLASH_TYPE_F1_XL; -diff --git a/src/stlink-lib/common_flash.c b/src/stlink-lib/common_flash.c -index 3038b53..491cf46 100644 ---- a/src/stlink-lib/common_flash.c -+++ b/src/stlink-lib/common_flash.c -@@ -46,7 +46,9 @@ uint32_t get_stm32l0_flash_base(stlink_t *sl) { - uint32_t read_flash_cr(stlink_t *sl, uint32_t bank) { - uint32_t reg, res; - -- if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { -+ if (sl->flash_type == STM32_FLASH_TYPE_C0) { -+ reg = FLASH_C0_CR; -+ } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { - reg = FLASH_F4_CR; - } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { - reg = FLASH_F7_CR; -@@ -77,7 +79,10 @@ void lock_flash(stlink_t *sl) { - uint32_t cr_lock_shift = 0, cr_reg = 0, n = 0, cr2_reg = 0; - uint32_t cr_mask = 0xffffffffu; - -- if (sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) { -+ if (sl->flash_type == STM32_FLASH_TYPE_C0) { -+ cr_reg = FLASH_C0_CR; -+ cr_lock_shift = FLASH_C0_CR_LOCK; -+ } else if (sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) { - cr_reg = FLASH_CR; - cr_lock_shift = FLASH_CR_LOCK; - } else if (sl->flash_type == STM32_FLASH_TYPE_F1_XL) { -@@ -132,8 +137,10 @@ void lock_flash(stlink_t *sl) { - static inline int32_t write_flash_sr(stlink_t *sl, uint32_t bank, uint32_t val) { - uint32_t sr_reg; - -- if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || -- (sl->flash_type == STM32_FLASH_TYPE_F1_XL)) { -+ if (sl->flash_type == STM32_FLASH_TYPE_C0) { -+ sr_reg = FLASH_C0_SR; -+ } else if (sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3 || -+ sl->flash_type == STM32_FLASH_TYPE_F1_XL) { - sr_reg = (bank == BANK_1) ? FLASH_SR : FLASH_SR2; - } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { - sr_reg = FLASH_F4_SR; -@@ -162,6 +169,9 @@ static inline int32_t write_flash_sr(stlink_t *sl, uint32_t bank, uint32_t val) - - void clear_flash_error(stlink_t *sl) { - switch (sl->flash_type) { -+ case STM32_FLASH_TYPE_C0: -+ write_flash_sr(sl, BANK_1, FLASH_C0_SR_ERROR_MASK); -+ break; - case STM32_FLASH_TYPE_F0_F1_F3: - write_flash_sr(sl, BANK_1, FLASH_SR_ERROR_MASK); - break; -@@ -205,8 +215,10 @@ void clear_flash_error(stlink_t *sl) { - uint32_t read_flash_sr(stlink_t *sl, uint32_t bank) { - uint32_t res, sr_reg; - -- if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || -- (sl->flash_type == STM32_FLASH_TYPE_F1_XL)) { -+ if (sl->flash_type == STM32_FLASH_TYPE_C0) { -+ sr_reg = FLASH_C0_SR; -+ } else if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || -+ (sl->flash_type == STM32_FLASH_TYPE_F1_XL)) { - sr_reg = (bank == BANK_1) ? FLASH_SR : FLASH_SR2; - } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { - sr_reg = FLASH_F4_SR; -@@ -238,9 +250,11 @@ uint32_t is_flash_busy(stlink_t *sl) { - uint32_t sr_busy_shift; - uint32_t res; - -- if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || -- (sl->flash_type == STM32_FLASH_TYPE_F1_XL) || -- (sl->flash_type == STM32_FLASH_TYPE_L0_L1)) { -+ if (sl->flash_type == STM32_FLASH_TYPE_C0) { -+ sr_busy_shift = FLASH_C0_SR_BSY; -+ } else if (sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3 || -+ sl->flash_type == STM32_FLASH_TYPE_F1_XL || -+ sl->flash_type == STM32_FLASH_TYPE_L0_L1) { - sr_busy_shift = FLASH_SR_BSY; - } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { - sr_busy_shift = FLASH_F4_SR_BSY; -@@ -286,6 +300,12 @@ int32_t check_flash_error(stlink_t *sl) { - WRPERR = PROGERR = PGAERR = 0; - - switch (sl->flash_type) { -+ case STM32_FLASH_TYPE_C0: -+ res = read_flash_sr(sl, BANK_1) & FLASH_C0_SR_ERROR_MASK; -+ WRPERR = (1 << FLASH_C0_SR_WRPERR); -+ PROGERR = (1 << FLASH_C0_SR_PROGERR); -+ PGAERR = (1 << FLASH_C0_SR_PGAERR); -+ break; - case STM32_FLASH_TYPE_F0_F1_F3: - case STM32_FLASH_TYPE_F1_XL: - res = read_flash_sr(sl, BANK_1) & FLASH_SR_ERROR_MASK; -@@ -382,8 +402,11 @@ static inline uint32_t is_flash_locked(stlink_t *sl) { - uint32_t cr_reg; - uint32_t n; - -- if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || -- (sl->flash_type == STM32_FLASH_TYPE_F1_XL)) { -+ if (sl->flash_type == STM32_FLASH_TYPE_C0) { -+ cr_reg = FLASH_C0_CR; -+ cr_lock_shift = FLASH_C0_CR_LOCK; -+ } else if (sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3 || -+ sl->flash_type == STM32_FLASH_TYPE_F1_XL) { - cr_reg = FLASH_CR; - cr_lock_shift = FLASH_CR_LOCK; - } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { -@@ -429,7 +452,9 @@ static void unlock_flash(stlink_t *sl) { - * definitive lock of the FPEC block until next reset. - */ - -- if (sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) { -+ if (sl->flash_type == STM32_FLASH_TYPE_C0) { -+ key_reg = FLASH_C0_KEYR; -+ } else if (sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) { - key_reg = FLASH_KEYR; - } else if (sl->flash_type == STM32_FLASH_TYPE_F1_XL) { - key_reg = FLASH_KEYR; -@@ -497,6 +522,10 @@ int32_t lock_flash_option(stlink_t *sl) { - int32_t active_bit_level = 1; - - switch (sl->flash_type) { -+ case STM32_FLASH_TYPE_C0: -+ optcr_reg = FLASH_C0_CR; -+ optlock_shift = FLASH_C0_CR_OPTLOCK; -+ break; - case STM32_FLASH_TYPE_F0_F1_F3: - case STM32_FLASH_TYPE_F1_XL: - optcr_reg = FLASH_CR; -@@ -574,6 +603,10 @@ static bool is_flash_option_locked(stlink_t *sl) { - uint32_t n; - - switch (sl->flash_type) { -+ case STM32_FLASH_TYPE_C0: -+ optcr_reg = FLASH_C0_CR; -+ optlock_shift = FLASH_C0_CR_OPTLOCK; -+ break; - case STM32_FLASH_TYPE_F0_F1_F3: - case STM32_FLASH_TYPE_F1_XL: - optcr_reg = FLASH_CR; -@@ -633,6 +666,9 @@ static int32_t unlock_flash_option(stlink_t *sl) { - uint32_t optkey2 = FLASH_OPTKEY2; - - switch (sl->flash_type) { -+ case STM32_FLASH_TYPE_C0: -+ optkey_reg = FLASH_C0_OPT_KEYR; -+ break; - case STM32_FLASH_TYPE_F0_F1_F3: - case STM32_FLASH_TYPE_F1_XL: - optkey_reg = FLASH_OPTKEYR; -@@ -726,7 +762,9 @@ void clear_flash_cr_pg(stlink_t *sl, uint32_t bank) { - uint32_t cr_reg, n; - uint32_t bit = FLASH_CR_PG; - -- if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { -+ if (sl->flash_type == STM32_FLASH_TYPE_C0) { -+ cr_reg = FLASH_C0_CR; -+ } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { - cr_reg = FLASH_F4_CR; - } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { - cr_reg = FLASH_F7_CR; -@@ -802,8 +840,10 @@ static inline void write_flash_cr_snb(stlink_t *sl, uint32_t n, uint32_t bank) { - static void set_flash_cr_per(stlink_t *sl, uint32_t bank) { - uint32_t cr_reg, val; - -- if (sl->flash_type == STM32_FLASH_TYPE_G0 || -- sl->flash_type == STM32_FLASH_TYPE_G4) { -+ if (sl->flash_type == STM32_FLASH_TYPE_C0) { -+ cr_reg = FLASH_C0_CR; -+ } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || -+ sl->flash_type == STM32_FLASH_TYPE_G4) { - cr_reg = FLASH_Gx_CR; - } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5_H5) { - cr_reg = FLASH_L5_NSCR; -@@ -821,8 +861,10 @@ static void set_flash_cr_per(stlink_t *sl, uint32_t bank) { - static void clear_flash_cr_per(stlink_t *sl, uint32_t bank) { - uint32_t cr_reg; - -- if (sl->flash_type == STM32_FLASH_TYPE_G0 || -- sl->flash_type == STM32_FLASH_TYPE_G4) { -+ if (sl->flash_type == STM32_FLASH_TYPE_C0) { -+ cr_reg = FLASH_C0_CR; -+ } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || -+ sl->flash_type == STM32_FLASH_TYPE_G4) { - cr_reg = FLASH_Gx_CR; - } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5_H5) { - cr_reg = FLASH_L5_NSCR; -@@ -855,7 +897,10 @@ static inline void write_flash_cr_bker_pnb(stlink_t *sl, uint32_t n) { - static void set_flash_cr_strt(stlink_t *sl, uint32_t bank) { - uint32_t val, cr_reg, cr_strt; - -- if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { -+ if (sl->flash_type == STM32_FLASH_TYPE_C0) { -+ cr_reg = FLASH_C0_CR; -+ cr_strt = 1 << FLASH_C0_CR_STRT; -+ } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { - cr_reg = FLASH_F4_CR; - cr_strt = 1 << FLASH_F4_CR_STRT; - } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { -@@ -890,7 +935,11 @@ static void set_flash_cr_strt(stlink_t *sl, uint32_t bank) { - static void set_flash_cr_mer(stlink_t *sl, bool v, uint32_t bank) { - uint32_t val, cr_reg, cr_mer, cr_pg; - -- if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { -+ if (sl->flash_type == STM32_FLASH_TYPE_C0) { -+ cr_reg = FLASH_C0_CR; -+ cr_mer = 1 << FLASH_CR_MER; -+ cr_pg = 1 << FLASH_CR_PG; -+ } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { - cr_reg = FLASH_F4_CR; - cr_mer = 1 << FLASH_CR_MER; - cr_pg = 1 << FLASH_CR_PG; -@@ -1062,7 +1111,8 @@ int32_t stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { - } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || - sl->flash_type == STM32_FLASH_TYPE_G4 || - sl->flash_type == STM32_FLASH_TYPE_L5_U5_H5 || -- sl->flash_type == STM32_FLASH_TYPE_WB_WL) { -+ sl->flash_type == STM32_FLASH_TYPE_WB_WL || -+ sl->flash_type == STM32_FLASH_TYPE_C0) { - uint32_t val; - unlock_flash_if(sl); - set_flash_cr_per(sl, BANK_1); // set the 'enable Flash erase' bit -@@ -1107,6 +1157,14 @@ int32_t stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { - val |= ((flash_page & 0xFF) << 3); - - stlink_write_debug32(sl, FLASH_WB_CR, val); -+ } else if (sl->flash_type == STM32_FLASH_TYPE_C0) { -+ uint32_t flash_page = ((flashaddr - STM32_FLASH_BASE) / sl->flash_pgsz); -+ stlink_read_debug32(sl, FLASH_C0_CR, &val); -+ -+ val &= ~(0xF << FLASH_C0_CR_PNB); -+ val |= ((flash_page & 0xF) << FLASH_C0_CR_PNB); -+ -+ stlink_write_debug32(sl, FLASH_C0_CR, val); - } - - set_flash_cr_strt(sl, BANK_1); // set the 'start operation' bit -diff --git a/src/stlink-lib/flash_loader.c b/src/stlink-lib/flash_loader.c -index ea1f6d9..0d01dfd 100644 ---- a/src/stlink-lib/flash_loader.c -+++ b/src/stlink-lib/flash_loader.c -@@ -491,12 +491,15 @@ static void set_flash_cr_pg(stlink_t *sl, uint32_t bank) { - - x = read_flash_cr(sl, bank); - -- if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { -+ if (sl->flash_type == STM32_FLASH_TYPE_C0) { -+ cr_reg = FLASH_C0_CR; -+ x |= (1 << FLASH_CR_PG); -+ } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { - cr_reg = FLASH_F4_CR; -- x |= 1 << FLASH_CR_PG; -+ x |= (1 << FLASH_CR_PG); - } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { - cr_reg = FLASH_F7_CR; -- x |= 1 << FLASH_CR_PG; -+ x |= (1 << FLASH_CR_PG); - } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { - cr_reg = FLASH_L4_CR; - x &= ~FLASH_L4_CR_OPBITS; -@@ -528,6 +531,10 @@ static void set_dma_state(stlink_t *sl, flash_loader_t *fl, int32_t bckpRstr) { - rcc = rcc_dma_mask = value = 0; - - switch (sl->flash_type) { -+ case STM32_FLASH_TYPE_C0: -+ rcc = STM32C0_RCC_AHBENR; -+ rcc_dma_mask = STM32C0_RCC_DMAEN; -+ break; - case STM32_FLASH_TYPE_F0_F1_F3: - case STM32_FLASH_TYPE_F1_XL: - rcc = STM32F1_RCC_AHBENR; -@@ -639,8 +646,9 @@ int32_t stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { - } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL || - sl->flash_type == STM32_FLASH_TYPE_G0 || - sl->flash_type == STM32_FLASH_TYPE_G4 || -- sl->flash_type == STM32_FLASH_TYPE_L5_U5_H5) { -- ILOG("Starting Flash write for WB/G0/G4/L5/U5/H5\n"); -+ sl->flash_type == STM32_FLASH_TYPE_L5_U5_H5 || -+ sl->flash_type == STM32_FLASH_TYPE_C0) { -+ ILOG("Starting Flash write for WB/G0/G4/L5/U5/H5/C0\n"); - - unlock_flash_if(sl); // unlock flash if necessary - set_flash_cr_pg(sl, BANK_1); // set PG 'allow programming' bit -@@ -720,6 +728,7 @@ int32_t stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { - - int32_t stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t addr, uint8_t *base, uint32_t len) { - uint32_t off; -+ - if ((sl->flash_type == STM32_FLASH_TYPE_F2_F4) || - (sl->flash_type == STM32_FLASH_TYPE_F7) || - (sl->flash_type == STM32_FLASH_TYPE_L4)) { -@@ -737,13 +746,14 @@ int32_t stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t - } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL || - sl->flash_type == STM32_FLASH_TYPE_G0 || - sl->flash_type == STM32_FLASH_TYPE_G4 || -- sl->flash_type == STM32_FLASH_TYPE_L5_U5_H5) { -+ sl->flash_type == STM32_FLASH_TYPE_L5_U5_H5 || -+ sl->flash_type == STM32_FLASH_TYPE_C0) { - DLOG("Starting %3u page write\n", len / sl->flash_pgsz); - for (off = 0; off < len; off += sizeof(uint32_t)) { - uint32_t data; - - if ((off % sl->flash_pgsz) > (sl->flash_pgsz - 5)) { -- fprintf(stdout, "\r%3u/%3u pages written", (off / sl->flash_pgsz + 1), (len / sl->flash_pgsz)); -+ fprintf(stdout, "\r%3u/%-3u pages written", (off / sl->flash_pgsz + 1), (len / sl->flash_pgsz)); - fflush(stdout); - } - -@@ -782,7 +792,7 @@ int32_t stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t - uint32_t data; - - if ((off % sl->flash_pgsz) > (sl->flash_pgsz - 5)) { -- fprintf(stdout, "\r%3u/%3u pages written", (off / sl->flash_pgsz + 1), (len / sl->flash_pgsz)); -+ fprintf(stdout, "\r%3u/%-3u pages written", (off / sl->flash_pgsz + 1), (len / sl->flash_pgsz)); - fflush(stdout); - } - -@@ -819,7 +829,7 @@ int32_t stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t - if (sl->verbose >= 1) { - // show progress; writing procedure is slow and previous errors are - // misleading -- fprintf(stdout, "\r%3u/%3u pages written", ++write_block_count, -+ fprintf(stdout, "\r%3u/%-3u pages written", ++write_block_count, - (len + sl->flash_pgsz - 1) / sl->flash_pgsz); - fflush(stdout); - } -@@ -856,7 +866,8 @@ int32_t stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t - int32_t stlink_flashloader_stop(stlink_t *sl, flash_loader_t *fl) { - uint32_t dhcsr; - -- if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || -+ if ((sl->flash_type == STM32_FLASH_TYPE_C0) || -+ (sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || - (sl->flash_type == STM32_FLASH_TYPE_F1_XL) || - (sl->flash_type == STM32_FLASH_TYPE_F2_F4) || - (sl->flash_type == STM32_FLASH_TYPE_F7) || -diff --git a/src/stlink-lib/option_bytes.c b/src/stlink-lib/option_bytes.c -index ee03dce..2ee45c9 100644 ---- a/src/stlink-lib/option_bytes.c -+++ b/src/stlink-lib/option_bytes.c -@@ -18,6 +18,101 @@ - #include "md5.h" - #include "read_write.h" - -+/** -+ * Read option control register C0 -+ * @param sl -+ * @param option_byte -+ * @return 0 on success, -ve on failure. -+ */ -+static int32_t stlink_read_option_control_register_c0(stlink_t *sl, uint32_t *option_byte) { -+ return stlink_read_debug32(sl, FLASH_C0_OPTR, option_byte); -+} -+ -+/** -+ * Read option bytes C0 -+ * @param sl -+ * @param option_byte -+ * @return 0 on success, -ve on failure. -+ */ -+static int32_t stlink_read_option_bytes_c0(stlink_t *sl, uint32_t *option_byte) { -+ return stlink_read_option_control_register_c0(sl, option_byte); -+} -+ -+/** -+ * Write option control register C0 -+ * @param sl -+ * @param option_cr -+ * @return 0 on success, -ve on failure. -+ */ -+static int32_t stlink_write_option_control_register_c0(stlink_t *sl, uint32_t option_cr) { -+ int32_t ret = 0; -+ -+ clear_flash_error(sl); -+ -+ if ((ret = stlink_write_debug32(sl, FLASH_C0_OPTR, option_cr))) -+ return ret; -+ -+ wait_flash_busy(sl); -+ -+ uint32_t cr_reg = (1 << FLASH_C0_CR_OPTSTRT); -+ if ((ret = stlink_write_debug32(sl, FLASH_C0_CR, cr_reg))) -+ return ret; -+ -+ wait_flash_busy(sl); -+ -+ if ((ret = check_flash_error(sl))) -+ return ret; -+ -+ // trigger the load of option bytes into option registers -+ cr_reg = (1 << FLASH_C0_CR_OBL_LAUNCH); -+ stlink_write_debug32(sl, FLASH_C0_CR, cr_reg); -+ -+ return ret; -+} -+ -+/** -+ * Write option bytes C0 -+ * @param sl -+ * @param addr of the memory mapped option bytes -+ * @param base option bytes -+ * @param len of option bytes -+ * @return 0 on success, -ve on failure. -+ */ -+static int32_t stlink_write_option_bytes_c0(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint32_t len) { -+#if 0 -+ uint32_t val; -+ int32_t ret = 0; -+ (void)len; -+ uint32_t data; -+ -+ clear_flash_error(sl); -+ -+ write_uint32((unsigned char *)&data, *(uint32_t *)(base)); -+ WLOG("Writing option bytes %#10x to %#10x\n", data, addr); -+ stlink_write_debug32(sl, FLASH_C0_OPTR, data); -+ -+ stlink_read_debug32(sl, FLASH_C0_CR, &val); -+ val |= (1 << FLASH_C0_CR_OPTSTRT); -+ stlink_write_debug32(sl, FLASH_C0_CR, val); -+ -+ wait_flash_busy(sl); -+ -+ ret = check_flash_error(sl); -+ -+ // trigger the load of option bytes into option registers -+ stlink_read_debug32(sl, FLASH_C0_CR, &val); -+ val |= (1 << FLASH_C0_CR_OBL_LAUNCH); -+ stlink_write_debug32(sl, FLASH_C0_CR, val); -+ -+ return (ret); -+#else -+ (void)addr; -+ (void)len; -+ -+ return stlink_write_option_control_register_c0(sl, *(uint32_t*)base); -+#endif -+} -+ - /** - * Read option control register F0 - * @param sl -@@ -745,7 +840,6 @@ int32_t stlink_read_option_bytes_generic(stlink_t *sl, uint32_t *option_byte) { - return stlink_read_debug32(sl, sl->option_base, option_byte); - } - -- - /** - * Write option bytes - * @param sl -@@ -785,6 +879,9 @@ int32_t stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t *base - } - - switch (sl->flash_type) { -+ case STM32_FLASH_TYPE_C0: -+ ret = stlink_write_option_bytes_c0(sl, addr, base, len); -+ break; - case STM32_FLASH_TYPE_F0_F1_F3: - case STM32_FLASH_TYPE_F1_XL: - ret = stlink_write_option_bytes_f0(sl, addr, base, len); -@@ -870,6 +967,8 @@ int32_t stlink_read_option_control_register32(stlink_t *sl, uint32_t *option_byt - } - - switch (sl->flash_type) { -+ case STM32_FLASH_TYPE_C0: -+ return stlink_read_option_control_register_c0(sl, option_byte); - case STM32_FLASH_TYPE_F0_F1_F3: - case STM32_FLASH_TYPE_F1_XL: - return stlink_read_option_control_register_f0(sl, option_byte); -@@ -904,6 +1003,9 @@ int32_t stlink_write_option_control_register32(stlink_t *sl, uint32_t option_cr) - } - - switch (sl->flash_type) { -+ case STM32_FLASH_TYPE_C0: -+ ret = stlink_write_option_control_register_c0(sl, option_cr); -+ break; - case STM32_FLASH_TYPE_F0_F1_F3: - case STM32_FLASH_TYPE_F1_XL: - ret = stlink_write_option_control_register_f0(sl, option_cr); -@@ -1009,6 +1111,9 @@ int32_t stlink_read_option_bytes32(stlink_t *sl, uint32_t *option_byte) { - } - - switch (sl->chip_id) { -+ case STM32_CHIPID_C011xx: -+ case STM32_CHIPID_C031xx: -+ return stlink_read_option_bytes_c0(sl, option_byte); - case STM32_CHIPID_F2: - return stlink_read_option_bytes_f2(sl, option_byte); - case STM32_CHIPID_F4: From e286f243efaf73e4fec1cf99e532e695c6383316 Mon Sep 17 00:00:00 2001 From: Marcelo Barros de Almeida Date: Tue, 14 Nov 2023 00:27:19 -0300 Subject: [PATCH 481/503] Fixing support for U5 chips (original U5x5.chip was not handling all U5 chips ) --- config/chips/U535_U545.chip | 14 ++++++++++++++ config/chips/U55Fx_U5Gx.chip | 14 ++++++++++++++ config/chips/{U5x5.chip => U575_U585.chip} | 6 +++--- config/chips/U59x_U5Ax.chip | 14 ++++++++++++++ inc/stm32.h | 5 ++++- src/stlink-lib/common_flash.c | 12 ++++++++---- 6 files changed, 57 insertions(+), 8 deletions(-) create mode 100644 config/chips/U535_U545.chip create mode 100644 config/chips/U55Fx_U5Gx.chip rename config/chips/{U5x5.chip => U575_U585.chip} (67%) create mode 100644 config/chips/U59x_U5Ax.chip diff --git a/config/chips/U535_U545.chip b/config/chips/U535_U545.chip new file mode 100644 index 000000000..84ca3c914 --- /dev/null +++ b/config/chips/U535_U545.chip @@ -0,0 +1,14 @@ +# Chip-ID file for STM32U535 / STM32U545 device +# +dev_type STM32U535_U545 +ref_manual_id 0456 +chip_id 0x455 // STM32U535/545 +flash_type L5_U5_H5 +flash_size_reg 0x0bfa07a0 +flash_pagesize 0x2000 // 8 KB +sram_size 0x44800 // 274 KB +bootrom_base 0x0bf90000 +bootrom_size 0x8000 // 32 KB +option_base 0x0 +option_size 0x0 +flags none diff --git a/config/chips/U55Fx_U5Gx.chip b/config/chips/U55Fx_U5Gx.chip new file mode 100644 index 000000000..6c7eca784 --- /dev/null +++ b/config/chips/U55Fx_U5Gx.chip @@ -0,0 +1,14 @@ +# Chip-ID file for STM32U5Fx / STM32U5Gx device +# +dev_type STM32U5Fx_U5Gx +ref_manual_id 0456 +chip_id 0x476 // STM32U5Fx5/5Gx +flash_type L5_U5_H5 +flash_size_reg 0x0bfa07a0 +flash_pagesize 0x2000 // 8 KB +sram_size 0x2f4800 // 3026 KB +bootrom_base 0x0bf90000 +bootrom_size 0x8000 // 32 KB +option_base 0x0 +option_size 0x0 +flags none diff --git a/config/chips/U5x5.chip b/config/chips/U575_U585.chip similarity index 67% rename from config/chips/U5x5.chip rename to config/chips/U575_U585.chip index 82964b1c3..fa2fb86fa 100644 --- a/config/chips/U5x5.chip +++ b/config/chips/U575_U585.chip @@ -1,8 +1,8 @@ -# Chip-ID file for STM32U5x5 device +# Chip-ID file for STM32U575 / STM32U585 device # -dev_type STM32U5x5 +dev_type STM32U575_U585 ref_manual_id 0456 -chip_id 0x482 // STM32_CHIPID_U5x5 +chip_id 0x482 // STM32U575/585 flash_type L5_U5_H5 flash_size_reg 0x0bfa07a0 flash_pagesize 0x2000 // 8 KB diff --git a/config/chips/U59x_U5Ax.chip b/config/chips/U59x_U5Ax.chip new file mode 100644 index 000000000..6be20855e --- /dev/null +++ b/config/chips/U59x_U5Ax.chip @@ -0,0 +1,14 @@ +# Chip-ID file for STM32U59x / STM32U5Ax device +# +dev_type STM32U59x_U5Ax +ref_manual_id 0456 +chip_id 0x481 // STM32U59x/5Ax +flash_type L5_U5_H5 +flash_size_reg 0x0bfa07a0 +flash_pagesize 0x2000 // 8 KB +sram_size 0x274800 // 2514 KB +bootrom_base 0x0bf90000 +bootrom_size 0x8000 // 32 KB +option_base 0x0 +option_size 0x0 +flags none diff --git a/inc/stm32.h b/inc/stm32.h index cf9a8a2ad..b716ac44e 100644 --- a/inc/stm32.h +++ b/inc/stm32.h @@ -111,6 +111,7 @@ enum stm32_chipids { STM32_CHIPID_H74xxx = 0x450, /* RM0433, p.3189 */ STM32_CHIPID_F76xxx = 0x451, STM32_CHIPID_F72xxx = 0x452, /* Nucleo F722ZE board */ + STM32_CHIPID_U535_U545 = 0x455, /* RM0456, p.3604 */ STM32_CHIPID_G0_CAT4 = 0x456, /* G051/G061 */ STM32_CHIPID_L0_CAT1 = 0x457, STM32_CHIPID_F410 = 0x458, @@ -126,9 +127,11 @@ enum stm32_chipids { STM32_CHIPID_L4Rx = 0x470, /* RM0432, p.2247, found on the STM32L4R9I-DISCO board */ STM32_CHIPID_L4PX = 0x471, /* RM0432, p.2247 */ STM32_CHIPID_L5x2xx = 0x472, /* RM0438, p.2157 */ + STM32_CHIPID_U5Fx_U5Gx = 0x476, /* RM0456, p.3604 */ STM32_CHIPID_G4_CAT4 = 0x479, STM32_CHIPID_H7Ax = 0x480, /* RM0455, p.2863 */ - STM32_CHIPID_U5x5 = 0x482, /* RM0456, p.2991 */ + STM32_CHIPID_U59x_U5Ax = 0x481, /* RM0456, p.3604 */ + STM32_CHIPID_U575_U585 = 0x482, /* RM0456, p.3604 */ STM32_CHIPID_H72x = 0x483, /* RM0468, p.3199 */ STM32_CHIPID_H5xx = 0x484, /* RM0481, p.3085 */ STM32_CHIPID_WB55 = 0x495, diff --git a/src/stlink-lib/common_flash.c b/src/stlink-lib/common_flash.c index 3038b53e7..ab754cb77 100644 --- a/src/stlink-lib/common_flash.c +++ b/src/stlink-lib/common_flash.c @@ -1082,10 +1082,12 @@ int32_t stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { val &= ~(0x7F << 3); val |= ((flash_page & 0x7F) << 3) | (1 << FLASH_CR_PER); stlink_write_debug32(sl, FLASH_Gx_CR, val); + // STM32L5x2xx has two banks with 2k pages or single with 4k pages + // STM32H5xx, STM32U535, STM32U545, STM32U575 or STM32U585 have 2 banks with 8k pages } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5_H5) { uint32_t flash_page; stlink_read_debug32(sl, FLASH_L5_NSCR, &val); - if (sl->flash_pgsz == 0x800 && (flashaddr - STM32_FLASH_BASE) >= sl->flash_size/2) { + if ((sl->flash_pgsz == 0x800 || sl->flash_pgsz == 0x2000) && (flashaddr - STM32_FLASH_BASE) >= sl->flash_size/2) { flash_page = (flashaddr - STM32_FLASH_BASE - sl->flash_size/2) / sl->flash_pgsz; // set bank 2 for erasure val |= (1 << FLASH_L5_NSCR_NSBKER); @@ -1094,9 +1096,11 @@ int32_t stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { // set bank 1 for erasure val &= ~(1 << FLASH_L5_NSCR_NSBKER); } - // sec 6.9.9 - val &= ~(0x7F << 3); - val |= ((flash_page & 0x7F) << 3) | (1 << FLASH_CR_PER); + // sec 7.9.9 for U5, 6.9.9 for L5 (for L7 we have 7 bits instead 8 bits for U5 but + // the bit position for 8th bit reserved. + // Maybe the best solution is to handle each one separately. + val &= ~(0xFF << 3); + val |= ((flash_page & 0xFF) << 3) | (1 << FLASH_CR_PER); stlink_write_debug32(sl, FLASH_L5_NSCR, val); } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { uint32_t flash_page = ((flashaddr - STM32_FLASH_BASE) / sl->flash_pgsz); From 5df53adb2c65f100c307824034b49eccd24931f3 Mon Sep 17 00:00:00 2001 From: Marcelo Barros de Almeida Date: Tue, 14 Nov 2023 07:39:56 -0300 Subject: [PATCH 482/503] Missing swo and dualback flags in U6 chip models --- config/chips/U535_U545.chip | 2 +- config/chips/U55Fx_U5Gx.chip | 2 +- config/chips/U575_U585.chip | 2 +- config/chips/U59x_U5Ax.chip | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/config/chips/U535_U545.chip b/config/chips/U535_U545.chip index 84ca3c914..adc0560dd 100644 --- a/config/chips/U535_U545.chip +++ b/config/chips/U535_U545.chip @@ -11,4 +11,4 @@ bootrom_base 0x0bf90000 bootrom_size 0x8000 // 32 KB option_base 0x0 option_size 0x0 -flags none +flags swo dualbank diff --git a/config/chips/U55Fx_U5Gx.chip b/config/chips/U55Fx_U5Gx.chip index 6c7eca784..b9c79b235 100644 --- a/config/chips/U55Fx_U5Gx.chip +++ b/config/chips/U55Fx_U5Gx.chip @@ -11,4 +11,4 @@ bootrom_base 0x0bf90000 bootrom_size 0x8000 // 32 KB option_base 0x0 option_size 0x0 -flags none +flags swo dualbank diff --git a/config/chips/U575_U585.chip b/config/chips/U575_U585.chip index fa2fb86fa..6724d00f5 100644 --- a/config/chips/U575_U585.chip +++ b/config/chips/U575_U585.chip @@ -11,4 +11,4 @@ bootrom_base 0x0bf90000 bootrom_size 0x10000 // 64 KB option_base 0x0 option_size 0x0 -flags none +flags swo dualbank diff --git a/config/chips/U59x_U5Ax.chip b/config/chips/U59x_U5Ax.chip index 6be20855e..9b45a411c 100644 --- a/config/chips/U59x_U5Ax.chip +++ b/config/chips/U59x_U5Ax.chip @@ -11,4 +11,4 @@ bootrom_base 0x0bf90000 bootrom_size 0x8000 // 32 KB option_base 0x0 option_size 0x0 -flags none +flags swo dualbank From 3fd714052485156f7be332d0da1d8bbc30ccbce8 Mon Sep 17 00:00:00 2001 From: rcubee Date: Tue, 14 Nov 2023 17:30:00 +0100 Subject: [PATCH 483/503] forgot to include these --- config/chips/C011xx.chip | 14 ++++++++++++++ config/chips/C031xx.chip | 14 ++++++++++++++ 2 files changed, 28 insertions(+) create mode 100644 config/chips/C011xx.chip create mode 100644 config/chips/C031xx.chip diff --git a/config/chips/C011xx.chip b/config/chips/C011xx.chip new file mode 100644 index 000000000..9124c6a1e --- /dev/null +++ b/config/chips/C011xx.chip @@ -0,0 +1,14 @@ +# Chip-ID file for STM32C011xx device +# +dev_type STM32C011xx +ref_manual_id 0490 +chip_id 0x453 // STM32_CHIPID_C011xx +flash_type C0 +flash_size_reg 0x1fff75a0 +flash_pagesize 0x800 // 2 KB +sram_size 0x1800 // 6 KB +bootrom_base 0x1fff0000 +bootrom_size 0x1800 // 6 KB +option_base 0x1fff7800 // STM32_C0_OPTION_BYTES_BASE +option_size 0x80 // 128 B +flags none diff --git a/config/chips/C031xx.chip b/config/chips/C031xx.chip new file mode 100644 index 000000000..30017ae90 --- /dev/null +++ b/config/chips/C031xx.chip @@ -0,0 +1,14 @@ +# Chip-ID file for STM32C031xx device +# +dev_type STM32C031xx +ref_manual_id 0490 +chip_id 0x453 // STM32_CHIPID_C031xx +flash_type C0 +flash_size_reg 0x1fff75a0 +flash_pagesize 0x800 // 2 KB +sram_size 0x3000 // 12 KB +bootrom_base 0x1fff0000 +bootrom_size 0x1800 // 6 KB +option_base 0x1fff7800 // STM32_C0_OPTION_BYTES_BASE +option_size 0x80 // 128 B +flags none From cf840b5f3d8d4154efb8058adeddb20e14c934cd Mon Sep 17 00:00:00 2001 From: rcubee Date: Tue, 14 Nov 2023 17:38:12 +0100 Subject: [PATCH 484/503] fixed formatting --- config/chips/C011xx.chip | 4 ++-- config/chips/C031xx.chip | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/config/chips/C011xx.chip b/config/chips/C011xx.chip index 9124c6a1e..b961a18f8 100644 --- a/config/chips/C011xx.chip +++ b/config/chips/C011xx.chip @@ -9,6 +9,6 @@ flash_pagesize 0x800 // 2 KB sram_size 0x1800 // 6 KB bootrom_base 0x1fff0000 bootrom_size 0x1800 // 6 KB -option_base 0x1fff7800 // STM32_C0_OPTION_BYTES_BASE -option_size 0x80 // 128 B +option_base 0x1fff7800 // STM32_C0_OPTION_BYTES_BASE +option_size 0x80 // 128 B flags none diff --git a/config/chips/C031xx.chip b/config/chips/C031xx.chip index 30017ae90..921c1f1fa 100644 --- a/config/chips/C031xx.chip +++ b/config/chips/C031xx.chip @@ -9,6 +9,6 @@ flash_pagesize 0x800 // 2 KB sram_size 0x3000 // 12 KB bootrom_base 0x1fff0000 bootrom_size 0x1800 // 6 KB -option_base 0x1fff7800 // STM32_C0_OPTION_BYTES_BASE -option_size 0x80 // 128 B +option_base 0x1fff7800 // STM32_C0_OPTION_BYTES_BASE +option_size 0x80 // 128 B flags none From 0d16dbac9a7cb89dddc92f1c5b1a1274362d6906 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Wed, 22 Nov 2023 01:13:44 +0100 Subject: [PATCH 485/503] CodeQL Workflow Maintenance - Removed incompatible workflow - Updated existing workflow --- .github/workflows/codeql-analysis.yml | 14 +-- .github/workflows/codeql-buildscript.sh | 6 -- .github/workflows/codeql.yml | 126 ------------------------ .github/workflows/fail_on_error.py | 34 ------- 4 files changed, 7 insertions(+), 173 deletions(-) delete mode 100644 .github/workflows/codeql-buildscript.sh delete mode 100644 .github/workflows/codeql.yml delete mode 100755 .github/workflows/fail_on_error.py diff --git a/.github/workflows/codeql-analysis.yml b/.github/workflows/codeql-analysis.yml index 55a21294f..94f256249 100644 --- a/.github/workflows/codeql-analysis.yml +++ b/.github/workflows/codeql-analysis.yml @@ -13,12 +13,12 @@ name: "CodeQL" on: push: - branches: [ testing, develop, master ] + branches: [testing, develop, master] pull_request: # The branches below must be a subset of the branches above - branches: [ testing, develop ] + branches: [testing, develop] schedule: - - cron: '00 20 * * 1' + - cron: "00 20 * * 1" jobs: analyze: @@ -28,7 +28,7 @@ jobs: strategy: fail-fast: false matrix: - language: [ 'cpp' ] + language: ["cpp"] # CodeQL supports [ 'cpp', 'csharp', 'go', 'java', 'javascript', 'python' ] # Learn more: # https://docs.github.com/en/free-pro-team@latest/github/finding-security-vulnerabilities-and-errors-in-your-code/configuring-code-scanning#changing-the-languages-that-are-analyzed @@ -41,7 +41,7 @@ jobs: # Initializes the CodeQL tools for scanning. - name: Initialize CodeQL - uses: github/codeql-action/init@v1 + uses: github/codeql-action/init@v2 with: languages: ${{ matrix.language }} # If you wish to specify custom queries, you can do so here or in a config file. @@ -52,7 +52,7 @@ jobs: # Autobuild attempts to build any compiled languages (C/C++, C#, or Java). # If this step fails, then you should remove it and run the build manually (see below) - name: Autobuild - uses: github/codeql-action/autobuild@v1 + uses: github/codeql-action/autobuild@v2 # ℹ️ Command-line programs to run using the OS shell. # 📚 https://git.io/JvXDl @@ -66,4 +66,4 @@ jobs: # make release - name: Perform CodeQL Analysis - uses: github/codeql-action/analyze@v1 + uses: github/codeql-action/analyze@v2 diff --git a/.github/workflows/codeql-buildscript.sh b/.github/workflows/codeql-buildscript.sh deleted file mode 100644 index d626d4283..000000000 --- a/.github/workflows/codeql-buildscript.sh +++ /dev/null @@ -1,6 +0,0 @@ -#!/usr/bin/env bash - -sudo apt-get -y update -sudo apt-get -y install libusb-1.0 libusb-1.0-0-dev libgtk-3-dev -make clean -make release -j$(nproc) diff --git a/.github/workflows/codeql.yml b/.github/workflows/codeql.yml deleted file mode 100644 index 816492278..000000000 --- a/.github/workflows/codeql.yml +++ /dev/null @@ -1,126 +0,0 @@ -# For most projects, this workflow file will not need changing; you simply need -# to commit it to your repository. -# -# You may wish to alter this file to override the set of languages analyzed, -# or to provide custom queries or build logic. -# -# ******** NOTE ******** -# We have attempted to detect the languages in your repository. Please check -# the `language` matrix defined below to confirm you have the correct set of -# supported CodeQL languages. -# -name: "CodeQL" - -on: - # push: - # branches: [ "main", "master" ] - schedule: - - cron: '0 0 * * *' - pull_request: - branches: '*' - -jobs: - analyze: - name: Analyze - # Runner size impacts CodeQL analysis time. To learn more, please see: - # - https://gh.io/recommended-hardware-resources-for-running-codeql - # - https://gh.io/supported-runners-and-hardware-resources - # - https://gh.io/using-larger-runners - # Consider using larger runners for possible analysis time improvements. - runs-on: ${{ (matrix.language == 'swift' && 'macos-latest') || 'ubuntu-20.04' }} - timeout-minutes: ${{ (matrix.language == 'swift' && 120) || 360 }} - permissions: - actions: read - contents: read - security-events: write - - strategy: - fail-fast: false - matrix: - language: [ 'cpp' ] - # CodeQL supports [ 'cpp', 'csharp', 'go', 'java', 'javascript', 'python', 'ruby', 'swift' ] - # Use only 'java' to analyze code written in Java, Kotlin or both - # Use only 'javascript' to analyze code written in JavaScript, TypeScript or both - # Learn more about CodeQL language support at https://aka.ms/codeql-docs/language-support - - steps: - - name: Checkout repository - uses: actions/checkout@v3 - with: - submodules: recursive - - # Initializes the CodeQL tools for scanning. - - name: Initialize CodeQL - uses: github/codeql-action/init@v2 - with: - languages: ${{ matrix.language }} - # If you wish to specify custom queries, you can do so here or in a config file. - # By default, queries listed here will override any specified in a config file. - # Prefix the list here with "+" to use these queries and those in the config file. - - # For more details on CodeQL's query packs, refer to: https://docs.github.com/en/code-security/code-scanning/automatically-scanning-your-code-for-vulnerabilities-and-errors/configuring-code-scanning#using-queries-in-ql-packs - # queries: security-extended,security-and-quality - queries: security-and-quality - - - # Autobuild attempts to build any compiled languages (C/C++, C#, Go, Java, or Swift). - # If this step fails, then you should remove it and run the build manually (see below) - #- name: Autobuild - # uses: github/codeql-action/autobuild@v2 - - # ℹ️ Command-line programs to run using the OS shell. - # 📚 See https://docs.github.com/en/actions/using-workflows/workflow-syntax-for-github-actions#jobsjob_idstepsrun - - # If the Autobuild fails above, remove it and uncomment the following three lines. - # modify them (or add more) to build your code if your project, please refer to the EXAMPLE below for guidance. - - - run: | - ./.github/workflows/codeql-buildscript.sh - - - name: Perform CodeQL Analysis - uses: github/codeql-action/analyze@v2 - with: - category: "/language:${{matrix.language}}" - upload: false - id: step1 - - # Filter out rules with low severity or high false positve rate - # Also filter out warnings in third-party code - - name: Filter out unwanted errors and warnings - uses: advanced-security/filter-sarif@v1 - with: - patterns: | - -**:cpp/path-injection - -**:cpp/world-writable-file-creation - -**:cpp/poorly-documented-function - -**:cpp/potentially-dangerous-function - -**:cpp/use-of-goto - -**:cpp/integer-multiplication-cast-to-long - -**:cpp/comparison-with-wider-type - -**:cpp/leap-year/* - -**:cpp/ambiguously-signed-bit-field - -**:cpp/suspicious-pointer-scaling - -**:cpp/suspicious-pointer-scaling-void - -**:cpp/unsigned-comparison-zero - -**/cmake*/Modules/** - input: ${{ steps.step1.outputs.sarif-output }}/cpp.sarif - output: ${{ steps.step1.outputs.sarif-output }}/cpp.sarif - - - name: Upload CodeQL results to code scanning - uses: github/codeql-action/upload-sarif@v2 - with: - sarif_file: ${{ steps.step1.outputs.sarif-output }} - category: "/language:${{matrix.language}}" - - - name: Upload CodeQL results as an artifact - if: success() || failure() - uses: actions/upload-artifact@v3 - with: - name: codeql-results - path: ${{ steps.step1.outputs.sarif-output }} - retention-days: 5 - - - name: Fail if an error is found - run: | - ./.github/workflows/fail_on_error.py \ - ${{ steps.step1.outputs.sarif-output }}/cpp.sarif diff --git a/.github/workflows/fail_on_error.py b/.github/workflows/fail_on_error.py deleted file mode 100755 index 29791742b..000000000 --- a/.github/workflows/fail_on_error.py +++ /dev/null @@ -1,34 +0,0 @@ -#!/usr/bin/env python3 - -import json -import sys - -# Return whether SARIF file contains error-level results -def codeql_sarif_contain_error(filename): - with open(filename, 'r') as f: - s = json.load(f) - - for run in s.get('runs', []): - rules_metadata = run['tool']['driver']['rules'] - if not rules_metadata: - rules_metadata = run['tool']['extensions'][0]['rules'] - - for res in run.get('results', []): - if 'ruleIndex' in res: - rule_index = res['ruleIndex'] - elif 'rule' in res and 'index' in res['rule']: - rule_index = res['rule']['index'] - else: - continue - try: - rule_level = rules_metadata[rule_index]['defaultConfiguration']['level'] - except IndexError as e: - print(e, rule_index, len(rules_metadata)) - else: - if rule_level == 'error': - return True - return False - -if __name__ == "__main__": - if codeql_sarif_contain_error(sys.argv[1]): - sys.exit(1) From 033007fd2713aba630d28c706499959dc8792277 Mon Sep 17 00:00:00 2001 From: Mirko Matonti Date: Thu, 23 Nov 2023 17:46:09 +0000 Subject: [PATCH 486/503] pr adjustment --- src/stlink-lib/common_flash.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/stlink-lib/common_flash.c b/src/stlink-lib/common_flash.c index 5005a632f..7172352ee 100644 --- a/src/stlink-lib/common_flash.c +++ b/src/stlink-lib/common_flash.c @@ -1312,7 +1312,7 @@ int32_t stlink_fwrite_flash(stlink_t *sl, const char *path, stm32_addr_t addr) { */ /* In case the address is within the OTP area we use a different flash method */ - if(addr >= sl->otp_base && addr <= sl->otp_base + sl->otp_size) { + if(addr >= sl->otp_base && addr < sl->otp_base + sl->otp_size) { err = stlink_write_otp(sl, addr, mf.base, (num_empty == mf.len) ? (uint32_t)mf.len : (uint32_t)mf.len - num_empty); } else { @@ -1404,7 +1404,7 @@ int32_t stlink_check_address_range_validity_otp(stlink_t *sl, stm32_addr_t addr, ELOG("Invalid address, it should be within 0x%08x - 0x%08x\n", sl->otp_base, logvar); return (-1); } - if ((addr + size) > (sl->otp_base + sl->otp_size)) { + if ((addr + size) >= (sl->otp_base + sl->otp_size)) { logvar = sl->otp_base + sl->otp_size - addr; ELOG("The size exceeds the size of the OTP Area (0x%08x bytes available)\n", logvar); return (-1); @@ -1431,7 +1431,7 @@ int32_t stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint3 int32_t ret; flash_loader_t fl; ILOG("Attempting to write %d (%#x) bytes to stm32 address: %u (%#x)\n", len, len, addr, addr); - + // check addr range is inside the flash stlink_calculate_pagesize(sl, addr); From 7dcb1302d8b91b2217c4ce50cb255aa8e78ab001 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Fri, 24 Nov 2023 18:21:31 +0100 Subject: [PATCH 487/503] Fixes for STM32H7 & STM32G0B1 devices - Fixed flash lock for STM32H7 dual bank devices - Fixed flash erase issue on STM32G0B1 (Closes #1321) --- src/stlink-lib/calculate.c | 2 +- src/stlink-lib/common_flash.c | 28 ++++++++++++---------------- 2 files changed, 13 insertions(+), 17 deletions(-) diff --git a/src/stlink-lib/calculate.c b/src/stlink-lib/calculate.c index a7344e0b0..1230875fd 100644 --- a/src/stlink-lib/calculate.c +++ b/src/stlink-lib/calculate.c @@ -66,7 +66,7 @@ uint32_t calculate_L4_page(stlink_t *sl, uint32_t flashaddr) { if (sl->chip_id == STM32_CHIPID_L4 || sl->chip_id == STM32_CHIPID_L496x_L4A6x || sl->chip_id == STM32_CHIPID_L4Rx) { - // this chip use dual banked flash + // these chips use dual bank flash if (flashopt & (uint32_t)(1lu << FLASH_L4_OPTR_DUALBANK)) { uint32_t banksize = sl->flash_size / 2; diff --git a/src/stlink-lib/common_flash.c b/src/stlink-lib/common_flash.c index 6f2a47f43..ef6b8370c 100644 --- a/src/stlink-lib/common_flash.c +++ b/src/stlink-lib/common_flash.c @@ -101,6 +101,11 @@ void lock_flash(stlink_t *sl) { cr_lock_shift = FLASH_Gx_CR_LOCK; } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { cr_reg = FLASH_H7_CR1; + if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { + cr2_reg = FLASH_H7_CR2; + } + cr_lock_shift = FLASH_H7_CR_LOCK; + cr_mask = ~(1u << FLASH_H7_CR_SER); } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { cr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF; cr_lock_shift = FLASH_L0_PELOCK; @@ -113,11 +118,6 @@ void lock_flash(stlink_t *sl) { } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { cr_reg = FLASH_WB_CR; cr_lock_shift = FLASH_WB_CR_LOCK; - if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { - cr2_reg = FLASH_H7_CR2; - } - cr_lock_shift = FLASH_H7_CR_LOCK; - cr_mask = ~(1u << FLASH_H7_CR_SER); } else { ELOG("unsupported flash method, abort\n"); return; @@ -1014,11 +1014,7 @@ int32_t stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { unlock_flash_if(sl); // select the page to erase - if ((sl->chip_id == STM32_CHIPID_L4) || - (sl->chip_id == STM32_CHIPID_L43x_L44x) || - (sl->chip_id == STM32_CHIPID_L45x_L46x) || - (sl->chip_id == STM32_CHIPID_L496x_L4A6x) || - (sl->chip_id == STM32_CHIPID_L4Rx)) { + if (sl->flash_type == STM32_FLASH_TYPE_L4) { // calculate the actual bank+page from the address uint32_t page = calculate_L4_page(sl, flashaddr); @@ -1121,16 +1117,16 @@ int32_t stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { if (sl->flash_type == STM32_FLASH_TYPE_G0) { uint32_t flash_page = ((flashaddr - STM32_FLASH_BASE) / sl->flash_pgsz); stlink_read_debug32(sl, FLASH_Gx_CR, &val); - // sec 3.7.5 - PNB[5:0] is offset by 3. PER is 0x2. - val &= ~(0x3F << 3); - val |= ((flash_page & 0x3F) << 3) | (1 << FLASH_CR_PER); + // sec 3.7.5 - PNB[9:0] is offset by 3. PER is 0x2. + val &= ~(0x3FF << 3); + val |= ((flash_page & 0x3FF) << 3) | (1 << FLASH_CR_PER); stlink_write_debug32(sl, FLASH_Gx_CR, val); } else if (sl->flash_type == STM32_FLASH_TYPE_G4) { uint32_t flash_page = ((flashaddr - STM32_FLASH_BASE) / sl->flash_pgsz); stlink_read_debug32(sl, FLASH_Gx_CR, &val); - // sec 3.7.5 - PNB[6:0] is offset by 3. PER is 0x2. - val &= ~(0x7F << 3); - val |= ((flash_page & 0x7F) << 3) | (1 << FLASH_CR_PER); + // sec 3.7.5 - PNB[9:0] is offset by 3. PER is 0x2. + val &= ~(0x7FF << 3); + val |= ((flash_page & 0x7FF) << 3) | (1 << FLASH_CR_PER); stlink_write_debug32(sl, FLASH_Gx_CR, val); // STM32L5x2xx has two banks with 2k pages or single with 4k pages // STM32H5xx, STM32U535, STM32U545, STM32U575 or STM32U585 have 2 banks with 8k pages From 3efa7932fb7f062f31693c6a2a00941ecf64431b Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Fri, 24 Nov 2023 20:22:50 +0100 Subject: [PATCH 488/503] Fixed memory allocation for stlink-gui (Closes #1356) --- src/stlink-gui/gui.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/stlink-gui/gui.c b/src/stlink-gui/gui.c index e3eec34b8..51ee293e8 100644 --- a/src/stlink-gui/gui.c +++ b/src/stlink-gui/gui.c @@ -313,7 +313,7 @@ static gpointer stlink_gui_populate_filemem_view(gpointer data) { goto out_input; } - gui->file_mem.size = (gsize) file_info; + gui->file_mem.size = file_size; gui->file_mem.memory = g_malloc(gui->file_mem.size); for (off = 0; off < (gint)gui->file_mem.size; off += MEM_READ_SIZE) { From ba335a47ab3ad820461ac0175dc0d540090c978c Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Mon, 27 Nov 2023 22:00:27 +0100 Subject: [PATCH 489/503] STM32F76xxx: Added flashing in dual bank mode (Closes #1174) --- inc/stlink.h | 28 ++++++----- inc/stm32flash.h | 59 +++++++++++----------- src/stlink-lib/calculate.c | 8 ++- src/stlink-lib/common.c | 94 ++++++++++++++++++++++++++++++++++- src/stlink-lib/common_flash.c | 4 +- src/stlink-lib/flash_loader.c | 4 +- 6 files changed, 145 insertions(+), 52 deletions(-) diff --git a/inc/stlink.h b/inc/stlink.h index 557a9eeaa..920822a85 100644 --- a/inc/stlink.h +++ b/inc/stlink.h @@ -199,23 +199,23 @@ struct _stlink { // transport layer verboseness: 0 for no debug info, 10 for lots int32_t verbose; int32_t opt; - uint32_t core_id; // set by stlink_core_id(), result from STLINK_DEBUGREADCOREID - uint32_t chip_id; // set by stlink_load_device_params(), used to identify flash and sram - enum target_state core_stat; // set by stlink_status() + uint32_t core_id; // set by stlink_core_id(), result from STLINK_DEBUGREADCOREID + uint32_t chip_id; // set by stlink_load_device_params(), used to identify flash and sram + enum target_state core_stat; // set by stlink_status() char serial[STLINK_SERIAL_BUFFER_SIZE]; - int32_t freq; // set by stlink_open_usb(), values: STLINK_SWDCLK_xxx_DIVISOR + int32_t freq; // set by stlink_open_usb(), values: STLINK_SWDCLK_xxx_DIVISOR enum stm32_flash_type flash_type; // stlink_chipid_params.flash_type, set by stlink_load_device_params(), values: STM32_FLASH_TYPE_xx - stm32_addr_t flash_base; // STM32_FLASH_BASE, set by stlink_load_device_params() - uint32_t flash_size; // calculated by stlink_load_device_params() - uint32_t flash_pgsz; // stlink_chipid_params.flash_pagesize, set by stlink_load_device_params() + stm32_addr_t flash_base; // STM32_FLASH_BASE, set by stlink_load_device_params() + uint32_t flash_size; // calculated by stlink_load_device_params() + uint32_t flash_pgsz; // stlink_chipid_params.flash_pagesize, set by stlink_load_device_params() /* sram settings */ - stm32_addr_t sram_base; // STM32_SRAM_BASE, set by stlink_load_device_params() - uint32_t sram_size; // stlink_chipid_params.sram_size, set by stlink_load_device_params() + stm32_addr_t sram_base; // STM32_SRAM_BASE, set by stlink_load_device_params() + uint32_t sram_size; // stlink_chipid_params.sram_size, set by stlink_load_device_params() /* option settings */ stm32_addr_t option_base; @@ -224,14 +224,16 @@ struct _stlink { // bootloader // sys_base and sys_size are not used by the tools, but are only there to download the bootloader code // (see tests/sg.c) - stm32_addr_t sys_base; // stlink_chipid_params.bootrom_base, set by stlink_load_device_params() - uint32_t sys_size; // stlink_chipid_params.bootrom_size, set by stlink_load_device_params() + stm32_addr_t sys_base; // stlink_chipid_params.bootrom_base, set by stlink_load_device_params() + uint32_t sys_size; // stlink_chipid_params.bootrom_size, set by stlink_load_device_params() struct stlink_version_ version; - uint32_t chip_flags; // stlink_chipid_params.flags, set by stlink_load_device_params(), values: CHIP_F_xxx + uint32_t chip_flags; // stlink_chipid_params.flags, set by stlink_load_device_params(), values: CHIP_F_xxx - uint32_t max_trace_freq; // set by stlink_open_usb() + uint32_t max_trace_freq; // set by stlink_open_usb() + + bool dual_bank; // set for F7xxx devices by reading optcr uint32_t otp_base; uint32_t otp_size; diff --git a/inc/stm32flash.h b/inc/stm32flash.h index b5e47e0d3..4fed8b597 100644 --- a/inc/stm32flash.h +++ b/inc/stm32flash.h @@ -142,6 +142,7 @@ #define FLASH_F7_OPTCR_START 1 #define FLASH_F7_OPTCR1_BOOT_ADD0 0 #define FLASH_F7_OPTCR1_BOOT_ADD1 16 +#define FLASH_F7_OPTCR_DBANK (29) /* FLASH_OPTCR Dual Bank Mode */ // F7 Flash control register #define FLASH_F7_CR_STRT 16 @@ -152,12 +153,12 @@ // F7 Flash status register #define FLASH_F7_SR_BSY 16 -#define FLASH_F7_SR_ERS_ERR 7 /* Erase Sequence Error */ -#define FLASH_F7_SR_PGP_ERR 6 /* Programming parallelism error */ -#define FLASH_F7_SR_PGA_ERR 5 /* Programming alignment error */ -#define FLASH_F7_SR_WRP_ERR 4 /* Write protection error */ -#define FLASH_F7_SR_OP_ERR 1 /* Operation error */ -#define FLASH_F7_SR_EOP 0 /* End of operation */ +#define FLASH_F7_SR_ERS_ERR 7 /* Erase Sequence Error */ +#define FLASH_F7_SR_PGP_ERR 6 /* Programming parallelism error */ +#define FLASH_F7_SR_PGA_ERR 5 /* Programming alignment error */ +#define FLASH_F7_SR_WRP_ERR 4 /* Write protection error */ +#define FLASH_F7_SR_OP_ERR 1 /* Operation error */ +#define FLASH_F7_SR_EOP 0 /* End of operation */ #define FLASH_F7_SR_ERROR_MASK \ ((1 << FLASH_F7_SR_ERS_ERR) | (1 << FLASH_F7_SR_PGP_ERR) | \ (1 << FLASH_F7_SR_PGA_ERR) | (1 << FLASH_F7_SR_WRP_ERR) | \ @@ -196,8 +197,8 @@ #define FLASH_Gx_SR_PROGERR (3) #define FLASH_Gx_SR_WRPERR (4) #define FLASH_Gx_SR_PGAERR (5) -#define FLASH_Gx_SR_BSY (16) /* FLASH_SR Busy */ -#define FLASH_Gx_SR_EOP (0) /* FLASH_EOP End of Operation */ +#define FLASH_Gx_SR_BSY (16) /* FLASH_SR Busy */ +#define FLASH_Gx_SR_EOP (0) /* FLASH_EOP End of Operation */ // == STM32G0 == (RM0444 Table 1, sec. 3.7) // Mostly the same as G4 chips, but the notation @@ -272,8 +273,8 @@ #define FLASH_H7_SR_WRPERR 17 #define FLASH_H7_SR_PGSERR 18 #define FLASH_H7_SR_STRBERR 19 -#define FLASH_H7_SR_ERROR_MASK \ - ((1 << FLASH_H7_SR_PGSERR) | (1 << FLASH_H7_SR_STRBERR) | \ +#define FLASH_H7_SR_ERROR_MASK \ + ((1 << FLASH_H7_SR_PGSERR) | (1 << FLASH_H7_SR_STRBERR) | \ (1 << FLASH_H7_SR_WRPERR)) // == STM32L0/L1/L4/L5 == @@ -332,27 +333,27 @@ #define FLASH_L4_OPTR (FLASH_REGS_ADDR + 0x20) // L4 Flash status register -#define FLASH_L4_SR_ERROR_MASK 0x3f8 /* SR [9:3] */ +#define FLASH_L4_SR_ERROR_MASK 0x3f8 // SR [9:3] #define FLASH_L4_SR_PROGERR 3 #define FLASH_L4_SR_WRPERR 4 #define FLASH_L4_SR_PGAERR 5 #define FLASH_L4_SR_BSY 16 // L4 Flash control register -#define FLASH_L4_CR_LOCK 31 /* Lock control register */ -#define FLASH_L4_CR_OPTLOCK 30 /* Lock option bytes */ -#define FLASH_L4_CR_PG 0 /* Program */ -#define FLASH_L4_CR_PER 1 /* Page erase */ -#define FLASH_L4_CR_MER1 2 /* Bank 1 erase */ -#define FLASH_L4_CR_MER2 15 /* Bank 2 erase */ -#define FLASH_L4_CR_STRT 16 /* Start command */ -#define FLASH_L4_CR_OPTSTRT 17 /* Start writing option bytes */ -#define FLASH_L4_CR_BKER 11 /* Bank select for page erase */ -#define FLASH_L4_CR_PNB 3 /* Page number (8 bits) */ -#define FLASH_L4_CR_OBL_LAUNCH 27 /* Option bytes reload */ +#define FLASH_L4_CR_LOCK 31 /* Lock control register */ +#define FLASH_L4_CR_OPTLOCK 30 /* Lock option bytes */ +#define FLASH_L4_CR_PG 0 /* Program */ +#define FLASH_L4_CR_PER 1 /* Page erase */ +#define FLASH_L4_CR_MER1 2 /* Bank 1 erase */ +#define FLASH_L4_CR_MER2 15 /* Bank 2 erase */ +#define FLASH_L4_CR_STRT 16 /* Start command */ +#define FLASH_L4_CR_OPTSTRT 17 /* Start writing option bytes */ +#define FLASH_L4_CR_BKER 11 /* Bank select for page erase */ +#define FLASH_L4_CR_PNB 3 /* Page number (8 bits) */ +#define FLASH_L4_CR_OBL_LAUNCH 27 /* Option bytes reload */ // Bits requesting flash operations (useful when we want to clear them) -#define FLASH_L4_CR_OPBITS \ - (uint32_t)((1lu << FLASH_L4_CR_PG) | (1lu << FLASH_L4_CR_PER) | \ +#define FLASH_L4_CR_OPBITS \ + (uint32_t)((1lu << FLASH_L4_CR_PG) | (1lu << FLASH_L4_CR_PER) | \ (1lu << FLASH_L4_CR_MER1) | (1lu << FLASH_L4_CR_MER1)) // Page is fully specified by BKER and PNB #define FLASH_L4_CR_PAGEMASK (uint32_t)(0x1fflu << FLASH_L4_CR_PNB) @@ -428,10 +429,10 @@ #define FLASH_WB_CR_LOCK (31) /* Lock */ // WB Flash status register -#define FLASH_WB_SR_ERROR_MASK (0x3f8) /* SR [9:3] */ -#define FLASH_WB_SR_PROGERR (3) /* Programming alignment error */ -#define FLASH_WB_SR_WRPERR (4) /* Write protection error */ -#define FLASH_WB_SR_PGAERR (5) /* Programming error */ -#define FLASH_WB_SR_BSY (16) /* Busy */ +#define FLASH_WB_SR_ERROR_MASK (0x3f8) // SR [9:3] +#define FLASH_WB_SR_PROGERR (3) /* Programming alignment error */ +#define FLASH_WB_SR_WRPERR (4) /* Write protection error */ +#define FLASH_WB_SR_PGAERR (5) /* Programming error */ +#define FLASH_WB_SR_BSY (16) /* Busy */ #endif // STM32FLASH_H diff --git a/src/stlink-lib/calculate.c b/src/stlink-lib/calculate.c index 1230875fd..a8a66a844 100644 --- a/src/stlink-lib/calculate.c +++ b/src/stlink-lib/calculate.c @@ -36,7 +36,7 @@ uint32_t calculate_F4_sectornum(uint32_t flashaddr) { } } -uint32_t calculate_F7_sectornum(uint32_t flashaddr) { +uint32_t calculate_F7_sectornum_old(uint32_t flashaddr) { flashaddr &= ~STM32_FLASH_BASE; // Page now holding the actual flash address if (flashaddr < 0x20000) { @@ -49,10 +49,8 @@ uint32_t calculate_F7_sectornum(uint32_t flashaddr) { } uint32_t calculate_H7_sectornum(stlink_t *sl, uint32_t flashaddr, uint32_t bank) { - flashaddr &= - ~((bank == BANK_1) - ? STM32_FLASH_BASE - : STM32_H7_FLASH_BANK2_BASE); // sector holding the flash address + // sector holding the flash address + flashaddr &= ~((bank == BANK_1) ? STM32_FLASH_BASE : STM32_H7_FLASH_BANK2_BASE); return (flashaddr / sl->flash_pgsz); } diff --git a/src/stlink-lib/common.c b/src/stlink-lib/common.c index 337fe6efa..4ff90ef3d 100644 --- a/src/stlink-lib/common.c +++ b/src/stlink-lib/common.c @@ -318,6 +318,19 @@ int32_t stlink_load_device_params(stlink_t *sl) { } } + // F76xxx device with dual bank + if (sl->chip_id == STM32_CHIPID_F76xxx) { + // Check the nDBANK bit in OPTCR + uint32_t optcr; + stlink_read_option_control_register32(sl, & optcr); + + if (!(optcr & (1 << STM32F7_FLASH_OPTCR_DBANK))) + { + sl->dual_bank = true; + } + DLOG("*** stm32f76xx dual-bank %d ***\n", sl->dual_bank); + } + // H7 devices with small flash has one bank if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK && sl->flash_type == STM32_FLASH_TYPE_H7) { @@ -830,8 +843,87 @@ int32_t write_buffer_to_sram(stlink_t *sl, flash_loader_t *fl, const uint8_t *bu return (ret); } +/* STM32F7 Series Flash memory dual bank mode + * See application note AN4826 pp.18 + */ + +struct sectors_f7 { + int sector; + uint32_t base; + uint32_t size; +}; + +static const struct sectors_f7 f7_single[] = { + { 0, 0x08000000, 0x8000 }, + { 1, 0x08008000, 0x8000 }, + { 2, 0x08010000, 0x8000 }, + { 3, 0x08018000, 0x8000 }, + { 4, 0x08020000, 0x20000 }, + { 5, 0x08040000, 0x40000 }, + { 6, 0x08080000, 0x40000 }, + { 7, 0x080C0000, 0x40000 }, + { 0, 0, 0 }, +}; + +static const struct sectors_f7 f7_dual[] = { + { 0, 0x08000000, 0x4000 }, + { 1, 0x08004000, 0x4000 }, + { 2, 0x08008000, 0x4000 }, + { 3, 0x0800C000, 0x4000 }, + { 4, 0x08010000, 0x10000 }, + { 5, 0x08020000, 0x20000 }, + { 6, 0x08040000, 0x20000 }, + { 7, 0x08060000, 0x20000 }, + { 8, 0x08080000, 0x20000 }, + { 9, 0x080A0000, 0x20000 }, + { 10, 0x080C0000, 0x20000 }, + { 11, 0x080E0000, 0x20000 }, + { 12, 0x08100000, 0x4000 }, + { 13, 0x08104000, 0x4000 }, + { 14, 0x08108000, 0x4000 }, + { 15, 0x0810C000, 0x4000 }, + { 16, 0x08110000, 0x10000 }, + { 17, 0x08120000, 0x20000 }, + { 18, 0x08140000, 0x20000 }, + { 19, 0x08160000, 0x20000 }, + { 20, 0x08180000, 0x20000 }, + { 21, 0x081A0000, 0x20000 }, + { 22, 0x081C0000, 0x20000 }, + { 23, 0x081E0000, 0x20000 }, + { 0, 0, 0 }, +}; + +static const struct sectors_f7 *get_f7_info(stlink_t *sl) { + return sl->dual_bank ? f7_dual : f7_single; +} + +static const struct sectors_f7 *find_sector(stlink_t *sl, uint32_t flashaddr) { + for (const struct sectors_f7 *s = get_f7_info(sl); s->base; s++) { + const uint32_t end = s->base + s->size; + if ((s->base <= flashaddr) && (flashaddr < end)) { + return s; + } + } + fprintf(stderr, "Bad address %#x\n", flashaddr); + exit(0); +} + +uint32_t calculate_F7_sectornum(stlink_t *sl, uint32_t flashaddr) { + if (sl->chip_id == STM32_CHIPID_F76xxx) { + const struct sectors_f7 *s = find_sector(sl, flashaddr); + return s->sector; + } + return calculate_F7_sectornum_old(flashaddr); +} + // 291 uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr) { + + if (sl->chip_id == STM32_CHIPID_F76xxx) { + const struct sectors_f7 *s = find_sector(sl, flashaddr); + return s->size; + } + if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || @@ -857,7 +949,7 @@ uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr) { } } else if (sl->chip_id == STM32_CHIPID_F7 || sl->chip_id == STM32_CHIPID_F76xxx) { - uint32_t sector = calculate_F7_sectornum(flashaddr); + uint32_t sector = calculate_F7_sectornum(sl, flashaddr); if (sector < 4) { sl->flash_pgsz = 0x8000; diff --git a/src/stlink-lib/common_flash.c b/src/stlink-lib/common_flash.c index ef6b8370c..fc377a471 100644 --- a/src/stlink-lib/common_flash.c +++ b/src/stlink-lib/common_flash.c @@ -145,7 +145,7 @@ static inline int32_t write_flash_sr(stlink_t *sl, uint32_t bank, uint32_t val) } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { sr_reg = FLASH_F4_SR; } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { - sr_reg = FLASH_F7_SR; + sr_reg = (bank == BANK_1) ? FLASH_F7_SR1 : FLASH_F7_SR2; } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || sl->flash_type == STM32_FLASH_TYPE_G4) { sr_reg = FLASH_Gx_SR; @@ -1025,7 +1025,7 @@ int32_t stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { } else if (sl->chip_id == STM32_CHIPID_F7 || sl->chip_id == STM32_CHIPID_F76xxx) { // calculate the actual page from the address - uint32_t sector = calculate_F7_sectornum(flashaddr); + uint32_t sector = calculate_F7_sectornum(sl, flashaddr); fprintf(stderr, "EraseFlash - Sector:0x%x Size:0x%x ", sector, stlink_calculate_pagesize(sl, flashaddr)); diff --git a/src/stlink-lib/flash_loader.c b/src/stlink-lib/flash_loader.c index 0d01dfd61..9511c9282 100644 --- a/src/stlink-lib/flash_loader.c +++ b/src/stlink-lib/flash_loader.c @@ -363,7 +363,7 @@ int32_t stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t t /* Run loader */ stlink_run(sl, RUN_FLASH_LOADER); -/* +/* * This piece of code used to try to spin for .1 second by waiting doing 10000 rounds of 10 µs. * But because this usually runs on Unix-like OSes, the 10 µs get rounded up to the "tick" * (actually almost two ticks) of the system. 1 ms. Thus, the ten thousand attempts, when @@ -393,7 +393,7 @@ int32_t stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t t // check written byte count stlink_read_reg(sl, 2, &rr); - /* + /* * The chunk size for loading is not rounded. The flash loader * subtracts the size of the written block (1-8 bytes) from * the remaining size each time. A negative value may mean that From 8f2b289f20372583ae5f2889069e56df3c71477c Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Mon, 27 Nov 2023 23:41:27 +0100 Subject: [PATCH 490/503] Info on HW breakpoints for external bus - [doc] Updated tutorial.md (Closes #1219) - Moved memory maps into separate file. --- doc/tutorial.md | 32 +++--- src/st-util/gdb-server.c | 214 +------------------------------------- src/st-util/memory-map.h | 217 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 238 insertions(+), 225 deletions(-) create mode 100644 src/st-util/memory-map.h diff --git a/doc/tutorial.md b/doc/tutorial.md index 53ecabe7d..736c4283b 100644 --- a/doc/tutorial.md +++ b/doc/tutorial.md @@ -2,18 +2,18 @@ ## Available tools and options -| Option | Tool | Description | Available
since | -| --------------------- | ---------------------------------- | --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | -------------------- | -| --flash=n[k, M] | st-flash | One can specify `--flash=128k` for example, to override the default value of 64k for the STM32F103C8T6
to assume 128k of flash being present. This option accepts decimal (128k), octal 0200k, or hex 0x80k values.
Leaving the multiplier out is equally valid, e.g.: `--flash=0x20000`. The size may be followed by an optional
"k" or "M" to multiply the given value by 1k (1024) or 1M (1024 x 1024) respectively.
One can read arbitary addresses of memory out to a binary file with: `st-flash read out.bin 0x8000000 4096`.
In this example `4096 bytes` are read and subsequently written to `out.bin`.
Binary files (here: `in.bin`) are written into flash memory with: `st-flash write in.bin 0x8000000` | v1.4.0 | -| --format | st-flash | Specify file image format to read or write. Valid formats are `binary` and `ihex`. | v1.3.0 | -| --freq=n[k, M] | st-info
st-flash
st-util | The frequency of the SWD/JTAG interface can be specified, to override the default 1800 kHz configuration.
This option solely accepts decimal values with the unit `Hz` being left out. Valid frequencies are:
`5k, 15k, 25k, 50k, 100k, 125k, 240k, 480k, 950k, 1200k (1.2M), 1800k (1.8M), 4000k (4M)`. | v1.6.1 | -| --opt | st-flash | Optimisation can be enabled in order to skip flashing empty (0x00 or 0xff) bytes at the end of binary file.
This may cause some garbage data left after a flash operation. This option was enabled by default in earlier releases. | v1.6.1 | -| --reset | st-flash | Trigger a reset after flashing. The default uses the hardware reset through `NRST` pin.
A software reset (via `AIRCR`; since v1.5.1) is used, if the hardware reset failed (`NRST` pin not connected). | v1.0.0 | -| --connect-under-reset | st-info
st-flash
st-util | Connect under reset. Option makes it possible to connect to the device before code execution. This is useful
when the target contains code that lets the device go to sleep, disables debug pins or other special code. | v1.6.1 | -| --hot-plug | st-info
st-flash
st-util | Connect to the target without reset. | v1.6.2 | -| --probe | st-info | Display hardware information about the connected programmer and target MCU. | v1.2.0 | -| --version | st-info
st-flash
st-util | Print version information. | v1.3.0 | -| --help | st-flash
st-util | Print list of available commands. | | +| Option | Tool | Description | Available
since | +| --------------------- | ---------------------------------- | ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ | -------------------- | +| --flash=n[k, M] | st-flash | One can specify `--flash=128k` for example, to override the default value of 64k for the STM32F103C8T6 to assume 128k of flash being present. This option accepts decimal (128k), octal 0200k, or hex 0x80k values.
Leaving the multiplier out is equally valid, e.g.: `--flash=0x20000`. The size may be followed by an optional "k" or "M" to multiply the given value by 1k (1024) or 1M (1024 x 1024) respectively.
One can read arbitary addresses of memory out to a binary file with: `st-flash read out.bin 0x8000000 4096`. In this example `4096 bytes` are read and subsequently written to `out.bin`.
Binary files (here: `in.bin`) are written into flash memory with: `st-flash write in.bin 0x8000000` | v1.4.0 | +| --format | st-flash | Specify file image format to read or write.
Valid formats are `binary` and `ihex`. | v1.3.0 | +| --freq=n[k, M] | st-info
st-flash
st-util | The frequency of the SWD/JTAG interface can be specified, to override the default 1800 kHz configuration.
This option solely accepts decimal values with the unit `Hz` being left out. Valid frequencies are:
`5k, 15k, 25k, 50k, 100k, 125k, 240k, 480k, 950k, 1200k (1.2M), 1800k (1.8M), 4000k (4M)`. | v1.6.1 | +| --opt | st-flash | Optimisation can be enabled in order to skip flashing empty (0x00 or 0xff) bytes at the end of binary file.
This may cause some garbage data left after a flash operation. This option was enabled by default in earlier releases. | v1.6.1 | +| --reset | st-flash | Trigger a reset after flashing. The default uses the hardware reset through `NRST` pin.
A software reset (via `AIRCR`; since v1.5.1) is used, if the hardware reset failed (`NRST` pin not connected). | v1.0.0 | +| --connect-under-reset | st-info
st-flash
st-util | Connect under reset. Option makes it possible to connect to the device before code execution. This is useful when the target contains code that lets the device go to sleep, disables debug pins or other special code. | v1.6.1 | +| --hot-plug | st-info
st-flash
st-util | Connect to the target without reset. | v1.6.2 | +| --probe | st-info | Display hardware information about the connected programmer and target MCU. | v1.2.0 | +| --version | st-info
st-flash
st-util | Print version information. | v1.3.0 | +| --help | st-flash
st-util | Print list of available commands. | | ### Reading & Writing Option Bytes @@ -156,6 +156,14 @@ Here flashing of the device is now possible with and without the `--reset` optio The debug command `(gdb) monitor jtag_reset` sends a _hard reset_ signal via the `NRST` pin to reset the device and allows for flashing it (again). +### e) Note on setting hardware breakpoints for external bus (Example: STM32H735-DK) + +GDB is setting breakpoints based on the XML memory map designation of `rom` or `ram`, which is hardcoded in st-util for a given processor. +However the external bus can be *RAM* or *ROM* depending on design. + +The STM32H735-DK has external FLASH at address 0x90000000. As a result, because the entire external memory range is `ram` as it could be either, +software breakpoints (Z0) get sent when a breakpoint is created and they never get tripped as the memory area is read only. + --- ( Content below is currently unrevised and may be outdated as of Mar 2021. ) diff --git a/src/st-util/gdb-server.c b/src/st-util/gdb-server.c index 71f24fb60..28e06231a 100644 --- a/src/st-util/gdb-server.c +++ b/src/st-util/gdb-server.c @@ -29,6 +29,7 @@ #include #include "gdb-server.h" #include "gdb-remote.h" +#include "memory-map.h" #include "semihosting.h" #include @@ -344,219 +345,6 @@ static const char* const target_description = " " ""; -static const char* const memory_map_template_F4 = - "" - "" - "" - " " // code = sram, bootrom or flash; flash is bigger - " " // ccm ram - " " // sram - " " // Sectors 0..3 - " 0x4000" // 16kB - " " - " " // Sector 4 - " 0x10000" // 64kB - " " - " " // Sectors 5..11 - " 0x20000" // 128kB - " " - " " // peripheral regs - " " // AHB3 Peripherals - " " // cortex regs - " " // bootrom - " " // option byte area - ""; - -static const char* const memory_map_template_F4_HD = - "" - "" - "" - " " // code = sram, bootrom or flash; flash is bigger - " " // ccm ram - " " // sram - " " // fmc bank 1 (nor/psram/sram) - " " // fmc bank 2 & 3 (nand flash) - " " // fmc bank 4 (pc card) - " " // fmc sdram bank 1 & 2 - " " // Sectors 0..3 - " 0x4000" // 16kB - " " - " " // Sector 4 - " 0x10000" // 64kB - " " - " " // Sectors 5..11 - " 0x20000" // 128kB - " " - " " // peripheral regs - " " // cortex regs - " " // bootrom - " " // option byte area - ""; - -static const char* const memory_map_template_F2 = - "" - "" - "" - " " // code = sram, bootrom or flash; flash is bigger - " " // sram - " " // Sectors 0..3 - " 0x4000" // 16kB - " " - " " // Sector 4 - " 0x10000" // 64kB - " " - " " // Sectors 5.. - " 0x20000" // 128kB - " " - " " // peripheral regs - " " // cortex regs - " " // bootrom - " " // option byte area - ""; - -static const char* const memory_map_template_L4 = - "" - "" - "" - " " // code = sram, bootrom or flash; flash is bigger - " " // SRAM2 (32kB) - " " // SRAM1 (96kB) - " " - " 0x800" - " " - " " // peripheral regs - " " // AHB3 Peripherals - " " // cortex regs - " " // bootrom - " " // option byte area - " " // option byte area - ""; - -static const char* const memory_map_template_L496 = - "" - "" - "" - " " // code = sram, bootrom or flash; flash is bigger - " " // SRAM2 (64kB) - " " // SRAM1 + aliased SRAM2 (256 + 64 = 320kB) - " " - " 0x800" - " " - " " // peripheral regs - " " // AHB3 Peripherals - " " // cortex regs - " " // bootrom - " " // option byte area - " " // option byte area - ""; - -static const char* const memory_map_template = - "" - "" - "" - " " // code = sram, bootrom or flash; flash is bigger - " " // sram 8kB - " " - " 0x%x" - " " - " " // peripheral regs - " " // cortex regs - " " // bootrom - " " // option byte area - ""; - -static const char* const memory_map_template_F7 = - "" - "" - "" - " " // ITCM ram 16kB - " " // ITCM flash - " " // sram - " " // Sectors 0..3 - " 0x8000" // 32kB - " " - " " // Sector 4 - " 0x20000" // 128kB - " " - " " // Sectors 5..7 - " 0x40000" // 128kB - " " - " " // peripheral regs - " " // AHB3 Peripherals - " " // cortex regs - " " // bootrom - " " // option byte area - ""; - -static const char* const memory_map_template_H7 = - "" - "" - "" - " " // ITCMRAM 64kB - " " // DTCMRAM 128kB - " " // RAM D1 512kB - " " // RAM D2 288kB - " " // RAM D3 64kB - " " - " 0x%x" - " " - " " // peripheral regs - " " // cortex regs - " " // bootrom - ""; - -static const char* const memory_map_template_H72x3x = - "" - "" - "" - " " // ITCMRAM 64kB + Optional remap - " " // DTCMRAM 128kB - " " // RAM D1 320kB - " " // RAM D2 23kB - " " // RAM D3 16kB - " " // Backup RAM 4kB - " " - " 0x%x" - " " - " " // peripheral regs - " " // External Memory - " " // External device - " " // cortex regs - " " // bootrom - ""; - -static const char* const memory_map_template_F4_DE = - "" - "" - "" - " " // code = sram, bootrom or flash; flash is bigger - " " // sram - " " // Sectors 0..3 - " 0x4000" // 16kB - " " - " " // Sector 4 - " 0x10000" // 64kB - " " - " " // Sectors 5..7 - " 0x20000" // 128kB - " " - " " // peripheral regs - " " // cortex regs - " " // bootrom - " " // otp - " " // option byte area - ""; - char* make_memory_map(stlink_t *sl) { // this will be freed in serve() const uint32_t sz = 4096; diff --git a/src/st-util/memory-map.h b/src/st-util/memory-map.h new file mode 100644 index 000000000..6f34eedac --- /dev/null +++ b/src/st-util/memory-map.h @@ -0,0 +1,217 @@ +#ifndef MEMORY_MAP_H +#define MEMORY_MAP_H + +static const char* const memory_map_template_F4 = + "" + "" + "" + " " // code = sram, bootrom or flash; flash is bigger + " " // ccm ram + " " // sram + " " // Sectors 0...3 + " 0x4000" // 16 kB + " " + " " // Sector 4 + " 0x10000" // 64 kB + " " + " " // Sectors 5...11 + " 0x20000" // 128 kB + " " + " " // peripheral regs + " " // AHB3 Peripherals + " " // cortex regs + " " // bootrom + " " // option byte area + ""; + +static const char* const memory_map_template_F4_HD = + "" + "" + "" + " " // code = sram, bootrom or flash; flash is bigger + " " // ccm ram + " " // sram + " " // fmc bank 1 (nor/psram/sram) + " " // fmc bank 2 & 3 (nand flash) + " " // fmc bank 4 (pc card) + " " // fmc sdram bank 1 & 2 + " " // Sectors 0...3 + " 0x4000" // 16 kB + " " + " " // Sector 4 + " 0x10000" // 64 kB + " " + " " // Sectors 5...11 + " 0x20000" // 128 kB + " " + " " // peripheral regs + " " // cortex regs + " " // bootrom + " " // option byte area + ""; + +static const char* const memory_map_template_F2 = + "" + "" + "" + " " // code = sram, bootrom or flash; flash is bigger + " " // SRAM + " " // Sectors 0...3 + " 0x4000" // 16 kB + " " + " " // Sector 4 + " 0x10000" // 64 kB + " " + " " // Sectors 5... + " 0x20000" // 128 kB + " " + " " // peripheral regs + " " // cortex regs + " " // bootrom + " " // option byte area + ""; + +static const char* const memory_map_template_L4 = + "" + "" + "" + " " // code = sram, bootrom or flash; flash is bigger + " " // SRAM2 (32 kB) + " " // SRAM1 (96 kB) + " " + " 0x800" + " " + " " // peripheral regs + " " // AHB3 Peripherals + " " // cortex regs + " " // bootrom + " " // option byte area + " " // option byte area + ""; + +static const char* const memory_map_template_L496 = + "" + "" + "" + " " // code = sram, bootrom or flash; flash is bigger + " " // SRAM2 (64 kB) + " " // SRAM1 + aliased SRAM2 (256 + 64 = 320 kB) + " " + " 0x800" + " " + " " // peripheral regs + " " // AHB3 Peripherals + " " // cortex regs + " " // bootrom + " " // option byte area + " " // option byte area + ""; + +static const char* const memory_map_template = + "" + "" + "" + " " // code = sram, bootrom or flash; flash is bigger + " " // SRAM (8 kB) + " " + " 0x%x" + " " + " " // peripheral regs + " " // cortex regs + " " // bootrom + " " // option byte area + ""; + +static const char* const memory_map_template_F7 = + "" + "" + "" + " " // ITCM ram 16 kB + " " // ITCM flash + " " // SRAM + " " // Sectors 0...3 + " 0x8000" // 32 kB + " " + " " // Sector 4 + " 0x20000" // 128 kB + " " + " " // Sectors 5...7 + " 0x40000" // 128 kB + " " + " " // peripheral regs + " " // AHB3 Peripherals + " " // cortex regs + " " // bootrom + " " // option byte area + ""; + +static const char* const memory_map_template_H7 = + "" + "" + "" + " " // ITCMRAM 64 kB + " " // DTCMRAM 128 kB + " " // RAM D1 512 kB + " " // RAM D2 288 kB + " " // RAM D3 64 kB + " " + " 0x%x" + " " + " " // peripheral regs + " " // cortex regs + " " // bootrom + ""; + +static const char* const memory_map_template_H72x3x = + "" + "" + "" + " " // ITCMRAM 64 kB + Optional remap + " " // DTCMRAM 128 kB + " " // RAM D1 320 kB + " " // RAM D2 23 kB + " " // RAM D3 16 kB + " " // Backup RAM 4 kB + " " + " 0x%x" + " " + " " // peripheral regs + " " // External Memory + " " // External device + " " // cortex regs + " " // bootrom + ""; + +static const char* const memory_map_template_F4_DE = + "" + "" + "" + " " // code = sram, bootrom or flash; flash is bigger + " " // SRAM + " " // Sectors 0..3 + " 0x4000" // 16 kB + " " + " " // Sector 4 + " 0x10000" // 64 kB + " " + " " // Sectors 5..7 + " 0x20000" // 128 kB + " " + " " // peripheral regs + " " // cortex regs + " " // bootrom + " " // otp + " " // option byte area + ""; + +#endif // MEMORY_MAP_H \ No newline at end of file From 81575cb2d9fd1db32dd12581baf642447e5ab623 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sat, 23 Dec 2023 17:45:17 +0100 Subject: [PATCH 491/503] [doc] Updated udev directory (#1358) --- doc/compiling.md | 2 +- doc/tutorial.md | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/doc/compiling.md b/doc/compiling.md index 8936f6a58..e2c686c0a 100644 --- a/doc/compiling.md +++ b/doc/compiling.md @@ -165,7 +165,7 @@ Within the sourcefolder of the project, these rules are located in the subdirect Afterwards it may be necessary to reload the udev rules: ```sh -$ sudo cp -a config/udev/rules.d/* /etc/udev/rules.d/ +$ sudo cp -a config/udev/rules.d/* /lib/udev/rules.d/ $ sudo udevadm control --reload-rules $ sudo udevadm trigger ``` diff --git a/doc/tutorial.md b/doc/tutorial.md index 736c4283b..36c80c674 100644 --- a/doc/tutorial.md +++ b/doc/tutorial.md @@ -62,7 +62,7 @@ On my system I see the following: crw-rw-rw- 1 root root 189, 528 Jan 24 17:52 /dev/bus/usb/005/017 ``` -which is world writable (this is from the `MODE:="0666"` below). I have several files in my `/etc/udev/rules.d` directory. In this particular case, the `49-stlinkv2-1.rules` file contains the following: +which is world writable (this is from the `MODE:="0666"` below). I have several files in my `/lib/udev/rules.d` directory. In this particular case, the `49-stlinkv2-1.rules` file contains the following: ``` # STM32 nucleo boards, with onboard STLINK/V2-1 @@ -81,7 +81,7 @@ SUBSYSTEMS=="usb", ATTRS{idVendor}=="0483", ATTRS{idProduct}=="374b", \ and the `idVendor` of `0483` and `idProduct` of `374b` matches the vendor id from the `lsusb` output. -Make sure that you have all 3 files from [/config/udev/rules.d](https://github.com/stlink-org/stlink/tree/master/config/udev/rules.d) in your `/etc/udev/rules.d` directory. After copying new files or editing existing files in `/etc/udev/ruled.d` you should run the following: +Make sure that you have all 3 files from [/config/udev/rules.d](https://github.com/stlink-org/stlink/tree/master/config/udev/rules.d) in your `/lib/udev/rules.d` directory. After copying new files or editing existing files in `/lib/udev/rules.d` you should run the following: ``` sudo udevadm control --reload-rules From 135a5472d9fd52d252774dce2b5d05cdc25dd458 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 24 Dec 2023 00:01:35 +0100 Subject: [PATCH 492/503] Reverted commit ba335a47 "STM32F76xxx: Added flashing in dual bank mode" --- inc/stlink.h | 2 - inc/stm32flash.h | 1 - src/stlink-lib/calculate.c | 2 +- src/stlink-lib/common.c | 91 ----------------------------------- src/stlink-lib/common_flash.c | 4 +- 5 files changed, 3 insertions(+), 97 deletions(-) diff --git a/inc/stlink.h b/inc/stlink.h index 920822a85..788392d72 100644 --- a/inc/stlink.h +++ b/inc/stlink.h @@ -233,8 +233,6 @@ struct _stlink { uint32_t max_trace_freq; // set by stlink_open_usb() - bool dual_bank; // set for F7xxx devices by reading optcr - uint32_t otp_base; uint32_t otp_size; }; diff --git a/inc/stm32flash.h b/inc/stm32flash.h index 4fed8b597..a5081d694 100644 --- a/inc/stm32flash.h +++ b/inc/stm32flash.h @@ -142,7 +142,6 @@ #define FLASH_F7_OPTCR_START 1 #define FLASH_F7_OPTCR1_BOOT_ADD0 0 #define FLASH_F7_OPTCR1_BOOT_ADD1 16 -#define FLASH_F7_OPTCR_DBANK (29) /* FLASH_OPTCR Dual Bank Mode */ // F7 Flash control register #define FLASH_F7_CR_STRT 16 diff --git a/src/stlink-lib/calculate.c b/src/stlink-lib/calculate.c index a8a66a844..95a94143b 100644 --- a/src/stlink-lib/calculate.c +++ b/src/stlink-lib/calculate.c @@ -36,7 +36,7 @@ uint32_t calculate_F4_sectornum(uint32_t flashaddr) { } } -uint32_t calculate_F7_sectornum_old(uint32_t flashaddr) { +uint32_t calculate_F7_sectornum(uint32_t flashaddr) { flashaddr &= ~STM32_FLASH_BASE; // Page now holding the actual flash address if (flashaddr < 0x20000) { diff --git a/src/stlink-lib/common.c b/src/stlink-lib/common.c index 4ff90ef3d..57aa53a25 100644 --- a/src/stlink-lib/common.c +++ b/src/stlink-lib/common.c @@ -318,19 +318,6 @@ int32_t stlink_load_device_params(stlink_t *sl) { } } - // F76xxx device with dual bank - if (sl->chip_id == STM32_CHIPID_F76xxx) { - // Check the nDBANK bit in OPTCR - uint32_t optcr; - stlink_read_option_control_register32(sl, & optcr); - - if (!(optcr & (1 << STM32F7_FLASH_OPTCR_DBANK))) - { - sl->dual_bank = true; - } - DLOG("*** stm32f76xx dual-bank %d ***\n", sl->dual_bank); - } - // H7 devices with small flash has one bank if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK && sl->flash_type == STM32_FLASH_TYPE_H7) { @@ -843,87 +830,9 @@ int32_t write_buffer_to_sram(stlink_t *sl, flash_loader_t *fl, const uint8_t *bu return (ret); } -/* STM32F7 Series Flash memory dual bank mode - * See application note AN4826 pp.18 - */ - -struct sectors_f7 { - int sector; - uint32_t base; - uint32_t size; -}; - -static const struct sectors_f7 f7_single[] = { - { 0, 0x08000000, 0x8000 }, - { 1, 0x08008000, 0x8000 }, - { 2, 0x08010000, 0x8000 }, - { 3, 0x08018000, 0x8000 }, - { 4, 0x08020000, 0x20000 }, - { 5, 0x08040000, 0x40000 }, - { 6, 0x08080000, 0x40000 }, - { 7, 0x080C0000, 0x40000 }, - { 0, 0, 0 }, -}; - -static const struct sectors_f7 f7_dual[] = { - { 0, 0x08000000, 0x4000 }, - { 1, 0x08004000, 0x4000 }, - { 2, 0x08008000, 0x4000 }, - { 3, 0x0800C000, 0x4000 }, - { 4, 0x08010000, 0x10000 }, - { 5, 0x08020000, 0x20000 }, - { 6, 0x08040000, 0x20000 }, - { 7, 0x08060000, 0x20000 }, - { 8, 0x08080000, 0x20000 }, - { 9, 0x080A0000, 0x20000 }, - { 10, 0x080C0000, 0x20000 }, - { 11, 0x080E0000, 0x20000 }, - { 12, 0x08100000, 0x4000 }, - { 13, 0x08104000, 0x4000 }, - { 14, 0x08108000, 0x4000 }, - { 15, 0x0810C000, 0x4000 }, - { 16, 0x08110000, 0x10000 }, - { 17, 0x08120000, 0x20000 }, - { 18, 0x08140000, 0x20000 }, - { 19, 0x08160000, 0x20000 }, - { 20, 0x08180000, 0x20000 }, - { 21, 0x081A0000, 0x20000 }, - { 22, 0x081C0000, 0x20000 }, - { 23, 0x081E0000, 0x20000 }, - { 0, 0, 0 }, -}; - -static const struct sectors_f7 *get_f7_info(stlink_t *sl) { - return sl->dual_bank ? f7_dual : f7_single; -} - -static const struct sectors_f7 *find_sector(stlink_t *sl, uint32_t flashaddr) { - for (const struct sectors_f7 *s = get_f7_info(sl); s->base; s++) { - const uint32_t end = s->base + s->size; - if ((s->base <= flashaddr) && (flashaddr < end)) { - return s; - } - } - fprintf(stderr, "Bad address %#x\n", flashaddr); - exit(0); -} - -uint32_t calculate_F7_sectornum(stlink_t *sl, uint32_t flashaddr) { - if (sl->chip_id == STM32_CHIPID_F76xxx) { - const struct sectors_f7 *s = find_sector(sl, flashaddr); - return s->sector; - } - return calculate_F7_sectornum_old(flashaddr); -} - // 291 uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr) { - if (sl->chip_id == STM32_CHIPID_F76xxx) { - const struct sectors_f7 *s = find_sector(sl, flashaddr); - return s->size; - } - if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || diff --git a/src/stlink-lib/common_flash.c b/src/stlink-lib/common_flash.c index fc377a471..ef6b8370c 100644 --- a/src/stlink-lib/common_flash.c +++ b/src/stlink-lib/common_flash.c @@ -145,7 +145,7 @@ static inline int32_t write_flash_sr(stlink_t *sl, uint32_t bank, uint32_t val) } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { sr_reg = FLASH_F4_SR; } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { - sr_reg = (bank == BANK_1) ? FLASH_F7_SR1 : FLASH_F7_SR2; + sr_reg = FLASH_F7_SR; } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || sl->flash_type == STM32_FLASH_TYPE_G4) { sr_reg = FLASH_Gx_SR; @@ -1025,7 +1025,7 @@ int32_t stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { } else if (sl->chip_id == STM32_CHIPID_F7 || sl->chip_id == STM32_CHIPID_F76xxx) { // calculate the actual page from the address - uint32_t sector = calculate_F7_sectornum(sl, flashaddr); + uint32_t sector = calculate_F7_sectornum(flashaddr); fprintf(stderr, "EraseFlash - Sector:0x%x Size:0x%x ", sector, stlink_calculate_pagesize(sl, flashaddr)); From a60c24cbc040fe63b12172e93d0d99778b30eaca Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 24 Dec 2023 00:34:29 +0100 Subject: [PATCH 493/503] General Project Update - [doc] Updated system requirements - Updated CHANGELOG.md - Updated list of contributors --- CHANGELOG.md | 19 +++++++--- contributors.txt | 16 +++++---- doc/version_support.md | 67 ++++++++++++++++------------------- src/stlink-gui/CMakeLists.txt | 2 +- 4 files changed, 55 insertions(+), 49 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index 9b6cccdf9..c477eb54a 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -2,7 +2,7 @@ # v1.8.0 -Release date: 2023-xx-xx +Release date: 2024-xx-xx This release drops support for macOS and some older operating systems. Check project README for details. Removed Travis CI integration as it is no longer functional. @@ -16,7 +16,7 @@ Features: - Support for writing option bytes on STM32F0/F1/F3 ([#346](https://github.com/stlink-org/stlink/pull/346), [#458](https://github.com/stlink-org/stlink/pull/458), [#808](https://github.com/stlink-org/stlink/pull/808), [#1084](https://github.com/stlink-org/stlink/pull/1084), [#1112](https://github.com/stlink-org/stlink/pull/1112)) - Initial support for STM32 L5 & U5 devices and minor changes ([#1005](https://github.com/stlink-org/stlink/pull/1005), [#1096](https://github.com/stlink-org/stlink/pull/1096), [#1247](https://github.com/stlink-org/stlink/pull/1247), [#1300](https://github.com/stlink-org/stlink/pull/1300), [#1301](https://github.com/stlink-org/stlink/pull/1301)) -- Added chip-IDs for STM32G0B0/G0B1/G0C1/G050/G051/G061 ([#1140](https://github.com/stlink-org/stlink/pull/1140)) +- Added chip-IDs for STM32G0B0/G0B1/G0C1/G050/G051/G061 ([#1140](https://github.com/stlink-org/stlink/pull/1140), [#1359](https://github.com/stlink-org/stlink/pull/1359)) - Added option byte info for STM32F411XX ([#1141](https://github.com/stlink-org/stlink/pull/1141)) - Expanded and revised list of chips ([#1145](https://github.com/stlink-org/stlink/pull/1145), [#1164](https://github.com/stlink-org/stlink/pull/1164)) - STM32H72X/3X: Added full access to all device memory ([#1158](https://github.com/stlink-org/stlink/pull/1158), [#1159](https://github.com/stlink-org/stlink/pull/1159)) @@ -29,7 +29,9 @@ Features: - Added parametres option_base, option_size for F401xD_xE ([#1235](https://github.com/stlink-org/stlink/pull/1235)) - Added support for option bytes to F1xx_XLD (GD32F30x) ([#1250](https://github.com/stlink-org/stlink/pull/1250)) - Added option byte address for L4Rx devices ([#1254](https://github.com/stlink-org/stlink/pull/1254)) -- Added udev-rule rule for the STLink v3 MINIE programmer ([#1274](https://github.com/stlink-org/stlink/pull/1274), [#1281](https://github.com/stlink-org/stlink/pull/1281)) +- Added udev-rule rule for the STLink v3 MINIE programmer ([#1274](https://github.com/stlink-org/stlink/pull/1274), [#1281](https://github.com/stlink-org/stlink/pull/1281), [#1358](https://github.com/stlink-org/stlink/pull/1358)) +- Added support for STM32C0x1 devices ([#1329](https://github.com/stlink-org/stlink/pull/1329), [#1354](https://github.com/stlink-org/stlink/pull/1354)) +- First Implementation of the OTP Read/Write function ([#1352](https://github.com/stlink-org/stlink/pull/1352), [#1353](https://github.com/stlink-org/stlink/pull/1353)) Updates & changes: @@ -42,11 +44,13 @@ Updates & changes: - [doc] Human-readable flash_type in chip-id files ([#1155](https://github.com/stlink-org/stlink/pull/1155), commit [#1745bf5](https://github.com/stlink-org/stlink/commit/1745bf5193c4d3186d4f6fde59cc86e9bad6e61b)) - Dropped execute bits from source code files ([#1167](https://github.com/stlink-org/stlink/pull/1167)) - Use proper Markdown headers for supported MCUs ([#1168](https://github.com/stlink-org/stlink/pull/1168)) +- Ability to flash F7 devices when in dual-bank mode ([#1174](https://github.com/stlink-org/stlink/pull/1174)) - Removed redundant array ([#1178](https://github.com/stlink-org/stlink/pull/1178)) - Updated chip config files from the library structs ([#1181](https://github.com/stlink-org/stlink/pull/1181)) - [doc] Corrected file path in tutorial ([#1186](https://github.com/stlink-org/stlink/pull/1186)) - Improved chipid checks and printouts ([#1188](https://github.com/stlink-org/stlink/pull/1188)) - [refactoring] Sourcefile 'common.c' ([#1218](https://github.com/stlink-org/stlink/pull/1218), [#1220](https://github.com/stlink-org/stlink/pull/1220)) +- [STM32H735]: Set hardware breakpoints for external bus ([#1219](https://github.com/stlink-org/stlink/pull/1219)) - Set C standard through cmake variables ([#1221](https://github.com/stlink-org/stlink/pull/1221)) - [doc] Added make install to the macOS compiling instructions ([#1259](https://github.com/stlink-org/stlink/pull/1259)) - [doc] Linux Install from code Documentation improvement ([#1263](https://github.com/stlink-org/stlink/pull/1263), commit [#43498de](https://github.com/stlink-org/stlink/commit/43498dedf651260ef34197e512d35e3ad7142401)) @@ -56,12 +60,13 @@ Updates & changes: - [doc] Updated package source link for Arch Linux ([#1318](https://github.com/stlink-org/stlink/pull/1318)) - CMake: Avoid hard-wired /usr/local/share ([#1325](https://github.com/stlink-org/stlink/pull/1325)) + Fixes: - Fixed some flashing issues on STM32L0 ([#681](https://github.com/stlink-org/stlink/pull/681), [#1203](https://github.com/stlink-org/stlink/pull/1203), [#1225](https://github.com/stlink-org/stlink/pull/1225), [#1253](https://github.com/stlink-org/stlink/pull/1253), [#1289](https://github.com/stlink-org/stlink/pull/1289), [#1330](https://github.com/stlink-org/stlink/pull/1330)) - cmake: Install shared libraries in proper directories ([#1098](https://github.com/stlink-org/stlink/pull/1098), [#1138](https://github.com/stlink-org/stlink/pull/1138), [#1154](https://github.com/stlink-org/stlink/pull/1154)) - cmake: Install shared libraries in proper directories ([#1142](https://github.com/stlink-org/stlink/pull/1142)) -- Fixed clearance of the H7 dual bank flag ([#1146](https://github.com/stlink-org/stlink/pull/1146), [#1147](https://github.com/stlink-org/stlink/pull/1147)) +- Fixed clearance of the H7 dual bank flag ([#1146](https://github.com/stlink-org/stlink/pull/1146), [#1147](https://github.com/stlink-org/stlink/pull/1147), [#1342](https://github.com/stlink-org/stlink/pull/1342)) - Fix for 'libusb_devices were leaked' when no ST-LINK programmer was found ([#1150](https://github.com/stlink-org/stlink/pull/1150)) - Set of fixes and improvements ([#1153](https://github.com/stlink-org/stlink/pull/1153), [#1154](https://github.com/stlink-org/stlink/pull/1154)) - Removed limit check for WRITEMEM_32BIT ([#1157](https://github.com/stlink-org/stlink/pull/1157)) @@ -75,7 +80,7 @@ Fixes: - st-flash and other utilities search for chip files in the wrong directory ([#1180](https://github.com/stlink-org/stlink/pull/1180), commit [#c8fc656](https://github.com/stlink-org/stlink/commit/c8fc6561fead79ad49c09d82bab864745086792c)) - Fixed broken build on 32 bit systems ([#985](https://github.com/stlink-org/stlink/pull/985), [#1175](https://github.com/stlink-org/stlink/pull/1175), commit [#c8fc656](https://github.com/stlink-org/stlink/commit/c8fc6561fead79ad49c09d82bab864745086792c)) - Define 'SSIZE_MAX' if not defined ([#1183](https://github.com/stlink-org/stlink/pull/1183)) -- STM32G031G8: BOOT_LOCK is not possible to change on option bytes address 0x1FFF7870 ([#1194](https://github.com/stlink-org/stlink/pull/1194)) +- [STM32G031G8]: BOOT_LOCK is not possible to change on option bytes address 0x1FFF7870 ([#1194](https://github.com/stlink-org/stlink/pull/1194)) - Fixed compliation for OpenBSD 7.0 ([#1202](https://github.com/stlink-org/stlink/pull/1202)) - Included 'SSIZE_MAX' from 'limits.h' in 'src/common.c' ([#1207](https://github.com/stlink-org/stlink/pull/1207)) - Fix for libusb_kernel_driver_active & error handling for st.st_size () ([#1210](https://github.com/stlink-org/stlink/pull/1210), [#1211](https://github.com/stlink-org/stlink/pull/1211), [#1214](https://github.com/stlink-org/stlink/pull/1214)) @@ -93,7 +98,11 @@ Fixes: - Fixed unbounded write and check return values of sscanf ([#1306](https://github.com/stlink-org/stlink/pull/1306)) - Added null check for return value of stlink_chipid_get_params() ([#1307](https://github.com/stlink-org/stlink/pull/1307)) - Fixed warning in a few *.cmake files ([#1309](https://github.com/stlink-org/stlink/pull/1309)) +- Fixed support for STM32U5 chips ([#1320](https://github.com/stlink-org/stlink/pull/1320), [#1355](https://github.com/stlink-org/stlink/pull/1355)) +- [STM32G0B1]: Erase fails starting page 64 ([#1321](https://github.com/stlink-org/stlink/pull/1321)) - Notification "unknown option -- u" in tool st-util ([#1326](https://github.com/stlink-org/stlink/pull/1326), [#1327](https://github.com/stlink-org/stlink/pull/1327)) +- Do not crash when the STLink chip returns a voltage factor of zero ([#1343](https://github.com/stlink-org/stlink/pull/1343)) +- stlink-gui: failed to allocate 139988352155568 bytes ([#1356](https://github.com/stlink-org/stlink/pull/1356)) # v1.7.0 diff --git a/contributors.txt b/contributors.txt index 2425ae7f0..dacb4e4af 100644 --- a/contributors.txt +++ b/contributors.txt @@ -4,7 +4,7 @@ Alexey Cherevatenko Alexey Panarin Anatoli Klassen [dev26th] Andrea Mucignat -Andrew Andrianov [necromant] +Andrew Andrianov [nekromant] Andrey Yurovsky Andy Isaacson Andreas Sandberg [andysan] @@ -52,10 +52,10 @@ Greg Meiste [meisteg] Grzegorz Szymaszek [gszy] Guillaume Revaillot [grevaillot] Gwenhael Goavec-Merou [trabucayre] -Hakkavélin +[Hakkavélin] Halt Hammerzeit +Hsu Pu [hsupu] [hydroconstructor] -htk Ian Griffiths Jack Peel Jakub Tyszkowski @@ -68,6 +68,7 @@ Jens Hoffmann Jerome Lambourg Jim Paris Jiří Netolický +Jerry Jacobs [xor-gate] Jerry Nosky [jnosky] Jochen Wilhelmy [Jochen0x90h] John Hall [simplerobot] @@ -90,7 +91,6 @@ Michael Pratt [prattmic] Michael Sparmann Mike Szczys Magnus Lundin [mlu] -mux Ned Konz Nic McDonald Nicolas Schodet @@ -98,7 +98,7 @@ Oleksiy Slyshyk [slyshykO] Olivier Croquette Olivier Gay Onno Kortmann -orangeudav +[orangeudav] Pavel Kirienko Pekka Nikander Pete Nelson @@ -107,6 +107,7 @@ Peter Zotov Petteri Aimonen Piotr Haber [RafaelLeeImg] +[rcubee] Rene Hopf [rene-dev] Robin Kreis Roger Wolff [rewolff] @@ -117,11 +118,11 @@ Sean Simmons Sergey Alirzaev Simon Derr [sderr] Simon Wright -[simplerobot] Stany Marcel Stefan Misik Sven Wegener -Tarek Bochkati [tarek-bochkati] (STMicroelectronics) +Tarek Bochkati [tarek-bochkati] +[texane] Timothy Lee [timothytylee] Tuomo Kaikkonen Theodore A. Roth @@ -136,6 +137,7 @@ Vasiliy Glazov [Vascom] Vegard Storheil Eriksen Viacheslav Dobromyslov Victor Mayoral Vilches +[whitequark] William Ransohoff [WRansohoff] Wojciech A. Koszek Woodrow Douglass diff --git a/doc/version_support.md b/doc/version_support.md index 022fb5e4d..c87ad1772 100644 --- a/doc/version_support.md +++ b/doc/version_support.md @@ -25,42 +25,34 @@ Maintained versions of: Other Linux-/Unix-based Operating Systems: -| Operating System | libusb | cmake | libgtk-dev | Notes | -| ------------------------ | ------------------------------ | ---------- | ----------- | ------------------------ | -| Debian Sid | 1.0.24 | 3.22.1 | 3.24.31 | | -| Debian 11 (Bullseye) | 1.0.24 | 3.**18.4** | 3.24.24 | | -| Debian 10 (Buster) | 1.0.**22** | 3.**13.4** | 3.24.**5** | | -| | | | | | -| Ubuntu 20.04 LTS (Focal) | 1.0.23 | 3.**16.3** | 3.24.**18** | | -| | | | | | -| Alpine 3.15 | 1.0.24 | 3.21.3 | 3.24.30 | End of Support: Nov 2023 | -| Alpine 3.14 | 1.0.24 | 3.20.3 | 3.24.28 | End of Support: May 2023 | -| | | | | | -| FreeBSD 13.x | 1.0.**16-18** (API 0x01000102) | 3.22.1 | 3.24.31 | | -| FreeBSD 12.x | 1.0.**16-18** (API 0x01000102) | 3.22.1 | 3.24.31 | | -| | | | | | -| NetBSD 9.x | 1.0.24 | 3.21.2 | 3.24.30 | | -| NetBSD 8.x | 1.0.24 | 3.**19.7** | 3.24.27 | | -| | | | | | -| CentOS 9 Stream [x64] | 1.0.24 (`libusbx`) | 3.20.3 | 3.24.30 | | -| CentOS 8 Stream [x64] | 1.0.23 (`libusbx`) | 3.20.2 | 3.**22.30** | | -| | | | | | -| ALT Linux Sisyphus | 1.0.24 | 3.22.1 | 3.24.31 | | -| ALT Linux P10 | 1.0.24 | 3.20.5 | 3.24.31 | | -| ALT Linux P9 | 1.0.**22** | 3.**16.3** | 3.24.29 | | -| | | | | | -| OpenMandriva Rolling | 1.0.24 | 3.22.1 | 3.24.31 | | -| OpenMandriva Cooker | 1.0.24 | 3.22.1 | 3.24.31 | | -| OpenMandriva Lx 4.2 | 1.0.24 | 3.**19.3** | 3.24.24 | | -| | | | | | -| Arch Linux | 1.0.24 | 3.22.1 | - | | -| KaOS [x64] | 1.0.24 | 3.22.1 | 3.24.31 | | -| Mageia Cauldron | 1.0.24 | 3.22.1 | 3.24.31 | | -| PCLinuxOS [x64] | (?) | 3.22.1 | 3.24.31 | | -| Solus [x64] | 1.0.24 | 3.22.1 | 3.24.30 | | -| Void Linux | 1.0.24 | 3.22.1 | 3.24.31 | | -| Slackware Current | 1.0.24 | 3.21.4 | 3.24.31 | | -| Adélie 1.0 | 1.0.23 | 3.**16.4** | 3.24.23 | | +| Operating System | libusb | cmake | libgtk-dev | End of
OS-Support | +| ------------------------ | ------------------------------ | ---------- | ----------- | ---------------------- | +| Debian Sid | 1.0.24 | 3.22.1 | 3.24.31 | | +| Debian 11 (Bullseye) | 1.0.24 | 3.**18.4** | 3.24.24 | | +| Debian 10 (Buster) | 1.0.**22** | 3.**13.4** | 3.24.**5** | Jun 2024 | +| | | | | | +| Ubuntu 20.04 LTS (Focal) | 1.0.23 | 3.**16.3** | 3.24.**18** | May 2025 | +| | | | | | +| FreeBSD 13.x | 1.0.**16-18** (API 0x01000102) | 3.22.1 | 3.24.31 | | +| FreeBSD 12.x | 1.0.**16-18** (API 0x01000102) | 3.22.1 | 3.24.31 | Dec 2023 | +| | | | | | +| NetBSD 9.x | 1.0.24 | 3.21.2 | 3.24.30 | | +| NetBSD 8.x | 1.0.24 | 3.**19.7** | 3.24.27 | | +| | | | | | +| CentOS 9 Stream [x64] | 1.0.24 (`libusbx`) | 3.20.3 | 3.24.30 | | +| CentOS 8 Stream [x64] | 1.0.23 (`libusbx`) | 3.20.2 | 3.**22.30** | May 2024 | +| | | | | | +| ALT Linux Sisyphus | 1.0.24 | 3.22.1 | 3.24.31 | | +| ALT Linux P10 | 1.0.24 | 3.20.5 | 3.24.31 | | +| ALT Linux P9 | 1.0.**22** | 3.**16.3** | 3.24.29 | | +| | | | | | +| KaOS [x64] | 1.0.24 | 3.22.1 | 3.24.31 | | +| Mageia Cauldron | 1.0.24 | 3.22.1 | 3.24.31 | | +| PCLinuxOS [x64] | (?) | 3.22.1 | 3.24.31 | | +| Solus [x64] | 1.0.24 | 3.22.1 | 3.24.30 | | +| Void Linux | 1.0.24 | 3.22.1 | 3.24.31 | | +| Slackware Current | 1.0.24 | 3.21.4 | 3.24.31 | | +| Adélie 1.0 | 1.0.23 | 3.**16.4** | 3.24.23 | | ## Unsupported Operating Systems (as of Release v1.8.0) @@ -68,9 +60,12 @@ Systems with highlighted versions remain compatible with this toolset. | Operating System | libusb | cmake | End of
OS-Support | | ---------------------------------------- | ------------------------------ | ---------- | ---------------------- | +| Alpine 3.15 | 1.0.**24** | 3.**21.3** | Nov 2023 | | Fedora 35 [x64] | 1.0.**24** | 3.**21.3** | Dec 2022 | +| Alpine 3.14 | 1.0.**24** | 3.**20.3** | May 2023 | | CentOS / Rocky Linux / AlmaLinux 8 [x64] | 1.0.**23** (`libusbx`) | 3.**20.3** | Dec 2021 | | Fedora 34 [x64] | 1.0.**24** (`libusbx`) | 3.**19.7** | Jun 2022 | +| OpenMandriva Lx 4.2 | 1.0.**24** | 3.**19.3** | Mar 2023 | | Mageia 8 | 1.0.**24** | 3.**19.2** | Aug 2022 | | Alpine 3.13 | 1.0.**24** | 3.**18.4** | Nov 2022 | | Ubuntu 21.04 (Hirsute) | 1.0.**24** | 3.**18.4** | Jan 2022 | diff --git a/src/stlink-gui/CMakeLists.txt b/src/stlink-gui/CMakeLists.txt index 042e8d37d..062814e42 100644 --- a/src/stlink-gui/CMakeLists.txt +++ b/src/stlink-gui/CMakeLists.txt @@ -2,7 +2,7 @@ # Build GUI ### -if (NOT WIN32 AND NOT CMAKE_CROSSCOMPILING) +if (NOT WIN32) find_package(PkgConfig) pkg_check_modules(GTK3 gtk+-3.0) From 5613f281c5b8b4abe0e0f94149e5d6a4b7afa1c1 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 24 Dec 2023 00:46:56 +0100 Subject: [PATCH 494/503] Fixed compilation error. --- src/stlink-lib/common.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/stlink-lib/common.c b/src/stlink-lib/common.c index 57aa53a25..c9bf67157 100644 --- a/src/stlink-lib/common.c +++ b/src/stlink-lib/common.c @@ -858,7 +858,7 @@ uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr) { } } else if (sl->chip_id == STM32_CHIPID_F7 || sl->chip_id == STM32_CHIPID_F76xxx) { - uint32_t sector = calculate_F7_sectornum(sl, flashaddr); + uint32_t sector = calculate_F7_sectornum(flashaddr); if (sector < 4) { sl->flash_pgsz = 0x8000; From c1efbec7a77eec1dc9611d448c4870cb6121ea2e Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 24 Dec 2023 11:47:51 +0100 Subject: [PATCH 495/503] Fixed incorrect chip-ID for STM32C01x MCU --- config/chips/C011xx.chip | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/config/chips/C011xx.chip b/config/chips/C011xx.chip index b961a18f8..eac66ca68 100644 --- a/config/chips/C011xx.chip +++ b/config/chips/C011xx.chip @@ -2,7 +2,7 @@ # dev_type STM32C011xx ref_manual_id 0490 -chip_id 0x453 // STM32_CHIPID_C011xx +chip_id 0x443 // STM32_CHIPID_C011xx flash_type C0 flash_size_reg 0x1fff75a0 flash_pagesize 0x800 // 2 KB From e7f41b2965d95eff75114c6f89f13c24cb7357a2 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 24 Dec 2023 12:08:08 +0100 Subject: [PATCH 496/503] Support for STLINK/v2 & /v3 max trace buffers --- inc/stlink.h | 9 ++++++++- src/st-trace/trace.c | 2 +- src/stlink-lib/usb.c | 9 ++++++++- 3 files changed, 17 insertions(+), 3 deletions(-) diff --git a/inc/stlink.h b/inc/stlink.h index 788392d72..0c3675083 100644 --- a/inc/stlink.h +++ b/inc/stlink.h @@ -66,7 +66,8 @@ enum target_state { #define STLINK_V3_MAX_FREQ_NB 10 -#define STLINK_TRACE_BUF_LEN 2048 +#define STLINK_V2_TRACE_BUF_LEN 2048 +#define STLINK_V3_TRACE_BUF_LEN 8192 #define STLINK_V2_MAX_TRACE_FREQUENCY 2000000 #define STLINK_V3_MAX_TRACE_FREQUENCY 24000000 #define STLINK_DEFAULT_TRACE_FREQUENCY 2000000 @@ -273,7 +274,13 @@ int32_t stlink_fread(stlink_t* sl, const char* path, bool is_ihex, stm32_addr_t int32_t stlink_load_device_params(stlink_t *sl); int32_t stlink_target_connect(stlink_t *sl, enum connect_type connect); +#include +#include +#include +#include +#include #include +#include #ifdef __cplusplus } diff --git a/src/st-trace/trace.c b/src/st-trace/trace.c index 04557794a..4ef03c07b 100644 --- a/src/st-trace/trace.c +++ b/src/st-trace/trace.c @@ -425,7 +425,7 @@ static trace_state update_trace(st_trace_t *trace, uint8_t c) { } static bool read_trace(stlink_t *stlink, st_trace_t *trace) { - uint8_t buffer[STLINK_TRACE_BUF_LEN]; + uint8_t buffer[max_trace_buf_len]; int32_t length = stlink_trace_read(stlink, buffer, sizeof(buffer)); if (length < 0) { diff --git a/src/stlink-lib/usb.c b/src/stlink-lib/usb.c index d3a57c33f..b0d0494cf 100644 --- a/src/stlink-lib/usb.c +++ b/src/stlink-lib/usb.c @@ -977,11 +977,18 @@ int32_t _stlink_usb_enable_trace(stlink_t* sl, uint32_t frequency) { unsigned char* const cmd = sl->c_buf; ssize_t size; uint32_t rep_len = 2; + uint32_t max_trace_buf_len; + + if(sl->version.stlink_v == 2) { + max_trace_buf_len = STLINK_V2_TRACE_BUF_LEN; + } else (sl->version.stlink_v == 3) { + max_trace_buf_len = STLINK_V3_TRACE_BUF_LEN; + } int32_t i = fill_command(sl, SG_DXFER_TO_DEV, rep_len); cmd[i++] = STLINK_DEBUG_COMMAND; cmd[i++] = STLINK_DEBUG_APIV2_START_TRACE_RX; - write_uint16(&cmd[i + 0], 2 * STLINK_TRACE_BUF_LEN); + write_uint16(&cmd[i + 0], 2 * max_trace_buf_len); write_uint32(&cmd[i + 2], frequency); size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_STATUS, "START_TRACE_RX"); From 45c31e91696db3f44f2fb4aee51ba2c869fa81f7 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 24 Dec 2023 12:26:01 +0100 Subject: [PATCH 497/503] Added interface for spdlog (optional) --- src/stlink-lib/logging.h | 17 +++++++++++++++++ src/stlink-lib/spdlog_wrapper.h | 14 ++++++++++++++ 2 files changed, 31 insertions(+) create mode 100644 src/stlink-lib/spdlog_wrapper.h diff --git a/src/stlink-lib/logging.h b/src/stlink-lib/logging.h index cb49a7af3..560e20eca 100644 --- a/src/stlink-lib/logging.h +++ b/src/stlink-lib/logging.h @@ -8,10 +8,16 @@ #ifndef LOGGING_H #define LOGGING_H +#include +#include "spdlog_wrapper.h" + #ifdef __cplusplus extern "C" { #endif // __cplusplus +/* Optional: Enable interface for SPDLOG to replace UglyLogging */ +// #define SPDLOG_LOGGING + enum ugly_loglevel { UDEBUG = 90, UINFO = 50, @@ -44,6 +50,17 @@ int32_t ugly_libusb_log_level(enum ugly_loglevel v); #define ELOG_HELPER(format, ...) ugly_log(UERROR, UGLY_LOG_FILE, format, __VA_ARGS__) #define ELOG(...) ugly_log(UERROR, UGLY_LOG_FILE, __VA_ARGS__) +#if defined(SPDLOG_LOGGING) +#undef DLOG_HELPER +#undef ILOG_HELPER +#undef WLOG_HELPER +#undef ELOG_HELPER +#define DLOG(...) spdlogLog(UDEBUG, __VA_ARGS__) +#define ILOG(...) spdlogLog(UINFO, __VA_ARGS__) +#define WLOG(...) spdlogLog(UWARN, __VA_ARGS__) +#define ELOG(...) spdlogLog(UERROR, __VA_ARGS__) +#endif // SPDLOG_LOGGING + #ifdef __cplusplus } #endif // __cplusplus diff --git a/src/stlink-lib/spdlog_wrapper.h b/src/stlink-lib/spdlog_wrapper.h new file mode 100644 index 000000000..26f34c8b5 --- /dev/null +++ b/src/stlink-lib/spdlog_wrapper.h @@ -0,0 +1,14 @@ +#ifndef _SPDLOG_WRAPPER_ +#define _SPDLOG_WRAPPER_ + +#ifdef __cplusplus +#define EXTERNC extern "C" +#else +#define EXTERNC +#endif + +EXTERNC int spdlogLog(int level, const char *str, ...); + +#undef EXTERNC + +#endif \ No newline at end of file From 816730f4f7517611e5ff3a03067ae0a673fb72bd Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 24 Dec 2023 19:15:03 +0100 Subject: [PATCH 498/503] [refactoring] Clean-up & bugfix for st-trace --- inc/stlink.h | 3 - src/st-trace/trace.c | 159 ++++++++++++++++------------------------ src/st-trace/trace.h | 24 ++++++ src/stlink-lib/common.c | 17 ----- src/stlink-lib/usb.c | 6 +- 5 files changed, 90 insertions(+), 119 deletions(-) create mode 100644 src/st-trace/trace.h diff --git a/inc/stlink.h b/inc/stlink.h index 0c3675083..d516e5c4f 100644 --- a/inc/stlink.h +++ b/inc/stlink.h @@ -255,9 +255,6 @@ int32_t stlink_current_mode(stlink_t *sl); int32_t stlink_force_debug(stlink_t *sl); int32_t stlink_target_voltage(stlink_t *sl); int32_t stlink_set_swdclk(stlink_t *sl, int32_t freq_khz); -int32_t stlink_trace_enable(stlink_t* sl, uint32_t frequency); -int32_t stlink_trace_disable(stlink_t* sl); -int32_t stlink_trace_read(stlink_t* sl, uint8_t* buf, uint32_t size); int32_t stlink_parse_ihex(const char* path, uint8_t erased_pattern, uint8_t* *mem, uint32_t* size, uint32_t* begin); uint8_t stlink_get_erased_pattern(stlink_t *sl); int32_t stlink_mwrite_sram(stlink_t *sl, uint8_t* data, uint32_t length, stm32_addr_t addr); diff --git a/src/st-trace/trace.c b/src/st-trace/trace.c index 4ef03c07b..591e29252 100644 --- a/src/st-trace/trace.c +++ b/src/st-trace/trace.c @@ -97,6 +97,20 @@ BOOL WINAPI CtrlHandler(DWORD fdwCtrlType) { } #endif +int32_t stlink_trace_enable(stlink_t *sl, uint32_t frequency) { + DLOG("*** stlink_trace_enable ***\n"); + return (sl->backend->trace_enable(sl, frequency)); +} + +int32_t stlink_trace_disable(stlink_t *sl) { + DLOG("*** stlink_trace_disable ***\n"); + return (sl->backend->trace_disable(sl)); +} + +int32_t stlink_trace_read(stlink_t *sl, uint8_t *buf, uint32_t size) { + return (sl->backend->trace_read(sl, buf, size)); +} + static void usage(void) { puts("st-trace - usage:"); puts(" -h, --help Print this help"); @@ -112,8 +126,7 @@ static void usage(void) { puts(" -f, --force Ignore most initialization errors"); } -static bool parse_frequency(char* text, uint32_t* result) -{ +static bool parse_frequency(char* text, uint32_t* result) { if (text == NULL) { ELOG("Invalid frequency.\n"); return false; @@ -193,12 +206,10 @@ bool parse_options(int32_t argc, char **argv, st_settings_t *settings) { ugly_init(settings->logging_level); break; case 'c': - if (!parse_frequency(optarg, &settings->core_frequency)) - error = true; + if (!parse_frequency(optarg, &settings->core_frequency)) error = true; break; case 't': - if (!parse_frequency(optarg, &settings->trace_frequency)) - error = true; + if (!parse_frequency(optarg, &settings->trace_frequency)) error = true; break; case 'n': settings->reset_board = false; @@ -226,29 +237,24 @@ bool parse_options(int32_t argc, char **argv, st_settings_t *settings) { error = true; } - if (error && !settings->force) - return false; + if (error && !settings->force) return false; return true; } static stlink_t *stlink_connect(const st_settings_t *settings) { - return stlink_open_usb(settings->logging_level, false, - settings->serial_number, 0); + return stlink_open_usb(settings->logging_level, false, settings->serial_number, 0); } -static bool enable_trace(stlink_t *stlink, const st_settings_t *settings, - uint32_t trace_frequency) { +static bool enable_trace(stlink_t *stlink, const st_settings_t *settings, uint32_t trace_frequency) { if (stlink_force_debug(stlink)) { ELOG("Unable to debug device\n"); - if (!settings->force) - return false; + if (!settings->force) return false; } if (settings->reset_board && stlink_reset(stlink, RESET_SOFT_AND_HALT)) { ELOG("Unable to reset device\n"); - if (!settings->force) - return false; + if (!settings->force) return false; } stlink_write_debug32(stlink, STLINK_REG_DHCSR, @@ -262,29 +268,24 @@ static bool enable_trace(stlink_t *stlink, const st_settings_t *settings, stlink_write_debug32(stlink, STLINK_REG_DWT_FUNCTION2, 0); stlink_write_debug32(stlink, STLINK_REG_DWT_FUNCTION3, 0); stlink_write_debug32(stlink, STLINK_REG_DWT_CTRL, 0); - stlink_write_debug32( - stlink, STLINK_REG_DBGMCU_CR, + stlink_write_debug32(stlink, STLINK_REG_DBGMCU_CR, STLINK_REG_DBGMCU_CR_DBG_SLEEP | STLINK_REG_DBGMCU_CR_DBG_STOP | STLINK_REG_DBGMCU_CR_DBG_STANDBY | STLINK_REG_DBGMCU_CR_TRACE_IOEN | STLINK_REG_DBGMCU_CR_TRACE_MODE_ASYNC); if (stlink_trace_enable(stlink, trace_frequency)) { ELOG("Unable to turn on tracing in stlink\n"); - if (!settings->force) - return false; + if (!settings->force) return false; } - stlink_write_debug32(stlink, STLINK_REG_TPI_CSPSR, - STLINK_REG_TPI_CSPSR_PORT_SIZE_1); + stlink_write_debug32(stlink, STLINK_REG_TPI_CSPSR, STLINK_REG_TPI_CSPSR_PORT_SIZE_1); if (settings->core_frequency) { uint32_t prescaler = settings->core_frequency / trace_frequency - 1; if (prescaler > STLINK_REG_TPI_ACPR_MAX) { - ELOG("Trace frequency prescaler %d out of range. Try setting a faster " - "trace frequency.\n", - prescaler); - if (!settings->force) - return false; + ELOG("Trace frequency prescaler %d out of range. Try setting a faster " + "trace frequency.\n", prescaler); + if (!settings->force) return false; } stlink_write_debug32(stlink, STLINK_REG_TPI_ACPR, prescaler); // Set TPIU_ACPR clock divisor @@ -294,12 +295,11 @@ static bool enable_trace(stlink_t *stlink, const st_settings_t *settings, stlink_write_debug32(stlink, STLINK_REG_TPI_SPPR, STLINK_REG_TPI_SPPR_SWO_NRZ); stlink_write_debug32(stlink, STLINK_REG_ITM_LAR, STLINK_REG_ITM_LAR_KEY); - stlink_write_debug32(stlink, STLINK_REG_ITM_TCC, - 0x00000400); // Set sync counter + stlink_write_debug32(stlink, STLINK_REG_ITM_TCC, 0x00000400); // Set sync counter stlink_write_debug32(stlink, STLINK_REG_ITM_TCR, STLINK_REG_ITM_TCR_TRACE_BUS_ID_1 | - STLINK_REG_ITM_TCR_TS_ENA | - STLINK_REG_ITM_TCR_ITM_ENA); + STLINK_REG_ITM_TCR_TS_ENA | + STLINK_REG_ITM_TCR_ITM_ENA); stlink_write_debug32(stlink, STLINK_REG_ITM_TER, STLINK_REG_ITM_TER_PORTS_ALL); stlink_write_debug32(stlink, STLINK_REG_ITM_TPR, @@ -333,9 +333,7 @@ static bool enable_trace(stlink_t *stlink, const st_settings_t *settings, static trace_state update_trace_idle(st_trace_t *trace, uint8_t c) { // Handle a trace byte when we are in the idle state. - if (TRACE_OP_IS_TARGET_SOURCE(c)) { - return TRACE_STATE_TARGET_SOURCE; - } + if (TRACE_OP_IS_TARGET_SOURCE(c)) return TRACE_STATE_TARGET_SOURCE; if (TRACE_OP_IS_SOURCE(c)) { uint8_t size = TRACE_OP_GET_SOURCE_SIZE(c); @@ -345,36 +343,28 @@ static trace_state update_trace_idle(st_trace_t *trace, uint8_t c) { WLOG("Unsupported source 0x%x size %d\n", addr, size); trace->unknown_sources |= (1 << addr); } - if (size == 1) - return TRACE_STATE_SKIP_1; - if (size == 2) - return TRACE_STATE_SKIP_2; - if (size == 3) - return TRACE_STATE_SKIP_4; + if (size == 1) return TRACE_STATE_SKIP_1; + if (size == 2) return TRACE_STATE_SKIP_2; + if (size == 3) return TRACE_STATE_SKIP_4; } if (TRACE_OP_IS_LOCAL_TIME(c) || TRACE_OP_IS_GLOBAL_TIME(c)) { trace->count_time_packets++; - return TRACE_OP_GET_CONTINUATION(c) ? TRACE_STATE_SKIP_FRAME - : TRACE_STATE_IDLE; + return TRACE_OP_GET_CONTINUATION(c) ? TRACE_STATE_SKIP_FRAME : TRACE_STATE_IDLE; } if (TRACE_OP_IS_EXTENSION(c)) { - return TRACE_OP_GET_CONTINUATION(c) ? TRACE_STATE_SKIP_FRAME - : TRACE_STATE_IDLE; + return TRACE_OP_GET_CONTINUATION(c) ? TRACE_STATE_SKIP_FRAME : TRACE_STATE_IDLE; } - if (TRACE_OP_IS_OVERFLOW(c)) { - trace->count_hw_overflow++; - } + if (TRACE_OP_IS_OVERFLOW(c)) trace->count_hw_overflow++; if (!(trace->unknown_opcodes[c / 8] & (1 << c % 8))) WLOG("Unknown opcode 0x%02x\n", c); trace->unknown_opcodes[c / 8] |= (1 << c % 8); trace->count_error++; - return TRACE_OP_GET_CONTINUATION(c) ? TRACE_STATE_SKIP_FRAME - : TRACE_STATE_IDLE; + return TRACE_OP_GET_CONTINUATION(c) ? TRACE_STATE_SKIP_FRAME : TRACE_STATE_IDLE; } static trace_state update_trace(st_trace_t *trace, uint8_t c) { @@ -383,8 +373,7 @@ static trace_state update_trace(st_trace_t *trace, uint8_t c) { // Parse the input using a state machine. if (trace->state == TRACE_STATE_UNKNOWN) { - if (TRACE_OP_IS_TARGET_SOURCE(c) || TRACE_OP_IS_LOCAL_TIME(c) || - TRACE_OP_IS_GLOBAL_TIME(c)) + if (TRACE_OP_IS_TARGET_SOURCE(c) || TRACE_OP_IS_LOCAL_TIME(c) || TRACE_OP_IS_GLOBAL_TIME(c)) trace->state = TRACE_STATE_IDLE; } @@ -394,14 +383,12 @@ static trace_state update_trace(st_trace_t *trace, uint8_t c) { case TRACE_STATE_TARGET_SOURCE: putchar(c); - if (c == '\n') - fflush(stdout); + if (c == '\n') fflush(stdout); trace->count_target_data++; return TRACE_STATE_IDLE; case TRACE_STATE_SKIP_FRAME: - return TRACE_OP_GET_CONTINUATION(c) ? TRACE_STATE_SKIP_FRAME - : TRACE_STATE_IDLE; + return TRACE_OP_GET_CONTINUATION(c) ? TRACE_STATE_SKIP_FRAME : TRACE_STATE_IDLE; case TRACE_STATE_SKIP_4: return TRACE_STATE_SKIP_3; @@ -425,7 +412,7 @@ static trace_state update_trace(st_trace_t *trace, uint8_t c) { } static bool read_trace(stlink_t *stlink, st_trace_t *trace) { - uint8_t buffer[max_trace_buf_len]; + uint8_t* buffer = 0; int32_t length = stlink_trace_read(stlink, buffer, sizeof(buffer)); if (length < 0) { @@ -453,8 +440,7 @@ static bool read_trace(stlink_t *stlink, st_trace_t *trace) { return true; } -static void check_for_configuration_error(stlink_t *stlink, st_trace_t *trace, - uint32_t trace_frequency) { +static void check_for_configuration_error(stlink_t *stlink, st_trace_t *trace, uint32_t trace_frequency) { // Only check configuration one time after the first 10 seconds of running. time_t elapsed_time_s = time(NULL) - trace->start_time; if (trace->configuration_checked || elapsed_time_s < 10) { @@ -469,8 +455,7 @@ static void check_for_configuration_error(stlink_t *stlink, st_trace_t *trace, bool error_bad_data = (trace->count_error > 1 || trace->unknown_sources > 0); bool error_dropped_data = (trace->count_sw_overflow > 0); - if (!error_no_data && !error_low_data && !error_bad_data && - !error_dropped_data) + if (!error_no_data && !error_low_data && !error_bad_data && !error_dropped_data) return; WLOG("****\n"); @@ -487,8 +472,7 @@ static void check_for_configuration_error(stlink_t *stlink, st_trace_t *trace, stlink_read_debug32(stlink, STLINK_REG_TPI_ACPR, &prescaler); if (prescaler) { uint32_t system_clock_speed = (prescaler + 1) * trace_frequency; - WLOG("Verify the system clock is running at %d Hz.\n", - system_clock_speed); + WLOG("Verify the system clock is running at %d Hz.\n", system_clock_speed); } WLOG("Try specifying the system clock with the --clock=XX command line " "option.\n"); @@ -510,11 +494,8 @@ static void check_for_configuration_error(stlink_t *stlink, st_trace_t *trace, uint32_t offset = 0; for (uint32_t i = 0; i <= 0xFF; i++) if (trace->unknown_opcodes[i / 8] & (1 << i % 8)) { - uint32_t n = - snprintf(buffer + offset, sizeof(buffer) - offset, "%02x, ", i); - if (n >= sizeof(buffer) - offset) { - break; - } + uint32_t n = snprintf(buffer + offset, sizeof(buffer) - offset, "%02x, ", i); + if (n >= sizeof(buffer) - offset) break; offset += n; } WLOG("Unknown Opcodes: %s\n", buffer); @@ -523,11 +504,8 @@ static void check_for_configuration_error(stlink_t *stlink, st_trace_t *trace, offset = 0; for (uint32_t i = 0; i < 32; i++) if (trace->unknown_sources & (1 << i)) { - uint32_t n = - snprintf(buffer + offset, sizeof(buffer) - offset, "%d, ", i); - if (n >= sizeof(buffer) - offset) { - break; - } + uint32_t n = snprintf(buffer + offset, sizeof(buffer) - offset, "%d, ", i); + if (n >= sizeof(buffer) - offset) break; offset += n; } WLOG("Unknown Sources: %s\n", buffer); @@ -583,48 +561,38 @@ int32_t main(int32_t argc, char **argv) { if (stlink->chip_id == STM32_CHIPID_UNKNOWN) { ELOG("Your stlink is not connected to a device\n"); - if (!settings.force) - return APP_RESULT_STLINK_MISSING_DEVICE; + if (!settings.force) return APP_RESULT_STLINK_MISSING_DEVICE; } if (!(stlink->version.flags & STLINK_F_HAS_TRACE)) { ELOG("Your stlink does not support tracing\n"); - if (!settings.force) - return APP_RESULT_STLINK_UNSUPPORTED_LINK; + if (!settings.force) return APP_RESULT_STLINK_UNSUPPORTED_LINK; } if (!(stlink->chip_flags & CHIP_F_HAS_SWO_TRACING)) { - const struct stlink_chipid_params *params = - stlink_chipid_get_params(stlink->chip_id); - ELOG("We do not support SWO output for device '%s'\n", - params ? params->dev_type : ""); - if (!settings.force) - return APP_RESULT_STLINK_UNSUPPORTED_DEVICE; + const struct stlink_chipid_params *params = stlink_chipid_get_params(stlink->chip_id); + ELOG("We do not support SWO output for device '%s'\n", params ? params->dev_type : ""); + if (!settings.force) return APP_RESULT_STLINK_UNSUPPORTED_DEVICE; } uint32_t trace_frequency = settings.trace_frequency; - if (!trace_frequency) - trace_frequency = STLINK_DEFAULT_TRACE_FREQUENCY; + if (!trace_frequency) trace_frequency = STLINK_DEFAULT_TRACE_FREQUENCY; uint32_t max_trace_freq = stlink->max_trace_freq; uint32_t min_trace_freq = 0; if (settings.core_frequency != 0) { - if (max_trace_freq > settings.core_frequency / 5) - max_trace_freq = settings.core_frequency / 5; + if (max_trace_freq > settings.core_frequency / 5) max_trace_freq = settings.core_frequency / 5; min_trace_freq = settings.core_frequency / (STLINK_REG_TPI_ACPR_MAX + 1); } - if (trace_frequency > max_trace_freq || - trace_frequency < min_trace_freq) { - ELOG("Invalid trace frequency %d (min %d max %d)\n", trace_frequency, - min_trace_freq, max_trace_freq); - if (!settings.force) - return APP_RESULT_UNSUPPORTED_TRACE_FREQUENCY; + if (trace_frequency > max_trace_freq || trace_frequency < min_trace_freq) { + ELOG("Invalid trace frequency %d (min %d max %d)\n", trace_frequency, min_trace_freq, + max_trace_freq); + if (!settings.force) return APP_RESULT_UNSUPPORTED_TRACE_FREQUENCY; } if (!enable_trace(stlink, &settings, trace_frequency)) { ELOG("Unable to enable trace mode\n"); - if (!settings.force) - return APP_RESULT_STLINK_STATE_ERROR; + if (!settings.force) return APP_RESULT_STLINK_STATE_ERROR; } ILOG("Reading Trace\n"); @@ -634,8 +602,7 @@ int32_t main(int32_t argc, char **argv) { if (stlink_run(stlink, RUN_NORMAL)) { ELOG("Unable to run device\n"); - if (!settings.force) - return APP_RESULT_STLINK_STATE_ERROR; + if (!settings.force) return APP_RESULT_STLINK_STATE_ERROR; } while (!g_abort_trace && read_trace(stlink, &trace)) { diff --git a/src/st-trace/trace.h b/src/st-trace/trace.h new file mode 100644 index 000000000..8dfc7e42d --- /dev/null +++ b/src/st-trace/trace.h @@ -0,0 +1,24 @@ +/* + * File: trace.h + * + * Tool st-trace + */ + +#ifndef TRACE_H +#define TRACE_H + +int32_t stlink_trace_enable(stlink_t* sl, uint32_t frequency); +int32_t stlink_trace_disable(stlink_t* sl); +int32_t stlink_trace_read(stlink_t* sl, uint8_t* buf, uint32_t size); + +static void usage(void); +static bool parse_frequency(char* text, uint32_t* result); +bool parse_options(int32_t argc, char **argv, st_settings_t *settings); +static stlink_t *stlink_connect(const st_settings_t *settings); +static bool enable_trace(stlink_t *stlink, const st_settings_t *settings, uint32_t trace_frequency); +static trace_state update_trace_idle(st_trace_t *trace, uint8_t c); +static trace_state update_trace(st_trace_t *trace, uint8_t c); +static bool read_trace(stlink_t *stlink, st_trace_t *trace); +static void check_for_configuration_error(stlink_t *stlink, st_trace_t *trace, uint32_t trace_frequency); + +#endif // TRACE_H \ No newline at end of file diff --git a/src/stlink-lib/common.c b/src/stlink-lib/common.c index c9bf67157..3e49a779d 100644 --- a/src/stlink-lib/common.c +++ b/src/stlink-lib/common.c @@ -599,23 +599,6 @@ int32_t stlink_current_mode(stlink_t *sl) { return (STLINK_DEV_UNKNOWN_MODE); } -// 274 -int32_t stlink_trace_enable(stlink_t *sl, uint32_t frequency) { - DLOG("*** stlink_trace_enable ***\n"); - return (sl->backend->trace_enable(sl, frequency)); -} - -// 275 -int32_t stlink_trace_disable(stlink_t *sl) { - DLOG("*** stlink_trace_disable ***\n"); - return (sl->backend->trace_disable(sl)); -} - -// 276 -int32_t stlink_trace_read(stlink_t *sl, uint8_t *buf, uint32_t size) { - return (sl->backend->trace_read(sl, buf, size)); -} - // 294 void stlink_print_data(stlink_t *sl) { if (sl->q_len <= 0 || sl->verbose < UDEBUG) { diff --git a/src/stlink-lib/usb.c b/src/stlink-lib/usb.c index b0d0494cf..83e2652ea 100644 --- a/src/stlink-lib/usb.c +++ b/src/stlink-lib/usb.c @@ -977,13 +977,13 @@ int32_t _stlink_usb_enable_trace(stlink_t* sl, uint32_t frequency) { unsigned char* const cmd = sl->c_buf; ssize_t size; uint32_t rep_len = 2; - uint32_t max_trace_buf_len; + uint32_t max_trace_buf_len = 0; if(sl->version.stlink_v == 2) { max_trace_buf_len = STLINK_V2_TRACE_BUF_LEN; - } else (sl->version.stlink_v == 3) { + } else if (sl->version.stlink_v == 3) { max_trace_buf_len = STLINK_V3_TRACE_BUF_LEN; - } + }; int32_t i = fill_command(sl, SG_DXFER_TO_DEV, rep_len); cmd[i++] = STLINK_DEBUG_COMMAND; From 8c581c3eec91248de028c332a06ea276bbb2e969 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Mon, 25 Dec 2023 14:40:10 +0100 Subject: [PATCH 499/503] Updated CHANGELOG.md --- CHANGELOG.md | 1 + src/stlink-lib/common_flash.c | 4 +--- 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index c477eb54a..c1f998600 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -95,6 +95,7 @@ Fixes: - [compilation] Corrected path to stlink/chips subdirectory ([#1276](https://github.com/stlink-org/stlink/pull/1276), [#1279](https://github.com/stlink-org/stlink/pull/1279)) - [compilation] Fixed GUI compilation failure on OpenBSD i386 ([#1284](https://github.com/stlink-org/stlink/pull/1284)) - [STM32U5x5]: Last bytes are not written (flashed) when len()%16 <= 8 ([#1303](https://github.com/stlink-org/stlink/pull/1303), [#1315](https://github.com/stlink-org/stlink/pull/1315)) +- [STM32WLE]: Erase flash fails on second page ([#1305](https://github.com/stlink-org/stlink/pull/1305), commit [#7dcb130](https://github.com/stlink-org/stlink/commit/7dcb1302d8b91b2217c4ce50cb255aa8e78ab001)) - Fixed unbounded write and check return values of sscanf ([#1306](https://github.com/stlink-org/stlink/pull/1306)) - Added null check for return value of stlink_chipid_get_params() ([#1307](https://github.com/stlink-org/stlink/pull/1307)) - Fixed warning in a few *.cmake files ([#1309](https://github.com/stlink-org/stlink/pull/1309)) diff --git a/src/stlink-lib/common_flash.c b/src/stlink-lib/common_flash.c index ef6b8370c..6a519f1fc 100644 --- a/src/stlink-lib/common_flash.c +++ b/src/stlink-lib/common_flash.c @@ -387,9 +387,7 @@ int32_t check_flash_error(stlink_t *sl) { res &= ~PGAERR; } - if (res) { - ELOG("Flash programming error: %#010x\n", res); - } + if (res) ELOG("Flash programming error: %#010x\n", res); return (-1); } From 0145baeb2e3bac31bf9d3cbd0dab38d70618d46b Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sat, 20 Jan 2024 13:00:52 +0100 Subject: [PATCH 500/503] Fixed memory alignment for STM32L5/U5/H5 chips (Closes #1362) --- src/stlink-lib/common_flash.c | 2 +- src/stlink-lib/flash_loader.c | 5 +++++ 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/src/stlink-lib/common_flash.c b/src/stlink-lib/common_flash.c index 6a519f1fc..aa8db5bfd 100644 --- a/src/stlink-lib/common_flash.c +++ b/src/stlink-lib/common_flash.c @@ -1140,7 +1140,7 @@ int32_t stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { // set bank 1 for erasure val &= ~(1 << FLASH_L5_NSCR_NSBKER); } - // sec 7.9.9 for U5, 6.9.9 for L5 (for L7 we have 7 bits instead 8 bits for U5 but + // sec 7.9.9 for U5, 6.9.9 for L5 (for L7 we have 7 bits instead of 8 bits for U5 but // the bit position for 8th bit reserved. // Maybe the best solution is to handle each one separately. val &= ~(0xFF << 3); diff --git a/src/stlink-lib/flash_loader.c b/src/stlink-lib/flash_loader.c index 9511c9282..16c717ca7 100644 --- a/src/stlink-lib/flash_loader.c +++ b/src/stlink-lib/flash_loader.c @@ -748,6 +748,11 @@ int32_t stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t sl->flash_type == STM32_FLASH_TYPE_G4 || sl->flash_type == STM32_FLASH_TYPE_L5_U5_H5 || sl->flash_type == STM32_FLASH_TYPE_C0) { + + if (sl->flash_type == STM32_FLASH_TYPE_L5_U5_H5 && (len % 16)) { + WLOG("Data size is aligned to 16 byte"); + len += 16 - len%16; + } DLOG("Starting %3u page write\n", len / sl->flash_pgsz); for (off = 0; off < len; off += sizeof(uint32_t)) { uint32_t data; From 32e8dcc8b5dbed7b6412e7838ea1b2c41f0247fd Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 21 Jan 2024 14:43:22 +0100 Subject: [PATCH 501/503] [doc] Updated tutorial: Access to the UART via a virtual COM port (Closes #1334) --- doc/tutorial.md | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/doc/tutorial.md b/doc/tutorial.md index 36c80c674..da09978e7 100644 --- a/doc/tutorial.md +++ b/doc/tutorial.md @@ -43,7 +43,7 @@ The stlink-gui offers the following features: Within the GUI main window tooltips explain the available user elements. -## Solutions to common problems +## HowTos & solutions to common problems ### a) Verify if udev rules are set correctly (by Dave Hylands) @@ -164,6 +164,17 @@ However the external bus can be *RAM* or *ROM* depending on design. The STM32H735-DK has external FLASH at address 0x90000000. As a result, because the entire external memory range is `ram` as it could be either, software breakpoints (Z0) get sent when a breakpoint is created and they never get tripped as the memory area is read only. +### f) UART-Access via a virtual COM port + +Access to the Universal Asynchronous Receiver Transmitter (UART) via a virtual COM port is not related to the stlink toolset itself. It is an independent feature that should natively be available on UNIX-based operating systems. Windows operating systems require the installation of a virtual COM device driver. The appropriate device driver is downloaded and installed automatically via Windows Update in the background as soon as the device is plugged-in for the first time. A connected ST-LINK programmer with UART functionality is detected as a CDC (ACM) USB device. After each reset the device will be reloaded and will pop up as `/dev/ttyACM0` or `/dev/ttyACM1` depending on the specific design. + +UART connections to the interface are typically initiated with a serial terminal. For UNIX operating systems we recommend to use either [minicom](https://en.wikipedia.org/wiki/Minicom) (terminal-based) or [cutecom](https://cutecom.sourceforge.net/) (GUI-based). Windows users should have a look at [Teraterm](https://github.com/TeraTermProject/teraterm). + +Most common and established settings for the interface are 115200 or 9600 baud together with the `8-N-1` configuration, standing for (8) data bits, no parity bit (N) and (1) stop bit. Please refer to relevant literature on the UART interface for more detailed technical information and limitations. + +Note: On some debian-based UNIX-based systems the `modemmanager` package is installed by default. In has been reported that this tool unfortunately may delay the release of the serial port to applications which is handled by the operating system in the background. Subseqently the CDC/ACM device is also delayed after each reset. This typically includes not only the connection itself, but also some programming operations (at least those using the mass storage emulation). However one can not predict the behaviour exactly - in some cases the boards may be essentially useless or even working fairly well. +Proper determined functionality can be achieved by uninstalling the `modemmanager` package or by setting an appropriate `udev` device rule. + --- ( Content below is currently unrevised and may be outdated as of Mar 2021. ) From 926e7efe4c44fdf1deac0138c6c78965d49e7dc3 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Tue, 30 Jan 2024 23:40:04 +0100 Subject: [PATCH 502/503] General Project Update - Updated build script for Windows - [doc] Updated documentation on: --> compile instructions --> release preparation steps --> list of supported devices --> OS version support status --- doc/compiling.md | 38 ++------------------------------------ doc/release.md | 14 +++++++------- doc/supported_devices.md | 7 +++++-- doc/version_support.md | 2 +- mingw64-build.bat | 2 +- 5 files changed, 16 insertions(+), 47 deletions(-) diff --git a/doc/compiling.md b/doc/compiling.md index e2c686c0a..804781faa 100644 --- a/doc/compiling.md +++ b/doc/compiling.md @@ -16,35 +16,14 @@ On Windows users should ensure that the following software is installed: 1. Install `git` from 2. Install `cmake` from
Ensure that you add cmake to the $PATH system variable when following the instructions by the setup assistant. -3. Install - - - _EITHER_: Download **MinGW-w64** from . Extract content to `C:\mingw-w64\` and add `C:\mingw-w64\bin\` to PATH-Variable.
- - _OR_: **MSVC toolchain** from Visual Studio Build Tools 2019 +3. Install MinGW-w64
+ Download **MinGW-w64** from . Extract content to `C:\mingw-w64\` and add `C:\mingw-w64\bin\` to PATH-Variable.
4. Create a new destination folder at a place of your choice 5. Open the command-line (cmd.exe) and execute `cd C:\$Path-to-your-destination-folder$\` 6. Fetch the project sourcefiles by running `git clone https://github.com/stlink-org/stlink.git`from the command-line (cmd.exe)
or download and extract the stlink zip-sourcefolder from the Release page on GitHub. -#### MSVC toolchain - minimal installation - -Visual Studio IDE is not necessary, only Windows SDK & build tools are required (~3,3GB). - -1. Open -2. Navigate through menus as follows (might change overtime) - - `All downloads > Tools for Visual Studio 2019 > Build Tools for Visual Studio 2019 > Download` - -3. Start downloaded executable. After Visual Studio Installer bootstraps and main window pops up, open `Individual Components` tab, and pick - -- latest build tools (eg. `MSVC v142 - VS 2019 C++ x64/x86 build tools (v14.25)`) -- latest Windows SDK (eg. `Windows 10 SDK (10.0.18362.0)`) - -4. After installation finishes, you can press `Launch` button in Visual Studio Installer's main menu. - - Thus you can open `Developer Command Prompt for VS 2019`. It is `cmd.exe` instance with adjusted PATHs including eg. `msbuild`. - - Alternatively, you can use `Developer Powershell for VS 2019` which is the same thing for `powershell.exe`. Both are available from Start menu. - - Another option is to add `msbuild` to PATH manually. Its location should be `C:\Program Files (x86)\Microsoft Visual Studio\2019\BuildTools\MSBuild\Current\Bin`. Then, it should be available from any `powershell.exe` or `cmd.exe` session. - ### Building #### MinGW-w64 @@ -58,19 +37,6 @@ Per default the build script (currently) uses `C:\mingw-w64\x86_64-8.1.0-release When installing different toolchains make sure to update the path in the `mingw64-build.bat`.
This can be achieved by opening the .bat file with a common text editor. -#### MSVC toolchain - -1. In a command prompt, change the directory to the folder where the stlink files were cloned (or unzipped) to. -2. Make sure the build folder exists (`mkdir build` if not). -3. From the build folder, run cmake (`cd build; cmake ..`). - -This will create a solution file `stlink.sln` in the build folder. -Now, you can build whole `stlink` suite using following command: - -``` -msbuild /m /p:Configuration=Release stlink.sln -``` - Options: - `/m` - compilation runs in parallel utilizing multiple cores diff --git a/doc/release.md b/doc/release.md index 7d5ead83c..25cb2d5ff 100644 --- a/doc/release.md +++ b/doc/release.md @@ -3,12 +3,12 @@ Release This document describes the necessary steps for developers to create a release: -1. Update `CHANGELOG.md`, `cmake/packaging/deb/changelog` & `cmake/packaging/rpm/changelog` +1. Update changelog (`CHANGELOG.md`, `cmake/packaging/deb/changelog` & `cmake/packaging/rpm/changelog`) 2. Update `.version` with semantic version: `x.x.x` 3. Update `README.md` with semantic version `x.x.x` in commits badge -4. Merge `develop` into `master` -5. Create and push git tag and commits `git tag x.x.x` -6. Create binary packages (.rpm / .deb / .zip) with `make package && sh ./cmake/packaging/windows/generate_binaries.sh` -7. Upload packages to the [release page](https://github.com/stlink-org/stlink/releases) of this project -8. Merge `master` into `develop` -9. Update GitHub security policy (/SECURITY.md) +4. Update GitHub security policy (`SECURITY.md`) +5. Merge `develop` into `master` +6. Create and push git tag and commits `git tag x.x.x` +7. Create binary packages (.rpm / .deb / .zip) with `make package && sh ./cmake/packaging/windows/generate_binaries.sh` +8. Upload packages to the [release page](https://github.com/stlink-org/stlink/releases) of this project +9. Merge `master` into `develop` diff --git a/doc/supported_devices.md b/doc/supported_devices.md index 103c7fb5f..b22b1c11a 100644 --- a/doc/supported_devices.md +++ b/doc/supported_devices.md @@ -30,10 +30,13 @@ More commonly these are: | STM32F4 | M4F | | | STM32G4 | M4F | | | STM32L4 | M4F | | -| STM32F7 | M4F | | -| STM32H7 | M4F | | +| STM32F7 | M7F | | +| STM32H7 | M7F | | | STM32WB | M4F | | | STM32WL | M4 | | +| STM32L5 | M33 | | +| STM32H5 | M33 | | +| STM32U5 | M33 | | # Chinese Clone-Chips [may work, but without support!] diff --git a/doc/version_support.md b/doc/version_support.md index c87ad1772..c0c8389dd 100644 --- a/doc/version_support.md +++ b/doc/version_support.md @@ -34,7 +34,6 @@ Other Linux-/Unix-based Operating Systems: | Ubuntu 20.04 LTS (Focal) | 1.0.23 | 3.**16.3** | 3.24.**18** | May 2025 | | | | | | | | FreeBSD 13.x | 1.0.**16-18** (API 0x01000102) | 3.22.1 | 3.24.31 | | -| FreeBSD 12.x | 1.0.**16-18** (API 0x01000102) | 3.22.1 | 3.24.31 | Dec 2023 | | | | | | | | NetBSD 9.x | 1.0.24 | 3.21.2 | 3.24.30 | | | NetBSD 8.x | 1.0.24 | 3.**19.7** | 3.24.27 | | @@ -60,6 +59,7 @@ Systems with highlighted versions remain compatible with this toolset. | Operating System | libusb | cmake | End of
OS-Support | | ---------------------------------------- | ------------------------------ | ---------- | ---------------------- | +| FreeBSD 12.x | 1.0.**16-18** (API 0x01000102) | 3.**22.1** | Dec 2023 | | Alpine 3.15 | 1.0.**24** | 3.**21.3** | Nov 2023 | | Fedora 35 [x64] | 1.0.**24** | 3.**21.3** | Dec 2022 | | Alpine 3.14 | 1.0.**24** | 3.**20.3** | May 2023 | diff --git a/mingw64-build.bat b/mingw64-build.bat index b52e529e2..bc50c97a3 100644 --- a/mingw64-build.bat +++ b/mingw64-build.bat @@ -2,7 +2,7 @@ mkdir build-mingw cd build-mingw -set PATH=C:\Program Files (x86)\CMake\bin;C:\Program Files\CMake\bin;C:\mingw-w64\x86_64-8.1.0-win32-sjlj-rt_v6-rev0\mingw64\bin;%PATH% +set PATH=C:\Program Files\CMake\bin;C:\mingw-w64\x86_64-13.2.0-release-win32-seh-msvcrt-rt_v11-rev1\mingw64\bin;%PATH% cmake -G "MinGW Makefiles" .. mingw32-make mingw32-make install From 133c2564dee478ed2fcf634ae217441ac723b3e3 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Thu, 1 Feb 2024 00:00:02 +0100 Subject: [PATCH 503/503] Release v1.8.0 --- .version | 2 +- CHANGELOG.md | 9 +++++---- README.md | 4 ++-- SECURITY.md | 1 + cmake/packaging/deb/changelog | 6 ++++++ cmake/packaging/rpm/changelog | 3 +++ 6 files changed, 18 insertions(+), 7 deletions(-) diff --git a/.version b/.version index bd8bf882d..27f9cd322 100644 --- a/.version +++ b/.version @@ -1 +1 @@ -1.7.0 +1.8.0 diff --git a/CHANGELOG.md b/CHANGELOG.md index c1f998600..5c618a752 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -2,14 +2,14 @@ # v1.8.0 -Release date: 2024-xx-xx +Release date: 2024-02-01 This release drops support for macOS and some older operating systems. Check project README for details. Removed Travis CI integration as it is no longer functional. Updated system requirements: -- `cmake` >= 3.10.2 -- `libusb` >= 1.0.21 +- `cmake` >= 3.13.0 +- `libusb` >= 1.0.22 - `libgtk-dev` >= 3.22.30 Features: @@ -59,7 +59,7 @@ Updates & changes: - [doc] Fixed broken links ([#1312](https://github.com/stlink-org/stlink/pull/1312)) - [doc] Updated package source link for Arch Linux ([#1318](https://github.com/stlink-org/stlink/pull/1318)) - CMake: Avoid hard-wired /usr/local/share ([#1325](https://github.com/stlink-org/stlink/pull/1325)) - +- [doc] Provide access to the UART via virtual com port ([#1334](https://github.com/stlink-org/stlink/pull/1334), commit [#32e8dcc](https://github.com/stlink-org/stlink/commit/32e8dcc8b5dbed7b6412e7838ea1b2c41f0247fd)) Fixes: @@ -104,6 +104,7 @@ Fixes: - Notification "unknown option -- u" in tool st-util ([#1326](https://github.com/stlink-org/stlink/pull/1326), [#1327](https://github.com/stlink-org/stlink/pull/1327)) - Do not crash when the STLink chip returns a voltage factor of zero ([#1343](https://github.com/stlink-org/stlink/pull/1343)) - stlink-gui: failed to allocate 139988352155568 bytes ([#1356](https://github.com/stlink-org/stlink/pull/1356)) +- [STM32U575RGT6]: Verification failed at offset 43008 ([#1362](https://github.com/stlink-org/stlink/pull/1362), commit [#0145bae](https://github.com/stlink-org/stlink/commit/0145baeb2e3bac31bf9d3cbd0dab38d70618d46b)) # v1.7.0 diff --git a/README.md b/README.md index ad1bfe910..93cdac07d 100644 --- a/README.md +++ b/README.md @@ -3,7 +3,7 @@ [![BSD licensed](https://img.shields.io/badge/license-BSD-blue.svg)](https://raw.githubusercontent.com/hyperium/hyper/master/LICENSE) [![GitHub release](https://img.shields.io/github/release/stlink-org/stlink.svg)](https://github.com/stlink-org/stlink/releases/latest) [![Downloads](https://img.shields.io/github/downloads/stlink-org/stlink/total)](https://github.com/stlink-org/stlink/releases/latest) -![GitHub commits](https://img.shields.io/github/commits-since/stlink-org/stlink/v1.7.0/develop) +![GitHub commits](https://img.shields.io/github/commits-since/stlink-org/stlink/v1.8.0/develop) ![GitHub activity](https://img.shields.io/github/commit-activity/m/stlink-org/stlink) ![GitHub contributors](https://img.shields.io/github/contributors/stlink-org/stlink) [![CodeQL](https://github.com/stlink-org/stlink/actions/workflows/codeql-analysis.yml/badge.svg)](https://github.com/stlink-org/stlink/actions/workflows/codeql-analysis.yml) @@ -81,7 +81,7 @@ We recommend to install `stlink-tools` from the package repository of the used d **macOS**: -**Support for macOS will be dropped with v1.8.0.** +**Support for macOS has been dropped with v1.8.0.** Please use v1.7.0 instead, **but note that this version is no longer maintained and supported!** diff --git a/SECURITY.md b/SECURITY.md index 13432b927..3a357bafc 100644 --- a/SECURITY.md +++ b/SECURITY.md @@ -7,6 +7,7 @@ The following versions of the stlink toolset are currently being supported.
Thu, 01 Feb 2024 00:00:00 +0100 + stlink (1.7.0) unstable; urgency=medium * Release v1.7.0 diff --git a/cmake/packaging/rpm/changelog b/cmake/packaging/rpm/changelog index 3d1c76996..36853060d 100644 --- a/cmake/packaging/rpm/changelog +++ b/cmake/packaging/rpm/changelog @@ -1,3 +1,6 @@ +* Thu Feb 01 2024 Nightwalker-87 - 1.8.0 +- Release v1.8.0 + * Sun Apr 25 2021 Nightwalker-87 - 1.7.0 - Release v1.7.0