Stars
RISC-V Functional ISA Simulator
Small footprint and configurable SDCard core
SD-Card controller, using either SPI, SDIO, or eMMC interfaces
WISHBONE SD Card Controller IP Core
Improved version of http://web.mit.edu/6.111/volume2/www/f2018/tools/sd_controller.v
Multi Bus Memory Controller supporting HyperBUS and OPI
A directory of Western Digital’s RISC-V SweRV Cores
RISC-V Assembly Programmer's Manual
OpenTitan: Open source silicon root of trust
openhwgroup / cve2
Forked from lowRISC/ibexThe CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH Zurich and Ibex work from lowRISC.
Random instruction generator for RISC-V proc 994B essor verification
Spike, a RISC-V ISA Simulator
This tool translates synthesizable SystemC code to synthesizable SystemVerilog.
Implements a synthesizable 16550/16750 UART core in VHDL
The repo contains the SPMP architectural specification, which includes capabilities like access control of read/write/execute requests by an hart, address matching, encoding of permissions, excepti…
Official git repository for libdivide: optimized integer division
Multi-platform nightly builds of open source digital design and verification tools
This task group will propose ISA extension(s) and non-ISA hardware and software interop interfaces to enable routine reuse and composition of a subcategory of custom extensions called composable ex…
Cadence Virtuoso Git Integration written in SKILL++
rbennell-gh / cdsgit_lfs
Forked from cdsgit/cdsgitCadence Virtuoso Git Integration written in SKILL++