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open-logic Public
Forked from open-logic/open-logicOpen Logic FPGA Standard Library
VHDL Other UpdatedMay 20, 2025 -
surf Public
Forked from slaclab/surfA huge VHDL library for FPGA and digital ASIC development
VHDL Other UpdatedMay 19, 2025 -
basic_verilog Public
Forked from pConst/basic_verilogMust-have verilog systemverilog modules
Verilog UpdatedMay 7, 2025 -
synth_school_verif_tasks Public
Forked from serge0699/synth_school_verif_tasksРепозиторий заданий и примеров направления функциональной верификации Школы синтеза цифровых схем
SystemVerilog UpdatedMay 6, 2025 -
vfa Public
Forked from serge0699/vfaРепозиторий канала Verification For All
SystemVerilog Creative Commons Attribution Share Alike 4.0 International UpdatedApr 3, 2025 -
systemverilog-homework Public
Forked from yuri-panchul/systemverilog-homeworkSystemVerilog language-oriented exercises
SystemVerilog MIT License UpdatedApr 1, 2025 -
basics-graphics-music Public
Forked from yuri-panchul/basics-graphics-musicFPGA exercise for beginners
Verilog Other UpdatedApr 1, 2025 -
hdl-modules Public
Forked from hdl-modules/hdl-modulesA collection of reusable, high-quality, peer-reviewed VHDL building blocks.
VHDL BSD 3-Clause "New" or "Revised" License UpdatedFeb 10, 2025 -
riscv-dv Public
Forked from chipsalliance/riscv-dvRandom instruction generator for RISC-V processor verification
Python Apache License 2.0 UpdatedFeb 7, 2025 -
riscv-tests-intro Public
Forked from riscv-tests-intro/riscv-tests-introОткрытый ознакомительный курс "Введение в функциональную верификацию RISC-V ядер"
SystemVerilog Creative Commons Attribution Share Alike 4.0 International UpdatedJan 24, 2025 -
Contest-2023_RISCV-for-FPGA Public
Forked from RISCV-Alliance-Education/Contest-2023_RISCV-for-FPGACurricula grants contest results - Курс RISC-V для FPGA - архитектура, микроархитектурные реализации
UpdatedOct 28, 2024 -
Методические материалы по разработке процессора архитектуры RISC-V
SystemVerilog Creative Commons Attribution Share Alike 4.0 International UpdatedOct 21, 2024 -
riscv-isa-sim Public
Forked from riscv-software-src/riscv-isa-simSpike, a RISC-V ISA Simulator
C Other UpdatedOct 19, 2024 -
riscv-arch-test Public
Forked from riscv-non-isa/riscv-arch-testAssembly Apache License 2.0 UpdatedOct 18, 2024 -
ibex Public
Forked from lowRISC/ibexIbex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
SystemVerilog Apache License 2.0 UpdatedOct 1, 2024 -
core-v-verif Public
Forked from openhwgroup/core-v-verifFunctional verification project for the CORE-V family of RISC-V cores.
Assembly EA60 Other UpdatedSep 24, 2024 -
riscv-asm-manual Public
Forked from riscv-non-isa/riscv-asm-manualRISC-V Assembly Programmer's Manual
Makefile Creative Commons Attribution 4.0 International UpdatedSep 18, 2024 -
ddlm_riscv Public
Forked from RomeoMe5/ddlm_riscvИсходные коды к Цифровой синтез: RISC-V
Verilog MIT License UpdatedSep 9, 2024 -
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tt08-adder-with-flow-control Public template
Forked from yuri-panchul/tt08-adder-with-flow-controlSubmission for Tiny Tapeout 8 - Verilog HDL Projects. An adder with a separate flow control for each argument and the result.
SystemVerilog Apache License 2.0 UpdatedSep 5, 2024 -
uvm-core Public
Forked from accellera-official/uvm-coreSystemVerilog Apache License 2.0 UpdatedSep 3, 2024 -
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uvm_book_examples Public
Forked from yuravg/uvm_book_examplesUVM Book Examples - A Practical Guide to Adopting the Universal Verification Methodology (UVM) Second Edition by Kathleen Meade and Sharon Rosenberg
Verilog Apache License 2.0 UpdatedSep 3, 2024 -
verif_elective_miet Public
Forked from serge0699/verif_elective_mietРепозиторий факультатива по функциональной верификации НИУ МИЭТ
SystemVerilog Creative Commons Attribution Share Alike 4.0 International UpdatedAug 24, 2024 -
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verilog-axis Public
Forked from alexforencich/verilog-axisVerilog AXI stream components for FPGA implementation
Python MIT License UpdatedAug 7, 2024 -
axi Public
Forked from pulp-platform/axiAXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
SystemVerilog Other UpdatedJul 31, 2024 -
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verilog-ethernet Public
Forked from alexforencich/verilog-ethernetVerilog Ethernet components for FPGA implementation
Verilog MIT License UpdatedJul 18, 2024 -
arl Public
Forked from pConst/arllists of most popular repositories for most favoured programming languages (according to StackOverflow)
Python UpdatedJun 24, 2024
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