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opentitan: https://github.com/lowRISC/opentitan
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nvdla: https://github.com/nvdla/hw
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riscv-dv: https://github.com/google/riscv-dv
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core-v-verif: https://github.com/openhwgroup/core-v-verif
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openhmc: https://github.com/unihd-cag/openhmc
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riscv-vip: https://github.com/jerralph/riscv-vip
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ISP-UVM: https://github.com/nelsoncsc/ISP_UVM
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force-riscv: https://github.com/openhwgroup/force-riscv
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core-v-isg: https://github.com/openhwgroup/core-v-isg
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LM-RISCV-DV: https://github.com/Lampro-Mellon/LM-RISCV-DV LM RISC-V DV is a verification environment which integrates SweRV EH-1 Core from Western Digital and a random assembly test generator from RISCV-DV which is a SV/UVM based instructions generator
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fwperiph-dma: https://github.com/Featherweight-IP/fwperiph-dma
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apb-vip-uvm: https://github.com/zhangyl4991/apb-vip-uvm
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axi-uvm: https://github.com/marcoz001/axi-uvm
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amba3-vip: amba3 apb/axi vip
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i2c-vip-uvm: https://github.com/zhangyl4991/i2c-vip-uvm
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SDRAM-Verification: https://github.com/yvnr4you/SDRAM-Verification
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ethernet_10ge_mac_SV_UVM_tb: https://github.com/andres-mancera/ethernet_10ge_mac_SV_UVM_tb
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AXI/AHB/Ethernet: https://github.com/zhajio1988/ExtremeDV_UVM
- Practical-UVM-Step-By-Step: https://github.com/Practical-UVM-Step-By-Step/Practical-UVM-Step-By-Step
- uvmprimer: https://github.com/rdsalemi/uvmprimer
- UVM Tutorial for Candy Lovers: https://github.com/cluelogic/uvm-tutorial-for-candy-lovers
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Cores-SweRV: https://github.com/chipsalliance/Cores-SweRV
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e200_opensource: https://github.com/SI-RISCV/e200_opensource
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ultraembedded_riscv: https://github.com/ultraembedded/riscv
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ultraembedded_ipcores: https://github.com/ultraembedded/cores
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schoolMIPS: https://github.com/MIPSfpga/schoolMIPS
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verilog-pcie: https://github.com/alexforencich/verilog-pcie
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verilog-axi: https://github.com/alexforencich/verilog-axi
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black-parrot: https://github.com/black-parrot/black-parrot
BlackParrot aims to be the default Linux-capable, cache-coherent, RV64GC multicore used by the world.
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zet: https://github.com/marmolejo/zet
Open source implementation of a x86 processor -
ao486: https://github.com/alfikpl/ao486
The ao486 is an x86 compatible Verilog core implementing all features of a 486 SX. -
VexRiscv: https://github.com/SpinalHDL/VexRiscv
A FPGA friendly 32 4F1B bit RISC-V CPU implementation from SpinalHDL -
hadbadge2019_fpgasoc: FPGA SoC code and application example for Hackaday Supercon 2019 badge
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vortexgpgpu Vortex is a full-system RISCV-based GPGPU processor. https://github.com/vortexgpgpu/vortex
- Soclib: http://www.soclib.fr/trac/dev
- Gem5: http://www.m5sim.org/Main_Page
- Datum-Technology-Corporation: https://github.com/Datum-Technology-Corporation