8000 Ahtesham18112011 (# Ahtesham Ahmed ) · GitHub
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Ahtesham18112011/README.md

Hi there, I'm Ahtesham! 👋

Welcome to my GitHub profile.

🚀 About Me

  • 💻 Hardware Description Language enthusiast (Verilog)
  • 🌱 I’m currently learning advanced digital design and FPGA development
  • 👯 I’m looking to collaborate on open-source hardware projects
  • 💬 Ask me about Verilog, FPGAs, and digital circuits

🛠️ Languages and Tools

Verilog

⚡ Hardware Projects

📈 GitHub Stats

Ahtesham's GitHub stats

🔗 Connect with Me

LinkedIn

Popular repositories Loading

  1. RISCV_MYTH RISCV_MYTH Public

    This repository is a summary of the RISC-V based MYTH workshop organised by VSD and Redwood EDA, made by Ahtesham Ahmed of grade 8.

    TL-Verilog 10

  2. RISCV_VSDSquadronFM_Implementation RISCV_VSDSquadronFM_Implementation Public

    This repository is a step-by-step guide to implement a RISC-V based core in VSDSquadronFM

    Verilog 2

  3. vsd-iat vsd-iat Public

    1

  4. VSDSquadron_FM VSDSquadron_FM Public

    This repository is the internship of the VSDSQUADRON_FM board created by Ahtesham Ahmed, class 8. This repository provides the details about VSDSQUADRON_FM and the tasks commanded by the internship…

    Verilog 1

  5. Traffic_controller_VSDSquadronFM Traffic_controller_VSDSquadronFM Public

    This repository contains verilog code for a Traffic controller system, logic behind it, and finally implementation in VSDSqudronFM

    Verilog 1

  6. Ahtesham18112011 Ahtesham18112011 Public

    Config files for my GitHub profile.

0