Stars
An open source, parameterized SystemVerilog digital hardware IP library
Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.
Project F brings FPGAs to life with exciting open-source designs you can build on.
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
Verilog for a SECDED Hsaio ECC and a DEC ECC. Power, delay, and area are compared for Berkeley MASIC EEW241B - Advanced Digital Integrated Circuits.
Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2
⛔ DEPRECATED ⛔ Lean but mean RISC-V system!