32-Bit CPU based on the MIPS architecture designed for the computer architecture and design course (COEN 316).
- Simulations performed on ModelSim
- Synthesized using Xilinx Vivado
- Uploaded to the Digilent Nexys A7-100T FPGA for testing
Use the do files to simulate each individual component on ModelSim or the full CPU.
A 4-bit adaptation of the CPU and its components was created for the Nexys A7-100T.
Inputs and outputs were mapped to various switches, LEDs, and buttons using xdc files.
Block diagram of the CPU and its datapath