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A series of CORDIC related projects

C++ 107 25 Updated Nov 12, 2024

Python script that converts PyTorch pth and pt files to safetensors format

Python 23 Updated Apr 13, 2025

A Primer on Memory Consistency and Cache Coherence (Second Edition) 翻译计划

250 45 Updated May 5, 2024

Open Source Computer Vision Library

C++ 1 Updated Mar 19, 2019

32-bit Superscalar RISC-V CPU

Verilog 1,031 173 Updated Sep 18, 2021

GPL v3 2D/3D graphics engine in verilog

VHDL 666 146 Updated Aug 31, 2014

A Pi emulating a GameBoy sounds cheap. What about an FPGA?

Verilog 493 62 Updated Dec 10, 2022

Verilog Ethernet components for FPGA implementation

Verilog 2,586 763 Updated Feb 27, 2025

mor1kx - an OpenRISC 1000 processor IP core

Verilog 541 150 Updated Mar 29, 2025

Verilog Configurable Cache

Verilog 179 36 Updated Dec 2, 2024

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

Verilog 2,337 307 Updated May 23, 2025

Rocket Chip Generator

Scala 3,465 1,168 Updated May 27, 2025

Hardware-Platforms

7 5 Updated Jun 9, 2020

Light-weight RISC-V RV32IMC microcontroller core.

Verilog 104 30 Updated Mar 4, 2017

Chisel: A Modern Hardware Design Language

Scala 4,287 631 Updated Jun 7, 2025

The root repo for lowRISC project and FPGA demos.

SystemVerilog 601 149 Updated Aug 3, 2023

Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators

Verilog 667 110 Updated May 30, 2025

Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2

Verilog 2,723 1,036 Updated Mar 24, 2021

Rocket Chip Generator

Scala 1 Updated Jul 25, 2018

An open-source microcontroller system based on RISC-V

C 959 310 Updated Feb 6, 2024
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