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Bounti / riscv-dv
Forked from chipsalliance/riscv-dvRandom instruction generator for RISC-V processor verification
Simple JTAG Multiplexer, to allow controlling a device over JTAG from FPGA (2 PMOD connctors) or a standard JTAG debugger
A simple screen parsing tool towards pure vision based GUI agent
A snapshotting, coverage-guided fuzzer for software (UEFI, Kernel, firmware, BIOS) built on SIMICS
Fuzzing General-Purpose Hardware Designs with Software Fuzzers
ZSWatch - the Open Source Zephyr™ based Smartwatch, including both HW and FW.
Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
Qualcomm MSM8974 SoC emulation with Qiling
Advanced Fuzzing Library - Slot your Fuzzer together in Rust! Scales across cores and machines. For Windows, Android, MacOS, Linux, no_std, ...
The fuzzer afl++ is afl with community patches, qemu 5.1 upgrade, collision-free coverage, enhanced laf-intel & redqueen, AFLfast++ power schedules, MOpt mutators, unicorn_mode, and a lot more!
Hardware implementation of the SHA-256 cryptographic hash function
A LLVM-based static analysis framework.
AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream transmitter and receiver verification components
Documenting the Xilinx 7-series bit-stream format.
6 axis stepper motor robot and control software - Gen2
A 32-bit Microcontroller featuring a RISC-V core
Static Analyzer for LLVM bitcode based on Abstract Interpretation. **Update**: clam is still actively maintained. Please use branch dev14.
Static Value-Flow Analysis Framework for Source Code
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain accelerated by a PULP cluster with 8 cores.
Working Draft of the RISC-V Debug Specification Standard
an architecture-independent decompiler to LLVM IR