MIPS CPU

This is a MIPS CPU write with verilog HDL.

Name		Name	Last commit message	Last commit date
Latest commit History 27 Commits
.gitignore		.gitignore
MyMIPS.v		MyMIPS.v
MyMIPS_min_sopc.v		MyMIPS_min_sopc.v
MyMIPS_min_sopc_tb.v		MyMIPS_min_sopc_tb.v
README.md		README.md
ctrl.v		ctrl.v
defines.v		defines.v
div.v		div.v
ex.v		ex.v
ex_mem.v		ex_mem.v
hilo_reg.v		hilo_reg.v
id.v		id.v
id_ex.v		id_ex.v
if_id.v		if_id.v
inst_rom.v		inst_rom.v
mem.v		mem.v
mem_wb.v		mem_wb.v
pc_reg.v		pc_reg.v
regfile.v		regfile.v

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