Stars
An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V SoC，包含一个RV32I CPU、一个简单可扩展的总线、一些外设。
Machine Learning project using RISC-V and NVDLA on Linux
UltraMIPS SoC composed of dual-issue cpu, pipeline Cache and systematic peripheral.
An exquisite superscalar RV32GC processor.
RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.
Verilog AXI components for FPGA implementation
NVDLA (An Opensource DL Accelerator Framework) implementation on FPGA.
commit rtl and build cosim env
Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC Coding, Carry Select and Carry Look Ahead Adder, Carry Skip …
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2
分享FPGA开发知识、优秀文章、学习网站以及开源项目。本项目收集了github中许多FPGA开源项目。
Apache Doris is an easy-to-use, high performance and unified analytics database.
A Simple DNS System -- Coursework of Internet Applications