8000 Deepansh1992 (Deepansh Agrawal) · GitHub
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  1. TenGEthernetMac TenGEthernetMac Public

    A UVM based verification environment for 10gEthernetMac. The RTL is an open source Mac taken from the opencores.com

    Verilog 1

  2. 1X4-Ethernet-Switch- 1X4-Ethernet-Switch- Public

    The main aim of the project was to demonstrate the working of a 1x4 ethernet switch and verify its functionality. The methodology used for the Verification is "Constraint random coverage-driven ver…

    Verilog

  3. Timed-Electronic-safe- Timed-Electronic-safe- Public

    A model of an electronic safe that has a time limit in which user have to enter the password.The project is based on finite state machiens and beign programmed in Verilog using Quartus II 13.0 as t…

    Verilog

  4. labyrinth labyrinth Public

    The objective of the project is to create a labyrinth using pthread.

    C

0