An experienced hardware Engineer, Masters in Computer engineering from California State University Chico.
- San Jose, CA, United states
- www.linkedin.com/in/deepansh-agrawal
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TenGEthernetMac
TenGEthernetMac PublicA UVM based verification environment for 10gEthernetMac. The RTL is an open source Mac taken from the opencores.com
Verilog 1
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1X4-Ethernet-Switch-
1X4-Ethernet-Switch- PublicThe main aim of the project was to demonstrate the working of a 1x4 ethernet switch and verify its functionality. The methodology used for the Verification is "Constraint random coverage-driven ver…
Verilog
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Timed-Electronic-safe-
Timed-Electronic-safe- PublicA model of an electronic safe that has a time limit in which user have to enter the password.The project is based on finite state machiens and beign programmed in Verilog using Quartus II 13.0 as t…
Verilog
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