Stars
AMBA bus generator including AXI4, AXI3, AHB, and APB
《UVM实战》书本源代码和UVM 1.1d源码及Doc
All in one vscode plugin for HDL development
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
The best free and open-source automated time tracker. Cross-platform, extensible, privacy-focused.
Common SystemVerilog components
Must-have verilog systemverilog modules
A minimal GPU design in Verilog to learn how GPUs work from the ground up
Simplified HTTP client, A simplie golang HTTP client library.