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A SystemVerilog / verilog RTL implementation of linked list with a test bench (W.I.P)
A simulated memory controller for use in FPGA designs that want to model rea 8000 l system performance
Common SystemVerilog components
RTL code of some arbitration algorithm
An open-source static random access memory (SRAM) compiler.
GPGPU processor supporting RISCV-V extension, developed with Chisel HDL
An unofficial cuda assembler, for all generations of SASS, hopefully ：）
CudaPAD is a PTX/SASS viewer for NVIDIA Cuda kernels and provides an on-the-fly view of the assembly.
List of awesome open source hardware tools, generators, and reusable designs
GPGPU-Sim provides a detailed simulation model of contemporary NVIDIA GPUs running CUDA and/or OpenCL workloads. It includes support for features such as TensorCores and CUDA Dynamic Parallelism as…
An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.
Repo for all activity related to the ODSA Bunch of Wires Specification
Chisel artifacts developed under IBM's involvement with the DARPA PERFECT program
Lightweight re-packaging of AsyncQueue library from rocket-chip
Wavious DDR (WDDR) Physical interface (PHY) Hardware
Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro
An open-source microcontroller system based on RISC-V