Pinned Loading
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rtl_to_gds
rtl_to_gds PublicLearning RTL to GDSII flow using Mod-N conditional counter design
Verilog
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riscv32_proc
riscv32_proc Public32-bit, single cycle RISCV processor designed using RV32 ISA
Verilog
-
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SynthoSphere_Pradhyumna
SynthoSphere_Pradhyumna PublicReport of my activities done during SynthoSphere hackathon
Verilog 1
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Pyinterface_ir
Pyinterface_ir PublicA hobby project for changing ppt slides using an arduino and IR sensor
C++
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