GPP-PIM is a PIM architecture with weight update capabilities, supporting three modes: Generalized Ping-Pong, naive Ping-Pong, and in situ write/compute.
It possesses a set of customized instructions to facilitate the architecture in completing computational tasks.
Data such as execution time, macro utilization, off-chip bandwidth utilization, and on-chip memory usage will be monitored to test and compare the optimal parallel write/compute strategies.
GPP-PIM now supports comparisons in 12 different strategy usage environments.
| cores | 16 |
| number of macros in a core | 16 |
| array size | 32*32B |
| rewrite speed | 8B/cycle~1B/cycle |
'Instruction.md' This document defines the ISA utilized by GPP-PIM.
| off-chip bandwidth | result memory usage by a macro |
| 128 | 1*512B |
| 128 | 2*512B |
| 128 | 4*512B |
| 128 | 8*512B |
| 128 | 24*512B |
| 128 | 56*512B |
| off-chip bandwidth | result memory usage by a macro |
| 512 | 4*512B |
| 256 | 4*512B |
| 128 | 4*512B |
| 64 | 4*512B |
| 32 | 4*512B |
| 16 | 4*512B |
| 8 | 4*512B |
You can utilize the provided instruction code to conduct execution strategy tests for various usage scenarios. For detailed information, please refer to the 'GPP-PIM_usage_guide.md'.
Preparation:
- Python 3 environment: Employed for running the assembler program.
- ModelSim software: Utilized for simulating our Verilog files.
You can cite GPP-PIM using our related paper as: