Author: Soham Kapur
Description: Implementation of a generalized Parallel Multiplier using Carry Save Adder with SystemVerilog and Xilinx Vivado. Includes UVM-based testbench.
Tools Used: SystemVerilog, Xilinx Vivado
Concepts used: Parameterization, Universal Verification Mehtodology (UVM), Parallel Multiplier, Carry Save Adder
Multiplier Schematic: 4x4 multiplier
Adder Row Schematic: Individual instance of Intermediate Product module