Tags: TT432/chisel
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Fix ChiselStage and Builder handling of logging (backport chipsallian… …ce#3895) (chipsalliance#3898) * Fix ChiselStage and Builder handling of logging (chipsalliance#3895) Previously, object circt.stage.ChiselStage was ignoring the Logger. Also, Chisel was not creating its own logger scope which could lead to clobbering of the Console when running invoking Chisel in the same process multiple times. Fix various places we had to workaround this behavior and fix tests checking --log-level debug. (cherry picked from commit 88d147d) # Conflicts: # src/main/scala/circt/stage/ChiselStage.scala * Resolve backport conflicts * Make logger annotations unserializable Change logger annotations to mix-in the Unserializable trait so that they will not emitted by a stage. These annotations are not intended to be seen by CIRCT and these should be stripped from the output FIRRTL text. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com> --------- Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com> Co-authored-by: Jack Koenig <koenig@sifive.com> Co-authored-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
Add DataProduct for Iterables and primitive types (chipsalliance#3856)
Add Scala 2.13.13 to cross-build (chipsalliance#3851) (chipsalliance#… …3864) (cherry picked from commit 68eb248) Co-authored-by: Jack Koenig <koenig@sifive.com>
Preserve probe-ness and const-ness in Output() and friends. (chipsall… …iance#3654) Using `Output()` shouldn't drop important type information, only override the specified direction to force alignment. Until chipsalliance#3647 is addressed, use `cloneTypeFull` to get the expected behavior. The cloned direction information is unnecessary but is overridden by the coerced direction. cc chipsalliance#3647. Co-authored-by: Jack Koenig <koenig@sifive.com>
Clean up Bindings deprecations (chipsalliance#3736) * Make already deprecated APIs package private * Add deprecation warnings to a few that we missed
[cd] Bump CIRCT from firtool-1.60.0 to firtool-1.61.0 (chipsalliance#… …3681)
Add --dump-fir option to ChiselStage (backport chipsalliance#3453) (c… …hipsalliance#3456) * Add --dump-fir option to ChiselStage (chipsalliance#3453) This option will dump the .fir before invoking firtool. Additional changes: * Use os.lib for invoking firtool * Use lazy serialization to avoid holding the entire FIRRTL in memory. * Mix NoStackTrace into FirtoolNotFound * Fix detection of no firtool (cherry picked from commit 4db86b2) # Conflicts: # src/main/scala/circt/stage/CIRCTOptions.scala # src/main/scala/circt/stage/ChiselStage.scala # src/main/scala/circt/stage/phases/CIRCT.scala * Resolve backport conflicts --------- Co-authored-by: Jack Koenig <koenig@sifive.com>
Optimize BitPat equals, overlap, and cover (backport chipsalliance#3285… …) (chipsalliance#3288) * Optimize BitPat equals, overlap, and cover (chipsalliance#3285) (cherry picked from commit f590ac9) * Fix binary compatibility issue --------- Co-authored-by: Jack Koenig <koenig@sifive.com>
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