I am a M.S.E student in the Shenzhen Institute for Advanced Study at University of Electronic Science and Technology of China, supervised by Xili Han. I received my B.E degree from college of Electronic Engineering, South China Agricultural University. I used to intern at Guangdong Institute of Intelligence Science and Technology, GDIIST.
🌱 I’m currently learning Hardware Formal Verification.
👯 I'll be graduating in June 2025.
🔭 Expertise
- Verilog, SystemVerilog and UVM
- C++ and Python
- FPGA