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bender Public
Forked from pulp-platform/benderA dependency management tool for hardware projects.
Rust Apache License 2.0 UpdatedDec 9, 2021 -
axi Public
Forked from pulp-platform/axiAXI4 and AXI4-Lite interface definitions and testbench utilities
SystemVerilog Other UpdatedJan 25, 2021 -
common_cells Public
Forked from pulp-platform/common_cellsCommon SV components
SystemVerilog Other UpdatedJan 20, 2021 -
tech_cells_generic Public
Forked from pulp-platform/tech_cells_genericTechnology dependent cells instantiated in the design for generic process (simulation, FPGA)
SystemVerilog Other UpdatedApr 22, 2020 -
ariane Public
Forked from openhwgroup/cva6Ariane is a 6-stage RISC-V CPU capable of booting Linux
SystemVerilog Other UpdatedApr 17, 2020 -
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riscv-dbg Public
Forked from pulp-platform/riscv-dbgRISC-V Debug Support for our PULP Cores
SystemVerilog Other UpdatedFeb 11, 2020 -
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