RISCV-Pipelined-Processor

This is an implementation of a pipelined RISC-V CPU. It consists of 5 stages as:

Instruction Fetch (IF)
Instruction Decode (ID)
Execute (EX)
Memory Access (ME)
Write Back (WB)

Instructions for use: Simulation

Clone the repository using the following command:

git clone https://github.com/Warren-SJ/RISCV-Pipelined-Processor.git

Create a new project in your preferred FPGA development environment (e.g., Vivado, Quartus, etc.)
Add all the .sv files to the project
Set the top simulation module to RISCV_Processor_Top_Tb.sv
Run the simulation

To view the simulation waveform, it is recommended that you use gtkwave or any other waveform viewer. To use gtkwave on Windows, you must use the Windows Subsystem for Linux (WSL). Instructions can be found here.

Next, run the following command in the Linux terminal:

sudo apt-get install gtkwave

After installing gtkwave, run the following command to open the waveform:

cd /mnt/path_to_your_project_folder
gtkwave RISC_V_Processor_Top.vcd

Note: To change the instructions, change them in Instruction_Memory.sv. To obtain instructions, refer to this.

Instructions for use: FPGA Implementation

Clone the repository using the following command:

git clone https://github.com/Warren-SJ/RISCV-Pipelined-Processor.git

Create a new project in your preferred FPGA development environment (e.g., Vivado, Quartus, etc.)
Add all the .sv files to the project
Set the top module to RISCV_Processor_Top.sv
Run the synthesis and implementation process
Map the ports as required. This was implemented on a DE2-115 FPGA board and the port mappings are found in Pipelined.qsf. You may import this file into your Quartus project to use the same port mappings.
Program the FPGA

Notes:

The clock is mapped to KEY0, and reset is mapped to KEY3. The clock is mapped to a button so that the results can be observed on the 7-segment display.
To reset, press KEY3 and while pressing it, press KEY0.
The 7-segment display will show the output of the ALU operation or the value being written to register. This may be changed by using SW17.

Improvements:

The processor is not fully pipelined. The processor is stalled when a branch instruction is executed. This can be improved by implementing branch prediction.
Hazard detection is not implemented. This can be improved by implementing forwarding and stalling.

The initial design which was a single cycle design can be found here.

Name		Name	Last commit message	Last commit date
Latest commit History 16 Commits
ALU_32bit.sv		ALU_32bit.sv
Adder_32bit.sv		Adder_32bit.sv
Branch_Comparator.sv		Branch_Comparator.sv
Control_Unit.sv		Control_Unit.sv
Data_Memory.sv		Data_Memory.sv
EX_MW.sv		EX_MW.sv
ID_EX.sv		ID_EX.sv
IF_ID.sv		IF_ID.sv
Immediate_Generator.sv		Immediate_Generator.sv
Immediate_Limiter.sv		Immediate_Limiter.sv
Instruction_Memory.sv		Instruction_Memory.sv
Instruction_Parser.sv		Instruction_Parser.sv
LICENSE		LICENSE
Load_Generator.sv		Load_Generator.sv
MW_WB.sv		MW_WB.sv
PC.sv		PC.sv
Pipelined.qsf		Pipelined.qsf
README.md		README.md
RISC_V_Processor_Top.sv		RISC_V_Processor_Top.sv
RISC_V_Processor_Top_Tb.sv		RISC_V_Processor_Top_Tb.sv
Register_File.sv		Register_File.sv
Simulation.png		Simulation.png
Three_One_Mux.sv		Three_One_Mux.sv
Two_One_Mux.sv		Two_One_Mux.sv
hex_decoder.v		hex_decoder.v
memory.hex		memory.hex

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RISCV-Pipelined-Processor

Instructions for use: Simulation

Instructions for use: FPGA Implementation

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RISCV-Pipelined-Processor

Instructions for use: Simulation

Instructions for use: FPGA Implementation

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