Verilog_Module

收集一些常用的Verilog模块代码，方便调用

Name		Name	Last commit message	Last commit date
Latest commit History 40 Commits
AHB2BRAM		AHB2BRAM
AHB_GPIO		AHB_GPIO
AHB_UART		AHB_UART
AXI_DMA_RD_1.0		AXI_DMA_RD_1.0
AXI_DMA_WR_1.0		AXI_DMA_WR_1.0
AXI_lite_test_hdl		AXI_lite_test_hdl
BMP_FAT		BMP_FAT
BRAM		BRAM
DE1_SOC_SEG_HEX		DE1_SOC_SEG_HEX
Edge_Detect		Edge_Detect
Fudan_uart		Fudan_uart
Key_Module		Key_Module
RGB_Gary_Binary		RGB_Gary_Binary
SEG_display		SEG_display
UART_Module		UART_Module
aq_axi_master		aq_axi_master
async_fifo-master		async_fifo-master
axi_full_sim		axi_full_sim
fifo		fifo
hdmi_tx_1.0		hdmi_tx_1.0
i2c_master		i2c_master
pwm		pwm
pwm_motor		pwm_motor
ram_2p		ram_2p
sdram_core		sdram_core
uart_module		uart_module
wave_data		wave_data
white_balance		white_balance
.gitattributes		.gitattributes
.gitignore		.gitignore
README.md		README.md
vivado-library-master.zip		vivado-library-master.zip

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