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This is really a reopening of #59. I'm actually proposing a solution and requesting comments.
The problem I'm out to solve is to provide some way of doing:
always (@negedge clk) begin
// ...
end
The previous proposed solution involved creating a new clock domain, which ends up changing the module's interface IIUC.
What I'd like to propose is to provide it as an alternative by creating another sensitivity list, along with comb and sync. For example, we can call it negsync.
I'm looking over the code and do not believe this would be difficult to support.
I'm interested in what others think.
The text was updated successfully, but these errors were encountered:
This is really a reopening of #59. I'm actually proposing a solution and requesting comments.
The problem I'm out to solve is to provide some way of doing:
The previous proposed solution involved creating a new clock domain, which ends up changing the module's interface IIUC.
What I'd like to propose is to provide it as an alternative by creating another sensitivity list, along with
comb
andsync
. For example, we can call itnegsync
.I'm looking over the code and do not believe this would be difficult to support.
I'm interested in what others think.
The text was updated successfully, but these errors were encountered: