8000 sensitivity list and negative clock edge · Issue #59 · m-labs/migen · GitHub

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sensitivity list and negative clock edge #59

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raspberrypisig opened this issue Nov 27, 2016 · 2 comments

raspberrypisig commented

NOOB QUESTION.

Is there a way to spit the following verilog

always @ ( negedge clk) ....

Or a more complicated sensitivity list?

Member

sbourdeauducq commented

No. But you can use a PLL or some clock buffers to invert the clock.

sbourdeauducq closed this as completed

Member

jordens commented

Or just self.cd_sys_falling.clk.eq(~ClockSignal("sys"))

shantzis62 mentioned this issue

Support for negedge sensitivity list #304

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