8000 Asynchronous reset with and ResetSignal(in vhdl) · Issue #440 · myhdl/myhdl · GitHub

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Asynchronous reset with and ResetSignal(in vhdl) #440

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0TulipRose0 opened this issue Aug 8, 2024 · 1 comment

0TulipRose0 commented

When transferring the module to vhdl, it turns out that if you specify reset in the sensitivity list when using always_seq, then it simply cleans it up and leaves only clk
He also does not understand how to correctly transfer the ResetSignal construction, since he understands both the initial value and the active one as the same thing, which is why the condition loops simply

0TulipRose0 added the enhancement label

josyb removed the enhancement label

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josyb commented

Please add a MRE ((minimal reproducible example)

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