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115 Open 96 Closed
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Issues list

multi-dimensional signals? enhancement
#455 opened Apr 12, 2025 by brightening-eyes
1
Shadow Signal doesn't generate correct Verilog bug
#453 opened Mar 31, 2025 by cychotic
4
Please switch from setup-ghdl-ci to setup-ghdl other
#449 opened Jan 12, 2025 by Paebbels
7
Conversion problem between Python and Verilog enhancement wontfix
#448 opened Dec 30, 2024 by PeterInTheEarth
1
Asynchronous reset with and ResetSignal(in vhdl)
#440 opened Aug 8, 2024 by 0TulipRose0
1
Inconsistent behavior of assignment of Signal(intbv()[w:]) to Signal(bool()) help wanted
#434 opened Jun 21, 2024 by josyb
@JanCoombs @davekeeshan
2
Bit indexing may cause deprecation warnings
#429 opened Feb 17, 2024 by zhijieshi
9
different python versions question
#414 opened Apr 4, 2023 by olisnr
14
8000
verify_convert() doesn't appear to work as expected bug
#409 opened Feb 3, 2023 by davekeeshan
3
Python3.7 Deprecation list bug
#406 opened Feb 3, 2023 by davekeeshan
1 task
11
Review Tests Investigate all marked xfail
#397 opened Dec 16, 2022 by davekeeshan
Migrate PyPi release to github actions enhancement
#393 opened Dec 10, 2022 by davekeeshan
2 of 4 tasks
6
Support for switch in MyHDL enhancement
#386 opened Dec 5, 2022 by davekeeshan
4
Dynamic Variable assignment bug conversion
#385 opened Nov 30, 2022 by davekeeshan
9
User Defined code not working (verilog_code/vhdl_code) enhancement
#384 opened Nov 30, 2022 by davekeeshan
9
how to properly create a (synthesized) parity checker function question
#378 opened Sep 2, 2022 by rafaelcorsi
1
AttributeError: 'Name' object has no attribute 'value'
#373 opened Jul 1, 2022 by Grissess
9
Incorrect translation in comparation bug
#372 opened Jun 19, 2022 by Pusiol
3
shift_left conversion issue in vhdl bug
#367 opened Apr 13, 2022 by davekeeshan
46
ConcatSignal misbehavior converting to hdl
#364 opened Mar 29, 2022 by rafaelcorsi
2
Could you help to check if here is non-blocking or blocking? question
#361 opened Jun 26, 2021 by TarzanPan
1
Modelsim vlog vcom and vsim clarification
#360 opened Mar 31, 2021 by dmitrii-galantsev
One-hot state machine conversion to Verilog bug
#356 opened Feb 19, 2021 by kc64
conda-forge package documentation
#354 opened Jan 10, 2021 by davidbrochart
@cfelton
1
Verilog Conversion could handle tuples of quantities convertible to ints bug
#349 opened Dec 2, 2020 by venks1
8
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